From 00693707da4b0139a0537874ade3707c9bf3e465 Mon Sep 17 00:00:00 2001
From: Jamie Iles <jamie@jamieiles.com>
Date: Mon, 14 Mar 2011 17:38:30 +0000
Subject: [PATCH] --- yaml --- r: 281793 b: refs/heads/master c:
 0116da4fcc1ae8a80d9002441e98768f2a6fa2fe h: refs/heads/master i:   281791:
 44052fb2f678a18190dab45c5cf8c944e2ad7d02 v: v3

---
 [refs]                                    |  2 +-
 trunk/drivers/net/ethernet/cadence/macb.c | 17 +++++++++++++++++
 trunk/drivers/net/ethernet/cadence/macb.h |  5 +++++
 3 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index c5d135c4ec16..78f45c2cf6e2 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 757a03c6e004fbbdef872cb7ecdc940a891b8e6e
+refs/heads/master: 0116da4fcc1ae8a80d9002441e98768f2a6fa2fe
diff --git a/trunk/drivers/net/ethernet/cadence/macb.c b/trunk/drivers/net/ethernet/cadence/macb.c
index 38f1932013d1..64d61461bdc7 100644
--- a/trunk/drivers/net/ethernet/cadence/macb.c
+++ b/trunk/drivers/net/ethernet/cadence/macb.c
@@ -856,6 +856,21 @@ static u32 macb_dbw(struct macb *bp)
 	}
 }
 
+/*
+ * Configure the receive DMA engine to use the correct receive buffer size.
+ * This is a configurable parameter for GEM.
+ */
+static void macb_configure_dma(struct macb *bp)
+{
+	u32 dmacfg;
+
+	if (macb_is_gem(bp)) {
+		dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
+		dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64);
+		gem_writel(bp, DMACFG, dmacfg);
+	}
+}
+
 static void macb_init_hw(struct macb *bp)
 {
 	u32 config;
@@ -874,6 +889,8 @@ static void macb_init_hw(struct macb *bp)
 	config |= macb_dbw(bp);
 	macb_writel(bp, NCFGR, config);
 
+	macb_configure_dma(bp);
+
 	/* Initialize TX and RX buffers */
 	macb_writel(bp, RBQP, bp->rx_ring_dma);
 	macb_writel(bp, TBQP, bp->tx_ring_dma);
diff --git a/trunk/drivers/net/ethernet/cadence/macb.h b/trunk/drivers/net/ethernet/cadence/macb.h
index 71424aae9c50..193107884a5a 100644
--- a/trunk/drivers/net/ethernet/cadence/macb.h
+++ b/trunk/drivers/net/ethernet/cadence/macb.h
@@ -64,6 +64,7 @@
 /* GEM register offsets. */
 #define GEM_NCFGR				0x0004
 #define GEM_USRIO				0x000c
+#define GEM_DMACFG				0x0010
 #define GEM_HRB					0x0080
 #define GEM_HRT					0x0084
 #define GEM_SA1B				0x0088
@@ -154,6 +155,10 @@
 #define GEM_DBW64				1
 #define GEM_DBW128				2
 
+/* Bitfields in DMACFG. */
+#define GEM_RXBS_OFFSET				16
+#define GEM_RXBS_SIZE				8
+
 /* Bitfields in NSR */
 #define MACB_NSR_LINK_OFFSET			0
 #define MACB_NSR_LINK_SIZE			1