From 013fe02af3b208522284ad9b3961f1cfdb62dcea Mon Sep 17 00:00:00 2001 From: Jeff Garzik Date: Tue, 7 Apr 2009 19:18:32 -0400 Subject: [PATCH] --- yaml --- r: 158501 b: refs/heads/master c: 2fc37adba0fb05760b8635c6706773af828ccf3c h: refs/heads/master i: 158499: 0b8b23e30434e529d46faf9f6993b5def13dbbc0 v: v3 --- [refs] | 2 +- trunk/drivers/ata/sata_sil.c | 13 +++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index d96d23ba4b7e..36066eedc33b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 54c38444fad6a99b4b19512f8f0055d69115e69e +refs/heads/master: 2fc37adba0fb05760b8635c6706773af828ccf3c diff --git a/trunk/drivers/ata/sata_sil.c b/trunk/drivers/ata/sata_sil.c index 35bd5cc7f285..3cb69d5fb817 100644 --- a/trunk/drivers/ata/sata_sil.c +++ b/trunk/drivers/ata/sata_sil.c @@ -565,6 +565,19 @@ static void sil_freeze(struct ata_port *ap) tmp |= SIL_MASK_IDE0_INT << ap->port_no; writel(tmp, mmio_base + SIL_SYSCFG); readl(mmio_base + SIL_SYSCFG); /* flush */ + + /* Ensure DMA_ENABLE is off. + * + * This is because the controller will not give us access to the + * taskfile registers while a DMA is in progress + */ + iowrite8(ioread8(ap->ioaddr.bmdma_addr) & ~SIL_DMA_ENABLE, + ap->ioaddr.bmdma_addr); + + /* According to ata_bmdma_stop, an HDMA transition requires + * on PIO cycle. But we can't read a taskfile register. + */ + ioread8(ap->ioaddr.bmdma_addr); } static void sil_thaw(struct ata_port *ap)