From 01a4290e6e65e6cf2c3442a5c5e96178e2edf4d4 Mon Sep 17 00:00:00 2001 From: Jesper Nilsson Date: Wed, 4 Aug 2010 10:49:17 +0200 Subject: [PATCH] --- yaml --- r: 207148 b: refs/heads/master c: 6f09963caf5ff7cb4b8de600caee3ff016e97139 h: refs/heads/master v: v3 --- [refs] | 2 +- .../cris/include/arch-v32/mach-a3/mach/dma.h | 27 +++++++++++++++++++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index bdec400f15f4..33a3a6d463a5 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: da2af0a771caa8f8cff9c7bfc979f0510eb0faea +refs/heads/master: 6f09963caf5ff7cb4b8de600caee3ff016e97139 diff --git a/trunk/arch/cris/include/arch-v32/mach-a3/mach/dma.h b/trunk/arch/cris/include/arch-v32/mach-a3/mach/dma.h index 9e8eb13b601d..f01dca1ad108 100644 --- a/trunk/arch/cris/include/arch-v32/mach-a3/mach/dma.h +++ b/trunk/arch/cris/include/arch-v32/mach-a3/mach/dma.h @@ -5,6 +5,33 @@ #define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */ +#define NETWORK_ETH_TX_DMA_NBR 0 /* Ethernet 0 out. */ +#define NETWORK_ETH_RX_DMA_NBR 1 /* Ethernet 0 in. */ + +#define IO_PROC_DMA_TX_DMA_NBR 4 /* IO processor DMA0 out. */ +#define IO_PROC_DMA_RX_DMA_NBR 5 /* IO processor DMA0 in. */ + +#define ASYNC_SER3_TX_DMA_NBR 2 /* Asynchronous serial port 3 out. */ +#define ASYNC_SER3_RX_DMA_NBR 3 /* Asynchronous serial port 3 in. */ + +#define ASYNC_SER2_TX_DMA_NBR 6 /* Asynchronous serial port 2 out. */ +#define ASYNC_SER2_RX_DMA_NBR 7 /* Asynchronous serial port 2 in. */ + +#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */ +#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */ + +#define SYNC_SER_TX_DMA_NBR 6 /* Synchronous serial port 0 out. */ +#define SYNC_SER_RX_DMA_NBR 7 /* Synchronous serial port 0 in. */ + +#define ASYNC_SER0_TX_DMA_NBR 0 /* Asynchronous serial port 0 out. */ +#define ASYNC_SER0_RX_DMA_NBR 1 /* Asynchronous serial port 0 in. */ + +#define STRCOP_TX_DMA_NBR 2 /* Stream co-processor out. */ +#define STRCOP_RX_DMA_NBR 3 /* Stream co-processor in. */ + +#define dma_eth0 dma_eth +#define dma_eth1 dma_eth + enum dma_owner { dma_eth, dma_ser0,