From 01f553f41d3124d2ab1bcaa9569d3f9f77735f17 Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Sat, 22 Sep 2012 13:13:38 -0700 Subject: [PATCH] --- yaml --- r: 331326 b: refs/heads/master c: 0b177ab53d0a2303ba287ec8babfd6e1de801500 h: refs/heads/master v: v3 --- [refs] | 2 +- .../arm/Samsung-S3C24XX/GPIO.txt | 82 +- trunk/Documentation/arm/Samsung/GPIO.txt | 8 +- trunk/Documentation/arm/memory.txt | 3 + .../devicetree/bindings/arm/bcm2835.txt | 8 + .../devicetree/bindings/arm/mrvl/tauros2.txt | 17 + .../devicetree/bindings/arm/msm/timer.txt | 38 + .../devicetree/bindings/arm/omap/omap.txt | 3 + .../devicetree/bindings/arm/pmu.txt | 4 + .../devicetree/bindings/clock/imx23-clock.txt | 76 + .../devicetree/bindings/clock/imx28-clock.txt | 99 + .../devicetree/bindings/clock/imx6q-clock.txt | 222 ++ .../devicetree/bindings/gpio/gpio-samsung.txt | 43 + .../devicetree/bindings/gpio/gpio-twl4030.txt | 6 + .../bindings/i2c/trivial-devices.txt | 1 + .../brcm,bcm2835-armctrl-ic.txt | 110 + .../bindings/lpddr2/lpddr2-timings.txt | 52 + .../devicetree/bindings/lpddr2/lpddr2.txt | 102 + .../bindings/memory-controllers/ti/emif.txt | 55 + .../devicetree/bindings/mtd/pxa3xx-nand.txt | 31 + .../bindings/regulator/tps6586x.txt | 65 +- .../devicetree/bindings/rtc/pxa-rtc.txt | 14 + .../timer/brcm,bcm2835-system-timer.txt | 22 + .../devicetree/bindings/vendor-prefixes.txt | 1 + trunk/MAINTAINERS | 11 +- trunk/arch/arm/Kconfig | 231 +- trunk/arch/arm/Kconfig.debug | 33 + trunk/arch/arm/Makefile | 150 +- trunk/arch/arm/boot/Makefile | 2 + trunk/arch/arm/boot/compressed/misc.c | 6 + trunk/arch/arm/boot/dts/Makefile | 100 + trunk/arch/arm/boot/dts/am335x-bone.dts | 60 + trunk/arch/arm/boot/dts/am335x-evm.dts | 100 + trunk/arch/arm/boot/dts/am33xx.dtsi | 71 +- trunk/arch/arm/boot/dts/bcm2835-rpi-b.dts | 12 + trunk/arch/arm/boot/dts/bcm2835.dtsi | 39 + trunk/arch/arm/boot/dts/ea3250.dts | 109 +- .../arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 67 + trunk/arch/arm/boot/dts/imx23-evk.dts | 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640 ++++ trunk/arch/arm/boot/dts/pxa27x.dtsi | 14 + trunk/arch/arm/boot/dts/pxa2xx.dtsi | 132 + trunk/arch/arm/boot/dts/pxa3xx.dtsi | 32 + trunk/arch/arm/boot/dts/pxa910.dtsi | 5 + trunk/arch/arm/boot/dts/tegra20-harmony.dts | 220 ++ .../arch/arm/boot/dts/tegra20-medcom-wide.dts | 58 + trunk/arch/arm/boot/dts/tegra20-paz00.dts | 173 ++ trunk/arch/arm/boot/dts/tegra20-plutux.dts | 50 + trunk/arch/arm/boot/dts/tegra20-seaboard.dts | 186 ++ trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi | 449 +++ trunk/arch/arm/boot/dts/tegra20-tec.dts | 53 + trunk/arch/arm/boot/dts/tegra20-ventana.dts | 206 ++ trunk/arch/arm/boot/dts/tegra20-whistler.dts | 295 ++ trunk/arch/arm/boot/dts/tegra20.dtsi | 2 +- .../arch/arm/boot/dts/tegra30-cardhu-a02.dts | 87 + .../arch/arm/boot/dts/tegra30-cardhu-a04.dts | 98 + trunk/arch/arm/boot/dts/tegra30-cardhu.dts | 171 -- trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi | 475 +++ trunk/arch/arm/boot/dts/tegra30.dtsi | 2 +- trunk/arch/arm/boot/dts/tps65217.dtsi | 56 + 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.../arm/mach-bcmring/include/csp/intcHw.h | 40 - .../arm/mach-bcmring/include/csp/module.h | 32 - .../arch/arm/mach-bcmring/include/csp/secHw.h | 65 - .../arm/mach-bcmring/include/csp/stdint.h | 30 - .../arm/mach-bcmring/include/csp/string.h | 34 - .../cfg_global.h} | 11 + .../include/mach/csp/cap_inline.h | 2 +- .../include/mach/csp/chipcHw_def.h | 6 +- .../include/mach/csp/chipcHw_inline.h | 119 +- .../include/mach/csp/chipcHw_reg.h | 6 +- .../mach-bcmring/include/mach/csp/ddrcReg.h | 6 +- .../include/{ => mach}/csp/dmacHw.h | 4 +- .../include/mach/csp/dmacHw_priv.h | 2 +- .../include/mach/csp/dmacHw_reg.h | 106 +- .../mach-bcmring/include/mach/csp/hw_cfg.h | 2 +- .../include/mach/csp/intcHw_reg.h | 18 +- .../mach-bcmring/include/mach/csp/mm_addr.h | 2 +- .../arm/mach-bcmring/include/mach/csp/mm_io.h | 8 +- .../mach-bcmring/include/{ => mach}/csp/reg.h | 25 +- .../include/mach/csp/secHw_inline.h | 10 +- .../include/{ => mach}/csp/tmrHw.h | 2 +- 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trunk/arch/arm/mach-highbank/pm.c | 4 +- trunk/arch/arm/mach-imx/Kconfig | 106 +- trunk/arch/arm/mach-imx/Makefile | 11 +- trunk/arch/arm/mach-imx/Makefile.boot | 7 - trunk/arch/arm/mach-imx/clk-imx21.c | 1 - trunk/arch/arm/mach-imx/clk-imx35.c | 11 +- trunk/arch/arm/mach-imx/clk-imx51-imx53.c | 18 +- trunk/arch/arm/mach-imx/clk-imx6q.c | 51 +- trunk/arch/arm/mach-imx/clk-pllv1.c | 49 +- trunk/arch/arm/mach-imx/clk.c | 3 + trunk/arch/arm/mach-imx/clk.h | 3 +- trunk/arch/arm/mach-imx/devices-imx53.h | 48 - trunk/arch/arm/mach-imx/efika.h | 10 - trunk/arch/arm/mach-imx/hotplug.c | 16 +- trunk/arch/arm/mach-imx/imx51-dt.c | 21 - .../arm/mach-imx/{imx53-dt.c => mach-imx53.c} | 27 - trunk/arch/arm/mach-imx/mach-imx6q.c | 12 +- trunk/arch/arm/mach-imx/mach-kzm_arm11_01.c | 5 +- trunk/arch/arm/mach-imx/mach-mx31ads.c | 2 +- trunk/arch/arm/mach-imx/mach-mx31lite.c | 2 +- trunk/arch/arm/mach-imx/mach-mx51_efikamx.c | 300 -- trunk/arch/arm/mach-imx/mach-mx51_efikasb.c | 296 -- trunk/arch/arm/mach-imx/mach-mx53_ard.c | 272 -- trunk/arch/arm/mach-imx/mach-mx53_evk.c | 179 -- trunk/arch/arm/mach-imx/mach-mx53_loco.c | 321 -- trunk/arch/arm/mach-imx/mach-mx53_smd.c | 168 -- trunk/arch/arm/mach-imx/mm-imx5.c | 47 - trunk/arch/arm/mach-imx/mx51_efika.c | 633 ---- trunk/arch/arm/mach-imx/platsmp.c | 18 +- trunk/arch/arm/mach-integrator/core.c | 4 +- trunk/arch/arm/mach-integrator/cpu.c | 8 +- .../arm/mach-integrator/include/mach/io.h | 33 - .../mach-integrator/include/mach/platform.h | 4 + .../arch/arm/mach-integrator/integrator_ap.c | 21 +- .../arch/arm/mach-integrator/integrator_cp.c | 6 +- trunk/arch/arm/mach-integrator/pci_v3.c | 62 +- trunk/arch/arm/mach-iop13xx/include/mach/io.h | 28 - .../arm/mach-iop13xx/include/mach/iop13xx.h | 48 +- .../arm/mach-iop13xx/include/mach/memory.h | 14 +- trunk/arch/arm/mach-iop13xx/io.c | 35 +- trunk/arch/arm/mach-iop13xx/pci.c | 53 +- trunk/arch/arm/mach-iop13xx/pci.h | 4 +- trunk/arch/arm/mach-iop13xx/setup.c | 20 +- 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trunk/arch/arm/mach-lpc32xx/Makefile.boot | 2 - trunk/arch/arm/mach-lpc32xx/common.c | 8 +- .../arm/mach-lpc32xx/include/mach/hardware.h | 2 +- trunk/arch/arm/mach-lpc32xx/irq.c | 7 +- trunk/arch/arm/mach-lpc32xx/phy3250.c | 20 +- trunk/arch/arm/mach-mmp/Kconfig | 3 + trunk/arch/arm/mach-mmp/Makefile | 8 +- trunk/arch/arm/mach-mmp/clock-mmp2.c | 111 + trunk/arch/arm/mach-mmp/clock-pxa168.c | 91 + trunk/arch/arm/mach-mmp/clock-pxa910.c | 67 + trunk/arch/arm/mach-mmp/common.h | 3 + .../arm/mach-mmp/include/mach/regs-apbc.h | 95 - .../arm/mach-mmp/include/mach/regs-apmu.h | 15 - trunk/arch/arm/mach-mmp/irq.c | 4 +- trunk/arch/arm/mach-mmp/mmp2.c | 73 +- trunk/arch/arm/mach-mmp/pxa168.c | 58 +- trunk/arch/arm/mach-mmp/pxa910.c | 44 +- trunk/arch/arm/mach-msm/Kconfig | 41 +- trunk/arch/arm/mach-msm/Makefile | 8 +- trunk/arch/arm/mach-msm/acpuclock-arm11.c | 525 ---- trunk/arch/arm/mach-msm/acpuclock.h | 32 - trunk/arch/arm/mach-msm/board-dt-8660.c | 65 + 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| 90 - trunk/arch/arm/plat-omap/omap_device.c | 194 +- trunk/arch/arm/plat-orion/gpio.c | 2 +- .../include/plat/{gpio.h => orion-gpio.h} | 2 +- trunk/arch/arm/plat-orion/irq.c | 2 +- trunk/arch/arm/plat-orion/mpp.c | 1 + trunk/arch/arm/plat-samsung/devs.c | 3 +- .../arm/plat-samsung/include/plat/gpio-fns.h | 97 - trunk/arch/arm/plat-samsung/s5p-irq-gpioint.c | 4 +- trunk/arch/arm/plat-spear/include/plat/gpio.h | 1 - trunk/arch/arm/plat-versatile/Makefile | 2 + .../arm/plat-versatile/include/plat/platsmp.h | 14 + trunk/arch/arm/plat-versatile/platsmp.c | 10 +- trunk/arch/arm/tools/mach-types | 1 - trunk/drivers/Kconfig | 2 + trunk/drivers/Makefile | 2 + trunk/drivers/char/hw_random/omap-rng.c | 121 +- trunk/drivers/clk/Kconfig | 13 + trunk/drivers/clk/Makefile | 10 +- trunk/drivers/clk/clk-bcm2835.c | 59 + trunk/drivers/clk/clk-ls1x.c | 111 + trunk/drivers/clk/clk-max77686.c | 244 ++ trunk/drivers/clk/clk-prima2.c | 1171 ++++++++ trunk/drivers/clk/clk.c | 57 +- trunk/drivers/clk/mmp/Makefile | 9 + trunk/drivers/clk/mmp/clk-apbc.c | 152 + trunk/drivers/clk/mmp/clk-apmu.c | 97 + trunk/drivers/clk/mmp/clk-frac.c | 153 + trunk/drivers/clk/mmp/clk-mmp2.c | 449 +++ trunk/drivers/clk/mmp/clk-pxa168.c | 346 +++ trunk/drivers/clk/mmp/clk-pxa910.c | 320 ++ trunk/drivers/clk/mmp/clk.h | 35 + trunk/drivers/clk/mxs/clk-imx23.c | 55 +- trunk/drivers/clk/mxs/clk-imx28.c | 113 +- trunk/drivers/clk/ux500/Makefile | 12 + trunk/drivers/clk/ux500/clk-prcc.c | 164 ++ trunk/drivers/clk/ux500/clk-prcmu.c | 252 ++ trunk/drivers/clk/ux500/clk.h | 48 + trunk/drivers/clk/ux500/u8500_clk.c | 477 +++ trunk/drivers/clk/ux500/u8540_clk.c | 21 + trunk/drivers/clk/ux500/u9540_clk.c | 21 + trunk/drivers/clk/versatile/Makefile | 1 + trunk/drivers/clk/versatile/clk-realview.c | 114 + trunk/drivers/clocksource/Makefile | 1 + trunk/drivers/clocksource/bcm2835_timer.c | 161 + trunk/drivers/gpio/gpio-pxa.c | 77 +- trunk/drivers/gpio/gpio-samsung.c | 103 +- trunk/drivers/gpio/gpio-tegra.c | 3 - trunk/drivers/gpio/gpio-twl4030.c | 77 +- trunk/drivers/i2c/busses/Kconfig | 2 +- trunk/drivers/i2c/busses/i2c-iop3xx.c | 121 +- trunk/drivers/input/keyboard/omap-keypad.c | 2 +- trunk/drivers/input/mouse/rpcmouse.c | 2 +- trunk/drivers/input/serio/ams_delta_serio.c | 2 +- trunk/drivers/irqchip/Kconfig | 0 trunk/drivers/irqchip/Makefile | 1 + trunk/drivers/irqchip/irq-bcm2835.c | 223 ++ trunk/drivers/mfd/db8500-prcmu.c | 42 + trunk/drivers/mfd/dbx500-prcmu-regs.h | 4 +- trunk/drivers/mfd/tps6586x.c | 13 + trunk/drivers/mmc/host/omap.c | 1 - trunk/drivers/mmc/host/sdhci-tegra.c | 1 - trunk/drivers/mtd/nand/ams-delta.c | 2 +- trunk/drivers/mtd/nand/bcm_umi_nand.c | 12 +- trunk/drivers/mtd/nand/nand_bcm_umi.h | 73 +- trunk/drivers/mtd/nand/omap2.c | 2 +- trunk/drivers/mtd/nand/pxa3xx_nand.c | 87 +- trunk/drivers/mtd/onenand/omap2.c | 2 +- trunk/drivers/net/ethernet/seeq/ether3.c | 4 +- trunk/drivers/net/irda/pxaficp_ir.c | 28 +- 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trunk/drivers/usb/host/ohci-hcd.c | 2 +- trunk/drivers/usb/host/ohci-nxp.c | 84 +- trunk/drivers/usb/host/ohci-omap.c | 2 +- trunk/drivers/usb/musb/tusb6010_omap.c | 1 - trunk/drivers/usb/otg/isp1301_omap.c | 2 +- trunk/drivers/video/backlight/omap1_bl.c | 2 +- trunk/drivers/video/da8xx-fb.c | 8 +- trunk/drivers/video/omap/lcd_ams_delta.c | 3 +- trunk/drivers/video/omap/lcd_mipid.c | 2 +- trunk/drivers/video/omap/lcd_osk.c | 2 +- trunk/drivers/watchdog/Kconfig | 6 +- trunk/drivers/watchdog/ks8695_wdt.c | 14 +- .../linux/bcm2835_timer.h} | 13 +- trunk/include/linux/clk-provider.h | 6 + .../param.h => include/linux/clk/bcm2835.h} | 11 +- .../io.h => include/linux/irqchip/bcm2835.h} | 16 +- trunk/include/linux/mfd/dbx500-prcmu.h | 1 + trunk/include/linux/mfd/tps6586x.h | 1 + .../linux/platform_data/asoc-ti-mcbsp.h} | 0 .../linux/platform_data/clk-realview.h | 1 + trunk/include/linux/platform_data/clk-ux500.h | 17 + .../linux/platform_data/dsp-omap.h} | 0 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trunk/sound/soc/tegra/tegra_pcm.c | 232 -- trunk/sound/soc/tegra/tegra_pcm.h | 14 - 955 files changed, 23329 insertions(+), 32393 deletions(-) create mode 100644 trunk/Documentation/devicetree/bindings/arm/bcm2835.txt create mode 100644 trunk/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt create mode 100644 trunk/Documentation/devicetree/bindings/arm/msm/timer.txt create mode 100644 trunk/Documentation/devicetree/bindings/clock/imx23-clock.txt create mode 100644 trunk/Documentation/devicetree/bindings/clock/imx28-clock.txt create mode 100644 trunk/Documentation/devicetree/bindings/clock/imx6q-clock.txt create mode 100644 trunk/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt create mode 100644 trunk/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt create mode 100644 trunk/Documentation/devicetree/bindings/lpddr2/lpddr2.txt create mode 100644 trunk/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt create mode 100644 trunk/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt create mode 100644 trunk/Documentation/devicetree/bindings/rtc/pxa-rtc.txt create mode 100644 trunk/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt create mode 100644 trunk/arch/arm/boot/dts/Makefile create mode 100644 trunk/arch/arm/boot/dts/bcm2835-rpi-b.dts create mode 100644 trunk/arch/arm/boot/dts/bcm2835.dtsi create mode 100644 trunk/arch/arm/boot/dts/elpida_ecb240abacn.dtsi create mode 100644 trunk/arch/arm/boot/dts/imx28-cfa10049.dts create mode 100644 trunk/arch/arm/boot/dts/msm8960-cdp.dts create mode 100644 trunk/arch/arm/boot/dts/omap2420.dtsi create mode 100644 trunk/arch/arm/boot/dts/omap2430.dtsi rename trunk/arch/arm/boot/dts/{omap3-beagle.dts => omap3-beagle-xm.dts} (52%) create mode 100644 trunk/arch/arm/boot/dts/omap3-overo.dtsi create mode 100644 trunk/arch/arm/boot/dts/omap3-tobi.dts create mode 100644 trunk/arch/arm/boot/dts/omap36xx.dtsi delete mode 100644 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trunk/drivers/clk/mmp/clk-pxa910.c create mode 100644 trunk/drivers/clk/mmp/clk.h create mode 100644 trunk/drivers/clk/ux500/Makefile create mode 100644 trunk/drivers/clk/ux500/clk-prcc.c create mode 100644 trunk/drivers/clk/ux500/clk-prcmu.c create mode 100644 trunk/drivers/clk/ux500/clk.h create mode 100644 trunk/drivers/clk/ux500/u8500_clk.c create mode 100644 trunk/drivers/clk/ux500/u8540_clk.c create mode 100644 trunk/drivers/clk/ux500/u9540_clk.c create mode 100644 trunk/drivers/clk/versatile/clk-realview.c create mode 100644 trunk/drivers/clocksource/bcm2835_timer.c create mode 100644 trunk/drivers/irqchip/Kconfig create mode 100644 trunk/drivers/irqchip/Makefile create mode 100644 trunk/drivers/irqchip/irq-bcm2835.c rename trunk/{arch/arm/mach-picoxcell/include/mach/hardware.h => include/linux/bcm2835_timer.h} (70%) rename trunk/{arch/arm/mach-pnx4008/include/mach/param.h => include/linux/clk/bcm2835.h} (83%) rename trunk/{arch/arm/mach-versatile/include/mach/io.h => include/linux/irqchip/bcm2835.h} (74%) rename trunk/{arch/arm/plat-omap/include/plat/mcbsp.h => include/linux/platform_data/asoc-ti-mcbsp.h} (100%) create mode 100644 trunk/include/linux/platform_data/clk-realview.h create mode 100644 trunk/include/linux/platform_data/clk-ux500.h rename trunk/{arch/arm/plat-omap/include/plat/dsp.h => include/linux/platform_data/dsp-omap.h} (100%) rename trunk/{arch/arm/plat-omap/include/plat/keypad.h => include/linux/platform_data/keypad-omap.h} (100%) rename trunk/{arch/arm/plat-omap/include/plat/lcd_mipid.h => include/linux/platform_data/lcd-mipid.h} (100%) rename trunk/{arch/arm/plat-omap/include/plat/nand.h => include/linux/platform_data/mtd-nand-omap2.h} (100%) rename trunk/{arch/arm/plat-omap/include/plat/onenand.h => include/linux/platform_data/mtd-onenand-omap2.h} (100%) rename trunk/{arch/arm/mach-u300/include/mach/gpio-u300.h => include/linux/platform_data/pinctrl-coh901.h} (72%) rename trunk/{arch/arm/plat-omap/include/plat/remoteproc.h => include/linux/platform_data/remoteproc-omap.h} (100%) rename trunk/{arch/arm/plat-omap/include/plat/mcspi.h => include/linux/platform_data/spi-omap2-mcspi.h} (100%) rename trunk/{arch/arm/plat-omap/include/plat/voltage.h => include/linux/platform_data/voltage-omap.h} (100%) diff --git a/[refs] b/[refs] index 630bcd619270..7166c51051f0 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: ad932bb6b549722a561fb31ac2fa50dcbcb3e36b +refs/heads/master: 0b177ab53d0a2303ba287ec8babfd6e1de801500 diff --git a/trunk/Documentation/arm/Samsung-S3C24XX/GPIO.txt b/trunk/Documentation/arm/Samsung-S3C24XX/GPIO.txt index 816d6071669e..8b46c79679c4 100644 --- a/trunk/Documentation/arm/Samsung-S3C24XX/GPIO.txt +++ b/trunk/Documentation/arm/Samsung-S3C24XX/GPIO.txt @@ -1,4 +1,4 @@ - S3C2410 GPIO Control + S3C24XX GPIO Control ==================== Introduction @@ -12,7 +12,7 @@ Introduction of the s3c2410 GPIO system, please read the Samsung provided data-sheet/users manual to find out the complete list. - See Documentation/arm/Samsung/GPIO.txt for the core implemetation. + See Documentation/arm/Samsung/GPIO.txt for the core implementation. GPIOLIB @@ -41,8 +41,8 @@ GPIOLIB GPIOLIB conversion ------------------ -If you need to convert your board or driver to use gpiolib from the exiting -s3c2410 api, then here are some notes on the process. +If you need to convert your board or driver to use gpiolib from the phased +out s3c2410 API, then here are some notes on the process. 1) If your board is exclusively using an GPIO, say to control peripheral power, then it will require to claim the gpio with gpio_request() before @@ -55,7 +55,7 @@ s3c2410 api, then here are some notes on the process. as they have the same arguments, and can either take the pin specific values, or the more generic special-function-number arguments. -3) s3c2410_gpio_pullup() changs have the problem that whilst the +3) s3c2410_gpio_pullup() changes have the problem that whilst the s3c2410_gpio_pullup(x, 1) can be easily translated to the s3c_gpio_setpull(x, S3C_GPIO_PULL_NONE), the s3c2410_gpio_pullup(x, 0) are not so easy. @@ -74,7 +74,7 @@ s3c2410 api, then here are some notes on the process. when using gpio_get_value() on an output pin (s3c2410_gpio_getpin would return the value the pin is supposed to be outputting). -6) s3c2410_gpio_getirq() should be directly replacable with the +6) s3c2410_gpio_getirq() should be directly replaceable with the gpio_to_irq() call. The s3c2410_gpio and gpio_ calls have always operated on the same gpio @@ -105,7 +105,7 @@ PIN Numbers ----------- Each pin has an unique number associated with it in regs-gpio.h, - eg S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell + e.g. S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell the GPIO functions which pin is to be used. With the conversion to gpiolib, there is no longer a direct conversion @@ -120,31 +120,27 @@ Configuring a pin The following function allows the configuration of a given pin to be changed. - void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function); + void s3c_gpio_cfgpin(unsigned int pin, unsigned int function); - Eg: + e.g.: - s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0); - s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1); + s3c_gpio_cfgpin(S3C2410_GPA(0), S3C_GPIO_SFN(1)); + s3c_gpio_cfgpin(S3C2410_GPE(8), S3C_GPIO_SFN(2)); which would turn GPA(0) into the lowest Address line A0, and set GPE(8) to be connected to the SDIO/MMC controller's SDDAT1 line. - The s3c_gpio_cfgpin() call is a functional replacement for this call. - Reading the current configuration --------------------------------- - The current configuration of a pin can be read by using: + The current configuration of a pin can be read by using standard + gpiolib function: - s3c2410_gpio_getcfg(unsigned int pin); + s3c_gpio_getcfg(unsigned int pin); The return value will be from the same set of values which can be - passed to s3c2410_gpio_cfgpin(). - - The s3c_gpio_getcfg() call should be a functional replacement for - this call. + passed to s3c_gpio_cfgpin(). Configuring a pull-up resistor @@ -154,61 +150,33 @@ Configuring a pull-up resistor pull-up resistors enabled. This can be configured by the following function: - void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); - - Where the to value is zero to set the pull-up off, and 1 to enable - the specified pull-up. Any other values are currently undefined. - - The s3c_gpio_setpull() offers similar functionality, but with the - ability to encode whether the pull is up or down. Currently there - is no 'just on' state, so up or down must be selected. - - -Getting the state of a PIN --------------------------- - - The state of a pin can be read by using the function: - - unsigned int s3c2410_gpio_getpin(unsigned int pin); + void s3c_gpio_setpull(unsigned int pin, unsigned int to); - This will return either zero or non-zero. Do not count on this - function returning 1 if the pin is set. + Where the to value is S3C_GPIO_PULL_NONE to set the pull-up off, + and S3C_GPIO_PULL_UP to enable the specified pull-up. Any other + values are currently undefined. - This call is now implemented by the relevant gpiolib calls, convert - your board or driver to use gpiolib. - - -Setting the state of a PIN --------------------------- - - The value an pin is outputing can be modified by using the following: - void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); +Getting and setting the state of a PIN +-------------------------------------- - Which sets the given pin to the value. Use 0 to write 0, and 1 to - set the output to 1. - - This call is now implemented by the relevant gpiolib calls, convert + These calls are now implemented by the relevant gpiolib calls, convert your board or driver to use gpiolib. Getting the IRQ number associated with a PIN -------------------------------------------- - The following function can map the given pin number to an IRQ + A standard gpiolib function can map the given pin number to an IRQ number to pass to the IRQ system. - int s3c2410_gpio_getirq(unsigned int pin); + int gpio_to_irq(unsigned int pin); Note, not all pins have an IRQ. - This call is now implemented by the relevant gpiolib calls, convert - your board or driver to use gpiolib. - -Authour +Author ------- - Ben Dooks, 03 October 2004 Copyright 2004 Ben Dooks, Simtec Electronics diff --git a/trunk/Documentation/arm/Samsung/GPIO.txt b/trunk/Documentation/arm/Samsung/GPIO.txt index 513f2562c1a3..795adfd88081 100644 --- a/trunk/Documentation/arm/Samsung/GPIO.txt +++ b/trunk/Documentation/arm/Samsung/GPIO.txt @@ -5,14 +5,14 @@ Introduction ------------ This outlines the Samsung GPIO implementation and the architecture -specific calls provided alongisde the drivers/gpio core. +specific calls provided alongside the drivers/gpio core. S3C24XX (Legacy) ---------------- See Documentation/arm/Samsung-S3C24XX/GPIO.txt for more information -about these devices. Their implementation is being brought into line +about these devices. Their implementation has been brought into line with the core samsung implementation described in this document. @@ -29,7 +29,7 @@ GPIO numbering is synchronised between the Samsung and gpiolib system. PIN configuration ----------------- -Pin configuration is specific to the Samsung architecutre, with each SoC +Pin configuration is specific to the Samsung architecture, with each SoC registering the necessary information for the core gpio configuration implementation to configure pins as necessary. @@ -38,5 +38,3 @@ driver or machine to change gpio configuration. See arch/arm/plat-samsung/include/plat/gpio-cfg.h for more information on these functions. - - diff --git a/trunk/Documentation/arm/memory.txt b/trunk/Documentation/arm/memory.txt index 208a2d465b92..4bfb9ffbdbc1 100644 --- a/trunk/Documentation/arm/memory.txt +++ b/trunk/Documentation/arm/memory.txt @@ -51,6 +51,9 @@ ffc00000 ffefffff DMA memory mapping region. Memory returned ff000000 ffbfffff Reserved for future expansion of DMA mapping region. +fee00000 feffffff Mapping of PCI I/O space. This is a static + mapping within the vmalloc space. + VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space. Memory returned by vmalloc/ioremap will be dynamically placed in this region. diff --git a/trunk/Documentation/devicetree/bindings/arm/bcm2835.txt b/trunk/Documentation/devicetree/bindings/arm/bcm2835.txt new file mode 100644 index 000000000000..ac683480c486 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/arm/bcm2835.txt @@ -0,0 +1,8 @@ +Broadcom BCM2835 device tree bindings +------------------------------------------- + +Boards with the BCM2835 SoC shall have the following properties: + +Required root node property: + +compatible = "brcm,bcm2835"; diff --git a/trunk/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt b/trunk/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt new file mode 100644 index 000000000000..31af1cbb60bd --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt @@ -0,0 +1,17 @@ +* Marvell Tauros2 Cache + +Required properties: +- compatible : Should be "marvell,tauros2-cache". +- marvell,tauros2-cache-features : Specify the features supported for the + tauros2 cache. + The features including + CACHE_TAUROS2_PREFETCH_ON (1 << 0) + CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1) + The definition can be found at + arch/arm/include/asm/hardware/cache-tauros2.h + +Example: + L2: l2-cache { + compatible = "marvell,tauros2-cache"; + marvell,tauros2-cache-features = <0x3>; + }; diff --git a/trunk/Documentation/devicetree/bindings/arm/msm/timer.txt b/trunk/Documentation/devicetree/bindings/arm/msm/timer.txt new file mode 100644 index 000000000000..8c5907b9cae8 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/arm/msm/timer.txt @@ -0,0 +1,38 @@ +* MSM Timer + +Properties: + +- compatible : Should at least contain "qcom,msm-timer". More specific + properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general + purpose timer and a debug timer respectively. + +- interrupts : Interrupt indicating a match event. + +- reg : Specifies the base address of the timer registers. The second region + specifies an optional register used to configure the clock divider. + +- clock-frequency : The frequency of the timer in Hz. + +Optional: + +- cpu-offset : per-cpu offset used when the timer is accessed without the + CPU remapping facilities. The offset is cpu-offset * cpu-nr. + +Example: + + timer@200a004 { + compatible = "qcom,msm-gpt", "qcom,msm-timer"; + interrupts = <1 2 0x301>; + reg = <0x0200a004 0x10>; + clock-frequency = <32768>; + cpu-offset = <0x40000>; + }; + + timer@200a024 { + compatible = "qcom,msm-dgt", "qcom,msm-timer"; + interrupts = <1 3 0x301>; + reg = <0x0200a024 0x10>, + <0x0200a034 0x4>; + clock-frequency = <6750000>; + cpu-offset = <0x40000>; + }; diff --git a/trunk/Documentation/devicetree/bindings/arm/omap/omap.txt b/trunk/Documentation/devicetree/bindings/arm/omap/omap.txt index ccdd0e53451f..d0051a750587 100644 --- a/trunk/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/trunk/Documentation/devicetree/bindings/arm/omap/omap.txt @@ -36,6 +36,9 @@ Boards: - OMAP3 BeagleBoard : Low cost community board compatible = "ti,omap3-beagle", "ti,omap3" +- OMAP3 Tobi with Overo : Commercial expansion board with daughter board + compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3" + - OMAP4 SDP : Software Developement Board compatible = "ti,omap4-sdp", "ti,omap4430" diff --git a/trunk/Documentation/devicetree/bindings/arm/pmu.txt b/trunk/Documentation/devicetree/bindings/arm/pmu.txt index 1c044eb320cc..343781b9f246 100644 --- a/trunk/Documentation/devicetree/bindings/arm/pmu.txt +++ b/trunk/Documentation/devicetree/bindings/arm/pmu.txt @@ -7,8 +7,12 @@ representation in the device tree should be done as under:- Required properties: - compatible : should be one of + "arm,cortex-a15-pmu" "arm,cortex-a9-pmu" "arm,cortex-a8-pmu" + "arm,cortex-a7-pmu" + "arm,cortex-a5-pmu" + "arm,arm11mpcore-pmu" "arm,arm1176-pmu" "arm,arm1136-pmu" - interrupts : 1 combined interrupt or 1 per core. diff --git a/trunk/Documentation/devicetree/bindings/clock/imx23-clock.txt b/trunk/Documentation/devicetree/bindings/clock/imx23-clock.txt new file mode 100644 index 000000000000..a0b867ef8d96 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/clock/imx23-clock.txt @@ -0,0 +1,76 @@ +* Clock bindings for Freescale i.MX23 + +Required properties: +- compatible: Should be "fsl,imx23-clkctrl" +- reg: Address and length of the register set +- #clock-cells: Should be <1> + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. The following is a full list of i.MX23 +clocks and IDs. + + Clock ID + ------------------ + ref_xtal 0 + pll 1 + ref_cpu 2 + ref_emi 3 + ref_pix 4 + ref_io 5 + saif_sel 6 + lcdif_sel 7 + gpmi_sel 8 + ssp_sel 9 + emi_sel 10 + cpu 11 + etm_sel 12 + cpu_pll 13 + cpu_xtal 14 + hbus 15 + xbus 16 + lcdif_div 17 + ssp_div 18 + gpmi_div 19 + emi_pll 20 + emi_xtal 21 + etm_div 22 + saif_div 23 + clk32k_div 24 + rtc 25 + adc 26 + spdif_div 27 + clk32k 28 + dri 29 + pwm 30 + filt 31 + uart 32 + ssp 33 + gpmi 34 + spdif 35 + emi 36 + saif 37 + lcdif 38 + etm 39 + usb 40 + usb_pwr 41 + +Examples: + +clks: clkctrl@80040000 { + compatible = "fsl,imx23-clkctrl"; + reg = <0x80040000 0x2000>; + #clock-cells = <1>; + clock-output-names = + ... + "uart", /* 32 */ + ... + "end_of_list"; +}; + +auart0: serial@8006c000 { + compatible = "fsl,imx23-auart"; + reg = <0x8006c000 0x2000>; + interrupts = <24 25 23>; + clocks = <&clks 32>; + status = "disabled"; +}; diff --git a/trunk/Documentation/devicetree/bindings/clock/imx28-clock.txt b/trunk/Documentation/devicetree/bindings/clock/imx28-clock.txt new file mode 100644 index 000000000000..aa2af2866fe8 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/clock/imx28-clock.txt @@ -0,0 +1,99 @@ +* Clock bindings for Freescale i.MX28 + +Required properties: +- compatible: Should be "fsl,imx28-clkctrl" +- reg: Address and length of the register set +- #clock-cells: Should be <1> + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. The following is a full list of i.MX28 +clocks and IDs. + + Clock ID + ------------------ + ref_xtal 0 + pll0 1 + pll1 2 + pll2 3 + ref_cpu 4 + ref_emi 5 + ref_io0 6 + ref_io1 7 + ref_pix 8 + ref_hsadc 9 + ref_gpmi 10 + saif0_sel 11 + saif1_sel 12 + gpmi_sel 13 + ssp0_sel 14 + ssp1_sel 15 + ssp2_sel 16 + ssp3_sel 17 + emi_sel 18 + etm_sel 19 + lcdif_sel 20 + cpu 21 + ptp_sel 22 + cpu_pll 23 + cpu_xtal 24 + hbus 25 + xbus 26 + ssp0_div 27 + ssp1_div 28 + ssp2_div 29 + ssp3_div 30 + gpmi_div 31 + emi_pll 32 + emi_xtal 33 + lcdif_div 34 + etm_div 35 + ptp 36 + saif0_div 37 + saif1_div 38 + clk32k_div 39 + rtc 40 + lradc 41 + spdif_div 42 + clk32k 43 + pwm 44 + uart 45 + ssp0 46 + ssp1 47 + ssp2 48 + ssp3 49 + gpmi 50 + spdif 51 + emi 52 + saif0 53 + saif1 54 + lcdif 55 + etm 56 + fec 57 + can0 58 + can1 59 + usb0 60 + usb1 61 + usb0_pwr 62 + usb1_pwr 63 + enet_out 64 + +Examples: + +clks: clkctrl@80040000 { + compatible = "fsl,imx28-clkctrl"; + reg = <0x80040000 0x2000>; + #clock-cells = <1>; + clock-output-names = + ... + "uart", /* 45 */ + ... + "end_of_list"; +}; + +auart0: serial@8006a000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x8006a000 0x2000>; + interrupts = <112 70 71>; + clocks = <&clks 45>; + status = "disabled"; +}; diff --git a/trunk/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/trunk/Documentation/devicetree/bindings/clock/imx6q-clock.txt new file mode 100644 index 000000000000..492bd991d52a --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/clock/imx6q-clock.txt @@ -0,0 +1,222 @@ +* Clock bindings for Freescale i.MX6 Quad + +Required properties: +- compatible: Should be "fsl,imx6q-ccm" +- reg: Address and length of the register set +- interrupts: Should contain CCM interrupt +- #clock-cells: Should be <1> + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. The following is a full list of i.MX6Q +clocks and IDs. + + Clock ID + --------------------------- + dummy 0 + ckil 1 + ckih 2 + osc 3 + pll2_pfd0_352m 4 + pll2_pfd1_594m 5 + pll2_pfd2_396m 6 + pll3_pfd0_720m 7 + pll3_pfd1_540m 8 + pll3_pfd2_508m 9 + pll3_pfd3_454m 10 + pll2_198m 11 + pll3_120m 12 + pll3_80m 13 + pll3_60m 14 + twd 15 + step 16 + pll1_sw 17 + periph_pre 18 + periph2_pre 19 + periph_clk2_sel 20 + periph2_clk2_sel 21 + axi_sel 22 + esai_sel 23 + asrc_sel 24 + spdif_sel 25 + gpu2d_axi 26 + gpu3d_axi 27 + gpu2d_core_sel 28 + gpu3d_core_sel 29 + gpu3d_shader_sel 30 + ipu1_sel 31 + ipu2_sel 32 + ldb_di0_sel 33 + ldb_di1_sel 34 + ipu1_di0_pre_sel 35 + ipu1_di1_pre_sel 36 + ipu2_di0_pre_sel 37 + ipu2_di1_pre_sel 38 + ipu1_di0_sel 39 + ipu1_di1_sel 40 + ipu2_di0_sel 41 + ipu2_di1_sel 42 + hsi_tx_sel 43 + pcie_axi_sel 44 + ssi1_sel 45 + ssi2_sel 46 + ssi3_sel 47 + usdhc1_sel 48 + usdhc2_sel 49 + usdhc3_sel 50 + usdhc4_sel 51 + enfc_sel 52 + emi_sel 53 + emi_slow_sel 54 + vdo_axi_sel 55 + vpu_axi_sel 56 + cko1_sel 57 + periph 58 + periph2 59 + periph_clk2 60 + periph2_clk2 61 + ipg 62 + ipg_per 63 + esai_pred 64 + esai_podf 65 + asrc_pred 66 + asrc_podf 67 + spdif_pred 68 + spdif_podf 69 + can_root 70 + ecspi_root 71 + gpu2d_core_podf 72 + gpu3d_core_podf 73 + gpu3d_shader 74 + ipu1_podf 75 + ipu2_podf 76 + ldb_di0_podf 77 + ldb_di1_podf 78 + ipu1_di0_pre 79 + ipu1_di1_pre 80 + ipu2_di0_pre 81 + ipu2_di1_pre 82 + hsi_tx_podf 83 + ssi1_pred 84 + ssi1_podf 85 + ssi2_pred 86 + ssi2_podf 87 + ssi3_pred 88 + ssi3_podf 89 + uart_serial_podf 90 + usdhc1_podf 91 + usdhc2_podf 92 + usdhc3_podf 93 + usdhc4_podf 94 + enfc_pred 95 + enfc_podf 96 + emi_podf 97 + emi_slow_podf 98 + vpu_axi_podf 99 + cko1_podf 100 + axi 101 + mmdc_ch0_axi_podf 102 + mmdc_ch1_axi_podf 103 + arm 104 + ahb 105 + apbh_dma 106 + asrc 107 + can1_ipg 108 + can1_serial 109 + can2_ipg 110 + can2_serial 111 + ecspi1 112 + ecspi2 113 + ecspi3 114 + ecspi4 115 + ecspi5 116 + enet 117 + esai 118 + gpt_ipg 119 + gpt_ipg_per 120 + gpu2d_core 121 + gpu3d_core 122 + hdmi_iahb 123 + hdmi_isfr 124 + i2c1 125 + i2c2 126 + i2c3 127 + iim 128 + enfc 129 + ipu1 130 + ipu1_di0 131 + ipu1_di1 132 + ipu2 133 + ipu2_di0 134 + ldb_di0 135 + ldb_di1 136 + ipu2_di1 137 + hsi_tx 138 + mlb 139 + mmdc_ch0_axi 140 + mmdc_ch1_axi 141 + ocram 142 + openvg_axi 143 + pcie_axi 144 + pwm1 145 + pwm2 146 + pwm3 147 + pwm4 148 + per1_bch 149 + gpmi_bch_apb 150 + gpmi_bch 151 + gpmi_io 152 + gpmi_apb 153 + sata 154 + sdma 155 + spba 156 + ssi1 157 + ssi2 158 + ssi3 159 + uart_ipg 160 + uart_serial 161 + usboh3 162 + usdhc1 163 + usdhc2 164 + usdhc3 165 + usdhc4 166 + vdo_axi 167 + vpu_axi 168 + cko1 169 + pll1_sys 170 + pll2_bus 171 + pll3_usb_otg 172 + pll4_audio 173 + pll5_video 174 + pll6_mlb 175 + pll7_usb_host 176 + pll8_enet 177 + ssi1_ipg 178 + ssi2_ipg 179 + ssi3_ipg 180 + rom 181 + usbphy1 182 + usbphy2 183 + ldb_di0_div_3_5 184 + ldb_di1_div_3_5 185 + +Examples: + +clks: ccm@020c4000 { + compatible = "fsl,imx6q-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <0 87 0x04 0 88 0x04>; + #clock-cells = <1>; + clock-output-names = ... + "uart_ipg", + "uart_serial", + ...; +}; + +uart1: serial@02020000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = <0 26 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; + status = "disabled"; +}; diff --git a/trunk/Documentation/devicetree/bindings/gpio/gpio-samsung.txt b/trunk/Documentation/devicetree/bindings/gpio/gpio-samsung.txt index 5375625e8cd2..f1e5dfecf55d 100644 --- a/trunk/Documentation/devicetree/bindings/gpio/gpio-samsung.txt +++ b/trunk/Documentation/devicetree/bindings/gpio/gpio-samsung.txt @@ -39,3 +39,46 @@ Example: #gpio-cells = <4>; gpio-controller; }; + + +Samsung S3C24XX GPIO Controller + +Required properties: +- compatible: Compatible property value should be "samsung,s3c24xx-gpio". + +- reg: Physical base address of the controller and length of memory mapped + region. + +- #gpio-cells: Should be 3. The syntax of the gpio specifier used by client nodes + should be the following with values derived from the SoC user manual. + <[phandle of the gpio controller node] + [pin number within the gpio controller] + [mux function] + [flags and pull up/down] + + Values for gpio specifier: + - Pin number: depending on the controller a number from 0 up to 15. + - Mux function: Depending on the SoC and the gpio bank the gpio can be set + as input, output or a special function + - Flags and Pull Up/Down: the values to use differ for the individual SoCs + example S3C2416/S3C2450: + 0 - Pull Up/Down Disabled. + 1 - Pull Down Enabled. + 2 - Pull Up Enabled. + Bit 16 (0x00010000) - Input is active low. + Consult the user manual for the correct values of Mux and Pull Up/Down. + +- gpio-controller: Specifies that the node is a gpio controller. +- #address-cells: should be 1. +- #size-cells: should be 1. + +Example: + + gpa: gpio-controller@56000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "samsung,s3c24xx-gpio"; + reg = <0x56000000 0x10>; + #gpio-cells = <3>; + gpio-controller; + }; diff --git a/trunk/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt b/trunk/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt index 16695d9cf1e8..66788fda1db3 100644 --- a/trunk/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt +++ b/trunk/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt @@ -11,6 +11,11 @@ Required properties: - interrupt-controller: Mark the device node as an interrupt controller The first cell is the GPIO number. The second cell is not used. +- ti,use-leds : Enables LEDA and LEDB outputs if set +- ti,debounce : if n-th bit is set, debounces GPIO-n +- ti,mmc-cd : if n-th bit is set, GPIO-n controls VMMC(n+1) +- ti,pullups : if n-th bit is set, set a pullup on GPIO-n +- ti,pulldowns : if n-th bit is set, set a pulldown on GPIO-n Example: @@ -20,4 +25,5 @@ twl_gpio: gpio { gpio-controller; #interrupt-cells = <2>; interrupt-controller; + ti,use-leds; }; diff --git a/trunk/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/trunk/Documentation/devicetree/bindings/i2c/trivial-devices.txt index 1a85f986961b..2f5322b119eb 100644 --- a/trunk/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/trunk/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -56,3 +56,4 @@ stm,m41t00 Serial Access TIMEKEEPER stm,m41t62 Serial real-time clock (RTC) with alarm stm,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS ti,tsc2003 I2C Touch-Screen Controller +ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface diff --git a/trunk/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt b/trunk/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt new file mode 100644 index 000000000000..548892c08c59 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt @@ -0,0 +1,110 @@ +BCM2835 Top-Level ("ARMCTRL") Interrupt Controller + +The BCM2835 contains a custom top-level interrupt controller, which supports +72 interrupt sources using a 2-level register scheme. The interrupt +controller, or the HW block containing it, is referred to occasionally +as "armctrl" in the SoC documentation, hence naming of this binding. + +Required properties: + +- compatible : should be "brcm,bcm2835-armctrl-ic.txt" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 2. + + The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic + pending" register, or 1/2 respectively for interrupts in the "IRQ pending + 1/2" register. + + The 2nd cell contains the interrupt number within the bank. Valid values + are 0..7 for bank 0, and 0..31 for bank 1. + +The interrupt sources are as follows: + +Bank 0: +0: ARM_TIMER +1: ARM_MAILBOX +2: ARM_DOORBELL_0 +3: ARM_DOORBELL_1 +4: VPU0_HALTED +5: VPU1_HALTED +6: ILLEGAL_TYPE0 +7: ILLEGAL_TYPE1 + +Bank 1: +0: TIMER0 +1: TIMER1 +2: TIMER2 +3: TIMER3 +4: CODEC0 +5: CODEC1 +6: CODEC2 +7: VC_JPEG +8: ISP +9: VC_USB +10: VC_3D +11: TRANSPOSER +12: MULTICORESYNC0 +13: MULTICORESYNC1 +14: MULTICORESYNC2 +15: MULTICORESYNC3 +16: DMA0 +17: DMA1 +18: VC_DMA2 +19: VC_DMA3 +20: DMA4 +21: DMA5 +22: DMA6 +23: DMA7 +24: DMA8 +25: DMA9 +26: DMA10 +27: DMA11 +28: DMA12 +29: AUX +30: ARM +31: VPUDMA + +Bank 2: +0: HOSTPORT +1: VIDEOSCALER +2: CCP2TX +3: SDC +4: DSI0 +5: AVE +6: CAM0 +7: CAM1 +8: HDMI0 +9: HDMI1 +10: PIXELVALVE1 +11: I2CSPISLV +12: DSI1 +13: PWA0 +14: PWA1 +15: CPR +16: SMI +17: GPIO0 +18: GPIO1 +19: GPIO2 +20: GPIO3 +21: VC_I2C +22: VC_SPI +23: VC_I2SPCM +24: VC_SDIO +25: VC_UART +26: SLIMBUS +27: VEC +28: CPG +29: RNG +30: VC_ARASANSDIO +31: AVSPMON + +Example: + +intc: interrupt-controller { + compatible = "brcm,bcm2835-armctrl-ic"; + reg = <0x7e00b200 0x200>; + interrupt-controller; + #interrupt-cells = <2>; +}; diff --git a/trunk/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/trunk/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt new file mode 100644 index 000000000000..9ceb19e0c7fd --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt @@ -0,0 +1,52 @@ +* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin + +Required properties: +- compatible : Should be "jedec,lpddr2-timings" +- min-freq : minimum DDR clock frequency for the speed-bin. Type is +- max-freq : maximum DDR clock frequency for the speed-bin. Type is + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type and the default unit is ps (pico seconds). Parameters with +a different unit have a suffix indicating the unit such as 'tRAS-max-ns' +- tRCD +- tWR +- tRAS-min +- tRRD +- tWTR +- tXP +- tRTP +- tDQSCK-max +- tFAW +- tZQCS +- tZQinit +- tRPab +- tZQCL +- tCKESR +- tRAS-max-ns +- tDQSCK-max-derated + +Example: + +timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; +}; diff --git a/trunk/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/trunk/Documentation/devicetree/bindings/lpddr2/lpddr2.txt new file mode 100644 index 000000000000..58354a075e13 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/lpddr2/lpddr2.txt @@ -0,0 +1,102 @@ +* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2 + +Required properties: +- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2", + "jedec,lpddr2-s4" + + "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type + + "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type + + "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type + +- density : representing density in Mb (Mega bits) + +- io-width : representing bus width. Possible values are 8, 16, and 32 + +Optional properties: + +The following optional properties represent the minimum value of some AC +timing parameters of the DDR device in terms of number of clock cycles. +These values shall be obtained from the device data-sheet. +- tRRD-min-tck +- tWTR-min-tck +- tXP-min-tck +- tRTP-min-tck +- tCKE-min-tck +- tRPab-min-tck +- tRCD-min-tck +- tWR-min-tck +- tRASmin-min-tck +- tCKESR-min-tck +- tFAW-min-tck + +Child nodes: +- The lpddr2 node may have one or more child nodes of type "lpddr2-timings". + "lpddr2-timings" provides AC timing parameters of the device for + a given speed-bin. The user may provide the timings for as many + speed-bins as is required. Please see Documentation/devicetree/ + bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings" + +Example: + +elpida_ECB240ABACN : lpddr2 { + compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; + density = <2048>; + io-width = <32>; + + tRPab-min-tck = <3>; + tRCD-min-tck = <3>; + tWR-min-tck = <3>; + tRASmin-min-tck = <3>; + tRRD-min-tck = <2>; + tWTR-min-tck = <2>; + tXP-min-tck = <2>; + tRTP-min-tck = <2>; + tCKE-min-tck = <3>; + tCKESR-min-tck = <3>; + tFAW-min-tck = <8>; + + timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + }; + + timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <200000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <10000>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + }; + +} diff --git a/trunk/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/trunk/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt new file mode 100644 index 000000000000..938f8e1ba205 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt @@ -0,0 +1,55 @@ +* EMIF family of TI SDRAM controllers + +EMIF - External Memory Interface - is an SDRAM controller used in +TI SoCs. EMIF supports, based on the IP revision, one or more of +DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance +of the EMIF IP and memory parts attached to it. + +Required properties: +- compatible : Should be of the form "ti,emif-" where + is the IP revision of the specific EMIF instance. + +- phy-type : indicating the DDR phy type. Following are the + allowed values + <1> : Attila PHY + <2> : Intelli PHY + +- device-handle : phandle to a "lpddr2" node representing the memory part + +- ti,hwmods : For TI hwmods processing and omap device creation + the value shall be "emif" where is the number of the EMIF + instance with base 1. + +Optional properties: +- cs1-used : Have this property if CS1 of this EMIF + instance has a memory part attached to it. If there is a memory + part attached to CS1, it should be the same type as the one on CS0, + so there is no need to give the details of this memory part. + +- cal-resistor-per-cs : Have this property if the board has one + calibration resistor per chip-select. + +- hw-caps-read-idle-ctrl: Have this property if the controller + supports read idle window programming + +- hw-caps-dll-calib-ctrl: Have this property if the controller + supports dll calibration control + +- hw-caps-ll-interface : Have this property if the controller + has a low latency interface and corresponding interrupt events + +- hw-caps-temp-alert : Have this property if the controller + has capability for generating SDRAM temperature alerts + +Example: + +emif1: emif@0x4c000000 { + compatible = "ti,emif-4d"; + ti,hwmods = "emif2"; + phy-type = <1>; + device-handle = <&elpida_ECB240ABACN>; + cs1-used; + hw-caps-read-idle-ctrl; + hw-caps-ll-interface; + hw-caps-temp-alert; +}; diff --git a/trunk/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/trunk/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt new file mode 100644 index 000000000000..f1421e2bbab7 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt @@ -0,0 +1,31 @@ +PXA3xx NAND DT bindings + +Required properties: + + - compatible: Should be "marvell,pxa3xx-nand" + - reg: The register base for the controller + - interrupts: The interrupt to map + - #address-cells: Set to <1> if the node includes partitions + +Optional properties: + + - marvell,nand-enable-arbiter: Set to enable the bus arbiter + - marvell,nand-keep-config: Set to keep the NAND controller config as set + by the bootloader + - num-cs: Number of chipselect lines to usw + +Example: + + nand0: nand@43100000 { + compatible = "marvell,pxa3xx-nand"; + reg = <0x43100000 90>; + interrupts = <45>; + #address-cells = <1>; + + marvell,nand-enable-arbiter; + marvell,nand-keep-config; + num-cs = <1>; + + /* partitions (optional) */ + }; + diff --git a/trunk/Documentation/devicetree/bindings/regulator/tps6586x.txt b/trunk/Documentation/devicetree/bindings/regulator/tps6586x.txt index da80c2ae0915..a2436e1edfc1 100644 --- a/trunk/Documentation/devicetree/bindings/regulator/tps6586x.txt +++ b/trunk/Documentation/devicetree/bindings/regulator/tps6586x.txt @@ -8,7 +8,8 @@ Required properties: - gpio-controller: mark the device as a GPIO controller - regulators: list of regulators provided by this controller, must have property "regulator-compatible" to match their hardware counterparts: - sm[0-2], ldo[0-9] and ldo_rtc + sys, sm[0-2], ldo[0-9] and ldo_rtc +- sys-supply: The input supply for SYS. - vin-sm0-supply: The input supply for the SM0. - vin-sm1-supply: The input supply for the SM1. - vin-sm2-supply: The input supply for the SM2. @@ -20,6 +21,9 @@ Required properties: Each regulator is defined using the standard binding for regulators. +Note: LDO5 and LDO_RTC is supplied by SYS regulator internally and driver + take care of making proper parent child relationship. + Example: pmu: tps6586x@34 { @@ -30,6 +34,7 @@ Example: #gpio-cells = <2>; gpio-controller; + sys-supply = <&some_reg>; vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; @@ -43,8 +48,16 @@ Example: #address-cells = <1>; #size-cells = <0>; - sm0_reg: regulator@0 { + sys_reg: regulator@0 { reg = <0>; + regulator-compatible = "sys"; + regulator-name = "vdd_sys"; + regulator-boot-on; + regulator-always-on; + }; + + sm0_reg: regulator@1 { + reg = <1>; regulator-compatible = "sm0"; regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; @@ -52,8 +65,8 @@ Example: regulator-always-on; }; - sm1_reg: regulator@1 { - reg = <1>; + sm1_reg: regulator@2 { + reg = <2>; regulator-compatible = "sm1"; regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; @@ -61,8 +74,8 @@ Example: regulator-always-on; }; - sm2_reg: regulator@2 { - reg = <2>; + sm2_reg: regulator@3 { + reg = <3>; regulator-compatible = "sm2"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; @@ -70,72 +83,72 @@ Example: regulator-always-on; }; - ldo0_reg: regulator@3 { - reg = <3>; + ldo0_reg: regulator@4 { + reg = <4>; regulator-compatible = "ldo0"; regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - ldo1_reg: regulator@4 { - reg = <4>; + ldo1_reg: regulator@5 { + reg = <5>; regulator-compatible = "ldo1"; regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; - ldo2_reg: regulator@5 { - reg = <5>; + ldo2_reg: regulator@6 { + reg = <6>; regulator-compatible = "ldo2"; regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; - ldo3_reg: regulator@6 { - reg = <6>; + ldo3_reg: regulator@7 { + reg = <7>; regulator-compatible = "ldo3"; regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; - ldo4_reg: regulator@7 { - reg = <7>; + ldo4_reg: regulator@8 { + reg = <8>; regulator-compatible = "ldo4"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; - ldo5_reg: regulator@8 { - reg = <8>; + ldo5_reg: regulator@9 { + reg = <9>; regulator-compatible = "ldo5"; regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; - ldo6_reg: regulator@9 { - reg = <9>; + ldo6_reg: regulator@10 { + reg = <10>; regulator-compatible = "ldo6"; regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; - ldo7_reg: regulator@10 { - reg = <10>; + ldo7_reg: regulator@11 { + reg = <11>; regulator-compatible = "ldo7"; regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; - ldo8_reg: regulator@11 { - reg = <11>; + ldo8_reg: regulator@12 { + reg = <12>; regulator-compatible = "ldo8"; regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; - ldo9_reg: regulator@12 { - reg = <12>; + ldo9_reg: regulator@13 { + reg = <13>; regulator-compatible = "ldo9"; regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; diff --git a/trunk/Documentation/devicetree/bindings/rtc/pxa-rtc.txt b/trunk/Documentation/devicetree/bindings/rtc/pxa-rtc.txt new file mode 100644 index 000000000000..8c6672a1b7d7 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/rtc/pxa-rtc.txt @@ -0,0 +1,14 @@ +* PXA RTC + +PXA specific RTC driver. + +Required properties: +- compatible : Should be "marvell,pxa-rtc" + +Examples: + +rtc@40900000 { + compatible = "marvell,pxa-rtc"; + reg = <0x40900000 0x3c>; + interrupts = <30 31>; +}; diff --git a/trunk/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt b/trunk/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt new file mode 100644 index 000000000000..2de21c2acf55 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt @@ -0,0 +1,22 @@ +BCM2835 System Timer + +The System Timer peripheral provides four 32-bit timer channels and a +single 64-bit free running counter. Each channel has an output compare +register, which is compared against the 32 least significant bits of the +free running counter values, and generates an interrupt. + +Required properties: + +- compatible : should be "brcm,bcm2835-system-timer.txt" +- reg : Specifies base physical address and size of the registers. +- interrupts : A list of 4 interrupt sinks; one per timer channel. +- clock-frequency : The frequency of the clock that drives the counter, in Hz. + +Example: + +timer { + compatible = "brcm,bcm2835-system-timer"; + reg = <0x7e003000 0x1000>; + interrupts = <1 0>, <1 1>, <1 2>, <1 3>; + clock-frequency = <1000000>; +}; diff --git a/trunk/Documentation/devicetree/bindings/vendor-prefixes.txt b/trunk/Documentation/devicetree/bindings/vendor-prefixes.txt index db4d3af3643c..4f293e5571f0 100644 --- a/trunk/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/trunk/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -10,6 +10,7 @@ apm Applied Micro Circuits Corporation (APM) arm ARM Ltd. atmel Atmel Corporation bosch Bosch Sensortec GmbH +brcm Broadcom Corporation cavium Cavium, Inc. chrp Common Hardware Reference Platform cortina Cortina Systems, Inc. diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index 53cc13c82cb1..9d3965cbf48c 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -595,7 +595,6 @@ M: Will Deacon S: Maintained F: arch/arm/kernel/perf_event* F: arch/arm/oprofile/common.c -F: arch/arm/kernel/pmu.c F: arch/arm/include/asm/pmu.h F: arch/arm/kernel/hw_breakpoint.c F: arch/arm/include/asm/hw_breakpoint.h @@ -1613,6 +1612,16 @@ L: netdev@vger.kernel.org S: Supported F: drivers/net/ethernet/broadcom/bnx2x/ +BROADCOM BCM2835 ARM ARCHICTURE +M: Stephen Warren +L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers) +T: git git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi.git +S: Maintained +F: arch/arm/mach-bcm2835/ +F: arch/arm/boot/dts/bcm2835* +F: arch/arm/configs/bcm2835_defconfig +F: drivers/*/*bcm2835* + BROADCOM TG3 GIGABIT ETHERNET DRIVER M: Matt Carlson M: Michael Chan diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index 2f88d8d97701..f416422ddb0e 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -202,6 +202,13 @@ config ARM_PATCH_PHYS_VIRT this feature (eg, building a kernel for a single machine) and you need to shrink the kernel to the minimal size. +config NEED_MACH_GPIO_H + bool + help + Select this when mach/gpio.h is required to provide special + definitions for this platform. The need for mach/gpio.h should + be avoided when possible. + config NEED_MACH_IO_H bool help @@ -247,39 +254,29 @@ config MMU # choice prompt "ARM system type" - default ARCH_VERSATILE + default ARCH_MULTIPLATFORM -config ARCH_SOCFPGA - bool "Altera SOCFPGA family" - select ARCH_WANT_OPTIONAL_GPIOLIB - select ARM_AMBA - select ARM_GIC - select CACHE_L2X0 - select CLKDEV_LOOKUP +config ARCH_MULTIPLATFORM + bool "Allow multiple platforms to be selected" + select ARM_PATCH_PHYS_VIRT + select AUTO_ZRELADDR select COMMON_CLK - select CPU_V7 - select DW_APB_TIMER - select DW_APB_TIMER_OF - select GENERIC_CLOCKEVENTS - select GPIO_PL061 if GPIOLIB - select HAVE_ARM_SCU + select MULTI_IRQ_HANDLER select SPARSE_IRQ select USE_OF - help - This enables support for Altera SOCFPGA Cyclone V platform + depends on MMU config ARCH_INTEGRATOR bool "ARM Ltd. Integrator family" select ARM_AMBA select ARCH_HAS_CPUFREQ select COMMON_CLK - select CLK_VERSATILE + select COMMON_CLK_VERSATILE select HAVE_TCM select ICST select GENERIC_CLOCKEVENTS select PLAT_VERSATILE select PLAT_VERSATILE_FPGA_IRQ - select NEED_MACH_IO_H select NEED_MACH_MEMORY_H select SPARSE_IRQ select MULTI_IRQ_HANDLER @@ -289,13 +286,12 @@ config ARCH_INTEGRATOR config ARCH_REALVIEW bool "ARM Ltd. RealView family" select ARM_AMBA - select CLKDEV_LOOKUP - select HAVE_MACH_CLKDEV + select COMMON_CLK + select COMMON_CLK_VERSATILE select ICST select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB select PLAT_VERSATILE - select PLAT_VERSATILE_CLOCK select PLAT_VERSATILE_CLCD select ARM_TIMER_SP804 select GPIO_PL061 if GPIOLIB @@ -312,7 +308,6 @@ config ARCH_VERSATILE select ICST select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB - select NEED_MACH_IO_H if PCI select PLAT_VERSATILE select PLAT_VERSATILE_CLOCK select PLAT_VERSATILE_CLCD @@ -321,64 +316,46 @@ config ARCH_VERSATILE help This enables support for ARM Ltd Versatile board. -config ARCH_VEXPRESS - bool "ARM Ltd. Versatile Express family" - select ARCH_WANT_OPTIONAL_GPIOLIB - select ARM_AMBA - select ARM_TIMER_SP804 - select CLKDEV_LOOKUP - select COMMON_CLK - select GENERIC_CLOCKEVENTS - select HAVE_CLK - select HAVE_PATA_PLATFORM - select ICST - select NO_IOPORT - select PLAT_VERSATILE - select PLAT_VERSATILE_CLCD - select REGULATOR_FIXED_VOLTAGE if REGULATOR - help - This enables support for the ARM Ltd Versatile Express boards. - config ARCH_AT91 bool "Atmel AT91" select ARCH_REQUIRE_GPIOLIB select HAVE_CLK select CLKDEV_LOOKUP select IRQ_DOMAIN + select NEED_MACH_GPIO_H select NEED_MACH_IO_H if PCCARD help This enables support for systems based on Atmel AT91RM9200 and AT91SAM9* processors. -config ARCH_BCMRING - bool "Broadcom BCMRING" - depends on MMU - select CPU_V6 +config ARCH_BCM2835 + bool "Broadcom BCM2835 family" + select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_AMBA + select ARM_ERRATA_411920 select ARM_TIMER_SP804 select CLKDEV_LOOKUP + select COMMON_CLK + select CPU_V6 select GENERIC_CLOCKEVENTS - select ARCH_WANT_OPTIONAL_GPIOLIB + select MULTI_IRQ_HANDLER + select SPARSE_IRQ + select USE_OF help - Support for Broadcom's BCMRing platform. + This enables support for the Broadcom BCM2835 SoC. This SoC is + use in the Raspberry Pi, and Roku 2 devices. -config ARCH_HIGHBANK - bool "Calxeda Highbank-based" - select ARCH_WANT_OPTIONAL_GPIOLIB +config ARCH_BCMRING + bool "Broadcom BCMRING" + depends on MMU + select CPU_V6 select ARM_AMBA - select ARM_GIC select ARM_TIMER_SP804 - select CACHE_L2X0 select CLKDEV_LOOKUP - select COMMON_CLK - select CPU_V7 select GENERIC_CLOCKEVENTS - select HAVE_ARM_SCU - select HAVE_SMP - select SPARSE_IRQ - select USE_OF + select ARCH_WANT_OPTIONAL_GPIOLIB help - Support for the Calxeda Highbank SoC based boards. + Support for Broadcom's BCMRing platform. config ARCH_CLPS711X bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" @@ -407,21 +384,19 @@ config ARCH_GEMINI help Support for the Cortina Systems Gemini family SoCs -config ARCH_PRIMA2 - bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" - select CPU_V7 +config ARCH_SIRF + bool "CSR SiRF" select NO_IOPORT select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select CLKDEV_LOOKUP + select COMMON_CLK select GENERIC_IRQ_CHIP select MIGHT_HAVE_CACHE_L2X0 select PINCTRL select PINCTRL_SIRF select USE_OF - select ZONE_DMA help - Support for CSR SiRFSoC ARM Cortex A9 Platform + Support for CSR SiRFprimaII/Marco/Polo platforms config ARCH_EBSA110 bool "EBSA-110" @@ -456,7 +431,7 @@ config ARCH_FOOTBRIDGE select FOOTBRIDGE select GENERIC_CLOCKEVENTS select HAVE_IDE - select NEED_MACH_IO_H + select NEED_MACH_IO_H if !MMU select NEED_MACH_MEMORY_H help Support for systems based on the DC21285 companion chip @@ -513,7 +488,6 @@ config ARCH_IOP13XX select PCI select ARCH_SUPPORTS_MSI select VMSPLIT_1G - select NEED_MACH_IO_H select NEED_MACH_MEMORY_H select NEED_RET_TO_USER help @@ -523,6 +497,7 @@ config ARCH_IOP32X bool "IOP32x-based" depends on MMU select CPU_XSCALE + select NEED_MACH_GPIO_H select NEED_MACH_IO_H select NEED_RET_TO_USER select PLAT_IOP @@ -536,6 +511,7 @@ config ARCH_IOP33X bool "IOP33x-based" depends on MMU select CPU_XSCALE + select NEED_MACH_GPIO_H select NEED_MACH_IO_H select NEED_RET_TO_USER select PLAT_IOP @@ -558,25 +534,12 @@ config ARCH_IXP4XX help Support for Intel's IXP4XX (XScale) family of processors. -config ARCH_MVEBU - bool "Marvell SOCs with Device Tree support" - select GENERIC_CLOCKEVENTS - select MULTI_IRQ_HANDLER - select SPARSE_IRQ - select CLKSRC_MMIO - select GENERIC_IRQ_CHIP - select IRQ_DOMAIN - select COMMON_CLK - help - Support for the Marvell SoC Family with device tree support - config ARCH_DOVE bool "Marvell Dove" select CPU_V7 select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select NEED_MACH_IO_H select PLAT_ORION help Support for the Marvell Dove SoC 88AP510 @@ -587,7 +550,6 @@ config ARCH_KIRKWOOD select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select NEED_MACH_IO_H select PLAT_ORION help Support for the following Marvell Kirkwood series SoCs: @@ -614,7 +576,6 @@ config ARCH_MV78XX0 select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select NEED_MACH_IO_H select PLAT_ORION help Support for the following Marvell MV78xx0 series SoCs: @@ -627,7 +588,6 @@ config ARCH_ORION5X select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select NEED_MACH_IO_H select PLAT_ORION help Support for the following Marvell Orion 5x series SoCs: @@ -645,6 +605,7 @@ config ARCH_MMP select PLAT_PXA select SPARSE_IRQ select GENERIC_ALLOCATOR + select NEED_MACH_GPIO_H help Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. @@ -652,8 +613,9 @@ config ARCH_KS8695 bool "Micrel/Kendin KS8695" select CPU_ARM922T select ARCH_REQUIRE_GPIOLIB - select ARCH_USES_GETTIMEOFFSET select NEED_MACH_MEMORY_H + select CLKSRC_MMIO + select GENERIC_CLOCKEVENTS help Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based System-on-Chip devices. @@ -683,40 +645,13 @@ config ARCH_TEGRA select HAVE_CLK select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 - select NEED_MACH_IO_H if PCI select ARCH_HAS_CPUFREQ select USE_OF + select COMMON_CLK help This enables support for NVIDIA Tegra based systems (Tegra APX, Tegra 6xx and Tegra 2 series). -config ARCH_PICOXCELL - bool "Picochip picoXcell" - select ARCH_REQUIRE_GPIOLIB - select ARM_PATCH_PHYS_VIRT - select ARM_VIC - select CPU_V6K - select DW_APB_TIMER - select DW_APB_TIMER_OF - select GENERIC_CLOCKEVENTS - select GENERIC_GPIO - select HAVE_TCM - select NO_IOPORT - select SPARSE_IRQ - select USE_OF - help - This enables support for systems based on the Picochip picoXcell - family of Femtocell devices. The picoxcell support requires device tree - for all boards. - -config ARCH_PNX4008 - bool "Philips Nexperia PNX4008 Mobile" - select CPU_ARM926T - select CLKDEV_LOOKUP - select ARCH_USES_GETTIMEOFFSET - help - This enables support for Philips PNX4008 mobile platform. - config ARCH_PXA bool "PXA2xx/PXA3xx-based" depends on MMU @@ -733,6 +668,7 @@ config ARCH_PXA select MULTI_IRQ_HANDLER select ARM_CPU_SUSPEND if PM select HAVE_IDE + select NEED_MACH_GPIO_H help Support for Intel/Marvell's PXA2xx/PXA3xx processor line. @@ -795,6 +731,7 @@ config ARCH_SA1100 select CLKDEV_LOOKUP select ARCH_REQUIRE_GPIOLIB select HAVE_IDE + select NEED_MACH_GPIO_H select NEED_MACH_MEMORY_H select SPARSE_IRQ help @@ -810,6 +747,7 @@ config ARCH_S3C24XX select HAVE_S3C2410_I2C if I2C select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C2410_WATCHDOG if WATCHDOG + select NEED_MACH_GPIO_H select NEED_MACH_IO_H help Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 @@ -837,6 +775,7 @@ config ARCH_S3C64XX select SAMSUNG_GPIOLIB_4BIT select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG + select NEED_MACH_GPIO_H help Samsung S3C64XX series based systems @@ -851,6 +790,7 @@ config ARCH_S5P64X0 select GENERIC_CLOCKEVENTS select HAVE_S3C2410_I2C if I2C select HAVE_S3C_RTC if RTC_CLASS + select NEED_MACH_GPIO_H help Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, SMDK6450. @@ -865,6 +805,7 @@ config ARCH_S5PC100 select HAVE_S3C2410_I2C if I2C select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C2410_WATCHDOG if WATCHDOG + select NEED_MACH_GPIO_H help Samsung S5PC100 series based systems @@ -882,6 +823,7 @@ config ARCH_S5PV210 select HAVE_S3C2410_I2C if I2C select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C2410_WATCHDOG if WATCHDOG + select NEED_MACH_GPIO_H select NEED_MACH_MEMORY_H help Samsung S5PV210/S5PC110 series based systems @@ -899,6 +841,7 @@ config ARCH_EXYNOS select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG + select NEED_MACH_GPIO_H select NEED_MACH_MEMORY_H help Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) @@ -912,7 +855,6 @@ config ARCH_SHARK select PCI select ARCH_USES_GETTIMEOFFSET select NEED_MACH_MEMORY_H - select NEED_MACH_IO_H help Support for the StrongARM based Digital DNARD machine, also known as "Shark" (). @@ -931,6 +873,7 @@ config ARCH_U300 select COMMON_CLK select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB + select SPARSE_IRQ help Support for ST-Ericsson U300 series mobile platforms. @@ -971,6 +914,7 @@ config ARCH_DAVINCI select GENERIC_ALLOCATOR select GENERIC_IRQ_CHIP select ARCH_HAS_HOLES_MEMORYMODEL + select NEED_MACH_GPIO_H help Support for TI's DaVinci platform. @@ -983,6 +927,7 @@ config ARCH_OMAP select CLKSRC_MMIO select GENERIC_CLOCKEVENTS select ARCH_HAS_HOLES_MEMORYMODEL + select NEED_MACH_GPIO_H help Support for TI's OMAP platform (OMAP1/2/3/4). @@ -1022,6 +967,50 @@ config ARCH_ZYNQ Support for Xilinx Zynq ARM Cortex A9 Platform endchoice +menu "Multiple platform selection" + depends on ARCH_MULTIPLATFORM + +comment "CPU Core family selection" + +config ARCH_MULTI_V4 + bool "ARMv4 based platforms (FA526, StrongARM)" + select ARCH_MULTI_V4_V5 + depends on !ARCH_MULTI_V6_V7 + +config ARCH_MULTI_V4T + bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" + select ARCH_MULTI_V4_V5 + depends on !ARCH_MULTI_V6_V7 + +config ARCH_MULTI_V5 + bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" + select ARCH_MULTI_V4_V5 + depends on !ARCH_MULTI_V6_V7 + +config ARCH_MULTI_V4_V5 + bool + +config ARCH_MULTI_V6 + bool "ARMv6 based platforms (ARM11, Scorpion, ...)" + select CPU_V6 + select ARCH_MULTI_V6_V7 + +config ARCH_MULTI_V7 + bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)" + select CPU_V7 + select ARCH_VEXPRESS + default y + select ARCH_MULTI_V6_V7 + +config ARCH_MULTI_V6_V7 + bool + +config ARCH_MULTI_CPU_AUTO + def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) + select ARCH_MULTI_V5 + +endmenu + # # This is sorted alphabetically by mach-* pathname. However, plat-* # Kconfigs may be included either alphabetically (according to the @@ -1049,6 +1038,8 @@ source "arch/arm/mach-gemini/Kconfig" source "arch/arm/mach-h720x/Kconfig" +source "arch/arm/mach-highbank/Kconfig" + source "arch/arm/mach-integrator/Kconfig" source "arch/arm/mach-iop32x/Kconfig" @@ -1084,6 +1075,8 @@ source "arch/arm/mach-omap2/Kconfig" source "arch/arm/mach-orion5x/Kconfig" +source "arch/arm/mach-picoxcell/Kconfig" + source "arch/arm/mach-pxa/Kconfig" source "arch/arm/plat-pxa/Kconfig" @@ -1096,6 +1089,8 @@ source "arch/arm/mach-sa1100/Kconfig" source "arch/arm/plat-samsung/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig" +source "arch/arm/mach-socfpga/Kconfig" + source "arch/arm/plat-spear/Kconfig" source "arch/arm/mach-s3c24xx/Kconfig" @@ -1118,6 +1113,8 @@ source "arch/arm/mach-exynos/Kconfig" source "arch/arm/mach-shmobile/Kconfig" +source "arch/arm/mach-prima2/Kconfig" + source "arch/arm/mach-tegra/Kconfig" source "arch/arm/mach-u300/Kconfig" @@ -1179,12 +1176,6 @@ config XSCALE_PMU depends on CPU_XSCALE default y -config CPU_HAS_PMU - depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ - (!ARCH_OMAP3 || OMAP3_EMU) - default y - bool - config MULTI_IRQ_HANDLER bool help @@ -1757,7 +1748,7 @@ config HIGHPTE config HW_PERF_EVENTS bool "Enable hardware performance counter support for perf events" - depends on PERF_EVENTS && CPU_HAS_PMU + depends on PERF_EVENTS default y help Enable hardware performance counter support for perf events. If @@ -2060,7 +2051,7 @@ endchoice config XIP_KERNEL bool "Kernel Execute-In-Place from ROM" - depends on !ZBOOT_ROM && !ARM_LPAE + depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM help Execute-In-Place allows the kernel to run from non-volatile storage directly addressable by the CPU, such as NOR flash. This saves RAM diff --git a/trunk/arch/arm/Kconfig.debug b/trunk/arch/arm/Kconfig.debug index e968a52e4881..a7eb28260b2e 100644 --- a/trunk/arch/arm/Kconfig.debug +++ b/trunk/arch/arm/Kconfig.debug @@ -261,6 +261,20 @@ choice Say Y here if you want the debug print routines to direct their output to the serial port on MSM 8960 devices. + config DEBUG_MVEBU_UART + bool "Kernel low-level debugging messages via MVEBU UART" + depends on ARCH_MVEBU + help + Say Y here if you want kernel low-level debugging support + on MVEBU based platforms. + + config DEBUG_PICOXCELL_UART + depends on ARCH_PICOXCELL + bool "Use PicoXcell UART for low-level debug" + help + Say Y here if you want kernel low-level debugging support + on PicoXcell based platforms. + config DEBUG_REALVIEW_STD_PORT bool "RealView Default UART" depends on ARCH_REALVIEW @@ -310,6 +324,13 @@ choice The uncompressor code port configuration is now handled by CONFIG_S3C_LOWLEVEL_UART_PORT. + config DEBUG_SOCFPGA_UART + depends on ARCH_SOCFPGA + bool "Use SOCFPGA UART for low-level debug" + help + Say Y here if you want kernel low-level debugging support + on SOCFPGA based platforms. + config DEBUG_VEXPRESS_UART0_DETECT bool "Autodetect UART0 on Versatile Express Cortex-A core tiles" depends on ARCH_VEXPRESS && CPU_CP15_MMU @@ -338,6 +359,7 @@ choice config DEBUG_LL_UART_NONE bool "No low-level debugging UART" + depends on !ARCH_MULTIPLATFORM help Say Y here if your platform doesn't provide a UART option below. This relies on your platform choosing the right UART @@ -373,6 +395,17 @@ choice endchoice +config DEBUG_LL_INCLUDE + string + default "debug/icedcc.S" if DEBUG_ICEDCC + default "debug/highbank.S" if DEBUG_HIGHBANK_UART + default "debug/mvebu.S" if DEBUG_MVEBU_UART + default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART + default "debug/socfpga.S" if DEBUG_SOCFPGA_UART + default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \ + DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 + default "mach/debug-macro.S" + config EARLY_PRINTK bool "Early printk" depends on DEBUG_LL diff --git a/trunk/arch/arm/Makefile b/trunk/arch/arm/Makefile index a051dfbdd7db..1c974cf9db1b 100644 --- a/trunk/arch/arm/Makefile +++ b/trunk/arch/arm/Makefile @@ -135,84 +135,79 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000 # Machine directory name. This list is sorted alphanumerically # by CONFIG_* macro name. -machine-$(CONFIG_ARCH_AT91) := at91 -machine-$(CONFIG_ARCH_BCMRING) := bcmring -machine-$(CONFIG_ARCH_CLPS711X) := clps711x -machine-$(CONFIG_ARCH_CNS3XXX) := cns3xxx -machine-$(CONFIG_ARCH_DAVINCI) := davinci -machine-$(CONFIG_ARCH_DOVE) := dove -machine-$(CONFIG_ARCH_EBSA110) := ebsa110 -machine-$(CONFIG_ARCH_EP93XX) := ep93xx -machine-$(CONFIG_ARCH_GEMINI) := gemini -machine-$(CONFIG_ARCH_H720X) := h720x -machine-$(CONFIG_ARCH_HIGHBANK) := highbank -machine-$(CONFIG_ARCH_INTEGRATOR) := integrator -machine-$(CONFIG_ARCH_IOP13XX) := iop13xx -machine-$(CONFIG_ARCH_IOP32X) := iop32x -machine-$(CONFIG_ARCH_IOP33X) := iop33x -machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx -machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood -machine-$(CONFIG_ARCH_KS8695) := ks8695 -machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx -machine-$(CONFIG_ARCH_MMP) := mmp -machine-$(CONFIG_ARCH_MSM) := msm -machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 -machine-$(CONFIG_ARCH_IMX_V4_V5) := imx -machine-$(CONFIG_ARCH_IMX_V6_V7) := imx -machine-$(CONFIG_ARCH_MXS) := mxs -machine-$(CONFIG_ARCH_MVEBU) := mvebu -machine-$(CONFIG_ARCH_NETX) := netx -machine-$(CONFIG_ARCH_NOMADIK) := nomadik -machine-$(CONFIG_ARCH_OMAP1) := omap1 -machine-$(CONFIG_ARCH_OMAP2PLUS) := omap2 -machine-$(CONFIG_ARCH_ORION5X) := orion5x -machine-$(CONFIG_ARCH_PICOXCELL) := picoxcell -machine-$(CONFIG_ARCH_PNX4008) := pnx4008 -machine-$(CONFIG_ARCH_PRIMA2) := prima2 -machine-$(CONFIG_ARCH_PXA) := pxa -machine-$(CONFIG_ARCH_REALVIEW) := realview -machine-$(CONFIG_ARCH_RPC) := rpc -machine-$(CONFIG_ARCH_S3C24XX) := s3c24xx s3c2412 s3c2440 -machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx -machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0 -machine-$(CONFIG_ARCH_S5PC100) := s5pc100 -machine-$(CONFIG_ARCH_S5PV210) := s5pv210 -machine-$(CONFIG_ARCH_EXYNOS4) := exynos -machine-$(CONFIG_ARCH_EXYNOS5) := exynos -machine-$(CONFIG_ARCH_SA1100) := sa1100 -machine-$(CONFIG_ARCH_SHARK) := shark -machine-$(CONFIG_ARCH_SHMOBILE) := shmobile -machine-$(CONFIG_ARCH_TEGRA) := tegra -machine-$(CONFIG_ARCH_U300) := u300 -machine-$(CONFIG_ARCH_U8500) := ux500 -machine-$(CONFIG_ARCH_VERSATILE) := versatile -machine-$(CONFIG_ARCH_VEXPRESS) := vexpress -machine-$(CONFIG_ARCH_VT8500) := vt8500 -machine-$(CONFIG_ARCH_W90X900) := w90x900 -machine-$(CONFIG_FOOTBRIDGE) := footbridge -machine-$(CONFIG_ARCH_SOCFPGA) := socfpga -machine-$(CONFIG_MACH_SPEAR1310) := spear13xx -machine-$(CONFIG_MACH_SPEAR1340) := spear13xx -machine-$(CONFIG_MACH_SPEAR300) := spear3xx -machine-$(CONFIG_MACH_SPEAR310) := spear3xx -machine-$(CONFIG_MACH_SPEAR320) := spear3xx -machine-$(CONFIG_MACH_SPEAR600) := spear6xx -machine-$(CONFIG_ARCH_ZYNQ) := zynq +machine-$(CONFIG_ARCH_AT91) += at91 +machine-$(CONFIG_ARCH_BCM2835) += bcm2835 +machine-$(CONFIG_ARCH_BCMRING) += bcmring +machine-$(CONFIG_ARCH_CLPS711X) += clps711x +machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx +machine-$(CONFIG_ARCH_DAVINCI) += davinci +machine-$(CONFIG_ARCH_DOVE) += dove +machine-$(CONFIG_ARCH_EBSA110) += ebsa110 +machine-$(CONFIG_ARCH_EP93XX) += ep93xx +machine-$(CONFIG_ARCH_GEMINI) += gemini +machine-$(CONFIG_ARCH_H720X) += h720x +machine-$(CONFIG_ARCH_HIGHBANK) += highbank +machine-$(CONFIG_ARCH_INTEGRATOR) += integrator +machine-$(CONFIG_ARCH_IOP13XX) += iop13xx +machine-$(CONFIG_ARCH_IOP32X) += iop32x +machine-$(CONFIG_ARCH_IOP33X) += iop33x +machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx +machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood +machine-$(CONFIG_ARCH_KS8695) += ks8695 +machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx +machine-$(CONFIG_ARCH_MMP) += mmp +machine-$(CONFIG_ARCH_MSM) += msm +machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 +machine-$(CONFIG_ARCH_MXC) += imx +machine-$(CONFIG_ARCH_MXS) += mxs +machine-$(CONFIG_ARCH_MVEBU) += mvebu +machine-$(CONFIG_ARCH_NETX) += netx +machine-$(CONFIG_ARCH_NOMADIK) += nomadik +machine-$(CONFIG_ARCH_OMAP1) += omap1 +machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 +machine-$(CONFIG_ARCH_ORION5X) += orion5x +machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell +machine-$(CONFIG_ARCH_PRIMA2) += prima2 +machine-$(CONFIG_ARCH_PXA) += pxa +machine-$(CONFIG_ARCH_REALVIEW) += realview +machine-$(CONFIG_ARCH_RPC) += rpc +machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx s3c2412 s3c2440 +machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx +machine-$(CONFIG_ARCH_S5P64X0) += s5p64x0 +machine-$(CONFIG_ARCH_S5PC100) += s5pc100 +machine-$(CONFIG_ARCH_S5PV210) += s5pv210 +machine-$(CONFIG_ARCH_EXYNOS) += exynos +machine-$(CONFIG_ARCH_SA1100) += sa1100 +machine-$(CONFIG_ARCH_SHARK) += shark +machine-$(CONFIG_ARCH_SHMOBILE) += shmobile +machine-$(CONFIG_ARCH_TEGRA) += tegra +machine-$(CONFIG_ARCH_U300) += u300 +machine-$(CONFIG_ARCH_U8500) += ux500 +machine-$(CONFIG_ARCH_VERSATILE) += versatile +machine-$(CONFIG_ARCH_VEXPRESS) += vexpress +machine-$(CONFIG_ARCH_VT8500) += vt8500 +machine-$(CONFIG_ARCH_W90X900) += w90x900 +machine-$(CONFIG_FOOTBRIDGE) += footbridge +machine-$(CONFIG_ARCH_SOCFPGA) += socfpga +machine-$(CONFIG_ARCH_SPEAR13XX) += spear13xx +machine-$(CONFIG_ARCH_SPEAR3XX) += spear3xx +machine-$(CONFIG_MACH_SPEAR600) += spear6xx +machine-$(CONFIG_ARCH_ZYNQ) += zynq # Platform directory name. This list is sorted alphanumerically # by CONFIG_* macro name. -plat-$(CONFIG_ARCH_MXC) := mxc -plat-$(CONFIG_ARCH_OMAP) := omap -plat-$(CONFIG_ARCH_S3C64XX) := samsung -plat-$(CONFIG_ARCH_ZYNQ) := versatile -plat-$(CONFIG_PLAT_IOP) := iop -plat-$(CONFIG_PLAT_NOMADIK) := nomadik -plat-$(CONFIG_PLAT_ORION) := orion -plat-$(CONFIG_PLAT_PXA) := pxa -plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx samsung -plat-$(CONFIG_PLAT_S5P) := samsung -plat-$(CONFIG_PLAT_SPEAR) := spear -plat-$(CONFIG_PLAT_VERSATILE) := versatile +plat-$(CONFIG_ARCH_MXC) += mxc +plat-$(CONFIG_ARCH_OMAP) += omap +plat-$(CONFIG_ARCH_S3C64XX) += samsung +plat-$(CONFIG_ARCH_ZYNQ) += versatile +plat-$(CONFIG_PLAT_IOP) += iop +plat-$(CONFIG_PLAT_NOMADIK) += nomadik +plat-$(CONFIG_PLAT_ORION) += orion +plat-$(CONFIG_PLAT_PXA) += pxa +plat-$(CONFIG_PLAT_S3C24XX) += s3c24xx samsung +plat-$(CONFIG_PLAT_S5P) += samsung +plat-$(CONFIG_PLAT_SPEAR) += spear +plat-$(CONFIG_PLAT_VERSATILE) += versatile ifeq ($(CONFIG_ARCH_EBSA110),y) # This is what happens if you forget the IOCS16 line. @@ -230,15 +225,20 @@ MACHINE := arch/arm/mach-$(word 1,$(machine-y))/ else MACHINE := endif +ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y) +MACHINE := +endif machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y)) +ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y) ifeq ($(KBUILD_SRC),) KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs)) else KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs)) endif +endif export TEXT_OFFSET GZFLAGS MMUEXT diff --git a/trunk/arch/arm/boot/Makefile b/trunk/arch/arm/boot/Makefile index c877087d2000..3fdab016aa5c 100644 --- a/trunk/arch/arm/boot/Makefile +++ b/trunk/arch/arm/boot/Makefile @@ -15,6 +15,8 @@ ifneq ($(MACHINE),) include $(srctree)/$(MACHINE)/Makefile.boot endif +include $(srctree)/arch/arm/boot/dts/Makefile + # Note: the following conditions must always be true: # ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET) # PARAMS_PHYS must be within 4MB of ZRELADDR diff --git a/trunk/arch/arm/boot/compressed/misc.c b/trunk/arch/arm/boot/compressed/misc.c index 8e2a8fca5ed2..df899834d84e 100644 --- a/trunk/arch/arm/boot/compressed/misc.c +++ b/trunk/arch/arm/boot/compressed/misc.c @@ -25,7 +25,13 @@ unsigned int __machine_arch_type; static void putstr(const char *ptr); extern void error(char *x); +#ifdef CONFIG_ARCH_MULTIPLATFORM +static inline void putc(int c) {} +static inline void flush(void) {} +static inline void arch_decomp_setup(void) {} +#else #include +#endif #ifdef CONFIG_DEBUG_ICEDCC diff --git a/trunk/arch/arm/boot/dts/Makefile b/trunk/arch/arm/boot/dts/Makefile new file mode 100644 index 000000000000..d302e6655e65 --- /dev/null +++ b/trunk/arch/arm/boot/dts/Makefile @@ -0,0 +1,100 @@ +ifeq ($(CONFIG_OF),y) + +dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \ + at91sam9263ek.dtb \ + at91sam9g20ek_2mmc.dtb \ + at91sam9g20ek.dtb \ + at91sam9g25ek.dtb \ + at91sam9m10g45ek.dtb \ + at91sam9n12ek.dtb \ + ethernut5.dtb \ + evk-pro3.dtb \ + kizbox.dtb \ + tny_a9260.dtb \ + tny_a9263.dtb \ + tny_a9g20.dtb \ + usb_a9260.dtb \ + usb_a9263.dtb \ + usb_a9g20.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb +dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ + exynos4210-smdkv310.dtb \ + exynos5250-smdk5250.dtb +dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb +dtb-$(CONFIG_ARCH_IMX5) += imx51-babbage.dtb \ + imx53-ard.dtb \ + imx53-evk.dtb \ + imx53-qsb.dtb \ + imx53-smd.dtb +dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \ + imx6q-sabrelite.dtb \ + imx6q-sabresd.dtb +dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb +dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \ + kirkwood-dns325.dtb \ + kirkwood-dreamplug.dtb \ + kirkwood-goflexnet.dtb \ + kirkwood-ib62x0.dtb \ + kirkwood-iconnect.dtb \ + kirkwood-lschlv2.dtb \ + kirkwood-lsxhl.dtb \ + kirkwood-ts219-6281.dtb \ + kirkwood-ts219-6282.dtb +dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \ + msm8960-cdp.dtb +dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ + armada-xp-db.dtb +dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \ + imx53-ard.dtb \ + imx53-evk.dtb \ + imx53-qsb.dtb \ + imx53-smd.dtb \ + imx6q-arm2.dtb \ + imx6q-sabrelite.dtb \ + imx6q-sabresd.dtb +dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ + imx23-olinuxino.dtb \ + imx23-stmp378x_devb.dtb \ + imx28-apx4devkit.dtb \ + imx28-cfa10036.dtb \ + imx28-cfa10049.dtb \ + imx28-evk.dtb \ + imx28-m28evk.dtb \ + imx28-tx28.dtb +dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ + omap3-beagle-xm.dtb \ + omap3-evm.dtb \ + omap3-tobi.dtb \ + omap4-panda.dtb \ + omap4-pandaES.dtb \ + omap4-var_som.dtb \ + omap4-sdp.dtb \ + omap5-evm.dtb +dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb +dtb-$(CONFIG_ARCH_U8500) += snowball.dtb +dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ + r8a7740-armadillo800eva.dtb \ + sh73a0-kzm9g.dtb +dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ + spear1340-evb.dtb +dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ + spear310-evb.dtb \ + spear320-evb.dtb +dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb +dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ + tegra20-medcom-wide.dtb \ + tegra20-paz00.dtb \ + tegra20-plutux.dtb \ + tegra20-seaboard.dtb \ + tegra20-tec.dtb \ + tegra20-trimslice.dtb \ + tegra20-ventana.dtb \ + tegra20-whistler.dtb \ + tegra30-cardhu-a02.dtb \ + tegra30-cardhu-a04.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ + vexpress-v2p-ca9.dtb \ + vexpress-v2p-ca15-tc1.dtb \ + vexpress-v2p-ca15_a7.dtb + +endif diff --git a/trunk/arch/arm/boot/dts/am335x-bone.dts b/trunk/arch/arm/boot/dts/am335x-bone.dts index a9af4db7234c..c634f87e230e 100644 --- a/trunk/arch/arm/boot/dts/am335x-bone.dts +++ b/trunk/arch/arm/boot/dts/am335x-bone.dts @@ -17,4 +17,64 @@ device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; + + ocp { + uart1: serial@44e09000 { + status = "okay"; + }; + + i2c1: i2c@44e0b000 { + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + + }; + }; +}; + +/include/ "tps65217.dtsi" + +&tps { + regulators { + dcdc1_reg: regulator@0 { + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-always-on; + }; + }; }; diff --git a/trunk/arch/arm/boot/dts/am335x-evm.dts b/trunk/arch/arm/boot/dts/am335x-evm.dts index d6a97d9eff72..185d6325a458 100644 --- a/trunk/arch/arm/boot/dts/am335x-evm.dts +++ b/trunk/arch/arm/boot/dts/am335x-evm.dts @@ -17,4 +17,104 @@ device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; + + ocp { + uart1: serial@44e09000 { + status = "okay"; + }; + + i2c1: i2c@44e0b000 { + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; + }; + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +/include/ "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-always-on; + }; + }; }; diff --git a/trunk/arch/arm/boot/dts/am33xx.dtsi b/trunk/arch/arm/boot/dts/am33xx.dtsi index bd0cff3f808c..bb31bff01998 100644 --- a/trunk/arch/arm/boot/dts/am33xx.dtsi +++ b/trunk/arch/arm/boot/dts/am33xx.dtsi @@ -69,95 +69,146 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; + reg = <0x44e07000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <96>; }; - gpio2: gpio@4804C000 { + gpio2: gpio@4804c000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; + reg = <0x4804c000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <98>; }; - gpio3: gpio@481AC000 { + gpio3: gpio@481ac000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; + reg = <0x481ac000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <32>; }; - gpio4: gpio@481AE000 { + gpio4: gpio@481ae000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; + reg = <0x481ae000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <62>; }; - uart1: serial@44E09000 { + uart1: serial@44e09000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart1"; clock-frequency = <48000000>; + reg = <0x44e09000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <72>; + status = "disabled"; }; uart2: serial@48022000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart2"; clock-frequency = <48000000>; + reg = <0x48022000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <73>; + status = "disabled"; }; uart3: serial@48024000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart3"; clock-frequency = <48000000>; + reg = <0x48024000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <74>; + status = "disabled"; }; - uart4: serial@481A6000 { + uart4: serial@481a6000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart4"; clock-frequency = <48000000>; + reg = <0x481a6000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <44>; + status = "disabled"; }; - uart5: serial@481A8000 { + uart5: serial@481a8000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart5"; clock-frequency = <48000000>; + reg = <0x481a8000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <45>; + status = "disabled"; }; - uart6: serial@481AA000 { + uart6: serial@481aa000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart6"; clock-frequency = <48000000>; + reg = <0x481aa000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <46>; + status = "disabled"; }; - i2c1: i2c@44E0B000 { + i2c1: i2c@44e0b000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; + reg = <0x44e0b000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <70>; + status = "disabled"; }; - i2c2: i2c@4802A000 { + i2c2: i2c@4802a000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; + reg = <0x4802a000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <71>; + status = "disabled"; }; - i2c3: i2c@4819C000 { + i2c3: i2c@4819c000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; + reg = <0x4819c000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <30>; + status = "disabled"; }; wdt2: wdt@44e35000 { compatible = "ti,omap3-wdt"; ti,hwmods = "wd_timer2"; + reg = <0x44e35000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <91>; }; }; }; diff --git a/trunk/arch/arm/boot/dts/bcm2835-rpi-b.dts b/trunk/arch/arm/boot/dts/bcm2835-rpi-b.dts new file mode 100644 index 000000000000..7dd860f83f96 --- /dev/null +++ b/trunk/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/memreserve/ 0x0c000000 0x04000000; +/include/ "bcm2835.dtsi" + +/ { + compatible = "raspberrypi,model-b", "brcm,bcm2835"; + model = "Raspberry Pi Model B"; + + memory { + reg = <0 0x10000000>; + }; +}; diff --git a/trunk/arch/arm/boot/dts/bcm2835.dtsi b/trunk/arch/arm/boot/dts/bcm2835.dtsi new file mode 100644 index 000000000000..0b619398532c --- /dev/null +++ b/trunk/arch/arm/boot/dts/bcm2835.dtsi @@ -0,0 +1,39 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "brcm,bcm2835"; + model = "BCM2835"; + interrupt-parent = <&intc>; + + chosen { + bootargs = "earlyprintk console=ttyAMA0"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x7e000000 0x20000000 0x02000000>; + + timer { + compatible = "brcm,bcm2835-system-timer"; + reg = <0x7e003000 0x1000>; + interrupts = <1 0>, <1 1>, <1 2>, <1 3>; + clock-frequency = <1000000>; + }; + + intc: interrupt-controller { + compatible = "brcm,bcm2835-armctrl-ic"; + reg = <0x7e00b200 0x200>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart@20201000 { + compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; + reg = <0x7e201000 0x1000>; + interrupts = <2 25>; + clock-frequency = <3000000>; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/ea3250.dts b/trunk/arch/arm/boot/dts/ea3250.dts index d79b28d9c963..a4ba31b23c88 100644 --- a/trunk/arch/arm/boot/dts/ea3250.dts +++ b/trunk/arch/arm/boot/dts/ea3250.dts @@ -166,9 +166,116 @@ #size-cells = <0>; autorepeat; button@21 { - label = "GPIO Key UP"; + label = "Interrupt Key"; linux,code = <103>; gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ }; + key1 { + label = "KEY1"; + linux,code = <1>; + gpios = <&pca9532 0 0>; + }; + key2 { + label = "KEY2"; + linux,code = <2>; + gpios = <&pca9532 1 0>; + }; + key3 { + label = "KEY3"; + linux,code = <3>; + gpios = <&pca9532 2 0>; + }; + key4 { + label = "KEY4"; + linux,code = <4>; + gpios = <&pca9532 3 0>; + }; + joy0 { + label = "Joystick Key 0"; + linux,code = <10>; + gpios = <&gpio 2 0 0>; /* P2.0 */ + }; + joy1 { + label = "Joystick Key 1"; + linux,code = <11>; + gpios = <&gpio 2 1 0>; /* P2.1 */ + }; + joy2 { + label = "Joystick Key 2"; + linux,code = <12>; + gpios = <&gpio 2 2 0>; /* P2.2 */ + }; + joy3 { + label = "Joystick Key 3"; + linux,code = <13>; + gpios = <&gpio 2 3 0>; /* P2.3 */ + }; + joy4 { + label = "Joystick Key 4"; + linux,code = <14>; + gpios = <&gpio 2 4 0>; /* P2.4 */ + }; + }; + + leds { + compatible = "gpio-leds"; + + /* LEDs on OEM Board */ + + led1 { + gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */ + linux,default-trigger = "timer"; + default-state = "off"; + }; + + led2 { + gpios = <&gpio 2 10 1>; /* P2.10, active low */ + default-state = "off"; + }; + + led3 { + gpios = <&gpio 2 11 1>; /* P2.11, active low */ + default-state = "off"; + }; + + led4 { + gpios = <&gpio 2 12 1>; /* P2.12, active low */ + default-state = "off"; + }; + + /* LEDs on Base Board */ + + lede1 { + gpios = <&pca9532 8 0>; + default-state = "off"; + }; + lede2 { + gpios = <&pca9532 9 0>; + default-state = "off"; + }; + lede3 { + gpios = <&pca9532 10 0>; + default-state = "off"; + }; + lede4 { + gpios = <&pca9532 11 0>; + default-state = "off"; + }; + lede5 { + gpios = <&pca9532 12 0>; + default-state = "off"; + }; + lede6 { + gpios = <&pca9532 13 0>; + default-state = "off"; + }; + lede7 { + gpios = <&pca9532 14 0>; + default-state = "off"; + }; + lede8 { + gpios = <&pca9532 15 0>; + default-state = "off"; + }; }; }; diff --git a/trunk/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/trunk/arch/arm/boot/dts/elpida_ecb240abacn.dtsi new file mode 100644 index 000000000000..f97f70f83374 --- /dev/null +++ b/trunk/arch/arm/boot/dts/elpida_ecb240abacn.dtsi @@ -0,0 +1,67 @@ +/* + * Common devices used in different OMAP boards + */ + +/ { + elpida_ECB240ABACN: lpddr2 { + compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; + density = <2048>; + io-width = <32>; + + tRPab-min-tck = <3>; + tRCD-min-tck = <3>; + tWR-min-tck = <3>; + tRASmin-min-tck = <3>; + tRRD-min-tck = <2>; + tWTR-min-tck = <2>; + tXP-min-tck = <2>; + tRTP-min-tck = <2>; + tCKE-min-tck = <3>; + tCKESR-min-tck = <3>; + tFAW-min-tck = <8>; + + timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + tDQSCK-max-derated = <6000>; + }; + + timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <200000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <10000>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + tDQSCK-max-derated = <6000>; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/imx23-evk.dts b/trunk/arch/arm/boot/dts/imx23-evk.dts index e3486f486b40..035c13f9d3c0 100644 --- a/trunk/arch/arm/boot/dts/imx23-evk.dts +++ b/trunk/arch/arm/boot/dts/imx23-evk.dts @@ -42,12 +42,13 @@ pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */ 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ + 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ >; fsl,drive-strength = <0>; fsl,voltage = <1>; diff --git a/trunk/arch/arm/boot/dts/imx23-olinuxino.dts b/trunk/arch/arm/boot/dts/imx23-olinuxino.dts index 20912b1d8893..384d8b66f337 100644 --- a/trunk/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/trunk/arch/arm/boot/dts/imx23-olinuxino.dts @@ -31,6 +31,22 @@ bus-width = <4>; status = "okay"; }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */ + 0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; }; apbx@80040000 { @@ -39,6 +55,47 @@ pinctrl-0 = <&duart_pins_a>; status = "okay"; }; + + auart0: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; + }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + vbus-supply = <®_usb0_vbus>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_usb0_vbus: usb0_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */ + gpio = <&gpio0 17 0>; + }; + }; + + leds { + compatible = "gpio-leds"; + + user { + label = "green"; + gpios = <&gpio2 1 0>; + linux,default-trigger = "default-on"; }; }; }; diff --git a/trunk/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/trunk/arch/arm/boot/dts/imx23-stmp378x_devb.dts index 757a327ff3e8..85c3864b6a56 100644 --- a/trunk/arch/arm/boot/dts/imx23-stmp378x_devb.dts +++ b/trunk/arch/arm/boot/dts/imx23-stmp378x_devb.dts @@ -36,7 +36,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ diff --git a/trunk/arch/arm/boot/dts/imx23.dtsi b/trunk/arch/arm/boot/dts/imx23.dtsi index e6138310e5ce..3f3b6fc229b3 100644 --- a/trunk/arch/arm/boot/dts/imx23.dtsi +++ b/trunk/arch/arm/boot/dts/imx23.dtsi @@ -52,6 +52,7 @@ dma-apbh@80004000 { compatible = "fsl,imx23-dma-apbh"; reg = <0x80004000 0x2000>; + clocks = <&clks 15>; }; ecc@80008000 { @@ -67,6 +68,7 @@ reg-names = "gpmi-nand", "bch"; interrupts = <13>, <56>; interrupt-names = "gpmi-dma", "bch"; + clocks = <&clks 34>; fsl,gpmi-dma-channel = <4>; status = "disabled"; }; @@ -74,6 +76,7 @@ ssp0: ssp@80010000 { reg = <0x80010000 0x2000>; interrupts = <15 14>; + clocks = <&clks 33>; fsl,ssp-dma-channel = <1>; status = "disabled"; }; @@ -140,6 +143,17 @@ fsl,pull-up = <0>; }; + auart0_2pins_a: auart0-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */ + 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + gpmi_pins_a: gpmi-nand@0 { reg = <0>; fsl,pinmux-ids = < @@ -183,7 +197,6 @@ 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ - 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ >; fsl,drive-strength = <1>; @@ -280,6 +293,7 @@ dma-apbx@80024000 { compatible = "fsl,imx23-dma-apbx"; reg = <0x80024000 0x2000>; + clocks = <&clks 16>; }; dcp@80028000 { @@ -306,12 +320,14 @@ compatible = "fsl,imx23-lcdif"; reg = <0x80030000 2000>; interrupts = <46 45>; + clocks = <&clks 38>; status = "disabled"; }; ssp1: ssp@80034000 { reg = <0x80034000 0x2000>; interrupts = <2 20>; + clocks = <&clks 33>; fsl,ssp-dma-channel = <2>; status = "disabled"; }; @@ -329,9 +345,10 @@ reg = <0x80040000 0x40000>; ranges; - clkctl@80040000 { + clks: clkctrl@80040000 { + compatible = "fsl,imx23-clkctrl"; reg = <0x80040000 0x2000>; - status = "disabled"; + #clock-cells = <1>; }; saif0: saif@80042000 { @@ -383,6 +400,7 @@ pwm: pwm@80064000 { compatible = "fsl,imx23-pwm"; reg = <0x80064000 0x2000>; + clocks = <&clks 30>; #pwm-cells = <2>; fsl,pwm-number = <5>; status = "disabled"; @@ -397,6 +415,7 @@ compatible = "fsl,imx23-auart"; reg = <0x8006c000 0x2000>; interrupts = <24 25 23>; + clocks = <&clks 32>; status = "disabled"; }; @@ -404,6 +423,7 @@ compatible = "fsl,imx23-auart"; reg = <0x8006e000 0x2000>; interrupts = <59 60 58>; + clocks = <&clks 32>; status = "disabled"; }; @@ -411,11 +431,15 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x80070000 0x2000>; interrupts = <0>; + clocks = <&clks 32>, <&clks 16>; + clock-names = "uart", "apb_pclk"; status = "disabled"; }; - usbphy@8007c000 { + usbphy0: usbphy@8007c000 { + compatible = "fsl,imx23-usbphy"; reg = <0x8007c000 0x2000>; + clocks = <&clks 41>; status = "disabled"; }; }; @@ -428,8 +452,12 @@ reg = <0x80080000 0x80000>; ranges; - usbctrl@80080000 { + usb0: usb@80080000 { + compatible = "fsl,imx23-usb", "fsl,imx27-usb"; reg = <0x80080000 0x40000>; + interrupts = <11>; + fsl,usbphy = <&usbphy0>; + clocks = <&clks 40>; status = "disabled"; }; }; diff --git a/trunk/arch/arm/boot/dts/imx27-phytec-phycore.dts b/trunk/arch/arm/boot/dts/imx27-phytec-phycore.dts index 2b0ff60247a4..af50469e34b2 100644 --- a/trunk/arch/arm/boot/dts/imx27-phytec-phycore.dts +++ b/trunk/arch/arm/boot/dts/imx27-phytec-phycore.dts @@ -23,10 +23,6 @@ soc { aipi@10000000 { /* aipi */ - wdog@10002000 { - status = "okay"; - }; - serial@1000a000 { fsl,uart-has-rtscts; status = "okay"; @@ -49,7 +45,7 @@ i2c@1001d000 { clock-frequency = <400000>; status = "okay"; - at24@4c { + at24@52 { compatible = "at,24c32"; pagesize = <32>; reg = <0x52>; diff --git a/trunk/arch/arm/boot/dts/imx27.dtsi b/trunk/arch/arm/boot/dts/imx27.dtsi index 5303ab680a34..3e54f1498841 100644 --- a/trunk/arch/arm/boot/dts/imx27.dtsi +++ b/trunk/arch/arm/boot/dts/imx27.dtsi @@ -62,7 +62,6 @@ compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; reg = <0x10002000 0x4000>; interrupts = <27>; - status = "disabled"; }; uart1: serial@1000a000 { diff --git a/trunk/arch/arm/boot/dts/imx28-apx4devkit.dts b/trunk/arch/arm/boot/dts/imx28-apx4devkit.dts index b383417a558f..5171667a7763 100644 --- a/trunk/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/trunk/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -37,7 +37,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ diff --git a/trunk/arch/arm/boot/dts/imx28-cfa10049.dts b/trunk/arch/arm/boot/dts/imx28-cfa10049.dts new file mode 100644 index 000000000000..05c892e931e3 --- /dev/null +++ b/trunk/arch/arm/boot/dts/imx28-cfa10049.dts @@ -0,0 +1,99 @@ +/* + * Copyright 2012 Free Electrons + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * The CFA-10049 is an expansion board for the CFA-10036 module, thus we + * need to include the CFA-10036 DTS. + */ +/include/ "imx28-cfa10036.dts" + +/ { + model = "Crystalfontz CFA-10049 Board"; + compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28"; + + apb@80000000 { + apbh@80000000 { + pinctrl@80018000 { + spi3_pins_cfa10049: spi3-cfa10049@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */ + 0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */ + 0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */ + 0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + }; + + ssp3: ssp@80016000 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins_cfa10049>; + status = "okay"; + + gpio5: gpio5@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <2>; + spi-max-frequency = <100000>; + }; + + gpio6: gpio6@1 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <1>; + registers-number = <4>; + spi-max-frequency = <100000>; + }; + + }; + }; + + apbx@80040000 { + i2c1: i2c@8005a000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + + usbphy1: usbphy@8007e000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb1: usb@80090000 { + vbus-supply = <®_usb1_vbus>; + pinctrl-0 = <&usbphy1_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_usb1_vbus: usb1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 7 1>; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/imx28-evk.dts b/trunk/arch/arm/boot/dts/imx28-evk.dts index 773c0e84d1fb..a0ad71ca3a44 100644 --- a/trunk/arch/arm/boot/dts/imx28-evk.dts +++ b/trunk/arch/arm/boot/dts/imx28-evk.dts @@ -46,11 +46,28 @@ wp-gpios = <&gpio0 28 0>; }; + ssp2: ssp@80014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf016b"; + spi-max-frequency = <40000000>; + reg = <0>; + }; + }; + pinctrl@80018000 { pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */ @@ -128,6 +145,10 @@ status = "okay"; }; + lradc@80050000 { + status = "okay"; + }; + i2c0: i2c@80058000 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -140,6 +161,12 @@ VDDIO-supply = <®_3p3v>; }; + + at24@51 { + compatible = "at24,24c32"; + pagesize = <32>; + reg = <0x51>; + }; }; pwm: pwm@80064000 { diff --git a/trunk/arch/arm/boot/dts/imx28-m28evk.dts b/trunk/arch/arm/boot/dts/imx28-m28evk.dts index 183a3fd2d859..3bab6b00c52d 100644 --- a/trunk/arch/arm/boot/dts/imx28-m28evk.dts +++ b/trunk/arch/arm/boot/dts/imx28-m28evk.dts @@ -23,6 +23,8 @@ apb@80000000 { apbh@80000000 { gpmi-nand@8000c000 { + #address-cells = <1>; + #size-cells = <1>; pinctrl-names = "default"; pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; status = "okay"; @@ -61,19 +63,40 @@ &mmc0_cd_cfg &mmc0_sck_cfg>; bus-width = <8>; - wp-gpios = <&gpio3 10 1>; + wp-gpios = <&gpio3 10 0>; + vmmc-supply = <®_vddio_sd0>; status = "okay"; }; + ssp2: ssp@80014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + spi-max-frequency = <40000000>; + reg = <0>; + }; + }; + pinctrl@80018000 { pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < + 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */ 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */ + 0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */ + 0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */ >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -129,6 +152,7 @@ i2c0: i2c@80058000 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; + clock-frequency = <400000>; status = "okay"; sgtl5000: codec@0a { @@ -151,32 +175,51 @@ }; }; + lradc@80050000 { + status = "okay"; + }; + duart: serial@80074000 { pinctrl-names = "default"; pinctrl-0 = <&duart_pins_a>; status = "okay"; }; - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; + usbphy0: usbphy@8007c000 { status = "okay"; }; - auart3: serial@80070000 { + usbphy1: usbphy@8007e000 { + status = "okay"; + }; + + auart0: serial@8006a000 { pinctrl-names = "default"; - pinctrl-0 = <&auart3_pins_a>; + pinctrl-0 = <&auart0_2pins_a>; status = "okay"; }; }; }; ahb@80080000 { + usb0: usb@80080000 { + vbus-supply = <®_usb0_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&usbphy0_pins_a>; + status = "okay"; + }; + + usb1: usb@80090000 { + vbus-supply = <®_usb1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&usbphy1_pins_a>; + status = "okay"; + }; + mac0: ethernet@800f0000 { phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio3 11 0>; status = "okay"; }; @@ -198,6 +241,30 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + reg_vddio_sd0: vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 28 0>; + }; + + reg_usb0_vbus: usb0_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 12 0>; + }; + + reg_usb1_vbus: usb1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 13 0>; + }; }; sound { diff --git a/trunk/arch/arm/boot/dts/imx28-tx28.dts b/trunk/arch/arm/boot/dts/imx28-tx28.dts index 62bf767409a6..37be532f0055 100644 --- a/trunk/arch/arm/boot/dts/imx28-tx28.dts +++ b/trunk/arch/arm/boot/dts/imx28-tx28.dts @@ -25,7 +25,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */ @@ -34,6 +34,24 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; + + mac0_pins_gpio: mac0-gpio-mode@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */ + 0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */ + 0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */ + 0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */ + 0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */ + 0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */ + 0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */ + 0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */ + 0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; }; }; @@ -72,8 +90,9 @@ ahb@80080000 { mac0: ethernet@800f0000 { phy-mode = "rmii"; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio_mode"; pinctrl-0 = <&mac0_pins_a>; + pinctrl-1 = <&mac0_pins_gpio>; status = "okay"; }; }; diff --git a/trunk/arch/arm/boot/dts/imx28.dtsi b/trunk/arch/arm/boot/dts/imx28.dtsi index 3fa6d190fab4..724147eab84b 100644 --- a/trunk/arch/arm/boot/dts/imx28.dtsi +++ b/trunk/arch/arm/boot/dts/imx28.dtsi @@ -27,6 +27,8 @@ serial2 = &auart2; serial3 = &auart3; serial4 = &auart4; + ethernet0 = &mac0; + ethernet1 = &mac1; }; cpus { @@ -65,6 +67,7 @@ dma-apbh@80004000 { compatible = "fsl,imx28-dma-apbh"; reg = <0x80004000 0x2000>; + clocks = <&clks 25>; }; perfmon@80006000 { @@ -81,34 +84,47 @@ reg-names = "gpmi-nand", "bch"; interrupts = <88>, <41>; interrupt-names = "gpmi-dma", "bch"; + clocks = <&clks 50>; fsl,gpmi-dma-channel = <4>; status = "disabled"; }; ssp0: ssp@80010000 { + #address-cells = <1>; + #size-cells = <0>; reg = <0x80010000 0x2000>; interrupts = <96 82>; + clocks = <&clks 46>; fsl,ssp-dma-channel = <0>; status = "disabled"; }; ssp1: ssp@80012000 { + #address-cells = <1>; + #size-cells = <0>; reg = <0x80012000 0x2000>; interrupts = <97 83>; + clocks = <&clks 47>; fsl,ssp-dma-channel = <1>; status = "disabled"; }; ssp2: ssp@80014000 { + #address-cells = <1>; + #size-cells = <0>; reg = <0x80014000 0x2000>; interrupts = <98 84>; + clocks = <&clks 48>; fsl,ssp-dma-channel = <2>; status = "disabled"; }; ssp3: ssp@80016000 { + #address-cells = <1>; + #size-cells = <0>; reg = <0x80016000 0x2000>; interrupts = <99 85>; + clocks = <&clks 49>; fsl,ssp-dma-channel = <3>; status = "disabled"; }; @@ -410,6 +426,28 @@ fsl,pull-up = <1>; }; + i2c0_pins_b: i2c0@1 { + reg = <1>; + fsl,pinmux-ids = < + 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */ + 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + i2c1_pins_a: i2c1@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */ + 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + saif0_pins_a: saif0@0 { reg = <0>; fsl,pinmux-ids = < @@ -453,6 +491,16 @@ fsl,pull-up = <0>; }; + pwm4_pins_a: pwm4@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x31d0 /* MX28_PAD_PWM4__PWM_4 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + lcdif_24bit_pins_a: lcdif-24bit@0 { reg = <0>; fsl,pinmux-ids = < @@ -507,6 +555,49 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; + + spi2_pins_a: spi2@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */ + 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */ + 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */ + 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + usbphy0_pins_a: usbphy0@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */ + >; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + usbphy0_pins_b: usbphy0@1 { + reg = <1>; + fsl,pinmux-ids = < + 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */ + >; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + usbphy1_pins_a: usbphy1@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */ + >; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; }; digctl@8001c000 { @@ -523,6 +614,7 @@ dma-apbx@80024000 { compatible = "fsl,imx28-dma-apbx"; reg = <0x80024000 0x2000>; + clocks = <&clks 26>; }; dcp@80028000 { @@ -551,6 +643,7 @@ compatible = "fsl,imx28-lcdif"; reg = <0x80030000 0x2000>; interrupts = <38 86>; + clocks = <&clks 55>; status = "disabled"; }; @@ -558,6 +651,8 @@ compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; reg = <0x80032000 0x2000>; interrupts = <8>; + clocks = <&clks 58>, <&clks 58>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -565,6 +660,8 @@ compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; reg = <0x80034000 0x2000>; interrupts = <9>; + clocks = <&clks 59>, <&clks 59>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -611,15 +708,17 @@ reg = <0x80040000 0x40000>; ranges; - clkctl@80040000 { + clks: clkctrl@80040000 { + compatible = "fsl,imx28-clkctrl"; reg = <0x80040000 0x2000>; - status = "disabled"; + #clock-cells = <1>; }; saif0: saif@80042000 { compatible = "fsl,imx28-saif"; reg = <0x80042000 0x2000>; interrupts = <59 80>; + clocks = <&clks 53>; fsl,saif-dma-channel = <4>; status = "disabled"; }; @@ -633,12 +732,16 @@ compatible = "fsl,imx28-saif"; reg = <0x80046000 0x2000>; interrupts = <58 81>; + clocks = <&clks 54>; fsl,saif-dma-channel = <5>; status = "disabled"; }; lradc@80050000 { + compatible = "fsl,imx28-lradc"; reg = <0x80050000 0x2000>; + interrupts = <10 14 15 16 17 18 19 + 20 21 22 23 24 25>; status = "disabled"; }; @@ -677,6 +780,7 @@ pwm: pwm@80064000 { compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; reg = <0x80064000 0x2000>; + clocks = <&clks 44>; #pwm-cells = <2>; fsl,pwm-number = <8>; status = "disabled"; @@ -691,6 +795,7 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006a000 0x2000>; interrupts = <112 70 71>; + clocks = <&clks 45>; status = "disabled"; }; @@ -698,6 +803,7 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006c000 0x2000>; interrupts = <113 72 73>; + clocks = <&clks 45>; status = "disabled"; }; @@ -705,6 +811,7 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006e000 0x2000>; interrupts = <114 74 75>; + clocks = <&clks 45>; status = "disabled"; }; @@ -712,6 +819,7 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x80070000 0x2000>; interrupts = <115 76 77>; + clocks = <&clks 45>; status = "disabled"; }; @@ -719,6 +827,7 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x80072000 0x2000>; interrupts = <116 78 79>; + clocks = <&clks 45>; status = "disabled"; }; @@ -726,18 +835,22 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x80074000 0x1000>; interrupts = <47>; + clocks = <&clks 45>, <&clks 26>; + clock-names = "uart", "apb_pclk"; status = "disabled"; }; usbphy0: usbphy@8007c000 { compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; reg = <0x8007c000 0x2000>; + clocks = <&clks 62>; status = "disabled"; }; usbphy1: usbphy@8007e000 { compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; reg = <0x8007e000 0x2000>; + clocks = <&clks 63>; status = "disabled"; }; }; @@ -754,6 +867,7 @@ compatible = "fsl,imx28-usb", "fsl,imx27-usb"; reg = <0x80080000 0x10000>; interrupts = <93>; + clocks = <&clks 60>; fsl,usbphy = <&usbphy0>; status = "disabled"; }; @@ -762,6 +876,7 @@ compatible = "fsl,imx28-usb", "fsl,imx27-usb"; reg = <0x80090000 0x10000>; interrupts = <92>; + clocks = <&clks 61>; fsl,usbphy = <&usbphy1>; status = "disabled"; }; @@ -775,6 +890,8 @@ compatible = "fsl,imx28-fec"; reg = <0x800f0000 0x4000>; interrupts = <101>; + clocks = <&clks 57>, <&clks 57>; + clock-names = "ipg", "ahb"; status = "disabled"; }; @@ -782,6 +899,8 @@ compatible = "fsl,imx28-fec"; reg = <0x800f4000 0x4000>; interrupts = <102>; + clocks = <&clks 57>, <&clks 57>; + clock-names = "ipg", "ahb"; status = "disabled"; }; diff --git a/trunk/arch/arm/boot/dts/imx51-babbage.dts b/trunk/arch/arm/boot/dts/imx51-babbage.dts index 59d9789e5508..cbd2b1c7487b 100644 --- a/trunk/arch/arm/boot/dts/imx51-babbage.dts +++ b/trunk/arch/arm/boot/dts/imx51-babbage.dts @@ -25,23 +25,31 @@ aips@70000000 { /* aips-1 */ spba@70000000 { esdhc@70004000 { /* ESDHC1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1_1>; fsl,cd-controller; fsl,wp-controller; status = "okay"; }; esdhc@70008000 { /* ESDHC2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2_1>; cd-gpios = <&gpio1 6 0>; wp-gpios = <&gpio1 5 0>; status = "okay"; }; uart3: serial@7000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; fsl,uart-has-rtscts; status = "okay"; }; ecspi@70010000 { /* ECSPI1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; status = "okay"; @@ -169,31 +177,43 @@ }; }; - wdog@73f98000 { /* WDOG1 */ - status = "okay"; - }; - iomuxc@73fa8000 { - compatible = "fsl,imx51-iomuxc-babbage"; - reg = <0x73fa8000 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */ + 697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */ + 737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */ + 740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */ + 121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */ + 402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */ + 405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */ + >; + }; + }; }; uart1: serial@73fbc000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; fsl,uart-has-rtscts; status = "okay"; }; uart2: serial@73fc0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; status = "okay"; }; }; aips@80000000 { /* aips-2 */ - sdma@83fb0000 { - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; - }; - i2c@83fc4000 { /* I2C2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_1>; status = "okay"; sgtl5000: codec@0a { @@ -206,10 +226,14 @@ }; audmux@83fd0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_1>; status = "okay"; }; ethernet@83fec000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_1>; phy-mode = "mii"; status = "okay"; }; diff --git a/trunk/arch/arm/boot/dts/imx51.dtsi b/trunk/arch/arm/boot/dts/imx51.dtsi index aba28dc87fc8..2f71a91ca98e 100644 --- a/trunk/arch/arm/boot/dts/imx51.dtsi +++ b/trunk/arch/arm/boot/dts/imx51.dtsi @@ -130,6 +130,34 @@ }; }; + usb@73f80000 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80000 0x0200>; + interrupts = <18>; + status = "disabled"; + }; + + usb@73f80200 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80200 0x0200>; + interrupts = <14>; + status = "disabled"; + }; + + usb@73f80400 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80400 0x0200>; + interrupts = <16>; + status = "disabled"; + }; + + usb@73f80600 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80600 0x0200>; + interrupts = <17>; + status = "disabled"; + }; + gpio1: gpio@73f84000 { compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; reg = <0x73f84000 0x4000>; @@ -174,7 +202,6 @@ compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f98000 0x4000>; interrupts = <58>; - status = "disabled"; }; wdog@73f9c000 { /* WDOG2 */ @@ -184,6 +211,122 @@ status = "disabled"; }; + iomuxc@73fa8000 { + compatible = "fsl,imx51-iomuxc"; + reg = <0x73fa8000 0x4000>; + + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */ + 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */ + 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */ + 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */ + >; + }; + }; + + fec { + pinctrl_fec_1: fecgrp-1 { + fsl,pins = < + 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */ + 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */ + 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */ + 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */ + 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */ + 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */ + 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */ + 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */ + 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */ + 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */ + 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */ + 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */ + 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */ + 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */ + 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */ + 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */ + 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */ + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */ + 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */ + 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */ + >; + }; + }; + + esdhc1 { + pinctrl_esdhc1_1: esdhc1grp-1 { + fsl,pins = < + 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */ + 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */ + 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */ + 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */ + 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */ + 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */ + >; + }; + }; + + esdhc2 { + pinctrl_esdhc2_1: esdhc2grp-1 { + fsl,pins = < + 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */ + 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */ + 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */ + 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */ + 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */ + 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */ + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */ + 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */ + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */ + 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */ + 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */ + 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */ + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */ + 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */ + >; + }; + }; + + uart3 { + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */ + 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */ + 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */ + 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */ + >; + }; + }; + }; + uart1: serial@73fbc000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fbc000 0x4000>; @@ -219,6 +362,7 @@ compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; reg = <0x83fb0000 0x4000>; interrupts = <6>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; }; cspi@83fc0000 { diff --git a/trunk/arch/arm/boot/dts/imx53-ard.dts b/trunk/arch/arm/boot/dts/imx53-ard.dts index da895e93a999..4be76f223526 100644 --- a/trunk/arch/arm/boot/dts/imx53-ard.dts +++ b/trunk/arch/arm/boot/dts/imx53-ard.dts @@ -25,31 +25,66 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1_2>; cd-gpios = <&gpio1 1 0>; wp-gpios = <&gpio1 9 0>; status = "okay"; }; }; - wdog@53f98000 { /* WDOG1 */ - status = "okay"; - }; - iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc-ard"; - reg = <0x53fa8000 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */ + 1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */ + 486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */ + 739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */ + 218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */ + 226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */ + 233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */ + 241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */ + 429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */ + 435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */ + 441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */ + 448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */ + 456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */ + 464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */ + 471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */ + 477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */ + 492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */ + 500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */ + 508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */ + 516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */ + 524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */ + 532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */ + 540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */ + 548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */ + 637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */ + 642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */ + 647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */ + 652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */ + 657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */ + 662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */ + 667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */ + 611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */ + 616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */ + 607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */ + >; + }; + }; }; uart1: serial@53fbc000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_2>; status = "okay"; }; }; - - aips@60000000 { /* AIPS2 */ - sdma@63fb0000 { - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; - }; - }; }; eim-cs1@f4000000 { diff --git a/trunk/arch/arm/boot/dts/imx53-evk.dts b/trunk/arch/arm/boot/dts/imx53-evk.dts index 9c798034675e..a124d1e25258 100644 --- a/trunk/arch/arm/boot/dts/imx53-evk.dts +++ b/trunk/arch/arm/boot/dts/imx53-evk.dts @@ -25,12 +25,16 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1_1>; cd-gpios = <&gpio3 13 0>; wp-gpios = <&gpio3 14 0>; status = "okay"; }; ecspi@50010000 { /* ECSPI1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; status = "okay"; @@ -56,32 +60,45 @@ }; esdhc@50020000 { /* ESDHC3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3_1>; cd-gpios = <&gpio3 11 0>; wp-gpios = <&gpio3 12 0>; status = "okay"; }; }; - wdog@53f98000 { /* WDOG1 */ - status = "okay"; - }; - iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc-evk"; - reg = <0x53fa8000 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */ + 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */ + 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */ + 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ + 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ + 705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */ + 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ + 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */ + >; + }; + }; }; uart1: serial@53fbc000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; status = "okay"; }; }; aips@60000000 { /* AIPS2 */ - sdma@63fb0000 { - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; - }; - i2c@63fc4000 { /* I2C2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_1>; status = "okay"; pmic: mc13892@08 { @@ -96,6 +113,8 @@ }; ethernet@63fec000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_1>; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 0>; status = "okay"; diff --git a/trunk/arch/arm/boot/dts/imx53-qsb.dts b/trunk/arch/arm/boot/dts/imx53-qsb.dts index 2d803a9a6949..08948af86d1a 100644 --- a/trunk/arch/arm/boot/dts/imx53-qsb.dts +++ b/trunk/arch/arm/boot/dts/imx53-qsb.dts @@ -25,6 +25,8 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1_1>; cd-gpios = <&gpio3 13 0>; status = "okay"; }; @@ -35,32 +37,46 @@ }; esdhc@50020000 { /* ESDHC3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3_1>; cd-gpios = <&gpio3 11 0>; wp-gpios = <&gpio3 12 0>; status = "okay"; }; }; - wdog@53f98000 { /* WDOG1 */ - status = "okay"; - }; - iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc-qsb"; - reg = <0x53fa8000 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */ + 1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */ + 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */ + 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */ + 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */ + 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ + 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ + 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ + 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */ + >; + }; + }; }; uart1: serial@53fbc000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; status = "okay"; }; }; aips@60000000 { /* AIPS2 */ - sdma@63fb0000 { - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; - }; - i2c@63fc4000 { /* I2C2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_1>; status = "okay"; sgtl5000: codec@0a { @@ -72,6 +88,8 @@ }; i2c@63fc8000 { /* I2C1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; status = "okay"; accelerometer: mma8450@1c { @@ -158,10 +176,14 @@ }; audmux@63fd0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_1>; status = "okay"; }; ethernet@63fec000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_1>; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 0>; status = "okay"; diff --git a/trunk/arch/arm/boot/dts/imx53-smd.dts b/trunk/arch/arm/boot/dts/imx53-smd.dts index 08091029168e..06c68580c842 100644 --- a/trunk/arch/arm/boot/dts/imx53-smd.dts +++ b/trunk/arch/arm/boot/dts/imx53-smd.dts @@ -25,22 +25,30 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1_1>; cd-gpios = <&gpio3 13 0>; wp-gpios = <&gpio4 11 0>; status = "okay"; }; esdhc@50008000 { /* ESDHC2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2_1>; non-removable; status = "okay"; }; uart3: serial@5000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; fsl,uart-has-rtscts; status = "okay"; }; ecspi@50010000 { /* ECSPI1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; status = "okay"; @@ -72,35 +80,49 @@ }; esdhc@50020000 { /* ESDHC3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3_1>; non-removable; status = "okay"; }; }; - wdog@53f98000 { /* WDOG1 */ - status = "okay"; - }; - iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc-smd"; - reg = <0x53fa8000 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */ + 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */ + 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */ + 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ + 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */ + 43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */ + 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ + >; + }; + }; }; uart1: serial@53fbc000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; status = "okay"; }; uart2: serial@53fc0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; status = "okay"; }; }; aips@60000000 { /* AIPS2 */ - sdma@63fb0000 { - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; - }; - i2c@63fc4000 { /* I2C2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_1>; status = "okay"; codec: sgtl5000@0a { @@ -120,6 +142,8 @@ }; i2c@63fc8000 { /* I2C1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; status = "okay"; accelerometer: mma8450@1c { @@ -139,6 +163,8 @@ }; ethernet@63fec000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_1>; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 0>; status = "okay"; diff --git a/trunk/arch/arm/boot/dts/imx53.dtsi b/trunk/arch/arm/boot/dts/imx53.dtsi index cd37165edce5..221cf3321b0a 100644 --- a/trunk/arch/arm/boot/dts/imx53.dtsi +++ b/trunk/arch/arm/boot/dts/imx53.dtsi @@ -135,6 +135,34 @@ }; }; + usb@53f80000 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80000 0x0200>; + interrupts = <18>; + status = "disabled"; + }; + + usb@53f80200 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80200 0x0200>; + interrupts = <14>; + status = "disabled"; + }; + + usb@53f80400 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80400 0x0200>; + interrupts = <16>; + status = "disabled"; + }; + + usb@53f80600 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80600 0x0200>; + interrupts = <17>; + status = "disabled"; + }; + gpio1: gpio@53f84000 { compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; reg = <0x53f84000 0x4000>; @@ -179,7 +207,6 @@ compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f98000 0x4000>; interrupts = <58>; - status = "disabled"; }; wdog@53f9c000 { /* WDOG2 */ @@ -189,6 +216,161 @@ status = "disabled"; }; + iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc"; + reg = <0x53fa8000 0x4000>; + + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */ + 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */ + 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */ + 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */ + >; + }; + }; + + fec { + pinctrl_fec_1: fecgrp-1 { + fsl,pins = < + 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */ + 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */ + 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */ + 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */ + 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */ + 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */ + 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */ + 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */ + 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */ + 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */ + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */ + 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */ + 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */ + >; + }; + }; + + esdhc1 { + pinctrl_esdhc1_1: esdhc1grp-1 { + fsl,pins = < + 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ + 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ + 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ + 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ + 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ + 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ + >; + }; + + pinctrl_esdhc1_2: esdhc1grp-2 { + fsl,pins = < + 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ + 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ + 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ + 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ + 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */ + 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */ + 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */ + 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */ + 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ + 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ + >; + }; + }; + + esdhc2 { + pinctrl_esdhc2_1: esdhc2grp-1 { + fsl,pins = < + 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */ + 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */ + 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */ + 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */ + 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */ + 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */ + >; + }; + }; + + esdhc3 { + pinctrl_esdhc3_1: esdhc3grp-1 { + fsl,pins = < + 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */ + 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */ + 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */ + 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */ + 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */ + 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */ + 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */ + 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */ + 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */ + 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */ + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */ + 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */ + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */ + 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */ + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */ + 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */ + >; + }; + + pinctrl_uart1_2: uart1grp-2 { + fsl,pins = < + 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */ + 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */ + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */ + 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */ + >; + }; + }; + + uart3 { + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */ + 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */ + 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */ + 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */ + >; + }; + }; + }; + uart1: serial@53fbc000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fbc000 0x4000>; @@ -203,6 +385,20 @@ status = "disabled"; }; + can1: can@53fc8000 { + compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; + reg = <0x53fc8000 0x4000>; + interrupts = <82>; + status = "disabled"; + }; + + can2: can@53fcc000 { + compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; + reg = <0x53fcc000 0x4000>; + interrupts = <83>; + status = "disabled"; + }; + gpio5: gpio@53fdc000 { compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; reg = <0x53fdc000 0x4000>; @@ -277,6 +473,7 @@ compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; reg = <0x63fb0000 0x4000>; interrupts = <6>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; }; cspi@63fc0000 { diff --git a/trunk/arch/arm/boot/dts/imx6q-arm2.dts b/trunk/arch/arm/boot/dts/imx6q-arm2.dts index d792581672cc..15df4c105e89 100644 --- a/trunk/arch/arm/boot/dts/imx6q-arm2.dts +++ b/trunk/arch/arm/boot/dts/imx6q-arm2.dts @@ -28,8 +28,27 @@ status = "disabled"; /* gpmi nand conflicts with SD */ }; + aips-bus@02000000 { /* AIPS1 */ + iomuxc@020e0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */ + 1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */ + 1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */ + >; + }; + }; + }; + }; + aips-bus@02100000 { /* AIPS2 */ ethernet@02188000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_2>; phy-mode = "rgmii"; status = "okay"; }; @@ -52,6 +71,8 @@ }; uart4: serial@021f0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_1>; status = "okay"; }; }; diff --git a/trunk/arch/arm/boot/dts/imx6q-sabrelite.dts b/trunk/arch/arm/boot/dts/imx6q-sabrelite.dts index 72f30f3e6171..d152328285a1 100644 --- a/trunk/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/trunk/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -46,15 +46,20 @@ iomuxc@020e0000 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_hog>; + pinctrl-0 = <&pinctrl_hog>; - gpios { - pinctrl_gpio_hog: gpiohog { + hog { + pinctrl_hog: hoggrp { fsl,pins = < - 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ - 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ - 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */ - >; + 1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */ + 1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */ + 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ + 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ + 152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */ + 1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */ + 1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */ + 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */ + >; }; }; }; @@ -63,6 +68,9 @@ aips-bus@02100000 { /* AIPS2 */ usb@02184000 { /* USB OTG */ vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_1>; + disable-over-current; status = "okay"; }; @@ -71,12 +79,16 @@ }; ethernet@02188000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_1>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio3 23 0>; status = "okay"; }; usdhc@02198000 { /* uSDHC3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_2>; cd-gpios = <&gpio7 0 0>; wp-gpios = <&gpio7 1 0>; vmmc-supply = <®_3p3v>; @@ -84,6 +96,8 @@ }; usdhc@0219c000 { /* uSDHC4 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_2>; cd-gpios = <&gpio2 6 0>; wp-gpios = <&gpio2 7 0>; vmmc-supply = <®_3p3v>; @@ -99,7 +113,7 @@ uart2: serial@021e8000 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial2_1>; + pinctrl-0 = <&pinctrl_uart2_1>; }; i2c@021a0000 { /* I2C1 */ @@ -111,6 +125,7 @@ codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + clocks = <&clks 169>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; }; diff --git a/trunk/arch/arm/boot/dts/imx6q-sabresd.dts b/trunk/arch/arm/boot/dts/imx6q-sabresd.dts index 07509a181178..e596c28c214d 100644 --- a/trunk/arch/arm/boot/dts/imx6q-sabresd.dts +++ b/trunk/arch/arm/boot/dts/imx6q-sabresd.dts @@ -22,28 +22,51 @@ }; soc { - aips-bus@02000000 { /* AIPS1 */ spba-bus@02000000 { uart1: serial@02020000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; status = "okay"; }; }; + + iomuxc@020e0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */ + 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */ + 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */ + 1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */ + >; + }; + }; + }; }; aips-bus@02100000 { /* AIPS2 */ ethernet@02188000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_1>; phy-mode = "rgmii"; status = "okay"; }; usdhc@02194000 { /* uSDHC2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_1>; cd-gpios = <&gpio2 2 0>; wp-gpios = <&gpio2 3 0>; status = "okay"; }; usdhc@02198000 { /* uSDHC3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_1>; cd-gpios = <&gpio2 0 0>; wp-gpios = <&gpio2 1 0>; status = "okay"; diff --git a/trunk/arch/arm/boot/dts/imx6q.dtsi b/trunk/arch/arm/boot/dts/imx6q.dtsi index fd57079f71a9..35e5895ba3df 100644 --- a/trunk/arch/arm/boot/dts/imx6q.dtsi +++ b/trunk/arch/arm/boot/dts/imx6q.dtsi @@ -97,18 +97,23 @@ dma-apbh@00110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x00110000 0x2000>; + clocks = <&clks 106>; }; gpmi-nand@00112000 { - compatible = "fsl,imx6q-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x00112000 0x2000>, <0x00114000 0x2000>; - reg-names = "gpmi-nand", "bch"; - interrupts = <0 13 0x04>, <0 15 0x04>; - interrupt-names = "gpmi-dma", "bch"; - fsl,gpmi-dma-channel = <0>; - status = "disabled"; + compatible = "fsl,imx6q-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00112000 0x2000>, <0x00114000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <0 13 0x04>, <0 15 0x04>; + interrupt-names = "gpmi-dma", "bch"; + clocks = <&clks 152>, <&clks 153>, <&clks 151>, + <&clks 150>, <&clks 149>; + clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", + "gpmi_bch_apb", "per1_bch"; + fsl,gpmi-dma-channel = <0>; + status = "disabled"; }; timer@00a00600 { @@ -150,6 +155,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02008000 0x4000>; interrupts = <0 31 0x04>; + clocks = <&clks 112>, <&clks 112>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -159,6 +166,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x0200c000 0x4000>; interrupts = <0 32 0x04>; + clocks = <&clks 113>, <&clks 113>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -168,6 +177,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02010000 0x4000>; interrupts = <0 33 0x04>; + clocks = <&clks 114>, <&clks 114>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -177,6 +188,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02014000 0x4000>; interrupts = <0 34 0x04>; + clocks = <&clks 115>, <&clks 115>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -186,6 +199,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02018000 0x4000>; interrupts = <0 35 0x04>; + clocks = <&clks 116>, <&clks 116>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -193,6 +208,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = <0 26 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -205,6 +222,7 @@ compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; reg = <0x02028000 0x4000>; interrupts = <0 46 0x04>; + clocks = <&clks 178>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <38 37>; status = "disabled"; @@ -214,6 +232,7 @@ compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; reg = <0x0202c000 0x4000>; interrupts = <0 47 0x04>; + clocks = <&clks 179>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <42 41>; status = "disabled"; @@ -223,6 +242,7 @@ compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; reg = <0x02030000 0x4000>; interrupts = <0 48 0x04>; + clocks = <&clks 180>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <46 45>; status = "disabled"; @@ -362,20 +382,22 @@ compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <0 80 0x04>; - status = "disabled"; + clocks = <&clks 0>; }; wdog@020c0000 { /* WDOG2 */ compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <0 81 0x04>; + clocks = <&clks 0>; status = "disabled"; }; - ccm@020c4000 { + clks: ccm@020c4000 { compatible = "fsl,imx6q-ccm"; reg = <0x020c4000 0x4000>; interrupts = <0 87 0x04 0 88 0x04>; + #clock-cells = <1>; }; anatop@020c8000 { @@ -472,12 +494,14 @@ compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <0 44 0x04>; + clocks = <&clks 182>; }; usbphy2: usbphy@020ca000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = <0 45 0x04>; + clocks = <&clks 183>; }; snvs@020cc000 { @@ -514,86 +538,207 @@ /* shared pinctrl settings */ audmux { pinctrl_audmux_1: audmux-1 { - fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ - 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ - 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ - 3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ + fsl,pins = < + 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ + 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ + 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ + 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ + 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ + 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ + >; + }; + }; + + enet { + pinctrl_enet_1: enetgrp-1 { + fsl,pins = < + 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */ + 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */ + 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ + 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ + 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ + 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ + 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ + 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ + 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ + 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ + 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ + 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ + 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ + 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ + 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ + >; + }; + + pinctrl_enet_2: enetgrp-2 { + fsl,pins = < + 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */ + 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */ + 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ + 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ + 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ + 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ + 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ + 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ + 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ + 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ + 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ + 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ + 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ + 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ + 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ + >; }; }; gpmi-nand { pinctrl_gpmi_nand_1: gpmi-nand-1 { - fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ - 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ - 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ - 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ - 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ - 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ - 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ - 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ - 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ - 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ - 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ - 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ - 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ - 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ - 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ - 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ - 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ - 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ - 1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ + fsl,pins = < + 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ + 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ + 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ + 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ + 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ + 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ + 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ + 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ + 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ + 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ + 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ + 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ + 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ + 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ + 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ + 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ + 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ + 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ + 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ + >; }; }; i2c1 { pinctrl_i2c1_1: i2c1grp-1 { - fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ - 196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */ + fsl,pins = < + 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ + 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */ + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ + 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ + >; }; }; - serial2 { - pinctrl_serial2_1: serial2grp-1 { - fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ - 191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */ + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ + 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */ + >; + }; + }; + + uart4 { + pinctrl_uart4_1: uart4grp-1 { + fsl,pins = < + 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */ + 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */ + >; + }; + }; + + usbotg { + pinctrl_usbotg_1: usbotggrp-1 { + fsl,pins = < + 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */ + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ + 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ + 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ + 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ + 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ + 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ + 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ + 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ + 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ + 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ + >; }; }; usdhc3 { pinctrl_usdhc3_1: usdhc3grp-1 { - fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ - 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ - 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ - 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ - 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ - 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ - 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ - 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ - 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ - 1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ + fsl,pins = < + 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ + 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ + 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ + 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ + 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ + 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ + 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ + 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ + 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ + 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ + >; + }; + + pinctrl_usdhc3_2: usdhc3grp-2 { + fsl,pins = < + 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ + 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ + 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ + 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ + 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ + 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ + >; }; }; usdhc4 { pinctrl_usdhc4_1: usdhc4grp-1 { - fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ - 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ - 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ - 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ - 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ - 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ - 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ - 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ - 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ - 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ + fsl,pins = < + 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ + 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ + 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ + 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ + 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ + 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ + 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ + 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ + 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ + 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ + >; }; - }; - ecspi1 { - pinctrl_ecspi1_1: ecspi1grp-1 { - fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ - 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ - 94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ + 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ + 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ + 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ + 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ + 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ + >; }; }; }; @@ -612,6 +757,9 @@ compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = <0 2 0x04>; + clocks = <&clks 155>, <&clks 155>; + clock-names = "ipg", "ahb"; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin"; }; }; @@ -635,7 +783,9 @@ compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; interrupts = <0 43 0x04>; + clocks = <&clks 162>; fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; status = "disabled"; }; @@ -643,7 +793,9 @@ compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; interrupts = <0 40 0x04>; + clocks = <&clks 162>; fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; status = "disabled"; }; @@ -651,6 +803,8 @@ compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184400 0x200>; interrupts = <0 41 0x04>; + clocks = <&clks 162>; + fsl,usbmisc = <&usbmisc 2>; status = "disabled"; }; @@ -658,13 +812,24 @@ compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184600 0x200>; interrupts = <0 42 0x04>; + clocks = <&clks 162>; + fsl,usbmisc = <&usbmisc 3>; status = "disabled"; }; + usbmisc: usbmisc@02184800 { + #index-cells = <1>; + compatible = "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + clocks = <&clks 162>; + }; + ethernet@02188000 { compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; interrupts = <0 118 0x04 0 119 0x04>; + clocks = <&clks 117>, <&clks 117>; + clock-names = "ipg", "ahb"; status = "disabled"; }; @@ -677,6 +842,8 @@ compatible = "fsl,imx6q-usdhc"; reg = <0x02190000 0x4000>; interrupts = <0 22 0x04>; + clocks = <&clks 163>, <&clks 163>, <&clks 163>; + clock-names = "ipg", "ahb", "per"; status = "disabled"; }; @@ -684,6 +851,8 @@ compatible = "fsl,imx6q-usdhc"; reg = <0x02194000 0x4000>; interrupts = <0 23 0x04>; + clocks = <&clks 164>, <&clks 164>, <&clks 164>; + clock-names = "ipg", "ahb", "per"; status = "disabled"; }; @@ -691,6 +860,8 @@ compatible = "fsl,imx6q-usdhc"; reg = <0x02198000 0x4000>; interrupts = <0 24 0x04>; + clocks = <&clks 165>, <&clks 165>, <&clks 165>; + clock-names = "ipg", "ahb", "per"; status = "disabled"; }; @@ -698,6 +869,8 @@ compatible = "fsl,imx6q-usdhc"; reg = <0x0219c000 0x4000>; interrupts = <0 25 0x04>; + clocks = <&clks 166>, <&clks 166>, <&clks 166>; + clock-names = "ipg", "ahb", "per"; status = "disabled"; }; @@ -707,6 +880,7 @@ compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; reg = <0x021a0000 0x4000>; interrupts = <0 36 0x04>; + clocks = <&clks 125>; status = "disabled"; }; @@ -716,6 +890,7 @@ compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; reg = <0x021a4000 0x4000>; interrupts = <0 37 0x04>; + clocks = <&clks 126>; status = "disabled"; }; @@ -725,6 +900,7 @@ compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; reg = <0x021a8000 0x4000>; interrupts = <0 38 0x04>; + clocks = <&clks 127>; status = "disabled"; }; @@ -788,6 +964,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021e8000 0x4000>; interrupts = <0 27 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -795,6 +973,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021ec000 0x4000>; interrupts = <0 28 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -802,6 +982,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f0000 0x4000>; interrupts = <0 29 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -809,6 +991,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f4000 0x4000>; interrupts = <0 30 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; status = "disabled"; }; }; diff --git a/trunk/arch/arm/boot/dts/mmp2.dtsi b/trunk/arch/arm/boot/dts/mmp2.dtsi index 80f74e256408..0514fb41627e 100644 --- a/trunk/arch/arm/boot/dts/mmp2.dtsi +++ b/trunk/arch/arm/boot/dts/mmp2.dtsi @@ -26,6 +26,11 @@ interrupt-parent = <&intc>; ranges; + L2: l2-cache { + compatible = "marvell,tauros2-cache"; + marvell,tauros2-cache-features = <0x3>; + }; + axi@d4200000 { /* AXI */ compatible = "mrvl,axi-bus", "simple-bus"; #address-cells = <1>; diff --git a/trunk/arch/arm/boot/dts/msm8660-surf.dts b/trunk/arch/arm/boot/dts/msm8660-surf.dts index 45bc4bb04e57..31f2157cd7d7 100644 --- a/trunk/arch/arm/boot/dts/msm8660-surf.dts +++ b/trunk/arch/arm/boot/dts/msm8660-surf.dts @@ -7,7 +7,7 @@ compatible = "qcom,msm8660-surf", "qcom,msm8660"; interrupt-parent = <&intc>; - intc: interrupt-controller@02080000 { + intc: interrupt-controller@2080000 { compatible = "qcom,msm-8660-qgic"; interrupt-controller; #interrupt-cells = <3>; @@ -15,6 +15,23 @@ < 0x02081000 0x1000 >; }; + timer@2000004 { + compatible = "qcom,msm-gpt", "qcom,msm-timer"; + interrupts = <1 1 0x301>; + reg = <0x02000004 0x10>; + clock-frequency = <32768>; + cpu-offset = <0x40000>; + }; + + timer@2000024 { + compatible = "qcom,msm-dgt", "qcom,msm-timer"; + interrupts = <1 0 0x301>; + reg = <0x02000024 0x10>, + <0x02000034 0x4>; + clock-frequency = <6750000>; + cpu-offset = <0x40000>; + }; + serial@19c400000 { compatible = "qcom,msm-hsuart", "qcom,msm-uart"; reg = <0x19c40000 0x1000>, diff --git a/trunk/arch/arm/boot/dts/msm8960-cdp.dts b/trunk/arch/arm/boot/dts/msm8960-cdp.dts new file mode 100644 index 000000000000..9e621b5ad3dd --- /dev/null +++ b/trunk/arch/arm/boot/dts/msm8960-cdp.dts @@ -0,0 +1,41 @@ +/dts-v1/; + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MSM8960 CDP"; + compatible = "qcom,msm8960-cdp", "qcom,msm8960"; + interrupt-parent = <&intc>; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x02000000 0x1000 >, + < 0x02002000 0x1000 >; + }; + + timer@200a004 { + compatible = "qcom,msm-gpt", "qcom,msm-timer"; + interrupts = <1 2 0x301>; + reg = <0x0200a004 0x10>; + clock-frequency = <32768>; + cpu-offset = <0x80000>; + }; + + timer@200a024 { + compatible = "qcom,msm-dgt", "qcom,msm-timer"; + interrupts = <1 1 0x301>; + reg = <0x0200a024 0x10>, + <0x0200a034 0x4>; + clock-frequency = <6750000>; + cpu-offset = <0x80000>; + }; + + serial@19c400000 { + compatible = "qcom,msm-hsuart", "qcom,msm-uart"; + reg = <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts = <0 154 0x0>; + }; +}; diff --git a/trunk/arch/arm/boot/dts/omap2420-h4.dts b/trunk/arch/arm/boot/dts/omap2420-h4.dts index 25b50b759dec..77b84e17c477 100644 --- a/trunk/arch/arm/boot/dts/omap2420-h4.dts +++ b/trunk/arch/arm/boot/dts/omap2420-h4.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "omap2.dtsi" +/include/ "omap2420.dtsi" / { model = "TI OMAP2420 H4 board"; diff --git a/trunk/arch/arm/boot/dts/omap2420.dtsi b/trunk/arch/arm/boot/dts/omap2420.dtsi new file mode 100644 index 000000000000..bfd76b4a0ddc --- /dev/null +++ b/trunk/arch/arm/boot/dts/omap2420.dtsi @@ -0,0 +1,48 @@ +/* + * Device Tree Source for OMAP2420 SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "omap2.dtsi" + +/ { + compatible = "ti,omap2420", "ti,omap2"; + + ocp { + omap2420_pmx: pinmux@48000030 { + compatible = "ti,omap2420-padconf", "pinctrl-single"; + reg = <0x48000030 0x0113>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <8>; + pinctrl-single,function-mask = <0x3f>; + }; + + mcbsp1: mcbsp@48074000 { + compatible = "ti,omap2420-mcbsp"; + reg = <0x48074000 0xff>; + reg-names = "mpu"; + interrupts = <59>, /* TX interrupt */ + <60>; /* RX interrupt */ + interrupt-names = "tx", "rx"; + interrupt-parent = <&intc>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@48076000 { + compatible = "ti,omap2420-mcbsp"; + reg = <0x48076000 0xff>; + reg-names = "mpu"; + interrupts = <62>, /* TX interrupt */ + <63>; /* RX interrupt */ + interrupt-names = "tx", "rx"; + interrupt-parent = <&intc>; + ti,hwmods = "mcbsp2"; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/omap2430.dtsi b/trunk/arch/arm/boot/dts/omap2430.dtsi new file mode 100644 index 000000000000..4565d9750f4d --- /dev/null +++ b/trunk/arch/arm/boot/dts/omap2430.dtsi @@ -0,0 +1,92 @@ +/* + * Device Tree Source for OMAP243x SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "omap2.dtsi" + +/ { + compatible = "ti,omap2430", "ti,omap2"; + + ocp { + omap2430_pmx: pinmux@49002030 { + compatible = "ti,omap2430-padconf", "pinctrl-single"; + reg = <0x49002030 0x0154>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <8>; + pinctrl-single,function-mask = <0x3f>; + }; + + mcbsp1: mcbsp@48074000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x48074000 0xff>; + reg-names = "mpu"; + interrupts = <64>, /* OCP compliant interrupt */ + <59>, /* TX interrupt */ + <60>, /* RX interrupt */ + <61>; /* RX overflow interrupt */ + interrupt-names = "common", "tx", "rx", "rx_overflow"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@48076000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x48076000 0xff>; + reg-names = "mpu"; + interrupts = <16>, /* OCP compliant interrupt */ + <62>, /* TX interrupt */ + <63>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp2"; + }; + + mcbsp3: mcbsp@4808c000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x4808c000 0xff>; + reg-names = "mpu"; + interrupts = <17>, /* OCP compliant interrupt */ + <89>, /* TX interrupt */ + <90>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp3"; + }; + + mcbsp4: mcbsp@4808e000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x4808e000 0xff>; + reg-names = "mpu"; + interrupts = <18>, /* OCP compliant interrupt */ + <54>, /* TX interrupt */ + <55>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp4"; + }; + + mcbsp5: mcbsp@48096000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x48096000 0xff>; + reg-names = "mpu"; + interrupts = <19>, /* OCP compliant interrupt */ + <81>, /* TX interrupt */ + <82>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp5"; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/omap3-beagle.dts b/trunk/arch/arm/boot/dts/omap3-beagle-xm.dts similarity index 52% rename from trunk/arch/arm/boot/dts/omap3-beagle.dts rename to trunk/arch/arm/boot/dts/omap3-beagle-xm.dts index cdcb98c7e075..c38cf76df81f 100644 --- a/trunk/arch/arm/boot/dts/omap3-beagle.dts +++ b/trunk/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -7,16 +7,44 @@ */ /dts-v1/; -/include/ "omap3.dtsi" +/include/ "omap36xx.dtsi" / { - model = "TI OMAP3 BeagleBoard"; - compatible = "ti,omap3-beagle", "ti,omap3"; + model = "TI OMAP3 BeagleBoard xM"; + compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3"; memory { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; + + leds { + compatible = "gpio-leds"; + pmu_stat { + label = "beagleboard::pmu_stat"; + gpios = <&twl_gpio 19 0>; /* LEDB */ + }; + + heartbeat { + label = "beagleboard::usr0"; + gpios = <&gpio5 22 0>; /* 150 -> D6 LED */ + linux,default-trigger = "heartbeat"; + }; + + mmc { + label = "beagleboard::usr1"; + gpios = <&gpio5 21 0>; /* 149 -> D7 LED */ + linux,default-trigger = "mmc0"; + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3beagle"; + + ti,mcbsp = <&mcbsp2>; + ti,codec = <&twl_audio>; + }; }; &i2c1 { @@ -27,11 +55,17 @@ interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; - vsim: regulator@10 { + vsim: regulator-vsim { compatible = "ti,twl4030-vsim"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; }; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; }; }; @@ -67,3 +101,15 @@ &mmc3 { status = "disabled"; }; + +&twl_gpio { + ti,use-leds; + /* pullups: BIT(1) */ + ti,pullups = <0x000002>; + /* + * pulldowns: + * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) + * BIT(15), BIT(16), BIT(17) + */ + ti,pulldowns = <0x03a1c4>; +}; diff --git a/trunk/arch/arm/boot/dts/omap3-evm.dts b/trunk/arch/arm/boot/dts/omap3-evm.dts index f349ee9182ce..e8ba1c247a39 100644 --- a/trunk/arch/arm/boot/dts/omap3-evm.dts +++ b/trunk/arch/arm/boot/dts/omap3-evm.dts @@ -17,6 +17,15 @@ device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; + + leds { + compatible = "gpio-leds"; + ledb { + label = "omap3evm::ledb"; + gpios = <&twl_gpio 19 0>; /* LEDB */ + linux,default-trigger = "default-on"; + }; + }; }; &i2c1 { @@ -46,3 +55,7 @@ reg = <0x5c>; }; }; + +&twl_gpio { + ti,use-leds; +}; diff --git a/trunk/arch/arm/boot/dts/omap3-overo.dtsi b/trunk/arch/arm/boot/dts/omap3-overo.dtsi new file mode 100644 index 000000000000..89808ce01673 --- /dev/null +++ b/trunk/arch/arm/boot/dts/omap3-overo.dtsi @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * The Gumstix Overo must be combined with an expansion board. + */ +/dts-v1/; + +/include/ "omap3.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + overo { + label = "overo:blue:COM"; + gpios = <&twl_gpio 19 0>; + linux,default-trigger = "mmc0"; + }; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +/include/ "twl4030.dtsi" + +/* i2c2 pins are used for gpio */ +&i2c2 { + status = "disabled"; +}; + +/* on board microSD slot */ +&mmc1 { + vmmc-supply = <&vmmc1>; + bus-width = <4>; +}; + +/* optional on board WiFi */ +&mmc2 { + bus-width = <4>; +}; + +&twl_gpio { + ti,use-leds; +}; diff --git a/trunk/arch/arm/boot/dts/omap3-tobi.dts b/trunk/arch/arm/boot/dts/omap3-tobi.dts new file mode 100644 index 000000000000..a13d12de77ff --- /dev/null +++ b/trunk/arch/arm/boot/dts/omap3-tobi.dts @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Tobi expansion board is manufactured by Gumstix Inc. + */ + +/include/ "omap3-overo.dtsi" + +/ { + model = "TI OMAP3 Gumstix Overo on Tobi"; + compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"; + + leds { + compatible = "gpio-leds"; + heartbeat { + label = "overo:red:gpio21"; + gpios = <&gpio1 21 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; +}; + +&mmc3 { + status = "disabled"; +}; diff --git a/trunk/arch/arm/boot/dts/omap3.dtsi b/trunk/arch/arm/boot/dts/omap3.dtsi index 810947198208..f38ea8771b44 100644 --- a/trunk/arch/arm/boot/dts/omap3.dtsi +++ b/trunk/arch/arm/boot/dts/omap3.dtsi @@ -17,7 +17,6 @@ serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; - serial3 = &uart4; }; cpus { @@ -69,6 +68,24 @@ reg = <0x48200000 0x1000>; }; + omap3_pmx_core: pinmux@48002030 { + compatible = "ti,omap3-padconf", "pinctrl-single"; + reg = <0x48002030 0x05cc>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + + omap3_pmx_wkup: pinmux@0x48002a58 { + compatible = "ti,omap3-padconf", "pinctrl-single"; + reg = <0x48002a58 0x5c>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + gpio1: gpio@48310000 { compatible = "ti,omap3-gpio"; ti,hwmods = "gpio1"; @@ -141,12 +158,6 @@ clock-frequency = <48000000>; }; - uart4: serial@49042000 { - compatible = "ti,omap3-uart"; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - }; - i2c1: i2c@48070000 { compatible = "ti,omap3-i2c"; #address-cells = <1>; @@ -220,5 +231,74 @@ compatible = "ti,omap3-wdt"; ti,hwmods = "wd_timer2"; }; + + mcbsp1: mcbsp@48074000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x48074000 0xff>; + reg-names = "mpu"; + interrupts = <16>, /* OCP compliant interrupt */ + <59>, /* TX interrupt */ + <60>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@49022000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x49022000 0xff>, + <0x49028000 0xff>; + reg-names = "mpu", "sidetone"; + interrupts = <17>, /* OCP compliant interrupt */ + <62>, /* TX interrupt */ + <63>, /* RX interrupt */ + <4>; /* Sidetone */ + interrupt-names = "common", "tx", "rx", "sidetone"; + interrupt-parent = <&intc>; + ti,buffer-size = <1280>; + ti,hwmods = "mcbsp2"; + }; + + mcbsp3: mcbsp@49024000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x49024000 0xff>, + <0x4902a000 0xff>; + reg-names = "mpu", "sidetone"; + interrupts = <22>, /* OCP compliant interrupt */ + <89>, /* TX interrupt */ + <90>, /* RX interrupt */ + <5>; /* Sidetone */ + interrupt-names = "common", "tx", "rx", "sidetone"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp3"; + }; + + mcbsp4: mcbsp@49026000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x49026000 0xff>; + reg-names = "mpu"; + interrupts = <23>, /* OCP compliant interrupt */ + <54>, /* TX interrupt */ + <55>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp4"; + }; + + mcbsp5: mcbsp@48096000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x48096000 0xff>; + reg-names = "mpu"; + interrupts = <27>, /* OCP compliant interrupt */ + <81>, /* TX interrupt */ + <82>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp5"; + }; }; }; diff --git a/trunk/arch/arm/boot/dts/omap36xx.dtsi b/trunk/arch/arm/boot/dts/omap36xx.dtsi new file mode 100644 index 000000000000..96bf0287cb9f --- /dev/null +++ b/trunk/arch/arm/boot/dts/omap36xx.dtsi @@ -0,0 +1,25 @@ +/* + * Device Tree Source for OMAP3 SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "omap3.dtsi" + +/ { + aliases { + serial3 = &uart4; + }; + + ocp { + uart4: serial@49042000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/omap4-panda.dts b/trunk/arch/arm/boot/dts/omap4-panda.dts index 9880c12877b3..20b966ee1bb3 100644 --- a/trunk/arch/arm/boot/dts/omap4-panda.dts +++ b/trunk/arch/arm/boot/dts/omap4-panda.dts @@ -8,6 +8,7 @@ /dts-v1/; /include/ "omap4.dtsi" +/include/ "elpida_ecb240abacn.dtsi" / { model = "TI OMAP4 PandaBoard"; @@ -126,3 +127,13 @@ ti,non-removable; bus-width = <4>; }; + +&emif1 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; + +&emif2 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; diff --git a/trunk/arch/arm/boot/dts/omap4-sdp.dts b/trunk/arch/arm/boot/dts/omap4-sdp.dts index 72216e932fc0..94a23b39033d 100644 --- a/trunk/arch/arm/boot/dts/omap4-sdp.dts +++ b/trunk/arch/arm/boot/dts/omap4-sdp.dts @@ -8,6 +8,7 @@ /dts-v1/; /include/ "omap4.dtsi" +/include/ "elpida_ecb240abacn.dtsi" / { model = "TI OMAP4 SDP board"; @@ -18,7 +19,7 @@ reg = <0x80000000 0x40000000>; /* 1 GB */ }; - vdd_eth: fixedregulator@0 { + vdd_eth: fixedregulator-vdd-eth { compatible = "regulator-fixed"; regulator-name = "VDD_ETH"; regulator-min-microvolt = <3300000>; @@ -28,7 +29,7 @@ regulator-boot-on; }; - vbat: fixedregulator@2 { + vbat: fixedregulator-vbat { compatible = "regulator-fixed"; regulator-name = "VBAT"; regulator-min-microvolt = <3750000>; @@ -115,6 +116,33 @@ }; }; +&omap4_pmx_core { + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + 0xd8 0x118 /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */ + 0xda 0 /* uart2_rts.uart2_rts OUTPUT | MODE0 */ + 0xdc 0x118 /* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */ + 0xde 0 /* uart2_tx.uart2_tx OUTPUT | MODE0 */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x100 0x118 /* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */ + 0x102 0 /* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */ + 0x104 0x100 /* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */ + 0x106 0 /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ + >; + }; + + uart4_pins: pinmux_uart4_pins { + pinctrl-single,pins = < + 0x11c 0x100 /* uart4_rx.uart4_rx INPUT | MODE0 */ + 0x11e 0 /* uart4_tx.uart4_tx OUTPUT | MODE0 */ + >; + }; +}; + &i2c1 { clock-frequency = <400000>; @@ -226,3 +254,98 @@ bus-width = <4>; ti,non-removable; }; + +&emif1 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; + +&emif2 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; + +&keypad { + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = <0x00000012 /* KEY_E */ + 0x00010013 /* KEY_R */ + 0x00020014 /* KEY_T */ + 0x00030066 /* KEY_HOME */ + 0x0004003f /* KEY_F5 */ + 0x000500f0 /* KEY_UNKNOWN */ + 0x00060017 /* KEY_I */ + 0x0007002a /* KEY_LEFTSHIFT */ + 0x01000020 /* KEY_D*/ + 0x01010021 /* KEY_F */ + 0x01020022 /* KEY_G */ + 0x010300e7 /* KEY_SEND */ + 0x01040040 /* KEY_F6 */ + 0x010500f0 /* KEY_UNKNOWN */ + 0x01060025 /* KEY_K */ + 0x0107001c /* KEY_ENTER */ + 0x0200002d /* KEY_X */ + 0x0201002e /* KEY_C */ + 0x0202002f /* KEY_V */ + 0x0203006b /* KEY_END */ + 0x02040041 /* KEY_F7 */ + 0x020500f0 /* KEY_UNKNOWN */ + 0x02060034 /* KEY_DOT */ + 0x0207003a /* KEY_CAPSLOCK */ + 0x0300002c /* KEY_Z */ + 0x0301004e /* KEY_KPLUS */ + 0x03020030 /* KEY_B */ + 0x0303003b /* KEY_F1 */ + 0x03040042 /* KEY_F8 */ + 0x030500f0 /* KEY_UNKNOWN */ + 0x03060018 /* KEY_O */ + 0x03070039 /* KEY_SPACE */ + 0x04000011 /* KEY_W */ + 0x04010015 /* KEY_Y */ + 0x04020016 /* KEY_U */ + 0x0403003c /* KEY_F2 */ + 0x04040073 /* KEY_VOLUMEUP */ + 0x040500f0 /* KEY_UNKNOWN */ + 0x04060026 /* KEY_L */ + 0x04070069 /* KEY_LEFT */ + 0x0500001f /* KEY_S */ + 0x05010023 /* KEY_H */ + 0x05020024 /* KEY_J */ + 0x0503003d /* KEY_F3 */ + 0x05040043 /* KEY_F9 */ + 0x05050072 /* KEY_VOLUMEDOWN */ + 0x05060032 /* KEY_M */ + 0x0507006a /* KEY_RIGHT */ + 0x06000010 /* KEY_Q */ + 0x0601001e /* KEY_A */ + 0x06020031 /* KEY_N */ + 0x0603009e /* KEY_BACK */ + 0x0604000e /* KEY_BACKSPACE */ + 0x060500f0 /* KEY_UNKNOWN */ + 0x06060019 /* KEY_P */ + 0x06070067 /* KEY_UP */ + 0x07000094 /* KEY_PROG1 */ + 0x07010095 /* KEY_PROG2 */ + 0x070200ca /* KEY_PROG3 */ + 0x070300cb /* KEY_PROG4 */ + 0x0704003e /* KEY_F4 */ + 0x070500f0 /* KEY_UNKNOWN */ + 0x07060160 /* KEY_OK */ + 0x0707006c>; /* KEY_DOWN */ + linux,input-no-autorepeat; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; +}; diff --git a/trunk/arch/arm/boot/dts/omap4.dtsi b/trunk/arch/arm/boot/dts/omap4.dtsi index 04cbbcb6ff91..5d1c48459e6e 100644 --- a/trunk/arch/arm/boot/dts/omap4.dtsi +++ b/trunk/arch/arm/boot/dts/omap4.dtsi @@ -30,12 +30,35 @@ cpus { cpu@0 { compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; }; cpu@1 { compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; }; }; + gic: interrupt-controller@48241000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48241000 0x1000>, + <0x48240100 0x0100>; + }; + + L2: l2-cache-controller@48242000 { + compatible = "arm,pl310-cache"; + reg = <0x48242000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + local-timer@0x48240600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x48240600 0x20>; + interrupts = <1 13 0x304>; + }; + /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. @@ -61,30 +84,6 @@ /* * XXX: Use a flat representation of the OMAP4 interconnect. * The real OMAP interconnect network is quite complex. - * - * MPU -+-- MPU_PRIVATE - GIC, L2 - * | - * +----------------+----------+ - * | | | - * + +- EMIF - DDR | - * | | | - * | + +--------+ - * | | | - * | +- L4_ABE - AESS, MCBSP, TIMERs... - * | | - * +- L3_MAIN --+- L4_CORE - IPs... - * | - * +- L4_PER - IPs... - * | - * +- L4_CFG -+- L4_WKUP - IPs... - * | | - * | +- IPs... - * +- IPU ----+ - * | | - * +- DSP ----+ - * | | - * +- DSS ----+ - * * Since that will not bring real advantage to represent that in DT for * the moment, just use a fake OCP bus entry to represent the whole bus * hierarchy. @@ -96,16 +95,27 @@ ranges; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; - gic: interrupt-controller@48241000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48241000 0x1000>, - <0x48240100 0x0100>; + omap4_pmx_core: pinmux@4a100040 { + compatible = "ti,omap4-padconf", "pinctrl-single"; + reg = <0x4a100040 0x0196>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + omap4_pmx_wkup: pinmux@4a31e040 { + compatible = "ti,omap4-padconf", "pinctrl-single"; + reg = <0x4a31e040 0x0038>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; }; gpio1: gpio@4a310000 { compatible = "ti,omap4-gpio"; + reg = <0x4a310000 0x200>; + interrupts = <0 29 0x4>; ti,hwmods = "gpio1"; gpio-controller; #gpio-cells = <2>; @@ -115,6 +125,8 @@ gpio2: gpio@48055000 { compatible = "ti,omap4-gpio"; + reg = <0x48055000 0x200>; + interrupts = <0 30 0x4>; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>; @@ -124,6 +136,8 @@ gpio3: gpio@48057000 { compatible = "ti,omap4-gpio"; + reg = <0x48057000 0x200>; + interrupts = <0 31 0x4>; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>; @@ -133,6 +147,8 @@ gpio4: gpio@48059000 { compatible = "ti,omap4-gpio"; + reg = <0x48059000 0x200>; + interrupts = <0 32 0x4>; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>; @@ -142,6 +158,8 @@ gpio5: gpio@4805b000 { compatible = "ti,omap4-gpio"; + reg = <0x4805b000 0x200>; + interrupts = <0 33 0x4>; ti,hwmods = "gpio5"; gpio-controller; #gpio-cells = <2>; @@ -151,6 +169,8 @@ gpio6: gpio@4805d000 { compatible = "ti,omap4-gpio"; + reg = <0x4805d000 0x200>; + interrupts = <0 34 0x4>; ti,hwmods = "gpio6"; gpio-controller; #gpio-cells = <2>; @@ -160,30 +180,40 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; + reg = <0x4806a000 0x100>; + interrupts = <0 72 0x4>; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial@4806c000 { compatible = "ti,omap4-uart"; + reg = <0x4806c000 0x100>; + interrupts = <0 73 0x4>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial@48020000 { compatible = "ti,omap4-uart"; + reg = <0x48020000 0x100>; + interrupts = <0 74 0x4>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; uart4: serial@4806e000 { compatible = "ti,omap4-uart"; + reg = <0x4806e000 0x100>; + interrupts = <0 70 0x4>; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; i2c1: i2c@48070000 { compatible = "ti,omap4-i2c"; + reg = <0x48070000 0x100>; + interrupts = <0 56 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; @@ -191,6 +221,8 @@ i2c2: i2c@48072000 { compatible = "ti,omap4-i2c"; + reg = <0x48072000 0x100>; + interrupts = <0 57 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; @@ -198,6 +230,8 @@ i2c3: i2c@48060000 { compatible = "ti,omap4-i2c"; + reg = <0x48060000 0x100>; + interrupts = <0 61 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; @@ -205,6 +239,8 @@ i2c4: i2c@48350000 { compatible = "ti,omap4-i2c"; + reg = <0x48350000 0x100>; + interrupts = <0 62 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c4"; @@ -212,6 +248,8 @@ mcspi1: spi@48098000 { compatible = "ti,omap4-mcspi"; + reg = <0x48098000 0x200>; + interrupts = <0 65 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi1"; @@ -220,6 +258,8 @@ mcspi2: spi@4809a000 { compatible = "ti,omap4-mcspi"; + reg = <0x4809a000 0x200>; + interrupts = <0 66 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi2"; @@ -228,6 +268,8 @@ mcspi3: spi@480b8000 { compatible = "ti,omap4-mcspi"; + reg = <0x480b8000 0x200>; + interrupts = <0 91 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi3"; @@ -236,6 +278,8 @@ mcspi4: spi@480ba000 { compatible = "ti,omap4-mcspi"; + reg = <0x480ba000 0x200>; + interrupts = <0 48 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi4"; @@ -244,6 +288,8 @@ mmc1: mmc@4809c000 { compatible = "ti,omap4-hsmmc"; + reg = <0x4809c000 0x400>; + interrupts = <0 83 0x4>; ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset; @@ -251,30 +297,40 @@ mmc2: mmc@480b4000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480b4000 0x400>; + interrupts = <0 86 0x4>; ti,hwmods = "mmc2"; ti,needs-special-reset; }; mmc3: mmc@480ad000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480ad000 0x400>; + interrupts = <0 94 0x4>; ti,hwmods = "mmc3"; ti,needs-special-reset; }; mmc4: mmc@480d1000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480d1000 0x400>; + interrupts = <0 96 0x4>; ti,hwmods = "mmc4"; ti,needs-special-reset; }; mmc5: mmc@480d5000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480d5000 0x400>; + interrupts = <0 59 0x4>; ti,hwmods = "mmc5"; ti,needs-special-reset; }; wdt2: wdt@4a314000 { compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + reg = <0x4a314000 0x80>; + interrupts = <0 80 0x4>; ti,hwmods = "wd_timer2"; }; @@ -282,6 +338,7 @@ compatible = "ti,omap4-mcpdm"; reg = <0x40132000 0x7f>, /* MPU private access */ <0x49032000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; interrupts = <0 112 0x4>; interrupt-parent = <&gic>; ti,hwmods = "mcpdm"; @@ -291,9 +348,87 @@ compatible = "ti,omap4-dmic"; reg = <0x4012e000 0x7f>, /* MPU private access */ <0x4902e000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; interrupts = <0 114 0x4>; interrupt-parent = <&gic>; ti,hwmods = "dmic"; }; + + mcbsp1: mcbsp@40122000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40122000 0xff>, /* MPU private access */ + <0x49022000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 17 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@40124000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40124000 0xff>, /* MPU private access */ + <0x49024000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 22 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp2"; + }; + + mcbsp3: mcbsp@40126000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40126000 0xff>, /* MPU private access */ + <0x49026000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 23 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp3"; + }; + + mcbsp4: mcbsp@48096000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x48096000 0xff>; /* L4 Interconnect */ + reg-names = "mpu"; + interrupts = <0 16 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp4"; + }; + + keypad: keypad@4a31c000 { + compatible = "ti,omap4-keypad"; + reg = <0x4a31c000 0x80>; + interrupts = <0 120 0x4>; + reg-names = "mpu"; + ti,hwmods = "kbd"; + }; + + emif1: emif@4c000000 { + compatible = "ti,emif-4d"; + reg = <0x4c000000 0x100>; + interrupts = <0 110 0x4>; + ti,hwmods = "emif1"; + phy-type = <1>; + hw-caps-read-idle-ctrl; + hw-caps-ll-interface; + hw-caps-temp-alert; + }; + + emif2: emif@4d000000 { + compatible = "ti,emif-4d"; + reg = <0x4d000000 0x100>; + interrupts = <0 111 0x4>; + ti,hwmods = "emif2"; + phy-type = <1>; + hw-caps-read-idle-ctrl; + hw-caps-ll-interface; + hw-caps-temp-alert; + }; }; }; diff --git a/trunk/arch/arm/boot/dts/omap5-evm.dts b/trunk/arch/arm/boot/dts/omap5-evm.dts index 200c39ad1c82..9c41a3f311aa 100644 --- a/trunk/arch/arm/boot/dts/omap5-evm.dts +++ b/trunk/arch/arm/boot/dts/omap5-evm.dts @@ -17,4 +17,68 @@ device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; + + vmmcsd_fixed: fixedregulator-mmcsd { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + ti,non-removable; +}; + +&mmc3 { + bus-width = <4>; + ti,non-removable; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <400000>; + + /* Pressure Sensor */ + bmp085@77 { + compatible = "bosch,bmp085"; + reg = <0x77>; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + + /* Temperature Sensor */ + tmp102@48{ + compatible = "ti,tmp102"; + reg = <0x48>; + }; +}; + +&keypad { + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = <0x02020073 /* VOLUP */ + 0x02030072 /* VOLDOWM */ + 0x020400e7 /* SEND */ + 0x02050066 /* HOME */ + 0x0206006b /* END */ + 0x020700d9>; /* SEARCH */ + linux,input-no-autorepeat; }; diff --git a/trunk/arch/arm/boot/dts/omap5.dtsi b/trunk/arch/arm/boot/dts/omap5.dtsi index 57e527083746..9ac75b37c992 100644 --- a/trunk/arch/arm/boot/dts/omap5.dtsi +++ b/trunk/arch/arm/boot/dts/omap5.dtsi @@ -145,6 +145,41 @@ #interrupt-cells = <1>; }; + i2c1: i2c@48070000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c1"; + }; + + i2c2: i2c@48072000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c2"; + }; + + i2c3: i2c@48060000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c3"; + }; + + i2c4: i2c@4807A000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c4"; + }; + + i2c5: i2c@4807C000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c5"; + }; + uart1: serial@4806a000 { compatible = "ti,omap4-uart"; ti,hwmods = "uart1"; @@ -180,5 +215,97 @@ ti,hwmods = "uart6"; clock-frequency = <48000000>; }; + + mmc1: mmc@4809c000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc1"; + ti,dual-volt; + ti,needs-special-reset; + }; + + mmc2: mmc@480b4000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc2"; + ti,needs-special-reset; + }; + + mmc3: mmc@480ad000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc3"; + ti,needs-special-reset; + }; + + mmc4: mmc@480d1000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc4"; + ti,needs-special-reset; + }; + + mmc5: mmc@480d5000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc5"; + ti,needs-special-reset; + }; + + keypad: keypad@4ae1c000 { + compatible = "ti,omap4-keypad"; + ti,hwmods = "kbd"; + }; + + mcpdm: mcpdm@40132000 { + compatible = "ti,omap4-mcpdm"; + reg = <0x40132000 0x7f>, /* MPU private access */ + <0x49032000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 112 0x4>; + interrupt-parent = <&gic>; + ti,hwmods = "mcpdm"; + }; + + dmic: dmic@4012e000 { + compatible = "ti,omap4-dmic"; + reg = <0x4012e000 0x7f>, /* MPU private access */ + <0x4902e000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 114 0x4>; + interrupt-parent = <&gic>; + ti,hwmods = "dmic"; + }; + + mcbsp1: mcbsp@40122000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40122000 0xff>, /* MPU private access */ + <0x49022000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 17 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@40124000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40124000 0xff>, /* MPU private access */ + <0x49024000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 22 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp2"; + }; + + mcbsp3: mcbsp@40126000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40126000 0xff>, /* MPU private access */ + <0x49026000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 23 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp3"; + }; }; }; diff --git a/trunk/arch/arm/boot/dts/phy3250.dts b/trunk/arch/arm/boot/dts/phy3250.dts index 802ec5b2fd00..a7ad85e4b8f9 100644 --- a/trunk/arch/arm/boot/dts/phy3250.dts +++ b/trunk/arch/arm/boot/dts/phy3250.dts @@ -135,13 +135,11 @@ ssp0: ssp@20084000 { #address-cells = <1>; #size-cells = <0>; - pl022,num-chipselects = <1>; + num-cs = <1>; cs-gpios = <&gpio 3 5 0>; eeprom: at25@0 { - pl022,hierarchy = <0>; pl022,interface = <0>; - pl022,slave-tx-disable = <0>; pl022,com-mode = <0>; pl022,rx-level-trig = <1>; pl022,tx-level-trig = <1>; diff --git a/trunk/arch/arm/boot/dts/prima2-cb.dts b/trunk/arch/arm/boot/dts/prima2-cb.dts deleted file mode 100644 index 34ae3a64ba25..000000000000 --- a/trunk/arch/arm/boot/dts/prima2-cb.dts +++ /dev/null @@ -1,424 +0,0 @@ -/dts-v1/; -/ { - model = "SiRF Prima2 eVB"; - compatible = "sirf,prima2-cb", "sirf,prima2"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - memory { - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1"; - linux,stdout-path = &uart1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - reg = <0x0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <32768>; - i-cache-size = <32768>; - /* from bootloader */ - timebase-frequency = <0>; - bus-frequency = <0>; - clock-frequency = <0>; - }; - }; - - axi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x40000000 0x40000000 0x80000000>; - - l2-cache-controller@80040000 { - compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; - reg = <0x80040000 0x1000>; - interrupts = <59>; - arm,tag-latency = <1 1 1>; - arm,data-latency = <1 1 1>; - arm,filter-ranges = <0 0x40000000>; - }; - - intc: interrupt-controller@80020000 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "sirf,prima2-intc"; - reg = <0x80020000 0x1000>; - }; - - sys-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x88000000 0x88000000 0x40000>; - - clock-controller@88000000 { - compatible = "sirf,prima2-clkc"; - reg = <0x88000000 0x1000>; - interrupts = <3>; - }; - - reset-controller@88010000 { - compatible = "sirf,prima2-rstc"; - reg = <0x88010000 0x1000>; - }; - - rsc-controller@88020000 { - compatible = "sirf,prima2-rsc"; - reg = <0x88020000 0x1000>; - }; - }; - - mem-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90000000 0x90000000 0x10000>; - - memory-controller@90000000 { - compatible = "sirf,prima2-memc"; - reg = <0x90000000 0x10000>; - interrupts = <27>; - }; - }; - - disp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90010000 0x90010000 0x30000>; - - display@90010000 { - compatible = "sirf,prima2-lcd"; - reg = <0x90010000 0x20000>; - interrupts = <30>; - }; - - vpp@90020000 { - compatible = "sirf,prima2-vpp"; - reg = <0x90020000 0x10000>; - interrupts = <31>; - }; - }; - - graphics-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x98000000 0x98000000 0x8000000>; - - graphics@98000000 { - compatible = "powervr,sgx531"; - reg = <0x98000000 0x8000000>; - interrupts = <6>; - }; - }; - - multimedia-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa0000000 0xa0000000 0x8000000>; - - multimedia@a0000000 { - compatible = "sirf,prima2-video-codec"; - reg = <0xa0000000 0x8000000>; - interrupts = <5>; - }; - }; - - dsp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa8000000 0xa8000000 0x2000000>; - - dspif@a8000000 { - compatible = "sirf,prima2-dspif"; - reg = <0xa8000000 0x10000>; - interrupts = <9>; - }; - - gps@a8010000 { - compatible = "sirf,prima2-gps"; - reg = <0xa8010000 0x10000>; - interrupts = <7>; - }; - - dsp@a9000000 { - compatible = "sirf,prima2-dsp"; - reg = <0xa9000000 0x1000000>; - interrupts = <8>; - }; - }; - - peri-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb0000000 0xb0000000 0x180000>; - - timer@b0020000 { - compatible = "sirf,prima2-tick"; - reg = <0xb0020000 0x1000>; - interrupts = <0>; - }; - - nand@b0030000 { - compatible = "sirf,prima2-nand"; - reg = <0xb0030000 0x10000>; - interrupts = <41>; - }; - - audio@b0040000 { - compatible = "sirf,prima2-audio"; - reg = <0xb0040000 0x10000>; - interrupts = <35>; - }; - - uart0: uart@b0050000 { - cell-index = <0>; - compatible = "sirf,prima2-uart"; - reg = <0xb0050000 0x10000>; - interrupts = <17>; - }; - - uart1: uart@b0060000 { - cell-index = <1>; - compatible = "sirf,prima2-uart"; - reg = <0xb0060000 0x10000>; - interrupts = <18>; - }; - - uart2: uart@b0070000 { - cell-index = <2>; - compatible = "sirf,prima2-uart"; - reg = <0xb0070000 0x10000>; - interrupts = <19>; - }; - - usp0: usp@b0080000 { - cell-index = <0>; - compatible = "sirf,prima2-usp"; - reg = <0xb0080000 0x10000>; - interrupts = <20>; - }; - - usp1: usp@b0090000 { - cell-index = <1>; - compatible = "sirf,prima2-usp"; - reg = <0xb0090000 0x10000>; - interrupts = <21>; - }; - - usp2: usp@b00a0000 { - cell-index = <2>; - compatible = "sirf,prima2-usp"; - reg = <0xb00a0000 0x10000>; - interrupts = <22>; - }; - - dmac0: dma-controller@b00b0000 { - cell-index = <0>; - compatible = "sirf,prima2-dmac"; - reg = <0xb00b0000 0x10000>; - interrupts = <12>; - }; - - dmac1: dma-controller@b0160000 { - cell-index = <1>; - compatible = "sirf,prima2-dmac"; - reg = <0xb0160000 0x10000>; - interrupts = <13>; - }; - - vip@b00C0000 { - compatible = "sirf,prima2-vip"; - reg = <0xb00C0000 0x10000>; - }; - - spi0: spi@b00d0000 { - cell-index = <0>; - compatible = "sirf,prima2-spi"; - reg = <0xb00d0000 0x10000>; - interrupts = <15>; - }; - - spi1: spi@b0170000 { - cell-index = <1>; - compatible = "sirf,prima2-spi"; - reg = <0xb0170000 0x10000>; - interrupts = <16>; - }; - - i2c0: i2c@b00e0000 { - cell-index = <0>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00e0000 0x10000>; - interrupts = <24>; - }; - - i2c1: i2c@b00f0000 { - cell-index = <1>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00f0000 0x10000>; - interrupts = <25>; - }; - - tsc@b0110000 { - compatible = "sirf,prima2-tsc"; - reg = <0xb0110000 0x10000>; - interrupts = <33>; - }; - - gpio: gpio-controller@b0120000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,prima2-gpio-pinmux"; - reg = <0xb0120000 0x10000>; - gpio-controller; - interrupt-controller; - }; - - pwm@b0130000 { - compatible = "sirf,prima2-pwm"; - reg = <0xb0130000 0x10000>; - }; - - efusesys@b0140000 { - compatible = "sirf,prima2-efuse"; - reg = <0xb0140000 0x10000>; - }; - - pulsec@b0150000 { - compatible = "sirf,prima2-pulsec"; - reg = <0xb0150000 0x10000>; - interrupts = <48>; - }; - - pci-iobg { - compatible = "sirf,prima2-pciiobg", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x56000000 0x56000000 0x1b00000>; - - sd0: sdhci@56000000 { - cell-index = <0>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56000000 0x100000>; - interrupts = <38>; - }; - - sd1: sdhci@56100000 { - cell-index = <1>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56100000 0x100000>; - interrupts = <38>; - }; - - sd2: sdhci@56200000 { - cell-index = <2>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56200000 0x100000>; - interrupts = <23>; - }; - - sd3: sdhci@56300000 { - cell-index = <3>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56300000 0x100000>; - interrupts = <23>; - }; - - sd4: sdhci@56400000 { - cell-index = <4>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56400000 0x100000>; - interrupts = <39>; - }; - - sd5: sdhci@56500000 { - cell-index = <5>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56500000 0x100000>; - interrupts = <39>; - }; - - pci-copy@57900000 { - compatible = "sirf,prima2-pcicp"; - reg = <0x57900000 0x100000>; - interrupts = <40>; - }; - - rom-interface@57a00000 { - compatible = "sirf,prima2-romif"; - reg = <0x57a00000 0x100000>; - }; - }; - }; - - rtc-iobg { - compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80030000 0x10000>; - - gpsrtc@1000 { - compatible = "sirf,prima2-gpsrtc"; - reg = <0x1000 0x1000>; - interrupts = <55 56 57>; - }; - - sysrtc@2000 { - compatible = "sirf,prima2-sysrtc"; - reg = <0x2000 0x1000>; - interrupts = <52 53 54>; - }; - - pwrc@3000 { - compatible = "sirf,prima2-pwrc"; - reg = <0x3000 0x1000>; - interrupts = <32>; - }; - }; - - uus-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb8000000 0xb8000000 0x40000>; - - usb0: usb@b00e0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8000000 0x10000>; - interrupts = <10>; - }; - - usb1: usb@b00f0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8010000 0x10000>; - interrupts = <11>; - }; - - sata@b00f0000 { - compatible = "synopsys,dwc-ahsata"; - reg = <0xb8020000 0x10000>; - interrupts = <37>; - }; - - security@b00f0000 { - compatible = "sirf,prima2-security"; - reg = <0xb8030000 0x10000>; - interrupts = <42>; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/prima2-evb.dts b/trunk/arch/arm/boot/dts/prima2-evb.dts new file mode 100644 index 000000000000..57286b4e7b87 --- /dev/null +++ b/trunk/arch/arm/boot/dts/prima2-evb.dts @@ -0,0 +1,37 @@ +/* + * DTS file for CSR SiRFprimaII Evaluation Board + * + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +/dts-v1/; + +/include/ "prima2.dtsi" + +/ { + model = "CSR SiRFprimaII Evaluation Board"; + compatible = "sirf,prima2", "sirf,prima2-cb"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + axi { + peri-iobg { + uart@b0060000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>; + }; + spi@b00d0000 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_a>; + }; + spi@b0170000 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + }; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/prima2.dtsi b/trunk/arch/arm/boot/dts/prima2.dtsi new file mode 100644 index 000000000000..055fca542120 --- /dev/null +++ b/trunk/arch/arm/boot/dts/prima2.dtsi @@ -0,0 +1,640 @@ +/* + * DTS file for CSR SiRFprimaII SoC + * + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" +/ { + compatible = "sirf,prima2"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + reg = <0x0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-size = <32768>; + /* from bootloader */ + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + axi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x40000000 0x40000000 0x80000000>; + + l2-cache-controller@80040000 { + compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; + reg = <0x80040000 0x1000>; + interrupts = <59>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <1 1 1>; + arm,filter-ranges = <0 0x40000000>; + }; + + intc: interrupt-controller@80020000 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "sirf,prima2-intc"; + reg = <0x80020000 0x1000>; + }; + + sys-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x88000000 0x88000000 0x40000>; + + clock-controller@88000000 { + compatible = "sirf,prima2-clkc"; + reg = <0x88000000 0x1000>; + interrupts = <3>; + }; + + reset-controller@88010000 { + compatible = "sirf,prima2-rstc"; + reg = <0x88010000 0x1000>; + }; + + rsc-controller@88020000 { + compatible = "sirf,prima2-rsc"; + reg = <0x88020000 0x1000>; + }; + }; + + mem-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x90000000 0x90000000 0x10000>; + + memory-controller@90000000 { + compatible = "sirf,prima2-memc"; + reg = <0x90000000 0x10000>; + interrupts = <27>; + }; + }; + + disp-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x90010000 0x90010000 0x30000>; + + display@90010000 { + compatible = "sirf,prima2-lcd"; + reg = <0x90010000 0x20000>; + interrupts = <30>; + }; + + vpp@90020000 { + compatible = "sirf,prima2-vpp"; + reg = <0x90020000 0x10000>; + interrupts = <31>; + }; + }; + + graphics-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x98000000 0x98000000 0x8000000>; + + graphics@98000000 { + compatible = "powervr,sgx531"; + reg = <0x98000000 0x8000000>; + interrupts = <6>; + }; + }; + + multimedia-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xa0000000 0xa0000000 0x8000000>; + + multimedia@a0000000 { + compatible = "sirf,prima2-video-codec"; + reg = <0xa0000000 0x8000000>; + interrupts = <5>; + }; + }; + + dsp-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xa8000000 0xa8000000 0x2000000>; + + dspif@a8000000 { + compatible = "sirf,prima2-dspif"; + reg = <0xa8000000 0x10000>; + interrupts = <9>; + }; + + gps@a8010000 { + compatible = "sirf,prima2-gps"; + reg = <0xa8010000 0x10000>; + interrupts = <7>; + }; + + dsp@a9000000 { + compatible = "sirf,prima2-dsp"; + reg = <0xa9000000 0x1000000>; + interrupts = <8>; + }; + }; + + peri-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb0000000 0xb0000000 0x180000>; + + timer@b0020000 { + compatible = "sirf,prima2-tick"; + reg = <0xb0020000 0x1000>; + interrupts = <0>; + }; + + nand@b0030000 { + compatible = "sirf,prima2-nand"; + reg = <0xb0030000 0x10000>; + interrupts = <41>; + }; + + audio@b0040000 { + compatible = "sirf,prima2-audio"; + reg = <0xb0040000 0x10000>; + interrupts = <35>; + }; + + uart0: uart@b0050000 { + cell-index = <0>; + compatible = "sirf,prima2-uart"; + reg = <0xb0050000 0x10000>; + interrupts = <17>; + }; + + uart1: uart@b0060000 { + cell-index = <1>; + compatible = "sirf,prima2-uart"; + reg = <0xb0060000 0x10000>; + interrupts = <18>; + }; + + uart2: uart@b0070000 { + cell-index = <2>; + compatible = "sirf,prima2-uart"; + reg = <0xb0070000 0x10000>; + interrupts = <19>; + }; + + usp0: usp@b0080000 { + cell-index = <0>; + compatible = "sirf,prima2-usp"; + reg = <0xb0080000 0x10000>; + interrupts = <20>; + }; + + usp1: usp@b0090000 { + cell-index = <1>; + compatible = "sirf,prima2-usp"; + reg = <0xb0090000 0x10000>; + interrupts = <21>; + }; + + usp2: usp@b00a0000 { + cell-index = <2>; + compatible = "sirf,prima2-usp"; + reg = <0xb00a0000 0x10000>; + interrupts = <22>; + }; + + dmac0: dma-controller@b00b0000 { + cell-index = <0>; + compatible = "sirf,prima2-dmac"; + reg = <0xb00b0000 0x10000>; + interrupts = <12>; + }; + + dmac1: dma-controller@b0160000 { + cell-index = <1>; + compatible = "sirf,prima2-dmac"; + reg = <0xb0160000 0x10000>; + interrupts = <13>; + }; + + vip@b00C0000 { + compatible = "sirf,prima2-vip"; + reg = <0xb00C0000 0x10000>; + }; + + spi0: spi@b00d0000 { + cell-index = <0>; + compatible = "sirf,prima2-spi"; + reg = <0xb00d0000 0x10000>; + interrupts = <15>; + }; + + spi1: spi@b0170000 { + cell-index = <1>; + compatible = "sirf,prima2-spi"; + reg = <0xb0170000 0x10000>; + interrupts = <16>; + }; + + i2c0: i2c@b00e0000 { + cell-index = <0>; + compatible = "sirf,prima2-i2c"; + reg = <0xb00e0000 0x10000>; + interrupts = <24>; + }; + + i2c1: i2c@b00f0000 { + cell-index = <1>; + compatible = "sirf,prima2-i2c"; + reg = <0xb00f0000 0x10000>; + interrupts = <25>; + }; + + tsc@b0110000 { + compatible = "sirf,prima2-tsc"; + reg = <0xb0110000 0x10000>; + interrupts = <33>; + }; + + gpio: pinctrl@b0120000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "sirf,prima2-pinctrl"; + reg = <0xb0120000 0x10000>; + interrupts = <43 44 45 46 47>; + gpio-controller; + interrupt-controller; + + lcd_16pins_a: lcd0@0 { + lcd { + sirf,pins = "lcd_16bitsgrp"; + sirf,function = "lcd_16bits"; + }; + }; + lcd_18pins_a: lcd0@1 { + lcd { + sirf,pins = "lcd_18bitsgrp"; + sirf,function = "lcd_18bits"; + }; + }; + lcd_24pins_a: lcd0@2 { + lcd { + sirf,pins = "lcd_24bitsgrp"; + sirf,function = "lcd_24bits"; + }; + }; + lcdrom_pins_a: lcdrom0@0 { + lcd { + sirf,pins = "lcdromgrp"; + sirf,function = "lcdrom"; + }; + }; + uart0_pins_a: uart0@0 { + uart { + sirf,pins = "uart0grp"; + sirf,function = "uart0"; + }; + }; + uart1_pins_a: uart1@0 { + uart { + sirf,pins = "uart1grp"; + sirf,function = "uart1"; + }; + }; + uart2_pins_a: uart2@0 { + uart { + sirf,pins = "uart2grp"; + sirf,function = "uart2"; + }; + }; + uart2_noflow_pins_a: uart2@1 { + uart { + sirf,pins = "uart2_nostreamctrlgrp"; + sirf,function = "uart2_nostreamctrl"; + }; + }; + spi0_pins_a: spi0@0 { + spi { + sirf,pins = "spi0grp"; + sirf,function = "spi0"; + }; + }; + spi1_pins_a: spi1@0 { + spi { + sirf,pins = "spi1grp"; + sirf,function = "spi1"; + }; + }; + i2c0_pins_a: i2c0@0 { + i2c { + sirf,pins = "i2c0grp"; + sirf,function = "i2c0"; + }; + }; + i2c1_pins_a: i2c1@0 { + i2c { + sirf,pins = "i2c1grp"; + sirf,function = "i2c1"; + }; + }; + pwm0_pins_a: pwm0@0 { + pwm { + sirf,pins = "pwm0grp"; + sirf,function = "pwm0"; + }; + }; + pwm1_pins_a: pwm1@0 { + pwm { + sirf,pins = "pwm1grp"; + sirf,function = "pwm1"; + }; + }; + pwm2_pins_a: pwm2@0 { + pwm { + sirf,pins = "pwm2grp"; + sirf,function = "pwm2"; + }; + }; + pwm3_pins_a: pwm3@0 { + pwm { + sirf,pins = "pwm3grp"; + sirf,function = "pwm3"; + }; + }; + gps_pins_a: gps@0 { + gps { + sirf,pins = "gpsgrp"; + sirf,function = "gps"; + }; + }; + vip_pins_a: vip@0 { + vip { + sirf,pins = "vipgrp"; + sirf,function = "vip"; + }; + }; + sdmmc0_pins_a: sdmmc0@0 { + sdmmc0 { + sirf,pins = "sdmmc0grp"; + sirf,function = "sdmmc0"; + }; + }; + sdmmc1_pins_a: sdmmc1@0 { + sdmmc1 { + sirf,pins = "sdmmc1grp"; + sirf,function = "sdmmc1"; + }; + }; + sdmmc2_pins_a: sdmmc2@0 { + sdmmc2 { + sirf,pins = "sdmmc2grp"; + sirf,function = "sdmmc2"; + }; + }; + sdmmc3_pins_a: sdmmc3@0 { + sdmmc3 { + sirf,pins = "sdmmc3grp"; + sirf,function = "sdmmc3"; + }; + }; + sdmmc4_pins_a: sdmmc4@0 { + sdmmc4 { + sirf,pins = "sdmmc4grp"; + sirf,function = "sdmmc4"; + }; + }; + sdmmc5_pins_a: sdmmc5@0 { + sdmmc5 { + sirf,pins = "sdmmc5grp"; + sirf,function = "sdmmc5"; + }; + }; + i2s_pins_a: i2s@0 { + i2s { + sirf,pins = "i2sgrp"; + sirf,function = "i2s"; + }; + }; + ac97_pins_a: ac97@0 { + ac97 { + sirf,pins = "ac97grp"; + sirf,function = "ac97"; + }; + }; + nand_pins_a: nand@0 { + nand { + sirf,pins = "nandgrp"; + sirf,function = "nand"; + }; + }; + usp0_pins_a: usp0@0 { + usp0 { + sirf,pins = "usp0grp"; + sirf,function = "usp0"; + }; + }; + usp1_pins_a: usp1@0 { + usp1 { + sirf,pins = "usp1grp"; + sirf,function = "usp1"; + }; + }; + usp2_pins_a: usp2@0 { + usp2 { + sirf,pins = "usp2grp"; + sirf,function = "usp2"; + }; + }; + usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { + usb0_utmi_drvbus { + sirf,pins = "usb0_utmi_drvbusgrp"; + sirf,function = "usb0_utmi_drvbus"; + }; + }; + usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { + usb1_utmi_drvbus { + sirf,pins = "usb1_utmi_drvbusgrp"; + sirf,function = "usb1_utmi_drvbus"; + }; + }; + warm_rst_pins_a: warm_rst@0 { + warm_rst { + sirf,pins = "warm_rstgrp"; + sirf,function = "warm_rst"; + }; + }; + pulse_count_pins_a: pulse_count@0 { + pulse_count { + sirf,pins = "pulse_countgrp"; + sirf,function = "pulse_count"; + }; + }; + cko0_rst_pins_a: cko0_rst@0 { + cko0_rst { + sirf,pins = "cko0_rstgrp"; + sirf,function = "cko0_rst"; + }; + }; + cko1_rst_pins_a: cko1_rst@0 { + cko1_rst { + sirf,pins = "cko1_rstgrp"; + sirf,function = "cko1_rst"; + }; + }; + }; + + pwm@b0130000 { + compatible = "sirf,prima2-pwm"; + reg = <0xb0130000 0x10000>; + }; + + efusesys@b0140000 { + compatible = "sirf,prima2-efuse"; + reg = <0xb0140000 0x10000>; + }; + + pulsec@b0150000 { + compatible = "sirf,prima2-pulsec"; + reg = <0xb0150000 0x10000>; + interrupts = <48>; + }; + + pci-iobg { + compatible = "sirf,prima2-pciiobg", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56000000 0x56000000 0x1b00000>; + + sd0: sdhci@56000000 { + cell-index = <0>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56000000 0x100000>; + interrupts = <38>; + }; + + sd1: sdhci@56100000 { + cell-index = <1>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56100000 0x100000>; + interrupts = <38>; + }; + + sd2: sdhci@56200000 { + cell-index = <2>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56200000 0x100000>; + interrupts = <23>; + }; + + sd3: sdhci@56300000 { + cell-index = <3>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56300000 0x100000>; + interrupts = <23>; + }; + + sd4: sdhci@56400000 { + cell-index = <4>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56400000 0x100000>; + interrupts = <39>; + }; + + sd5: sdhci@56500000 { + cell-index = <5>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56500000 0x100000>; + interrupts = <39>; + }; + + pci-copy@57900000 { + compatible = "sirf,prima2-pcicp"; + reg = <0x57900000 0x100000>; + interrupts = <40>; + }; + + rom-interface@57a00000 { + compatible = "sirf,prima2-romif"; + reg = <0x57a00000 0x100000>; + }; + }; + }; + + rtc-iobg { + compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80030000 0x10000>; + + gpsrtc@1000 { + compatible = "sirf,prima2-gpsrtc"; + reg = <0x1000 0x1000>; + interrupts = <55 56 57>; + }; + + sysrtc@2000 { + compatible = "sirf,prima2-sysrtc"; + reg = <0x2000 0x1000>; + interrupts = <52 53 54>; + }; + + pwrc@3000 { + compatible = "sirf,prima2-pwrc"; + reg = <0x3000 0x1000>; + interrupts = <32>; + }; + }; + + uus-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb8000000 0xb8000000 0x40000>; + + usb0: usb@b00e0000 { + compatible = "chipidea,ci13611a-prima2"; + reg = <0xb8000000 0x10000>; + interrupts = <10>; + }; + + usb1: usb@b00f0000 { + compatible = "chipidea,ci13611a-prima2"; + reg = <0xb8010000 0x10000>; + interrupts = <11>; + }; + + sata@b00f0000 { + compatible = "synopsys,dwc-ahsata"; + reg = <0xb8020000 0x10000>; + interrupts = <37>; + }; + + security@b00f0000 { + compatible = "sirf,prima2-security"; + reg = <0xb8030000 0x10000>; + interrupts = <42>; + }; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/pxa27x.dtsi b/trunk/arch/arm/boot/dts/pxa27x.dtsi new file mode 100644 index 000000000000..d7c5d721a5c7 --- /dev/null +++ b/trunk/arch/arm/boot/dts/pxa27x.dtsi @@ -0,0 +1,14 @@ +/* The pxa3xx skeleton simply augments the 2xx version */ +/include/ "pxa2xx.dtsi" + +/ { + model = "Marvell PXA27x familiy SoC"; + compatible = "marvell,pxa27x"; + + pxabus { + pxairq: interrupt-controller@40d00000 { + marvell,intc-priority; + marvell,intc-nr-irqs = <34>; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/pxa2xx.dtsi b/trunk/arch/arm/boot/dts/pxa2xx.dtsi new file mode 100644 index 000000000000..f18aad35e8b3 --- /dev/null +++ b/trunk/arch/arm/boot/dts/pxa2xx.dtsi @@ -0,0 +1,132 @@ +/* + * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC + * + * Copyright (C) 2011 Marek Vasut + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Marvell PXA2xx family SoC"; + compatible = "marvell,pxa2xx"; + interrupt-parent = <&pxairq>; + + aliases { + serial0 = &ffuart; + serial1 = &btuart; + serial2 = &stuart; + serial3 = &hwuart; + i2c0 = &pwri2c; + i2c1 = &pxai2c1; + }; + + cpus { + cpu@0 { + compatible = "arm,xscale"; + }; + }; + + pxabus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pxairq: interrupt-controller@40d00000 { + #interrupt-cells = <1>; + compatible = "marvell,pxa-intc"; + interrupt-controller; + interrupt-parent; + marvell,intc-nr-irqs = <32>; + reg = <0x40d00000 0xd0>; + }; + + gpio: gpio@40e00000 { + compatible = "mrvl,pxa-gpio"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x40e00000 0x10000>; + gpio-controller; + #gpio-cells = <0x2>; + interrupts = <10>; + interrupt-names = "gpio_mux"; + interrupt-controller; + #interrupt-cells = <0x2>; + ranges; + + gcb0: gpio@40e00000 { + reg = <0x40e00000 0x4>; + }; + + gcb1: gpio@40e00004 { + reg = <0x40e00004 0x4>; + }; + + gcb2: gpio@40e00008 { + reg = <0x40e00008 0x4>; + }; + gcb3: gpio@40e0000c { + reg = <0x40e0000c 0x4>; + }; + }; + + ffuart: uart@40100000 { + compatible = "mrvl,pxa-uart"; + reg = <0x40100000 0x30>; + interrupts = <22>; + status = "disabled"; + }; + + btuart: uart@40200000 { + compatible = "mrvl,pxa-uart"; + reg = <0x40200000 0x30>; + interrupts = <21>; + status = "disabled"; + }; + + stuart: uart@40700000 { + compatible = "mrvl,pxa-uart"; + reg = <0x40700000 0x30>; + interrupts = <20>; + status = "disabled"; + }; + + hwuart: uart@41100000 { + compatible = "mrvl,pxa-uart"; + reg = <0x41100000 0x30>; + interrupts = <7>; + status = "disabled"; + }; + + pxai2c1: i2c@40301680 { + compatible = "mrvl,pxa-i2c"; + reg = <0x40301680 0x30>; + interrupts = <18>; + #address-cells = <0x1>; + #size-cells = <0>; + status = "disabled"; + }; + + usb0: ohci@4c000000 { + compatible = "mrvl,pxa-ohci"; + reg = <0x4c000000 0x10000>; + interrupts = <3>; + status = "disabled"; + }; + + mmc0: mmc@41100000 { + compatible = "mrvl,pxa-mmc"; + reg = <0x41100000 0x1000>; + interrupts = <23>; + status = "disabled"; + }; + + rtc@40900000 { + compatible = "marvell,pxa-rtc"; + reg = <0x40900000 0x3c>; + interrupts = <30 31>; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/pxa3xx.dtsi b/trunk/arch/arm/boot/dts/pxa3xx.dtsi new file mode 100644 index 000000000000..f9d92da86783 --- /dev/null +++ b/trunk/arch/arm/boot/dts/pxa3xx.dtsi @@ -0,0 +1,32 @@ +/* The pxa3xx skeleton simply augments the 2xx version */ +/include/ "pxa2xx.dtsi" + +/ { + model = "Marvell PXA3xx familiy SoC"; + compatible = "marvell,pxa3xx"; + + pxabus { + pwri2c: i2c@40f500c0 { + compatible = "mrvl,pwri2c"; + reg = <0x40f500c0 0x30>; + interrupts = <6>; + #address-cells = <0x1>; + #size-cells = <0>; + status = "disabled"; + }; + + nand0: nand@43100000 { + compatible = "marvell,pxa3xx-nand"; + reg = <0x43100000 90>; + interrupts = <45>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + pxairq: interrupt-controller@40d00000 { + marvell,intc-priority; + marvell,intc-nr-irqs = <56>; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/pxa910.dtsi b/trunk/arch/arm/boot/dts/pxa910.dtsi index aebf32de73b4..a3be44d86bcd 100644 --- a/trunk/arch/arm/boot/dts/pxa910.dtsi +++ b/trunk/arch/arm/boot/dts/pxa910.dtsi @@ -25,6 +25,11 @@ interrupt-parent = <&intc>; ranges; + L2: l2-cache { + compatible = "marvell,tauros2-cache"; + marvell,tauros2-cache-features = <0x3>; + }; + axi@d4200000 { /* AXI */ compatible = "mrvl,axi-bus", "simple-bus"; #address-cells = <1>; diff --git a/trunk/arch/arm/boot/dts/tegra20-harmony.dts b/trunk/arch/arm/boot/dts/tegra20-harmony.dts index f146dbf6f7f8..c3ef1ad26b6a 100644 --- a/trunk/arch/arm/boot/dts/tegra20-harmony.dts +++ b/trunk/arch/arm/boot/dts/tegra20-harmony.dts @@ -275,6 +275,160 @@ i2c@7000d000 { status = "okay"; clock-frequency = <400000>; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + regulator@4 { + reg = <4>; + regulator-compatible = "ldo0"; + regulator-name = "vdd_ldo0,vddio_pex_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; + regulator-name = "vdd_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; }; pmc { @@ -310,6 +464,72 @@ bus-width = <8>; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 0>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 0>; + enable-active-high; + }; + + regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd_1v05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&pmic 2 0>; + enable-active-high; + /* Hack until board-harmony-pcie.c is removed */ + status = "disabled"; + }; + + regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio 22 0>; /* gpio PC6 */ + enable-active-high; + }; + + regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio 176 0>; /* gpio PW0 */ + enable-active-high; + }; + }; + sound { compatible = "nvidia,tegra-audio-wm8903-harmony", "nvidia,tegra-audio-wm8903"; diff --git a/trunk/arch/arm/boot/dts/tegra20-medcom-wide.dts b/trunk/arch/arm/boot/dts/tegra20-medcom-wide.dts new file mode 100644 index 000000000000..a2d6d6541f83 --- /dev/null +++ b/trunk/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -0,0 +1,58 @@ +/dts-v1/; + +/include/ "tegra20-tamonten.dtsi" + +/ { + model = "Avionic Design Medcom-Wide board"; + compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; + + i2c@7000c000 { + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <187 0x04>; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff + 0xffffffff + 0 + 0xffffffff + 0xffffffff>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + sound { + compatible = "ad,tegra-audio-wm8903-medcom-wide", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Avionic Design Medcom-Wide"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + }; +}; diff --git a/trunk/arch/arm/boot/dts/tegra20-paz00.dts b/trunk/arch/arm/boot/dts/tegra20-paz00.dts index 684a9e1ff7e9..ddf287f52d49 100644 --- a/trunk/arch/arm/boot/dts/tegra20-paz00.dts +++ b/trunk/arch/arm/boot/dts/tegra20-paz00.dts @@ -272,12 +272,170 @@ status = "okay"; clock-frequency = <400000>; + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&p5valw_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; + regulator-name = "+1.2vs_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; + regulator-name = "+1.0vs_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; + regulator-name = "+3.7vs_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; + regulator-name = "+1.1vs_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; + regulator-name = "+1.2vs_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; + regulator-name = "+3.3vs_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; + regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; + regulator-name = "+2.85vs_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; + /* + * Research indicates this should be + * 1.8v; other boards that use this + * rail for the same purpose need it + * set to 1.8v. The schematic signal + * name is incorrect; perhaps copied + * from an incorrect NVIDIA reference. + */ + regulator-name = "+2.85vs_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; + regulator-name = "+3.3vs_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; + regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; + regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; + regulator-name = "+3.3vs_rtc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + adt7461@4c { compatible = "adi,adt7461"; reg = <0x4c>; }; }; + pmc { + nvidia,invert-interrupt; + }; + usb@c5000000 { status = "okay"; }; @@ -325,6 +483,21 @@ }; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + p5valw_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "+5valw"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; + sound { compatible = "nvidia,tegra-audio-alc5632-paz00", "nvidia,tegra-audio-alc5632"; diff --git a/trunk/arch/arm/boot/dts/tegra20-plutux.dts b/trunk/arch/arm/boot/dts/tegra20-plutux.dts new file mode 100644 index 000000000000..331a3ef24d59 --- /dev/null +++ b/trunk/arch/arm/boot/dts/tegra20-plutux.dts @@ -0,0 +1,50 @@ +/dts-v1/; + +/include/ "tegra20-tamonten.dtsi" + +/ { + model = "Avionic Design Plutux board"; + compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; + + i2c@7000c000 { + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <187 0x04>; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff + 0xffffffff + 0 + 0xffffffff + 0xffffffff>; + }; + }; + + sound { + compatible = "ad,tegra-audio-plutux", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Avionic Design Plutux"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + }; +}; diff --git a/trunk/arch/arm/boot/dts/tegra20-seaboard.dts b/trunk/arch/arm/boot/dts/tegra20-seaboard.dts index 85e621ab2968..e60dc7124e92 100644 --- a/trunk/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/trunk/arch/arm/boot/dts/tegra20-seaboard.dts @@ -374,6 +374,154 @@ status = "okay"; clock-frequency = <400000>; + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-always-on; + }; + + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; + regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + temperature-sensor@4c { compatible = "nct1008"; reg = <0x4c>; @@ -387,6 +535,10 @@ }; }; + pmc { + nvidia,invert-interrupt; + }; + memory-controller@0x7000f400 { emc-table@190000 { reg = <190000>; @@ -473,6 +625,40 @@ }; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 0>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 0>; + enable-active-high; + }; + }; + sound { compatible = "nvidia,tegra-audio-wm8903-seaboard", "nvidia,tegra-audio-wm8903"; diff --git a/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi b/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi new file mode 100644 index 000000000000..f18cec9f6a77 --- /dev/null +++ b/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -0,0 +1,449 @@ +/include/ "tegra20.dtsi" + +/ { + model = "Avionic Design Tamonten SOM"; + compatible = "ad,tamonten", "nvidia,tegra20"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", + "spia", "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + dta { + nvidia,pins = "dta", "dtd"; + nvidia,function = "sdio2"; + }; + dtb { + nvidia,pins = "dtb", "dtc", "dte"; + nvidia,function = "rsvd1"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint", "pta"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uarta"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ld0", "ld1", "ld2", + "ld3", "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", "ld12", + "ld13", "ld14", "ld15", "ld16", "ld17", + "ldc", "ldi", "lhp0", "lhp1", "lhp2", + "lhs", "lm0", "lm1", "lpp", "lpw0", + "lpw1", "lpw2", "lsc0", "lsc1", "lsck", + "lsda", "lsdi", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "pwm"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", "ate", + "cdev1", "cdev2", "dap1", "dtb", "gma", + "gmb", "gmc", "gmd", "gme", "gpu7", + "gpv", "i2cp", "pta", "rm", "slxa", + "slxk", "spia", "spib", "uac"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = <0>; + }; + conf_csus { + nvidia,pins = "csus", "spid", "spif"; + nvidia,pull = <1>; + nvidia,tristate = <1>; + }; + conf_crtp { + nvidia,pins = "crtp", "dap2", "dap3", "dap4", + "dtc", "dte", "dtf", "gpu", "sdio1", + "slxc", "slxd", "spdi", "spdo", "spig", + "uda"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + conf_ddc { + nvidia,pins = "ddc", "dta", "dtd", "kbca", + "kbcb", "kbcc", "kbcd", "kbce", "kbcf", + "sdc"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsc1", "lsck", "lsda", "lsdi", + "lvp0", "owc", "sdb"; + nvidia,tristate = <1>; + }; + conf_irrx { + nvidia,pins = "irrx", "irtx", "sdd", "spic", + "spie", "spih", "uaa", "uab", "uad", + "uca", "ucb"; + nvidia,pull = <2>; + nvidia,tristate = <1>; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = <2>; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lspi", "lvp1", + "lvs", "pmc"; + nvidia,tristate = <0>; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = <1>; + }; + }; + }; + + i2s@70002800 { + status = "okay"; + }; + + serial@70006300 { + clock-frequency = <216000000>; + status = "okay"; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + status = "okay"; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + status = "okay"; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; + regulator-name = "vdd_sys_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; + regulator-name = "vdd_sys_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; + regulator-name = "vdd_sys_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + regulator@4 { + reg = <4>; + regulator-compatible = "ldo0"; + regulator-name = "vdd_ldo0,vddio_pex_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; + regulator-name = "vdd_ldo6,avdd_vdac"; + /* + * According to the Tegra 2 Automotive + * DataSheet, a typical value for this + * would be 2.8V, but the PMIC only + * supports 2.85V. + */ + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; + regulator-name = "vdd_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; + regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; + /* + * According to the Tegra 2 Automotive + * DataSheet, a typical value for this + * would be 2.8V, but the PMIC only + * supports 2.85V. + */ + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; + regulator-name = "vdd_rtc_out"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + }; + + pmc { + nvidia,invert-interrupt; + }; + + usb@c5008000 { + status = "okay"; + }; + + sdhci@c8000600 { + cd-gpios = <&gpio 58 0>; /* gpio PH2 */ + wp-gpios = <&gpio 59 0>; /* gpio PH3 */ + bus-width = <4>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/tegra20-tec.dts b/trunk/arch/arm/boot/dts/tegra20-tec.dts new file mode 100644 index 000000000000..9aff31b0fe4a --- /dev/null +++ b/trunk/arch/arm/boot/dts/tegra20-tec.dts @@ -0,0 +1,53 @@ +/dts-v1/; + +/include/ "tegra20-tamonten.dtsi" + +/ { + model = "Avionic Design Tamonten Evaluation Carrier"; + compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; + + i2c@7000c000 { + clock-frequency = <400000>; + status = "okay"; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <187 0x04>; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff + 0xffffffff + 0 + 0xffffffff + 0xffffffff>; + }; + }; + + sound { + compatible = "ad,tegra-audio-wm8903-tec", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Avionic Design TEC"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + }; +}; diff --git a/trunk/arch/arm/boot/dts/tegra20-ventana.dts b/trunk/arch/arm/boot/dts/tegra20-ventana.dts index be90544e6b59..3e5952fcfbc5 100644 --- a/trunk/arch/arm/boot/dts/tegra20-ventana.dts +++ b/trunk/arch/arm/boot/dts/tegra20-ventana.dts @@ -289,6 +289,158 @@ i2c@7000d000 { status = "okay"; clock-frequency = <400000>; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + }; + + pmc { + nvidia,invert-interrupt; }; usb@c5000000 { @@ -317,6 +469,60 @@ bus-width = <8>; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 0>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 0>; + enable-active-high; + }; + + regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio 22 0>; /* gpio PC6 */ + enable-active-high; + }; + + regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio 176 0>; /* gpio PW0 */ + enable-active-high; + }; + }; + sound { compatible = "nvidia,tegra-audio-wm8903-ventana", "nvidia,tegra-audio-wm8903"; diff --git a/trunk/arch/arm/boot/dts/tegra20-whistler.dts b/trunk/arch/arm/boot/dts/tegra20-whistler.dts index 6916310bf58f..c636d002d6d8 100644 --- a/trunk/arch/arm/boot/dts/tegra20-whistler.dts +++ b/trunk/arch/arm/boot/dts/tegra20-whistler.dts @@ -261,6 +261,286 @@ gpio-controller; #gpio-cells = <2>; }; + + max8907@3c { + compatible = "maxim,max8907"; + reg = <0x3c>; + interrupts = <0 86 0x4>; + + maxim,system-power-controller; + + mbatt-supply = <&usb0_vbus_reg>; + in-v1-supply = <&mbatt_reg>; + in-v2-supply = <&mbatt_reg>; + in-v3-supply = <&mbatt_reg>; + in1-supply = <&mbatt_reg>; + in2-supply = <&nvvdd_sv3_reg>; + in3-supply = <&mbatt_reg>; + in4-supply = <&mbatt_reg>; + in5-supply = <&mbatt_reg>; + in6-supply = <&mbatt_reg>; + in7-supply = <&mbatt_reg>; + in8-supply = <&mbatt_reg>; + in9-supply = <&mbatt_reg>; + in10-supply = <&mbatt_reg>; + in11-supply = <&mbatt_reg>; + in12-supply = <&mbatt_reg>; + in13-supply = <&mbatt_reg>; + in14-supply = <&mbatt_reg>; + in15-supply = <&mbatt_reg>; + in16-supply = <&mbatt_reg>; + in17-supply = <&nvvdd_sv3_reg>; + in18-supply = <&nvvdd_sv3_reg>; + in19-supply = <&mbatt_reg>; + in20-supply = <&mbatt_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + mbatt_reg: regulator@0 { + reg = <0>; + regulator-compatible = "mbatt"; + regulator-name = "vbat_pmu"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sd1"; + regulator-name = "nvvdd_sv1,vdd_cpu_pmu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sd2"; + regulator-name = "nvvdd_sv2,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + nvvdd_sv3_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sd3"; + regulator-name = "nvvdd_sv3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@4 { + reg = <4>; + regulator-compatible = "ldo1"; + regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo2"; + regulator-name = "nvvdd_ldo2,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo3"; + regulator-name = "nvvdd_ldo3,vcom_1v8b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo4"; + regulator-name = "nvvdd_ldo4,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo5"; + regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo6"; + regulator-name = "nvvdd_ldo6,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo7"; + regulator-name = "nvvdd_ldo7,avddio_audio"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo8"; + regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo9"; + regulator-name = "nvvdd_ldo9,avdd_cam*"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo10"; + regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo11"; + regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@15 { + reg = <15>; + regulator-compatible = "ldo12"; + regulator-name = "nvvdd_ldo12,vddio_sdio"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + regulator@16 { + reg = <16>; + regulator-compatible = "ldo13"; + regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + regulator@17 { + reg = <17>; + regulator-compatible = "ldo14"; + regulator-name = "nvvdd_ldo14,avdd_vdac"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + regulator@18 { + reg = <18>; + regulator-compatible = "ldo15"; + regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@19 { + reg = <19>; + regulator-compatible = "ldo16"; + regulator-name = "nvvdd_ldo16,vdd_dbrtr"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + regulator@20 { + reg = <20>; + regulator-compatible = "ldo17"; + regulator-name = "nvvdd_ldo17,vddio_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@21 { + reg = <21>; + regulator-compatible = "ldo18"; + regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@22 { + reg = <22>; + regulator-compatible = "ldo19"; + regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + regulator@23 { + reg = <23>; + regulator-compatible = "ldo20"; + regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + regulator@24 { + reg = <24>; + regulator-compatible = "out5v"; + regulator-name = "usb0_vbus_reg"; + }; + + regulator@25 { + reg = <25>; + regulator-compatible = "out33v"; + regulator-name = "pmu_out3v3"; + }; + + regulator@26 { + reg = <26>; + regulator-compatible = "bbat"; + regulator-name = "pmu_bbat"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2400000>; + regulator-always-on; + }; + + regulator@27 { + reg = <27>; + regulator-compatible = "sdby"; + regulator-name = "vdd_aon"; + regulator-always-on; + }; + + regulator@28 { + reg = <28>; + regulator-compatible = "vrtc"; + regulator-name = "vrtc,pmu_vccadc"; + regulator-always-on; + }; + }; + }; + }; + + pmc { + nvidia,invert-interrupt; }; usb@c5000000 { @@ -284,6 +564,21 @@ bus-width = <8>; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb0_vbus_reg: regulator { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; + sound { compatible = "nvidia,tegra-audio-wm8753-whistler", "nvidia,tegra-audio-wm8753"; diff --git a/trunk/arch/arm/boot/dts/tegra20.dtsi b/trunk/arch/arm/boot/dts/tegra20.dtsi index 405d1673904e..67a6cd910b96 100644 --- a/trunk/arch/arm/boot/dts/tegra20.dtsi +++ b/trunk/arch/arm/boot/dts/tegra20.dtsi @@ -123,7 +123,7 @@ status = "disabled"; }; - pwm { + pwm: pwm { compatible = "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; diff --git a/trunk/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/trunk/arch/arm/boot/dts/tegra30-cardhu-a02.dts new file mode 100644 index 000000000000..dd4222f00eca --- /dev/null +++ b/trunk/arch/arm/boot/dts/tegra30-cardhu-a02.dts @@ -0,0 +1,87 @@ +/dts-v1/; + +/include/ "tegra30-cardhu.dtsi" + +/* This dts file support the cardhu A02 version of board */ + +/ { + model = "NVIDIA Tegra30 Cardhu A02 evaluation board"; + compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30"; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + ddr_reg: regulator@100 { + compatible = "regulator-fixed"; + reg = <100>; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 0>; + }; + + sys_3v3_reg: regulator@101 { + compatible = "regulator-fixed"; + reg = <101>; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 0>; + }; + + usb1_vbus_reg: regulator@102 { + compatible = "regulator-fixed"; + reg = <102>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio 68 0>; /* GPIO PI4 */ + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + usb3_vbus_reg: regulator@103 { + compatible = "regulator-fixed"; + reg = <103>; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio 63 0>; /* GPIO PH7 */ + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + vdd_5v0_reg: regulator@104 { + compatible = "regulator-fixed"; + reg = <104>; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 2 0>; + }; + + vdd_bl_reg: regulator@105 { + compatible = "regulator-fixed"; + reg = <105>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio 83 0>; /* GPIO PK3 */ + }; + }; +}; + diff --git a/trunk/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/trunk/arch/arm/boot/dts/tegra30-cardhu-a04.dts new file mode 100644 index 000000000000..0828f097ca86 --- /dev/null +++ b/trunk/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -0,0 +1,98 @@ +/dts-v1/; + +/include/ "tegra30-cardhu.dtsi" + +/* This dts file support the cardhu A04 and later versions of board */ + +/ { + model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board"; + compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30"; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + ddr_reg: regulator@100 { + compatible = "regulator-fixed"; + regulator-name = "ddr"; + reg = <100>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 0>; + }; + + sys_3v3_reg: regulator@101 { + compatible = "regulator-fixed"; + reg = <101>; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 0>; + }; + + usb1_vbus_reg: regulator@102 { + compatible = "regulator-fixed"; + reg = <102>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio 238 0>; /* GPIO PDD6 */ + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + usb3_vbus_reg: regulator@103 { + compatible = "regulator-fixed"; + reg = <103>; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio 236 0>; /* GPIO PDD4 */ + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + vdd_5v0_reg: regulator@104 { + compatible = "regulator-fixed"; + reg = <104>; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 8 0>; + }; + + vdd_bl_reg: regulator@105 { + compatible = "regulator-fixed"; + reg = <105>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio 234 0>; /* GPIO PDD2 */ + }; + + vdd_bl2_reg: regulator@106 { + compatible = "regulator-fixed"; + reg = <106>; + regulator-name = "vdd_bl2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio 232 0>; /* GPIO PDD0 */ + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/tegra30-cardhu.dts b/trunk/arch/arm/boot/dts/tegra30-cardhu.dts deleted file mode 100644 index c169bced131e..000000000000 --- a/trunk/arch/arm/boot/dts/tegra30-cardhu.dts +++ /dev/null @@ -1,171 +0,0 @@ -/dts-v1/; - -/include/ "tegra30.dtsi" - -/ { - model = "NVIDIA Tegra30 Cardhu evaluation board"; - compatible = "nvidia,cardhu", "nvidia,tegra30"; - - memory { - reg = <0x80000000 0x40000000>; - }; - - pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - }; - }; - - serial@70006000 { - status = "okay"; - clock-frequency = <408000000>; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - - /* ALS and Proximity sensor */ - isl29028@44 { - compatible = "isil,isl29028"; - reg = <0x44>; - interrupt-parent = <&gpio>; - interrupts = <88 0x04>; /*gpio PL0 */ - }; - }; - - i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = <179 0x04>; /* gpio PW3 */ - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - }; - - tps62361 { - compatible = "ti,tps62361"; - reg = <0x60>; - - regulator-name = "tps62361-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - }; - }; - - ahub { - i2s@70080400 { - status = "okay"; - }; - }; - - sdhci@78000000 { - status = "okay"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ - wp-gpios = <&gpio 155 0>; /* gpio PT3 */ - power-gpios = <&gpio 31 0>; /* gpio PD7 */ - bus-width = <4>; - }; - - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-cardhu", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Cardhu"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 0>; - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ - }; -}; diff --git a/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi b/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi new file mode 100644 index 000000000000..d10c9c5a3606 --- /dev/null +++ b/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -0,0 +1,475 @@ +/include/ "tegra30.dtsi" + +/** + * This file contains common DT entry for all fab version of Cardhu. + * There is multiple fab version of Cardhu starting from A01 to A07. + * Cardhu fab version A01 and A03 are not supported. Cardhu fab version + * A02 will have different sets of GPIOs for fixed regulator compare to + * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are + * compatible with fab version A04. Based on Cardhu fab version, the + * related dts file need to be chosen like for Cardhu fab version A02, + * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use + * tegra30-cardhu-a04.dts. + * The identification of board is done in two ways, by looking the sticker + * on PCB and by reading board id eeprom. + * The stciker will have number like 600-81291-1000-002 C.3. In this 4th + * number is the fab version like here it is 002 and hence fab version A02. + * The (downstream internal) U-Boot of Cardhu display the board-id as + * follows: + * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00 + * In this Fab version is 02 i.e. A02. + * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56). + * The location 0x8 of this eeprom contains the Fab version. It is 1 byte + * wide. + */ + +/ { + model = "NVIDIA Tegra30 Cardhu evaluation board"; + compatible = "nvidia,cardhu", "nvidia,tegra30"; + + memory { + reg = <0x80000000 0x40000000>; + }; + + pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4", + "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + }; + }; + + serial@70006000 { + status = "okay"; + clock-frequency = <408000000>; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + + /* ALS and Proximity sensor */ + isl29028@44 { + compatible = "isil,isl29028"; + reg = <0x44>; + interrupt-parent = <&gpio>; + interrupts = <88 0x04>; /*gpio PL0 */ + }; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <179 0x04>; /* gpio PW3 */ + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + }; + + tps62361 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + }; + + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = <0 86 0x4>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_ac_bat_reg>; + vcc2-supply = <&vdd_ac_bat_reg>; + vcc3-supply = <&vio_reg>; + vcc4-supply = <&vdd_5v0_reg>; + vcc5-supply = <&vdd_ac_bat_reg>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_ac_bat_reg>; + vccio-supply = <&vdd_ac_bat_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + vdd1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "vdd1"; + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "vdd2"; + regulator-name = "vdd_1v5_gen"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vddctrl_reg: regulator@2 { + reg = <2>; + regulator-compatible = "vddctrl"; + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vio_reg: regulator@3 { + reg = <3>; + regulator-compatible = "vio"; + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo1_reg: regulator@4 { + reg = <4>; + regulator-compatible = "ldo1"; + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo2_reg: regulator@5 { + reg = <5>; + regulator-compatible = "ldo2"; + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + /* LDO3 is not connected to anything */ + + ldo4_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo4"; + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo5"; + regulator-name = "vddio_sdmmc,avdd_vdac"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo6_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo6"; + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo7"; + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo8"; + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + }; + + ahub { + i2s@70080400 { + status = "okay"; + }; + }; + + pmc { + status = "okay"; + nvidia,invert-interrupt; + }; + + sdhci@78000000 { + status = "okay"; + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 155 0>; /* gpio PT3 */ + power-gpios = <&gpio 31 0>; /* gpio PD7 */ + bus-width = <4>; + }; + + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_ac_bat_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + cam_1v8_reg: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "cam_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&gpio 220 0>; /* gpio PBB4 */ + vin-supply = <&vio_reg>; + }; + + cp_5v_reg: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cp_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */ + }; + + emmc_3v3_reg: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "emmc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio 25 0>; /* gpio PD1 */ + vin-supply = <&sys_3v3_reg>; + }; + + modem_3v3_reg: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "modem_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio 30 0>; /* gpio PD6 */ + }; + + pex_hvdd_3v3_reg: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "pex_hvdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio 95 0>; /* gpio PL7 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam1_ldo_reg: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "vdd_cam1_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&gpio 142 0>; /* gpio PR6 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam2_ldo_reg: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "vdd_cam2_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&gpio 143 0>; /* gpio PR7 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam3_ldo_reg: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "vdd_cam3_ldo"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio 144 0>; /* gpio PS0 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_com_reg: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "vdd_com"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio 24 0>; /* gpio PD0 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_fuse_3v3_reg: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "vdd_fuse_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio 94 0>; /* gpio PL6 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_pnl1_reg: regulator@11 { + compatible = "regulator-fixed"; + reg = <11>; + regulator-name = "vdd_pnl1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio 92 0>; /* gpio PL4 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_vid_reg: regulator@12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "vddio_vid"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio 152 0>; /* GPIO PT0 */ + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-cardhu", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Cardhu"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + }; +}; diff --git a/trunk/arch/arm/boot/dts/tegra30.dtsi b/trunk/arch/arm/boot/dts/tegra30.dtsi index 3e4334d14efb..b1497c7d7d68 100644 --- a/trunk/arch/arm/boot/dts/tegra30.dtsi +++ b/trunk/arch/arm/boot/dts/tegra30.dtsi @@ -117,7 +117,7 @@ status = "disabled"; }; - pwm { + pwm: pwm { compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; diff --git a/trunk/arch/arm/boot/dts/tps65217.dtsi b/trunk/arch/arm/boot/dts/tps65217.dtsi new file mode 100644 index 000000000000..a63272422d76 --- /dev/null +++ b/trunk/arch/arm/boot/dts/tps65217.dtsi @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Integrated Power Management Chip + * http://www.ti.com/lit/ds/symlink/tps65217.pdf + */ + +&tps { + compatible = "ti,tps65217"; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + dcdc1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "dcdc1"; + }; + + dcdc2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "dcdc2"; + }; + + dcdc3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "dcdc3"; + }; + + ldo1_reg: regulator@3 { + reg = <3>; + regulator-compatible = "ldo1"; + }; + + ldo2_reg: regulator@4 { + reg = <4>; + regulator-compatible = "ldo2"; + }; + + ldo3_reg: regulator@5 { + reg = <5>; + regulator-compatible = "ldo3"; + }; + + ldo4_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo4"; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/tps65910.dtsi b/trunk/arch/arm/boot/dts/tps65910.dtsi new file mode 100644 index 000000000000..92693a89160e --- /dev/null +++ b/trunk/arch/arm/boot/dts/tps65910.dtsi @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Integrated Power Management Chip + * http://www.ti.com/lit/ds/symlink/tps65910.pdf + */ + +&tps { + compatible = "ti,tps65910"; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + vrtc_reg: regulator@0 { + reg = <0>; + regulator-compatible = "vrtc"; + }; + + vio_reg: regulator@1 { + reg = <1>; + regulator-compatible = "vio"; + }; + + vdd1_reg: regulator@2 { + reg = <2>; + regulator-compatible = "vdd1"; + }; + + vdd2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "vdd2"; + }; + + vdd3_reg: regulator@4 { + reg = <4>; + regulator-compatible = "vdd3"; + }; + + vdig1_reg: regulator@5 { + reg = <5>; + regulator-compatible = "vdig1"; + }; + + vdig2_reg: regulator@6 { + reg = <6>; + regulator-compatible = "vdig2"; + }; + + vpll_reg: regulator@7 { + reg = <7>; + regulator-compatible = "vpll"; + }; + + vdac_reg: regulator@8 { + reg = <8>; + regulator-compatible = "vdac"; + }; + + vaux1_reg: regulator@9 { + reg = <9>; + regulator-compatible = "vaux1"; + }; + + vaux2_reg: regulator@10 { + reg = <10>; + regulator-compatible = "vaux2"; + }; + + vaux33_reg: regulator@11 { + reg = <11>; + regulator-compatible = "vaux33"; + }; + + vmmc_reg: regulator@12 { + reg = <12>; + regulator-compatible = "vmmc"; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/twl4030.dtsi b/trunk/arch/arm/boot/dts/twl4030.dtsi index 22f4d1394ed3..ff000172c93c 100644 --- a/trunk/arch/arm/boot/dts/twl4030.dtsi +++ b/trunk/arch/arm/boot/dts/twl4030.dtsi @@ -19,19 +19,19 @@ interrupts = <11>; }; - vdac: regulator@0 { + vdac: regulator-vdac { compatible = "ti,twl4030-vdac"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vpll2: regulator@1 { + vpll2: regulator-vpll2 { compatible = "ti,twl4030-vpll2"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vmmc1: regulator@2 { + vmmc1: regulator-vmmc1 { compatible = "ti,twl4030-vmmc1"; regulator-min-microvolt = <1850000>; regulator-max-microvolt = <3150000>; diff --git a/trunk/arch/arm/boot/dts/twl6030.dtsi b/trunk/arch/arm/boot/dts/twl6030.dtsi index d351b27d7213..123e2c40218a 100644 --- a/trunk/arch/arm/boot/dts/twl6030.dtsi +++ b/trunk/arch/arm/boot/dts/twl6030.dtsi @@ -20,70 +20,70 @@ interrupts = <11>; }; - vaux1: regulator@0 { + vaux1: regulator-vaux1 { compatible = "ti,twl6030-vaux1"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <3000000>; }; - vaux2: regulator@1 { + vaux2: regulator-vaux2 { compatible = "ti,twl6030-vaux2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <2800000>; }; - vaux3: regulator@2 { + vaux3: regulator-vaux3 { compatible = "ti,twl6030-vaux3"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <3000000>; }; - vmmc: regulator@3 { + vmmc: regulator-vmmc { compatible = "ti,twl6030-vmmc"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3000000>; }; - vpp: regulator@4 { + vpp: regulator-vpp { compatible = "ti,twl6030-vpp"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2500000>; }; - vusim: regulator@5 { + vusim: regulator-vusim { compatible = "ti,twl6030-vusim"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <2900000>; }; - vdac: regulator@6 { + vdac: regulator-vdac { compatible = "ti,twl6030-vdac"; }; - vana: regulator@7 { + vana: regulator-vana { compatible = "ti,twl6030-vana"; }; - vcxio: regulator@8 { + vcxio: regulator-vcxio { compatible = "ti,twl6030-vcxio"; regulator-always-on; }; - vusb: regulator@9 { + vusb: regulator-vusb { compatible = "ti,twl6030-vusb"; }; - v1v8: regulator@10 { + v1v8: regulator-v1v8 { compatible = "ti,twl6030-v1v8"; regulator-always-on; }; - v2v1: regulator@11 { + v2v1: regulator-v2v1 { compatible = "ti,twl6030-v2v1"; regulator-always-on; }; - clk32kg: regulator@12 { + clk32kg: regulator-clk32kg { compatible = "ti,twl6030-clk32kg"; }; }; diff --git a/trunk/arch/arm/configs/bcm2835_defconfig b/trunk/arch/arm/configs/bcm2835_defconfig new file mode 100644 index 000000000000..7aea70253c63 --- /dev/null +++ b/trunk/arch/arm/configs/bcm2835_defconfig @@ -0,0 +1,95 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_FHANDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_PERF=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_NAMESPACES=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_JUMP_LABEL=y +# CONFIG_BLOCK is not set +CONFIG_ARCH_BCM2835=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_AEABI=y +CONFIG_COMPACTION=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_CLEANCACHE=y +CONFIG_SECCOMP=y +CONFIG_CC_STACKPROTECTOR=y +CONFIG_KEXEC=y +CONFIG_CRASH_DUMP=y +CONFIG_VFP=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_SUSPEND is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_UNIX98_PTYS is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_TTY_PRINTK=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_IOMMU_SUPPORT is not set +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_PROC_FS is not set +# CONFIG_SYSFS is not set +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_PRINTK_TIME=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_UNUSED_SYMBOLS=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_SCHED_TRACER=y +CONFIG_STACK_TRACER=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_KGDB=y +CONFIG_KGDB_KDB=y +CONFIG_TEST_KSTRTOX=y +CONFIG_STRICT_DEVMEM=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_ARM is not set +# CONFIG_XZ_DEC_ARMTHUMB is not set +# CONFIG_XZ_DEC_SPARC is not set diff --git a/trunk/arch/arm/configs/imx_v6_v7_defconfig b/trunk/arch/arm/configs/imx_v6_v7_defconfig index 3c9f32f9b6b4..565132d02105 100644 --- a/trunk/arch/arm/configs/imx_v6_v7_defconfig +++ b/trunk/arch/arm/configs/imx_v6_v7_defconfig @@ -32,9 +32,7 @@ CONFIG_MACH_VPR200=y CONFIG_MACH_IMX51_DT=y CONFIG_MACH_MX51_3DS=y CONFIG_MACH_EUKREA_CPUIMX51SD=y -CONFIG_MACH_MX51_EFIKAMX=y -CONFIG_MACH_MX51_EFIKASB=y -CONFIG_MACH_IMX53_DT=y +CONFIG_SOC_IMX53=y CONFIG_SOC_IMX6Q=y CONFIG_MXC_PWM=y CONFIG_SMP=y diff --git a/trunk/arch/arm/configs/kzm9d_defconfig b/trunk/arch/arm/configs/kzm9d_defconfig index 26146ffea1a5..8c49df66cac3 100644 --- a/trunk/arch/arm/configs/kzm9d_defconfig +++ b/trunk/arch/arm/configs/kzm9d_defconfig @@ -8,6 +8,7 @@ CONFIG_LOG_BUF_SHIFT=16 CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL_SYSCALL=y CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y CONFIG_SLAB=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set diff --git a/trunk/arch/arm/configs/kzm9g_defconfig b/trunk/arch/arm/configs/kzm9g_defconfig index 2388c8610627..5d0c66708960 100644 --- a/trunk/arch/arm/configs/kzm9g_defconfig +++ b/trunk/arch/arm/configs/kzm9g_defconfig @@ -14,6 +14,7 @@ CONFIG_NAMESPACES=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL_SYSCALL=y CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y diff --git a/trunk/arch/arm/configs/mxs_defconfig b/trunk/arch/arm/configs/mxs_defconfig index 4edcfb4e4dee..36d60dda310c 100644 --- a/trunk/arch/arm/configs/mxs_defconfig +++ b/trunk/arch/arm/configs/mxs_defconfig @@ -23,12 +23,6 @@ CONFIG_BLK_DEV_INTEGRITY=y # CONFIG_IOSCHED_CFQ is not set CONFIG_ARCH_MXS=y CONFIG_MACH_MXS_DT=y -CONFIG_MACH_MX23EVK=y -CONFIG_MACH_MX28EVK=y -CONFIG_MACH_STMP378X_DEVB=y -CONFIG_MACH_TX28=y -CONFIG_MACH_M28EVK=y -CONFIG_MACH_APX4DEVKIT=y # CONFIG_ARM_THUMB is not set CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y diff --git a/trunk/arch/arm/configs/omap2plus_defconfig b/trunk/arch/arm/configs/omap2plus_defconfig index e58edc36b406..62303043db9c 100644 --- a/trunk/arch/arm/configs/omap2plus_defconfig +++ b/trunk/arch/arm/configs/omap2plus_defconfig @@ -123,6 +123,7 @@ CONFIG_HW_RANDOM=y CONFIG_I2C_CHARDEV=y CONFIG_SPI=y CONFIG_SPI_OMAP24XX=y +CONFIG_PINCTRL_SINGLE=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_TWL4030=y diff --git a/trunk/arch/arm/configs/pnx4008_defconfig b/trunk/arch/arm/configs/pnx4008_defconfig deleted file mode 100644 index 35a31ccacc32..000000000000 --- a/trunk/arch/arm/configs/pnx4008_defconfig +++ /dev/null @@ -1,472 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_AUDIT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_ARCH_PNX4008=y -CONFIG_PREEMPT=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="mem=64M console=ttyS0,115200" -CONFIG_FPE_NWFPE=y -CONFIG_BINFMT_AOUT=m -CONFIG_BINFMT_MISC=m -CONFIG_PM=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_SYN_COOKIES=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_IPV6_PRIVACY=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_TUNNEL=m -CONFIG_NETFILTER=y -CONFIG_IP_VS=m -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m -CONFIG_IP_VS_FTP=m -CONFIG_IP_NF_QUEUE=m -CONFIG_IP6_NF_QUEUE=m -CONFIG_DECNET_NF_GRABULATOR=m -CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m -CONFIG_BRIDGE_EBT_802_3=m -CONFIG_BRIDGE_EBT_AMONG=m -CONFIG_BRIDGE_EBT_ARP=m -CONFIG_BRIDGE_EBT_IP=m -CONFIG_BRIDGE_EBT_LIMIT=m -CONFIG_BRIDGE_EBT_MARK=m -CONFIG_BRIDGE_EBT_PKTTYPE=m -CONFIG_BRIDGE_EBT_STP=m -CONFIG_BRIDGE_EBT_VLAN=m -CONFIG_BRIDGE_EBT_ARPREPLY=m -CONFIG_BRIDGE_EBT_DNAT=m -CONFIG_BRIDGE_EBT_MARK_T=m -CONFIG_BRIDGE_EBT_REDIRECT=m -CONFIG_BRIDGE_EBT_SNAT=m -CONFIG_BRIDGE_EBT_LOG=m -CONFIG_IP_SCTP=m -CONFIG_ATM=y -CONFIG_ATM_CLIP=y -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m -CONFIG_BRIDGE=m -CONFIG_VLAN_8021Q=m -CONFIG_DECNET=m -CONFIG_LLC2=m -CONFIG_IPX=m -CONFIG_ATALK=m -CONFIG_DEV_APPLETALK=m -CONFIG_IPDDP=m -CONFIG_IPDDP_ENCAP=y -CONFIG_IPDDP_DECAP=y -CONFIG_X25=m -CONFIG_LAPB=m -CONFIG_ECONET=m -CONFIG_ECONET_AUNUDP=y -CONFIG_ECONET_NATIVE=y -CONFIG_WAN_ROUTER=m -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_ATM=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -CONFIG_NET_PKTGEN=m -CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_SLRAM=m -CONFIG_MTD_PHRAM=m -CONFIG_MTD_MTDRAM=m -CONFIG_MTD_DOC2000=m -CONFIG_MTD_DOC2001=m -CONFIG_MTD_DOC2001PLUS=m -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_NANDSIM=m -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=y -CONFIG_BLK_DEV_NBD=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_CDROM_PKTCDVD=m -CONFIG_EEPROM_LEGACY=m -CONFIG_SCSI=m -CONFIG_BLK_DEV_SD=m -CONFIG_CHR_DEV_ST=m -CONFIG_CHR_DEV_OSST=m -CONFIG_BLK_DEV_SR=m -CONFIG_CHR_DEV_SG=m -CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_MULTI_LUN=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SPI_ATTRS=m -CONFIG_SCSI_FC_ATTRS=m -CONFIG_SCSI_DEBUG=m -CONFIG_NETDEVICES=y -CONFIG_DUMMY=m -CONFIG_BONDING=m -CONFIG_EQUALIZER=m -CONFIG_TUN=m -CONFIG_NET_ETHERNET=y -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_USBNET=m -# CONFIG_USB_NET_CDC_SUBSET is not set -CONFIG_WAN=y -CONFIG_HDLC=m -CONFIG_HDLC_RAW=m -CONFIG_HDLC_RAW_ETH=m -CONFIG_HDLC_CISCO=m -CONFIG_HDLC_FR=m -CONFIG_HDLC_PPP=m -CONFIG_HDLC_X25=m -CONFIG_DLCI=m -CONFIG_WAN_ROUTER_DRIVERS=m -CONFIG_LAPBETHER=m -CONFIG_X25_ASY=m -CONFIG_ATM_TCP=m -CONFIG_PPP=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_MPPE=m -CONFIG_PPPOE=m -CONFIG_PPPOATM=m -CONFIG_SLIP=m -CONFIG_SLIP_COMPRESSED=y -CONFIG_SLIP_SMART=y -CONFIG_SLIP_MODE_SLIP6=y -CONFIG_NETCONSOLE=m -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_JOYDEV=m -CONFIG_INPUT_EVDEV=m -CONFIG_INPUT_EVBUG=m -CONFIG_KEYBOARD_LKKBD=m -CONFIG_KEYBOARD_NEWTON=m -CONFIG_KEYBOARD_SUNKBD=m -CONFIG_KEYBOARD_XTKBD=m -CONFIG_MOUSE_PS2=m -CONFIG_MOUSE_SERIAL=m -CONFIG_MOUSE_VSXXXAA=m -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_ANALOG=m -CONFIG_JOYSTICK_A3D=m -CONFIG_JOYSTICK_ADI=m -CONFIG_JOYSTICK_COBRA=m -CONFIG_JOYSTICK_GF2K=m -CONFIG_JOYSTICK_GRIP=m -CONFIG_JOYSTICK_GRIP_MP=m -CONFIG_JOYSTICK_GUILLEMOT=m -CONFIG_JOYSTICK_INTERACT=m -CONFIG_JOYSTICK_SIDEWINDER=m -CONFIG_JOYSTICK_TMDC=m -CONFIG_JOYSTICK_IFORCE=m -CONFIG_JOYSTICK_IFORCE_USB=y -CONFIG_JOYSTICK_IFORCE_232=y -CONFIG_JOYSTICK_WARRIOR=m -CONFIG_JOYSTICK_MAGELLAN=m -CONFIG_JOYSTICK_SPACEORB=m -CONFIG_JOYSTICK_SPACEBALL=m -CONFIG_JOYSTICK_STINGER=m -CONFIG_JOYSTICK_JOYDUMP=m -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_GUNZE=m -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=m -CONFIG_SERIO_SERPORT=m -CONFIG_SERIO_RAW=m -CONFIG_GAMEPORT_NS558=m -CONFIG_GAMEPORT_L4=m -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_RSA=y -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_SOFT_WATCHDOG=m -CONFIG_USBPCWATCHDOG=m -# CONFIG_VGA_CONSOLE is not set -CONFIG_SOUND=m -CONFIG_SND=m -CONFIG_SND_SEQUENCER=m -CONFIG_SND_SEQ_DUMMY=m -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -CONFIG_SND_SEQUENCER_OSS=y -CONFIG_SND_DUMMY=m -CONFIG_SND_VIRMIDI=m -CONFIG_SND_MTPAV=m -CONFIG_SND_SERIAL_U16550=m -CONFIG_SND_MPU401=m -CONFIG_SND_USB_AUDIO=m -CONFIG_SOUND_PRIME=m -CONFIG_USB_HID=m -CONFIG_USB_HIDDEV=y -CONFIG_USB_KBD=m -CONFIG_USB_MOUSE=m -CONFIG_USB=y -CONFIG_USB_DEVICEFS=y -CONFIG_USB_MON=y -CONFIG_USB_SL811_HCD=m -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_STORAGE=m -CONFIG_USB_STORAGE_DATAFAB=m -CONFIG_USB_STORAGE_FREECOM=m -CONFIG_USB_STORAGE_USBAT=m -CONFIG_USB_STORAGE_SDDR09=m -CONFIG_USB_STORAGE_SDDR55=m -CONFIG_USB_STORAGE_JUMPSHOT=m -CONFIG_USB_MDC800=m -CONFIG_USB_MICROTEK=m -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_SAFE=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_RIO500=m -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_LED=m -CONFIG_USB_CYTHERM=m -CONFIG_USB_TEST=m -CONFIG_USB_ATM=m -CONFIG_USB_SPEEDTOUCH=m -CONFIG_USB_GADGET=m -CONFIG_USB_GADGET_DUMMY_HCD=y -CONFIG_USB_ZERO=m -CONFIG_USB_ETH=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_FILE_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_MMC=m -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=m -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_REISERFS_FS=m -CONFIG_REISERFS_FS_XATTR=y -CONFIG_REISERFS_FS_POSIX_ACL=y -CONFIG_REISERFS_FS_SECURITY=y -CONFIG_JFS_FS=m -CONFIG_JFS_POSIX_ACL=y -CONFIG_JFS_STATISTICS=y -CONFIG_XFS_FS=m -CONFIG_XFS_QUOTA=y -CONFIG_XFS_POSIX_ACL=y -CONFIG_XFS_RT=y -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V1=m -CONFIG_QFMT_V2=m -CONFIG_AUTOFS_FS=m -CONFIG_AUTOFS4_FS=m -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_NTFS_FS=m -CONFIG_TMPFS=y -CONFIG_ADFS_FS=m -CONFIG_AFFS_FS=m -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_JFFS2_FS=m -CONFIG_CRAMFS=y -CONFIG_VXFS_FS=m -CONFIG_MINIX_FS=m -CONFIG_HPFS_FS=m -CONFIG_QNX4FS_FS=m -CONFIG_ROMFS_FS=m -CONFIG_SYSV_FS=m -CONFIG_UFS_FS=m -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_NFSD=m -CONFIG_NFSD_V4=y -CONFIG_RPCSEC_GSS_SPKM3=m -CONFIG_SMB_FS=m -CONFIG_CIFS=m -CONFIG_NCP_FS=m -CONFIG_NCPFS_PACKET_SIGNING=y -CONFIG_NCPFS_IOCTL_LOCKING=y -CONFIG_NCPFS_STRONG=y -CONFIG_NCPFS_NFS_NS=y -CONFIG_NCPFS_OS2_NS=y -CONFIG_NCPFS_NLS=y -CONFIG_NCPFS_EXTRAS=y -CONFIG_CODA_FS=m -CONFIG_AFS_FS=m -CONFIG_PARTITION_ADVANCED=y -CONFIG_ACORN_PARTITION=y -CONFIG_ACORN_PARTITION_ICS=y -CONFIG_ACORN_PARTITION_RISCIX=y -CONFIG_OSF_PARTITION=y -CONFIG_AMIGA_PARTITION=y -CONFIG_ATARI_PARTITION=y -CONFIG_MAC_PARTITION=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_UNIXWARE_DISKLABEL=y -CONFIG_LDM_PARTITION=y -CONFIG_SGI_PARTITION=y -CONFIG_ULTRIX_PARTITION=y -CONFIG_SUN_PARTITION=y -CONFIG_NLS_DEFAULT="cp437" -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_SECURITY=y -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRC16=m diff --git a/trunk/arch/arm/configs/prima2_defconfig b/trunk/arch/arm/configs/prima2_defconfig index c328ac65479a..807d4e2acb17 100644 --- a/trunk/arch/arm/configs/prima2_defconfig +++ b/trunk/arch/arm/configs/prima2_defconfig @@ -1,4 +1,6 @@ CONFIG_EXPERIMENTAL=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y @@ -8,9 +10,7 @@ CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y CONFIG_BSD_DISKLABEL=y CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_ARCH_PRIMA2=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y +CONFIG_ARCH_SIRF=y CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_KEXEC=y @@ -36,7 +36,6 @@ CONFIG_SPI=y CONFIG_SPI_SIRF=y CONFIG_SPI_SPIDEV=y # CONFIG_HWMON is not set -# CONFIG_HID_SUPPORT is not set CONFIG_USB_GADGET=y CONFIG_USB_FILE_STORAGE=m CONFIG_USB_MASS_STORAGE=m diff --git a/trunk/arch/arm/configs/tegra_defconfig b/trunk/arch/arm/configs/tegra_defconfig index db2245353f0f..0d6bb738c6de 100644 --- a/trunk/arch/arm/configs/tegra_defconfig +++ b/trunk/arch/arm/configs/tegra_defconfig @@ -145,6 +145,8 @@ CONFIG_MMC_SDHCI_TEGRA=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_EM3027=y CONFIG_RTC_DRV_TEGRA=y +CONFIG_DMADEVICES=y +CONFIG_TEGRA20_APB_DMA=y CONFIG_STAGING=y CONFIG_SENSORS_ISL29018=y CONFIG_SENSORS_ISL29028=y diff --git a/trunk/arch/arm/include/asm/gpio.h b/trunk/arch/arm/include/asm/gpio.h index c402e9b31f4c..477e0206e016 100644 --- a/trunk/arch/arm/include/asm/gpio.h +++ b/trunk/arch/arm/include/asm/gpio.h @@ -6,7 +6,9 @@ #endif /* not all ARM platforms necessarily support this API ... */ +#ifdef CONFIG_NEED_MACH_GPIO_H #include +#endif #ifndef __ARM_GPIOLIB_COMPLEX /* Note: this may rely upon the value of ARCH_NR_GPIOS set in mach/gpio.h */ diff --git a/trunk/arch/arm/include/asm/hardware/cache-tauros2.h b/trunk/arch/arm/include/asm/hardware/cache-tauros2.h index 538f17ca905b..295e2e40151b 100644 --- a/trunk/arch/arm/include/asm/hardware/cache-tauros2.h +++ b/trunk/arch/arm/include/asm/hardware/cache-tauros2.h @@ -8,4 +8,7 @@ * warranty of any kind, whether express or implied. */ -extern void __init tauros2_init(void); +#define CACHE_TAUROS2_PREFETCH_ON (1 << 0) +#define CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1) + +extern void __init tauros2_init(unsigned int features); diff --git a/trunk/arch/arm/include/asm/hardware/iop3xx.h b/trunk/arch/arm/include/asm/hardware/iop3xx.h index 2ff2c75a4639..02fe2fbe2477 100644 --- a/trunk/arch/arm/include/asm/hardware/iop3xx.h +++ b/trunk/arch/arm/include/asm/hardware/iop3xx.h @@ -217,18 +217,8 @@ extern int iop3xx_get_init_atu(void); #define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 #define IOP3XX_PCI_MEM_WINDOW_SIZE 0x08000000 -#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000 #define IOP3XX_PCI_LOWER_IO_PA 0x90000000 -#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000 -#define IOP3XX_PCI_LOWER_IO_BA 0x90000000 -#define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\ - IOP3XX_PCI_IO_WINDOW_SIZE - 1) -#define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\ - IOP3XX_PCI_IO_WINDOW_SIZE - 1) -#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) (addr) -\ - IOP3XX_PCI_LOWER_IO_PA) +\ - IOP3XX_PCI_LOWER_IO_VA) - +#define IOP3XX_PCI_LOWER_IO_BA 0x00000000 #ifndef __ASSEMBLY__ diff --git a/trunk/arch/arm/include/asm/io.h b/trunk/arch/arm/include/asm/io.h index 815c669fec0a..8f4db67533e5 100644 --- a/trunk/arch/arm/include/asm/io.h +++ b/trunk/arch/arm/include/asm/io.h @@ -113,11 +113,19 @@ static inline void __iomem *__typesafe_io(unsigned long addr) #define __iowmb() do { } while (0) #endif +/* PCI fixed i/o mapping */ +#define PCI_IO_VIRT_BASE 0xfee00000 + +extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); + /* * Now, pick up the machine-defined IO definitions */ #ifdef CONFIG_NEED_MACH_IO_H #include +#elif defined(CONFIG_PCI) +#define IO_SPACE_LIMIT ((resource_size_t)0xfffff) +#define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT)) #else #define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT) #endif diff --git a/trunk/arch/arm/include/asm/mach/arch.h b/trunk/arch/arm/include/asm/mach/arch.h index 0b1c94b8c652..917d4fcfd9b4 100644 --- a/trunk/arch/arm/include/asm/mach/arch.h +++ b/trunk/arch/arm/include/asm/mach/arch.h @@ -14,6 +14,12 @@ struct tag; struct meminfo; struct sys_timer; struct pt_regs; +struct smp_operations; +#ifdef CONFIG_SMP +#define smp_ops(ops) (&(ops)) +#else +#define smp_ops(ops) (struct smp_operations *)NULL +#endif struct machine_desc { unsigned int nr; /* architecture number */ @@ -35,6 +41,7 @@ struct machine_desc { unsigned char reserve_lp1 :1; /* never has lp1 */ unsigned char reserve_lp2 :1; /* never has lp2 */ char restart_mode; /* default restart mode */ + struct smp_operations *smp; /* SMP operations */ void (*fixup)(struct tag *, char **, struct meminfo *); void (*reserve)(void);/* reserve mem blocks */ diff --git a/trunk/arch/arm/include/asm/mach/map.h b/trunk/arch/arm/include/asm/mach/map.h index a6efcdd6fd25..195ac2f9d3d3 100644 --- a/trunk/arch/arm/include/asm/mach/map.h +++ b/trunk/arch/arm/include/asm/mach/map.h @@ -9,6 +9,9 @@ * * Page table mapping constructs and function prototypes */ +#ifndef __ASM_MACH_MAP_H +#define __ASM_MACH_MAP_H + #include struct map_desc { @@ -34,6 +37,8 @@ struct map_desc { #ifdef CONFIG_MMU extern void iotable_init(struct map_desc *, int); +extern void vm_reserve_area_early(unsigned long addr, unsigned long size, + void *caller); struct mem_type; extern const struct mem_type *get_mem_type(unsigned int type); @@ -44,4 +49,7 @@ extern int ioremap_page(unsigned long virt, unsigned long phys, const struct mem_type *mtype); #else #define iotable_init(map,num) do { } while (0) +#define vm_reserve_area_early(a,s,c) do { } while (0) +#endif + #endif diff --git a/trunk/arch/arm/include/asm/mach/pci.h b/trunk/arch/arm/include/asm/mach/pci.h index 26c511fddf8f..db9fedb57f2c 100644 --- a/trunk/arch/arm/include/asm/mach/pci.h +++ b/trunk/arch/arm/include/asm/mach/pci.h @@ -11,6 +11,8 @@ #ifndef __ASM_MACH_PCI_H #define __ASM_MACH_PCI_H +#include + struct pci_sys_data; struct pci_ops; struct pci_bus; @@ -42,6 +44,8 @@ struct pci_sys_data { unsigned long io_offset; /* bus->cpu IO mapping offset */ struct pci_bus *bus; /* PCI bus */ struct list_head resources; /* root bus resources (apertures) */ + struct resource io_res; + char io_res_name[12]; /* Bridge swizzling */ u8 (*swizzle)(struct pci_dev *, u8 *); /* IRQ mapping */ @@ -54,6 +58,15 @@ struct pci_sys_data { */ void pci_common_init(struct hw_pci *); +/* + * Setup early fixed I/O mapping. + */ +#if defined(CONFIG_PCI) +extern void pci_map_io_early(unsigned long pfn); +#else +static inline void pci_map_io_early(unsigned long pfn) {} +#endif + /* * PCI controllers */ diff --git a/trunk/arch/arm/include/asm/perf_event.h b/trunk/arch/arm/include/asm/perf_event.h index e074948d8143..625cd621a436 100644 --- a/trunk/arch/arm/include/asm/perf_event.h +++ b/trunk/arch/arm/include/asm/perf_event.h @@ -12,6 +12,13 @@ #ifndef __ARM_PERF_EVENT_H__ #define __ARM_PERF_EVENT_H__ -/* Nothing to see here... */ +/* + * The ARMv7 CPU PMU supports up to 32 event counters. + */ +#define ARMPMU_MAX_HWEVENTS 32 + +#define HW_OP_UNSUPPORTED 0xFFFF +#define C(_x) PERF_COUNT_HW_CACHE_##_x +#define CACHE_OP_UNSUPPORTED 0xFFFF #endif /* __ARM_PERF_EVENT_H__ */ diff --git a/trunk/arch/arm/include/asm/pmu.h b/trunk/arch/arm/include/asm/pmu.h index 4432305f4a2a..a26170dce02e 100644 --- a/trunk/arch/arm/include/asm/pmu.h +++ b/trunk/arch/arm/include/asm/pmu.h @@ -15,15 +15,6 @@ #include #include -/* - * Types of PMUs that can be accessed directly and require mutual - * exclusion between profiling tools. - */ -enum arm_pmu_type { - ARM_PMU_DEVICE_CPU = 0, - ARM_NUM_PMU_DEVICES, -}; - /* * struct arm_pmu_platdata - ARM PMU platform data * @@ -31,54 +22,24 @@ enum arm_pmu_type { * interrupt and passed the address of the low level handler, * and can be used to implement any platform specific handling * before or after calling it. - * @enable_irq: an optional handler which will be called after - * request_irq and be used to handle some platform specific - * irq enablement - * @disable_irq: an optional handler which will be called before - * free_irq and be used to handle some platform specific - * irq disablement + * @runtime_resume: an optional handler which will be called by the + * runtime PM framework following a call to pm_runtime_get(). + * Note that if pm_runtime_get() is called more than once in + * succession this handler will only be called once. + * @runtime_suspend: an optional handler which will be called by the + * runtime PM framework following a call to pm_runtime_put(). + * Note that if pm_runtime_get() is called more than once in + * succession this handler will only be called following the + * final call to pm_runtime_put() that actually disables the + * hardware. */ struct arm_pmu_platdata { irqreturn_t (*handle_irq)(int irq, void *dev, irq_handler_t pmu_handler); - void (*enable_irq)(int irq); - void (*disable_irq)(int irq); + int (*runtime_resume)(struct device *dev); + int (*runtime_suspend)(struct device *dev); }; -#ifdef CONFIG_CPU_HAS_PMU - -/** - * reserve_pmu() - reserve the hardware performance counters - * - * Reserve the hardware performance counters in the system for exclusive use. - * Returns 0 on success or -EBUSY if the lock is already held. - */ -extern int -reserve_pmu(enum arm_pmu_type type); - -/** - * release_pmu() - Relinquish control of the performance counters - * - * Release the performance counters and allow someone else to use them. - */ -extern void -release_pmu(enum arm_pmu_type type); - -#else /* CONFIG_CPU_HAS_PMU */ - -#include - -static inline int -reserve_pmu(enum arm_pmu_type type) -{ - return -ENODEV; -} - -static inline void -release_pmu(enum arm_pmu_type type) { } - -#endif /* CONFIG_CPU_HAS_PMU */ - #ifdef CONFIG_HW_PERF_EVENTS /* The events for a given PMU register set. */ @@ -103,7 +64,6 @@ struct pmu_hw_events { struct arm_pmu { struct pmu pmu; - enum arm_pmu_type type; cpumask_t active_irqs; char *name; irqreturn_t (*handle_irq)(int irq_num, void *dev); @@ -118,6 +78,8 @@ struct arm_pmu { void (*start)(void); void (*stop)(void); void (*reset)(void *); + int (*request_irq)(irq_handler_t handler); + void (*free_irq)(void); int (*map_event)(struct perf_event *event); int num_events; atomic_t active_events; @@ -129,7 +91,9 @@ struct arm_pmu { #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) -int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type); +extern const struct dev_pm_ops armpmu_dev_pm_ops; + +int armpmu_register(struct arm_pmu *armpmu, char *name, int type); u64 armpmu_event_update(struct perf_event *event, struct hw_perf_event *hwc, @@ -139,6 +103,13 @@ int armpmu_event_set_period(struct perf_event *event, struct hw_perf_event *hwc, int idx); +int armpmu_map_event(struct perf_event *event, + const unsigned (*event_map)[PERF_COUNT_HW_MAX], + const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX], + u32 raw_event_mask); + #endif /* CONFIG_HW_PERF_EVENTS */ #endif /* __ARM_PMU_H__ */ diff --git a/trunk/arch/arm/include/asm/smp.h b/trunk/arch/arm/include/asm/smp.h index ae29293270a3..2e3be16c6766 100644 --- a/trunk/arch/arm/include/asm/smp.h +++ b/trunk/arch/arm/include/asm/smp.h @@ -60,15 +60,6 @@ extern int boot_secondary(unsigned int cpu, struct task_struct *); */ asmlinkage void secondary_start_kernel(void); -/* - * Perform platform specific initialisation of the specified CPU. - */ -extern void platform_secondary_init(unsigned int cpu); - -/* - * Initialize cpu_possible map, and enable coherency - */ -extern void platform_smp_prepare_cpus(unsigned int); /* * Initial data for bringing up a secondary CPU. @@ -79,18 +70,47 @@ struct secondary_data { void *stack; }; extern struct secondary_data secondary_data; +extern volatile int pen_release; extern int __cpu_disable(void); -extern int platform_cpu_disable(unsigned int cpu); extern void __cpu_die(unsigned int cpu); extern void cpu_die(void); -extern void platform_cpu_die(unsigned int cpu); -extern int platform_cpu_kill(unsigned int cpu); -extern void platform_cpu_enable(unsigned int cpu); - extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); +struct smp_operations { +#ifdef CONFIG_SMP + /* + * Setup the set of possible CPUs (via set_cpu_possible) + */ + void (*smp_init_cpus)(void); + /* + * Initialize cpu_possible map, and enable coherency + */ + void (*smp_prepare_cpus)(unsigned int max_cpus); + + /* + * Perform platform specific initialisation of the specified CPU. + */ + void (*smp_secondary_init)(unsigned int cpu); + /* + * Boot a secondary CPU, and assign it the specified idle task. + * This also gives us the initial stack to use for this CPU. + */ + int (*smp_boot_secondary)(unsigned int cpu, struct task_struct *idle); +#ifdef CONFIG_HOTPLUG_CPU + int (*cpu_kill)(unsigned int cpu); + void (*cpu_die)(unsigned int cpu); + int (*cpu_disable)(unsigned int cpu); +#endif +#endif +}; + +/* + * set platform specific SMP operations + */ +extern void smp_set_ops(struct smp_operations *); + #endif /* ifndef __ASM_ARM_SMP_H */ diff --git a/trunk/arch/arm/include/asm/timex.h b/trunk/arch/arm/include/asm/timex.h index ce119442277c..963342acebb7 100644 --- a/trunk/arch/arm/include/asm/timex.h +++ b/trunk/arch/arm/include/asm/timex.h @@ -13,7 +13,11 @@ #define _ASMARM_TIMEX_H #include +#ifdef CONFIG_ARCH_MULTIPLATFORM +#define CLOCK_TICK_RATE 1000000 +#else #include +#endif typedef unsigned long cycles_t; diff --git a/trunk/arch/arm/mach-highbank/include/mach/debug-macro.S b/trunk/arch/arm/include/debug/highbank.S similarity index 83% rename from trunk/arch/arm/mach-highbank/include/mach/debug-macro.S rename to trunk/arch/arm/include/debug/highbank.S index cb57fe5bcd04..8cad4322a5a2 100644 --- a/trunk/arch/arm/mach-highbank/include/mach/debug-macro.S +++ b/trunk/arch/arm/include/debug/highbank.S @@ -10,10 +10,8 @@ */ .macro addruart,rp,rv,tmp - movw \rv, #0x6000 - movt \rv, #0xfee3 - movw \rp, #0x6000 - movt \rp, #0xfff3 + ldr \rv, =0xfee36000 + ldr \rp, =0xfff36000 .endm #include diff --git a/trunk/arch/arm/include/debug/icedcc.S b/trunk/arch/arm/include/debug/icedcc.S new file mode 100644 index 000000000000..43afcb021fa3 --- /dev/null +++ b/trunk/arch/arm/include/debug/icedcc.S @@ -0,0 +1,90 @@ +/* + * arch/arm/include/debug/icedcc.S + * + * Copyright (C) 1994-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + + @@ debug using ARM EmbeddedICE DCC channel + + .macro addruart, rp, rv, tmp + .endm + +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) + + .macro senduart, rd, rx + mcr p14, 0, \rd, c0, c5, 0 + .endm + + .macro busyuart, rd, rx +1001: + mrc p14, 0, \rx, c0, c1, 0 + tst \rx, #0x20000000 + beq 1001b + .endm + + .macro waituart, rd, rx + mov \rd, #0x2000000 +1001: + subs \rd, \rd, #1 + bmi 1002f + mrc p14, 0, \rx, c0, c1, 0 + tst \rx, #0x20000000 + bne 1001b +1002: + .endm + +#elif defined(CONFIG_CPU_XSCALE) + + .macro senduart, rd, rx + mcr p14, 0, \rd, c8, c0, 0 + .endm + + .macro busyuart, rd, rx +1001: + mrc p14, 0, \rx, c14, c0, 0 + tst \rx, #0x10000000 + beq 1001b + .endm + + .macro waituart, rd, rx + mov \rd, #0x10000000 +1001: + subs \rd, \rd, #1 + bmi 1002f + mrc p14, 0, \rx, c14, c0, 0 + tst \rx, #0x10000000 + bne 1001b +1002: + .endm + +#else + + .macro senduart, rd, rx + mcr p14, 0, \rd, c1, c0, 0 + .endm + + .macro busyuart, rd, rx +1001: + mrc p14, 0, \rx, c0, c0, 0 + tst \rx, #2 + beq 1001b + + .endm + + .macro waituart, rd, rx + mov \rd, #0x2000000 +1001: + subs \rd, \rd, #1 + bmi 1002f + mrc p14, 0, \rx, c0, c0, 0 + tst \rx, #2 + bne 1001b +1002: + .endm + +#endif /* CONFIG_CPU_V6 */ diff --git a/trunk/arch/arm/mach-mvebu/include/mach/debug-macro.S b/trunk/arch/arm/include/debug/mvebu.S similarity index 86% rename from trunk/arch/arm/mach-mvebu/include/mach/debug-macro.S rename to trunk/arch/arm/include/debug/mvebu.S index 22825760c7e1..865c6d02b332 100644 --- a/trunk/arch/arm/mach-mvebu/include/mach/debug-macro.S +++ b/trunk/arch/arm/include/debug/mvebu.S @@ -11,7 +11,8 @@ * published by the Free Software Foundation. */ -#include +#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 +#define ARMADA_370_XP_REGS_VIRT_BASE 0xfeb00000 .macro addruart, rp, rv, tmp ldr \rp, =ARMADA_370_XP_REGS_PHYS_BASE diff --git a/trunk/arch/arm/mach-picoxcell/include/mach/debug-macro.S b/trunk/arch/arm/include/debug/picoxcell.S similarity index 89% rename from trunk/arch/arm/mach-picoxcell/include/mach/debug-macro.S rename to trunk/arch/arm/include/debug/picoxcell.S index 58d4ee3ae949..7419deb1b948 100644 --- a/trunk/arch/arm/mach-picoxcell/include/mach/debug-macro.S +++ b/trunk/arch/arm/include/debug/picoxcell.S @@ -9,10 +9,10 @@ * accesses to the 8250. */ #include -#include -#include #define UART_SHIFT 2 +#define PICOXCELL_UART1_BASE 0x80230000 +#define PHYS_TO_IO(x) (((x) & 0x00ffffff) | 0xfe000000) .macro addruart, rp, rv, tmp ldr \rv, =PHYS_TO_IO(PICOXCELL_UART1_BASE) diff --git a/trunk/arch/arm/mach-socfpga/include/mach/debug-macro.S b/trunk/arch/arm/include/debug/socfpga.S similarity index 100% rename from trunk/arch/arm/mach-socfpga/include/mach/debug-macro.S rename to trunk/arch/arm/include/debug/socfpga.S diff --git a/trunk/arch/arm/mach-vexpress/include/mach/debug-macro.S b/trunk/arch/arm/include/debug/vexpress.S similarity index 100% rename from trunk/arch/arm/mach-vexpress/include/mach/debug-macro.S rename to trunk/arch/arm/include/debug/vexpress.S diff --git a/trunk/arch/arm/kernel/Makefile b/trunk/arch/arm/kernel/Makefile index 7ad2d5cf7008..1c4321430737 100644 --- a/trunk/arch/arm/kernel/Makefile +++ b/trunk/arch/arm/kernel/Makefile @@ -69,8 +69,7 @@ obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o obj-$(CONFIG_IWMMXT) += iwmmxt.o -obj-$(CONFIG_CPU_HAS_PMU) += pmu.o -obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o +obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_event_cpu.o AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o diff --git a/trunk/arch/arm/kernel/bios32.c b/trunk/arch/arm/kernel/bios32.c index 2b2f25e7fef5..b244696de1a3 100644 --- a/trunk/arch/arm/kernel/bios32.c +++ b/trunk/arch/arm/kernel/bios32.c @@ -13,6 +13,7 @@ #include #include +#include #include static int debug_pci; @@ -423,6 +424,38 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } +static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys) +{ + int ret; + struct pci_host_bridge_window *window; + + if (list_empty(&sys->resources)) { + pci_add_resource_offset(&sys->resources, + &iomem_resource, sys->mem_offset); + } + + list_for_each_entry(window, &sys->resources, list) { + if (resource_type(window->res) == IORESOURCE_IO) + return 0; + } + + sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io; + sys->io_res.end = (busnr + 1) * SZ_64K - 1; + sys->io_res.flags = IORESOURCE_IO; + sys->io_res.name = sys->io_res_name; + sprintf(sys->io_res_name, "PCI%d I/O", busnr); + + ret = request_resource(&ioport_resource, &sys->io_res); + if (ret) { + pr_err("PCI: unable to allocate I/O port region (%d)\n", ret); + return ret; + } + pci_add_resource_offset(&sys->resources, &sys->io_res, + sys->io_offset); + + return 0; +} + static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) { struct pci_sys_data *sys = NULL; @@ -445,11 +478,10 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) ret = hw->setup(nr, sys); if (ret > 0) { - if (list_empty(&sys->resources)) { - pci_add_resource_offset(&sys->resources, - &ioport_resource, sys->io_offset); - pci_add_resource_offset(&sys->resources, - &iomem_resource, sys->mem_offset); + ret = pcibios_init_resources(nr, sys); + if (ret) { + kfree(sys); + break; } if (hw->scan) @@ -627,3 +659,15 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, return 0; } + +void __init pci_map_io_early(unsigned long pfn) +{ + struct map_desc pci_io_desc = { + .virtual = PCI_IO_VIRT_BASE, + .type = MT_DEVICE, + .length = SZ_64K, + }; + + pci_io_desc.pfn = pfn; + iotable_init(&pci_io_desc, 1); +} diff --git a/trunk/arch/arm/kernel/debug.S b/trunk/arch/arm/kernel/debug.S index c45522c36787..66f711b2e0e8 100644 --- a/trunk/arch/arm/kernel/debug.S +++ b/trunk/arch/arm/kernel/debug.S @@ -20,90 +20,9 @@ * references to these in a production kernel! */ -#if defined(CONFIG_DEBUG_ICEDCC) - @@ debug using ARM EmbeddedICE DCC channel - - .macro addruart, rp, rv, tmp - .endm - -#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) - - .macro senduart, rd, rx - mcr p14, 0, \rd, c0, c5, 0 - .endm - - .macro busyuart, rd, rx -1001: - mrc p14, 0, \rx, c0, c1, 0 - tst \rx, #0x20000000 - beq 1001b - .endm - - .macro waituart, rd, rx - mov \rd, #0x2000000 -1001: - subs \rd, \rd, #1 - bmi 1002f - mrc p14, 0, \rx, c0, c1, 0 - tst \rx, #0x20000000 - bne 1001b -1002: - .endm - -#elif defined(CONFIG_CPU_XSCALE) - - .macro senduart, rd, rx - mcr p14, 0, \rd, c8, c0, 0 - .endm - - .macro busyuart, rd, rx -1001: - mrc p14, 0, \rx, c14, c0, 0 - tst \rx, #0x10000000 - beq 1001b - .endm - - .macro waituart, rd, rx - mov \rd, #0x10000000 -1001: - subs \rd, \rd, #1 - bmi 1002f - mrc p14, 0, \rx, c14, c0, 0 - tst \rx, #0x10000000 - bne 1001b -1002: - .endm - -#else - - .macro senduart, rd, rx - mcr p14, 0, \rd, c1, c0, 0 - .endm - - .macro busyuart, rd, rx -1001: - mrc p14, 0, \rx, c0, c0, 0 - tst \rx, #2 - beq 1001b - - .endm - - .macro waituart, rd, rx - mov \rd, #0x2000000 -1001: - subs \rd, \rd, #1 - bmi 1002f - mrc p14, 0, \rx, c0, c0, 0 - tst \rx, #2 - bne 1001b -1002: - .endm - -#endif /* CONFIG_CPU_V6 */ - -#elif !defined(CONFIG_DEBUG_SEMIHOSTING) -#include -#endif /* CONFIG_DEBUG_ICEDCC */ +#if !defined(CONFIG_DEBUG_SEMIHOSTING) +#include CONFIG_DEBUG_LL_INCLUDE +#endif #ifdef CONFIG_MMU .macro addruart_current, rx, tmp1, tmp2 diff --git a/trunk/arch/arm/kernel/head.S b/trunk/arch/arm/kernel/head.S index 3db960e20cb8..9874d0741191 100644 --- a/trunk/arch/arm/kernel/head.S +++ b/trunk/arch/arm/kernel/head.S @@ -23,8 +23,8 @@ #include #include -#ifdef CONFIG_DEBUG_LL -#include +#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING) +#include CONFIG_DEBUG_LL_INCLUDE #endif /* diff --git a/trunk/arch/arm/kernel/perf_event.c b/trunk/arch/arm/kernel/perf_event.c index ab243b87118d..93971b1a4f0b 100644 --- a/trunk/arch/arm/kernel/perf_event.c +++ b/trunk/arch/arm/kernel/perf_event.c @@ -12,68 +12,15 @@ */ #define pr_fmt(fmt) "hw perfevents: " fmt -#include -#include #include -#include -#include #include -#include +#include #include -#include -#include #include #include #include -/* - * ARMv6 supports a maximum of 3 events, starting from index 0. If we add - * another platform that supports more, we need to increase this to be the - * largest of all platforms. - * - * ARMv7 supports up to 32 events: - * cycle counter CCNT + 31 events counters CNT0..30. - * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters. - */ -#define ARMPMU_MAX_HWEVENTS 32 - -static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events); -static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask); -static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events); - -#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) - -/* Set at runtime when we know what CPU type we are. */ -static struct arm_pmu *cpu_pmu; - -const char *perf_pmu_name(void) -{ - if (!cpu_pmu) - return NULL; - - return cpu_pmu->pmu.name; -} -EXPORT_SYMBOL_GPL(perf_pmu_name); - -int perf_num_counters(void) -{ - int max_events = 0; - - if (cpu_pmu != NULL) - max_events = cpu_pmu->num_events; - - return max_events; -} -EXPORT_SYMBOL_GPL(perf_num_counters); - -#define HW_OP_UNSUPPORTED 0xFFFF - -#define C(_x) \ - PERF_COUNT_HW_CACHE_##_x - -#define CACHE_OP_UNSUPPORTED 0xFFFF - static int armpmu_map_cache_event(const unsigned (*cache_map) [PERF_COUNT_HW_CACHE_MAX] @@ -104,7 +51,7 @@ armpmu_map_cache_event(const unsigned (*cache_map) } static int -armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) +armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) { int mapping = (*event_map)[config]; return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; @@ -116,19 +63,20 @@ armpmu_map_raw_event(u32 raw_event_mask, u64 config) return (int)(config & raw_event_mask); } -static int map_cpu_event(struct perf_event *event, - const unsigned (*event_map)[PERF_COUNT_HW_MAX], - const unsigned (*cache_map) - [PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX], - u32 raw_event_mask) +int +armpmu_map_event(struct perf_event *event, + const unsigned (*event_map)[PERF_COUNT_HW_MAX], + const unsigned (*cache_map) + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX], + u32 raw_event_mask) { u64 config = event->attr.config; switch (event->attr.type) { case PERF_TYPE_HARDWARE: - return armpmu_map_event(event_map, config); + return armpmu_map_hw_event(event_map, config); case PERF_TYPE_HW_CACHE: return armpmu_map_cache_event(cache_map, config); case PERF_TYPE_RAW: @@ -222,7 +170,6 @@ armpmu_stop(struct perf_event *event, int flags) */ if (!(hwc->state & PERF_HES_STOPPED)) { armpmu->disable(hwc, hwc->idx); - barrier(); /* why? */ armpmu_event_update(event, hwc, hwc->idx); hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; } @@ -350,99 +297,41 @@ validate_group(struct perf_event *event) return 0; } -static irqreturn_t armpmu_platform_irq(int irq, void *dev) +static irqreturn_t armpmu_dispatch_irq(int irq, void *dev) { struct arm_pmu *armpmu = (struct arm_pmu *) dev; struct platform_device *plat_device = armpmu->plat_device; struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev); - return plat->handle_irq(irq, dev, armpmu->handle_irq); + if (plat && plat->handle_irq) + return plat->handle_irq(irq, dev, armpmu->handle_irq); + else + return armpmu->handle_irq(irq, dev); } static void armpmu_release_hardware(struct arm_pmu *armpmu) { - int i, irq, irqs; - struct platform_device *pmu_device = armpmu->plat_device; - struct arm_pmu_platdata *plat = - dev_get_platdata(&pmu_device->dev); - - irqs = min(pmu_device->num_resources, num_possible_cpus()); - - for (i = 0; i < irqs; ++i) { - if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs)) - continue; - irq = platform_get_irq(pmu_device, i); - if (irq >= 0) { - if (plat && plat->disable_irq) - plat->disable_irq(irq); - free_irq(irq, armpmu); - } - } - - release_pmu(armpmu->type); + armpmu->free_irq(); + pm_runtime_put_sync(&armpmu->plat_device->dev); } static int armpmu_reserve_hardware(struct arm_pmu *armpmu) { - struct arm_pmu_platdata *plat; - irq_handler_t handle_irq; - int i, err, irq, irqs; + int err; struct platform_device *pmu_device = armpmu->plat_device; if (!pmu_device) return -ENODEV; - err = reserve_pmu(armpmu->type); + pm_runtime_get_sync(&pmu_device->dev); + err = armpmu->request_irq(armpmu_dispatch_irq); if (err) { - pr_warning("unable to reserve pmu\n"); + armpmu_release_hardware(armpmu); return err; } - plat = dev_get_platdata(&pmu_device->dev); - if (plat && plat->handle_irq) - handle_irq = armpmu_platform_irq; - else - handle_irq = armpmu->handle_irq; - - irqs = min(pmu_device->num_resources, num_possible_cpus()); - if (irqs < 1) { - pr_err("no irqs for PMUs defined\n"); - return -ENODEV; - } - - for (i = 0; i < irqs; ++i) { - err = 0; - irq = platform_get_irq(pmu_device, i); - if (irq < 0) - continue; - - /* - * If we have a single PMU interrupt that we can't shift, - * assume that we're running on a uniprocessor machine and - * continue. Otherwise, continue without this interrupt. - */ - if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { - pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", - irq, i); - continue; - } - - err = request_irq(irq, handle_irq, - IRQF_DISABLED | IRQF_NOBALANCING, - "arm-pmu", armpmu); - if (err) { - pr_err("unable to request IRQ%d for ARM PMU counters\n", - irq); - armpmu_release_hardware(armpmu); - return err; - } else if (plat && plat->enable_irq) - plat->enable_irq(irq); - - cpumask_set_cpu(i, &armpmu->active_irqs); - } - return 0; } @@ -581,6 +470,32 @@ static void armpmu_disable(struct pmu *pmu) armpmu->stop(); } +#ifdef CONFIG_PM_RUNTIME +static int armpmu_runtime_resume(struct device *dev) +{ + struct arm_pmu_platdata *plat = dev_get_platdata(dev); + + if (plat && plat->runtime_resume) + return plat->runtime_resume(dev); + + return 0; +} + +static int armpmu_runtime_suspend(struct device *dev) +{ + struct arm_pmu_platdata *plat = dev_get_platdata(dev); + + if (plat && plat->runtime_suspend) + return plat->runtime_suspend(dev); + + return 0; +} +#endif + +const struct dev_pm_ops armpmu_dev_pm_ops = { + SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL) +}; + static void __init armpmu_init(struct arm_pmu *armpmu) { atomic_set(&armpmu->active_events, 0); @@ -598,174 +513,14 @@ static void __init armpmu_init(struct arm_pmu *armpmu) }; } -int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type) +int armpmu_register(struct arm_pmu *armpmu, char *name, int type) { armpmu_init(armpmu); + pr_info("enabled with %s PMU driver, %d counters available\n", + armpmu->name, armpmu->num_events); return perf_pmu_register(&armpmu->pmu, name, type); } -/* Include the PMU-specific implementations. */ -#include "perf_event_xscale.c" -#include "perf_event_v6.c" -#include "perf_event_v7.c" - -/* - * Ensure the PMU has sane values out of reset. - * This requires SMP to be available, so exists as a separate initcall. - */ -static int __init -cpu_pmu_reset(void) -{ - if (cpu_pmu && cpu_pmu->reset) - return on_each_cpu(cpu_pmu->reset, NULL, 1); - return 0; -} -arch_initcall(cpu_pmu_reset); - -/* - * PMU platform driver and devicetree bindings. - */ -static struct of_device_id armpmu_of_device_ids[] = { - {.compatible = "arm,cortex-a9-pmu"}, - {.compatible = "arm,cortex-a8-pmu"}, - {.compatible = "arm,arm1136-pmu"}, - {.compatible = "arm,arm1176-pmu"}, - {}, -}; - -static struct platform_device_id armpmu_plat_device_ids[] = { - {.name = "arm-pmu"}, - {}, -}; - -static int __devinit armpmu_device_probe(struct platform_device *pdev) -{ - if (!cpu_pmu) - return -ENODEV; - - cpu_pmu->plat_device = pdev; - return 0; -} - -static struct platform_driver armpmu_driver = { - .driver = { - .name = "arm-pmu", - .of_match_table = armpmu_of_device_ids, - }, - .probe = armpmu_device_probe, - .id_table = armpmu_plat_device_ids, -}; - -static int __init register_pmu_driver(void) -{ - return platform_driver_register(&armpmu_driver); -} -device_initcall(register_pmu_driver); - -static struct pmu_hw_events *armpmu_get_cpu_events(void) -{ - return &__get_cpu_var(cpu_hw_events); -} - -static void __init cpu_pmu_init(struct arm_pmu *armpmu) -{ - int cpu; - for_each_possible_cpu(cpu) { - struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu); - events->events = per_cpu(hw_events, cpu); - events->used_mask = per_cpu(used_mask, cpu); - raw_spin_lock_init(&events->pmu_lock); - } - armpmu->get_hw_events = armpmu_get_cpu_events; - armpmu->type = ARM_PMU_DEVICE_CPU; -} - -/* - * PMU hardware loses all context when a CPU goes offline. - * When a CPU is hotplugged back in, since some hardware registers are - * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading - * junk values out of them. - */ -static int __cpuinit pmu_cpu_notify(struct notifier_block *b, - unsigned long action, void *hcpu) -{ - if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING) - return NOTIFY_DONE; - - if (cpu_pmu && cpu_pmu->reset) - cpu_pmu->reset(NULL); - - return NOTIFY_OK; -} - -static struct notifier_block __cpuinitdata pmu_cpu_notifier = { - .notifier_call = pmu_cpu_notify, -}; - -/* - * CPU PMU identification and registration. - */ -static int __init -init_hw_perf_events(void) -{ - unsigned long cpuid = read_cpuid_id(); - unsigned long implementor = (cpuid & 0xFF000000) >> 24; - unsigned long part_number = (cpuid & 0xFFF0); - - /* ARM Ltd CPUs. */ - if (0x41 == implementor) { - switch (part_number) { - case 0xB360: /* ARM1136 */ - case 0xB560: /* ARM1156 */ - case 0xB760: /* ARM1176 */ - cpu_pmu = armv6pmu_init(); - break; - case 0xB020: /* ARM11mpcore */ - cpu_pmu = armv6mpcore_pmu_init(); - break; - case 0xC080: /* Cortex-A8 */ - cpu_pmu = armv7_a8_pmu_init(); - break; - case 0xC090: /* Cortex-A9 */ - cpu_pmu = armv7_a9_pmu_init(); - break; - case 0xC050: /* Cortex-A5 */ - cpu_pmu = armv7_a5_pmu_init(); - break; - case 0xC0F0: /* Cortex-A15 */ - cpu_pmu = armv7_a15_pmu_init(); - break; - case 0xC070: /* Cortex-A7 */ - cpu_pmu = armv7_a7_pmu_init(); - break; - } - /* Intel CPUs [xscale]. */ - } else if (0x69 == implementor) { - part_number = (cpuid >> 13) & 0x7; - switch (part_number) { - case 1: - cpu_pmu = xscale1pmu_init(); - break; - case 2: - cpu_pmu = xscale2pmu_init(); - break; - } - } - - if (cpu_pmu) { - pr_info("enabled with %s PMU driver, %d counters available\n", - cpu_pmu->name, cpu_pmu->num_events); - cpu_pmu_init(cpu_pmu); - register_cpu_notifier(&pmu_cpu_notifier); - armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW); - } else { - pr_info("no hardware support available\n"); - } - - return 0; -} -early_initcall(init_hw_perf_events); - /* * Callchain handling code. */ diff --git a/trunk/arch/arm/kernel/perf_event_cpu.c b/trunk/arch/arm/kernel/perf_event_cpu.c new file mode 100644 index 000000000000..8d7d8d4de9d6 --- /dev/null +++ b/trunk/arch/arm/kernel/perf_event_cpu.c @@ -0,0 +1,295 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2012 ARM Limited + * + * Author: Will Deacon + */ +#define pr_fmt(fmt) "CPU PMU: " fmt + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* Set at runtime when we know what CPU type we are. */ +static struct arm_pmu *cpu_pmu; + +static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events); +static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask); +static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events); + +/* + * Despite the names, these two functions are CPU-specific and are used + * by the OProfile/perf code. + */ +const char *perf_pmu_name(void) +{ + if (!cpu_pmu) + return NULL; + + return cpu_pmu->pmu.name; +} +EXPORT_SYMBOL_GPL(perf_pmu_name); + +int perf_num_counters(void) +{ + int max_events = 0; + + if (cpu_pmu != NULL) + max_events = cpu_pmu->num_events; + + return max_events; +} +EXPORT_SYMBOL_GPL(perf_num_counters); + +/* Include the PMU-specific implementations. */ +#include "perf_event_xscale.c" +#include "perf_event_v6.c" +#include "perf_event_v7.c" + +static struct pmu_hw_events *cpu_pmu_get_cpu_events(void) +{ + return &__get_cpu_var(cpu_hw_events); +} + +static void cpu_pmu_free_irq(void) +{ + int i, irq, irqs; + struct platform_device *pmu_device = cpu_pmu->plat_device; + + irqs = min(pmu_device->num_resources, num_possible_cpus()); + + for (i = 0; i < irqs; ++i) { + if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs)) + continue; + irq = platform_get_irq(pmu_device, i); + if (irq >= 0) + free_irq(irq, cpu_pmu); + } +} + +static int cpu_pmu_request_irq(irq_handler_t handler) +{ + int i, err, irq, irqs; + struct platform_device *pmu_device = cpu_pmu->plat_device; + + if (!pmu_device) + return -ENODEV; + + irqs = min(pmu_device->num_resources, num_possible_cpus()); + if (irqs < 1) { + pr_err("no irqs for PMUs defined\n"); + return -ENODEV; + } + + for (i = 0; i < irqs; ++i) { + err = 0; + irq = platform_get_irq(pmu_device, i); + if (irq < 0) + continue; + + /* + * If we have a single PMU interrupt that we can't shift, + * assume that we're running on a uniprocessor machine and + * continue. Otherwise, continue without this interrupt. + */ + if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { + pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", + irq, i); + continue; + } + + err = request_irq(irq, handler, IRQF_NOBALANCING, "arm-pmu", + cpu_pmu); + if (err) { + pr_err("unable to request IRQ%d for ARM PMU counters\n", + irq); + return err; + } + + cpumask_set_cpu(i, &cpu_pmu->active_irqs); + } + + return 0; +} + +static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu) +{ + int cpu; + for_each_possible_cpu(cpu) { + struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu); + events->events = per_cpu(hw_events, cpu); + events->used_mask = per_cpu(used_mask, cpu); + raw_spin_lock_init(&events->pmu_lock); + } + + cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events; + cpu_pmu->request_irq = cpu_pmu_request_irq; + cpu_pmu->free_irq = cpu_pmu_free_irq; + + /* Ensure the PMU has sane values out of reset. */ + if (cpu_pmu && cpu_pmu->reset) + on_each_cpu(cpu_pmu->reset, NULL, 1); +} + +/* + * PMU hardware loses all context when a CPU goes offline. + * When a CPU is hotplugged back in, since some hardware registers are + * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading + * junk values out of them. + */ +static int __cpuinit cpu_pmu_notify(struct notifier_block *b, + unsigned long action, void *hcpu) +{ + if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING) + return NOTIFY_DONE; + + if (cpu_pmu && cpu_pmu->reset) + cpu_pmu->reset(NULL); + + return NOTIFY_OK; +} + +static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = { + .notifier_call = cpu_pmu_notify, +}; + +/* + * PMU platform driver and devicetree bindings. + */ +static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = { + {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init}, + {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init}, + {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init}, + {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init}, + {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init}, + {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init}, + {.compatible = "arm,arm1176-pmu", .data = armv6pmu_init}, + {.compatible = "arm,arm1136-pmu", .data = armv6pmu_init}, + {}, +}; + +static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = { + {.name = "arm-pmu"}, + {}, +}; + +/* + * CPU PMU identification and probing. + */ +static struct arm_pmu *__devinit probe_current_pmu(void) +{ + struct arm_pmu *pmu = NULL; + int cpu = get_cpu(); + unsigned long cpuid = read_cpuid_id(); + unsigned long implementor = (cpuid & 0xFF000000) >> 24; + unsigned long part_number = (cpuid & 0xFFF0); + + pr_info("probing PMU on CPU %d\n", cpu); + + /* ARM Ltd CPUs. */ + if (0x41 == implementor) { + switch (part_number) { + case 0xB360: /* ARM1136 */ + case 0xB560: /* ARM1156 */ + case 0xB760: /* ARM1176 */ + pmu = armv6pmu_init(); + break; + case 0xB020: /* ARM11mpcore */ + pmu = armv6mpcore_pmu_init(); + break; + case 0xC080: /* Cortex-A8 */ + pmu = armv7_a8_pmu_init(); + break; + case 0xC090: /* Cortex-A9 */ + pmu = armv7_a9_pmu_init(); + break; + case 0xC050: /* Cortex-A5 */ + pmu = armv7_a5_pmu_init(); + break; + case 0xC0F0: /* Cortex-A15 */ + pmu = armv7_a15_pmu_init(); + break; + case 0xC070: /* Cortex-A7 */ + pmu = armv7_a7_pmu_init(); + break; + } + /* Intel CPUs [xscale]. */ + } else if (0x69 == implementor) { + part_number = (cpuid >> 13) & 0x7; + switch (part_number) { + case 1: + pmu = xscale1pmu_init(); + break; + case 2: + pmu = xscale2pmu_init(); + break; + } + } + + put_cpu(); + return pmu; +} + +static int __devinit cpu_pmu_device_probe(struct platform_device *pdev) +{ + const struct of_device_id *of_id; + struct arm_pmu *(*init_fn)(void); + struct device_node *node = pdev->dev.of_node; + + if (cpu_pmu) { + pr_info("attempt to register multiple PMU devices!"); + return -ENOSPC; + } + + if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) { + init_fn = of_id->data; + cpu_pmu = init_fn(); + } else { + cpu_pmu = probe_current_pmu(); + } + + if (!cpu_pmu) + return -ENODEV; + + cpu_pmu->plat_device = pdev; + cpu_pmu_init(cpu_pmu); + register_cpu_notifier(&cpu_pmu_hotplug_notifier); + armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW); + + return 0; +} + +static struct platform_driver cpu_pmu_driver = { + .driver = { + .name = "arm-pmu", + .pm = &armpmu_dev_pm_ops, + .of_match_table = cpu_pmu_of_device_ids, + }, + .probe = cpu_pmu_device_probe, + .id_table = cpu_pmu_plat_device_ids, +}; + +static int __init register_pmu_driver(void) +{ + return platform_driver_register(&cpu_pmu_driver); +} +device_initcall(register_pmu_driver); diff --git a/trunk/arch/arm/kernel/perf_event_v6.c b/trunk/arch/arm/kernel/perf_event_v6.c index c90fcb2b6967..6ccc07971745 100644 --- a/trunk/arch/arm/kernel/perf_event_v6.c +++ b/trunk/arch/arm/kernel/perf_event_v6.c @@ -645,7 +645,7 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc, static int armv6_map_event(struct perf_event *event) { - return map_cpu_event(event, &armv6_perf_map, + return armpmu_map_event(event, &armv6_perf_map, &armv6_perf_cache_map, 0xFF); } @@ -664,7 +664,7 @@ static struct arm_pmu armv6pmu = { .max_period = (1LLU << 32) - 1, }; -static struct arm_pmu *__init armv6pmu_init(void) +static struct arm_pmu *__devinit armv6pmu_init(void) { return &armv6pmu; } @@ -679,7 +679,7 @@ static struct arm_pmu *__init armv6pmu_init(void) static int armv6mpcore_map_event(struct perf_event *event) { - return map_cpu_event(event, &armv6mpcore_perf_map, + return armpmu_map_event(event, &armv6mpcore_perf_map, &armv6mpcore_perf_cache_map, 0xFF); } @@ -698,17 +698,17 @@ static struct arm_pmu armv6mpcore_pmu = { .max_period = (1LLU << 32) - 1, }; -static struct arm_pmu *__init armv6mpcore_pmu_init(void) +static struct arm_pmu *__devinit armv6mpcore_pmu_init(void) { return &armv6mpcore_pmu; } #else -static struct arm_pmu *__init armv6pmu_init(void) +static struct arm_pmu *__devinit armv6pmu_init(void) { return NULL; } -static struct arm_pmu *__init armv6mpcore_pmu_init(void) +static struct arm_pmu *__devinit armv6mpcore_pmu_init(void) { return NULL; } diff --git a/trunk/arch/arm/kernel/perf_event_v7.c b/trunk/arch/arm/kernel/perf_event_v7.c index f04070bd2183..bd4b090ebcfd 100644 --- a/trunk/arch/arm/kernel/perf_event_v7.c +++ b/trunk/arch/arm/kernel/perf_event_v7.c @@ -1204,31 +1204,31 @@ static void armv7pmu_reset(void *info) static int armv7_a8_map_event(struct perf_event *event) { - return map_cpu_event(event, &armv7_a8_perf_map, + return armpmu_map_event(event, &armv7_a8_perf_map, &armv7_a8_perf_cache_map, 0xFF); } static int armv7_a9_map_event(struct perf_event *event) { - return map_cpu_event(event, &armv7_a9_perf_map, + return armpmu_map_event(event, &armv7_a9_perf_map, &armv7_a9_perf_cache_map, 0xFF); } static int armv7_a5_map_event(struct perf_event *event) { - return map_cpu_event(event, &armv7_a5_perf_map, + return armpmu_map_event(event, &armv7_a5_perf_map, &armv7_a5_perf_cache_map, 0xFF); } static int armv7_a15_map_event(struct perf_event *event) { - return map_cpu_event(event, &armv7_a15_perf_map, + return armpmu_map_event(event, &armv7_a15_perf_map, &armv7_a15_perf_cache_map, 0xFF); } static int armv7_a7_map_event(struct perf_event *event) { - return map_cpu_event(event, &armv7_a7_perf_map, + return armpmu_map_event(event, &armv7_a7_perf_map, &armv7_a7_perf_cache_map, 0xFF); } @@ -1245,7 +1245,7 @@ static struct arm_pmu armv7pmu = { .max_period = (1LLU << 32) - 1, }; -static u32 __init armv7_read_num_pmnc_events(void) +static u32 __devinit armv7_read_num_pmnc_events(void) { u32 nb_cnt; @@ -1256,7 +1256,7 @@ static u32 __init armv7_read_num_pmnc_events(void) return nb_cnt + 1; } -static struct arm_pmu *__init armv7_a8_pmu_init(void) +static struct arm_pmu *__devinit armv7_a8_pmu_init(void) { armv7pmu.name = "ARMv7 Cortex-A8"; armv7pmu.map_event = armv7_a8_map_event; @@ -1264,7 +1264,7 @@ static struct arm_pmu *__init armv7_a8_pmu_init(void) return &armv7pmu; } -static struct arm_pmu *__init armv7_a9_pmu_init(void) +static struct arm_pmu *__devinit armv7_a9_pmu_init(void) { armv7pmu.name = "ARMv7 Cortex-A9"; armv7pmu.map_event = armv7_a9_map_event; @@ -1272,7 +1272,7 @@ static struct arm_pmu *__init armv7_a9_pmu_init(void) return &armv7pmu; } -static struct arm_pmu *__init armv7_a5_pmu_init(void) +static struct arm_pmu *__devinit armv7_a5_pmu_init(void) { armv7pmu.name = "ARMv7 Cortex-A5"; armv7pmu.map_event = armv7_a5_map_event; @@ -1280,7 +1280,7 @@ static struct arm_pmu *__init armv7_a5_pmu_init(void) return &armv7pmu; } -static struct arm_pmu *__init armv7_a15_pmu_init(void) +static struct arm_pmu *__devinit armv7_a15_pmu_init(void) { armv7pmu.name = "ARMv7 Cortex-A15"; armv7pmu.map_event = armv7_a15_map_event; @@ -1289,7 +1289,7 @@ static struct arm_pmu *__init armv7_a15_pmu_init(void) return &armv7pmu; } -static struct arm_pmu *__init armv7_a7_pmu_init(void) +static struct arm_pmu *__devinit armv7_a7_pmu_init(void) { armv7pmu.name = "ARMv7 Cortex-A7"; armv7pmu.map_event = armv7_a7_map_event; @@ -1298,27 +1298,27 @@ static struct arm_pmu *__init armv7_a7_pmu_init(void) return &armv7pmu; } #else -static struct arm_pmu *__init armv7_a8_pmu_init(void) +static struct arm_pmu *__devinit armv7_a8_pmu_init(void) { return NULL; } -static struct arm_pmu *__init armv7_a9_pmu_init(void) +static struct arm_pmu *__devinit armv7_a9_pmu_init(void) { return NULL; } -static struct arm_pmu *__init armv7_a5_pmu_init(void) +static struct arm_pmu *__devinit armv7_a5_pmu_init(void) { return NULL; } -static struct arm_pmu *__init armv7_a15_pmu_init(void) +static struct arm_pmu *__devinit armv7_a15_pmu_init(void) { return NULL; } -static struct arm_pmu *__init armv7_a7_pmu_init(void) +static struct arm_pmu *__devinit armv7_a7_pmu_init(void) { return NULL; } diff --git a/trunk/arch/arm/kernel/perf_event_xscale.c b/trunk/arch/arm/kernel/perf_event_xscale.c index f759fe0bab63..426e19f380a2 100644 --- a/trunk/arch/arm/kernel/perf_event_xscale.c +++ b/trunk/arch/arm/kernel/perf_event_xscale.c @@ -430,7 +430,7 @@ xscale1pmu_write_counter(int counter, u32 val) static int xscale_map_event(struct perf_event *event) { - return map_cpu_event(event, &xscale_perf_map, + return armpmu_map_event(event, &xscale_perf_map, &xscale_perf_cache_map, 0xFF); } @@ -449,7 +449,7 @@ static struct arm_pmu xscale1pmu = { .max_period = (1LLU << 32) - 1, }; -static struct arm_pmu *__init xscale1pmu_init(void) +static struct arm_pmu *__devinit xscale1pmu_init(void) { return &xscale1pmu; } @@ -816,17 +816,17 @@ static struct arm_pmu xscale2pmu = { .max_period = (1LLU << 32) - 1, }; -static struct arm_pmu *__init xscale2pmu_init(void) +static struct arm_pmu *__devinit xscale2pmu_init(void) { return &xscale2pmu; } #else -static struct arm_pmu *__init xscale1pmu_init(void) +static struct arm_pmu *__devinit xscale1pmu_init(void) { return NULL; } -static struct arm_pmu *__init xscale2pmu_init(void) +static struct arm_pmu *__devinit xscale2pmu_init(void) { return NULL; } diff --git a/trunk/arch/arm/kernel/pmu.c b/trunk/arch/arm/kernel/pmu.c deleted file mode 100644 index 2334bf8a650a..000000000000 --- a/trunk/arch/arm/kernel/pmu.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * linux/arch/arm/kernel/pmu.c - * - * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles - * Copyright (C) 2010 ARM Ltd, Will Deacon - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include -#include -#include - -#include - -/* - * PMU locking to ensure mutual exclusion between different subsystems. - */ -static unsigned long pmu_lock[BITS_TO_LONGS(ARM_NUM_PMU_DEVICES)]; - -int -reserve_pmu(enum arm_pmu_type type) -{ - return test_and_set_bit_lock(type, pmu_lock) ? -EBUSY : 0; -} -EXPORT_SYMBOL_GPL(reserve_pmu); - -void -release_pmu(enum arm_pmu_type type) -{ - clear_bit_unlock(type, pmu_lock); -} -EXPORT_SYMBOL_GPL(release_pmu); diff --git a/trunk/arch/arm/kernel/setup.c b/trunk/arch/arm/kernel/setup.c index a81dcecc7343..725f9f2a9541 100644 --- a/trunk/arch/arm/kernel/setup.c +++ b/trunk/arch/arm/kernel/setup.c @@ -977,8 +977,10 @@ void __init setup_arch(char **cmdline_p) unflatten_device_tree(); #ifdef CONFIG_SMP - if (is_smp()) + if (is_smp()) { + smp_set_ops(mdesc->smp); smp_init_cpus(); + } #endif reserve_crashkernel(); diff --git a/trunk/arch/arm/kernel/smp.c b/trunk/arch/arm/kernel/smp.c index ebd8ad274d76..aa4ffe6e5ecf 100644 --- a/trunk/arch/arm/kernel/smp.c +++ b/trunk/arch/arm/kernel/smp.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -27,6 +26,7 @@ #include #include +#include #include #include #include @@ -42,6 +42,7 @@ #include #include #include +#include /* * as from 2.5, kernels no longer have an init_tasks structure @@ -50,6 +51,12 @@ */ struct secondary_data secondary_data; +/* + * control for which core is the next to come out of the secondary + * boot "holding pen" + */ +volatile int __cpuinitdata pen_release = -1; + enum ipi_msg_type { IPI_TIMER = 2, IPI_RESCHEDULE, @@ -60,6 +67,14 @@ enum ipi_msg_type { static DECLARE_COMPLETION(cpu_running); +static struct smp_operations smp_ops; + +void __init smp_set_ops(struct smp_operations *ops) +{ + if (ops) + smp_ops = *ops; +}; + int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle) { int ret; @@ -100,13 +115,64 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle) return ret; } +/* platform specific SMP operations */ +void __init smp_init_cpus(void) +{ + if (smp_ops.smp_init_cpus) + smp_ops.smp_init_cpus(); +} + +static void __init platform_smp_prepare_cpus(unsigned int max_cpus) +{ + if (smp_ops.smp_prepare_cpus) + smp_ops.smp_prepare_cpus(max_cpus); +} + +static void __cpuinit platform_secondary_init(unsigned int cpu) +{ + if (smp_ops.smp_secondary_init) + smp_ops.smp_secondary_init(cpu); +} + +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + if (smp_ops.smp_boot_secondary) + return smp_ops.smp_boot_secondary(cpu, idle); + return -ENOSYS; +} + #ifdef CONFIG_HOTPLUG_CPU static void percpu_timer_stop(void); +static int platform_cpu_kill(unsigned int cpu) +{ + if (smp_ops.cpu_kill) + return smp_ops.cpu_kill(cpu); + return 1; +} + +static void platform_cpu_die(unsigned int cpu) +{ + if (smp_ops.cpu_die) + smp_ops.cpu_die(cpu); +} + +static int platform_cpu_disable(unsigned int cpu) +{ + if (smp_ops.cpu_disable) + return smp_ops.cpu_disable(cpu); + + /* + * By default, allow disabling all CPUs except the first one, + * since this is special on a lot of platforms, e.g. because + * of clock tick interrupts. + */ + return cpu == 0 ? -EPERM : 0; +} /* * __cpu_disable runs on the processor to be shutdown. */ -int __cpu_disable(void) +int __cpuinit __cpu_disable(void) { unsigned int cpu = smp_processor_id(); int ret; @@ -149,7 +215,7 @@ static DECLARE_COMPLETION(cpu_died); * called on the thread which is asking for a CPU to be shutdown - * waits until shutdown has completed, or it is timed out. */ -void __cpu_die(unsigned int cpu) +void __cpuinit __cpu_die(unsigned int cpu) { if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) { pr_err("CPU%u: cpu didn't die\n", cpu); diff --git a/trunk/arch/arm/mach-at91/Makefile.boot b/trunk/arch/arm/mach-at91/Makefile.boot index 30bb7332e30b..5309f9b6aabc 100644 --- a/trunk/arch/arm/mach-at91/Makefile.boot +++ b/trunk/arch/arm/mach-at91/Makefile.boot @@ -12,27 +12,3 @@ else params_phys-y := 0x20000100 initrd_phys-y := 0x20410000 endif - -# Keep dtb files sorted alphabetically for each SoC -# sam9260 -dtb-$(CONFIG_MACH_AT91SAM_DT) += aks-cdu.dtb -dtb-$(CONFIG_MACH_AT91SAM_DT) += ethernut5.dtb -dtb-$(CONFIG_MACH_AT91SAM_DT) += evk-pro3.dtb -dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb -dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb -# sam9263 -dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9263ek.dtb -dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9263.dtb -dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9263.dtb -# sam9g20 -dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek.dtb -dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek_2mmc.dtb -dtb-$(CONFIG_MACH_AT91SAM_DT) += kizbox.dtb -dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9g20.dtb -dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb -# sam9g45 -dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb -# sam9n12 -dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9n12ek.dtb -# sam9x5 -dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb diff --git a/trunk/arch/arm/mach-at91/at91x40.c b/trunk/arch/arm/mach-at91/at91x40.c index 46090e642d8e..6bd7300a2bc5 100644 --- a/trunk/arch/arm/mach-at91/at91x40.c +++ b/trunk/arch/arm/mach-at91/at91x40.c @@ -47,7 +47,7 @@ static void at91x40_idle(void) * Disable the processor clock. The processor will be automatically * re-enabled by an interrupt or by a reset. */ - __raw_writel(AT91_PS_CR_CPU, AT91_PS_CR); + __raw_writel(AT91_PS_CR_CPU, AT91_IO_P2V(AT91_PS_CR)); cpu_do_idle(); } diff --git a/trunk/arch/arm/mach-at91/at91x40_time.c b/trunk/arch/arm/mach-at91/at91x40_time.c index 6ca680a1d5d1..ee06d7bcdf76 100644 --- a/trunk/arch/arm/mach-at91/at91x40_time.c +++ b/trunk/arch/arm/mach-at91/at91x40_time.c @@ -29,10 +29,10 @@ #include #define at91_tc_read(field) \ - __raw_readl(AT91_TC + field) + __raw_readl(AT91_IO_P2V(AT91_TC) + field) #define at91_tc_write(field, value) \ - __raw_writel(value, AT91_TC + field); + __raw_writel(value, AT91_IO_P2V(AT91_TC) + field); /* * 3 counter/timer units present. diff --git a/trunk/arch/arm/mach-at91/include/mach/hardware.h b/trunk/arch/arm/mach-at91/include/mach/hardware.h index 09242b67d277..711a7892d331 100644 --- a/trunk/arch/arm/mach-at91/include/mach/hardware.h +++ b/trunk/arch/arm/mach-at91/include/mach/hardware.h @@ -67,13 +67,13 @@ * to 0xFEF78000 .. 0xFF000000. (544Kb) */ #define AT91_IO_PHYS_BASE 0xFFF78000 -#define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE) +#define AT91_IO_VIRT_BASE IOMEM(0xFF000000 - AT91_IO_SIZE) #else /* * Identity mapping for the non MMU case. */ #define AT91_IO_PHYS_BASE AT91_BASE_SYS -#define AT91_IO_VIRT_BASE AT91_IO_PHYS_BASE +#define AT91_IO_VIRT_BASE IOMEM(AT91_IO_PHYS_BASE) #endif #define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) diff --git a/trunk/arch/arm/mach-at91/include/mach/uncompress.h b/trunk/arch/arm/mach-at91/include/mach/uncompress.h index 6f6118d1576a..97ad68a826f8 100644 --- a/trunk/arch/arm/mach-at91/include/mach/uncompress.h +++ b/trunk/arch/arm/mach-at91/include/mach/uncompress.h @@ -94,7 +94,7 @@ static const u32 uarts_sam9x5[] = { 0, }; -static inline const u32* decomp_soc_detect(u32 dbgu_base) +static inline const u32* decomp_soc_detect(void __iomem *dbgu_base) { u32 cidr, socid; @@ -142,10 +142,10 @@ static inline void arch_decomp_setup(void) int i = 0; const u32* usarts; - usarts = decomp_soc_detect(AT91_BASE_DBGU0); + usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0); if (!usarts) - usarts = decomp_soc_detect(AT91_BASE_DBGU1); + usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1); if (!usarts) { at91_uart = NULL; return; diff --git a/trunk/arch/arm/mach-at91/setup.c b/trunk/arch/arm/mach-at91/setup.c index 944bffb08991..e6f52de1062f 100644 --- a/trunk/arch/arm/mach-at91/setup.c +++ b/trunk/arch/arm/mach-at91/setup.c @@ -73,7 +73,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length) { struct map_desc *desc = &sram_desc[bank]; - desc->virtual = AT91_IO_VIRT_BASE - length; + desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length; if (bank > 0) desc->virtual -= sram_desc[bank - 1].length; @@ -88,7 +88,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length) } static struct map_desc at91_io_desc __initdata = { - .virtual = AT91_VA_BASE_SYS, + .virtual = (unsigned long)AT91_VA_BASE_SYS, .pfn = __phys_to_pfn(AT91_BASE_SYS), .length = SZ_16K, .type = MT_DEVICE, diff --git a/trunk/arch/arm/mach-bcm2835/Makefile b/trunk/arch/arm/mach-bcm2835/Makefile new file mode 100644 index 000000000000..4c3892fe02c3 --- /dev/null +++ b/trunk/arch/arm/mach-bcm2835/Makefile @@ -0,0 +1 @@ +obj-y += bcm2835.o diff --git a/trunk/arch/arm/mach-bcm2835/Makefile.boot b/trunk/arch/arm/mach-bcm2835/Makefile.boot new file mode 100644 index 000000000000..2d30e17f5b69 --- /dev/null +++ b/trunk/arch/arm/mach-bcm2835/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/trunk/arch/arm/mach-bcm2835/bcm2835.c b/trunk/arch/arm/mach-bcm2835/bcm2835.c new file mode 100644 index 000000000000..f6fea4933571 --- /dev/null +++ b/trunk/arch/arm/mach-bcm2835/bcm2835.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2010 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include + +static struct map_desc io_map __initdata = { + .virtual = BCM2835_PERIPH_VIRT, + .pfn = __phys_to_pfn(BCM2835_PERIPH_PHYS), + .length = BCM2835_PERIPH_SIZE, + .type = MT_DEVICE +}; + +void __init bcm2835_map_io(void) +{ + iotable_init(&io_map, 1); +} + +void __init bcm2835_init(void) +{ + int ret; + + bcm2835_init_clocks(); + + ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, + NULL); + if (ret) { + pr_err("of_platform_populate failed: %d\n", ret); + BUG(); + } +} + +static const char * const bcm2835_compat[] = { + "brcm,bcm2835", + NULL +}; + +DT_MACHINE_START(BCM2835, "BCM2835") + .map_io = bcm2835_map_io, + .init_irq = bcm2835_init_irq, + .handle_irq = bcm2835_handle_irq, + .init_machine = bcm2835_init, + .timer = &bcm2835_timer, + .dt_compat = bcm2835_compat +MACHINE_END diff --git a/trunk/arch/arm/mach-picoxcell/include/mach/map.h b/trunk/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h similarity index 57% rename from trunk/arch/arm/mach-picoxcell/include/mach/map.h rename to trunk/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h index c06afad218bb..d4dfcf7a9cda 100644 --- a/trunk/arch/arm/mach-picoxcell/include/mach/map.h +++ b/trunk/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h @@ -1,5 +1,8 @@ /* - * Copyright (c) 2011 Picochip Ltd., Jamie Iles + * Copyright (C) 2012 Stephen Warren + * + * Derived from code: + * Copyright (C) 2010 Broadcom * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -11,15 +14,16 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#ifndef __PICOXCELL_MAP_H__ -#define __PICOXCELL_MAP_H__ -#define PHYS_TO_IO(x) (((x) & 0x00ffffff) | 0xfe000000) +#ifndef __MACH_BCM2835_BCM2835_SOC_H__ +#define __MACH_BCM2835_BCM2835_SOC_H__ -#ifdef __ASSEMBLY__ -#define IO_ADDRESS(x) PHYS_TO_IO((x)) -#else -#define IO_ADDRESS(x) (void __iomem __force *)(PHYS_TO_IO((x))) -#endif +#include -#endif /* __PICOXCELL_MAP_H__ */ +#define BCM2835_PERIPH_PHYS 0x20000000 +#define BCM2835_PERIPH_VIRT 0xf0000000 +#define BCM2835_PERIPH_SIZE SZ_16M +#define BCM2835_DEBUG_PHYS 0x20201000 +#define BCM2835_DEBUG_VIRT 0xf0201000 + +#endif diff --git a/trunk/arch/arm/mach-bcm2835/include/mach/debug-macro.S b/trunk/arch/arm/mach-bcm2835/include/mach/debug-macro.S new file mode 100644 index 000000000000..8a161e44ae28 --- /dev/null +++ b/trunk/arch/arm/mach-bcm2835/include/mach/debug-macro.S @@ -0,0 +1,21 @@ +/* + * Debugging macro include header + * + * Copyright (C) 2010 Broadcom + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include + + .macro addruart, rp, rv, tmp + ldr \rp, =BCM2835_DEBUG_PHYS + ldr \rv, =BCM2835_DEBUG_VIRT + .endm + +#include diff --git a/trunk/arch/arm/mach-socfpga/include/mach/timex.h b/trunk/arch/arm/mach-bcm2835/include/mach/timex.h similarity index 81% rename from trunk/arch/arm/mach-socfpga/include/mach/timex.h rename to trunk/arch/arm/mach-bcm2835/include/mach/timex.h index 43df4354e461..6d021e136ae3 100644 --- a/trunk/arch/arm/mach-socfpga/include/mach/timex.h +++ b/trunk/arch/arm/mach-bcm2835/include/mach/timex.h @@ -1,5 +1,7 @@ /* - * Copyright (C) 2003 ARM Limited + * BCM2835 system clock frequency + * + * Copyright (C) 2010 Broadcom * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,4 +18,9 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define CLOCK_TICK_RATE (50000000 / 16) +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +#define CLOCK_TICK_RATE (1000000) + +#endif diff --git a/trunk/arch/arm/mach-bcm2835/include/mach/uncompress.h b/trunk/arch/arm/mach-bcm2835/include/mach/uncompress.h new file mode 100644 index 000000000000..cc46dcc72377 --- /dev/null +++ b/trunk/arch/arm/mach-bcm2835/include/mach/uncompress.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2010 Broadcom + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#define UART0_BASE BCM2835_DEBUG_PHYS + +#define BCM2835_UART_DR IOMEM(UART0_BASE + UART01x_DR) +#define BCM2835_UART_FR IOMEM(UART0_BASE + UART01x_FR) +#define BCM2835_UART_CR IOMEM(UART0_BASE + UART011_CR) + +static inline void putc(int c) +{ + while (__raw_readl(BCM2835_UART_FR) & UART01x_FR_TXFF) + barrier(); + + __raw_writel(c, BCM2835_UART_DR); +} + +static inline void flush(void) +{ + int fr; + + do { + fr = __raw_readl(BCM2835_UART_FR); + barrier(); + } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE); +} + +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/trunk/arch/arm/mach-bcmring/arch.c b/trunk/arch/arm/mach-bcmring/arch.c index 45c97b1ee9b1..c18a5048b6c5 100644 --- a/trunk/arch/arm/mach-bcmring/arch.c +++ b/trunk/arch/arm/mach-bcmring/arch.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include @@ -38,7 +37,7 @@ #include #include -#include +#include #include "core.h" @@ -116,7 +115,7 @@ static struct resource pmu_resource = { static struct platform_device pmu_device = { .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, + .id = -1, .resource = &pmu_resource, .num_resources = 1, }; diff --git a/trunk/arch/arm/mach-bcmring/core.c b/trunk/arch/arm/mach-bcmring/core.c index adbfb1994582..4b50228a6771 100644 --- a/trunk/arch/arm/mach-bcmring/core.c +++ b/trunk/arch/arm/mach-bcmring/core.c @@ -43,11 +43,10 @@ #include #include -#include +#include #include "clock.h" -#include #include #include #include diff --git a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw.c index 96273ff34956..5050833817b7 100644 --- a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw.c +++ b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw.c @@ -26,15 +26,15 @@ /* ---- Include Files ---------------------------------------------------- */ -#include -#include -#include +#include +#include +#include #include #include -#include -#include +#include +#include /* ---- Private Constants and Types --------------------------------------- */ @@ -61,21 +61,21 @@ static int chipcHw_divide(int num, int denom) /****************************************************************************/ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ ) { - volatile uint32_t *pPLLReg = (uint32_t *) 0x0; - volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; - volatile uint32_t *pDependentClock = (uint32_t *) 0x0; + uint32_t __iomem *pPLLReg = NULL; + uint32_t __iomem *pClockCtrl = NULL; + uint32_t __iomem *pDependentClock = NULL; uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ uint32_t dependentClockType = 0; uint32_t vcoHz = 0; /* Get VCO frequencies */ - if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { + if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { uint64_t adjustFreq = 0; vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ @@ -86,13 +86,13 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur } else { vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); } vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); switch (clock) { @@ -187,51 +187,51 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur if (pPLLReg) { /* Obtain PLL clock frequency */ - if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { + if (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { /* Return crystal clock frequency when bypassed */ return chipcHw_XTAL_FREQ_Hz; } else if (clock == chipcHw_CLOCK_DDR) { /* DDR frequency is configured in PLLDivider register */ - return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256)); + return chipcHw_divide (vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256)); } else { /* From chip revision number B0, LCD clock is internally divided by 2 */ if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) { vcoHz >>= 1; } /* Obtain PLL clock frequency using VCO dividers */ - return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); + return chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); } } else if (pClockCtrl) { /* Obtain divider clock frequency */ uint32_t div; uint32_t freq = 0; - if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { + if (readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { /* Return crystal clock frequency when bypassed */ return chipcHw_XTAL_FREQ_Hz; } else if (pDependentClock) { /* Identify the dependent clock frequency */ switch (dependentClockType) { case PLL_CLOCK: - if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { + if (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { /* Use crystal clock frequency when dependent PLL clock is bypassed */ freq = chipcHw_XTAL_FREQ_Hz; } else { /* Obtain PLL clock frequency using VCO dividers */ - div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK; + div = readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK; freq = div ? chipcHw_divide(vcoHz, div) : 0; } break; case NON_PLL_CLOCK: - if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { + if (pDependentClock == &pChipcHw->ACLKClock) { freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS); } else { - if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { + if (readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { /* Use crystal clock frequency when dependent divider clock is bypassed */ freq = chipcHw_XTAL_FREQ_Hz; } else { /* Obtain divider clock frequency using XTAL dividers */ - div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK; + div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK; freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256)); } } @@ -242,7 +242,7 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur freq = chipcHw_XTAL_FREQ_Hz; } - div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK; + div = readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_DIV_MASK; return chipcHw_divide(freq, (div ? div : 256)); } return 0; @@ -261,9 +261,9 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */ uint32_t freq /* [ IN ] Clock frequency in Hz */ ) { - volatile uint32_t *pPLLReg = (uint32_t *) 0x0; - volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; - volatile uint32_t *pDependentClock = (uint32_t *) 0x0; + uint32_t __iomem *pPLLReg = NULL; + uint32_t __iomem *pClockCtrl = NULL; + uint32_t __iomem *pDependentClock = NULL; uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ uint32_t desVcoFreqPll1Hz = 0; /* Desired VCO frequency for PLL1 in Hz */ uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ @@ -272,12 +272,12 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu uint32_t desVcoHz = 0; /* Get VCO frequencies */ - if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { + if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { uint64_t adjustFreq = 0; vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ @@ -289,16 +289,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu /* Desired VCO frequency */ desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + (((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1); } else { vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); } vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); switch (clock) { @@ -307,8 +307,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu { REG_LOCAL_IRQ_SAVE; /* Dvide DDR_phy by two to obtain DDR_ctrl clock */ - pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) - << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT); + writel((readl(&pChipcHw->DDRClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->DDRClock); REG_LOCAL_IRQ_RESTORE; } pPLLReg = &pChipcHw->DDRClock; @@ -329,8 +328,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu /* Configure the VPM:BUS ratio settings */ { REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) - << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT); + writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->VPMClock); REG_LOCAL_IRQ_RESTORE; } pPLLReg = &pChipcHw->VPMClock; @@ -428,9 +426,9 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu /* For DDR settings use only the PLL divider clock */ if (pPLLReg == &pChipcHw->DDRClock) { /* Set M1DIV for PLL1, which controls the DDR clock */ - reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24)); + reg32_write(&pChipcHw->PLLDivider, (readl(&pChipcHw->PLLDivider) & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24)); /* Calculate expected frequency */ - freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256)); + freq = chipcHw_divide(vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256)); } else { /* From chip revision number B0, LCD clock is internally divided by 2 */ if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) { @@ -441,7 +439,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK)); reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq)); /* Calculate expected frequency */ - freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); + freq = chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); } /* Wait for for atleast 200ns as per the protocol to change frequency */ udelay(1); @@ -460,16 +458,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu if (pDependentClock) { switch (dependentClockType) { case PLL_CLOCK: - divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq); + divider = chipcHw_divide(chipcHw_divide (desVcoHz, (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq); break; case NON_PLL_CLOCK: { uint32_t sourceClock = 0; - if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { + if (pDependentClock == &pChipcHw->ACLKClock) { sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS); } else { - uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK; + uint32_t div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK; sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256)); } divider = chipcHw_divide(sourceClock, freq); @@ -483,7 +481,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu if (divider) { REG_LOCAL_IRQ_SAVE; /* Set the divider to obtain the required frequency */ - *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK); + writel((readl(pClockCtrl) & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK), pClockCtrl); REG_LOCAL_IRQ_RESTORE; return freq; } @@ -515,25 +513,26 @@ static int vpmPhaseAlignA0(void) int count = 0; for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) { - phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT; + phaseControl = (readl(&pChipcHw->VPMClock) & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT; phaseValue = 0; prevPhaseComp = 0; /* Step 1: Look for falling PH_COMP transition */ /* Read the contents of VPM Clock resgister */ - phaseValue = pChipcHw->VPMClock; + phaseValue = readl(&pChipcHw->VPMClock); do { /* Store previous value of phase comparator */ prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP; /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); /* Read the contents of VPM Clock resgister. */ - phaseValue = pChipcHw->VPMClock; + phaseValue = readl(&pChipcHw->VPMClock); if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) { phaseControl = (0x3F & (phaseControl - 1)); @@ -557,12 +556,13 @@ static int vpmPhaseAlignA0(void) for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) { phaseControl = (0x3F & (phaseControl + 1)); - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; - phaseValue = pChipcHw->VPMClock; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); + phaseValue = readl(&pChipcHw->VPMClock); /* Count number of adjustment made */ adjustCount++; } @@ -581,12 +581,13 @@ static int vpmPhaseAlignA0(void) for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) { phaseControl = (0x3F & (phaseControl - 1)); - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; - phaseValue = pChipcHw->VPMClock; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); + phaseValue = readl(&pChipcHw->VPMClock); /* Count number of adjustment made */ adjustCount++; } @@ -605,12 +606,13 @@ static int vpmPhaseAlignA0(void) for (count = 0; (count < 5); count++) { phaseControl = (0x3F & (phaseControl - 1)); - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; - phaseValue = pChipcHw->VPMClock; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); + phaseValue = readl(&pChipcHw->VPMClock); /* Count number of adjustment made */ adjustCount++; } @@ -631,14 +633,14 @@ static int vpmPhaseAlignA0(void) /* Store previous value of phase comparator */ prevPhaseComp = phaseValue; /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= - chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); /* Read the contents of VPM Clock resgister. */ - phaseValue = pChipcHw->VPMClock; + phaseValue = readl(&pChipcHw->VPMClock); if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) { phaseControl = (0x3F & (phaseControl - 1)); @@ -661,13 +663,13 @@ static int vpmPhaseAlignA0(void) } /* For VPM Phase should be perfectly aligned. */ - phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F); + phaseControl = (((readl(&pChipcHw->VPMClock) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F); { REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT); + writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT), &pChipcHw->VPMClock); /* Load new phase value */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); REG_LOCAL_IRQ_RESTORE; } @@ -697,7 +699,7 @@ int chipcHw_vpmPhaseAlign(void) int adjustCount = 0; /* Disable VPM access */ - pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; + writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1); /* Disable HW VPM phase alignment */ chipcHw_vpmHwPhaseAlignDisable(); /* Enable SW VPM phase alignment */ @@ -715,23 +717,24 @@ int chipcHw_vpmPhaseAlign(void) phaseControl--; } else { /* Enable VPM access */ - pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; + writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1); /* Return adjust count */ return adjustCount; } /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); /* Count adjustment */ adjustCount++; } } /* Disable VPM access */ - pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; + writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1); return -1; } diff --git a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c index 367df75d4bb3..8377d8054168 100644 --- a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c +++ b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c @@ -26,15 +26,15 @@ /* ---- Include Files ---------------------------------------------------- */ -#include -#include -#include +#include +#include +#include #include #include -#include -#include +#include +#include /* ---- Private Constants and Types --------------------------------------- */ /* @@ -73,9 +73,9 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) { REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig2 = - chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET; + writel(chipcHw_REG_PLL_CONFIG_D_RESET | + chipcHw_REG_PLL_CONFIG_A_RESET, + &pChipcHw->PLLConfig2); pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN | chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER | @@ -87,28 +87,30 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT); /* Enable CHIPC registers to control the PLL */ - pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; + writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus); /* Set pre divider to get desired VCO frequency */ - pChipcHw->PLLPreDivider2 = pllPreDivider2; + writel(pllPreDivider2, &pChipcHw->PLLPreDivider2); /* Set NDIV Frac */ - pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f; + writel(chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider2); /* This has to be removed once the default values are fixed for PLL2. */ - pChipcHw->PLLControl12 = 0x38000700; - pChipcHw->PLLControl22 = 0x00000015; + writel(0x38000700, &pChipcHw->PLLControl12); + writel(0x00000015, &pChipcHw->PLLControl22); /* Reset PLL2 */ if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { - pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | + writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN; + chipcHw_REG_PLL_CONFIG_POWER_DOWN, + &pChipcHw->PLLConfig2); } else { - pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | + writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN; + chipcHw_REG_PLL_CONFIG_POWER_DOWN, + &pChipcHw->PLLConfig2); } REG_LOCAL_IRQ_RESTORE; } @@ -119,22 +121,25 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) { REG_LOCAL_IRQ_SAVE; /* Remove analog reset and Power on the PLL */ - pChipcHw->PLLConfig2 &= + writel(readl(&pChipcHw->PLLConfig2) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_POWER_DOWN); + chipcHw_REG_PLL_CONFIG_POWER_DOWN), + &pChipcHw->PLLConfig2); REG_LOCAL_IRQ_RESTORE; } /* Wait until PLL is locked */ - while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED)) + while (!(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED)) ; { REG_LOCAL_IRQ_SAVE; /* Remove digital reset */ - pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET; + writel(readl(&pChipcHw->PLLConfig2) & + ~chipcHw_REG_PLL_CONFIG_D_RESET, + &pChipcHw->PLLConfig2); REG_LOCAL_IRQ_RESTORE; } @@ -157,9 +162,9 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) { REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig = - chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET; + writel(chipcHw_REG_PLL_CONFIG_D_RESET | + chipcHw_REG_PLL_CONFIG_A_RESET, + &pChipcHw->PLLConfig); /* Setting VCO frequency */ if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { pllPreDivider = @@ -182,30 +187,22 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) } /* Enable CHIPC registers to control the PLL */ - pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; + writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus); /* Set pre divider to get desired VCO frequency */ - pChipcHw->PLLPreDivider = pllPreDivider; + writel(pllPreDivider, &pChipcHw->PLLPreDivider); /* Set NDIV Frac */ if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { - pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | - chipcHw_REG_PLL_DIVIDER_NDIV_f_SS; + writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f_SS, &pChipcHw->PLLDivider); } else { - pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | - chipcHw_REG_PLL_DIVIDER_NDIV_f; + writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider); } /* Reset PLL1 */ if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { - pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN; + writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig); } else { - pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_VCO_800_1600 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN; + writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig); } REG_LOCAL_IRQ_RESTORE; @@ -216,22 +213,19 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) { REG_LOCAL_IRQ_SAVE; /* Remove analog reset and Power on the PLL */ - pChipcHw->PLLConfig &= - ~(chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_POWER_DOWN); + writel(readl(&pChipcHw->PLLConfig) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_POWER_DOWN), &pChipcHw->PLLConfig); REG_LOCAL_IRQ_RESTORE; } /* Wait until PLL is locked */ - while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED) - || !(pChipcHw-> - PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED)) + while (!(readl(&pChipcHw->PLLStatus) & chipcHw_REG_PLL_STATUS_LOCKED) + || !(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED)) ; /* Remove digital reset */ { REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET; + writel(readl(&pChipcHw->PLLConfig) & ~chipcHw_REG_PLL_CONFIG_D_RESET, &pChipcHw->PLLConfig); REG_LOCAL_IRQ_RESTORE; } } @@ -267,11 +261,7 @@ void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initializ chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET); /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */ - pChipcHw->ACLKClock = - (pChipcHw-> - ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> - armBusRatio & - chipcHw_REG_ACLKClock_CLK_DIV_MASK); + writel((readl(&pChipcHw->ACLKClock) & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> armBusRatio & chipcHw_REG_ACLKClock_CLK_DIV_MASK), &pChipcHw->ACLKClock); /* Set various core component frequencies. The order in which this is done is important for some. */ /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */ diff --git a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c index 2671d8896bbb..f95ce913fa1e 100644 --- a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c +++ b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c @@ -13,11 +13,11 @@ *****************************************************************************/ /* ---- Include Files ---------------------------------------------------- */ -#include +#include #include #include -#include -#include +#include +#include /* ---- Private Constants and Types --------------------------------------- */ /* ---- Private Variables ------------------------------------------------- */ @@ -50,17 +50,18 @@ void chipcHw_reset(uint32_t mask) chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT); } /* Bypass the PLL clocks before reboot */ - pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; - pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; + writel(readl(&pChipcHw->UARTClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT, + &pChipcHw->UARTClock); + writel(readl(&pChipcHw->SPIClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT, + &pChipcHw->SPIClock); /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */ do { - ((uint32_t *) MM_IO_BASE_ARAM)[i] = - ((uint32_t *) &chipcHw_reset_run_from_aram)[i]; + writel(((uint32_t *) &chipcHw_reset_run_from_aram)[i], ((uint32_t __iomem *) MM_IO_BASE_ARAM) + i); i++; - } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */ + } while (readl(((uint32_t __iomem*) MM_IO_BASE_ARAM) + i - 1) != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */ - CSP_CACHE_FLUSH_ALL; + flush_cache_all(); /* run the function from ARAM */ runFunc(); diff --git a/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw.c index 6b9be2e98e51..547f746c7ff4 100644 --- a/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw.c +++ b/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw.c @@ -25,11 +25,11 @@ /****************************************************************************/ /* ---- Include Files ---------------------------------------------------- */ -#include -#include -#include +#include +#include +#include -#include +#include #include #include #include @@ -55,33 +55,32 @@ static uint32_t GetFifoSize(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handl ) { uint32_t val = 0; dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); - dmacHw_MISC_t *pMiscReg = - (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module); + dmacHw_MISC_t __iomem *pMiscReg = (void __iomem *)dmacHw_REG_MISC_BASE(pCblk->module); switch (pCblk->channel) { case 0: - val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm2.lo) & 0x70000000) >> 28; break; case 1: - val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm3.hi) & 0x70000000) >> 28; break; case 2: - val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm3.lo) & 0x70000000) >> 28; break; case 3: - val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm4.hi) & 0x70000000) >> 28; break; case 4: - val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm4.lo) & 0x70000000) >> 28; break; case 5: - val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm5.hi) & 0x70000000) >> 28; break; case 6: - val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm5.lo) & 0x70000000) >> 28; break; case 7: - val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm6.hi) & 0x70000000) >> 28; break; } diff --git a/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c index a1f328357aa4..fe438699d11e 100644 --- a/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c +++ b/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c @@ -26,10 +26,10 @@ /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include +#include -#include +#include #include #include diff --git a/trunk/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/trunk/arch/arm/mach-bcmring/csp/tmr/tmrHw.c index 16225e43f3c3..dc4137ff75ca 100644 --- a/trunk/arch/arm/mach-bcmring/csp/tmr/tmrHw.c +++ b/trunk/arch/arm/mach-bcmring/csp/tmr/tmrHw.c @@ -26,10 +26,10 @@ /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include +#include -#include +#include #include #define tmrHw_ASSERT(a) if (!(a)) *(char *)0 = 0 diff --git a/trunk/arch/arm/mach-bcmring/include/cfg_global.h b/trunk/arch/arm/mach-bcmring/include/cfg_global.h deleted file mode 100644 index f01da877148e..000000000000 --- a/trunk/arch/arm/mach-bcmring/include/cfg_global.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _CFG_GLOBAL_H_ -#define _CFG_GLOBAL_H_ - -#include - -#define CFG_GLOBAL_CHIP BCM11107 -#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING -#define CFG_GLOBAL_CHIP_REV 0xB0 -#define CFG_GLOBAL_RAM_SIZE 0x10000000 -#define CFG_GLOBAL_RAM_BASE 0x00000000 -#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000 - -#endif /* _CFG_GLOBAL_H_ */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/cache.h b/trunk/arch/arm/mach-bcmring/include/csp/cache.h deleted file mode 100644 index caa20e59db99..000000000000 --- a/trunk/arch/arm/mach-bcmring/include/csp/cache.h +++ /dev/null @@ -1,35 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CSP_CACHE_H -#define CSP_CACHE_H - -/* ---- Include Files ---------------------------------------------------- */ - -#include - -/* ---- Public Constants and Types --------------------------------------- */ - -#if defined(__KERNEL__) && !defined(STANDALONE) -#include - -#define CSP_CACHE_FLUSH_ALL flush_cache_all() - -#else - -#define CSP_CACHE_FLUSH_ALL - -#endif - -#endif /* CSP_CACHE_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/delay.h b/trunk/arch/arm/mach-bcmring/include/csp/delay.h deleted file mode 100644 index 8b3d80367293..000000000000 --- a/trunk/arch/arm/mach-bcmring/include/csp/delay.h +++ /dev/null @@ -1,36 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - - -#ifndef CSP_DELAY_H -#define CSP_DELAY_H - -/* ---- Include Files ---------------------------------------------------- */ - -/* Some CSP routines require use of the following delay routines. Use the OS */ -/* version if available, otherwise use a CSP specific definition. */ -/* void udelay(unsigned long usecs); */ -/* void mdelay(unsigned long msecs); */ - -#if defined(__KERNEL__) && !defined(STANDALONE) - #include -#else - #include -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -#endif /* CSP_DELAY_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/errno.h b/trunk/arch/arm/mach-bcmring/include/csp/errno.h deleted file mode 100644 index 51357dd5b666..000000000000 --- a/trunk/arch/arm/mach-bcmring/include/csp/errno.h +++ /dev/null @@ -1,32 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CSP_ERRNO_H -#define CSP_ERRNO_H - -/* ---- Include Files ---------------------------------------------------- */ - -#if defined(__KERNEL__) -#include -#elif defined(CSP_SIMULATION) -#include -#else -#include -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -#endif /* CSP_ERRNO_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/intcHw.h b/trunk/arch/arm/mach-bcmring/include/csp/intcHw.h deleted file mode 100644 index 1c639c8ee08f..000000000000 --- a/trunk/arch/arm/mach-bcmring/include/csp/intcHw.h +++ /dev/null @@ -1,40 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - - -/****************************************************************************/ -/** -* @file intcHw.h -* -* @brief generic interrupt controller API -* -* @note -* None -*/ -/****************************************************************************/ - -#ifndef _INTCHW_H -#define _INTCHW_H - -/* ---- Include Files ---------------------------------------------------- */ -#include - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ -static inline void intcHw_irq_disable(void *basep, uint32_t mask); -static inline void intcHw_irq_enable(void *basep, uint32_t mask); - -#endif /* _INTCHW_H */ - diff --git a/trunk/arch/arm/mach-bcmring/include/csp/module.h b/trunk/arch/arm/mach-bcmring/include/csp/module.h deleted file mode 100644 index c30d2a5975a6..000000000000 --- a/trunk/arch/arm/mach-bcmring/include/csp/module.h +++ /dev/null @@ -1,32 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - - -#ifndef CSP_MODULE_H -#define CSP_MODULE_H - -/* ---- Include Files ---------------------------------------------------- */ - -#ifdef __KERNEL__ - #include -#else - #define EXPORT_SYMBOL(symbol) -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - - -#endif /* CSP_MODULE_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/secHw.h b/trunk/arch/arm/mach-bcmring/include/csp/secHw.h deleted file mode 100644 index b9d7e0732dfc..000000000000 --- a/trunk/arch/arm/mach-bcmring/include/csp/secHw.h +++ /dev/null @@ -1,65 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file secHw.h -* -* @brief Definitions for accessing low level security features -* -*/ -/****************************************************************************/ -#ifndef SECHW_H -#define SECHW_H - -typedef void (*secHw_FUNC_t) (void); - -typedef enum { - secHw_MODE_SECURE = 0x0, /* Switches processor into secure mode */ - secHw_MODE_NONSECURE = 0x1 /* Switches processor into non-secure mode */ -} secHw_MODE; - -/****************************************************************************/ -/** -* @brief Requesting to execute the function in secure mode -* -* This function requests the given function to run in secure mode -* -*/ -/****************************************************************************/ -void secHw_RunSecure(secHw_FUNC_t /* Function to run in secure mode */ - ); - -/****************************************************************************/ -/** -* @brief Sets the mode -* -* his function sets the processor mode (secure/non-secure) -* -*/ -/****************************************************************************/ -void secHw_SetMode(secHw_MODE /* Processor mode */ - ); - -/****************************************************************************/ -/** -* @brief Get the current mode -* -* This function retieves the processor mode (secure/non-secure) -* -*/ -/****************************************************************************/ -void secHw_GetMode(secHw_MODE *); - -#endif /* SECHW_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/stdint.h b/trunk/arch/arm/mach-bcmring/include/csp/stdint.h deleted file mode 100644 index 3a8718bbf700..000000000000 --- a/trunk/arch/arm/mach-bcmring/include/csp/stdint.h +++ /dev/null @@ -1,30 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CSP_STDINT_H -#define CSP_STDINT_H - -/* ---- Include Files ---------------------------------------------------- */ - -#ifdef __KERNEL__ -#include -#else -#include -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -#endif /* CSP_STDINT_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/string.h b/trunk/arch/arm/mach-bcmring/include/csp/string.h deleted file mode 100644 index ad9e4005f141..000000000000 --- a/trunk/arch/arm/mach-bcmring/include/csp/string.h +++ /dev/null @@ -1,34 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - - - -#ifndef CSP_STRING_H -#define CSP_STRING_H - -/* ---- Include Files ---------------------------------------------------- */ - -#ifdef __KERNEL__ - #include -#else - #include -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - - -#endif /* CSP_STRING_H */ - diff --git a/trunk/arch/arm/mach-bcmring/include/cfg_global_defines.h b/trunk/arch/arm/mach-bcmring/include/mach/cfg_global.h similarity index 74% rename from trunk/arch/arm/mach-bcmring/include/cfg_global_defines.h rename to trunk/arch/arm/mach-bcmring/include/mach/cfg_global.h index b5beb0b30734..449133eacdf5 100644 --- a/trunk/arch/arm/mach-bcmring/include/cfg_global_defines.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/cfg_global.h @@ -38,3 +38,14 @@ #define IMAGE_HEADER_SIZE_CHECKSUM 4 #endif +#ifndef _CFG_GLOBAL_H_ +#define _CFG_GLOBAL_H_ + +#define CFG_GLOBAL_CHIP BCM11107 +#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING +#define CFG_GLOBAL_CHIP_REV 0xB0 +#define CFG_GLOBAL_RAM_SIZE 0x10000000 +#define CFG_GLOBAL_RAM_BASE 0x00000000 +#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000 + +#endif /* _CFG_GLOBAL_H_ */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h index 933ce68ed90b..0a89e0c63419 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h @@ -17,7 +17,7 @@ /* ---- Include Files ---------------------------------------------------- */ #include -#include +#include /* ---- Public Constants and Types --------------------------------------- */ #define CAP_CONFIG0_VPM_DIS 0x00000001 diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h index 161973385faf..39f09cb89208 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h @@ -17,9 +17,9 @@ /* ---- Include Files ----------------------------------------------------- */ -#include -#include -#include +#include +#include +#include #include /* ---- Public Constants and Types ---------------------------------------- */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h index 03238c299001..a66f3f7abb86 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h @@ -17,8 +17,8 @@ /* ---- Include Files ----------------------------------------------------- */ -#include -#include +#include +#include #include #include @@ -47,7 +47,7 @@ static inline void chipcHw_setClock(chipcHw_CLOCK_e clock, /****************************************************************************/ static inline uint32_t chipcHw_getChipId(void) { - return pChipcHw->ChipId; + return readl(&pChipcHw->ChipId); } /****************************************************************************/ @@ -59,15 +59,16 @@ static inline uint32_t chipcHw_getChipId(void) /****************************************************************************/ static inline void chipcHw_enableSpreadSpectrum(void) { - if ((pChipcHw-> - PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != + if ((readl(&pChipcHw-> + PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { - ddrcReg_PHY_ADDR_CTL_REGP->ssCfg = - (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) | + writel((0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) | (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK << - ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT); - ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |= - ddrcReg_PHY_ADDR_SS_CTRL_ENABLE; + ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT), + &ddrcReg_PHY_ADDR_CTL_REGP->ssCfg); + writel(readl(&ddrcReg_PHY_ADDR_CTL_REGP->ssCtl) | + ddrcReg_PHY_ADDR_SS_CTRL_ENABLE, + &ddrcReg_PHY_ADDR_CTL_REGP->ssCtl); } } @@ -93,8 +94,8 @@ static inline void chipcHw_disableSpreadSpectrum(void) /****************************************************************************/ static inline uint32_t chipcHw_getChipProductId(void) { - return (pChipcHw-> - ChipId & chipcHw_REG_CHIPID_BASE_MASK) >> + return (readl(&pChipcHw-> + ChipId) & chipcHw_REG_CHIPID_BASE_MASK) >> chipcHw_REG_CHIPID_BASE_SHIFT; } @@ -109,7 +110,7 @@ static inline uint32_t chipcHw_getChipProductId(void) /****************************************************************************/ static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void) { - return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK; + return readl(&pChipcHw->ChipId) & chipcHw_REG_CHIPID_REV_MASK; } /****************************************************************************/ @@ -156,7 +157,7 @@ static inline void chipcHw_busInterfaceClockDisable(uint32_t mask) /****************************************************************************/ static inline uint32_t chipcHw_getBusInterfaceClockStatus(void) { - return pChipcHw->BusIntfClock; + return readl(&pChipcHw->BusIntfClock); } /****************************************************************************/ @@ -215,8 +216,9 @@ static inline void chipcHw_softResetDisable(uint64_t mask) /* Deassert module soft reset */ REG_LOCAL_IRQ_SAVE; - pChipcHw->SoftReset1 ^= ctrl1; - pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)); + writel(readl(&pChipcHw->SoftReset1) ^ ctrl1, &pChipcHw->SoftReset1); + writel(readl(&pChipcHw->SoftReset2) ^ (ctrl2 & + (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2); REG_LOCAL_IRQ_RESTORE; } @@ -227,9 +229,10 @@ static inline void chipcHw_softResetEnable(uint64_t mask) uint32_t unhold = 0; REG_LOCAL_IRQ_SAVE; - pChipcHw->SoftReset1 |= ctrl1; + writel(readl(&pChipcHw->SoftReset1) | ctrl1, &pChipcHw->SoftReset1); /* Mask out unhold request bits */ - pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)); + writel(readl(&pChipcHw->SoftReset2) | (ctrl2 & + (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2); /* Process unhold requests */ if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) { @@ -246,7 +249,7 @@ static inline void chipcHw_softResetEnable(uint64_t mask) if (unhold) { /* Make sure unhold request is effective */ - pChipcHw->SoftReset1 &= ~unhold; + writel(readl(&pChipcHw->SoftReset1) & ~unhold, &pChipcHw->SoftReset1); } REG_LOCAL_IRQ_RESTORE; } @@ -307,7 +310,7 @@ static inline void chipcHw_setOTPOption(uint64_t mask) /****************************************************************************/ static inline uint32_t chipcHw_getStickyBits(void) { - return pChipcHw->Sticky; + return readl(&pChipcHw->Sticky); } /****************************************************************************/ @@ -328,7 +331,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask) bits |= chipcHw_REG_STICKY_POR_BROM; } else { uint32_t sticky; - sticky = pChipcHw->Sticky; + sticky = readl(pChipcHw->Sticky); if ((mask & chipcHw_REG_STICKY_BOOT_DONE) && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) { @@ -355,7 +358,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask) bits |= chipcHw_REG_STICKY_GENERAL_5; } } - pChipcHw->Sticky = bits; + writel(bits, pChipcHw->Sticky); REG_LOCAL_IRQ_RESTORE; } @@ -377,7 +380,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask) (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 | chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 | chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) { - uint32_t sticky = pChipcHw->Sticky; + uint32_t sticky = readl(&pChipcHw->Sticky); if ((mask & chipcHw_REG_STICKY_BOOT_DONE) && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) { @@ -410,7 +413,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask) mask &= ~chipcHw_REG_STICKY_GENERAL_5; } } - pChipcHw->Sticky = bits | mask; + writel(bits | mask, &pChipcHw->Sticky); REG_LOCAL_IRQ_RESTORE; } @@ -426,7 +429,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask) /****************************************************************************/ static inline uint32_t chipcHw_getSoftStraps(void) { - return pChipcHw->SoftStraps; + return readl(&pChipcHw->SoftStraps); } /****************************************************************************/ @@ -456,7 +459,7 @@ static inline void chipcHw_setSoftStraps(uint32_t strapOptions) /****************************************************************************/ static inline uint32_t chipcHw_getPinStraps(void) { - return pChipcHw->PinStraps; + return readl(&pChipcHw->PinStraps); } /****************************************************************************/ @@ -671,9 +674,9 @@ static inline void chipcHw_selectGE3(void) /****************************************************************************/ static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin) { - return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) & + return (readl(chipcHw_REG_GPIO_MUX(pin))) & (chipcHw_REG_GPIO_MUX_MASK << - chipcHw_REG_GPIO_MUX_POSITION(pin))) >> + chipcHw_REG_GPIO_MUX_POSITION(pin)) >> chipcHw_REG_GPIO_MUX_POSITION(pin); } @@ -841,8 +844,8 @@ static inline void chipcHw_setUsbDevice(void) static inline void chipcHw_setClock(chipcHw_CLOCK_e clock, chipcHw_OPTYPE_e type, int mode) { - volatile uint32_t *pPLLReg = (uint32_t *) 0x0; - volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; + uint32_t __iomem *pPLLReg = NULL; + uint32_t __iomem *pClockCtrl = NULL; switch (clock) { case chipcHw_CLOCK_DDR: @@ -1071,7 +1074,7 @@ static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock) /****************************************************************************/ static inline int chipcHw_isSoftwareStrapsEnable(void) { - return pChipcHw->SoftStraps & 0x00000001; + return readl(&pChipcHw->SoftStraps) & 0x00000001; } /****************************************************************************/ @@ -1138,7 +1141,7 @@ static inline void chipcHw_pll2TestDisable(void) /****************************************************************************/ static inline int chipcHw_isPllTestEnable(void) { - return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; + return readl(&pChipcHw->PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; } /****************************************************************************/ @@ -1147,7 +1150,7 @@ static inline int chipcHw_isPllTestEnable(void) /****************************************************************************/ static inline int chipcHw_isPll2TestEnable(void) { - return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; + return readl(&pChipcHw->PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; } /****************************************************************************/ @@ -1183,8 +1186,8 @@ static inline void chipcHw_pll2TestSelect(uint32_t val) /****************************************************************************/ static inline uint8_t chipcHw_getPllTestSelected(void) { - return (uint8_t) ((pChipcHw-> - PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) + return (uint8_t) ((readl(&pChipcHw-> + PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT); } @@ -1194,8 +1197,8 @@ static inline uint8_t chipcHw_getPllTestSelected(void) /****************************************************************************/ static inline uint8_t chipcHw_getPll2TestSelected(void) { - return (uint8_t) ((pChipcHw-> - PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) + return (uint8_t) ((readl(&pChipcHw-> + PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT); } @@ -1208,7 +1211,8 @@ static inline uint8_t chipcHw_getPll2TestSelected(void) static inline void chipcHw_pll1Disable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN; + writel(readl(&pChipcHw->PLLConfig) | chipcHw_REG_PLL_CONFIG_POWER_DOWN, + &pChipcHw->PLLConfig); REG_LOCAL_IRQ_RESTORE; } @@ -1221,7 +1225,8 @@ static inline void chipcHw_pll1Disable(void) static inline void chipcHw_pll2Disable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN; + writel(readl(&pChipcHw->PLLConfig2) | chipcHw_REG_PLL_CONFIG_POWER_DOWN, + &pChipcHw->PLLConfig2); REG_LOCAL_IRQ_RESTORE; } @@ -1233,7 +1238,8 @@ static inline void chipcHw_pll2Disable(void) static inline void chipcHw_ddrPhaseAlignInterruptEnable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; + writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE, + &pChipcHw->Spare1); REG_LOCAL_IRQ_RESTORE; } @@ -1245,7 +1251,8 @@ static inline void chipcHw_ddrPhaseAlignInterruptEnable(void) static inline void chipcHw_ddrPhaseAlignInterruptDisable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; + writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE, + &pChipcHw->Spare1); REG_LOCAL_IRQ_RESTORE; } @@ -1333,7 +1340,8 @@ static inline void chipcHw_ddrHwPhaseAlignDisable(void) static inline void chipcHw_vpmSwPhaseAlignEnable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE; + writel(readl(&pChipcHw->VPMPhaseCtrl1) | chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE, + &pChipcHw->VPMPhaseCtrl1); REG_LOCAL_IRQ_RESTORE; } @@ -1372,7 +1380,8 @@ static inline void chipcHw_vpmHwPhaseAlignEnable(void) static inline void chipcHw_vpmHwPhaseAlignDisable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE; + writel(readl(&pChipcHw->VPMPhaseCtrl1) & ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE, + &pChipcHw->VPMPhaseCtrl1); REG_LOCAL_IRQ_RESTORE; } @@ -1474,8 +1483,8 @@ chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin) /****************************************************************************/ static inline uint32_t chipcHw_isDdrHwPhaseAligned(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0; + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0; } /****************************************************************************/ @@ -1488,8 +1497,8 @@ static inline uint32_t chipcHw_isDdrHwPhaseAligned(void) /****************************************************************************/ static inline uint32_t chipcHw_isVpmHwPhaseAligned(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0; + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0; } /****************************************************************************/ @@ -1500,8 +1509,8 @@ static inline uint32_t chipcHw_isVpmHwPhaseAligned(void) /****************************************************************************/ static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >> + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_STATUS_MASK) >> chipcHw_REG_DDR_PHASE_STATUS_SHIFT; } @@ -1513,8 +1522,8 @@ static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void) /****************************************************************************/ static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >> + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_STATUS_MASK) >> chipcHw_REG_VPM_PHASE_STATUS_SHIFT; } @@ -1526,8 +1535,8 @@ static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void) /****************************************************************************/ static inline uint32_t chipcHw_getDdrPhaseControl(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >> + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_CTRL_MASK) >> chipcHw_REG_DDR_PHASE_CTRL_SHIFT; } @@ -1539,8 +1548,8 @@ static inline uint32_t chipcHw_getDdrPhaseControl(void) /****************************************************************************/ static inline uint32_t chipcHw_getVpmPhaseControl(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >> + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_CTRL_MASK) >> chipcHw_REG_VPM_PHASE_CTRL_SHIFT; } diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h index b162448f613c..26f5d0e4e1dd 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h @@ -24,7 +24,7 @@ #define CHIPCHW_REG_H #include -#include +#include #include #define chipcHw_BASE_ADDRESS MM_IO_BASE_CHIPC @@ -131,8 +131,8 @@ typedef struct { uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */ } chipcHw_REG_t; -#define pChipcHw ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS) -#define pChipcPhysical ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC) +#define pChipcHw ((chipcHw_REG_t __iomem *) chipcHw_BASE_ADDRESS) +#define pChipcPhysical (MM_ADDR_IO_CHIPC) #define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000 #define chipcHw_REG_CHIPID_BASE_SHIFT 12 diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h index f1b68e26fa6d..39da2c1fdafb 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h @@ -30,8 +30,8 @@ extern "C" { /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include +#include #include @@ -416,7 +416,7 @@ extern "C" { } ddrcReg_PHY_ADDR_CTL_REG_t; #define ddrcReg_PHY_ADDR_CTL_REG_OFFSET 0x0400 -#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET)) +#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t __iomem*) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET)) /* @todo These SS definitions are duplicates of ones below */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/dmacHw.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h similarity index 99% rename from trunk/arch/arm/mach-bcmring/include/csp/dmacHw.h rename to trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h index e6a1dc484ca7..9dc90f46a84d 100644 --- a/trunk/arch/arm/mach-bcmring/include/csp/dmacHw.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h @@ -23,9 +23,9 @@ #ifndef _DMACHW_H #define _DMACHW_H -#include +#include -#include +#include #include /* Define DMA Channel ID using DMA controller number (m) and channel number (c). diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h index d67e2f8c22de..9d9455e0c391 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h @@ -24,7 +24,7 @@ #ifndef _DMACHW_PRIV_H #define _DMACHW_PRIV_H -#include +#include /* Data type for DMA Link List Item */ typedef struct { diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h index f1ecf96f2da5..7cd0aafa6f6e 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h @@ -24,7 +24,7 @@ #ifndef _DMACHW_REG_H #define _DMACHW_REG_H -#include +#include #include /* Data type for 64 bit little endian register */ @@ -121,75 +121,75 @@ typedef struct { } dmacHw_MISC_t; /* Base registers */ -#define dmacHw_0_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */ -#define dmacHw_1_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */ +#define dmacHw_0_MODULE_BASE_ADDR (char __iomem*) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */ +#define dmacHw_1_MODULE_BASE_ADDR (char __iomem*) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */ extern uint32_t dmaChannelCount_0; extern uint32_t dmaChannelCount_1; /* Define channel specific registers */ -#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t)))) +#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t __iomem*) ((char __iomem*)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t)))) /* Raw interrupt status registers */ -#define dmacHw_REG_INT_RAW_BASE(module) ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0))) -#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo) -#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo) -#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo) -#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo) -#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo) +#define dmacHw_REG_INT_RAW_BASE(module) ((char __iomem *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0))) +#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo) +#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo) +#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo) +#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo) +#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo) /* Interrupt status registers */ -#define dmacHw_REG_INT_STAT_BASE(module) ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t))) -#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo) -#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo) -#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo) -#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo) -#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo) +#define dmacHw_REG_INT_STAT_BASE(module) ((char __iomem*)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t))) +#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo) +#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo) +#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo) +#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo) +#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo) /* Interrupt status registers */ -#define dmacHw_REG_INT_MASK_BASE(module) ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t))) -#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo) -#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo) -#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo) -#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo) -#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo) +#define dmacHw_REG_INT_MASK_BASE(module) ((char __iomem*)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t))) +#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo) +#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo) +#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo) +#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo) +#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo) /* Interrupt clear registers */ -#define dmacHw_REG_INT_CLEAR_BASE(module) ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t))) -#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo) -#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo) -#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo) -#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo) -#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo) -#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo) +#define dmacHw_REG_INT_CLEAR_BASE(module) ((char __iomem*)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t))) +#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo) +#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo) +#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo) +#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo) +#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo) +#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo) /* Software handshaking registers */ -#define dmacHw_REG_SW_HS_BASE(module) ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t))) -#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo) -#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo) -#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo) +#define dmacHw_REG_SW_HS_BASE(module) ((char __iomem*)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t))) +#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo) +#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo) +#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo) +#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo) +#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo) +#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo) /* Miscellaneous registers */ -#define dmacHw_REG_MISC_BASE(module) ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t))) -#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo) -#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo) -#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo) -#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo) -#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo) -#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi) -#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo) -#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi) -#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo) -#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi) -#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo) -#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi) -#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo) -#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi) -#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo) -#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi) +#define dmacHw_REG_MISC_BASE(module) ((char __iomem*)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t))) +#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo) +#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo) +#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo) +#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo) +#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo) +#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi) +#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo) +#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi) +#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo) +#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi) +#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo) +#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi) +#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo) +#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi) +#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo) +#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi) /* Channel control registers */ #define dmacHw_REG_SAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo) diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h index cfa91bed9d34..27f59dd27792 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h @@ -18,7 +18,7 @@ /* ---- Include Files ---------------------------------------------------- */ -#include +#include #include #if defined(__KERNEL__) diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h index 0aeb6a6fe7f8..f59db25b5632 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h @@ -27,8 +27,8 @@ #define _INTCHW_REG_H /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include +#include #include /* ---- Public Constants and Types --------------------------------------- */ @@ -37,9 +37,9 @@ #define INTCHW_NUM_INTC 3 /* Defines for interrupt controllers. This simplifies and cleans up the function calls. */ -#define INTCHW_INTC0 ((void *)MM_IO_BASE_INTC0) -#define INTCHW_INTC1 ((void *)MM_IO_BASE_INTC1) -#define INTCHW_SINTC ((void *)MM_IO_BASE_SINTC) +#define INTCHW_INTC0 (MM_IO_BASE_INTC0) +#define INTCHW_INTC1 (MM_IO_BASE_INTC1) +#define INTCHW_SINTC (MM_IO_BASE_SINTC) /* INTC0 - interrupt controller 0 */ #define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */ @@ -232,15 +232,15 @@ /* ---- Public Variable Externs ------------------------------------------ */ /* ---- Public Function Prototypes --------------------------------------- */ /* Clear one or more IRQ interrupts. */ -static inline void intcHw_irq_disable(void *basep, uint32_t mask) +static inline void intcHw_irq_disable(void __iomem *basep, uint32_t mask) { - __REG32(basep + INTCHW_INTENCLEAR) = mask; + writel(mask, basep + INTCHW_INTENCLEAR); } /* Enables one or more IRQ interrupts. */ -static inline void intcHw_irq_enable(void *basep, uint32_t mask) +static inline void intcHw_irq_enable(void __iomem *basep, uint32_t mask) { - __REG32(basep + INTCHW_INTENABLE) = mask; + writel(mask, basep + INTCHW_INTENABLE); } #endif /* _INTCHW_REG_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h index ad58cf873377..d571962f2904 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h @@ -29,7 +29,7 @@ /* ---- Include Files ---------------------------------------------------- */ #if !defined(CSP_SIMULATION) -#include +#include #endif /* ---- Public Constants and Types --------------------------------------- */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_io.h index de92ec6a01aa..47450c23685a 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_io.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_io.h @@ -30,7 +30,7 @@ #include #if !defined(CSP_SIMULATION) -#include +#include #endif /* ---- Public Constants and Types --------------------------------------- */ @@ -49,7 +49,7 @@ #ifdef __ASSEMBLY__ #define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)) #else -#define MM_IO_PHYS_TO_VIRT(phys) (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \ +#define MM_IO_PHYS_TO_VIRT(phys) (void __iomem *)(((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \ (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))) #endif #endif @@ -60,8 +60,8 @@ #ifdef __ASSEMBLY__ #define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)) #else -#define MM_IO_VIRT_TO_PHYS(virt) (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \ - ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))) +#define MM_IO_VIRT_TO_PHYS(virt) (((unsigned long)(virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \ + ((((unsigned long)(virt) & 0x0F000000) << 4) | ((unsigned long)(virt) & 0xFFFFFF))) #endif #endif diff --git a/trunk/arch/arm/mach-bcmring/include/csp/reg.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/reg.h similarity index 81% rename from trunk/arch/arm/mach-bcmring/include/csp/reg.h rename to trunk/arch/arm/mach-bcmring/include/mach/csp/reg.h index 56654d23c3d7..d9cbdca8cd25 100644 --- a/trunk/arch/arm/mach-bcmring/include/csp/reg.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/reg.h @@ -25,13 +25,14 @@ /* ---- Include Files ---------------------------------------------------- */ -#include +#include +#include /* ---- Public Constants and Types --------------------------------------- */ -#define __REG32(x) (*((volatile uint32_t *)(x))) -#define __REG16(x) (*((volatile uint16_t *)(x))) -#define __REG8(x) (*((volatile uint8_t *) (x))) +#define __REG32(x) (*((volatile uint32_t __iomem *)(x))) +#define __REG16(x) (*((volatile uint16_t __iomem *)(x))) +#define __REG8(x) (*((volatile uint8_t __iomem *) (x))) /* Macros used to define a sequence of reserved registers. The start / end */ /* are byte offsets in the particular register definition, with the "end" */ @@ -84,31 +85,31 @@ #endif -static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value) +static inline void reg32_modify_and(volatile uint32_t __iomem *reg, uint32_t value) { REG_LOCAL_IRQ_SAVE; - *reg &= value; + __raw_writel(__raw_readl(reg) & value, reg); REG_LOCAL_IRQ_RESTORE; } -static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value) +static inline void reg32_modify_or(volatile uint32_t __iomem *reg, uint32_t value) { REG_LOCAL_IRQ_SAVE; - *reg |= value; + __raw_writel(__raw_readl(reg) | value, reg); REG_LOCAL_IRQ_RESTORE; } -static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask, +static inline void reg32_modify_mask(volatile uint32_t __iomem *reg, uint32_t mask, uint32_t value) { REG_LOCAL_IRQ_SAVE; - *reg = (*reg & mask) | value; + __raw_writel((__raw_readl(reg) & mask) | value, reg); REG_LOCAL_IRQ_RESTORE; } -static inline void reg32_write(volatile uint32_t *reg, uint32_t value) +static inline void reg32_write(volatile uint32_t __iomem *reg, uint32_t value) { - *reg = value; + __raw_writel(value, reg); } #endif /* CSP_REG_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h index 9cd6a032ab71..55d3cd4fd1e7 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h @@ -34,7 +34,7 @@ /****************************************************************************/ static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ ) { - secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; + secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC; if (mask & 0x0000FFFF) { regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF; @@ -53,13 +53,13 @@ static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK /****************************************************************************/ static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ ) { - secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; + secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC; if (mask & 0x0000FFFF) { - regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF; + writel(mask & 0x0000FFFF, ®p->reg[secHw_IDX_LS].setUnsecure); } if (mask & 0xFFFF0000) { - regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16; + writel(mask >> 16, ®p->reg[secHw_IDX_MS].setUnsecure); } } @@ -71,7 +71,7 @@ static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MA /****************************************************************************/ static inline uint32_t secHw_getStatus(void) { - secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; + secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC; return (regp->reg[1].status << 16) + regp->reg[0].status; } diff --git a/trunk/arch/arm/mach-bcmring/include/csp/tmrHw.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h similarity index 99% rename from trunk/arch/arm/mach-bcmring/include/csp/tmrHw.h rename to trunk/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h index 2cbb530db8ea..1cc882ae60f5 100644 --- a/trunk/arch/arm/mach-bcmring/include/csp/tmrHw.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h @@ -23,7 +23,7 @@ #ifndef _TMRHW_H #define _TMRHW_H -#include +#include typedef uint32_t tmrHw_ID_t; /* Timer ID */ typedef uint32_t tmrHw_COUNT_t; /* Timer count */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/dma.h b/trunk/arch/arm/mach-bcmring/include/mach/dma.h index 72543781207b..13e01384d6fc 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/dma.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/dma.h @@ -27,7 +27,7 @@ #include #include -#include +#include #include /* ---- Constants and Types ---------------------------------------------- */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/hardware.h b/trunk/arch/arm/mach-bcmring/include/mach/hardware.h index 6ae20a649a97..a0c92b4b8c60 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/hardware.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/hardware.h @@ -22,7 +22,7 @@ #define __ASM_ARCH_HARDWARE_H #include -#include +#include #include /* Hardware addresses of major areas. diff --git a/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h b/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h index 387376ffb56b..f8d51a8b0b15 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h @@ -30,7 +30,7 @@ #define __ASM_ARCH_REG_NAND_H /* ---- Include Files ---------------------------------------------------- */ -#include +#include #include /* ---- Constants and Types ---------------------------------------------- */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h b/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h index 0992842caa77..56dd9de7d83f 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h @@ -30,7 +30,7 @@ #define __ASM_ARCH_REG_UMI_H /* ---- Include Files ---------------------------------------------------- */ -#include +#include #include /* ---- Constants and Types ---------------------------------------------- */ @@ -233,5 +233,5 @@ #define REG_UMI_BCH_ERR_LOC_WORD 0x00000018 /* location within a page (512 byte) */ #define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0 -#define REG_UMI_BCH_ERR_LOC_ADDR(index) (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16)) +#define REG_UMI_BCH_ERR_LOC_ADDR(index) (readl(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16)) #endif diff --git a/trunk/arch/arm/mach-bcmring/mm.c b/trunk/arch/arm/mach-bcmring/mm.c index 1adec78ec940..33824a81cac4 100644 --- a/trunk/arch/arm/mach-bcmring/mm.c +++ b/trunk/arch/arm/mach-bcmring/mm.c @@ -20,12 +20,12 @@ #include #include -#define IO_DESC(va, sz) { .virtual = va, \ +#define IO_DESC(va, sz) { .virtual = (unsigned long)va, \ .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ .length = sz, \ .type = MT_DEVICE } -#define MEM_DESC(va, sz) { .virtual = va, \ +#define MEM_DESC(va, sz) { .virtual = (unsigned long)va, \ .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ .length = sz, \ .type = MT_MEMORY } diff --git a/trunk/arch/arm/mach-bcmring/timer.c b/trunk/arch/arm/mach-bcmring/timer.c index af9c3d7e2a0c..59412903466e 100644 --- a/trunk/arch/arm/mach-bcmring/timer.c +++ b/trunk/arch/arm/mach-bcmring/timer.c @@ -14,7 +14,7 @@ #include #include -#include +#include #include /* The core.c file initializes timers 1 and 3 as a linux clocksource. */ diff --git a/trunk/arch/arm/mach-dove/common.c b/trunk/arch/arm/mach-dove/common.c index 6321567d8eaa..bd54d7b7ef85 100644 --- a/trunk/arch/arm/mach-dove/common.c +++ b/trunk/arch/arm/mach-dove/common.c @@ -49,16 +49,6 @@ static struct map_desc dove_io_desc[] __initdata = { .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), .length = DOVE_NB_REGS_SIZE, .type = MT_DEVICE, - }, { - .virtual = DOVE_PCIE0_IO_VIRT_BASE, - .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE), - .length = DOVE_PCIE0_IO_SIZE, - .type = MT_DEVICE, - }, { - .virtual = DOVE_PCIE1_IO_VIRT_BASE, - .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE), - .length = DOVE_PCIE1_IO_SIZE, - .type = MT_DEVICE, }, }; @@ -289,7 +279,7 @@ void __init dove_init(void) printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); #ifdef CONFIG_CACHE_TAUROS2 - tauros2_init(); + tauros2_init(0); #endif dove_setup_cpu_mbus(); diff --git a/trunk/arch/arm/mach-dove/include/mach/dove.h b/trunk/arch/arm/mach-dove/include/mach/dove.h index d52b0ef313b7..c91e3004a47b 100644 --- a/trunk/arch/arm/mach-dove/include/mach/dove.h +++ b/trunk/arch/arm/mach-dove/include/mach/dove.h @@ -50,14 +50,12 @@ #define DOVE_NB_REGS_SIZE SZ_8M #define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 -#define DOVE_PCIE0_IO_VIRT_BASE 0xfee00000 #define DOVE_PCIE0_IO_BUS_BASE 0x00000000 -#define DOVE_PCIE0_IO_SIZE SZ_1M +#define DOVE_PCIE0_IO_SIZE SZ_64K #define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000 -#define DOVE_PCIE1_IO_VIRT_BASE 0xfef00000 -#define DOVE_PCIE1_IO_BUS_BASE 0x00100000 -#define DOVE_PCIE1_IO_SIZE SZ_1M +#define DOVE_PCIE1_IO_BUS_BASE 0x00010000 +#define DOVE_PCIE1_IO_SIZE SZ_64K /* * Dove Core Registers Map diff --git a/trunk/arch/arm/mach-dove/include/mach/gpio.h b/trunk/arch/arm/mach-dove/include/mach/gpio.h deleted file mode 100644 index e7e5101e35a5..000000000000 --- a/trunk/arch/arm/mach-dove/include/mach/gpio.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * arch/arm/mach-dove/include/mach/gpio.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include diff --git a/trunk/arch/arm/mach-dove/include/mach/io.h b/trunk/arch/arm/mach-dove/include/mach/io.h deleted file mode 100644 index 29c8b85355a5..000000000000 --- a/trunk/arch/arm/mach-dove/include/mach/io.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-dove/include/mach/io.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include "dove.h" - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \ - DOVE_PCIE0_IO_VIRT_BASE)) - -#endif diff --git a/trunk/arch/arm/mach-dove/irq.c b/trunk/arch/arm/mach-dove/irq.c index 9bc97a5baaa8..186357f3b4db 100644 --- a/trunk/arch/arm/mach-dove/irq.c +++ b/trunk/arch/arm/mach-dove/irq.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "common.h" static void pmu_irq_mask(struct irq_data *d) diff --git a/trunk/arch/arm/mach-dove/mpp.c b/trunk/arch/arm/mach-dove/mpp.c index 7f70afc26f91..60bd729a1ba5 100644 --- a/trunk/arch/arm/mach-dove/mpp.c +++ b/trunk/arch/arm/mach-dove/mpp.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "mpp.h" struct dove_mpp_grp { diff --git a/trunk/arch/arm/mach-dove/pcie.c b/trunk/arch/arm/mach-dove/pcie.c index 47921b0cdc65..355332d502cb 100644 --- a/trunk/arch/arm/mach-dove/pcie.c +++ b/trunk/arch/arm/mach-dove/pcie.c @@ -26,9 +26,8 @@ struct pcie_port { u8 root_bus_nr; void __iomem *base; spinlock_t conf_lock; - char io_space_name[16]; char mem_space_name[16]; - struct resource res[2]; + struct resource res; }; static struct pcie_port pcie_port[2]; @@ -53,24 +52,10 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) orion_pcie_setup(pp->base); - /* - * IORESOURCE_IO - */ - snprintf(pp->io_space_name, sizeof(pp->io_space_name), - "PCIe %d I/O", pp->index); - pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; - pp->res[0].name = pp->io_space_name; - if (pp->index == 0) { - pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE; - pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1; - } else { - pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE; - pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1; - } - pp->res[0].flags = IORESOURCE_IO; - if (request_resource(&ioport_resource, &pp->res[0])) - panic("Request PCIe IO resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); + if (pp->index == 0) + pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE); + else + pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE); /* * IORESOURCE_MEM @@ -78,18 +63,18 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), "PCIe %d MEM", pp->index); pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; - pp->res[1].name = pp->mem_space_name; + pp->res.name = pp->mem_space_name; if (pp->index == 0) { - pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE; - pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1; + pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE; + pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1; } else { - pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE; - pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1; + pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE; + pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1; } - pp->res[1].flags = IORESOURCE_MEM; - if (request_resource(&iomem_resource, &pp->res[1])) + pp->res.flags = IORESOURCE_MEM; + if (request_resource(&iomem_resource, &pp->res)) panic("Request PCIe Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); return 1; } @@ -210,7 +195,7 @@ static void __init add_pcie_port(int index, unsigned long base) pp->root_bus_nr = -1; pp->base = (void __iomem *)base; spin_lock_init(&pp->conf_lock); - memset(pp->res, 0, sizeof(pp->res)); + memset(&pp->res, 0, sizeof(pp->res)); } else { printk(KERN_INFO "link down, ignoring\n"); } diff --git a/trunk/arch/arm/mach-ebsa110/core.c b/trunk/arch/arm/mach-ebsa110/core.c index 6f8068692edf..f0fe6b5350e2 100644 --- a/trunk/arch/arm/mach-ebsa110/core.c +++ b/trunk/arch/arm/mach-ebsa110/core.c @@ -74,22 +74,22 @@ static struct map_desc ebsa110_io_desc[] __initdata = { * sparse external-decode ISAIO space */ { /* IRQ_STAT/IRQ_MCLR */ - .virtual = IRQ_STAT, + .virtual = (unsigned long)IRQ_STAT, .pfn = __phys_to_pfn(TRICK4_PHYS), .length = TRICK4_SIZE, .type = MT_DEVICE }, { /* IRQ_MASK/IRQ_MSET */ - .virtual = IRQ_MASK, + .virtual = (unsigned long)IRQ_MASK, .pfn = __phys_to_pfn(TRICK3_PHYS), .length = TRICK3_SIZE, .type = MT_DEVICE }, { /* SOFT_BASE */ - .virtual = SOFT_BASE, + .virtual = (unsigned long)SOFT_BASE, .pfn = __phys_to_pfn(TRICK1_PHYS), .length = TRICK1_SIZE, .type = MT_DEVICE }, { /* PIT_BASE */ - .virtual = PIT_BASE, + .virtual = (unsigned long)PIT_BASE, .pfn = __phys_to_pfn(TRICK0_PHYS), .length = TRICK0_SIZE, .type = MT_DEVICE diff --git a/trunk/arch/arm/mach-ebsa110/core.h b/trunk/arch/arm/mach-ebsa110/core.h index c93c9e43012d..afe137ee172e 100644 --- a/trunk/arch/arm/mach-ebsa110/core.h +++ b/trunk/arch/arm/mach-ebsa110/core.h @@ -31,11 +31,11 @@ #define TRICK7_PHYS 0xf3c00000 /* Virtual addresses */ -#define PIT_BASE 0xfc000000 /* trick 0 */ -#define SOFT_BASE 0xfd000000 /* trick 1 */ -#define IRQ_MASK 0xfe000000 /* trick 3 - read */ -#define IRQ_MSET 0xfe000000 /* trick 3 - write */ -#define IRQ_STAT 0xff000000 /* trick 4 - read */ -#define IRQ_MCLR 0xff000000 /* trick 4 - write */ +#define PIT_BASE IOMEM(0xfc000000) /* trick 0 */ +#define SOFT_BASE IOMEM(0xfd000000) /* trick 1 */ +#define IRQ_MASK IOMEM(0xfe000000) /* trick 3 - read */ +#define IRQ_MSET IOMEM(0xfe000000) /* trick 3 - write */ +#define IRQ_STAT IOMEM(0xff000000) /* trick 4 - read */ +#define IRQ_MCLR IOMEM(0xff000000) /* trick 4 - write */ #endif diff --git a/trunk/arch/arm/mach-ep93xx/include/mach/gpio.h b/trunk/arch/arm/mach-ep93xx/include/mach/gpio.h deleted file mode 100644 index 40a8c178f10d..000000000000 --- a/trunk/arch/arm/mach-ep93xx/include/mach/gpio.h +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/trunk/arch/arm/mach-exynos/Makefile.boot b/trunk/arch/arm/mach-exynos/Makefile.boot index 31bd181b0514..b9862e22bf10 100644 --- a/trunk/arch/arm/mach-exynos/Makefile.boot +++ b/trunk/arch/arm/mach-exynos/Makefile.boot @@ -1,5 +1,2 @@ zreladdr-y += 0x40008000 params_phys-y := 0x40000100 - -dtb-$(CONFIG_MACH_EXYNOS4_DT) += exynos4210-origen.dtb exynos4210-smdkv310.dtb -dtb-$(CONFIG_MACH_EXYNOS5_DT) += exynos5250-smdk5250.dtb diff --git a/trunk/arch/arm/mach-exynos/clock-exynos5.c b/trunk/arch/arm/mach-exynos/clock-exynos5.c index 774533c67066..3b00e299b624 100644 --- a/trunk/arch/arm/mach-exynos/clock-exynos5.c +++ b/trunk/arch/arm/mach-exynos/clock-exynos5.c @@ -166,11 +166,6 @@ static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable) return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable); } -static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable); -} - static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable); @@ -671,10 +666,6 @@ static struct clk exynos5_init_clocks_off[] = { .name = "usbotg", .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 7), - }, { - .name = "gps", - .enable = exynos5_clk_ip_gps_ctrl, - .ctrlbit = ((1 << 3) | (1 << 2) | (1 << 0)), }, { .name = "nfcon", .enable = exynos5_clk_ip_fsys_ctrl, diff --git a/trunk/arch/arm/mach-exynos/common.h b/trunk/arch/arm/mach-exynos/common.h index aed2eeb06517..dac146df79ac 100644 --- a/trunk/arch/arm/mach-exynos/common.h +++ b/trunk/arch/arm/mach-exynos/common.h @@ -14,6 +14,7 @@ extern struct sys_timer exynos4_timer; +struct map_desc; void exynos_init_io(struct map_desc *mach_desc, int size); void exynos4_init_irq(void); void exynos5_init_irq(void); @@ -59,4 +60,8 @@ void exynos4212_register_clocks(void); #define exynos4212_register_clocks() #endif +extern struct smp_operations exynos_smp_ops; + +extern void exynos_cpu_die(unsigned int cpu); + #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */ diff --git a/trunk/arch/arm/mach-exynos/hotplug.c b/trunk/arch/arm/mach-exynos/hotplug.c index 9c17a0a43858..f4d7dd20cdac 100644 --- a/trunk/arch/arm/mach-exynos/hotplug.c +++ b/trunk/arch/arm/mach-exynos/hotplug.c @@ -21,7 +21,7 @@ #include -extern volatile int pen_release; +#include "common.h" static inline void cpu_enter_lowpower(void) { @@ -95,17 +95,12 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious) } } -int platform_cpu_kill(unsigned int cpu) -{ - return 1; -} - /* * platform-specific code to shutdown a CPU * * Called with IRQs disabled */ -void platform_cpu_die(unsigned int cpu) +void __ref exynos_cpu_die(unsigned int cpu) { int spurious = 0; @@ -124,12 +119,3 @@ void platform_cpu_die(unsigned int cpu) if (spurious) pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); } - -int platform_cpu_disable(unsigned int cpu) -{ - /* - * we don't allow CPU 0 to be shutdown (it is still too special - * e.g. clock tick interrupts) - */ - return cpu == 0 ? -EPERM : 0; -} diff --git a/trunk/arch/arm/mach-exynos/include/mach/map.h b/trunk/arch/arm/mach-exynos/include/mach/map.h index c72b675b3e4b..9d1f3ac86db2 100644 --- a/trunk/arch/arm/mach-exynos/include/mach/map.h +++ b/trunk/arch/arm/mach-exynos/include/mach/map.h @@ -131,7 +131,6 @@ #define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000 #define EXYNOS5_PA_SYSMMU_IOP 0x12360000 #define EXYNOS5_PA_SYSMMU_RTIC 0x12370000 -#define EXYNOS5_PA_SYSMMU_GPS 0x12630000 #define EXYNOS5_PA_SYSMMU_ISP 0x13260000 #define EXYNOS5_PA_SYSMMU_DRC 0x12370000 #define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000 diff --git a/trunk/arch/arm/mach-exynos/mach-armlex4210.c b/trunk/arch/arm/mach-exynos/mach-armlex4210.c index 5a3daa0168d8..3f37a5e8a1f4 100644 --- a/trunk/arch/arm/mach-exynos/mach-armlex4210.c +++ b/trunk/arch/arm/mach-exynos/mach-armlex4210.c @@ -199,6 +199,7 @@ static void __init armlex4210_machine_init(void) MACHINE_START(ARMLEX4210, "ARMLEX4210") /* Maintainer: Alim Akhtar */ .atag_offset = 0x100, + .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = armlex4210_map_io, .handle_irq = gic_handle_irq, diff --git a/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c b/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c index ef770bc2318f..8833060f77e9 100644 --- a/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -79,6 +79,7 @@ static char const *exynos5250_dt_compat[] __initdata = { DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") /* Maintainer: Kukjin Kim */ .init_irq = exynos5_init_irq, + .smp = smp_ops(exynos_smp_ops), .map_io = exynos5250_dt_map_io, .handle_irq = gic_handle_irq, .init_machine = exynos5250_dt_machine_init, diff --git a/trunk/arch/arm/mach-exynos/mach-nuri.c b/trunk/arch/arm/mach-exynos/mach-nuri.c index ea785fcaf6c3..ffaa355c1bde 100644 --- a/trunk/arch/arm/mach-exynos/mach-nuri.c +++ b/trunk/arch/arm/mach-exynos/mach-nuri.c @@ -1383,6 +1383,7 @@ static void __init nuri_machine_init(void) MACHINE_START(NURI, "NURI") /* Maintainer: Kyungmin Park */ .atag_offset = 0x100, + .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = nuri_map_io, .handle_irq = gic_handle_irq, diff --git a/trunk/arch/arm/mach-exynos/mach-origen.c b/trunk/arch/arm/mach-exynos/mach-origen.c index 4e574c24581c..abd0e6059ab3 100644 --- a/trunk/arch/arm/mach-exynos/mach-origen.c +++ b/trunk/arch/arm/mach-exynos/mach-origen.c @@ -806,6 +806,7 @@ static void __init origen_machine_init(void) MACHINE_START(ORIGEN, "ORIGEN") /* Maintainer: JeongHyeon Kim */ .atag_offset = 0x100, + .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = origen_map_io, .handle_irq = gic_handle_irq, diff --git a/trunk/arch/arm/mach-exynos/mach-smdk4x12.c b/trunk/arch/arm/mach-exynos/mach-smdk4x12.c index b26beb13ebef..964693bdc242 100644 --- a/trunk/arch/arm/mach-exynos/mach-smdk4x12.c +++ b/trunk/arch/arm/mach-exynos/mach-smdk4x12.c @@ -370,6 +370,7 @@ static void __init smdk4x12_machine_init(void) MACHINE_START(SMDK4212, "SMDK4212") /* Maintainer: Kukjin Kim */ .atag_offset = 0x100, + .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = smdk4x12_map_io, .handle_irq = gic_handle_irq, @@ -383,6 +384,7 @@ MACHINE_START(SMDK4412, "SMDK4412") /* Maintainer: Kukjin Kim */ /* Maintainer: Changhwan Youn */ .atag_offset = 0x100, + .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = smdk4x12_map_io, .handle_irq = gic_handle_irq, diff --git a/trunk/arch/arm/mach-exynos/mach-smdkv310.c b/trunk/arch/arm/mach-exynos/mach-smdkv310.c index 73f2bce097e1..69b858ceefc5 100644 --- a/trunk/arch/arm/mach-exynos/mach-smdkv310.c +++ b/trunk/arch/arm/mach-exynos/mach-smdkv310.c @@ -417,6 +417,7 @@ MACHINE_START(SMDKV310, "SMDKV310") /* Maintainer: Kukjin Kim */ /* Maintainer: Changhwan Youn */ .atag_offset = 0x100, + .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = smdkv310_map_io, .handle_irq = gic_handle_irq, @@ -429,6 +430,7 @@ MACHINE_END MACHINE_START(SMDKC210, "SMDKC210") /* Maintainer: Kukjin Kim */ .atag_offset = 0x100, + .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = smdkv310_map_io, .handle_irq = gic_handle_irq, diff --git a/trunk/arch/arm/mach-exynos/mach-universal_c210.c b/trunk/arch/arm/mach-exynos/mach-universal_c210.c index 4d1f40d44ed1..922ca0f11795 100644 --- a/trunk/arch/arm/mach-exynos/mach-universal_c210.c +++ b/trunk/arch/arm/mach-exynos/mach-universal_c210.c @@ -1155,6 +1155,7 @@ static void __init universal_machine_init(void) MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") /* Maintainer: Kyungmin Park */ .atag_offset = 0x100, + .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = universal_map_io, .handle_irq = gic_handle_irq, diff --git a/trunk/arch/arm/mach-exynos/platsmp.c b/trunk/arch/arm/mach-exynos/platsmp.c index 36c3984aaa47..8d57e4223bdb 100644 --- a/trunk/arch/arm/mach-exynos/platsmp.c +++ b/trunk/arch/arm/mach-exynos/platsmp.c @@ -32,18 +32,13 @@ #include +#include "common.h" + extern void exynos4_secondary_startup(void); #define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ S5P_INFORM5 : S5P_VA_SYSRAM) -/* - * control for which core is the next to come out of the secondary - * boot "holding pen" - */ - -volatile int __cpuinitdata pen_release = -1; - /* * Write pen_release in a way that is guaranteed to be visible to all * observers, irrespective of whether they're taking part in coherency @@ -64,7 +59,7 @@ static void __iomem *scu_base_addr(void) static DEFINE_SPINLOCK(boot_lock); -void __cpuinit platform_secondary_init(unsigned int cpu) +static void __cpuinit exynos_secondary_init(unsigned int cpu) { /* * if any interrupts are already enabled for the primary @@ -86,7 +81,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) spin_unlock(&boot_lock); } -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; @@ -161,7 +156,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * which may be present or become present in the system. */ -void __init smp_init_cpus(void) +static void __init exynos_smp_init_cpus(void) { void __iomem *scu_base = scu_base_addr(); unsigned int i, ncores; @@ -184,7 +179,7 @@ void __init smp_init_cpus(void) set_smp_cross_call(gic_raise_softirq); } -void __init platform_smp_prepare_cpus(unsigned int max_cpus) +static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) { if (!soc_is_exynos5250()) scu_enable(scu_base_addr()); @@ -198,3 +193,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) __raw_writel(virt_to_phys(exynos4_secondary_startup), CPU1_BOOT_REG); } + +struct smp_operations exynos_smp_ops __initdata = { + .smp_init_cpus = exynos_smp_init_cpus, + .smp_prepare_cpus = exynos_smp_prepare_cpus, + .smp_secondary_init = exynos_secondary_init, + .smp_boot_secondary = exynos_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = exynos_cpu_die, +#endif +}; diff --git a/trunk/arch/arm/mach-footbridge/common.c b/trunk/arch/arm/mach-footbridge/common.c index 3e6aaa6361da..a42b369bc439 100644 --- a/trunk/arch/arm/mach-footbridge/common.c +++ b/trunk/arch/arm/mach-footbridge/common.c @@ -15,7 +15,7 @@ #include #include #include - + #include #include #include @@ -26,6 +26,7 @@ #include #include +#include #include "common.h" @@ -175,11 +176,6 @@ static struct map_desc ebsa285_host_io_desc[] __initdata = { .pfn = __phys_to_pfn(DC21285_PCI_IACK), .length = PCIIACK_SIZE, .type = MT_DEVICE, - }, { - .virtual = PCIO_BASE, - .pfn = __phys_to_pfn(DC21285_PCI_IO), - .length = PCIO_SIZE, - .type = MT_DEVICE, }, #endif }; @@ -196,8 +192,10 @@ void __init footbridge_map_io(void) * Now, work out what we've got to map in addition on this * platform. */ - if (footbridge_cfn_mode()) + if (footbridge_cfn_mode()) { iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc)); + pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO)); + } } void footbridge_restart(char mode, const char *cmd) diff --git a/trunk/arch/arm/mach-footbridge/dc21285.c b/trunk/arch/arm/mach-footbridge/dc21285.c index 9d62e3381024..a7cd2cf5e08d 100644 --- a/trunk/arch/arm/mach-footbridge/dc21285.c +++ b/trunk/arch/arm/mach-footbridge/dc21285.c @@ -276,8 +276,8 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys) sys->mem_offset = DC21285_PCI_MEM; - pci_add_resource_offset(&sys->resources, - &ioport_resource, sys->io_offset); + pci_ioremap_io(0, DC21285_PCI_IO); + pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset); pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); @@ -298,7 +298,7 @@ void __init dc21285_preinit(void) mem_size = (unsigned int)high_memory - PAGE_OFFSET; for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1) if (mem_mask >= mem_size) - break; + break; /* * These registers need to be set up whether we're the @@ -350,14 +350,6 @@ void __init dc21285_preinit(void) "PCI data parity", NULL); if (cfn_mode) { - static struct resource csrio; - - csrio.flags = IORESOURCE_IO; - csrio.name = "Footbridge"; - - allocate_resource(&ioport_resource, &csrio, 128, - 0xff00, 0xffff, 128, NULL, NULL); - /* * Map our SDRAM at a known address in PCI space, just in case * the firmware had other ideas. Using a nonzero base is @@ -365,7 +357,7 @@ void __init dc21285_preinit(void) * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards). */ *CSR_PCICSRBASE = 0xf4000000; - *CSR_PCICSRIOBASE = csrio.start; + *CSR_PCICSRIOBASE = 0; *CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET); *CSR_PCIROMBASE = 0; *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | diff --git a/trunk/arch/arm/mach-footbridge/include/mach/debug-macro.S b/trunk/arch/arm/mach-footbridge/include/mach/debug-macro.S index e5acde25ffc5..c169f0c99b2a 100644 --- a/trunk/arch/arm/mach-footbridge/include/mach/debug-macro.S +++ b/trunk/arch/arm/mach-footbridge/include/mach/debug-macro.S @@ -17,7 +17,8 @@ /* For NetWinder debugging */ .macro addruart, rp, rv, tmp mov \rp, #0x000003f8 - orr \rv, \rp, #0xff000000 @ virtual + orr \rv, \rp, #0xfe000000 @ virtual + orr \rv, \rv, #0x00e00000 @ virtual orr \rp, \rp, #0x7c000000 @ physical .endm diff --git a/trunk/arch/arm/mach-footbridge/include/mach/io.h b/trunk/arch/arm/mach-footbridge/include/mach/io.h index aba531eebbc6..aba46388cc0c 100644 --- a/trunk/arch/arm/mach-footbridge/include/mach/io.h +++ b/trunk/arch/arm/mach-footbridge/include/mach/io.h @@ -14,18 +14,10 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#ifdef CONFIG_MMU -#define MMU_IO(a, b) (a) -#else -#define MMU_IO(a, b) (b) -#endif - -#define PCIO_SIZE 0x00100000 -#define PCIO_BASE MMU_IO(0xff000000, 0x7c000000) - /* - * Translation of various region addresses to virtual addresses + * Translation of various i/o addresses to host addresses for !CONFIG_MMU */ +#define PCIO_BASE 0x7c000000 #define __io(a) ((void __iomem *)(PCIO_BASE + (a))) #endif diff --git a/trunk/arch/arm/mach-highbank/Kconfig b/trunk/arch/arm/mach-highbank/Kconfig new file mode 100644 index 000000000000..0e1d0a42a3ea --- /dev/null +++ b/trunk/arch/arm/mach-highbank/Kconfig @@ -0,0 +1,15 @@ +config ARCH_HIGHBANK + bool "Calxeda ECX-1000 (Highbank)" if ARCH_MULTI_V7 + select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_AMBA + select ARM_GIC + select ARM_TIMER_SP804 + select CACHE_L2X0 + select CLKDEV_LOOKUP + select COMMON_CLK + select CPU_V7 + select GENERIC_CLOCKEVENTS + select HAVE_ARM_SCU + select HAVE_SMP + select SPARSE_IRQ + select USE_OF diff --git a/trunk/arch/arm/mach-highbank/Makefile.boot b/trunk/arch/arm/mach-highbank/Makefile.boot deleted file mode 100644 index dae9661a7689..000000000000 --- a/trunk/arch/arm/mach-highbank/Makefile.boot +++ /dev/null @@ -1 +0,0 @@ -zreladdr-y := 0x00008000 diff --git a/trunk/arch/arm/mach-highbank/core.h b/trunk/arch/arm/mach-highbank/core.h index 141ed5171826..286ec82a4f63 100644 --- a/trunk/arch/arm/mach-highbank/core.h +++ b/trunk/arch/arm/mach-highbank/core.h @@ -8,4 +8,13 @@ extern void highbank_lluart_map_io(void); static inline void highbank_lluart_map_io(void) {} #endif +#ifdef CONFIG_PM_SLEEP +extern void highbank_pm_init(void); +#else +static inline void highbank_pm_init(void) {} +#endif + extern void highbank_smc1(int fn, int arg); +extern void highbank_cpu_die(unsigned int cpu); + +extern struct smp_operations highbank_smp_ops; diff --git a/trunk/arch/arm/mach-highbank/highbank.c b/trunk/arch/arm/mach-highbank/highbank.c index d75b0a78d88a..af1da34ccf9d 100644 --- a/trunk/arch/arm/mach-highbank/highbank.c +++ b/trunk/arch/arm/mach-highbank/highbank.c @@ -152,6 +152,7 @@ static void highbank_power_off(void) static void __init highbank_init(void) { pm_power_off = highbank_power_off; + highbank_pm_init(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } @@ -162,6 +163,7 @@ static const char *highbank_match[] __initconst = { }; DT_MACHINE_START(HIGHBANK, "Highbank") + .smp = smp_ops(highbank_smp_ops), .map_io = highbank_map_io, .init_irq = highbank_init_irq, .timer = &highbank_timer, diff --git a/trunk/arch/arm/mach-highbank/hotplug.c b/trunk/arch/arm/mach-highbank/hotplug.c index 977cebbea580..2c1b8c3c8e45 100644 --- a/trunk/arch/arm/mach-highbank/hotplug.c +++ b/trunk/arch/arm/mach-highbank/hotplug.c @@ -24,16 +24,11 @@ extern void secondary_startup(void); -int platform_cpu_kill(unsigned int cpu) -{ - return 1; -} - /* * platform-specific code to shutdown a CPU * */ -void platform_cpu_die(unsigned int cpu) +void __ref highbank_cpu_die(unsigned int cpu) { flush_cache_all(); @@ -45,12 +40,3 @@ void platform_cpu_die(unsigned int cpu) /* We should never return from idle */ panic("highbank: cpu %d unexpectedly exit from shutdown\n", cpu); } - -int platform_cpu_disable(unsigned int cpu) -{ - /* - * CPU0 should not be shut down via hotplug. cpu_idle can WFI - * or a proper shutdown or hibernate should be used. - */ - return cpu == 0 ? -EPERM : 0; -} diff --git a/trunk/arch/arm/mach-highbank/include/mach/gpio.h b/trunk/arch/arm/mach-highbank/include/mach/gpio.h deleted file mode 100644 index 40a8c178f10d..000000000000 --- a/trunk/arch/arm/mach-highbank/include/mach/gpio.h +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/trunk/arch/arm/mach-highbank/include/mach/timex.h b/trunk/arch/arm/mach-highbank/include/mach/timex.h deleted file mode 100644 index 88dac7a55a97..000000000000 --- a/trunk/arch/arm/mach-highbank/include/mach/timex.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __MACH_TIMEX_H -#define __MACH_TIMEX_H - -#define CLOCK_TICK_RATE 1000000 - -#endif diff --git a/trunk/arch/arm/mach-highbank/include/mach/uncompress.h b/trunk/arch/arm/mach-highbank/include/mach/uncompress.h deleted file mode 100644 index bbe20e696325..000000000000 --- a/trunk/arch/arm/mach-highbank/include/mach/uncompress.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __MACH_UNCOMPRESS_H -#define __MACH_UNCOMPRESS_H - -#define putc(c) -#define flush() -#define arch_decomp_setup() -#define arch_decomp_wdog() - -#endif diff --git a/trunk/arch/arm/mach-highbank/platsmp.c b/trunk/arch/arm/mach-highbank/platsmp.c index d01364c72b45..fa9560ec6e70 100644 --- a/trunk/arch/arm/mach-highbank/platsmp.c +++ b/trunk/arch/arm/mach-highbank/platsmp.c @@ -25,12 +25,12 @@ extern void secondary_startup(void); -void __cpuinit platform_secondary_init(unsigned int cpu) +static void __cpuinit highbank_secondary_init(unsigned int cpu) { gic_secondary_init(0); } -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle) { gic_raise_softirq(cpumask_of(cpu), 0); return 0; @@ -40,7 +40,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * Initialise the CPU possible map early - this describes the CPUs * which may be present or become present in the system. */ -void __init smp_init_cpus(void) +static void __init highbank_smp_init_cpus(void) { unsigned int i, ncores; @@ -61,7 +61,7 @@ void __init smp_init_cpus(void) set_smp_cross_call(gic_raise_softirq); } -void __init platform_smp_prepare_cpus(unsigned int max_cpus) +static void __init highbank_smp_prepare_cpus(unsigned int max_cpus) { int i; @@ -76,3 +76,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) for (i = 1; i < max_cpus; i++) highbank_set_cpu_jump(i, secondary_startup); } + +struct smp_operations highbank_smp_ops __initdata = { + .smp_init_cpus = highbank_smp_init_cpus, + .smp_prepare_cpus = highbank_smp_prepare_cpus, + .smp_secondary_init = highbank_secondary_init, + .smp_boot_secondary = highbank_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = highbank_cpu_die, +#endif +}; diff --git a/trunk/arch/arm/mach-highbank/pm.c b/trunk/arch/arm/mach-highbank/pm.c index 33b3beb89982..de866f21331f 100644 --- a/trunk/arch/arm/mach-highbank/pm.c +++ b/trunk/arch/arm/mach-highbank/pm.c @@ -47,9 +47,7 @@ static const struct platform_suspend_ops highbank_pm_ops = { .valid = suspend_valid_only_mem, }; -static int __init highbank_pm_init(void) +void __init highbank_pm_init(void) { suspend_set_ops(&highbank_pm_ops); - return 0; } -module_init(highbank_pm_init); diff --git a/trunk/arch/arm/mach-imx/Kconfig b/trunk/arch/arm/mach-imx/Kconfig index afd542ad6f97..7ca5fe45945f 100644 --- a/trunk/arch/arm/mach-imx/Kconfig +++ b/trunk/arch/arm/mach-imx/Kconfig @@ -101,13 +101,8 @@ config SOC_IMX51 select SOC_IMX5 select ARCH_MX5 select ARCH_MX51 - -config SOC_IMX53 - bool - select SOC_IMX5 - select ARCH_MX5 - select ARCH_MX53 - select HAVE_CAN_FLEXCAN if CAN + select PINCTRL + select PINCTRL_IMX51 if ARCH_IMX_V4_V5 @@ -561,7 +556,6 @@ config MACH_BUG config MACH_IMX31_DT bool "Support i.MX31 platforms from device tree" select SOC_IMX31 - select USE_OF help Include support for Freescale i.MX31 based platforms using the device tree for discovery. @@ -737,95 +731,19 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD endchoice -config MX51_EFIKA_COMMON - bool - select SOC_IMX51 - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_PATA_IMX - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_ULPI if USB_ULPI - -config MACH_MX51_EFIKAMX - bool "Support MX51 Genesi Efika MX nettop" - select LEDS_GPIO_REGISTER - select MX51_EFIKA_COMMON - help - Include support for Genesi Efika MX nettop. This includes specific - configurations for the board and its peripherals. - -config MACH_MX51_EFIKASB - bool "Support MX51 Genesi Efika Smartbook" - select LEDS_GPIO_REGISTER - select MX51_EFIKA_COMMON - help - Include support for Genesi Efika Smartbook. This includes specific - configurations for the board and its peripherals. - -comment "i.MX53 machines:" - -config MACH_IMX53_DT - bool "Support i.MX53 platforms from device tree" - select SOC_IMX53 - select MACH_MX53_ARD - select MACH_MX53_EVK - select MACH_MX53_LOCO - select MACH_MX53_SMD - help - Include support for Freescale i.MX53 based platforms - using the device tree for discovery - -config MACH_MX53_EVK - bool "Support MX53 EVK platforms" - select SOC_IMX53 - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_SPI_IMX - select LEDS_GPIO_REGISTER - help - Include support for MX53 EVK platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX53_SMD - bool "Support MX53 SMD platforms" - select SOC_IMX53 - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - help - Include support for MX53 SMD platform. This includes specific - configurations for the board and its peripherals. +comment "Device tree only" -config MACH_MX53_LOCO - bool "Support MX53 LOCO platforms" - select SOC_IMX53 - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_GPIO_KEYS - select LEDS_GPIO_REGISTER - help - Include support for MX53 LOCO platform. This includes specific - configurations for the board and its peripherals. +config SOC_IMX53 + bool "i.MX53 support" + select SOC_IMX5 + select ARCH_MX5 + select ARCH_MX53 + select HAVE_CAN_FLEXCAN if CAN + select PINCTRL + select PINCTRL_IMX53 -config MACH_MX53_ARD - bool "Support MX53 ARD platforms" - select SOC_IMX53 - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_GPIO_KEYS help - Include support for MX53 ARD platform. This includes specific - configurations for the board and its peripherals. - -comment "i.MX6 family:" + This enables support for Freescale i.MX53 processor. config SOC_IMX6Q bool "i.MX6 Quad support" diff --git a/trunk/arch/arm/mach-imx/Makefile b/trunk/arch/arm/mach-imx/Makefile index d004d37ad9d8..895754aeb4f3 100644 --- a/trunk/arch/arm/mach-imx/Makefile +++ b/trunk/arch/arm/mach-imx/Makefile @@ -13,7 +13,7 @@ imx5-pm-$(CONFIG_PM) += pm-imx5.o obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ - clk-pfd.o clk-busy.o + clk-pfd.o clk-busy.o clk.o # Support for CMOS sensor interface obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o @@ -83,16 +83,9 @@ endif # i.MX5 based machines obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o -obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o -obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o -obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o -obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o -obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o -obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o -obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o -obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o +obj-$(CONFIG_SOC_IMX53) += mach-imx53.o diff --git a/trunk/arch/arm/mach-imx/Makefile.boot b/trunk/arch/arm/mach-imx/Makefile.boot index 05541cf4a878..b27815de8473 100644 --- a/trunk/arch/arm/mach-imx/Makefile.boot +++ b/trunk/arch/arm/mach-imx/Makefile.boot @@ -37,10 +37,3 @@ initrd_phys-$(CONFIG_SOC_IMX53) := 0x70800000 zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000 params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100 initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000 - -dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb -dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \ - imx53-qsb.dtb imx53-smd.dtb -dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \ - imx6q-sabrelite.dtb \ - imx6q-sabresd.dtb \ diff --git a/trunk/arch/arm/mach-imx/clk-imx21.c b/trunk/arch/arm/mach-imx/clk-imx21.c index ea13e61bd5f3..cf65148bc519 100644 --- a/trunk/arch/arm/mach-imx/clk-imx21.c +++ b/trunk/arch/arm/mach-imx/clk-imx21.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include diff --git a/trunk/arch/arm/mach-imx/clk-imx35.c b/trunk/arch/arm/mach-imx/clk-imx35.c index 65fb8bcd86cb..177259b523cd 100644 --- a/trunk/arch/arm/mach-imx/clk-imx35.c +++ b/trunk/arch/arm/mach-imx/clk-imx35.c @@ -62,8 +62,8 @@ enum mx35_clks { kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate, rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate, ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate, - wdog_gate, max_gate, admux_gate, csi_gate, iim_gate, gpu2d_gate, - clk_max + wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate, + gpu2d_gate, clk_max }; static struct clk *clk[clk_max]; @@ -142,6 +142,9 @@ int __init mx35_clocks_init() clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4); + clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel)); + clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6); + clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0); clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2); clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4); @@ -192,7 +195,7 @@ int __init mx35_clocks_init() clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26); clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30); - clk[csi_gate] = imx_clk_gate2("csi_gate", "ipg", base + MX35_CCM_CGR3, 0); + clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0); clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4); @@ -228,6 +231,7 @@ int __init mx35_clocks_init() clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2"); clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); + clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad"); clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1"); clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); @@ -253,6 +257,7 @@ int __init mx35_clocks_init() clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc"); clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0"); + clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); clk_prepare_enable(clk[spba_gate]); clk_prepare_enable(clk[gpio1_gate]); diff --git a/trunk/arch/arm/mach-imx/clk-imx51-imx53.c b/trunk/arch/arm/mach-imx/clk-imx51-imx53.c index 4bdcaa97bd98..e5165a84f93f 100644 --- a/trunk/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/trunk/arch/arm/mach-imx/clk-imx51-imx53.c @@ -39,16 +39,17 @@ static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", }; static const char *emi_slow_sel[] = { "main_bus", "ahb", }; static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", }; static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", }; -static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0", }; +static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", }; static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", }; static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", }; -static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1", }; +static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", }; static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", }; static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", }; static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", }; static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", }; static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; +static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", }; enum imx5_clks { dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred, @@ -82,6 +83,7 @@ enum imx5_clks { ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate, ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate, epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate, + can_sel, can1_serial_gate, can1_ipg_gate, clk_max }; @@ -421,8 +423,12 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); - clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "ipg", MXC_CCM_CCGR4, 6); - clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 8); + clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2, + mx53_can_sel, ARRAY_SIZE(mx53_can_sel)); + clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); + clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); + clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); + clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); for (i = 0; i < ARRAY_SIZE(clk); i++) @@ -455,6 +461,10 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi"); clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi"); clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi"); + clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can"); + clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can"); + clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can"); + clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can"); /* set SDHC root clock to 200MHZ*/ clk_set_rate(clk[esdhc_a_podf], 200000000); diff --git a/trunk/arch/arm/mach-imx/clk-imx6q.c b/trunk/arch/arm/mach-imx/clk-imx6q.c index 4233d9e3531d..3ec242f3341e 100644 --- a/trunk/arch/arm/mach-imx/clk-imx6q.c +++ b/trunk/arch/arm/mach-imx/clk-imx6q.c @@ -157,6 +157,7 @@ enum mx6q_clks { }; static struct clk *clk[clk_max]; +static struct clk_onecell_data clk_data; static enum mx6q_clks const clks_init_on[] __initconst = { mmdc_ch0_axi, rom, @@ -394,52 +395,24 @@ int __init mx6q_clocks_init(void) pr_err("i.MX6q clk %d: register failed with %ld\n", i, PTR_ERR(clk[i])); + clk_data.clks = clk; + clk_data.clk_num = ARRAY_SIZE(clk); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); clk_register_clkdev(clk[twd], NULL, "smp_twd"); - clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh"); - clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand"); - clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand"); - clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand"); - clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand"); - clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand"); - clk_register_clkdev(clk[usboh3], NULL, "2184000.usb"); - clk_register_clkdev(clk[usboh3], NULL, "2184200.usb"); - clk_register_clkdev(clk[usboh3], NULL, "2184400.usb"); - clk_register_clkdev(clk[usboh3], NULL, "2184600.usb"); - clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy"); - clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy"); - clk_register_clkdev(clk[uart_serial], "per", "2020000.serial"); - clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial"); - clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial"); - clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial"); - clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial"); - clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial"); - clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial"); - clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial"); - clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial"); - clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial"); - clk_register_clkdev(clk[enet], NULL, "2188000.ethernet"); - clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc"); - clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc"); - clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc"); - clk_register_clkdev(clk[usdhc4], NULL, "219c000.usdhc"); - clk_register_clkdev(clk[i2c1], NULL, "21a0000.i2c"); - clk_register_clkdev(clk[i2c2], NULL, "21a4000.i2c"); - clk_register_clkdev(clk[i2c3], NULL, "21a8000.i2c"); - clk_register_clkdev(clk[ecspi1], NULL, "2008000.ecspi"); - clk_register_clkdev(clk[ecspi2], NULL, "200c000.ecspi"); - clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi"); - clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi"); - clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi"); - clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma"); - clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog"); - clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog"); - clk_register_clkdev(clk[ssi1_ipg], NULL, "2028000.ssi"); clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); clk_register_clkdev(clk[ahb], "ahb", NULL); clk_register_clkdev(clk[cko1], "cko1", NULL); + /* + * The gpmi needs 100MHz frequency in the EDO/Sync mode, + * We can not get the 100MHz from the pll2_pfd0_352m. + * So choose pll2_pfd2_396m as enfc_sel's parent. + */ + clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]); + for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clk[clks_init_on[i]]); diff --git a/trunk/arch/arm/mach-imx/clk-pllv1.c b/trunk/arch/arm/mach-imx/clk-pllv1.c index 2d856f9ccf59..02be73178912 100644 --- a/trunk/arch/arm/mach-imx/clk-pllv1.c +++ b/trunk/arch/arm/mach-imx/clk-pllv1.c @@ -6,7 +6,7 @@ #include #include #include -#include + #include "clk.h" /** @@ -29,8 +29,53 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_pllv1 *pll = to_clk_pllv1(hw); + long long ll; + int mfn_abs; + unsigned int mfi, mfn, mfd, pd; + u32 reg; + unsigned long rate; + + reg = readl(pll->base); + + /* + * Get the resulting clock rate from a PLL register value and the input + * frequency. PLLs with this register layout can be found on i.MX1, + * i.MX21, i.MX27 and i,MX31 + * + * mfi + mfn / (mfd + 1) + * f = 2 * f_ref * -------------------- + * pd + 1 + */ + + mfi = (reg >> 10) & 0xf; + mfn = reg & 0x3ff; + mfd = (reg >> 16) & 0x3ff; + pd = (reg >> 26) & 0xf; + + mfi = mfi <= 5 ? 5 : mfi; + + mfn_abs = mfn; + + /* + * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit + * 2's complements number + */ + if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) + mfn_abs = 0x400 - mfn; + + rate = parent_rate * 2; + rate /= pd + 1; + + ll = (unsigned long long)rate * mfn_abs; + + do_div(ll, mfd + 1); + + if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) + ll = -ll; + + ll = (rate * mfi) + ll; - return mxc_decode_pll(readl(pll->base), parent_rate); + return ll; } struct clk_ops clk_pllv1_ops = { diff --git a/trunk/arch/arm/mach-imx/clk.c b/trunk/arch/arm/mach-imx/clk.c new file mode 100644 index 000000000000..f5e8be8e7f11 --- /dev/null +++ b/trunk/arch/arm/mach-imx/clk.c @@ -0,0 +1,3 @@ +#include + +DEFINE_SPINLOCK(imx_ccm_lock); diff --git a/trunk/arch/arm/mach-imx/clk.h b/trunk/arch/arm/mach-imx/clk.h index 1bf64fe2523c..5f2d8acca25f 100644 --- a/trunk/arch/arm/mach-imx/clk.h +++ b/trunk/arch/arm/mach-imx/clk.h @@ -3,7 +3,8 @@ #include #include -#include + +extern spinlock_t imx_ccm_lock; struct clk *imx_clk_pllv1(const char *name, const char *parent, void __iomem *base); diff --git a/trunk/arch/arm/mach-imx/devices-imx53.h b/trunk/arch/arm/mach-imx/devices-imx53.h deleted file mode 100644 index 77e0db96c448..000000000000 --- a/trunk/arch/arm/mach-imx/devices-imx53.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2010 Yong Shen. - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include - -extern const struct imx_fec_data imx53_fec_data; -#define imx53_add_fec(pdata) \ - imx_add_fec(&imx53_fec_data, pdata) - -extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[]; -#define imx53_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata) - - -extern const struct imx_imx_i2c_data imx53_imx_i2c_data[]; -#define imx53_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata) - -extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[]; -#define imx53_add_sdhci_esdhc_imx(id, pdata) \ - imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata) - -extern const struct imx_spi_imx_data imx53_ecspi_data[]; -#define imx53_add_ecspi(id, pdata) \ - imx_add_spi_imx(&imx53_ecspi_data[id], pdata) - -extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[]; -#define imx53_add_imx2_wdt(id) \ - imx_add_imx2_wdt(&imx53_imx2_wdt_data[id]) - -extern const struct imx_imx_ssi_data imx53_imx_ssi_data[]; -#define imx53_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata) - -extern const struct imx_imx_keypad_data imx53_imx_keypad_data; -#define imx53_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx53_imx_keypad_data, pdata) - -extern const struct imx_pata_imx_data imx53_pata_imx_data; -#define imx53_add_pata_imx() \ - imx_add_pata_imx(&imx53_pata_imx_data) - -extern struct platform_device *__init imx53_add_ahci_imx(void); diff --git a/trunk/arch/arm/mach-imx/efika.h b/trunk/arch/arm/mach-imx/efika.h deleted file mode 100644 index 014aa985faae..000000000000 --- a/trunk/arch/arm/mach-imx/efika.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _EFIKA_H -#define _EFIKA_H - -#define EFIKA_WLAN_EN IMX_GPIO_NR(2, 16) -#define EFIKA_WLAN_RESET IMX_GPIO_NR(2, 10) -#define EFIKA_USB_PHY_RESET IMX_GPIO_NR(2, 9) - -void __init efika_board_common_init(void); - -#endif diff --git a/trunk/arch/arm/mach-imx/hotplug.c b/trunk/arch/arm/mach-imx/hotplug.c index f8f7437c83b8..b07b778dc9a8 100644 --- a/trunk/arch/arm/mach-imx/hotplug.c +++ b/trunk/arch/arm/mach-imx/hotplug.c @@ -15,11 +15,6 @@ #include #include -int platform_cpu_kill(unsigned int cpu) -{ - return 1; -} - static inline void cpu_enter_lowpower(void) { unsigned int v; @@ -47,7 +42,7 @@ static inline void cpu_enter_lowpower(void) * * Called with IRQs disabled */ -void platform_cpu_die(unsigned int cpu) +void imx_cpu_die(unsigned int cpu) { cpu_enter_lowpower(); imx_enable_cpu(cpu, false); @@ -56,12 +51,3 @@ void platform_cpu_die(unsigned int cpu) while (1) ; } - -int platform_cpu_disable(unsigned int cpu) -{ - /* - * we don't allow CPU 0 to be shutdown (it is still too special - * e.g. clock tick interrupts) - */ - return cpu == 0 ? -EPERM : 0; -} diff --git a/trunk/arch/arm/mach-imx/imx51-dt.c b/trunk/arch/arm/mach-imx/imx51-dt.c index d4067fe36357..f233b4bb2342 100644 --- a/trunk/arch/arm/mach-imx/imx51-dt.c +++ b/trunk/arch/arm/mach-imx/imx51-dt.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -44,27 +43,8 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = { { /* sentinel */ } }; -static const struct of_device_id imx51_iomuxc_of_match[] __initconst = { - { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, }, - { /* sentinel */ } -}; - static void __init imx51_dt_init(void) { - struct device_node *node; - const struct of_device_id *of_id; - void (*func)(void); - - pinctrl_provide_dummies(); - - node = of_find_matching_node(NULL, imx51_iomuxc_of_match); - if (node) { - of_id = of_match_node(imx51_iomuxc_of_match, node); - func = of_id->data; - func(); - of_node_put(node); - } - of_platform_populate(NULL, of_default_bus_match_table, imx51_auxdata_lookup, NULL); } @@ -79,7 +59,6 @@ static struct sys_timer imx51_timer = { }; static const char *imx51_dt_board_compat[] __initdata = { - "fsl,imx51-babbage", "fsl,imx51", NULL }; diff --git a/trunk/arch/arm/mach-imx/imx53-dt.c b/trunk/arch/arm/mach-imx/mach-imx53.c similarity index 81% rename from trunk/arch/arm/mach-imx/imx53-dt.c rename to trunk/arch/arm/mach-imx/mach-imx53.c index 1b7a2fc36591..29711e95579f 100644 --- a/trunk/arch/arm/mach-imx/imx53-dt.c +++ b/trunk/arch/arm/mach-imx/mach-imx53.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -51,14 +50,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = { { /* sentinel */ } }; -static const struct of_device_id imx53_iomuxc_of_match[] __initconst = { - { .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, }, - { .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, }, - { .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, }, - { .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, }, - { /* sentinel */ } -}; - static void __init imx53_qsb_init(void) { struct clk *clk; @@ -74,20 +65,6 @@ static void __init imx53_qsb_init(void) static void __init imx53_dt_init(void) { - struct device_node *node; - const struct of_device_id *of_id; - void (*func)(void); - - pinctrl_provide_dummies(); - - node = of_find_matching_node(NULL, imx53_iomuxc_of_match); - if (node) { - of_id = of_match_node(imx53_iomuxc_of_match, node); - func = of_id->data; - func(); - of_node_put(node); - } - if (of_machine_is_compatible("fsl,imx53-qsb")) imx53_qsb_init(); @@ -105,10 +82,6 @@ static struct sys_timer imx53_timer = { }; static const char *imx53_dt_board_compat[] __initdata = { - "fsl,imx53-ard", - "fsl,imx53-evk", - "fsl,imx53-qsb", - "fsl,imx53-smd", "fsl,imx53", NULL }; diff --git a/trunk/arch/arm/mach-imx/mach-imx6q.c b/trunk/arch/arm/mach-imx/mach-imx6q.c index 045b3f6a387d..36979d3dfe34 100644 --- a/trunk/arch/arm/mach-imx/mach-imx6q.c +++ b/trunk/arch/arm/mach-imx/mach-imx6q.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -100,7 +99,6 @@ static void __init imx6q_sabrelite_cko1_setup(void) clk_set_parent(cko1_sel, ahb); rate = clk_round_rate(cko1, 16000000); clk_set_rate(cko1, rate); - clk_register_clkdev(cko1, NULL, "0-000a"); put_clk: if (!IS_ERR(cko1_sel)) clk_put(cko1_sel); @@ -159,12 +157,6 @@ static void __init imx6q_usb_init(void) static void __init imx6q_init_machine(void) { - /* - * This should be removed when all imx6q boards have pinctrl - * states for devices defined in device tree. - */ - pinctrl_provide_dummies(); - if (of_machine_is_compatible("fsl,imx6q-sabrelite")) imx6q_sabrelite_init(); @@ -218,14 +210,12 @@ static struct sys_timer imx6q_timer = { }; static const char *imx6q_dt_compat[] __initdata = { - "fsl,imx6q-arm2", - "fsl,imx6q-sabrelite", - "fsl,imx6q-sabresd", "fsl,imx6q", NULL, }; DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)") + .smp = smp_ops(imx_smp_ops), .map_io = imx6q_map_io, .init_irq = imx6q_init_irq, .handle_irq = imx6q_handle_irq, diff --git a/trunk/arch/arm/mach-imx/mach-kzm_arm11_01.c b/trunk/arch/arm/mach-imx/mach-kzm_arm11_01.c index 5d08533ab2c7..0330078ff788 100644 --- a/trunk/arch/arm/mach-imx/mach-kzm_arm11_01.c +++ b/trunk/arch/arm/mach-imx/mach-kzm_arm11_01.c @@ -36,7 +36,6 @@ #include #include -#include #include #include #include @@ -259,13 +258,13 @@ static void __init kzm_board_init(void) */ static struct map_desc kzm_io_desc[] __initdata = { { - .virtual = MX31_CS4_BASE_ADDR_VIRT, + .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), .length = MX31_CS4_SIZE, .type = MT_DEVICE }, { - .virtual = MX31_CS5_BASE_ADDR_VIRT, + .virtual = (unsigned long)MX31_CS5_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR), .length = MX31_CS5_SIZE, .type = MT_DEVICE diff --git a/trunk/arch/arm/mach-imx/mach-mx31ads.c b/trunk/arch/arm/mach-imx/mach-mx31ads.c index d37f4809c556..e774b07f48d3 100644 --- a/trunk/arch/arm/mach-imx/mach-mx31ads.c +++ b/trunk/arch/arm/mach-imx/mach-mx31ads.c @@ -540,7 +540,7 @@ static void __init mxc_init_audio(void) */ static struct map_desc mx31ads_io_desc[] __initdata = { { - .virtual = MX31_CS4_BASE_ADDR_VIRT, + .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), .length = CS4_CS8900_MMIO_START, .type = MT_DEVICE diff --git a/trunk/arch/arm/mach-imx/mach-mx31lite.c b/trunk/arch/arm/mach-imx/mach-mx31lite.c index c8785b39eaed..ef57cff5abfb 100644 --- a/trunk/arch/arm/mach-imx/mach-mx31lite.c +++ b/trunk/arch/arm/mach-imx/mach-mx31lite.c @@ -207,7 +207,7 @@ static struct platform_device physmap_flash_device = { */ static struct map_desc mx31lite_io_desc[] __initdata = { { - .virtual = MX31_CS4_BASE_ADDR_VIRT, + .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), .length = MX31_CS4_SIZE, .type = MT_DEVICE diff --git a/trunk/arch/arm/mach-imx/mach-mx51_efikamx.c b/trunk/arch/arm/mach-imx/mach-mx51_efikamx.c deleted file mode 100644 index 8d09c0126cab..000000000000 --- a/trunk/arch/arm/mach-imx/mach-mx51_efikamx.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - * Copyright (C) 2010 Linaro Limited - * - * based on code from the following - * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. - * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "devices-imx51.h" -#include "efika.h" - -#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16) -#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17) -#define EFIKAMX_PCBID2 IMX_GPIO_NR(3, 11) - -#define EFIKAMX_BLUE_LED IMX_GPIO_NR(3, 13) -#define EFIKAMX_GREEN_LED IMX_GPIO_NR(3, 14) -#define EFIKAMX_RED_LED IMX_GPIO_NR(3, 15) - -#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31) - -/* board 1.1 doesn't have same reset gpio */ -#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2) -#define EFIKAMX_RESET IMX_GPIO_NR(1, 4) - -#define EFIKAMX_POWEROFF IMX_GPIO_NR(4, 13) - -#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6) - -/* the pci ids pin have pull up. they're driven low according to board id */ -#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) -#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) -#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) -#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) - -static iomux_v3_cfg_t mx51efikamx_pads[] = { - /* board id */ - MX51_PAD_PCBID0, - MX51_PAD_PCBID1, - MX51_PAD_PCBID2, - - /* leds */ - MX51_PAD_CSI1_D9__GPIO3_13, - MX51_PAD_CSI1_VSYNC__GPIO3_14, - MX51_PAD_CSI1_HSYNC__GPIO3_15, - - /* power key */ - MX51_PAD_PWRKEY, - - /* reset */ - MX51_PAD_DI1_PIN13__GPIO3_2, - MX51_PAD_GPIO1_4__GPIO1_4, - - /* power off */ - MX51_PAD_CSI2_VSYNC__GPIO4_13, -}; - -/* PCBID2 PCBID1 PCBID0 STATE - 1 1 1 ER1:rev1.1 - 1 1 0 ER2:rev1.2 - 1 0 1 ER3:rev1.3 - 1 0 0 ER4:rev1.4 -*/ -static void __init mx51_efikamx_board_id(void) -{ - int id; - - /* things are taking time to settle */ - msleep(150); - - gpio_request(EFIKAMX_PCBID0, "pcbid0"); - gpio_direction_input(EFIKAMX_PCBID0); - gpio_request(EFIKAMX_PCBID1, "pcbid1"); - gpio_direction_input(EFIKAMX_PCBID1); - gpio_request(EFIKAMX_PCBID2, "pcbid2"); - gpio_direction_input(EFIKAMX_PCBID2); - - id = gpio_get_value(EFIKAMX_PCBID0) ? 1 : 0; - id |= (gpio_get_value(EFIKAMX_PCBID1) ? 1 : 0) << 1; - id |= (gpio_get_value(EFIKAMX_PCBID2) ? 1 : 0) << 2; - - switch (id) { - case 7: - system_rev = 0x11; - break; - case 6: - system_rev = 0x12; - break; - case 5: - system_rev = 0x13; - break; - case 4: - system_rev = 0x14; - break; - default: - system_rev = 0x10; - break; - } - - if ((system_rev == 0x10) - || (system_rev == 0x12) - || (system_rev == 0x14)) { - printk(KERN_WARNING - "EfikaMX: Unsupported board revision 1.%u!\n", - system_rev & 0xf); - } -} - -static struct gpio_led mx51_efikamx_leds[] __initdata = { - { - .name = "efikamx:green", - .default_trigger = "default-on", - .gpio = EFIKAMX_GREEN_LED, - }, - { - .name = "efikamx:red", - .default_trigger = "ide-disk", - .gpio = EFIKAMX_RED_LED, - }, - { - .name = "efikamx:blue", - .default_trigger = "mmc0", - .gpio = EFIKAMX_BLUE_LED, - }, -}; - -static const struct gpio_led_platform_data - mx51_efikamx_leds_data __initconst = { - .leds = mx51_efikamx_leds, - .num_leds = ARRAY_SIZE(mx51_efikamx_leds), -}; - -static struct esdhc_platform_data sd_pdata = { - .cd_type = ESDHC_CD_CONTROLLER, - .wp_type = ESDHC_WP_CONTROLLER, -}; - -static struct gpio_keys_button mx51_efikamx_powerkey[] = { - { - .code = KEY_POWER, - .gpio = EFIKAMX_POWER_KEY, - .type = EV_PWR, - .desc = "Power Button (CM)", - .wakeup = 1, - .debounce_interval = 10, /* ms */ - }, -}; - -static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = { - .buttons = mx51_efikamx_powerkey, - .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey), -}; - -static void mx51_efikamx_restart(char mode, const char *cmd) -{ - if (system_rev == 0x11) - gpio_direction_output(EFIKAMX_RESET1_1, 0); - else - gpio_direction_output(EFIKAMX_RESET, 0); -} - -static struct regulator *pwgt1, *pwgt2, *coincell; - -static void mx51_efikamx_power_off(void) -{ - if (!IS_ERR(coincell)) - regulator_disable(coincell); - - if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { - regulator_disable(pwgt2); - regulator_disable(pwgt1); - } - gpio_direction_output(EFIKAMX_POWEROFF, 1); -} - -static int __init mx51_efikamx_power_init(void) -{ - pwgt1 = regulator_get(NULL, "pwgt1"); - pwgt2 = regulator_get(NULL, "pwgt2"); - if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { - regulator_enable(pwgt1); - regulator_enable(pwgt2); - } - gpio_request(EFIKAMX_POWEROFF, "poweroff"); - pm_power_off = mx51_efikamx_power_off; - - /* enable coincell charger. maybe need a small power driver ? */ - coincell = regulator_get(NULL, "coincell"); - if (!IS_ERR(coincell)) { - regulator_set_voltage(coincell, 3000000, 3000000); - regulator_enable(coincell); - } - - regulator_has_full_constraints(); - - return 0; -} - -static void __init mx51_efikamx_init_late(void) -{ - imx51_init_late(); - mx51_efikamx_power_init(); -} - -static void __init mx51_efikamx_init(void) -{ - imx51_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads, - ARRAY_SIZE(mx51efikamx_pads)); - efika_board_common_init(); - - mx51_efikamx_board_id(); - - /* on < 1.2 boards both SD controllers are used */ - if (system_rev < 0x12) { - imx51_add_sdhci_esdhc_imx(0, NULL); - imx51_add_sdhci_esdhc_imx(1, &sd_pdata); - mx51_efikamx_leds[2].default_trigger = "mmc1"; - } else - imx51_add_sdhci_esdhc_imx(0, &sd_pdata); - - gpio_led_register_device(-1, &mx51_efikamx_leds_data); - imx_add_gpio_keys(&mx51_efikamx_powerkey_data); - - if (system_rev == 0x11) { - gpio_request(EFIKAMX_RESET1_1, "reset"); - gpio_direction_output(EFIKAMX_RESET1_1, 1); - } else { - gpio_request(EFIKAMX_RESET, "reset"); - gpio_direction_output(EFIKAMX_RESET, 1); - } - - /* - * enable wifi by default only on mx - * sb and mx have same wlan pin but the value to enable it are - * different :/ - */ - gpio_request(EFIKA_WLAN_EN, "wlan_en"); - gpio_direction_output(EFIKA_WLAN_EN, 0); - msleep(10); - - gpio_request(EFIKA_WLAN_RESET, "wlan_rst"); - gpio_direction_output(EFIKA_WLAN_RESET, 0); - msleep(10); - gpio_set_value(EFIKA_WLAN_RESET, 1); -} - -static void __init mx51_efikamx_timer_init(void) -{ - mx51_clocks_init(32768, 24000000, 22579200, 24576000); -} - -static struct sys_timer mx51_efikamx_timer = { - .init = mx51_efikamx_timer_init, -}; - -MACHINE_START(MX51_EFIKAMX, "Genesi Efika MX (Smarttop)") - .atag_offset = 0x100, - .map_io = mx51_map_io, - .init_early = imx51_init_early, - .init_irq = mx51_init_irq, - .handle_irq = imx51_handle_irq, - .timer = &mx51_efikamx_timer, - .init_machine = mx51_efikamx_init, - .init_late = mx51_efikamx_init_late, - .restart = mx51_efikamx_restart, -MACHINE_END diff --git a/trunk/arch/arm/mach-imx/mach-mx51_efikasb.c b/trunk/arch/arm/mach-imx/mach-mx51_efikasb.c deleted file mode 100644 index fdbd181b97ef..000000000000 --- a/trunk/arch/arm/mach-imx/mach-mx51_efikasb.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * Copyright (C) Arnaud Patard - * - * based on code from the following - * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. - * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "devices-imx51.h" -#include "efika.h" - -#define EFIKASB_USBH2_STP IMX_GPIO_NR(2, 20) -#define EFIKASB_GREEN_LED IMX_GPIO_NR(1, 3) -#define EFIKASB_WHITE_LED IMX_GPIO_NR(2, 25) -#define EFIKASB_PCBID0 IMX_GPIO_NR(2, 28) -#define EFIKASB_PCBID1 IMX_GPIO_NR(2, 29) -#define EFIKASB_PWRKEY IMX_GPIO_NR(2, 31) -#define EFIKASB_LID IMX_GPIO_NR(3, 14) -#define EFIKASB_POWEROFF IMX_GPIO_NR(4, 13) -#define EFIKASB_RFKILL IMX_GPIO_NR(3, 1) - -#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) -#define MX51_PAD_SD1_CD IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL) - -static iomux_v3_cfg_t mx51efikasb_pads[] = { - /* USB HOST2 */ - MX51_PAD_EIM_D16__USBH2_DATA0, - MX51_PAD_EIM_D17__USBH2_DATA1, - MX51_PAD_EIM_D18__USBH2_DATA2, - MX51_PAD_EIM_D19__USBH2_DATA3, - MX51_PAD_EIM_D20__USBH2_DATA4, - MX51_PAD_EIM_D21__USBH2_DATA5, - MX51_PAD_EIM_D22__USBH2_DATA6, - MX51_PAD_EIM_D23__USBH2_DATA7, - MX51_PAD_EIM_A24__USBH2_CLK, - MX51_PAD_EIM_A25__USBH2_DIR, - MX51_PAD_EIM_A26__USBH2_STP, - MX51_PAD_EIM_A27__USBH2_NXT, - - /* leds */ - MX51_PAD_EIM_CS0__GPIO2_25, - MX51_PAD_GPIO1_3__GPIO1_3, - - /* pcb id */ - MX51_PAD_EIM_CS3__GPIO2_28, - MX51_PAD_EIM_CS4__GPIO2_29, - - /* lid */ - MX51_PAD_CSI1_VSYNC__GPIO3_14, - - /* power key*/ - MX51_PAD_PWRKEY, - - /* wifi/bt button */ - MX51_PAD_DI1_PIN12__GPIO3_1, - - /* power off */ - MX51_PAD_CSI2_VSYNC__GPIO4_13, - - /* wdog reset */ - MX51_PAD_GPIO1_4__WDOG1_WDOG_B, - - /* BT */ - MX51_PAD_EIM_A17__GPIO2_11, - - MX51_PAD_SD1_CD, -}; - -static int initialize_usbh2_port(struct platform_device *pdev) -{ - iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP; - iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20; - - mxc_iomux_v3_setup_pad(usbh2gpio); - gpio_request(EFIKASB_USBH2_STP, "usbh2_stp"); - gpio_direction_output(EFIKASB_USBH2_STP, 0); - msleep(1); - gpio_set_value(EFIKASB_USBH2_STP, 1); - msleep(1); - - gpio_free(EFIKASB_USBH2_STP); - mxc_iomux_v3_setup_pad(usbh2stp); - - mdelay(10); - - return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); -} - -static struct mxc_usbh_platform_data usbh2_config __initdata = { - .init = initialize_usbh2_port, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static void __init mx51_efikasb_usb(void) -{ - usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); - if (usbh2_config.otg) - imx51_add_mxc_ehci_hs(2, &usbh2_config); -} - -static const struct gpio_led mx51_efikasb_leds[] __initconst = { - { - .name = "efikasb:green", - .default_trigger = "default-on", - .gpio = EFIKASB_GREEN_LED, - .active_low = 1, - }, - { - .name = "efikasb:white", - .default_trigger = "caps", - .gpio = EFIKASB_WHITE_LED, - }, -}; - -static const struct gpio_led_platform_data - mx51_efikasb_leds_data __initconst = { - .leds = mx51_efikasb_leds, - .num_leds = ARRAY_SIZE(mx51_efikasb_leds), -}; - -static struct gpio_keys_button mx51_efikasb_keys[] = { - { - .code = KEY_POWER, - .gpio = EFIKASB_PWRKEY, - .type = EV_KEY, - .desc = "Power Button", - .wakeup = 1, - .active_low = 1, - }, - { - .code = SW_LID, - .gpio = EFIKASB_LID, - .type = EV_SW, - .desc = "Lid Switch", - .active_low = 1, - }, - { - .code = KEY_RFKILL, - .gpio = EFIKASB_RFKILL, - .type = EV_KEY, - .desc = "rfkill", - .active_low = 1, - }, -}; - -static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = { - .buttons = mx51_efikasb_keys, - .nbuttons = ARRAY_SIZE(mx51_efikasb_keys), -}; - -static struct esdhc_platform_data sd0_pdata = { -#define EFIKASB_SD1_CD IMX_GPIO_NR(2, 27) - .cd_gpio = EFIKASB_SD1_CD, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_CONTROLLER, -}; - -static struct esdhc_platform_data sd1_pdata = { - .cd_type = ESDHC_CD_CONTROLLER, - .wp_type = ESDHC_WP_CONTROLLER, -}; - -static struct regulator *pwgt1, *pwgt2; - -static void mx51_efikasb_power_off(void) -{ - gpio_set_value(EFIKA_USB_PHY_RESET, 0); - - if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { - regulator_disable(pwgt2); - regulator_disable(pwgt1); - } - gpio_direction_output(EFIKASB_POWEROFF, 1); -} - -static int __init mx51_efikasb_power_init(void) -{ - pwgt1 = regulator_get(NULL, "pwgt1"); - pwgt2 = regulator_get(NULL, "pwgt2"); - if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { - regulator_enable(pwgt1); - regulator_enable(pwgt2); - } - gpio_request(EFIKASB_POWEROFF, "poweroff"); - pm_power_off = mx51_efikasb_power_off; - - regulator_has_full_constraints(); - - return 0; -} - -static void __init mx51_efikasb_init_late(void) -{ - imx51_init_late(); - mx51_efikasb_power_init(); -} - -/* 01 R1.3 board - 10 R2.0 board */ -static void __init mx51_efikasb_board_id(void) -{ - int id; - - gpio_request(EFIKASB_PCBID0, "pcb id0"); - gpio_direction_input(EFIKASB_PCBID0); - gpio_request(EFIKASB_PCBID1, "pcb id1"); - gpio_direction_input(EFIKASB_PCBID1); - - id = gpio_get_value(EFIKASB_PCBID0) ? 1 : 0; - id |= (gpio_get_value(EFIKASB_PCBID1) ? 1 : 0) << 1; - - switch (id) { - default: - break; - case 1: - system_rev = 0x13; - break; - case 2: - system_rev = 0x20; - break; - } -} - -static void __init efikasb_board_init(void) -{ - imx51_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads, - ARRAY_SIZE(mx51efikasb_pads)); - efika_board_common_init(); - - mx51_efikasb_board_id(); - mx51_efikasb_usb(); - imx51_add_sdhci_esdhc_imx(0, &sd0_pdata); - imx51_add_sdhci_esdhc_imx(1, &sd1_pdata); - - gpio_led_register_device(-1, &mx51_efikasb_leds_data); - imx_add_gpio_keys(&mx51_efikasb_keys_data); -} - -static void __init mx51_efikasb_timer_init(void) -{ - mx51_clocks_init(32768, 24000000, 22579200, 24576000); -} - -static struct sys_timer mx51_efikasb_timer = { - .init = mx51_efikasb_timer_init, -}; - -MACHINE_START(MX51_EFIKASB, "Genesi Efika MX (Smartbook)") - .atag_offset = 0x100, - .map_io = mx51_map_io, - .init_early = imx51_init_early, - .init_irq = mx51_init_irq, - .handle_irq = imx51_handle_irq, - .init_machine = efikasb_board_init, - .init_late = mx51_efikasb_init_late, - .timer = &mx51_efikasb_timer, - .restart = mxc_restart, -MACHINE_END diff --git a/trunk/arch/arm/mach-imx/mach-mx53_ard.c b/trunk/arch/arm/mach-imx/mach-mx53_ard.c deleted file mode 100644 index 6c28e65f424d..000000000000 --- a/trunk/arch/arm/mach-imx/mach-mx53_ard.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "devices-imx53.h" - -#define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31) -#define ARD_SD1_CD IMX_GPIO_NR(1, 1) -#define ARD_SD1_WP IMX_GPIO_NR(1, 9) -#define ARD_I2CPORTEXP_B IMX_GPIO_NR(2, 3) -#define ARD_VOLUMEDOWN IMX_GPIO_NR(4, 0) -#define ARD_HOME IMX_GPIO_NR(5, 10) -#define ARD_BACK IMX_GPIO_NR(5, 11) -#define ARD_PROG IMX_GPIO_NR(5, 12) -#define ARD_VOLUMEUP IMX_GPIO_NR(5, 13) - -static iomux_v3_cfg_t mx53_ard_pads[] = { - /* UART1 */ - MX53_PAD_PATA_DIOW__UART1_TXD_MUX, - MX53_PAD_PATA_DMACK__UART1_RXD_MUX, - /* WEIM for CS1 */ - MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */ - MX53_PAD_EIM_D16__EMI_WEIM_D_16, - MX53_PAD_EIM_D17__EMI_WEIM_D_17, - MX53_PAD_EIM_D18__EMI_WEIM_D_18, - MX53_PAD_EIM_D19__EMI_WEIM_D_19, - MX53_PAD_EIM_D20__EMI_WEIM_D_20, - MX53_PAD_EIM_D21__EMI_WEIM_D_21, - MX53_PAD_EIM_D22__EMI_WEIM_D_22, - MX53_PAD_EIM_D23__EMI_WEIM_D_23, - MX53_PAD_EIM_D24__EMI_WEIM_D_24, - MX53_PAD_EIM_D25__EMI_WEIM_D_25, - MX53_PAD_EIM_D26__EMI_WEIM_D_26, - MX53_PAD_EIM_D27__EMI_WEIM_D_27, - MX53_PAD_EIM_D28__EMI_WEIM_D_28, - MX53_PAD_EIM_D29__EMI_WEIM_D_29, - MX53_PAD_EIM_D30__EMI_WEIM_D_30, - MX53_PAD_EIM_D31__EMI_WEIM_D_31, - MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0, - MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1, - MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2, - MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3, - MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4, - MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5, - MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6, - MX53_PAD_EIM_OE__EMI_WEIM_OE, - MX53_PAD_EIM_RW__EMI_WEIM_RW, - MX53_PAD_EIM_CS1__EMI_WEIM_CS_1, - /* SDHC1 */ - MX53_PAD_SD1_CMD__ESDHC1_CMD, - MX53_PAD_SD1_CLK__ESDHC1_CLK, - MX53_PAD_SD1_DATA0__ESDHC1_DAT0, - MX53_PAD_SD1_DATA1__ESDHC1_DAT1, - MX53_PAD_SD1_DATA2__ESDHC1_DAT2, - MX53_PAD_SD1_DATA3__ESDHC1_DAT3, - MX53_PAD_PATA_DATA8__ESDHC1_DAT4, - MX53_PAD_PATA_DATA9__ESDHC1_DAT5, - MX53_PAD_PATA_DATA10__ESDHC1_DAT6, - MX53_PAD_PATA_DATA11__ESDHC1_DAT7, - MX53_PAD_GPIO_1__GPIO1_1, - MX53_PAD_GPIO_9__GPIO1_9, - /* I2C2 */ - MX53_PAD_EIM_EB2__I2C2_SCL, - MX53_PAD_KEY_ROW3__I2C2_SDA, - /* I2C3 */ - MX53_PAD_GPIO_3__I2C3_SCL, - MX53_PAD_GPIO_16__I2C3_SDA, - /* GPIO */ - MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */ - MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */ - MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */ - MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */ - MX53_PAD_GPIO_10__GPIO4_0, /* vol down */ -}; - -#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ -{ \ - .gpio = gpio_num, \ - .type = EV_KEY, \ - .code = ev_code, \ - .active_low = act_low, \ - .desc = "btn " descr, \ - .wakeup = wake, \ -} - -static struct gpio_keys_button ard_buttons[] = { - GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0), - GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0), - GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0), - GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0), - GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0), -}; - -static const struct gpio_keys_platform_data ard_button_data __initconst = { - .buttons = ard_buttons, - .nbuttons = ARRAY_SIZE(ard_buttons), -}; - -static struct resource ard_smsc911x_resources[] = { - { - .start = MX53_CS1_64MB_BASE_ADDR, - .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, - { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ, - }, -}; - -struct smsc911x_platform_config ard_smsc911x_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_32BIT, -}; - -static struct platform_device ard_smsc_lan9220_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(ard_smsc911x_resources), - .resource = ard_smsc911x_resources, - .dev = { - .platform_data = &ard_smsc911x_config, - }, -}; - -static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = { - .cd_gpio = ARD_SD1_CD, - .wp_gpio = ARD_SD1_WP, -}; - -static struct imxi2c_platform_data mx53_ard_i2c2_data = { - .bitrate = 50000, -}; - -static struct imxi2c_platform_data mx53_ard_i2c3_data = { - .bitrate = 400000, -}; - -static void __init mx53_ard_io_init(void) -{ - gpio_request(ARD_ETHERNET_INT_B, "eth-int-b"); - gpio_direction_input(ARD_ETHERNET_INT_B); - - gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst"); - gpio_direction_output(ARD_I2CPORTEXP_B, 1); -} - -/* Config CS1 settings for ethernet controller */ -static int weim_cs_config(void) -{ - u32 reg; - void __iomem *weim_base, *iomuxc_base; - - weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K); - if (!weim_base) - return -ENOMEM; - - iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K); - if (!iomuxc_base) { - iounmap(weim_base); - return -ENOMEM; - } - - /* CS1 timings for LAN9220 */ - writel(0x20001, (weim_base + 0x18)); - writel(0x0, (weim_base + 0x1C)); - writel(0x16000202, (weim_base + 0x20)); - writel(0x00000002, (weim_base + 0x24)); - writel(0x16002082, (weim_base + 0x28)); - writel(0x00000000, (weim_base + 0x2C)); - writel(0x00000000, (weim_base + 0x90)); - - /* specify 64 MB on CS1 and CS0 on GPR1 */ - reg = readl(iomuxc_base + 0x4); - reg &= ~0x3F; - reg |= 0x1B; - writel(reg, (iomuxc_base + 0x4)); - - iounmap(iomuxc_base); - iounmap(weim_base); - - return 0; -} - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -void __init imx53_ard_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads, - ARRAY_SIZE(mx53_ard_pads)); - weim_cs_config(); -} - -static struct platform_device *devices[] __initdata = { - &ard_smsc_lan9220_device, -}; - -static void __init mx53_ard_board_init(void) -{ - imx53_soc_init(); - imx53_add_imx_uart(0, NULL); - - imx53_ard_common_init(); - mx53_ard_io_init(); - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - ard_smsc911x_resources[1].start = gpio_to_irq(ARD_ETHERNET_INT_B); - ard_smsc911x_resources[1].end = gpio_to_irq(ARD_ETHERNET_INT_B); - platform_add_devices(devices, ARRAY_SIZE(devices)); - - imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data); - imx53_add_imx2_wdt(0); - imx53_add_imx_i2c(1, &mx53_ard_i2c2_data); - imx53_add_imx_i2c(2, &mx53_ard_i2c3_data); - imx_add_gpio_keys(&ard_button_data); - imx53_add_ahci_imx(); -} - -static void __init mx53_ard_timer_init(void) -{ - mx53_clocks_init(32768, 24000000, 22579200, 0); -} - -static struct sys_timer mx53_ard_timer = { - .init = mx53_ard_timer_init, -}; - -MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board") - .map_io = mx53_map_io, - .init_early = imx53_init_early, - .init_irq = mx53_init_irq, - .handle_irq = imx53_handle_irq, - .timer = &mx53_ard_timer, - .init_machine = mx53_ard_board_init, - .init_late = imx53_init_late, - .restart = mxc_restart, -MACHINE_END diff --git a/trunk/arch/arm/mach-imx/mach-mx53_evk.c b/trunk/arch/arm/mach-imx/mach-mx53_evk.c deleted file mode 100644 index 09fe2197b491..000000000000 --- a/trunk/arch/arm/mach-imx/mach-mx53_evk.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2010 Yong Shen. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6) -#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30) -#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) -#define MX53EVK_LED IMX_GPIO_NR(7, 7) - -#include "devices-imx53.h" - -static iomux_v3_cfg_t mx53_evk_pads[] = { - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, - - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, - MX53_PAD_PATA_DIOR__UART2_RTS, - MX53_PAD_PATA_INTRQ__UART2_CTS, - - MX53_PAD_PATA_CS_0__UART3_TXD_MUX, - MX53_PAD_PATA_CS_1__UART3_RXD_MUX, - - MX53_PAD_EIM_D16__ECSPI1_SCLK, - MX53_PAD_EIM_D17__ECSPI1_MISO, - MX53_PAD_EIM_D18__ECSPI1_MOSI, - - /* ecspi chip select lines */ - MX53_PAD_EIM_EB2__GPIO2_30, - MX53_PAD_EIM_D19__GPIO3_19, - /* LED */ - MX53_PAD_PATA_DA_1__GPIO7_7, -}; - -static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct gpio_led mx53evk_leds[] __initconst = { - { - .name = "green", - .default_trigger = "heartbeat", - .gpio = MX53EVK_LED, - }, -}; - -static const struct gpio_led_platform_data mx53evk_leds_data __initconst = { - .leds = mx53evk_leds, - .num_leds = ARRAY_SIZE(mx53evk_leds), -}; - -static inline void mx53_evk_init_uart(void) -{ - imx53_add_imx_uart(0, NULL); - imx53_add_imx_uart(1, &mx53_evk_uart_pdata); - imx53_add_imx_uart(2, NULL); -} - -static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = { - .bitrate = 100000, -}; - -static inline void mx53_evk_fec_reset(void) -{ - int ret; - - /* reset FEC PHY */ - ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW, - "fec-phy-reset"); - if (ret) { - printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); - return; - } - msleep(1); - gpio_set_value(MX53_EVK_FEC_PHY_RST, 1); -} - -static const struct fec_platform_data mx53_evk_fec_pdata __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static struct spi_board_info mx53_evk_spi_board_info[] __initdata = { - { - .modalias = "mtd_dataflash", - .max_speed_hz = 25000000, - .bus_num = 0, - .chip_select = 1, - .mode = SPI_MODE_0, - .platform_data = NULL, - }, -}; - -static int mx53_evk_spi_cs[] = { - EVK_ECSPI1_CS0, - EVK_ECSPI1_CS1, -}; - -static const struct spi_imx_master mx53_evk_spi_data __initconst = { - .chipselect = mx53_evk_spi_cs, - .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs), -}; - -void __init imx53_evk_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads, - ARRAY_SIZE(mx53_evk_pads)); -} - -static void __init mx53_evk_board_init(void) -{ - imx53_soc_init(); - imx53_evk_common_init(); - - mx53_evk_init_uart(); - mx53_evk_fec_reset(); - imx53_add_fec(&mx53_evk_fec_pdata); - - imx53_add_imx_i2c(0, &mx53_evk_i2c_data); - imx53_add_imx_i2c(1, &mx53_evk_i2c_data); - - imx53_add_sdhci_esdhc_imx(0, NULL); - imx53_add_sdhci_esdhc_imx(1, NULL); - - spi_register_board_info(mx53_evk_spi_board_info, - ARRAY_SIZE(mx53_evk_spi_board_info)); - imx53_add_ecspi(0, &mx53_evk_spi_data); - imx53_add_imx2_wdt(0); - gpio_led_register_device(-1, &mx53evk_leds_data); -} - -static void __init mx53_evk_timer_init(void) -{ - mx53_clocks_init(32768, 24000000, 22579200, 0); -} - -static struct sys_timer mx53_evk_timer = { - .init = mx53_evk_timer_init, -}; - -MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board") - .map_io = mx53_map_io, - .init_early = imx53_init_early, - .init_irq = mx53_init_irq, - .handle_irq = imx53_handle_irq, - .timer = &mx53_evk_timer, - .init_machine = mx53_evk_board_init, - .init_late = imx53_init_late, - .restart = mxc_restart, -MACHINE_END diff --git a/trunk/arch/arm/mach-imx/mach-mx53_loco.c b/trunk/arch/arm/mach-imx/mach-mx53_loco.c deleted file mode 100644 index 8abe23c1d3c8..000000000000 --- a/trunk/arch/arm/mach-imx/mach-mx53_loco.c +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "devices-imx53.h" - -#define MX53_LOCO_POWER IMX_GPIO_NR(1, 8) -#define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14) -#define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15) -#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) -#define LOCO_LED IMX_GPIO_NR(7, 7) -#define LOCO_SD3_CD IMX_GPIO_NR(3, 11) -#define LOCO_SD3_WP IMX_GPIO_NR(3, 12) -#define LOCO_SD1_CD IMX_GPIO_NR(3, 13) -#define LOCO_ACCEL_EN IMX_GPIO_NR(6, 14) - -static iomux_v3_cfg_t mx53_loco_pads[] = { - /* FEC */ - MX53_PAD_FEC_MDC__FEC_MDC, - MX53_PAD_FEC_MDIO__FEC_MDIO, - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, - MX53_PAD_FEC_RX_ER__FEC_RX_ER, - MX53_PAD_FEC_CRS_DV__FEC_RX_DV, - MX53_PAD_FEC_RXD1__FEC_RDATA_1, - MX53_PAD_FEC_RXD0__FEC_RDATA_0, - MX53_PAD_FEC_TX_EN__FEC_TX_EN, - MX53_PAD_FEC_TXD1__FEC_TDATA_1, - MX53_PAD_FEC_TXD0__FEC_TDATA_0, - /* FEC_nRST */ - MX53_PAD_PATA_DA_0__GPIO7_6, - /* FEC_nINT */ - MX53_PAD_PATA_DATA4__GPIO2_4, - /* AUDMUX5 */ - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC, - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD, - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS, - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD, - /* I2C1 */ - MX53_PAD_CSI0_DAT8__I2C1_SDA, - MX53_PAD_CSI0_DAT9__I2C1_SCL, - MX53_PAD_NANDF_CS1__GPIO6_14, /* Accelerometer Enable */ - /* I2C2 */ - MX53_PAD_KEY_COL3__I2C2_SCL, - MX53_PAD_KEY_ROW3__I2C2_SDA, - /* SD1 */ - MX53_PAD_SD1_CMD__ESDHC1_CMD, - MX53_PAD_SD1_CLK__ESDHC1_CLK, - MX53_PAD_SD1_DATA0__ESDHC1_DAT0, - MX53_PAD_SD1_DATA1__ESDHC1_DAT1, - MX53_PAD_SD1_DATA2__ESDHC1_DAT2, - MX53_PAD_SD1_DATA3__ESDHC1_DAT3, - /* SD1_CD */ - MX53_PAD_EIM_DA13__GPIO3_13, - /* SD3 */ - MX53_PAD_PATA_DATA8__ESDHC3_DAT0, - MX53_PAD_PATA_DATA9__ESDHC3_DAT1, - MX53_PAD_PATA_DATA10__ESDHC3_DAT2, - MX53_PAD_PATA_DATA11__ESDHC3_DAT3, - MX53_PAD_PATA_DATA0__ESDHC3_DAT4, - MX53_PAD_PATA_DATA1__ESDHC3_DAT5, - MX53_PAD_PATA_DATA2__ESDHC3_DAT6, - MX53_PAD_PATA_DATA3__ESDHC3_DAT7, - MX53_PAD_PATA_IORDY__ESDHC3_CLK, - MX53_PAD_PATA_RESET_B__ESDHC3_CMD, - /* SD3_CD */ - MX53_PAD_EIM_DA11__GPIO3_11, - /* SD3_WP */ - MX53_PAD_EIM_DA12__GPIO3_12, - /* VGA */ - MX53_PAD_EIM_OE__IPU_DI1_PIN7, - MX53_PAD_EIM_RW__IPU_DI1_PIN8, - /* DISPLB */ - MX53_PAD_EIM_D20__IPU_SER_DISP0_CS, - MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK, - MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN, - MX53_PAD_EIM_D23__IPU_DI0_D0_CS, - /* DISP0_POWER_EN */ - MX53_PAD_EIM_D24__GPIO3_24, - /* DISP0 DET INT */ - MX53_PAD_EIM_D31__GPIO3_31, - /* LVDS */ - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3, - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK, - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2, - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1, - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0, - MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3, - MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2, - MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK, - MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1, - MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0, - /* I2C1 */ - MX53_PAD_CSI0_DAT8__I2C1_SDA, - MX53_PAD_CSI0_DAT9__I2C1_SCL, - /* UART1 */ - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, - /* CSI0 */ - MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12, - MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13, - MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14, - MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15, - MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16, - MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17, - MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18, - MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19, - MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC, - MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC, - MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK, - /* DISPLAY */ - MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK, - MX53_PAD_DI0_PIN15__IPU_DI0_PIN15, - MX53_PAD_DI0_PIN2__IPU_DI0_PIN2, - MX53_PAD_DI0_PIN3__IPU_DI0_PIN3, - MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0, - MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1, - MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2, - MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3, - MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4, - MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5, - MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6, - MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7, - MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8, - MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9, - MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10, - MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11, - MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12, - MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13, - MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14, - MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15, - MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16, - MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17, - MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18, - MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19, - MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20, - MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21, - MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22, - MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23, - /* Audio CLK*/ - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK, - /* PWM */ - MX53_PAD_GPIO_1__PWM2_PWMO, - /* SPDIF */ - MX53_PAD_GPIO_7__SPDIF_PLOCK, - MX53_PAD_GPIO_17__SPDIF_OUT1, - /* GPIO */ - MX53_PAD_PATA_DA_1__GPIO7_7, /* LED */ - MX53_PAD_PATA_DA_2__GPIO7_8, - MX53_PAD_PATA_DATA5__GPIO2_5, - MX53_PAD_PATA_DATA6__GPIO2_6, - MX53_PAD_PATA_DATA14__GPIO2_14, - MX53_PAD_PATA_DATA15__GPIO2_15, - MX53_PAD_PATA_INTRQ__GPIO7_2, - MX53_PAD_EIM_WAIT__GPIO5_0, - MX53_PAD_NANDF_WP_B__GPIO6_9, - MX53_PAD_NANDF_RB0__GPIO6_10, - MX53_PAD_NANDF_CS1__GPIO6_14, - MX53_PAD_NANDF_CS2__GPIO6_15, - MX53_PAD_NANDF_CS3__GPIO6_16, - MX53_PAD_GPIO_5__GPIO1_5, - MX53_PAD_GPIO_16__GPIO7_11, - MX53_PAD_GPIO_8__GPIO1_8, -}; - -#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ -{ \ - .gpio = gpio_num, \ - .type = EV_KEY, \ - .code = ev_code, \ - .active_low = act_low, \ - .desc = "btn " descr, \ - .wakeup = wake, \ -} - -static struct gpio_keys_button loco_buttons[] = { - GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0), - GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0), - GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0), -}; - -static const struct gpio_keys_platform_data loco_button_data __initconst = { - .buttons = loco_buttons, - .nbuttons = ARRAY_SIZE(loco_buttons), -}; - -static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = { - .cd_gpio = LOCO_SD1_CD, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_NONE, -}; - -static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = { - .cd_gpio = LOCO_SD3_CD, - .wp_gpio = LOCO_SD3_WP, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_GPIO, -}; - -static inline void mx53_loco_fec_reset(void) -{ - int ret; - - /* reset FEC PHY */ - ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset"); - if (ret) { - printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); - return; - } - gpio_direction_output(LOCO_FEC_PHY_RST, 0); - msleep(1); - gpio_set_value(LOCO_FEC_PHY_RST, 1); -} - -static const struct fec_platform_data mx53_loco_fec_data __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = { - .bitrate = 100000, -}; - -static const struct gpio_led mx53loco_leds[] __initconst = { - { - .name = "green", - .default_trigger = "heartbeat", - .gpio = LOCO_LED, - }, -}; - -static const struct gpio_led_platform_data mx53loco_leds_data __initconst = { - .leds = mx53loco_leds, - .num_leds = ARRAY_SIZE(mx53loco_leds), -}; - -void __init imx53_qsb_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads, - ARRAY_SIZE(mx53_loco_pads)); -} - -static struct i2c_board_info mx53loco_i2c_devices[] = { - { - I2C_BOARD_INFO("mma8450", 0x1C), - }, -}; - -static void __init mx53_loco_board_init(void) -{ - int ret; - imx53_soc_init(); - imx53_qsb_common_init(); - - imx53_add_imx_uart(0, NULL); - mx53_loco_fec_reset(); - imx53_add_fec(&mx53_loco_fec_data); - imx53_add_imx2_wdt(0); - - ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en"); - if (ret) - pr_err("Cannot request ACCEL_EN pin: %d\n", ret); - - i2c_register_board_info(0, mx53loco_i2c_devices, - ARRAY_SIZE(mx53loco_i2c_devices)); - imx53_add_imx_i2c(0, &mx53_loco_i2c_data); - imx53_add_imx_i2c(1, &mx53_loco_i2c_data); - imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data); - imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data); - imx_add_gpio_keys(&loco_button_data); - gpio_led_register_device(-1, &mx53loco_leds_data); - imx53_add_ahci_imx(); -} - -static void __init mx53_loco_timer_init(void) -{ - mx53_clocks_init(32768, 24000000, 0, 0); -} - -static struct sys_timer mx53_loco_timer = { - .init = mx53_loco_timer_init, -}; - -MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board") - .map_io = mx53_map_io, - .init_early = imx53_init_early, - .init_irq = mx53_init_irq, - .handle_irq = imx53_handle_irq, - .timer = &mx53_loco_timer, - .init_machine = mx53_loco_board_init, - .init_late = imx53_init_late, - .restart = mxc_restart, -MACHINE_END diff --git a/trunk/arch/arm/mach-imx/mach-mx53_smd.c b/trunk/arch/arm/mach-imx/mach-mx53_smd.c deleted file mode 100644 index b15d6a6d3b68..000000000000 --- a/trunk/arch/arm/mach-imx/mach-mx53_smd.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "devices-imx53.h" - -#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) -#define MX53_SMD_SATA_PWR_EN IMX_GPIO_NR(3, 3) - -static iomux_v3_cfg_t mx53_smd_pads[] = { - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, - - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, - - MX53_PAD_PATA_CS_0__UART3_TXD_MUX, - MX53_PAD_PATA_CS_1__UART3_RXD_MUX, - MX53_PAD_PATA_DA_1__UART3_CTS, - MX53_PAD_PATA_DA_2__UART3_RTS, - /* I2C1 */ - MX53_PAD_CSI0_DAT8__I2C1_SDA, - MX53_PAD_CSI0_DAT9__I2C1_SCL, - /* SD1 */ - MX53_PAD_SD1_CMD__ESDHC1_CMD, - MX53_PAD_SD1_CLK__ESDHC1_CLK, - MX53_PAD_SD1_DATA0__ESDHC1_DAT0, - MX53_PAD_SD1_DATA1__ESDHC1_DAT1, - MX53_PAD_SD1_DATA2__ESDHC1_DAT2, - MX53_PAD_SD1_DATA3__ESDHC1_DAT3, - /* SD2 */ - MX53_PAD_SD2_CMD__ESDHC2_CMD, - MX53_PAD_SD2_CLK__ESDHC2_CLK, - MX53_PAD_SD2_DATA0__ESDHC2_DAT0, - MX53_PAD_SD2_DATA1__ESDHC2_DAT1, - MX53_PAD_SD2_DATA2__ESDHC2_DAT2, - MX53_PAD_SD2_DATA3__ESDHC2_DAT3, - /* SD3 */ - MX53_PAD_PATA_DATA8__ESDHC3_DAT0, - MX53_PAD_PATA_DATA9__ESDHC3_DAT1, - MX53_PAD_PATA_DATA10__ESDHC3_DAT2, - MX53_PAD_PATA_DATA11__ESDHC3_DAT3, - MX53_PAD_PATA_DATA0__ESDHC3_DAT4, - MX53_PAD_PATA_DATA1__ESDHC3_DAT5, - MX53_PAD_PATA_DATA2__ESDHC3_DAT6, - MX53_PAD_PATA_DATA3__ESDHC3_DAT7, - MX53_PAD_PATA_IORDY__ESDHC3_CLK, - MX53_PAD_PATA_RESET_B__ESDHC3_CMD, -}; - -static const struct imxuart_platform_data mx53_smd_uart_data __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static inline void mx53_smd_init_uart(void) -{ - imx53_add_imx_uart(0, NULL); - imx53_add_imx_uart(1, NULL); - imx53_add_imx_uart(2, &mx53_smd_uart_data); -} - -static inline void mx53_smd_fec_reset(void) -{ - int ret; - - /* reset FEC PHY */ - ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset"); - if (ret) { - printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); - return; - } - gpio_direction_output(SMD_FEC_PHY_RST, 0); - msleep(1); - gpio_set_value(SMD_FEC_PHY_RST, 1); -} - -static const struct fec_platform_data mx53_smd_fec_data __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = { - .bitrate = 100000, -}; - -static inline void mx53_smd_ahci_pwr_on(void) -{ - int ret; - - /* Enable SATA PWR */ - ret = gpio_request_one(MX53_SMD_SATA_PWR_EN, - GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr"); - if (ret) { - pr_err("failed to enable SATA_PWR_EN: %d\n", ret); - return; - } -} - -void __init imx53_smd_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads, - ARRAY_SIZE(mx53_smd_pads)); -} - -static void __init mx53_smd_board_init(void) -{ - imx53_soc_init(); - imx53_smd_common_init(); - - mx53_smd_init_uart(); - mx53_smd_fec_reset(); - imx53_add_fec(&mx53_smd_fec_data); - imx53_add_imx2_wdt(0); - imx53_add_imx_i2c(0, &mx53_smd_i2c_data); - imx53_add_sdhci_esdhc_imx(0, NULL); - imx53_add_sdhci_esdhc_imx(1, NULL); - imx53_add_sdhci_esdhc_imx(2, NULL); - mx53_smd_ahci_pwr_on(); - imx53_add_ahci_imx(); -} - -static void __init mx53_smd_timer_init(void) -{ - mx53_clocks_init(32768, 24000000, 22579200, 0); -} - -static struct sys_timer mx53_smd_timer = { - .init = mx53_smd_timer_init, -}; - -MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board") - .map_io = mx53_map_io, - .init_early = imx53_init_early, - .init_irq = mx53_init_irq, - .handle_irq = imx53_handle_irq, - .timer = &mx53_smd_timer, - .init_machine = mx53_smd_board_init, - .init_late = imx53_init_late, - .restart = mxc_restart, -MACHINE_END diff --git a/trunk/arch/arm/mach-imx/mm-imx5.c b/trunk/arch/arm/mach-imx/mm-imx5.c index 52d8f534be10..acb0aadb4255 100644 --- a/trunk/arch/arm/mach-imx/mm-imx5.c +++ b/trunk/arch/arm/mach-imx/mm-imx5.c @@ -128,25 +128,6 @@ static struct sdma_platform_data imx51_sdma_pdata __initdata = { .script_addrs = &imx51_sdma_script, }; -static struct sdma_script_start_addrs imx53_sdma_script __initdata = { - .ap_2_ap_addr = 642, - .app_2_mcu_addr = 683, - .mcu_2_app_addr = 747, - .uart_2_mcu_addr = 817, - .shp_2_mcu_addr = 891, - .mcu_2_shp_addr = 960, - .uartsh_2_mcu_addr = 1032, - .spdif_2_mcu_addr = 1100, - .mcu_2_spdif_addr = 1134, - .firi_2_mcu_addr = 1193, - .mcu_2_firi_addr = 1290, -}; - -static struct sdma_platform_data imx53_sdma_pdata __initdata = { - .fw_name = "sdma-imx53.bin", - .script_addrs = &imx53_sdma_script, -}; - static const struct resource imx50_audmux_res[] __initconst = { DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K), }; @@ -155,10 +136,6 @@ static const struct resource imx51_audmux_res[] __initconst = { DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K), }; -static const struct resource imx53_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K), -}; - void __init imx50_soc_init(void) { /* i.mx50 has the i.mx35 type gpio */ @@ -196,30 +173,6 @@ void __init imx51_soc_init(void) ARRAY_SIZE(imx51_audmux_res)); } -void __init imx53_soc_init(void) -{ - /* i.mx53 has the i.mx35 type gpio */ - mxc_register_gpio("imx35-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH); - mxc_register_gpio("imx35-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH); - mxc_register_gpio("imx35-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH); - mxc_register_gpio("imx35-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH); - mxc_register_gpio("imx35-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH); - mxc_register_gpio("imx35-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH); - mxc_register_gpio("imx35-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH); - - pinctrl_provide_dummies(); - /* i.mx53 has the i.mx35 type sdma */ - imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata); - - /* Setup AIPS registers */ - imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR)); - imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR)); - - /* i.mx53 has the i.mx31 type audmux */ - platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res, - ARRAY_SIZE(imx53_audmux_res)); -} - void __init imx51_init_late(void) { mx51_neon_fixup(); diff --git a/trunk/arch/arm/mach-imx/mx51_efika.c b/trunk/arch/arm/mach-imx/mx51_efika.c deleted file mode 100644 index ee870c49bc63..000000000000 --- a/trunk/arch/arm/mach-imx/mx51_efika.c +++ /dev/null @@ -1,633 +0,0 @@ -/* - * based on code from the following - * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. - * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "devices-imx51.h" -#include "efika.h" -#include "cpu_op-mx51.h" - -#define MX51_USB_CTRL_1_OFFSET 0x10 -#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) -#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 - -#define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5) -#define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27) - -#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24) -#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25) - -#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6) - -static iomux_v3_cfg_t mx51efika_pads[] = { - /* UART1 */ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_RTS__UART1_RTS, - MX51_PAD_UART1_CTS__UART1_CTS, - - /* SD 1 */ - MX51_PAD_SD1_CMD__SD1_CMD, - MX51_PAD_SD1_CLK__SD1_CLK, - MX51_PAD_SD1_DATA0__SD1_DATA0, - MX51_PAD_SD1_DATA1__SD1_DATA1, - MX51_PAD_SD1_DATA2__SD1_DATA2, - MX51_PAD_SD1_DATA3__SD1_DATA3, - - /* SD 2 */ - MX51_PAD_SD2_CMD__SD2_CMD, - MX51_PAD_SD2_CLK__SD2_CLK, - MX51_PAD_SD2_DATA0__SD2_DATA0, - MX51_PAD_SD2_DATA1__SD2_DATA1, - MX51_PAD_SD2_DATA2__SD2_DATA2, - MX51_PAD_SD2_DATA3__SD2_DATA3, - - /* SD/MMC WP/CD */ - MX51_PAD_GPIO1_0__SD1_CD, - MX51_PAD_GPIO1_1__SD1_WP, - MX51_PAD_GPIO1_7__SD2_WP, - MX51_PAD_GPIO1_8__SD2_CD, - - /* spi */ - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, - MX51_PAD_CSPI1_MISO__ECSPI1_MISO, - MX51_PAD_CSPI1_SS0__GPIO4_24, - MX51_PAD_CSPI1_SS1__GPIO4_25, - MX51_PAD_CSPI1_RDY__ECSPI1_RDY, - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, - MX51_PAD_GPIO1_6__GPIO1_6, - - /* USB HOST1 */ - MX51_PAD_USBH1_CLK__USBH1_CLK, - MX51_PAD_USBH1_DIR__USBH1_DIR, - MX51_PAD_USBH1_NXT__USBH1_NXT, - MX51_PAD_USBH1_DATA0__USBH1_DATA0, - MX51_PAD_USBH1_DATA1__USBH1_DATA1, - MX51_PAD_USBH1_DATA2__USBH1_DATA2, - MX51_PAD_USBH1_DATA3__USBH1_DATA3, - MX51_PAD_USBH1_DATA4__USBH1_DATA4, - MX51_PAD_USBH1_DATA5__USBH1_DATA5, - MX51_PAD_USBH1_DATA6__USBH1_DATA6, - MX51_PAD_USBH1_DATA7__USBH1_DATA7, - - /* USB HUB RESET */ - MX51_PAD_GPIO1_5__GPIO1_5, - - /* WLAN */ - MX51_PAD_EIM_A22__GPIO2_16, - MX51_PAD_EIM_A16__GPIO2_10, - - /* USB PHY RESET */ - MX51_PAD_EIM_D27__GPIO2_9, -}; - -/* Serial ports */ -static const struct imxuart_platform_data uart_pdata = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* This function is board specific as the bit mask for the plldiv will also - * be different for other Freescale SoCs, thus a common bitmask is not - * possible and cannot get place in /plat-mxc/ehci.c. - */ -static int initialize_otg_port(struct platform_device *pdev) -{ - u32 v; - void __iomem *usb_base; - void __iomem *usbother_base; - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) - return -ENOMEM; - usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); - - /* Set the PHY clock to 19.2MHz */ - v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; - v |= MX51_USB_PLL_DIV_19_2_MHZ; - __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - iounmap(usb_base); - - mdelay(10); - - return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); -} - -static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { - .init = initialize_otg_port, - .portsc = MXC_EHCI_UTMI_16BIT, -}; - -static int initialize_usbh1_port(struct platform_device *pdev) -{ - iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; - iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27; - u32 v; - void __iomem *usb_base; - void __iomem *socregs_base; - - mxc_iomux_v3_setup_pad(usbh1gpio); - gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp"); - gpio_direction_output(EFIKAMX_USBH1_STP, 0); - msleep(1); - gpio_set_value(EFIKAMX_USBH1_STP, 1); - msleep(1); - - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); - - /* The clock for the USBH1 ULPI port will come externally */ - /* from the PHY. */ - v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET); - __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, - socregs_base + MX51_USB_CTRL_1_OFFSET); - - iounmap(usb_base); - - gpio_free(EFIKAMX_USBH1_STP); - mxc_iomux_v3_setup_pad(usbh1stp); - - mdelay(10); - - return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); -} - -static struct mxc_usbh_platform_data usbh1_config __initdata = { - .init = initialize_usbh1_port, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static void mx51_efika_hubreset(void) -{ - gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst"); - gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1); - msleep(1); - gpio_set_value(EFIKAMX_USB_HUB_RESET, 0); - msleep(1); - gpio_set_value(EFIKAMX_USB_HUB_RESET, 1); -} - -static void __init mx51_efika_usb(void) -{ - mx51_efika_hubreset(); - - /* pulling it low, means no USB at all... */ - gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset"); - gpio_direction_output(EFIKA_USB_PHY_RESET, 0); - msleep(1); - gpio_set_value(EFIKA_USB_PHY_RESET, 1); - - usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); - - imx51_add_mxc_ehci_otg(&dr_utmi_config); - if (usbh1_config.otg) - imx51_add_mxc_ehci_hs(1, &usbh1_config); -} - -static struct mtd_partition mx51_efika_spi_nor_partitions[] = { - { - .name = "u-boot", - .offset = 0, - .size = SZ_256K, - }, - { - .name = "config", - .offset = MTDPART_OFS_APPEND, - .size = SZ_64K, - }, -}; - -static struct flash_platform_data mx51_efika_spi_flash_data = { - .name = "spi_flash", - .parts = mx51_efika_spi_nor_partitions, - .nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions), - .type = "sst25vf032b", -}; - -static struct regulator_consumer_supply sw1_consumers[] = { - { - .supply = "cpu_vcc", - } -}; - -static struct regulator_consumer_supply vdig_consumers[] = { - /* sgtl5000 */ - REGULATOR_SUPPLY("VDDA", "1-000a"), - REGULATOR_SUPPLY("VDDD", "1-000a"), -}; - -static struct regulator_consumer_supply vvideo_consumers[] = { - /* sgtl5000 */ - REGULATOR_SUPPLY("VDDIO", "1-000a"), -}; - -static struct regulator_consumer_supply vsd_consumers[] = { - REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"), - REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"), -}; - -static struct regulator_consumer_supply pwgt1_consumer[] = { - { - .supply = "pwgt1", - } -}; - -static struct regulator_consumer_supply pwgt2_consumer[] = { - { - .supply = "pwgt2", - } -}; - -static struct regulator_consumer_supply coincell_consumer[] = { - { - .supply = "coincell", - } -}; - -static struct regulator_init_data sw1_init = { - .constraints = { - .name = "SW1", - .min_uV = 600000, - .max_uV = 1375000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .valid_modes_mask = 0, - .always_on = 1, - .boot_on = 1, - .state_mem = { - .uV = 850000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), - .consumer_supplies = sw1_consumers, -}; - -static struct regulator_init_data sw2_init = { - .constraints = { - .name = "SW2", - .min_uV = 900000, - .max_uV = 1850000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .boot_on = 1, - .state_mem = { - .uV = 950000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - } -}; - -static struct regulator_init_data sw3_init = { - .constraints = { - .name = "SW3", - .min_uV = 1100000, - .max_uV = 1850000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .boot_on = 1, - } -}; - -static struct regulator_init_data sw4_init = { - .constraints = { - .name = "SW4", - .min_uV = 1100000, - .max_uV = 1850000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .boot_on = 1, - } -}; - -static struct regulator_init_data viohi_init = { - .constraints = { - .name = "VIOHI", - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data vusb_init = { - .constraints = { - .name = "VUSB", - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data swbst_init = { - .constraints = { - .name = "SWBST", - } -}; - -static struct regulator_init_data vdig_init = { - .constraints = { - .name = "VDIG", - .min_uV = 1050000, - .max_uV = 1800000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .always_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(vdig_consumers), - .consumer_supplies = vdig_consumers, -}; - -static struct regulator_init_data vpll_init = { - .constraints = { - .name = "VPLL", - .min_uV = 1050000, - .max_uV = 1800000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data vusb2_init = { - .constraints = { - .name = "VUSB2", - .min_uV = 2400000, - .max_uV = 2775000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data vvideo_init = { - .constraints = { - .name = "VVIDEO", - .min_uV = 2775000, - .max_uV = 2775000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .apply_uV = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers), - .consumer_supplies = vvideo_consumers, -}; - -static struct regulator_init_data vaudio_init = { - .constraints = { - .name = "VAUDIO", - .min_uV = 2300000, - .max_uV = 3000000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - } -}; - -static struct regulator_init_data vsd_init = { - .constraints = { - .name = "VSD", - .min_uV = 1800000, - .max_uV = 3150000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(vsd_consumers), - .consumer_supplies = vsd_consumers, -}; - -static struct regulator_init_data vcam_init = { - .constraints = { - .name = "VCAM", - .min_uV = 2500000, - .max_uV = 3000000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, - .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, - .boot_on = 1, - } -}; - -static struct regulator_init_data vgen1_init = { - .constraints = { - .name = "VGEN1", - .min_uV = 1200000, - .max_uV = 3150000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data vgen2_init = { - .constraints = { - .name = "VGEN2", - .min_uV = 1200000, - .max_uV = 3150000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data vgen3_init = { - .constraints = { - .name = "VGEN3", - .min_uV = 1800000, - .max_uV = 2900000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data gpo1_init = { - .constraints = { - .name = "GPO1", - } -}; - -static struct regulator_init_data gpo2_init = { - .constraints = { - .name = "GPO2", - } -}; - -static struct regulator_init_data gpo3_init = { - .constraints = { - .name = "GPO3", - } -}; - -static struct regulator_init_data gpo4_init = { - .constraints = { - .name = "GPO4", - } -}; - -static struct regulator_init_data pwgt1_init = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer), - .consumer_supplies = pwgt1_consumer, -}; - -static struct regulator_init_data pwgt2_init = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer), - .consumer_supplies = pwgt2_consumer, -}; - -static struct regulator_init_data vcoincell_init = { - .constraints = { - .name = "COINCELL", - .min_uV = 3000000, - .max_uV = 3000000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(coincell_consumer), - .consumer_supplies = coincell_consumer, -}; - -static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = { - { .id = MC13892_SW1, .init_data = &sw1_init }, - { .id = MC13892_SW2, .init_data = &sw2_init }, - { .id = MC13892_SW3, .init_data = &sw3_init }, - { .id = MC13892_SW4, .init_data = &sw4_init }, - { .id = MC13892_SWBST, .init_data = &swbst_init }, - { .id = MC13892_VIOHI, .init_data = &viohi_init }, - { .id = MC13892_VPLL, .init_data = &vpll_init }, - { .id = MC13892_VDIG, .init_data = &vdig_init }, - { .id = MC13892_VSD, .init_data = &vsd_init }, - { .id = MC13892_VUSB2, .init_data = &vusb2_init }, - { .id = MC13892_VVIDEO, .init_data = &vvideo_init }, - { .id = MC13892_VAUDIO, .init_data = &vaudio_init }, - { .id = MC13892_VCAM, .init_data = &vcam_init }, - { .id = MC13892_VGEN1, .init_data = &vgen1_init }, - { .id = MC13892_VGEN2, .init_data = &vgen2_init }, - { .id = MC13892_VGEN3, .init_data = &vgen3_init }, - { .id = MC13892_VUSB, .init_data = &vusb_init }, - { .id = MC13892_GPO1, .init_data = &gpo1_init }, - { .id = MC13892_GPO2, .init_data = &gpo2_init }, - { .id = MC13892_GPO3, .init_data = &gpo3_init }, - { .id = MC13892_GPO4, .init_data = &gpo4_init }, - { .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init }, - { .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init }, - { .id = MC13892_VCOINCELL, .init_data = &vcoincell_init }, -}; - -static struct mc13xxx_platform_data mx51_efika_mc13892_data = { - .flags = MC13XXX_USE_RTC, - .regulators = { - .num_regulators = ARRAY_SIZE(mx51_efika_regulators), - .regulators = mx51_efika_regulators, - }, -}; - -static struct spi_board_info mx51_efika_spi_board_info[] __initdata = { - { - .modalias = "m25p80", - .max_speed_hz = 25000000, - .bus_num = 0, - .chip_select = 1, - .platform_data = &mx51_efika_spi_flash_data, - .irq = -1, - }, - { - .modalias = "mc13892", - .max_speed_hz = 1000000, - .bus_num = 0, - .chip_select = 0, - .platform_data = &mx51_efika_mc13892_data, - /* irq number is run-time assigned */ - }, -}; - -static int mx51_efika_spi_cs[] = { - EFIKAMX_SPI_CS0, - EFIKAMX_SPI_CS1, -}; - -static const struct spi_imx_master mx51_efika_spi_pdata __initconst = { - .chipselect = mx51_efika_spi_cs, - .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs), -}; - -void __init efika_board_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx51efika_pads, - ARRAY_SIZE(mx51efika_pads)); - imx51_add_imx_uart(0, &uart_pdata); - mx51_efika_usb(); - - /* FIXME: comes from original code. check this. */ - if (mx51_revision() < IMX_CHIP_REVISION_2_0) - sw2_init.constraints.state_mem.uV = 1100000; - else if (mx51_revision() == IMX_CHIP_REVISION_2_0) { - sw2_init.constraints.state_mem.uV = 1250000; - sw1_init.constraints.state_mem.uV = 1000000; - } - if (machine_is_mx51_efikasb()) - vgen1_init.constraints.max_uV = 1200000; - - gpio_request(EFIKAMX_PMIC, "pmic irq"); - gpio_direction_input(EFIKAMX_PMIC); - mx51_efika_spi_board_info[1].irq = gpio_to_irq(EFIKAMX_PMIC); - spi_register_board_info(mx51_efika_spi_board_info, - ARRAY_SIZE(mx51_efika_spi_board_info)); - imx51_add_ecspi(0, &mx51_efika_spi_pdata); - - imx51_add_pata_imx(); - -#if defined(CONFIG_CPU_FREQ_IMX) - get_cpu_op = mx51_get_cpu_op; -#endif -} diff --git a/trunk/arch/arm/mach-imx/platsmp.c b/trunk/arch/arm/mach-imx/platsmp.c index ab98c6fec9eb..2ac43e1a2dfd 100644 --- a/trunk/arch/arm/mach-imx/platsmp.c +++ b/trunk/arch/arm/mach-imx/platsmp.c @@ -41,7 +41,7 @@ void __init imx_scu_map_io(void) scu_base = IMX_IO_ADDRESS(base); } -void __cpuinit platform_secondary_init(unsigned int cpu) +static void __cpuinit imx_secondary_init(unsigned int cpu) { /* * if any interrupts are already enabled for the primary @@ -51,7 +51,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) gic_secondary_init(0); } -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle) { imx_set_cpu_jump(cpu, v7_secondary_startup); imx_enable_cpu(cpu, true); @@ -62,7 +62,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * Initialise the CPU possible map early - this describes the CPUs * which may be present or become present in the system. */ -void __init smp_init_cpus(void) +static void __init imx_smp_init_cpus(void) { int i, ncores; @@ -79,7 +79,17 @@ void imx_smp_prepare(void) scu_enable(scu_base); } -void __init platform_smp_prepare_cpus(unsigned int max_cpus) +static void __init imx_smp_prepare_cpus(unsigned int max_cpus) { imx_smp_prepare(); } + +struct smp_operations imx_smp_ops __initdata = { + .smp_init_cpus = imx_smp_init_cpus, + .smp_prepare_cpus = imx_smp_prepare_cpus, + .smp_secondary_init = imx_secondary_init, + .smp_boot_secondary = imx_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = imx_cpu_die, +#endif +}; diff --git a/trunk/arch/arm/mach-integrator/core.c b/trunk/arch/arm/mach-integrator/core.c index 3fa6c51390da..a432d4325f89 100644 --- a/trunk/arch/arm/mach-integrator/core.c +++ b/trunk/arch/arm/mach-integrator/core.c @@ -95,8 +95,8 @@ arch_initcall(integrator_init); * UART0 7 6 * UART1 5 4 */ -#define SC_CTRLC IO_ADDRESS(INTEGRATOR_SC_CTRLC) -#define SC_CTRLS IO_ADDRESS(INTEGRATOR_SC_CTRLS) +#define SC_CTRLC __io_address(INTEGRATOR_SC_CTRLC) +#define SC_CTRLS __io_address(INTEGRATOR_SC_CTRLS) static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl) { diff --git a/trunk/arch/arm/mach-integrator/cpu.c b/trunk/arch/arm/mach-integrator/cpu.c index fbb457779895..590c192cdf4d 100644 --- a/trunk/arch/arm/mach-integrator/cpu.c +++ b/trunk/arch/arm/mach-integrator/cpu.c @@ -25,10 +25,10 @@ static struct cpufreq_driver integrator_driver; -#define CM_ID IO_ADDRESS(INTEGRATOR_HDR_ID) -#define CM_OSC IO_ADDRESS(INTEGRATOR_HDR_OSC) -#define CM_STAT IO_ADDRESS(INTEGRATOR_HDR_STAT) -#define CM_LOCK IO_ADDRESS(INTEGRATOR_HDR_LOCK) +#define CM_ID __io_address(INTEGRATOR_HDR_ID) +#define CM_OSC __io_address(INTEGRATOR_HDR_OSC) +#define CM_STAT __io_address(INTEGRATOR_HDR_STAT) +#define CM_LOCK __io_address(INTEGRATOR_HDR_LOCK) static const struct icst_params lclk_params = { .ref = 24000000, diff --git a/trunk/arch/arm/mach-integrator/include/mach/io.h b/trunk/arch/arm/mach-integrator/include/mach/io.h deleted file mode 100644 index 8de70de3dd0a..000000000000 --- a/trunk/arch/arm/mach-integrator/include/mach/io.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * arch/arm/mach-integrator/include/mach/io.h - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -/* - * WARNING: this has to mirror definitions in platform.h - */ -#define PCI_MEMORY_VADDR 0xe8000000 -#define PCI_CONFIG_VADDR 0xec000000 -#define PCI_V3_VADDR 0xed000000 -#define PCI_IO_VADDR 0xee000000 - -#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a))) - -#endif diff --git a/trunk/arch/arm/mach-integrator/include/mach/platform.h b/trunk/arch/arm/mach-integrator/include/mach/platform.h index ec467baade09..4c0347526851 100644 --- a/trunk/arch/arm/mach-integrator/include/mach/platform.h +++ b/trunk/arch/arm/mach-integrator/include/mach/platform.h @@ -324,6 +324,10 @@ */ #define PHYS_PCI_V3_BASE 0x62000000 +#define PCI_MEMORY_VADDR 0xe8000000 +#define PCI_CONFIG_VADDR 0xec000000 +#define PCI_V3_VADDR 0xed000000 + /* ------------------------------------------------------------------------ * Integrator Interrupt Controllers * ------------------------------------------------------------------------ diff --git a/trunk/arch/arm/mach-integrator/integrator_ap.c b/trunk/arch/arm/mach-integrator/integrator_ap.c index 3b2267529f5e..2215d96cd735 100644 --- a/trunk/arch/arm/mach-integrator/integrator_ap.c +++ b/trunk/arch/arm/mach-integrator/integrator_ap.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include @@ -73,7 +74,7 @@ * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k) - * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) + * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) * ef000000 Cache flush * f1000000 10000000 Core module registers * f1100000 11000000 System controller registers @@ -133,25 +134,20 @@ static struct map_desc ap_io_desc[] __initdata = { .length = SZ_4K, .type = MT_DEVICE }, { - .virtual = PCI_MEMORY_VADDR, + .virtual = (unsigned long)PCI_MEMORY_VADDR, .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE), .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = PCI_CONFIG_VADDR, + .virtual = (unsigned long)PCI_CONFIG_VADDR, .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE), .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = PCI_V3_VADDR, + .virtual = (unsigned long)PCI_V3_VADDR, .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE), .length = SZ_64K, .type = MT_DEVICE - }, { - .virtual = PCI_IO_VADDR, - .pfn = __phys_to_pfn(PHYS_PCI_IO_BASE), - .length = SZ_64K, - .type = MT_DEVICE } }; @@ -159,6 +155,7 @@ static void __init ap_map_io(void) { iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); vga_base = PCI_MEMORY_VADDR; + pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE)); } #define INTEGRATOR_SC_VALID_INT 0x003fffff @@ -317,9 +314,9 @@ static void __init ap_init(void) /* * Where is the timer (VA)? */ -#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE) -#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE) -#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE) +#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE) +#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE) +#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE) static unsigned long timer_reload; diff --git a/trunk/arch/arm/mach-integrator/integrator_cp.c b/trunk/arch/arm/mach-integrator/integrator_cp.c index 82d5c837cc74..3df5fc369361 100644 --- a/trunk/arch/arm/mach-integrator/integrator_cp.c +++ b/trunk/arch/arm/mach-integrator/integrator_cp.c @@ -59,7 +59,7 @@ #define INTCP_ETH_SIZE 0x10 -#define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE) +#define INTCP_VA_CTRL_BASE __io_address(INTEGRATOR_CP_CTL_BASE) #define INTCP_FLASHPROG 0x04 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0) #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1) @@ -265,8 +265,8 @@ static struct platform_device *intcp_devs[] __initdata = { */ static unsigned int mmc_status(struct device *dev) { - unsigned int status = readl(IO_ADDRESS(0xca000000 + 4)); - writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8)); + unsigned int status = readl(__io_address(0xca000000 + 4)); + writel(8, __io_address(INTEGRATOR_CP_CTL_BASE + 8)); return status & 8; } diff --git a/trunk/arch/arm/mach-integrator/pci_v3.c b/trunk/arch/arm/mach-integrator/pci_v3.c index b866880e82ac..bbeca59df66b 100644 --- a/trunk/arch/arm/mach-integrator/pci_v3.c +++ b/trunk/arch/arm/mach-integrator/pci_v3.c @@ -41,61 +41,61 @@ /* * The V3 PCI interface chip in Integrator provides several windows from * local bus memory into the PCI memory areas. Unfortunately, there - * are not really enough windows for our usage, therefore we reuse + * are not really enough windows for our usage, therefore we reuse * one of the windows for access to PCI configuration space. The * memory map is as follows: - * + * * Local Bus Memory Usage - * + * * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable * 60000000 - 60FFFFFF PCI IO. 16M * 61000000 - 61FFFFFF PCI Configuration. 16M - * + * * There are three V3 windows, each described by a pair of V3 registers. * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2. * Base0 and Base1 can be used for any type of PCI memory access. Base2 * can be used either for PCI I/O or for I20 accesses. By default, uHAL * uses this only for PCI IO space. - * + * * Normally these spaces are mapped using the following base registers: - * + * * Usage Local Bus Memory Base/Map registers used - * + * * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 * Cfg 61000000 - 61FFFFFF - * + * * This means that I20 and PCI configuration space accesses will fail. - * When PCI configuration accesses are needed (via the uHAL PCI + * When PCI configuration accesses are needed (via the uHAL PCI * configuration space primitives) we must remap the spaces as follows: - * + * * Usage Local Bus Memory Base/Map registers used - * + * * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1 - * + * * To make this work, the code depends on overlapping windows working. - * The V3 chip translates an address by checking its range within + * The V3 chip translates an address by checking its range within * each of the BASE/MAP pairs in turn (in ascending register number * order). It will use the first matching pair. So, for example, * if the same address is mapped by both LB_BASE0/LB_MAP0 and - * LB_BASE1/LB_MAP1, the V3 will use the translation from + * LB_BASE1/LB_MAP1, the V3 will use the translation from * LB_BASE0/LB_MAP0. - * + * * To allow PCI Configuration space access, the code enlarges the * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can * be remapped for use by configuration cycles. - * - * At the end of the PCI Configuration space accesses, + * + * At the end of the PCI Configuration space accesses, * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to * reveal the now restored LB_BASE1/LB_MAP1 window. - * + * * NOTE: We do not set up I2O mapping. I suspect that this is only * for an intelligent (target) device. Using I2O disables most of * the mappings into PCI memory. @@ -127,8 +127,8 @@ * * returns: configuration address to play on the PCI bus * - * To generate the appropriate PCI configuration cycles in the PCI - * configuration address space, you present the V3 with the following pattern + * To generate the appropriate PCI configuration cycles in the PCI + * configuration address space, you present the V3 with the following pattern * (which is very nearly a type 1 (except that the lower two bits are 00 and * not 01). In order for this mapping to work you need to set up one of * the local to PCI aperatures to 16Mbytes in length translating to @@ -138,7 +138,7 @@ * * Type 0: * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 + * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0| @@ -150,7 +150,7 @@ * * Type 1: * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 + * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| @@ -161,7 +161,7 @@ * 15:11 Device number (5 bits) * 10:8 function number * 7:2 register number - * + * */ static DEFINE_RAW_SPINLOCK(v3_lock); @@ -181,7 +181,7 @@ static DEFINE_RAW_SPINLOCK(v3_lock); #undef V3_LB_BASE_PREFETCH #define V3_LB_BASE_PREFETCH 0 -static unsigned long v3_open_config_window(struct pci_bus *bus, +static void __iomem *v3_open_config_window(struct pci_bus *bus, unsigned int devfn, int offset) { unsigned int address, mapaddress, busnr; @@ -280,7 +280,7 @@ static void v3_close_config_window(void) static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { - unsigned long addr; + void __iomem *addr; unsigned long flags; u32 v; @@ -311,7 +311,7 @@ static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where, static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { - unsigned long addr; + void __iomem *addr; unsigned long flags; raw_spin_lock_irqsave(&v3_lock, flags); @@ -374,12 +374,9 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys) } /* - * the IO resource for this bus * the mem resource for this bus * the prefetch mem resource for this bus */ - pci_add_resource_offset(&sys->resources, - &ioport_resource, sys->io_offset); pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset); pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset); @@ -391,9 +388,9 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys) * means I can't get additional information on the reason for the pm2fb * problems. I suppose I'll just have to mind-meld with the machine. ;) */ -#define SC_PCI IO_ADDRESS(INTEGRATOR_SC_PCIENABLE) -#define SC_LBFADDR IO_ADDRESS(INTEGRATOR_SC_BASE + 0x20) -#define SC_LBFCODE IO_ADDRESS(INTEGRATOR_SC_BASE + 0x24) +#define SC_PCI __io_address(INTEGRATOR_SC_PCIENABLE) +#define SC_LBFADDR __io_address(INTEGRATOR_SC_BASE + 0x20) +#define SC_LBFCODE __io_address(INTEGRATOR_SC_BASE + 0x24) static int v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) @@ -498,7 +495,6 @@ void __init pci_v3_preinit(void) unsigned int temp; int ret; - pcibios_min_io = 0x6000; pcibios_min_mem = 0x00100000; /* diff --git a/trunk/arch/arm/mach-iop13xx/include/mach/io.h b/trunk/arch/arm/mach-iop13xx/include/mach/io.h deleted file mode 100644 index f13188518025..000000000000 --- a/trunk/arch/arm/mach-iop13xx/include/mach/io.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * iop13xx custom ioremap implementation - * Copyright (c) 2005-2006, Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 59 Temple - * Place - Suite 330, Boston, MA 02111-1307 USA. - * - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(a) __iop13xx_io(a) - -extern void __iomem * __iop13xx_io(unsigned long io_addr); - -#endif diff --git a/trunk/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/trunk/arch/arm/mach-iop13xx/include/mach/iop13xx.h index e190dcd7d72d..7480f58267aa 100644 --- a/trunk/arch/arm/mach-iop13xx/include/mach/iop13xx.h +++ b/trunk/arch/arm/mach-iop13xx/include/mach/iop13xx.h @@ -69,21 +69,11 @@ extern unsigned long get_iop_tick_rate(void); * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window * * IO MAP - * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window - * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window + * 0x00000 + 64K 0x0.fffb.0000 0xfee0.0000 PCIX outbound i/o window + * 0x10000 + 64K 0x0.fffd.0000 0xfee1.0000 PCIE outbound i/o window */ -#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL #define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL -#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL #define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */ -#define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL -#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\ - IOP13XX_PCIX_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\ - IOP13XX_PCIX_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ - (IOP13XX_PCIX_LOWER_IO_PA\ - - IOP13XX_PCIX_LOWER_IO_VA)) #define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL #define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL @@ -103,20 +93,8 @@ extern unsigned long get_iop_tick_rate(void); IOP13XX_PCIX_LOWER_MEM_BA) /* PCI-E ranges */ -#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL #define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL -#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL -#define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */ -#define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL -#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\ - IOP13XX_PCIE_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\ - IOP13XX_PCIE_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\ - IOP13XX_PCIE_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ - (IOP13XX_PCIE_LOWER_IO_PA\ - - IOP13XX_PCIE_LOWER_IO_VA)) +#define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL /* OIOTVR */ #define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL #define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL @@ -148,18 +126,16 @@ extern unsigned long get_iop_tick_rate(void); * IOP13XX chipset registers */ #define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */ -#define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */ +#define IOP13XX_PMMR_VIRT_MEM_BASE (void __iomem *)(0xfee80000UL) /* PMMR phys. address */ #define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000 #define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\ IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) #define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\ IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) -#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\ - (IOP13XX_PMMR_PHYS_MEM_BASE\ - - IOP13XX_PMMR_VIRT_MEM_BASE)) -#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ - (IOP13XX_PMMR_PHYS_MEM_BASE\ - - IOP13XX_PMMR_VIRT_MEM_BASE)) +#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\ + + IOP13XX_PMMR_PHYS_MEM_BASE) +#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\ + + IOP13XX_PMMR_VIRT_MEM_BASE) #define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) #define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) #define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) @@ -169,10 +145,10 @@ extern unsigned long get_iop_tick_rate(void); #define IOP13XX_PMMR_SIZE 0x00080000 /*=================== Defines for Platform Devices =====================*/ -#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300) -#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340) -#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300) -#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340) +#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300) +#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340) +#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300) +#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340) #define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500) #define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520) diff --git a/trunk/arch/arm/mach-iop13xx/include/mach/memory.h b/trunk/arch/arm/mach-iop13xx/include/mach/memory.h index 1afa99ef97fa..7c032d0ab24a 100644 --- a/trunk/arch/arm/mach-iop13xx/include/mach/memory.h +++ b/trunk/arch/arm/mach-iop13xx/include/mach/memory.h @@ -16,12 +16,12 @@ #define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE) #define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE) -static inline dma_addr_t __virt_to_lbus(unsigned long x) +static inline dma_addr_t __virt_to_lbus(void __iomem *x) { return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE; } -static inline unsigned long __lbus_to_virt(dma_addr_t x) +static inline void __iomem *__lbus_to_virt(dma_addr_t x) { return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE; } @@ -38,23 +38,23 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x) #define __arch_dma_to_virt(dev, addr) \ ({ \ - unsigned long __virt; \ + void * __virt; \ dma_addr_t __dma = addr; \ if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \ __virt = __lbus_to_virt(__dma); \ else \ - __virt = __phys_to_virt(__dma); \ - (void *)__virt; \ + __virt = (void *)__phys_to_virt(__dma); \ + __virt; \ }) #define __arch_virt_to_dma(dev, addr) \ ({ \ - unsigned long __virt = (unsigned long)addr; \ + void * __virt = addr; \ dma_addr_t __dma; \ if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \ __dma = __virt_to_lbus(__virt); \ else \ - __dma = __virt_to_phys(__virt); \ + __dma = __virt_to_phys((unsigned long)__virt); \ __dma; \ }) diff --git a/trunk/arch/arm/mach-iop13xx/io.c b/trunk/arch/arm/mach-iop13xx/io.c index 3c364198db9c..183dc8b5511b 100644 --- a/trunk/arch/arm/mach-iop13xx/io.c +++ b/trunk/arch/arm/mach-iop13xx/io.c @@ -23,25 +23,6 @@ #include "pci.h" -void * __iomem __iop13xx_io(unsigned long io_addr) -{ - void __iomem * io_virt; - - switch (io_addr) { - case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA: - io_virt = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(io_addr); - break; - case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA: - io_virt = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(io_addr); - break; - default: - BUG(); - } - - return io_virt; -} -EXPORT_SYMBOL(__iop13xx_io); - static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, size_t size, unsigned int mtype, void *caller) { @@ -52,14 +33,14 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, if (unlikely(!iop13xx_atux_mem_base)) retval = NULL; else - retval = (void *)(iop13xx_atux_mem_base + + retval = (iop13xx_atux_mem_base + (cookie - IOP13XX_PCIX_LOWER_MEM_RA)); break; case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA: if (unlikely(!iop13xx_atue_mem_base)) retval = NULL; else - retval = (void *)(iop13xx_atue_mem_base + + retval = (iop13xx_atue_mem_base + (cookie - IOP13XX_PCIE_LOWER_MEM_RA)); break; case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA: @@ -67,14 +48,8 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, (cookie - IOP13XX_PBI_LOWER_MEM_RA), size, mtype, __builtin_return_address(0)); break; - case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA: - retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie); - break; - case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA: - retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie); - break; case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA: - retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie); + retval = IOP13XX_PMMR_PHYS_TO_VIRT(cookie); break; default: retval = __arm_ioremap_caller(cookie, size, mtype, @@ -99,9 +74,7 @@ static void __iop13xx_iounmap(volatile void __iomem *addr) goto skip; switch ((u32) addr) { - case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA: - case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA: - case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA: + case (u32)IOP13XX_PMMR_VIRT_MEM_BASE ... (u32)IOP13XX_PMMR_UPPER_MEM_VA: goto skip; } __iounmap(addr); diff --git a/trunk/arch/arm/mach-iop13xx/pci.c b/trunk/arch/arm/mach-iop13xx/pci.c index 861cb12ef436..9082b84aeebb 100644 --- a/trunk/arch/arm/mach-iop13xx/pci.c +++ b/trunk/arch/arm/mach-iop13xx/pci.c @@ -36,8 +36,8 @@ u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */ u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */ static struct pci_bus *pci_bus_atux = 0; static struct pci_bus *pci_bus_atue = 0; -u32 iop13xx_atue_mem_base; -u32 iop13xx_atux_mem_base; +void __iomem *iop13xx_atue_mem_base; +void __iomem *iop13xx_atux_mem_base; size_t iop13xx_atue_mem_size; size_t iop13xx_atux_mem_size; @@ -88,8 +88,7 @@ void iop13xx_map_pci_memory(void) } if (end) { - iop13xx_atux_mem_base = - (u32) __arm_ioremap_pfn( + iop13xx_atux_mem_base = __arm_ioremap_pfn( __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA) , 0, iop13xx_atux_mem_size, MT_DEVICE); if (!iop13xx_atux_mem_base) { @@ -99,7 +98,7 @@ void iop13xx_map_pci_memory(void) } } else iop13xx_atux_mem_size = 0; - PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", + PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n", __func__, atu, iop13xx_atux_mem_size, iop13xx_atux_mem_base); break; @@ -114,8 +113,7 @@ void iop13xx_map_pci_memory(void) } if (end) { - iop13xx_atue_mem_base = - (u32) __arm_ioremap_pfn( + iop13xx_atue_mem_base = __arm_ioremap_pfn( __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA) , 0, iop13xx_atue_mem_size, MT_DEVICE); if (!iop13xx_atue_mem_base) { @@ -125,13 +123,13 @@ void iop13xx_map_pci_memory(void) } } else iop13xx_atue_mem_size = 0; - PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", + PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n", __func__, atu, iop13xx_atue_mem_size, iop13xx_atue_mem_base); break; } - printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n", + printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n", atu ? "ATUE" : "ATUX", (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) / SZ_1M, @@ -970,7 +968,6 @@ void __init iop13xx_pci_init(void) __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR); /* Setup the Min Address for PCI memory... */ - pcibios_min_io = 0; pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA; /* if Linux is given control of an ATU @@ -1003,7 +1000,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) if (nr > 1) return 0; - res = kcalloc(2, sizeof(struct resource), GFP_KERNEL); + res = kzalloc(sizeof(struct resource), GFP_KERNEL); if (!res) panic("PCI: unable to alloc resources"); @@ -1042,17 +1039,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) << IOP13XX_ATUX_PCIXSR_FUNC_NUM; __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); - res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET; - res[0].end = IOP13XX_PCIX_UPPER_IO_PA; - res[0].name = "IQ81340 ATUX PCI I/O Space"; - res[0].flags = IORESOURCE_IO; + pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA); - res[1].start = IOP13XX_PCIX_LOWER_MEM_RA; - res[1].end = IOP13XX_PCIX_UPPER_MEM_RA; - res[1].name = "IQ81340 ATUX PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; + res->start = IOP13XX_PCIX_LOWER_MEM_RA; + res->end = IOP13XX_PCIX_UPPER_MEM_RA; + res->name = "IQ81340 ATUX PCI Memory Space"; + res->flags = IORESOURCE_MEM; sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET; - sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA; break; case IOP13XX_INIT_ATU_ATUE: /* Note: the function number field in the PCSR is ro */ @@ -1063,17 +1056,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) __raw_writel(pcsr, IOP13XX_ATUE_PCSR); - res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET; - res[0].end = IOP13XX_PCIE_UPPER_IO_PA; - res[0].name = "IQ81340 ATUE PCI I/O Space"; - res[0].flags = IORESOURCE_IO; + pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA); - res[1].start = IOP13XX_PCIE_LOWER_MEM_RA; - res[1].end = IOP13XX_PCIE_UPPER_MEM_RA; - res[1].name = "IQ81340 ATUE PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; + res->start = IOP13XX_PCIE_LOWER_MEM_RA; + res->end = IOP13XX_PCIE_UPPER_MEM_RA; + res->name = "IQ81340 ATUE PCI Memory Space"; + res->flags = IORESOURCE_MEM; sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET; - sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA; sys->map_irq = iop13xx_pcie_map_irq; break; default: @@ -1081,11 +1070,9 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) return 0; } - request_resource(&ioport_resource, &res[0]); - request_resource(&iomem_resource, &res[1]); + request_resource(&iomem_resource, res); - pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); - pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, res, sys->mem_offset); return 1; } diff --git a/trunk/arch/arm/mach-iop13xx/pci.h b/trunk/arch/arm/mach-iop13xx/pci.h index c70cf5b41e31..d45a80b3080e 100644 --- a/trunk/arch/arm/mach-iop13xx/pci.h +++ b/trunk/arch/arm/mach-iop13xx/pci.h @@ -1,6 +1,6 @@ #include -extern u32 iop13xx_atue_mem_base; -extern u32 iop13xx_atux_mem_base; +extern void __iomem *iop13xx_atue_mem_base; +extern void __iomem *iop13xx_atux_mem_base; extern size_t iop13xx_atue_mem_size; extern size_t iop13xx_atux_mem_size; diff --git a/trunk/arch/arm/mach-iop13xx/setup.c b/trunk/arch/arm/mach-iop13xx/setup.c index daabb1fa6c2c..3181f61ea63e 100644 --- a/trunk/arch/arm/mach-iop13xx/setup.c +++ b/trunk/arch/arm/mach-iop13xx/setup.c @@ -36,20 +36,10 @@ */ static struct map_desc iop13xx_std_desc[] __initdata = { { /* mem mapped registers */ - .virtual = IOP13XX_PMMR_VIRT_MEM_BASE, + .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE, .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE), .length = IOP13XX_PMMR_SIZE, .type = MT_DEVICE, - }, { /* PCIE IO space */ - .virtual = IOP13XX_PCIE_LOWER_IO_VA, - .pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA), - .length = IOP13XX_PCIX_IO_WINDOW_SIZE, - .type = MT_DEVICE, - }, { /* PCIX IO space */ - .virtual = IOP13XX_PCIX_LOWER_IO_VA, - .pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA), - .length = IOP13XX_PCIX_IO_WINDOW_SIZE, - .type = MT_DEVICE, }, }; @@ -81,8 +71,8 @@ static struct resource iop13xx_uart1_resources[] = { static struct plat_serial8250_port iop13xx_uart0_data[] = { { - .membase = (char*)(IOP13XX_UART0_VIRT), - .mapbase = (IOP13XX_UART0_PHYS), + .membase = IOP13XX_UART0_VIRT, + .mapbase = IOP13XX_UART0_PHYS, .irq = IRQ_IOP13XX_UART0, .uartclk = IOP13XX_UART_XTAL, .regshift = 2, @@ -94,8 +84,8 @@ static struct plat_serial8250_port iop13xx_uart0_data[] = { static struct plat_serial8250_port iop13xx_uart1_data[] = { { - .membase = (char*)(IOP13XX_UART1_VIRT), - .mapbase = (IOP13XX_UART1_PHYS), + .membase = IOP13XX_UART1_VIRT, + .mapbase = IOP13XX_UART1_PHYS, .irq = IRQ_IOP13XX_UART1, .uartclk = IOP13XX_UART_XTAL, .regshift = 2, diff --git a/trunk/arch/arm/mach-iop32x/glantank.c b/trunk/arch/arm/mach-iop32x/glantank.c index c15a100ba779..02e20c3912ba 100644 --- a/trunk/arch/arm/mach-iop32x/glantank.c +++ b/trunk/arch/arm/mach-iop32x/glantank.c @@ -183,7 +183,7 @@ static struct i2c_board_info __initdata glantank_i2c_devices[] = { static void glantank_power_off(void) { - __raw_writeb(0x01, 0xfe8d0004); + __raw_writeb(0x01, IOMEM(0xfe8d0004)); while (1) ; diff --git a/trunk/arch/arm/mach-iop32x/include/mach/io.h b/trunk/arch/arm/mach-iop32x/include/mach/io.h deleted file mode 100644 index e2ada265bb8d..000000000000 --- a/trunk/arch/arm/mach-iop32x/include/mach/io.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-iop32x/include/mach/io.h - * - * Copyright (C) 2001 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __IO_H -#define __IO_H - -#include - -#define IO_SPACE_LIMIT 0xffffffff -#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p)) - -#endif diff --git a/trunk/arch/arm/mach-iop33x/include/mach/io.h b/trunk/arch/arm/mach-iop33x/include/mach/io.h deleted file mode 100644 index f7c1b6595660..000000000000 --- a/trunk/arch/arm/mach-iop33x/include/mach/io.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-iop33x/include/mach/io.h - * - * Copyright (C) 2001 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __IO_H -#define __IO_H - -#include - -#define IO_SPACE_LIMIT 0xffffffff -#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p)) - -#endif diff --git a/trunk/arch/arm/mach-ixp4xx/common.c b/trunk/arch/arm/mach-ixp4xx/common.c index a9f80943d01f..fdf91a160884 100644 --- a/trunk/arch/arm/mach-ixp4xx/common.c +++ b/trunk/arch/arm/mach-ixp4xx/common.c @@ -53,24 +53,24 @@ static struct clock_event_device clockevent_ixp4xx; *************************************************************************/ static struct map_desc ixp4xx_io_desc[] __initdata = { { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */ - .virtual = IXP4XX_PERIPHERAL_BASE_VIRT, + .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS), .length = IXP4XX_PERIPHERAL_REGION_SIZE, .type = MT_DEVICE }, { /* Expansion Bus Config Registers */ - .virtual = IXP4XX_EXP_CFG_BASE_VIRT, + .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS), .length = IXP4XX_EXP_CFG_REGION_SIZE, .type = MT_DEVICE }, { /* PCI Registers */ - .virtual = IXP4XX_PCI_CFG_BASE_VIRT, + .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS), .length = IXP4XX_PCI_CFG_REGION_SIZE, .type = MT_DEVICE }, #ifdef CONFIG_DEBUG_LL { /* Debug UART mapping */ - .virtual = IXP4XX_DEBUG_UART_BASE_VIRT, + .virtual = (unsigned long)IXP4XX_DEBUG_UART_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS), .length = IXP4XX_DEBUG_UART_REGION_SIZE, .type = MT_DEVICE diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/cpu.h b/trunk/arch/arm/mach-ixp4xx/include/mach/cpu.h index b2ef65db0e91..ebc0ba31ce85 100644 --- a/trunk/arch/arm/mach-ixp4xx/include/mach/cpu.h +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/cpu.h @@ -14,6 +14,7 @@ #ifndef __ASM_ARCH_CPU_H__ #define __ASM_ARCH_CPU_H__ +#include #include /* Processor id value in CP15 Register 0 */ @@ -37,7 +38,7 @@ static inline u32 ixp4xx_read_feature_bits(void) { - u32 val = ~*IXP4XX_EXP_CFG2; + u32 val = ~__raw_readl(IXP4XX_EXP_CFG2); if (cpu_is_ixp42x_rev_a0()) return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP | @@ -51,7 +52,7 @@ static inline u32 ixp4xx_read_feature_bits(void) static inline void ixp4xx_write_feature_bits(u32 value) { - *IXP4XX_EXP_CFG2 = ~value; + __raw_writel(~value, IXP4XX_EXP_CFG2); } #endif /* _ASM_ARCH_CPU_H */ diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/gpio.h b/trunk/arch/arm/mach-ixp4xx/include/mach/gpio.h deleted file mode 100644 index ef37f2635b0e..000000000000 --- a/trunk/arch/arm/mach-ixp4xx/include/mach/gpio.h +++ /dev/null @@ -1,2 +0,0 @@ -/* empty */ - diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/trunk/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h index 97c530f66e78..eb68b61ce975 100644 --- a/trunk/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h @@ -49,21 +49,21 @@ * Expansion BUS Configuration registers */ #define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000) -#define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFE000) +#define IXP4XX_EXP_CFG_BASE_VIRT IOMEM(0xFFBFE000) #define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000) /* * PCI Config registers */ #define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000) -#define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFF000) +#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFFBFF000) #define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000) /* * Peripheral space */ #define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000) -#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBEB000) +#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFFBEB000) #define IXP4XX_PERIPHERAL_REGION_SIZE (0x00013000) /* @@ -73,7 +73,7 @@ * aligned so that it * can be used with the low-level debug code. */ #define IXP4XX_DEBUG_UART_BASE_PHYS (0xC8000000) -#define IXP4XX_DEBUG_UART_BASE_VIRT (0xffb00000) +#define IXP4XX_DEBUG_UART_BASE_VIRT IOMEM(0xffb00000) #define IXP4XX_DEBUG_UART_REGION_SIZE (0x00001000) #define IXP4XX_EXP_CS0_OFFSET 0x00 @@ -92,7 +92,7 @@ /* * Expansion Bus Controller registers. */ -#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) +#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) #define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET) #define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET) diff --git a/trunk/arch/arm/mach-kirkwood/Makefile.boot b/trunk/arch/arm/mach-kirkwood/Makefile.boot index a13299d758e1..760a0efe7580 100644 --- a/trunk/arch/arm/mach-kirkwood/Makefile.boot +++ b/trunk/arch/arm/mach-kirkwood/Makefile.boot @@ -1,14 +1,3 @@ zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 - -dtb-$(CONFIG_MACH_DREAMPLUG_DT) += kirkwood-dreamplug.dtb -dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns320.dtb -dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb -dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb -dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb -dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-ts219-6281.dtb -dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-ts219-6282.dtb -dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb -dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb -dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb diff --git a/trunk/arch/arm/mach-kirkwood/common.c b/trunk/arch/arm/mach-kirkwood/common.c index 1201191d7f1b..3f7b05f30b46 100644 --- a/trunk/arch/arm/mach-kirkwood/common.c +++ b/trunk/arch/arm/mach-kirkwood/common.c @@ -42,16 +42,6 @@ ****************************************************************************/ static struct map_desc kirkwood_io_desc[] __initdata = { { - .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE, - .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE), - .length = KIRKWOOD_PCIE_IO_SIZE, - .type = MT_DEVICE, - }, { - .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE, - .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE), - .length = KIRKWOOD_PCIE1_IO_SIZE, - .type = MT_DEVICE, - }, { .virtual = KIRKWOOD_REGS_VIRT_BASE, .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), .length = KIRKWOOD_REGS_SIZE, diff --git a/trunk/arch/arm/mach-kirkwood/include/mach/gpio.h b/trunk/arch/arm/mach-kirkwood/include/mach/gpio.h deleted file mode 100644 index 84f340b546c0..000000000000 --- a/trunk/arch/arm/mach-kirkwood/include/mach/gpio.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * arch/asm-arm/mach-kirkwood/include/mach/gpio.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include diff --git a/trunk/arch/arm/mach-kirkwood/include/mach/io.h b/trunk/arch/arm/mach-kirkwood/include/mach/io.h deleted file mode 100644 index 5d0ab61700d2..000000000000 --- a/trunk/arch/arm/mach-kirkwood/include/mach/io.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-kirkwood/include/mach/io.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include "kirkwood.h" - -#define IO_SPACE_LIMIT 0xffffffff - -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_BUS_BASE) - + KIRKWOOD_PCIE_IO_VIRT_BASE); -} - -#define __io(a) __io(a) - -#endif diff --git a/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h index c5b68510776b..af4f0000dcef 100644 --- a/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -37,14 +37,12 @@ #define KIRKWOOD_NAND_MEM_SIZE SZ_1K #define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000 -#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000 -#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00100000 -#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M +#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00010000 +#define KIRKWOOD_PCIE1_IO_SIZE SZ_64K #define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 -#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000 #define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 -#define KIRKWOOD_PCIE_IO_SIZE SZ_1M +#define KIRKWOOD_PCIE_IO_SIZE SZ_64K #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 #define KIRKWOOD_REGS_VIRT_BASE 0xfed00000 diff --git a/trunk/arch/arm/mach-kirkwood/irq.c b/trunk/arch/arm/mach-kirkwood/irq.c index 720063ffa19d..20149a7fd280 100644 --- a/trunk/arch/arm/mach-kirkwood/irq.c +++ b/trunk/arch/arm/mach-kirkwood/irq.c @@ -11,6 +11,7 @@ #include #include #include +#include #include static int __initdata gpio0_irqs[4] = { diff --git a/trunk/arch/arm/mach-kirkwood/pcie.c b/trunk/arch/arm/mach-kirkwood/pcie.c index 6e8b2efa3c35..532d8acb38f9 100644 --- a/trunk/arch/arm/mach-kirkwood/pcie.c +++ b/trunk/arch/arm/mach-kirkwood/pcie.c @@ -56,7 +56,7 @@ struct pcie_port { void __iomem *base; spinlock_t conf_lock; int irq; - struct resource res[2]; + struct resource res; }; static int pcie_port_map[2]; @@ -136,21 +136,13 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp) pp->base = (void __iomem *)PCIE_VIRT_BASE; pp->irq = IRQ_KIRKWOOD_PCIE; - /* - * IORESOURCE_IO - */ - pp->res[0].name = "PCIe 0 I/O Space"; - pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE; - pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1; - pp->res[0].flags = IORESOURCE_IO; - /* * IORESOURCE_MEM */ - pp->res[1].name = "PCIe 0 MEM"; - pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE; - pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; - pp->res[1].flags = IORESOURCE_MEM; + pp->res.name = "PCIe 0 MEM"; + pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE; + pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1; + pp->res.flags = IORESOURCE_MEM; } static void __init pcie1_ioresources_init(struct pcie_port *pp) @@ -158,21 +150,13 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp) pp->base = (void __iomem *)PCIE1_VIRT_BASE; pp->irq = IRQ_KIRKWOOD_PCIE1; - /* - * IORESOURCE_IO - */ - pp->res[0].name = "PCIe 1 I/O Space"; - pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE; - pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1; - pp->res[0].flags = IORESOURCE_IO; - /* * IORESOURCE_MEM */ - pp->res[1].name = "PCIe 1 MEM"; - pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE; - pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1; - pp->res[1].flags = IORESOURCE_MEM; + pp->res.name = "PCIe 1 MEM"; + pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE; + pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1; + pp->res.flags = IORESOURCE_MEM; } static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) @@ -197,23 +181,21 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) case 0: kirkwood_enable_pcie_clk("0"); pcie0_ioresources_init(pp); + pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE); break; case 1: kirkwood_enable_pcie_clk("1"); pcie1_ioresources_init(pp); + pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE1_IO_PHYS_BASE); break; default: panic("PCIe setup: invalid controller %d", index); } - if (request_resource(&ioport_resource, &pp->res[0])) - panic("Request PCIe%d IO resource failed\n", index); - if (request_resource(&iomem_resource, &pp->res[1])) + if (request_resource(&iomem_resource, &pp->res)) panic("Request PCIe%d Memory resource failed\n", index); - sys->io_offset = 0; - pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); - pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); /* * Generic PCIe unit setup. diff --git a/trunk/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/trunk/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c index f742a66a7045..19072c84008f 100644 --- a/trunk/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c +++ b/trunk/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "common.h" #define RD88F6192_GPIO_USB_VBUS 10 diff --git a/trunk/arch/arm/mach-ks8695/cpu.c b/trunk/arch/arm/mach-ks8695/cpu.c index 7f3f24053a00..ddb24222918e 100644 --- a/trunk/arch/arm/mach-ks8695/cpu.c +++ b/trunk/arch/arm/mach-ks8695/cpu.c @@ -36,7 +36,7 @@ static struct __initdata map_desc ks8695_io_desc[] = { { - .virtual = KS8695_IO_VA, + .virtual = (unsigned long)KS8695_IO_VA, .pfn = __phys_to_pfn(KS8695_IO_PA), .length = KS8695_IO_SIZE, .type = MT_DEVICE, diff --git a/trunk/arch/arm/mach-ks8695/include/mach/hardware.h b/trunk/arch/arm/mach-ks8695/include/mach/hardware.h index 5e0c388143da..5090338c0db2 100644 --- a/trunk/arch/arm/mach-ks8695/include/mach/hardware.h +++ b/trunk/arch/arm/mach-ks8695/include/mach/hardware.h @@ -33,7 +33,7 @@ * head debug code as the initial MMU setup only deals in L1 sections. */ #define KS8695_IO_PA 0x03F00000 -#define KS8695_IO_VA 0xF0000000 +#define KS8695_IO_VA IOMEM(0xF0000000) #define KS8695_IO_SIZE SZ_1M #define KS8695_PCIMEM_PA 0x60000000 diff --git a/trunk/arch/arm/mach-ks8695/include/mach/regs-timer.h b/trunk/arch/arm/mach-ks8695/include/mach/regs-timer.h deleted file mode 100644 index e620cda99d2d..000000000000 --- a/trunk/arch/arm/mach-ks8695/include/mach/regs-timer.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-timer.h - * - * Copyright (C) 2006 Ben Dooks - * Copyright (C) 2006 Simtec Electronics - * - * KS8695 - Timer registers and bit definitions. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_TIMER_H -#define KS8695_TIMER_H - -#define KS8695_TMR_OFFSET (0xF0000 + 0xE400) -#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET) -#define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET) - - -/* - * Timer registers - */ -#define KS8695_TMCON (0x00) /* Timer Control Register */ -#define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */ -#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */ -#define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */ -#define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */ - - -/* Timer Control Register */ -#define TMCON_T1EN (1 << 1) /* Timer 1 Enable */ -#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */ - -/* Timer0 Timeout Counter Register */ -#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */ - - -#endif diff --git a/trunk/arch/arm/mach-ks8695/include/mach/uncompress.h b/trunk/arch/arm/mach-ks8695/include/mach/uncompress.h index 9495cb4d701a..8879d610308a 100644 --- a/trunk/arch/arm/mach-ks8695/include/mach/uncompress.h +++ b/trunk/arch/arm/mach-ks8695/include/mach/uncompress.h @@ -19,15 +19,15 @@ static void putc(char c) { - while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE)) + while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE)) barrier(); - __raw_writel(c, KS8695_UART_PA + KS8695_URTH); + __raw_writel(c, (void __iomem*)KS8695_UART_PA + KS8695_URTH); } static inline void flush(void) { - while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE)) + while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTE)) barrier(); } diff --git a/trunk/arch/arm/mach-ks8695/time.c b/trunk/arch/arm/mach-ks8695/time.c index ec783a3070ae..46c84bc7792c 100644 --- a/trunk/arch/arm/mach-ks8695/time.c +++ b/trunk/arch/arm/mach-ks8695/time.c @@ -25,53 +25,98 @@ #include #include #include +#include #include #include -#include #include #include "generic.h" +#define KS8695_TMR_OFFSET (0xF0000 + 0xE400) +#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET) +#define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET) + /* - * Returns number of ms since last clock interrupt. Note that interrupts - * will have been disabled by do_gettimeoffset() + * Timer registers */ -static unsigned long ks8695_gettimeoffset (void) +#define KS8695_TMCON (0x00) /* Timer Control Register */ +#define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */ +#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */ +#define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */ +#define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */ + +/* Timer Control Register */ +#define TMCON_T1EN (1 << 1) /* Timer 1 Enable */ +#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */ + +/* Timer0 Timeout Counter Register */ +#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */ + +static void ks8695_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) { - unsigned long elapsed, tick2, intpending; + u32 tmcon; - /* - * Get the current number of ticks. Note that there is a race - * condition between us reading the timer and checking for an - * interrupt. We solve this by ensuring that the counter has not - * reloaded between our two reads. - */ - elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD); - do { - tick2 = elapsed; - intpending = __raw_readl(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1); - elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD); - } while (elapsed > tick2); - - /* Convert to number of ticks expired (not remaining) */ - elapsed = (CLOCK_TICK_RATE / HZ) - elapsed; - - /* Is interrupt pending? If so, then timer has been reloaded already. */ - if (intpending) - elapsed += (CLOCK_TICK_RATE / HZ); - - /* Convert ticks to usecs */ - return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH; + if (mode == CLOCK_EVT_FEAT_PERIODIC) { + u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ); + u32 half = DIV_ROUND_CLOSEST(rate, 2); + + /* Disable timer 1 */ + tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); + tmcon &= ~TMCON_T1EN; + writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); + + /* Both registers need to count down */ + writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC); + writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD); + + /* Re-enable timer1 */ + tmcon |= TMCON_T1EN; + writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); + } } +static int ks8695_set_next_event(unsigned long cycles, + struct clock_event_device *evt) + +{ + u32 half = DIV_ROUND_CLOSEST(cycles, 2); + u32 tmcon; + + /* Disable timer 1 */ + tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); + tmcon &= ~TMCON_T1EN; + writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); + + /* Both registers need to count down */ + writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC); + writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD); + + /* Re-enable timer1 */ + tmcon |= TMCON_T1EN; + writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); + + return 0; +} + +static struct clock_event_device clockevent_ks8695 = { + .name = "ks8695_t1tc", + .rating = 300, /* Reasonably fast and accurate clock event */ + .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, + .set_next_event = ks8695_set_next_event, + .set_mode = ks8695_set_mode, +}; + /* * IRQ handler for the timer. */ static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id) { - timer_tick(); + struct clock_event_device *evt = &clockevent_ks8695; + + evt->event_handler(evt); return IRQ_HANDLED; } @@ -83,18 +128,22 @@ static struct irqaction ks8695_timer_irq = { static void ks8695_timer_setup(void) { - unsigned long tmout = CLOCK_TICK_RATE / HZ; unsigned long tmcon; - /* disable timer1 */ - tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); - __raw_writel(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON); - - __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1TC); - __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1PD); + /* Disable timer 0 and 1 */ + tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); + tmcon &= ~TMCON_T0EN; + tmcon &= ~TMCON_T1EN; + writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); - /* re-enable timer1 */ - __raw_writel(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON); + /* + * Use timer 1 to fire IRQs on the timeline, minimum 2 cycles + * (one on each counter) maximum 2*2^32, but the API will only + * accept up to a 32bit full word (0xFFFFFFFFU). + */ + clockevents_config_and_register(&clockevent_ks8695, + KS8695_CLOCK_RATE, 2, + 0xFFFFFFFFU); } static void __init ks8695_timer_init (void) @@ -107,8 +156,6 @@ static void __init ks8695_timer_init (void) struct sys_timer ks8695_timer = { .init = ks8695_timer_init, - .offset = ks8695_gettimeoffset, - .resume = ks8695_timer_setup, }; void ks8695_restart(char mode, const char *cmd) @@ -119,12 +166,12 @@ void ks8695_restart(char mode, const char *cmd) soft_restart(0); /* disable timer0 */ - reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); - __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); + reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); + writel_relaxed(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); /* enable watchdog mode */ - __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC); + writel_relaxed((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC); /* re-enable timer0 */ - __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); + writel_relaxed(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); } diff --git a/trunk/arch/arm/mach-lpc32xx/Makefile.boot b/trunk/arch/arm/mach-lpc32xx/Makefile.boot index 697323b5f92d..d7392a475247 100644 --- a/trunk/arch/arm/mach-lpc32xx/Makefile.boot +++ b/trunk/arch/arm/mach-lpc32xx/Makefile.boot @@ -1,5 +1,3 @@ zreladdr-y += 0x80008000 params_phys-y := 0x80000100 initrd_phys-y := 0x82000000 - -dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb diff --git a/trunk/arch/arm/mach-lpc32xx/common.c b/trunk/arch/arm/mach-lpc32xx/common.c index a48dc2dec485..0d4db8c544b5 100644 --- a/trunk/arch/arm/mach-lpc32xx/common.c +++ b/trunk/arch/arm/mach-lpc32xx/common.c @@ -177,25 +177,25 @@ u32 clk_get_pclk_div(void) static struct map_desc lpc32xx_io_desc[] __initdata = { { - .virtual = IO_ADDRESS(LPC32XX_AHB0_START), + .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START), .pfn = __phys_to_pfn(LPC32XX_AHB0_START), .length = LPC32XX_AHB0_SIZE, .type = MT_DEVICE }, { - .virtual = IO_ADDRESS(LPC32XX_AHB1_START), + .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB1_START), .pfn = __phys_to_pfn(LPC32XX_AHB1_START), .length = LPC32XX_AHB1_SIZE, .type = MT_DEVICE }, { - .virtual = IO_ADDRESS(LPC32XX_FABAPB_START), + .virtual = (unsigned long)IO_ADDRESS(LPC32XX_FABAPB_START), .pfn = __phys_to_pfn(LPC32XX_FABAPB_START), .length = LPC32XX_FABAPB_SIZE, .type = MT_DEVICE }, { - .virtual = IO_ADDRESS(LPC32XX_IRAM_BASE), + .virtual = (unsigned long)IO_ADDRESS(LPC32XX_IRAM_BASE), .pfn = __phys_to_pfn(LPC32XX_IRAM_BASE), .length = (LPC32XX_IRAM_BANK_SIZE * 2), .type = MT_DEVICE diff --git a/trunk/arch/arm/mach-lpc32xx/include/mach/hardware.h b/trunk/arch/arm/mach-lpc32xx/include/mach/hardware.h index 33e1dde37bd9..69065de97a3d 100644 --- a/trunk/arch/arm/mach-lpc32xx/include/mach/hardware.h +++ b/trunk/arch/arm/mach-lpc32xx/include/mach/hardware.h @@ -25,7 +25,7 @@ /* * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */ -#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ +#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ IO_BASE) #define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x)) diff --git a/trunk/arch/arm/mach-lpc32xx/irq.c b/trunk/arch/arm/mach-lpc32xx/irq.c index 5b1cc35e6fba..3c6332753358 100644 --- a/trunk/arch/arm/mach-lpc32xx/irq.c +++ b/trunk/arch/arm/mach-lpc32xx/irq.c @@ -283,21 +283,25 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_EDGE_RISING: /* Rising edge sensitive */ __lpc32xx_set_irq_type(d->hwirq, 1, 1); + __irq_set_handler_locked(d->hwirq, handle_edge_irq); break; case IRQ_TYPE_EDGE_FALLING: /* Falling edge sensitive */ __lpc32xx_set_irq_type(d->hwirq, 0, 1); + __irq_set_handler_locked(d->hwirq, handle_edge_irq); break; case IRQ_TYPE_LEVEL_LOW: /* Low level sensitive */ __lpc32xx_set_irq_type(d->hwirq, 0, 0); + __irq_set_handler_locked(d->hwirq, handle_level_irq); break; case IRQ_TYPE_LEVEL_HIGH: /* High level sensitive */ __lpc32xx_set_irq_type(d->hwirq, 1, 0); + __irq_set_handler_locked(d->hwirq, handle_level_irq); break; /* Other modes are not supported */ @@ -305,9 +309,6 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type) return -EINVAL; } - /* Ok to use the level handler for all types */ - irq_set_handler(d->hwirq, handle_level_irq); - return 0; } diff --git a/trunk/arch/arm/mach-lpc32xx/phy3250.c b/trunk/arch/arm/mach-lpc32xx/phy3250.c index b07dcc90829d..8f2a2f8712d7 100644 --- a/trunk/arch/arm/mach-lpc32xx/phy3250.c +++ b/trunk/arch/arm/mach-lpc32xx/phy3250.c @@ -37,6 +37,8 @@ #include #include #include +#include +#include #include #include @@ -223,6 +225,14 @@ static struct mmci_platform_data lpc32xx_mmci_data = { * gather, and the MMCI driver doesn't do it this way */ }; +static struct lpc32xx_slc_platform_data lpc32xx_slc_data = { + .dma_filter = pl08x_filter_id, +}; + +static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = { + .dma_filter = pl08x_filter_id, +}; + static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data), OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data), @@ -230,6 +240,10 @@ static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd), OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd", &lpc32xx_mmci_data), + OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash", + &lpc32xx_slc_data), + OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash", + &lpc32xx_mlc_data), { } }; @@ -253,12 +267,6 @@ static void __init lpc3250_machine_init(void) of_platform_populate(NULL, of_default_bus_match_table, lpc32xx_auxdata_lookup, NULL); - - /* Register GPIOs used on this board */ - if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en")) - pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO); - else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1)) - pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO); } static char const *lpc32xx_dt_compat[] __initdata = { diff --git a/trunk/arch/arm/mach-mmp/Kconfig b/trunk/arch/arm/mach-mmp/Kconfig index 7fddd01b85b9..d697d07a1bf0 100644 --- a/trunk/arch/arm/mach-mmp/Kconfig +++ b/trunk/arch/arm/mach-mmp/Kconfig @@ -108,18 +108,21 @@ endmenu config CPU_PXA168 bool select CPU_MOHAWK + select COMMON_CLK help Select code specific to PXA168 config CPU_PXA910 bool select CPU_MOHAWK + select COMMON_CLK help Select code specific to PXA910 config CPU_MMP2 bool select CPU_PJ4 + select COMMON_CLK help Select code specific to MMP2. MMP2 is ARMv7 compatible. diff --git a/trunk/arch/arm/mach-mmp/Makefile b/trunk/arch/arm/mach-mmp/Makefile index b786f7e6cd1f..095c155d6fb8 100644 --- a/trunk/arch/arm/mach-mmp/Makefile +++ b/trunk/arch/arm/mach-mmp/Makefile @@ -2,13 +2,19 @@ # Makefile for Marvell's PXA168 processors line # -obj-y += common.o clock.o devices.o time.o irq.o +obj-y += common.o devices.o time.o irq.o # SoC support obj-$(CONFIG_CPU_PXA168) += pxa168.o obj-$(CONFIG_CPU_PXA910) += pxa910.o obj-$(CONFIG_CPU_MMP2) += mmp2.o sram.o +ifeq ($(CONFIG_COMMON_CLK), ) +obj-y += clock.o +obj-$(CONFIG_CPU_PXA168) += clock-pxa168.o +obj-$(CONFIG_CPU_PXA910) += clock-pxa910.o +obj-$(CONFIG_CPU_MMP2) += clock-mmp2.o +endif ifeq ($(CONFIG_PM),y) obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o diff --git a/trunk/arch/arm/mach-mmp/clock-mmp2.c b/trunk/arch/arm/mach-mmp/clock-mmp2.c new file mode 100644 index 000000000000..21d22002cd19 --- /dev/null +++ b/trunk/arch/arm/mach-mmp/clock-mmp2.c @@ -0,0 +1,111 @@ +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "clock.h" + +/* + * APB Clock register offsets for MMP2 + */ +#define APBC_RTC APBC_REG(0x000) +#define APBC_TWSI1 APBC_REG(0x004) +#define APBC_TWSI2 APBC_REG(0x008) +#define APBC_TWSI3 APBC_REG(0x00c) +#define APBC_TWSI4 APBC_REG(0x010) +#define APBC_KPC APBC_REG(0x018) +#define APBC_UART1 APBC_REG(0x02c) +#define APBC_UART2 APBC_REG(0x030) +#define APBC_UART3 APBC_REG(0x034) +#define APBC_GPIO APBC_REG(0x038) +#define APBC_PWM0 APBC_REG(0x03c) +#define APBC_PWM1 APBC_REG(0x040) +#define APBC_PWM2 APBC_REG(0x044) +#define APBC_PWM3 APBC_REG(0x048) +#define APBC_SSP0 APBC_REG(0x04c) +#define APBC_SSP1 APBC_REG(0x050) +#define APBC_SSP2 APBC_REG(0x054) +#define APBC_SSP3 APBC_REG(0x058) +#define APBC_SSP4 APBC_REG(0x05c) +#define APBC_SSP5 APBC_REG(0x060) +#define APBC_TWSI5 APBC_REG(0x07c) +#define APBC_TWSI6 APBC_REG(0x080) +#define APBC_UART4 APBC_REG(0x088) + +#define APMU_USB APMU_REG(0x05c) +#define APMU_NAND APMU_REG(0x060) +#define APMU_SDH0 APMU_REG(0x054) +#define APMU_SDH1 APMU_REG(0x058) +#define APMU_SDH2 APMU_REG(0x0e8) +#define APMU_SDH3 APMU_REG(0x0ec) + +static void sdhc_clk_enable(struct clk *clk) +{ + uint32_t clk_rst; + + clk_rst = __raw_readl(clk->clk_rst); + clk_rst |= clk->enable_val; + __raw_writel(clk_rst, clk->clk_rst); +} + +static void sdhc_clk_disable(struct clk *clk) +{ + uint32_t clk_rst; + + clk_rst = __raw_readl(clk->clk_rst); + clk_rst &= ~clk->enable_val; + __raw_writel(clk_rst, clk->clk_rst); +} + +struct clkops sdhc_clk_ops = { + .enable = sdhc_clk_enable, + .disable = sdhc_clk_disable, +}; + +/* APB peripheral clocks */ +static APBC_CLK(uart1, UART1, 1, 26000000); +static APBC_CLK(uart2, UART2, 1, 26000000); +static APBC_CLK(uart3, UART3, 1, 26000000); +static APBC_CLK(uart4, UART4, 1, 26000000); +static APBC_CLK(twsi1, TWSI1, 0, 26000000); +static APBC_CLK(twsi2, TWSI2, 0, 26000000); +static APBC_CLK(twsi3, TWSI3, 0, 26000000); +static APBC_CLK(twsi4, TWSI4, 0, 26000000); +static APBC_CLK(twsi5, TWSI5, 0, 26000000); +static APBC_CLK(twsi6, TWSI6, 0, 26000000); +static APBC_CLK(gpio, GPIO, 0, 26000000); + +static APMU_CLK(nand, NAND, 0xbf, 100000000); +static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops); +static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops); +static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops); +static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops); + +static struct clk_lookup mmp2_clkregs[] = { + INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), + INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), + INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), + INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), + INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), + INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), + INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), + INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), + INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), + INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"), + INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"), + INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"), + INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"), +}; + +void __init mmp2_clk_init(void) +{ + clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs)); +} diff --git a/trunk/arch/arm/mach-mmp/clock-pxa168.c b/trunk/arch/arm/mach-mmp/clock-pxa168.c new file mode 100644 index 000000000000..5e6c18ccebd4 --- /dev/null +++ b/trunk/arch/arm/mach-mmp/clock-pxa168.c @@ -0,0 +1,91 @@ +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "clock.h" + +/* + * APB clock register offsets for PXA168 + */ +#define APBC_UART1 APBC_REG(0x000) +#define APBC_UART2 APBC_REG(0x004) +#define APBC_GPIO APBC_REG(0x008) +#define APBC_PWM1 APBC_REG(0x00c) +#define APBC_PWM2 APBC_REG(0x010) +#define APBC_PWM3 APBC_REG(0x014) +#define APBC_PWM4 APBC_REG(0x018) +#define APBC_RTC APBC_REG(0x028) +#define APBC_TWSI0 APBC_REG(0x02c) +#define APBC_KPC APBC_REG(0x030) +#define APBC_TWSI1 APBC_REG(0x06c) +#define APBC_UART3 APBC_REG(0x070) +#define APBC_SSP1 APBC_REG(0x81c) +#define APBC_SSP2 APBC_REG(0x820) +#define APBC_SSP3 APBC_REG(0x84c) +#define APBC_SSP4 APBC_REG(0x858) +#define APBC_SSP5 APBC_REG(0x85c) + +#define APMU_NAND APMU_REG(0x060) +#define APMU_LCD APMU_REG(0x04c) +#define APMU_ETH APMU_REG(0x0fc) +#define APMU_USB APMU_REG(0x05c) + +/* APB peripheral clocks */ +static APBC_CLK(uart1, UART1, 1, 14745600); +static APBC_CLK(uart2, UART2, 1, 14745600); +static APBC_CLK(uart3, UART3, 1, 14745600); +static APBC_CLK(twsi0, TWSI0, 1, 33000000); +static APBC_CLK(twsi1, TWSI1, 1, 33000000); +static APBC_CLK(pwm1, PWM1, 1, 13000000); +static APBC_CLK(pwm2, PWM2, 1, 13000000); +static APBC_CLK(pwm3, PWM3, 1, 13000000); +static APBC_CLK(pwm4, PWM4, 1, 13000000); +static APBC_CLK(ssp1, SSP1, 4, 0); +static APBC_CLK(ssp2, SSP2, 4, 0); +static APBC_CLK(ssp3, SSP3, 4, 0); +static APBC_CLK(ssp4, SSP4, 4, 0); +static APBC_CLK(ssp5, SSP5, 4, 0); +static APBC_CLK(gpio, GPIO, 0, 13000000); +static APBC_CLK(keypad, KPC, 0, 32000); +static APBC_CLK(rtc, RTC, 8, 32768); + +static APMU_CLK(nand, NAND, 0x19b, 156000000); +static APMU_CLK(lcd, LCD, 0x7f, 312000000); +static APMU_CLK(eth, ETH, 0x09, 0); +static APMU_CLK(usb, USB, 0x12, 0); + +/* device and clock bindings */ +static struct clk_lookup pxa168_clkregs[] = { + INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), + INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), + INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL), + INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), + INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), + INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), + INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL), + INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL), + INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL), + INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL), + INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL), + INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), + INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL), + INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), + INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL), + INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"), + INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"), + INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), +}; + +void __init pxa168_clk_init(void) +{ + clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs)); +} diff --git a/trunk/arch/arm/mach-mmp/clock-pxa910.c b/trunk/arch/arm/mach-mmp/clock-pxa910.c new file mode 100644 index 000000000000..933ea71d0b56 --- /dev/null +++ b/trunk/arch/arm/mach-mmp/clock-pxa910.c @@ -0,0 +1,67 @@ +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "clock.h" + +/* + * APB Clock register offsets for PXA910 + */ +#define APBC_UART0 APBC_REG(0x000) +#define APBC_UART1 APBC_REG(0x004) +#define APBC_GPIO APBC_REG(0x008) +#define APBC_PWM1 APBC_REG(0x00c) +#define APBC_PWM2 APBC_REG(0x010) +#define APBC_PWM3 APBC_REG(0x014) +#define APBC_PWM4 APBC_REG(0x018) +#define APBC_SSP1 APBC_REG(0x01c) +#define APBC_SSP2 APBC_REG(0x020) +#define APBC_RTC APBC_REG(0x028) +#define APBC_TWSI0 APBC_REG(0x02c) +#define APBC_KPC APBC_REG(0x030) +#define APBC_SSP3 APBC_REG(0x04c) +#define APBC_TWSI1 APBC_REG(0x06c) + +#define APMU_NAND APMU_REG(0x060) +#define APMU_USB APMU_REG(0x05c) + +static APBC_CLK(uart1, UART0, 1, 14745600); +static APBC_CLK(uart2, UART1, 1, 14745600); +static APBC_CLK(twsi0, TWSI0, 1, 33000000); +static APBC_CLK(twsi1, TWSI1, 1, 33000000); +static APBC_CLK(pwm1, PWM1, 1, 13000000); +static APBC_CLK(pwm2, PWM2, 1, 13000000); +static APBC_CLK(pwm3, PWM3, 1, 13000000); +static APBC_CLK(pwm4, PWM4, 1, 13000000); +static APBC_CLK(gpio, GPIO, 0, 13000000); +static APBC_CLK(rtc, RTC, 8, 32768); + +static APMU_CLK(nand, NAND, 0x19b, 156000000); +static APMU_CLK(u2o, USB, 0x1b, 480000000); + +/* device and clock bindings */ +static struct clk_lookup pxa910_clkregs[] = { + INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), + INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL), + INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL), + INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), + INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), + INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), + INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), + INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"), + INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), +}; + +void __init pxa910_clk_init(void) +{ + clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs)); +} diff --git a/trunk/arch/arm/mach-mmp/common.h b/trunk/arch/arm/mach-mmp/common.h index 1c9d6c1ea97a..bd453274fca2 100644 --- a/trunk/arch/arm/mach-mmp/common.h +++ b/trunk/arch/arm/mach-mmp/common.h @@ -7,3 +7,6 @@ extern void timer_init(int irq); extern void __init icu_init_irq(void); extern void __init mmp_map_io(void); extern void mmp_restart(char, const char *); +extern void __init pxa168_clk_init(void); +extern void __init pxa910_clk_init(void); +extern void __init mmp2_clk_init(void); diff --git a/trunk/arch/arm/mach-mmp/include/mach/regs-apbc.h b/trunk/arch/arm/mach-mmp/include/mach/regs-apbc.h index 68b0c93ec6a1..ddc812f40341 100644 --- a/trunk/arch/arm/mach-mmp/include/mach/regs-apbc.h +++ b/trunk/arch/arm/mach-mmp/include/mach/regs-apbc.h @@ -13,101 +13,6 @@ #include -/* - * APB clock register offsets for PXA168 - */ -#define APBC_PXA168_UART1 APBC_REG(0x000) -#define APBC_PXA168_UART2 APBC_REG(0x004) -#define APBC_PXA168_GPIO APBC_REG(0x008) -#define APBC_PXA168_PWM1 APBC_REG(0x00c) -#define APBC_PXA168_PWM2 APBC_REG(0x010) -#define APBC_PXA168_PWM3 APBC_REG(0x014) -#define APBC_PXA168_PWM4 APBC_REG(0x018) -#define APBC_PXA168_RTC APBC_REG(0x028) -#define APBC_PXA168_TWSI0 APBC_REG(0x02c) -#define APBC_PXA168_KPC APBC_REG(0x030) -#define APBC_PXA168_TIMERS APBC_REG(0x034) -#define APBC_PXA168_AIB APBC_REG(0x03c) -#define APBC_PXA168_SW_JTAG APBC_REG(0x040) -#define APBC_PXA168_ONEWIRE APBC_REG(0x048) -#define APBC_PXA168_ASFAR APBC_REG(0x050) -#define APBC_PXA168_ASSAR APBC_REG(0x054) -#define APBC_PXA168_TWSI1 APBC_REG(0x06c) -#define APBC_PXA168_UART3 APBC_REG(0x070) -#define APBC_PXA168_AC97 APBC_REG(0x084) -#define APBC_PXA168_SSP1 APBC_REG(0x81c) -#define APBC_PXA168_SSP2 APBC_REG(0x820) -#define APBC_PXA168_SSP3 APBC_REG(0x84c) -#define APBC_PXA168_SSP4 APBC_REG(0x858) -#define APBC_PXA168_SSP5 APBC_REG(0x85c) - -/* - * APB Clock register offsets for PXA910 - */ -#define APBC_PXA910_UART0 APBC_REG(0x000) -#define APBC_PXA910_UART1 APBC_REG(0x004) -#define APBC_PXA910_GPIO APBC_REG(0x008) -#define APBC_PXA910_PWM1 APBC_REG(0x00c) -#define APBC_PXA910_PWM2 APBC_REG(0x010) -#define APBC_PXA910_PWM3 APBC_REG(0x014) -#define APBC_PXA910_PWM4 APBC_REG(0x018) -#define APBC_PXA910_SSP1 APBC_REG(0x01c) -#define APBC_PXA910_SSP2 APBC_REG(0x020) -#define APBC_PXA910_IPC APBC_REG(0x024) -#define APBC_PXA910_RTC APBC_REG(0x028) -#define APBC_PXA910_TWSI0 APBC_REG(0x02c) -#define APBC_PXA910_KPC APBC_REG(0x030) -#define APBC_PXA910_TIMERS APBC_REG(0x034) -#define APBC_PXA910_TBROT APBC_REG(0x038) -#define APBC_PXA910_AIB APBC_REG(0x03c) -#define APBC_PXA910_SW_JTAG APBC_REG(0x040) -#define APBC_PXA910_TIMERS1 APBC_REG(0x044) -#define APBC_PXA910_ONEWIRE APBC_REG(0x048) -#define APBC_PXA910_SSP3 APBC_REG(0x04c) -#define APBC_PXA910_ASFAR APBC_REG(0x050) -#define APBC_PXA910_ASSAR APBC_REG(0x054) - -/* - * APB Clock register offsets for MMP2 - */ -#define APBC_MMP2_RTC APBC_REG(0x000) -#define APBC_MMP2_TWSI1 APBC_REG(0x004) -#define APBC_MMP2_TWSI2 APBC_REG(0x008) -#define APBC_MMP2_TWSI3 APBC_REG(0x00c) -#define APBC_MMP2_TWSI4 APBC_REG(0x010) -#define APBC_MMP2_ONEWIRE APBC_REG(0x014) -#define APBC_MMP2_KPC APBC_REG(0x018) -#define APBC_MMP2_TB_ROTARY APBC_REG(0x01c) -#define APBC_MMP2_SW_JTAG APBC_REG(0x020) -#define APBC_MMP2_TIMERS APBC_REG(0x024) -#define APBC_MMP2_UART1 APBC_REG(0x02c) -#define APBC_MMP2_UART2 APBC_REG(0x030) -#define APBC_MMP2_UART3 APBC_REG(0x034) -#define APBC_MMP2_GPIO APBC_REG(0x038) -#define APBC_MMP2_PWM0 APBC_REG(0x03c) -#define APBC_MMP2_PWM1 APBC_REG(0x040) -#define APBC_MMP2_PWM2 APBC_REG(0x044) -#define APBC_MMP2_PWM3 APBC_REG(0x048) -#define APBC_MMP2_SSP0 APBC_REG(0x04c) -#define APBC_MMP2_SSP1 APBC_REG(0x050) -#define APBC_MMP2_SSP2 APBC_REG(0x054) -#define APBC_MMP2_SSP3 APBC_REG(0x058) -#define APBC_MMP2_SSP4 APBC_REG(0x05c) -#define APBC_MMP2_SSP5 APBC_REG(0x060) -#define APBC_MMP2_AIB APBC_REG(0x064) -#define APBC_MMP2_ASFAR APBC_REG(0x068) -#define APBC_MMP2_ASSAR APBC_REG(0x06c) -#define APBC_MMP2_USIM APBC_REG(0x070) -#define APBC_MMP2_MPMU APBC_REG(0x074) -#define APBC_MMP2_IPC APBC_REG(0x078) -#define APBC_MMP2_TWSI5 APBC_REG(0x07c) -#define APBC_MMP2_TWSI6 APBC_REG(0x080) -#define APBC_MMP2_TWSI_INTSTS APBC_REG(0x084) -#define APBC_MMP2_UART4 APBC_REG(0x088) -#define APBC_MMP2_RIPC APBC_REG(0x08c) -#define APBC_MMP2_THSENS1 APBC_REG(0x090) /* Thermal Sensor */ -#define APBC_MMP2_THSENS_INTSTS APBC_REG(0x0a4) - /* Common APB clock register bit definitions */ #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ diff --git a/trunk/arch/arm/mach-mmp/include/mach/regs-apmu.h b/trunk/arch/arm/mach-mmp/include/mach/regs-apmu.h index 7af8deb63e83..93c8d0e29bb9 100644 --- a/trunk/arch/arm/mach-mmp/include/mach/regs-apmu.h +++ b/trunk/arch/arm/mach-mmp/include/mach/regs-apmu.h @@ -13,21 +13,6 @@ #include -/* Clock Reset Control */ -#define APMU_IRE APMU_REG(0x048) -#define APMU_LCD APMU_REG(0x04c) -#define APMU_CCIC APMU_REG(0x050) -#define APMU_SDH0 APMU_REG(0x054) -#define APMU_SDH1 APMU_REG(0x058) -#define APMU_USB APMU_REG(0x05c) -#define APMU_NAND APMU_REG(0x060) -#define APMU_DMA APMU_REG(0x064) -#define APMU_GEU APMU_REG(0x068) -#define APMU_BUS APMU_REG(0x06c) -#define APMU_SDH2 APMU_REG(0x0e8) -#define APMU_SDH3 APMU_REG(0x0ec) -#define APMU_ETH APMU_REG(0x0fc) - #define APMU_FNCLK_EN (1 << 4) #define APMU_AXICLK_EN (1 << 3) #define APMU_FNRST_DIS (1 << 1) diff --git a/trunk/arch/arm/mach-mmp/irq.c b/trunk/arch/arm/mach-mmp/irq.c index e60c7d98922b..3c71246cd994 100644 --- a/trunk/arch/arm/mach-mmp/irq.c +++ b/trunk/arch/arm/mach-mmp/irq.c @@ -153,10 +153,8 @@ static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc) status = readl_relaxed(data->reg_status) & ~mask; if (status == 0) break; - n = find_first_bit(&status, BITS_PER_LONG); - while (n < BITS_PER_LONG) { + for_each_set_bit(n, &status, BITS_PER_LONG) { generic_handle_irq(icu_data[i].virq_base + n); - n = find_next_bit(&status, BITS_PER_LONG, n + 1); } } } diff --git a/trunk/arch/arm/mach-mmp/mmp2.c b/trunk/arch/arm/mach-mmp/mmp2.c index c709a24a9d25..3a3768c7a191 100644 --- a/trunk/arch/arm/mach-mmp/mmp2.c +++ b/trunk/arch/arm/mach-mmp/mmp2.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -29,7 +28,6 @@ #include #include "common.h" -#include "clock.h" #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) @@ -98,95 +96,36 @@ void __init mmp2_init_irq(void) mmp2_init_icu(); } -static void sdhc_clk_enable(struct clk *clk) -{ - uint32_t clk_rst; - - clk_rst = __raw_readl(clk->clk_rst); - clk_rst |= clk->enable_val; - __raw_writel(clk_rst, clk->clk_rst); -} - -static void sdhc_clk_disable(struct clk *clk) -{ - uint32_t clk_rst; - - clk_rst = __raw_readl(clk->clk_rst); - clk_rst &= ~clk->enable_val; - __raw_writel(clk_rst, clk->clk_rst); -} - -struct clkops sdhc_clk_ops = { - .enable = sdhc_clk_enable, - .disable = sdhc_clk_disable, -}; - -/* APB peripheral clocks */ -static APBC_CLK(uart1, MMP2_UART1, 1, 26000000); -static APBC_CLK(uart2, MMP2_UART2, 1, 26000000); -static APBC_CLK(uart3, MMP2_UART3, 1, 26000000); -static APBC_CLK(uart4, MMP2_UART4, 1, 26000000); -static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000); -static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000); -static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000); -static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000); -static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); -static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); -static APBC_CLK(gpio, MMP2_GPIO, 0, 26000000); - -static APMU_CLK(nand, NAND, 0xbf, 100000000); -static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops); -static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops); -static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops); -static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops); - -static struct clk_lookup mmp2_clkregs[] = { - INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), - INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), - INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), - INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), - INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), - INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), - INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), - INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), - INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), - INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), - INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), - INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), - INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"), - INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"), - INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"), - INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"), -}; - static int __init mmp2_init(void) { if (cpu_is_mmp2()) { #ifdef CONFIG_CACHE_TAUROS2 - tauros2_init(); + tauros2_init(0); #endif mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(mmp2_addr_map); pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16); - clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs)); + mmp2_clk_init(); } return 0; } postcore_initcall(mmp2_init); +#define APBC_TIMERS APBC_REG(0x024) + static void __init mmp2_timer_init(void) { unsigned long clk_rst; - __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS); + __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); /* * enable bus/functional clock, enable 6.5MHz (divider 4), * release reset */ clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); - __raw_writel(clk_rst, APBC_MMP2_TIMERS); + __raw_writel(clk_rst, APBC_TIMERS); timer_init(IRQ_MMP2_TIMER1); } diff --git a/trunk/arch/arm/mach-mmp/pxa168.c b/trunk/arch/arm/mach-mmp/pxa168.c index 62d787c34475..b7f074f15498 100644 --- a/trunk/arch/arm/mach-mmp/pxa168.c +++ b/trunk/arch/arm/mach-mmp/pxa168.c @@ -18,8 +18,8 @@ #include #include -#include #include +#include #include #include #include @@ -50,62 +50,13 @@ void __init pxa168_init_irq(void) icu_init_irq(); } -/* APB peripheral clocks */ -static APBC_CLK(uart1, PXA168_UART1, 1, 14745600); -static APBC_CLK(uart2, PXA168_UART2, 1, 14745600); -static APBC_CLK(uart3, PXA168_UART3, 1, 14745600); -static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000); -static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000); -static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000); -static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000); -static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000); -static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000); -static APBC_CLK(ssp1, PXA168_SSP1, 4, 0); -static APBC_CLK(ssp2, PXA168_SSP2, 4, 0); -static APBC_CLK(ssp3, PXA168_SSP3, 4, 0); -static APBC_CLK(ssp4, PXA168_SSP4, 4, 0); -static APBC_CLK(ssp5, PXA168_SSP5, 4, 0); -static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000); -static APBC_CLK(keypad, PXA168_KPC, 0, 32000); -static APBC_CLK(rtc, PXA168_RTC, 8, 32768); - -static APMU_CLK(nand, NAND, 0x19b, 156000000); -static APMU_CLK(lcd, LCD, 0x7f, 312000000); -static APMU_CLK(eth, ETH, 0x09, 0); -static APMU_CLK(usb, USB, 0x12, 0); - -/* device and clock bindings */ -static struct clk_lookup pxa168_clkregs[] = { - INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), - INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), - INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), - INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), - INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), - INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL), - INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), - INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), - INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), - INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL), - INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL), - INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL), - INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL), - INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL), - INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), - INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL), - INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), - INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL), - INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"), - INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"), - INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), -}; - static int __init pxa168_init(void) { if (cpu_is_pxa168()) { mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(pxa168_mfp_addr_map); pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); - clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs)); + pxa168_clk_init(); } return 0; @@ -114,6 +65,7 @@ postcore_initcall(pxa168_init); /* system timer - clock enabled, 3.25MHz */ #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) +#define APBC_TIMERS APBC_REG(0x34) static void __init pxa168_timer_init(void) { @@ -121,10 +73,10 @@ static void __init pxa168_timer_init(void) * ourselves instead of using clk_* API. Clock rate is defined * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running */ - __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS); + __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); /* 3.25MHz, bus/functional clock enabled, release reset */ - __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS); + __raw_writel(TIMER_CLK_RST, APBC_TIMERS); timer_init(IRQ_PXA168_TIMER1); } diff --git a/trunk/arch/arm/mach-mmp/pxa910.c b/trunk/arch/arm/mach-mmp/pxa910.c index 6da52e9f2bdc..8b1e16fbb7a5 100644 --- a/trunk/arch/arm/mach-mmp/pxa910.c +++ b/trunk/arch/arm/mach-mmp/pxa910.c @@ -14,10 +14,10 @@ #include #include +#include #include #include #include -#include #include #include #include @@ -25,7 +25,6 @@ #include #include "common.h" -#include "clock.h" #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) @@ -82,44 +81,16 @@ void __init pxa910_init_irq(void) icu_init_irq(); } -/* APB peripheral clocks */ -static APBC_CLK(uart1, PXA910_UART0, 1, 14745600); -static APBC_CLK(uart2, PXA910_UART1, 1, 14745600); -static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000); -static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000); -static APBC_CLK(pwm1, PXA910_PWM1, 1, 13000000); -static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000); -static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000); -static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); -static APBC_CLK(gpio, PXA910_GPIO, 0, 13000000); -static APBC_CLK(rtc, PXA910_RTC, 8, 32768); - -static APMU_CLK(nand, NAND, 0x19b, 156000000); -static APMU_CLK(u2o, USB, 0x1b, 480000000); - -/* device and clock bindings */ -static struct clk_lookup pxa910_clkregs[] = { - INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), - INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), - INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), - INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), - INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL), - INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL), - INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), - INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), - INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), - INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), - INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"), - INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), -}; - static int __init pxa910_init(void) { if (cpu_is_pxa910()) { +#ifdef CONFIG_CACHE_TAUROS2 + tauros2_init(0); +#endif mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(pxa910_mfp_addr_map); pxa_init_dma(IRQ_PXA910_DMA_INT0, 32); - clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs)); + pxa910_clk_init(); } return 0; @@ -128,12 +99,13 @@ postcore_initcall(pxa910_init); /* system timer - clock enabled, 3.25MHz */ #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) +#define APBC_TIMERS APBC_REG(0x34) static void __init pxa910_timer_init(void) { /* reset and configure */ - __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS); - __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS); + __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); + __raw_writel(TIMER_CLK_RST, APBC_TIMERS); timer_init(IRQ_PXA910_AP1_TIMER1); } diff --git a/trunk/arch/arm/mach-msm/Kconfig b/trunk/arch/arm/mach-msm/Kconfig index 1cd40ad301d3..b2740c800e8c 100644 --- a/trunk/arch/arm/mach-msm/Kconfig +++ b/trunk/arch/arm/mach-msm/Kconfig @@ -38,8 +38,6 @@ config ARCH_QSD8X50 config ARCH_MSM8X60 bool "MSM8X60" - select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \ - && !MACH_MSM8X60_FFA) select ARCH_MSM_SCORPIONMP select ARM_GIC select CPU_V7 @@ -47,16 +45,17 @@ config ARCH_MSM8X60 select GPIO_MSM_V2 select MSM_GPIOMUX select MSM_SCM if SMP + select USE_OF config ARCH_MSM8960 bool "MSM8960" select ARCH_MSM_SCORPIONMP - select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3) select ARM_GIC select CPU_V7 select MSM_V2_TLMM select MSM_GPIOMUX select MSM_SCM if SMP + select USE_OF endchoice @@ -112,42 +111,6 @@ config MACH_QSD8X50A_ST1_5 help Support for the Qualcomm ST1.5. -config MACH_MSM8X60_RUMI3 - depends on ARCH_MSM8X60 - bool "MSM8x60 RUMI3" - help - Support for the Qualcomm MSM8x60 RUMI3 emulator. - -config MACH_MSM8X60_SURF - depends on ARCH_MSM8X60 - bool "MSM8x60 SURF" - help - Support for the Qualcomm MSM8x60 SURF eval board. - -config MACH_MSM8X60_SIM - depends on ARCH_MSM8X60 - bool "MSM8x60 Simulator" - help - Support for the Qualcomm MSM8x60 simulator. - -config MACH_MSM8X60_FFA - depends on ARCH_MSM8X60 - bool "MSM8x60 FFA" - help - Support for the Qualcomm MSM8x60 FFA eval board. - -config MACH_MSM8960_SIM - depends on ARCH_MSM8960 - bool "MSM8960 Simulator" - help - Support for the Qualcomm MSM8960 simulator. - -config MACH_MSM8960_RUMI3 - depends on ARCH_MSM8960 - bool "MSM8960 RUMI3" - help - Support for the Qualcomm MSM8960 RUMI3 emulator. - endmenu config MSM_SMD_PKG3 diff --git a/trunk/arch/arm/mach-msm/Makefile b/trunk/arch/arm/mach-msm/Makefile index 4ad3969b9881..17519faf082f 100644 --- a/trunk/arch/arm/mach-msm/Makefile +++ b/trunk/arch/arm/mach-msm/Makefile @@ -1,11 +1,11 @@ -obj-y += io.o idle.o timer.o +obj-y += io.o timer.o obj-y += clock.o obj-$(CONFIG_DEBUG_FS) += clock-debug.o obj-$(CONFIG_MSM_VIC) += irq-vic.o obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o -obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o +obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o obj-$(CONFIG_ARCH_MSM7X30) += dma.o obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o @@ -25,8 +25,8 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o b obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o -obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o -obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o +obj-$(CONFIG_ARCH_MSM8X60) += board-dt-8660.o +obj-$(CONFIG_ARCH_MSM8960) += board-dt-8960.o obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o diff --git a/trunk/arch/arm/mach-msm/acpuclock-arm11.c b/trunk/arch/arm/mach-msm/acpuclock-arm11.c deleted file mode 100644 index 805d4ee53f7e..000000000000 --- a/trunk/arch/arm/mach-msm/acpuclock-arm11.c +++ /dev/null @@ -1,525 +0,0 @@ -/* arch/arm/mach-msm/acpuclock.c - * - * MSM architecture clock driver - * - * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2007 QUALCOMM Incorporated - * Author: San Mehat - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "proc_comm.h" -#include "acpuclock.h" - - -#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100) -#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104) -#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124) - -/* - * ARM11 clock configuration for specific ACPU speeds - */ - -#define ACPU_PLL_TCXO -1 -#define ACPU_PLL_0 0 -#define ACPU_PLL_1 1 -#define ACPU_PLL_2 2 -#define ACPU_PLL_3 3 - -#define PERF_SWITCH_DEBUG 0 -#define PERF_SWITCH_STEP_DEBUG 0 - -struct clock_state -{ - struct clkctl_acpu_speed *current_speed; - struct mutex lock; - uint32_t acpu_switch_time_us; - uint32_t max_speed_delta_khz; - uint32_t vdd_switch_time_us; - unsigned long power_collapse_khz; - unsigned long wait_for_irq_khz; -}; - -static struct clk *ebi1_clk; -static struct clock_state drv_state = { 0 }; - -static void __init acpuclk_init(void); - -/* MSM7201A Levels 3-6 all correspond to 1.2V, level 7 corresponds to 1.325V. */ -enum { - VDD_0 = 0, - VDD_1 = 1, - VDD_2 = 2, - VDD_3 = 3, - VDD_4 = 3, - VDD_5 = 3, - VDD_6 = 3, - VDD_7 = 7, - VDD_END -}; - -struct clkctl_acpu_speed { - unsigned int a11clk_khz; - int pll; - unsigned int a11clk_src_sel; - unsigned int a11clk_src_div; - unsigned int ahbclk_khz; - unsigned int ahbclk_div; - int vdd; - unsigned int axiclk_khz; - unsigned long lpj; /* loops_per_jiffy */ -/* Index in acpu_freq_tbl[] for steppings. */ - short down; - short up; -}; - -/* - * ACPU speed table. Complete table is shown but certain speeds are commented - * out to optimized speed switching. Initialize loops_per_jiffy to 0. - * - * Table stepping up/down is optimized for 256mhz jumps while staying on the - * same PLL. - */ -#if (0) -static struct clkctl_acpu_speed acpu_freq_tbl[] = { - { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 8 }, - { 61440, ACPU_PLL_0, 4, 3, 61440, 0, VDD_0, 30720, 0, 0, 8 }, - { 81920, ACPU_PLL_0, 4, 2, 40960, 1, VDD_0, 61440, 0, 0, 8 }, - { 96000, ACPU_PLL_1, 1, 7, 48000, 1, VDD_0, 61440, 0, 0, 9 }, - { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 8 }, - { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 12 }, - { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 11 }, - { 192000, ACPU_PLL_1, 1, 3, 64000, 2, VDD_3, 61440, 0, 0, 12 }, - { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 12 }, - { 256000, ACPU_PLL_1, 1, 2, 128000, 2, VDD_5, 128000, 0, 0, 12 }, - { 264000, ACPU_PLL_2, 2, 3, 88000, 2, VDD_5, 128000, 0, 6, 13 }, - { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 6, 13 }, - { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 5, -1 }, - { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 11, -1 }, - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, -}; -#else /* Table of freq we currently use. */ -static struct clkctl_acpu_speed acpu_freq_tbl[] = { - { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 4 }, - { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 4 }, - { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 6 }, - { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 5 }, - { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 5 }, - { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 3, 7 }, - { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 2, -1 }, - { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 5, -1 }, - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, -}; -#endif - - -#ifdef CONFIG_CPU_FREQ_TABLE -static struct cpufreq_frequency_table freq_table[] = { - { 0, 122880 }, - { 1, 128000 }, - { 2, 245760 }, - { 3, 384000 }, - { 4, 528000 }, - { 5, CPUFREQ_TABLE_END }, -}; -#endif - -static int pc_pll_request(unsigned id, unsigned on) -{ - int res; - on = !!on; - -#if PERF_SWITCH_DEBUG - if (on) - printk(KERN_DEBUG "Enabling PLL %d\n", id); - else - printk(KERN_DEBUG "Disabling PLL %d\n", id); -#endif - - res = msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on); - if (res < 0) - return res; - -#if PERF_SWITCH_DEBUG - if (on) - printk(KERN_DEBUG "PLL %d enabled\n", id); - else - printk(KERN_DEBUG "PLL %d disabled\n", id); -#endif - return res; -} - - -/*---------------------------------------------------------------------------- - * ARM11 'owned' clock control - *---------------------------------------------------------------------------*/ - -unsigned long acpuclk_power_collapse(void) { - int ret = acpuclk_get_rate(); - ret *= 1000; - if (ret > drv_state.power_collapse_khz) - acpuclk_set_rate(drv_state.power_collapse_khz, 1); - return ret; -} - -unsigned long acpuclk_get_wfi_rate(void) -{ - return drv_state.wait_for_irq_khz; -} - -unsigned long acpuclk_wait_for_irq(void) { - int ret = acpuclk_get_rate(); - ret *= 1000; - if (ret > drv_state.wait_for_irq_khz) - acpuclk_set_rate(drv_state.wait_for_irq_khz, 1); - return ret; -} - -static int acpuclk_set_vdd_level(int vdd) -{ - uint32_t current_vdd; - - current_vdd = readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x07; - -#if PERF_SWITCH_DEBUG - printk(KERN_DEBUG "acpuclock: Switching VDD from %u -> %d\n", - current_vdd, vdd); -#endif - writel((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR); - udelay(drv_state.vdd_switch_time_us); - if ((readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) { -#if PERF_SWITCH_DEBUG - printk(KERN_ERR "acpuclock: VDD set failed\n"); -#endif - return -EIO; - } - -#if PERF_SWITCH_DEBUG - printk(KERN_DEBUG "acpuclock: VDD switched\n"); -#endif - return 0; -} - -/* Set proper dividers for the given clock speed. */ -static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) { - uint32_t reg_clkctl, reg_clksel, clk_div; - - /* AHB_CLK_DIV */ - clk_div = (readl(A11S_CLK_SEL_ADDR) >> 1) & 0x03; - /* - * If the new clock divider is higher than the previous, then - * program the divider before switching the clock - */ - if (hunt_s->ahbclk_div > clk_div) { - reg_clksel = readl(A11S_CLK_SEL_ADDR); - reg_clksel &= ~(0x3 << 1); - reg_clksel |= (hunt_s->ahbclk_div << 1); - writel(reg_clksel, A11S_CLK_SEL_ADDR); - } - if ((readl(A11S_CLK_SEL_ADDR) & 0x01) == 0) { - /* SRC0 */ - - /* Program clock source */ - reg_clkctl = readl(A11S_CLK_CNTL_ADDR); - reg_clkctl &= ~(0x07 << 4); - reg_clkctl |= (hunt_s->a11clk_src_sel << 4); - writel(reg_clkctl, A11S_CLK_CNTL_ADDR); - - /* Program clock divider */ - reg_clkctl = readl(A11S_CLK_CNTL_ADDR); - reg_clkctl &= ~0xf; - reg_clkctl |= hunt_s->a11clk_src_div; - writel(reg_clkctl, A11S_CLK_CNTL_ADDR); - - /* Program clock source selection */ - reg_clksel = readl(A11S_CLK_SEL_ADDR); - reg_clksel |= 1; /* CLK_SEL_SRC1NO == SRC1 */ - writel(reg_clksel, A11S_CLK_SEL_ADDR); - } else { - /* SRC1 */ - - /* Program clock source */ - reg_clkctl = readl(A11S_CLK_CNTL_ADDR); - reg_clkctl &= ~(0x07 << 12); - reg_clkctl |= (hunt_s->a11clk_src_sel << 12); - writel(reg_clkctl, A11S_CLK_CNTL_ADDR); - - /* Program clock divider */ - reg_clkctl = readl(A11S_CLK_CNTL_ADDR); - reg_clkctl &= ~(0xf << 8); - reg_clkctl |= (hunt_s->a11clk_src_div << 8); - writel(reg_clkctl, A11S_CLK_CNTL_ADDR); - - /* Program clock source selection */ - reg_clksel = readl(A11S_CLK_SEL_ADDR); - reg_clksel &= ~1; /* CLK_SEL_SRC1NO == SRC0 */ - writel(reg_clksel, A11S_CLK_SEL_ADDR); - } - - /* - * If the new clock divider is lower than the previous, then - * program the divider after switching the clock - */ - if (hunt_s->ahbclk_div < clk_div) { - reg_clksel = readl(A11S_CLK_SEL_ADDR); - reg_clksel &= ~(0x3 << 1); - reg_clksel |= (hunt_s->ahbclk_div << 1); - writel(reg_clksel, A11S_CLK_SEL_ADDR); - } -} - -int acpuclk_set_rate(unsigned long rate, int for_power_collapse) -{ - uint32_t reg_clkctl; - struct clkctl_acpu_speed *cur_s, *tgt_s, *strt_s; - int rc = 0; - unsigned int plls_enabled = 0, pll; - - strt_s = cur_s = drv_state.current_speed; - - WARN_ONCE(cur_s == NULL, "acpuclk_set_rate: not initialized\n"); - if (cur_s == NULL) - return -ENOENT; - - if (rate == (cur_s->a11clk_khz * 1000)) - return 0; - - for (tgt_s = acpu_freq_tbl; tgt_s->a11clk_khz != 0; tgt_s++) { - if (tgt_s->a11clk_khz == (rate / 1000)) - break; - } - - if (tgt_s->a11clk_khz == 0) - return -EINVAL; - - /* Choose the highest speed speed at or below 'rate' with same PLL. */ - if (for_power_collapse && tgt_s->a11clk_khz < cur_s->a11clk_khz) { - while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll) - tgt_s--; - } - - if (strt_s->pll != ACPU_PLL_TCXO) - plls_enabled |= 1 << strt_s->pll; - - if (!for_power_collapse) { - mutex_lock(&drv_state.lock); - if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) { - rc = pc_pll_request(tgt_s->pll, 1); - if (rc < 0) { - pr_err("PLL%d enable failed (%d)\n", - tgt_s->pll, rc); - goto out; - } - plls_enabled |= 1 << tgt_s->pll; - } - /* Increase VDD if needed. */ - if (tgt_s->vdd > cur_s->vdd) { - if ((rc = acpuclk_set_vdd_level(tgt_s->vdd)) < 0) { - printk(KERN_ERR "Unable to switch ACPU vdd\n"); - goto out; - } - } - } - - /* Set wait states for CPU between frequency changes */ - reg_clkctl = readl(A11S_CLK_CNTL_ADDR); - reg_clkctl |= (100 << 16); /* set WT_ST_CNT */ - writel(reg_clkctl, A11S_CLK_CNTL_ADDR); - -#if PERF_SWITCH_DEBUG - printk(KERN_INFO "acpuclock: Switching from ACPU rate %u -> %u\n", - strt_s->a11clk_khz * 1000, tgt_s->a11clk_khz * 1000); -#endif - - while (cur_s != tgt_s) { - /* - * Always jump to target freq if within 256mhz, regulardless of - * PLL. If differnece is greater, use the predefinied - * steppings in the table. - */ - int d = abs((int)(cur_s->a11clk_khz - tgt_s->a11clk_khz)); - if (d > drv_state.max_speed_delta_khz) { - /* Step up or down depending on target vs current. */ - int clk_index = tgt_s->a11clk_khz > cur_s->a11clk_khz ? - cur_s->up : cur_s->down; - if (clk_index < 0) { /* This should not happen. */ - printk(KERN_ERR "cur:%u target: %u\n", - cur_s->a11clk_khz, tgt_s->a11clk_khz); - rc = -EINVAL; - goto out; - } - cur_s = &acpu_freq_tbl[clk_index]; - } else { - cur_s = tgt_s; - } -#if PERF_SWITCH_STEP_DEBUG - printk(KERN_DEBUG "%s: STEP khz = %u, pll = %d\n", - __FUNCTION__, cur_s->a11clk_khz, cur_s->pll); -#endif - if (!for_power_collapse&& cur_s->pll != ACPU_PLL_TCXO - && !(plls_enabled & (1 << cur_s->pll))) { - rc = pc_pll_request(cur_s->pll, 1); - if (rc < 0) { - pr_err("PLL%d enable failed (%d)\n", - cur_s->pll, rc); - goto out; - } - plls_enabled |= 1 << cur_s->pll; - } - - acpuclk_set_div(cur_s); - drv_state.current_speed = cur_s; - /* Re-adjust lpj for the new clock speed. */ - loops_per_jiffy = cur_s->lpj; - udelay(drv_state.acpu_switch_time_us); - } - - /* Nothing else to do for power collapse. */ - if (for_power_collapse) - return 0; - - /* Disable PLLs we are not using anymore. */ - plls_enabled &= ~(1 << tgt_s->pll); - for (pll = ACPU_PLL_0; pll <= ACPU_PLL_2; pll++) - if (plls_enabled & (1 << pll)) { - rc = pc_pll_request(pll, 0); - if (rc < 0) { - pr_err("PLL%d disable failed (%d)\n", pll, rc); - goto out; - } - } - - /* Change the AXI bus frequency if we can. */ - if (strt_s->axiclk_khz != tgt_s->axiclk_khz) { - rc = clk_set_rate(ebi1_clk, tgt_s->axiclk_khz * 1000); - if (rc < 0) - pr_err("Setting AXI min rate failed!\n"); - } - - /* Drop VDD level if we can. */ - if (tgt_s->vdd < strt_s->vdd) { - if (acpuclk_set_vdd_level(tgt_s->vdd) < 0) - printk(KERN_ERR "acpuclock: Unable to drop ACPU vdd\n"); - } - -#if PERF_SWITCH_DEBUG - printk(KERN_DEBUG "%s: ACPU speed change complete\n", __FUNCTION__); -#endif -out: - if (!for_power_collapse) - mutex_unlock(&drv_state.lock); - return rc; -} - -static void __init acpuclk_init(void) -{ - struct clkctl_acpu_speed *speed; - uint32_t div, sel; - int rc; - - /* - * Determine the rate of ACPU clock - */ - - if (!(readl(A11S_CLK_SEL_ADDR) & 0x01)) { /* CLK_SEL_SRC1N0 */ - /* CLK_SRC0_SEL */ - sel = (readl(A11S_CLK_CNTL_ADDR) >> 12) & 0x7; - /* CLK_SRC0_DIV */ - div = (readl(A11S_CLK_CNTL_ADDR) >> 8) & 0x0f; - } else { - /* CLK_SRC1_SEL */ - sel = (readl(A11S_CLK_CNTL_ADDR) >> 4) & 0x07; - /* CLK_SRC1_DIV */ - div = readl(A11S_CLK_CNTL_ADDR) & 0x0f; - } - - for (speed = acpu_freq_tbl; speed->a11clk_khz != 0; speed++) { - if (speed->a11clk_src_sel == sel - && (speed->a11clk_src_div == div)) - break; - } - if (speed->a11clk_khz == 0) { - printk(KERN_WARNING "Warning - ACPU clock reports invalid speed\n"); - return; - } - - drv_state.current_speed = speed; - - rc = clk_set_rate(ebi1_clk, speed->axiclk_khz * 1000); - if (rc < 0) - pr_err("Setting AXI min rate failed!\n"); - - printk(KERN_INFO "ACPU running at %d KHz\n", speed->a11clk_khz); -} - -unsigned long acpuclk_get_rate(void) -{ - WARN_ONCE(drv_state.current_speed == NULL, - "acpuclk_get_rate: not initialized\n"); - if (drv_state.current_speed) - return drv_state.current_speed->a11clk_khz; - else - return 0; -} - -uint32_t acpuclk_get_switch_time(void) -{ - return drv_state.acpu_switch_time_us; -} - -/*---------------------------------------------------------------------------- - * Clock driver initialization - *---------------------------------------------------------------------------*/ - -/* Initialize the lpj field in the acpu_freq_tbl. */ -static void __init lpj_init(void) -{ - int i; - const struct clkctl_acpu_speed *base_clk = drv_state.current_speed; - for (i = 0; acpu_freq_tbl[i].a11clk_khz; i++) { - acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy, - base_clk->a11clk_khz, - acpu_freq_tbl[i].a11clk_khz); - } -} - -void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata) -{ - pr_info("acpu_clock_init()\n"); - - ebi1_clk = clk_get(NULL, "ebi1_clk"); - - mutex_init(&drv_state.lock); - drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us; - drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz; - drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us; - drv_state.power_collapse_khz = clkdata->power_collapse_khz; - drv_state.wait_for_irq_khz = clkdata->wait_for_irq_khz; - acpuclk_init(); - lpj_init(); -#ifdef CONFIG_CPU_FREQ_TABLE - cpufreq_frequency_table_get_attr(freq_table, smp_processor_id()); -#endif -} diff --git a/trunk/arch/arm/mach-msm/acpuclock.h b/trunk/arch/arm/mach-msm/acpuclock.h deleted file mode 100644 index 415de2eb9a5e..000000000000 --- a/trunk/arch/arm/mach-msm/acpuclock.h +++ /dev/null @@ -1,32 +0,0 @@ -/* arch/arm/mach-msm/acpuclock.h - * - * MSM architecture clock driver header - * - * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2007 QUALCOMM Incorporated - * Author: San Mehat - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ARCH_ARM_MACH_MSM_ACPUCLOCK_H -#define __ARCH_ARM_MACH_MSM_ACPUCLOCK_H - -int acpuclk_set_rate(unsigned long rate, int for_power_collapse); -unsigned long acpuclk_get_rate(void); -uint32_t acpuclk_get_switch_time(void); -unsigned long acpuclk_wait_for_irq(void); -unsigned long acpuclk_power_collapse(void); -unsigned long acpuclk_get_wfi_rate(void); - - -#endif - diff --git a/trunk/arch/arm/mach-msm/board-dt-8660.c b/trunk/arch/arm/mach-msm/board-dt-8660.c new file mode 100644 index 000000000000..e5643f629dcd --- /dev/null +++ b/trunk/arch/arm/mach-msm/board-dt-8660.c @@ -0,0 +1,65 @@ +/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include "common.h" +#include "core.h" + +static const struct of_device_id msm_dt_gic_match[] __initconst = { + { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init }, + {} +}; + +static void __init msm8x60_init_irq(void) +{ + of_irq_init(msm_dt_gic_match); +} + +static void __init msm8x60_init_late(void) +{ + smd_debugfs_init(); +} + +static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = { + {} +}; + +static void __init msm8x60_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + msm_auxdata_lookup, NULL); +} + +static const char *msm8x60_fluid_match[] __initdata = { + "qcom,msm8660-fluid", + "qcom,msm8660-surf", + NULL +}; + +DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") + .smp = smp_ops(msm_smp_ops), + .map_io = msm_map_msm8x60_io, + .init_irq = msm8x60_init_irq, + .handle_irq = gic_handle_irq, + .init_machine = msm8x60_dt_init, + .init_late = msm8x60_init_late, + .timer = &msm_dt_timer, + .dt_compat = msm8x60_fluid_match, +MACHINE_END diff --git a/trunk/arch/arm/mach-msm/board-dt-8960.c b/trunk/arch/arm/mach-msm/board-dt-8960.c new file mode 100644 index 000000000000..139d61bbc8e7 --- /dev/null +++ b/trunk/arch/arm/mach-msm/board-dt-8960.c @@ -0,0 +1,51 @@ +/* Copyright (c) 2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include +#include + +#include "common.h" +#include "core.h" + +static const struct of_device_id msm_dt_gic_match[] __initconst = { + { .compatible = "qcom,msm-qgic2", .data = gic_of_init }, + { } +}; + +static void __init msm_dt_init_irq(void) +{ + of_irq_init(msm_dt_gic_match); +} + +static void __init msm_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char * const msm8960_dt_match[] __initconst = { + "qcom,msm8960-cdp", + NULL +}; + +DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)") + .smp = smp_ops(msm_smp_ops), + .map_io = msm_map_msm8960_io, + .init_irq = msm_dt_init_irq, + .timer = &msm_dt_timer, + .init_machine = msm_dt_init, + .dt_compat = msm8960_dt_match, + .handle_irq = gic_handle_irq, +MACHINE_END diff --git a/trunk/arch/arm/mach-msm/board-halibut.c b/trunk/arch/arm/mach-msm/board-halibut.c index 4fa3e99d9a62..6ce542e2e21c 100644 --- a/trunk/arch/arm/mach-msm/board-halibut.c +++ b/trunk/arch/arm/mach-msm/board-halibut.c @@ -36,6 +36,7 @@ #include #include "devices.h" +#include "common.h" static struct resource smc91x_resources[] = { [0] = { @@ -66,8 +67,6 @@ static struct platform_device *devices[] __initdata = { &smc91x_device, }; -extern struct sys_timer msm_timer; - static void __init halibut_init_early(void) { arch_ioremap_caller = __msm_ioremap_caller; @@ -107,5 +106,5 @@ MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)") .init_irq = halibut_init_irq, .init_machine = halibut_init, .init_late = halibut_init_late, - .timer = &msm_timer, + .timer = &msm7x01_timer, MACHINE_END diff --git a/trunk/arch/arm/mach-msm/board-mahimahi.c b/trunk/arch/arm/mach-msm/board-mahimahi.c index cf1f89a5dc62..df00bc03ce74 100644 --- a/trunk/arch/arm/mach-msm/board-mahimahi.c +++ b/trunk/arch/arm/mach-msm/board-mahimahi.c @@ -30,7 +30,6 @@ #include #include -#include #include "board-mahimahi.h" #include "devices.h" diff --git a/trunk/arch/arm/mach-msm/board-msm7x27.c b/trunk/arch/arm/mach-msm/board-msm7x27.c deleted file mode 100644 index 451ab1d43c92..000000000000 --- a/trunk/arch/arm/mach-msm/board-msm7x27.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. - * Author: Brian Swetland - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_CACHE_L2X0 -#include -#endif - -#include -#include -#include -#include - -#include -#include - -#include "devices.h" -#include "socinfo.h" -#include "clock.h" - -static struct resource smc91x_resources[] = { - [0] = { - .start = 0x9C004300, - .end = 0x9C0043ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = MSM_GPIO_TO_INT(132), - .end = MSM_GPIO_TO_INT(132), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; - -static struct platform_device *devices[] __initdata = { - &msm_device_uart3, - &msm_device_smd, - &msm_device_dmov, - &msm_device_nand, - &smc91x_device, -}; - -extern struct sys_timer msm_timer; - -static void __init msm7x2x_init_irq(void) -{ - msm_init_irq(); -} - -static void __init msm7x2x_init(void) -{ - if (socinfo_init() < 0) - BUG(); - - if (machine_is_msm7x25_ffa() || machine_is_msm7x27_ffa()) { - smc91x_resources[0].start = 0x98000300; - smc91x_resources[0].end = 0x980003ff; - smc91x_resources[1].start = MSM_GPIO_TO_INT(85); - smc91x_resources[1].end = MSM_GPIO_TO_INT(85); - if (gpio_tlmm_config(GPIO_CFG(85, 0, - GPIO_INPUT, - GPIO_PULL_DOWN, - GPIO_2MA), - GPIO_ENABLE)) { - printk(KERN_ERR - "%s: Err: Config GPIO-85 INT\n", - __func__); - } - } - - platform_add_devices(devices, ARRAY_SIZE(devices)); -} - -static void __init msm7x2x_map_io(void) -{ - msm_map_common_io(); - /* Technically dependent on the SoC but using machine_is - * macros since socinfo is not available this early and there - * are plans to restructure the code which will eliminate the - * need for socinfo. - */ - if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) - msm_clock_init(msm_clocks_7x27, msm_num_clocks_7x27); - - if (machine_is_msm7x25_surf() || machine_is_msm7x25_ffa()) - msm_clock_init(msm_clocks_7x25, msm_num_clocks_7x25); - -#ifdef CONFIG_CACHE_L2X0 - if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) { - /* 7x27 has 256KB L2 cache: - 64Kb/Way and 4-Way Associativity; - R/W latency: 3 cycles; - evmon/parity/share disabled. */ - l2x0_init(MSM_L2CC_BASE, 0x00068012, 0xfe000000); - } -#endif -} - -static void __init msm7x2x_init_late(void) -{ - smd_debugfs_init(); -} - -MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF") - .atag_offset = 0x100, - .map_io = msm7x2x_map_io, - .init_irq = msm7x2x_init_irq, - .init_machine = msm7x2x_init, - .init_late = msm7x2x_init_late, - .timer = &msm_timer, -MACHINE_END - -MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA") - .atag_offset = 0x100, - .map_io = msm7x2x_map_io, - .init_irq = msm7x2x_init_irq, - .init_machine = msm7x2x_init, - .init_late = msm7x2x_init_late, - .timer = &msm_timer, -MACHINE_END - -MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF") - .atag_offset = 0x100, - .map_io = msm7x2x_map_io, - .init_irq = msm7x2x_init_irq, - .init_machine = msm7x2x_init, - .init_late = msm7x2x_init_late, - .timer = &msm_timer, -MACHINE_END - -MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA") - .atag_offset = 0x100, - .map_io = msm7x2x_map_io, - .init_irq = msm7x2x_init_irq, - .init_machine = msm7x2x_init, - .init_late = msm7x2x_init_late, - .timer = &msm_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-msm/board-msm7x30.c b/trunk/arch/arm/mach-msm/board-msm7x30.c index a5001378135d..effa6f4336c7 100644 --- a/trunk/arch/arm/mach-msm/board-msm7x30.c +++ b/trunk/arch/arm/mach-msm/board-msm7x30.c @@ -38,8 +38,7 @@ #include "devices.h" #include "gpiomux.h" #include "proc_comm.h" - -extern struct sys_timer msm_timer; +#include "common.h" static void __init msm7x30_fixup(struct tag *tag, char **cmdline, struct meminfo *mi) @@ -132,7 +131,7 @@ MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, .init_late = msm7x30_init_late, - .timer = &msm_timer, + .timer = &msm7x30_timer, MACHINE_END MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") @@ -143,7 +142,7 @@ MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, .init_late = msm7x30_init_late, - .timer = &msm_timer, + .timer = &msm7x30_timer, MACHINE_END MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") @@ -154,5 +153,5 @@ MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, .init_late = msm7x30_init_late, - .timer = &msm_timer, + .timer = &msm7x30_timer, MACHINE_END diff --git a/trunk/arch/arm/mach-msm/board-msm8960.c b/trunk/arch/arm/mach-msm/board-msm8960.c deleted file mode 100644 index 65f4a1daa2e5..000000000000 --- a/trunk/arch/arm/mach-msm/board-msm8960.c +++ /dev/null @@ -1,122 +0,0 @@ -/* Copyright (c) 2011, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - * - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -#include "devices.h" - -static void __init msm8960_fixup(struct tag *tag, char **cmdline, - struct meminfo *mi) -{ - for (; tag->hdr.size; tag = tag_next(tag)) - if (tag->hdr.tag == ATAG_MEM && - tag->u.mem.start == 0x40200000) { - tag->u.mem.start = 0x40000000; - tag->u.mem.size += SZ_2M; - } -} - -static void __init msm8960_reserve(void) -{ - memblock_remove(0x40000000, SZ_2M); -} - -static void __init msm8960_map_io(void) -{ - msm_map_msm8960_io(); -} - -static void __init msm8960_init_irq(void) -{ - unsigned int i; - gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, - (void *)MSM_QGIC_CPU_BASE); - - /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ - writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); - - if (machine_is_msm8960_rumi3()) - writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); - - /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet - * as they are configured as level, which does not play nice with - * handle_percpu_irq. - */ - for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { - if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) - irq_set_handler(i, handle_percpu_irq); - } -} - -static struct platform_device *sim_devices[] __initdata = { - &msm8960_device_uart_gsbi2, -}; - -static struct platform_device *rumi3_devices[] __initdata = { - &msm8960_device_uart_gsbi5, -}; - -static void __init msm8960_sim_init(void) -{ - platform_add_devices(sim_devices, ARRAY_SIZE(sim_devices)); -} - -static void __init msm8960_rumi3_init(void) -{ - platform_add_devices(rumi3_devices, ARRAY_SIZE(rumi3_devices)); -} - -static void __init msm8960_init_late(void) -{ - smd_debugfs_init(); -} - -MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR") - .fixup = msm8960_fixup, - .reserve = msm8960_reserve, - .map_io = msm8960_map_io, - .init_irq = msm8960_init_irq, - .timer = &msm_timer, - .handle_irq = gic_handle_irq, - .init_machine = msm8960_sim_init, - .init_late = msm8960_init_late, -MACHINE_END - -MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3") - .fixup = msm8960_fixup, - .reserve = msm8960_reserve, - .map_io = msm8960_map_io, - .init_irq = msm8960_init_irq, - .timer = &msm_timer, - .handle_irq = gic_handle_irq, - .init_machine = msm8960_rumi3_init, - .init_late = msm8960_init_late, -MACHINE_END - diff --git a/trunk/arch/arm/mach-msm/board-msm8x60.c b/trunk/arch/arm/mach-msm/board-msm8x60.c deleted file mode 100644 index e37a724cd1eb..000000000000 --- a/trunk/arch/arm/mach-msm/board-msm8x60.c +++ /dev/null @@ -1,166 +0,0 @@ -/* Copyright (c) 2010, 2011, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -static void __init msm8x60_fixup(struct tag *tag, char **cmdline, - struct meminfo *mi) -{ - for (; tag->hdr.size; tag = tag_next(tag)) - if (tag->hdr.tag == ATAG_MEM && - tag->u.mem.start == 0x40200000) { - tag->u.mem.start = 0x40000000; - tag->u.mem.size += SZ_2M; - } -} - -static void __init msm8x60_reserve(void) -{ - memblock_remove(0x40000000, SZ_2M); -} - -static void __init msm8x60_map_io(void) -{ - msm_map_msm8x60_io(); -} - -#ifdef CONFIG_OF -static struct of_device_id msm_dt_gic_match[] __initdata = { - { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init }, - {} -}; -#endif - -static void __init msm8x60_init_irq(void) -{ - if (!of_have_populated_dt()) - gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, - (void *)MSM_QGIC_CPU_BASE); -#ifdef CONFIG_OF - else - of_irq_init(msm_dt_gic_match); -#endif - - /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ - writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); - - /* RUMI does not adhere to GIC spec by enabling STIs by default. - * Enable/clear is supposed to be RO for STIs, but is RW on RUMI. - */ - if (!machine_is_msm8x60_sim()) - writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); -} - -static void __init msm8x60_init(void) -{ -} - -static void __init msm8x60_init_late(void) -{ - smd_debugfs_init(); -} - -#ifdef CONFIG_OF -static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = { - {} -}; - -static void __init msm8x60_dt_init(void) -{ - if (of_machine_is_compatible("qcom,msm8660-surf")) { - printk(KERN_INFO "Init surf UART registers\n"); - msm8x60_init_uart12dm(); - } - - of_platform_populate(NULL, of_default_bus_match_table, - msm_auxdata_lookup, NULL); -} - -static const char *msm8x60_fluid_match[] __initdata = { - "qcom,msm8660-fluid", - "qcom,msm8660-surf", - NULL -}; -#endif /* CONFIG_OF */ - -MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3") - .fixup = msm8x60_fixup, - .reserve = msm8x60_reserve, - .map_io = msm8x60_map_io, - .init_irq = msm8x60_init_irq, - .handle_irq = gic_handle_irq, - .init_machine = msm8x60_init, - .init_late = msm8x60_init_late, - .timer = &msm_timer, -MACHINE_END - -MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF") - .fixup = msm8x60_fixup, - .reserve = msm8x60_reserve, - .map_io = msm8x60_map_io, - .init_irq = msm8x60_init_irq, - .handle_irq = gic_handle_irq, - .init_machine = msm8x60_init, - .init_late = msm8x60_init_late, - .timer = &msm_timer, -MACHINE_END - -MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR") - .fixup = msm8x60_fixup, - .reserve = msm8x60_reserve, - .map_io = msm8x60_map_io, - .init_irq = msm8x60_init_irq, - .handle_irq = gic_handle_irq, - .init_machine = msm8x60_init, - .init_late = msm8x60_init_late, - .timer = &msm_timer, -MACHINE_END - -MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA") - .fixup = msm8x60_fixup, - .reserve = msm8x60_reserve, - .map_io = msm8x60_map_io, - .init_irq = msm8x60_init_irq, - .handle_irq = gic_handle_irq, - .init_machine = msm8x60_init, - .init_late = msm8x60_init_late, - .timer = &msm_timer, -MACHINE_END - -#ifdef CONFIG_OF -/* TODO: General device tree support for all MSM. */ -DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") - .map_io = msm8x60_map_io, - .init_irq = msm8x60_init_irq, - .init_machine = msm8x60_dt_init, - .init_late = msm8x60_init_late, - .timer = &msm_timer, - .dt_compat = msm8x60_fluid_match, -MACHINE_END -#endif /* CONFIG_OF */ diff --git a/trunk/arch/arm/mach-msm/board-qsd8x50.c b/trunk/arch/arm/mach-msm/board-qsd8x50.c index c8fe0edb9761..b16b71abf5f6 100644 --- a/trunk/arch/arm/mach-msm/board-qsd8x50.c +++ b/trunk/arch/arm/mach-msm/board-qsd8x50.c @@ -35,8 +35,7 @@ #include #include "devices.h" - -extern struct sys_timer msm_timer; +#include "common.h" static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300; static const unsigned qsd8x50_surf_smc91x_gpio __initdata = 156; @@ -201,7 +200,7 @@ MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") .init_irq = qsd8x50_init_irq, .init_machine = qsd8x50_init, .init_late = qsd8x50_init_late, - .timer = &msm_timer, + .timer = &qsd8x50_timer, MACHINE_END MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") @@ -210,5 +209,5 @@ MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") .init_irq = qsd8x50_init_irq, .init_machine = qsd8x50_init, .init_late = qsd8x50_init_late, - .timer = &msm_timer, + .timer = &qsd8x50_timer, MACHINE_END diff --git a/trunk/arch/arm/mach-msm/board-sapphire.c b/trunk/arch/arm/mach-msm/board-sapphire.c index 2e569ab10eef..b7b0fc7e3278 100644 --- a/trunk/arch/arm/mach-msm/board-sapphire.c +++ b/trunk/arch/arm/mach-msm/board-sapphire.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include diff --git a/trunk/arch/arm/mach-msm/board-trout.c b/trunk/arch/arm/mach-msm/board-trout.c index bbe13f12fa01..4ba0800e243e 100644 --- a/trunk/arch/arm/mach-msm/board-trout.c +++ b/trunk/arch/arm/mach-msm/board-trout.c @@ -31,6 +31,7 @@ #include "devices.h" #include "board-trout.h" +#include "common.h" extern int trout_init_mmc(unsigned int); @@ -42,8 +43,6 @@ static struct platform_device *devices[] __initdata = { &msm_device_i2c, }; -extern struct sys_timer msm_timer; - static void __init trout_init_early(void) { arch_ioremap_caller = __msm_ioremap_caller; @@ -111,5 +110,5 @@ MACHINE_START(TROUT, "HTC Dream") .init_irq = trout_init_irq, .init_machine = trout_init, .init_late = trout_init_late, - .timer = &msm_timer, + .timer = &msm7x01_timer, MACHINE_END diff --git a/trunk/arch/arm/mach-msm/clock-pcom.c b/trunk/arch/arm/mach-msm/clock-pcom.c index 63b711311086..a52c970df157 100644 --- a/trunk/arch/arm/mach-msm/clock-pcom.c +++ b/trunk/arch/arm/mach-msm/clock-pcom.c @@ -25,7 +25,7 @@ /* * glue for the proc_comm interface */ -int pc_clk_enable(unsigned id) +static int pc_clk_enable(unsigned id) { int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL); if (rc < 0) @@ -34,7 +34,7 @@ int pc_clk_enable(unsigned id) return (int)id < 0 ? -EINVAL : 0; } -void pc_clk_disable(unsigned id) +static void pc_clk_disable(unsigned id) { msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL); } @@ -54,7 +54,7 @@ int pc_clk_reset(unsigned id, enum clk_reset_action action) return (int)id < 0 ? -EINVAL : 0; } -int pc_clk_set_rate(unsigned id, unsigned rate) +static int pc_clk_set_rate(unsigned id, unsigned rate) { /* The rate _might_ be rounded off to the nearest KHz value by the * remote function. So a return value of 0 doesn't necessarily mean @@ -67,7 +67,7 @@ int pc_clk_set_rate(unsigned id, unsigned rate) return (int)id < 0 ? -EINVAL : 0; } -int pc_clk_set_min_rate(unsigned id, unsigned rate) +static int pc_clk_set_min_rate(unsigned id, unsigned rate) { int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate); if (rc < 0) @@ -76,7 +76,7 @@ int pc_clk_set_min_rate(unsigned id, unsigned rate) return (int)id < 0 ? -EINVAL : 0; } -int pc_clk_set_max_rate(unsigned id, unsigned rate) +static int pc_clk_set_max_rate(unsigned id, unsigned rate) { int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate); if (rc < 0) @@ -85,7 +85,7 @@ int pc_clk_set_max_rate(unsigned id, unsigned rate) return (int)id < 0 ? -EINVAL : 0; } -int pc_clk_set_flags(unsigned id, unsigned flags) +static int pc_clk_set_flags(unsigned id, unsigned flags) { int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags); if (rc < 0) @@ -94,7 +94,7 @@ int pc_clk_set_flags(unsigned id, unsigned flags) return (int)id < 0 ? -EINVAL : 0; } -unsigned pc_clk_get_rate(unsigned id) +static unsigned pc_clk_get_rate(unsigned id) { if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL)) return 0; @@ -102,7 +102,7 @@ unsigned pc_clk_get_rate(unsigned id) return id; } -unsigned pc_clk_is_enabled(unsigned id) +static unsigned pc_clk_is_enabled(unsigned id) { if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL)) return 0; @@ -110,7 +110,7 @@ unsigned pc_clk_is_enabled(unsigned id) return id; } -long pc_clk_round_rate(unsigned id, unsigned rate) +static long pc_clk_round_rate(unsigned id, unsigned rate) { /* Not really supported; pc_clk_set_rate() does rounding on it's own. */ diff --git a/trunk/arch/arm/mach-msm/common.h b/trunk/arch/arm/mach-msm/common.h new file mode 100644 index 000000000000..d68e5d7854f5 --- /dev/null +++ b/trunk/arch/arm/mach-msm/common.h @@ -0,0 +1,30 @@ +/* Copyright (c) 2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __MACH_COMMON_H +#define __MACH_COMMON_H + +extern struct sys_timer msm7x01_timer; +extern struct sys_timer msm7x30_timer; +extern struct sys_timer msm_dt_timer; +extern struct sys_timer qsd8x50_timer; + +extern void msm_map_common_io(void); +extern void msm_map_msm7x30_io(void); +extern void msm_map_msm8x60_io(void); +extern void msm_map_msm8960_io(void); +extern void msm_map_qsd8x50_io(void); + +extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size, + unsigned int mtype, void *caller); + + +#endif diff --git a/trunk/arch/arm/mach-msm/core.h b/trunk/arch/arm/mach-msm/core.h new file mode 100644 index 000000000000..a9bab53dddf4 --- /dev/null +++ b/trunk/arch/arm/mach-msm/core.h @@ -0,0 +1,2 @@ +extern struct smp_operations msm_smp_ops; +extern void msm_cpu_die(unsigned int cpu); diff --git a/trunk/arch/arm/mach-msm/devices-msm8960.c b/trunk/arch/arm/mach-msm/devices-msm8960.c deleted file mode 100644 index d9e1f26475de..000000000000 --- a/trunk/arch/arm/mach-msm/devices-msm8960.c +++ /dev/null @@ -1,85 +0,0 @@ -/* Copyright (c) 2011, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - */ - -#include -#include - -#include -#include -#include - -#include "devices.h" - -#define MSM_GSBI2_PHYS 0x16100000 -#define MSM_UART2DM_PHYS (MSM_GSBI2_PHYS + 0x40000) - -#define MSM_GSBI5_PHYS 0x16400000 -#define MSM_UART5DM_PHYS (MSM_GSBI5_PHYS + 0x40000) - -static struct resource resources_uart_gsbi2[] = { - { - .start = GSBI2_UARTDM_IRQ, - .end = GSBI2_UARTDM_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .start = MSM_UART2DM_PHYS, - .end = MSM_UART2DM_PHYS + PAGE_SIZE - 1, - .name = "uart_resource", - .flags = IORESOURCE_MEM, - }, - { - .start = MSM_GSBI2_PHYS, - .end = MSM_GSBI2_PHYS + PAGE_SIZE - 1, - .name = "gsbi_resource", - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device msm8960_device_uart_gsbi2 = { - .name = "msm_serial", - .id = 0, - .num_resources = ARRAY_SIZE(resources_uart_gsbi2), - .resource = resources_uart_gsbi2, -}; - -static struct resource resources_uart_gsbi5[] = { - { - .start = GSBI5_UARTDM_IRQ, - .end = GSBI5_UARTDM_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .start = MSM_UART5DM_PHYS, - .end = MSM_UART5DM_PHYS + PAGE_SIZE - 1, - .name = "uart_resource", - .flags = IORESOURCE_MEM, - }, - { - .start = MSM_GSBI5_PHYS, - .end = MSM_GSBI5_PHYS + PAGE_SIZE - 1, - .name = "gsbi_resource", - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device msm8960_device_uart_gsbi5 = { - .name = "msm_serial", - .id = 0, - .num_resources = ARRAY_SIZE(resources_uart_gsbi5), - .resource = resources_uart_gsbi5, -}; diff --git a/trunk/arch/arm/mach-msm/dma.c b/trunk/arch/arm/mach-msm/dma.c index 02cae5e2951c..354b91d4c3ac 100644 --- a/trunk/arch/arm/mach-msm/dma.c +++ b/trunk/arch/arm/mach-msm/dma.c @@ -223,8 +223,7 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id) PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status); if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) { cmd = list_entry(ready_commands[id].next, typeof(*cmd), list); - list_del(&cmd->list); - list_add_tail(&cmd->list, &active_commands[id]); + list_move_tail(&cmd->list, &active_commands[id]); if (cmd->execute_func) cmd->execute_func(cmd); PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id); diff --git a/trunk/arch/arm/mach-msm/hotplug.c b/trunk/arch/arm/mach-msm/hotplug.c index a446fc14221f..002ac1e47235 100644 --- a/trunk/arch/arm/mach-msm/hotplug.c +++ b/trunk/arch/arm/mach-msm/hotplug.c @@ -13,7 +13,7 @@ #include #include -extern volatile int pen_release; +#include "core.h" static inline void cpu_enter_lowpower(void) { @@ -57,17 +57,12 @@ static inline void platform_do_lowpower(unsigned int cpu) } } -int platform_cpu_kill(unsigned int cpu) -{ - return 1; -} - /* * platform-specific code to shutdown a CPU * * Called with IRQs disabled */ -void platform_cpu_die(unsigned int cpu) +void __ref msm_cpu_die(unsigned int cpu) { /* * we're ready for shutdown now, so do it @@ -81,12 +76,3 @@ void platform_cpu_die(unsigned int cpu) */ cpu_leave_lowpower(); } - -int platform_cpu_disable(unsigned int cpu) -{ - /* - * we don't allow CPU 0 to be shutdown (it is still too special - * e.g. clock tick interrupts) - */ - return cpu == 0 ? -EPERM : 0; -} diff --git a/trunk/arch/arm/mach-msm/idle.c b/trunk/arch/arm/mach-msm/idle.c deleted file mode 100644 index 0c9e13c65743..000000000000 --- a/trunk/arch/arm/mach-msm/idle.c +++ /dev/null @@ -1,49 +0,0 @@ -/* arch/arm/mach-msm/idle.c - * - * Idle processing for MSM7K - work around bugs with SWFI. - * - * Copyright (c) 2007 QUALCOMM Incorporated. - * Copyright (C) 2007 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include - -static void msm_idle(void) -{ -#ifdef CONFIG_MSM7X00A_IDLE - asm volatile ( - - "mrc p15, 0, r1, c1, c0, 0 /* read current CR */ \n\t" - "bic r0, r1, #(1 << 2) /* clear dcache bit */ \n\t" - "bic r0, r0, #(1 << 12) /* clear icache bit */ \n\t" - "mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */ \n\t" - - "mov r0, #0 /* prepare wfi value */ \n\t" - "mcr p15, 0, r0, c7, c10, 0 /* flush the cache */ \n\t" - "mcr p15, 0, r0, c7, c10, 4 /* memory barrier */ \n\t" - "mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */ \n\t" - - "mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */ \n\t" - - : : : "r0","r1" ); -#endif -} - -static int __init msm_idle_init(void) -{ - arm_pm_idle = msm_idle; - return 0; -} - -arch_initcall(msm_idle_init); diff --git a/trunk/arch/arm/mach-msm/include/mach/board.h b/trunk/arch/arm/mach-msm/include/mach/board.h index 435f8edfafd1..0a0c393d8e31 100644 --- a/trunk/arch/arm/mach-msm/include/mach/board.h +++ b/trunk/arch/arm/mach-msm/include/mach/board.h @@ -22,27 +22,14 @@ /* platform device data structures */ -struct msm_acpu_clock_platform_data -{ - uint32_t acpu_switch_time_us; - uint32_t max_speed_delta_khz; - uint32_t vdd_switch_time_us; - unsigned long power_collapse_khz; - unsigned long wait_for_irq_khz; -}; - struct clk_lookup; -extern struct sys_timer msm_timer; - /* common init routines for use by arch/arm/mach-msm/board-*.c */ void __init msm_add_devices(void); -void __init msm_map_common_io(void); void __init msm_init_irq(void); void __init msm_init_gpio(void); void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks); -void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *); int __init msm_add_sdcc(unsigned int controller, struct msm_mmc_platform_data *plat, unsigned int stat_irq, unsigned long stat_irq_flags); diff --git a/trunk/arch/arm/mach-msm/include/mach/gpio.h b/trunk/arch/arm/mach-msm/include/mach/gpio.h deleted file mode 100644 index 40a8c178f10d..000000000000 --- a/trunk/arch/arm/mach-msm/include/mach/gpio.h +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/trunk/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/trunk/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h index 6c4046c21296..67dc0e98b958 100644 --- a/trunk/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h +++ b/trunk/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h @@ -105,11 +105,4 @@ #define MSM_AD5_PHYS 0xAC000000 #define MSM_AD5_SIZE (SZ_1M*13) -#ifndef __ASSEMBLY__ - -extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size, - unsigned int mtype, void *caller); - -#endif - #endif diff --git a/trunk/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/trunk/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h index f944fe65a657..198202c267c8 100644 --- a/trunk/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h +++ b/trunk/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h @@ -100,8 +100,4 @@ #define MSM_HSUSB_PHYS 0xA3600000 #define MSM_HSUSB_SIZE SZ_1K -#ifndef __ASSEMBLY__ -extern void msm_map_msm7x30_io(void); -#endif - #endif diff --git a/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8960.h index a1752c0284fc..9819a556acae 100644 --- a/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8960.h +++ b/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8960.h @@ -46,12 +46,8 @@ #define MSM8960_TMR0_SIZE SZ_4K #ifdef CONFIG_DEBUG_MSM8960_UART -#define MSM_DEBUG_UART_BASE 0xE1040000 +#define MSM_DEBUG_UART_BASE 0xF0040000 #define MSM_DEBUG_UART_PHYS 0x16440000 #endif -#ifndef __ASSEMBLY__ -extern void msm_map_msm8960_io(void); -#endif - #endif diff --git a/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h index da77cc1d545d..0faa894729b7 100644 --- a/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h +++ b/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h @@ -122,8 +122,4 @@ #define MSM_SDC4_PHYS 0xA0600000 #define MSM_SDC4_SIZE SZ_4K -#ifndef __ASSEMBLY__ -extern void msm_map_qsd8x50_io(void); -#endif - #endif diff --git a/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index 5aed57dc808c..c6d38f1d0c98 100644 --- a/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -63,12 +63,8 @@ #define MSM8X60_TMR0_SIZE SZ_4K #ifdef CONFIG_DEBUG_MSM8660_UART -#define MSM_DEBUG_UART_BASE 0xE1040000 +#define MSM_DEBUG_UART_BASE 0xF0040000 #define MSM_DEBUG_UART_PHYS 0x19C40000 #endif -#ifndef __ASSEMBLY__ -extern void msm_map_msm8x60_io(void); -#endif - #endif diff --git a/trunk/arch/arm/mach-msm/include/mach/system.h b/trunk/arch/arm/mach-msm/include/mach/system.h deleted file mode 100644 index f5fb2ec87ffe..000000000000 --- a/trunk/arch/arm/mach-msm/include/mach/system.h +++ /dev/null @@ -1,19 +0,0 @@ -/* arch/arm/mach-msm/include/mach/system.h - * - * Copyright (C) 2007 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* low level hardware reset hook -- for example, hitting the - * PSHOLD line on the PMIC to hard reset the system - */ -extern void (*msm_hw_reset_hook)(void); diff --git a/trunk/arch/arm/mach-msm/io.c b/trunk/arch/arm/mach-msm/io.c index a1e7b1168850..3854f6f20ce2 100644 --- a/trunk/arch/arm/mach-msm/io.c +++ b/trunk/arch/arm/mach-msm/io.c @@ -29,30 +29,32 @@ #include -#define MSM_CHIP_DEVICE(name, chip) { \ +#include "common.h" + +#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \ .virtual = (unsigned long) MSM_##name##_BASE, \ .pfn = __phys_to_pfn(chip##_##name##_PHYS), \ .length = chip##_##name##_SIZE, \ - .type = MT_DEVICE_NONSHARED, \ + .type = mem_type, \ } +#define MSM_DEVICE_TYPE(name, mem_type) \ + MSM_CHIP_DEVICE_TYPE(name, MSM, mem_type) +#define MSM_CHIP_DEVICE(name, chip) \ + MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE) #define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM) -#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \ - || defined(CONFIG_ARCH_MSM7X25) +#if defined(CONFIG_ARCH_MSM7X00A) static struct map_desc msm_io_desc[] __initdata = { - MSM_DEVICE(VIC), - MSM_CHIP_DEVICE(CSR, MSM7X00), - MSM_DEVICE(DMOV), - MSM_CHIP_DEVICE(GPIO1, MSM7X00), - MSM_CHIP_DEVICE(GPIO2, MSM7X00), - MSM_DEVICE(CLK_CTL), + MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED), + MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED), + MSM_DEVICE_TYPE(DMOV, MT_DEVICE_NONSHARED), + MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED), + MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED), + MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED), #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ defined(CONFIG_DEBUG_MSM_UART3) - MSM_DEVICE(DEBUG_UART), -#endif -#ifdef CONFIG_ARCH_MSM7X30 - MSM_DEVICE(GCC), + MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED), #endif { .virtual = (unsigned long) MSM_SHARED_RAM_BASE, diff --git a/trunk/arch/arm/mach-msm/platsmp.c b/trunk/arch/arm/mach-msm/platsmp.c index e012dc8391cf..637021c0d8af 100644 --- a/trunk/arch/arm/mach-msm/platsmp.c +++ b/trunk/arch/arm/mach-msm/platsmp.c @@ -22,23 +22,14 @@ #include #include -#include - #include "scm-boot.h" +#include "core.h" #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 #define SCSS_CPU1CORE_RESET 0xD80 #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 -/* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ -#define GIC_PPI_EDGE_MASK 0xFFFFD7FF - extern void msm_secondary_startup(void); -/* - * control for which core is the next to come out of the secondary - * boot "holding pen". - */ -volatile int pen_release = -1; static DEFINE_SPINLOCK(boot_lock); @@ -48,11 +39,8 @@ static inline int get_core_count(void) return ((read_cpuid_id() >> 4) & 3) + 1; } -void __cpuinit platform_secondary_init(unsigned int cpu) +static void __cpuinit msm_secondary_init(unsigned int cpu) { - /* Configure edge-triggered PPIs */ - writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); - /* * if any interrupts are already enabled for the primary * core (e.g. timer irq), then they will not have been enabled @@ -93,7 +81,7 @@ static __cpuinit void prepare_cold_cpu(unsigned int cpu) "address\n"); } -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; static int cold_boot_done; @@ -153,7 +141,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * does not support the ARM SCU, so just set the possible cpu mask to * NR_CPUS. */ -void __init smp_init_cpus(void) +static void __init msm_smp_init_cpus(void) { unsigned int i, ncores = get_core_count(); @@ -169,6 +157,16 @@ void __init smp_init_cpus(void) set_smp_cross_call(gic_raise_softirq); } -void __init platform_smp_prepare_cpus(unsigned int max_cpus) +static void __init msm_smp_prepare_cpus(unsigned int max_cpus) { } + +struct smp_operations msm_smp_ops __initdata = { + .smp_init_cpus = msm_smp_init_cpus, + .smp_prepare_cpus = msm_smp_prepare_cpus, + .smp_secondary_init = msm_secondary_init, + .smp_boot_secondary = msm_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = msm_cpu_die, +#endif +}; diff --git a/trunk/arch/arm/mach-msm/proc_comm.c b/trunk/arch/arm/mach-msm/proc_comm.c index 9980dc736e7b..8f1eecd88186 100644 --- a/trunk/arch/arm/mach-msm/proc_comm.c +++ b/trunk/arch/arm/mach-msm/proc_comm.c @@ -19,7 +19,6 @@ #include #include #include -#include #include "proc_comm.h" diff --git a/trunk/arch/arm/mach-msm/smd.c b/trunk/arch/arm/mach-msm/smd.c index 657be73297db..c5a2eddc6cdc 100644 --- a/trunk/arch/arm/mach-msm/smd.c +++ b/trunk/arch/arm/mach-msm/smd.c @@ -30,7 +30,6 @@ #include #include -#include #include "smd_private.h" #include "proc_comm.h" @@ -39,8 +38,6 @@ #define CONFIG_QDSP6 1 #endif -void (*msm_hw_reset_hook)(void); - #define MODULE_NAME "msm_smd" enum { @@ -52,13 +49,14 @@ static int msm_smd_debug_mask; struct shared_info { int ready; - unsigned state; + void __iomem *state; }; static unsigned dummy_state[SMSM_STATE_COUNT]; static struct shared_info smd_info = { - .state = (unsigned) &dummy_state, + /* FIXME: not a real __iomem pointer */ + .state = &dummy_state, }; module_param_named(debug_mask, msm_smd_debug_mask, @@ -101,10 +99,6 @@ static void handle_modem_crash(void) pr_err("ARM9 has CRASHED\n"); smd_diag(); - /* hard reboot if possible */ - if (msm_hw_reset_hook) - msm_hw_reset_hook(); - /* in this case the modem or watchdog should reboot us */ for (;;) ; @@ -796,22 +790,22 @@ void *smem_alloc(unsigned id, unsigned size) return smem_find(id, size); } -void *smem_item(unsigned id, unsigned *size) +void __iomem *smem_item(unsigned id, unsigned *size) { struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE; struct smem_heap_entry *toc = shared->heap_toc; if (id >= SMEM_NUM_ITEMS) - return 0; + return NULL; if (toc[id].allocated) { *size = toc[id].size; - return (void *) (MSM_SHARED_RAM_BASE + toc[id].offset); + return (MSM_SHARED_RAM_BASE + toc[id].offset); } else { *size = 0; } - return 0; + return NULL; } void *smem_find(unsigned id, unsigned size_in) @@ -857,7 +851,7 @@ static irqreturn_t smsm_irq_handler(int irq, void *data) int smsm_change_state(enum smsm_state_item item, uint32_t clear_mask, uint32_t set_mask) { - unsigned long addr = smd_info.state + item * 4; + void __iomem *addr = smd_info.state + item * 4; unsigned long flags; unsigned state; @@ -943,10 +937,10 @@ int smd_core_init(void) /* wait for essential items to be initialized */ for (;;) { unsigned size; - void *state; + void __iomem *state; state = smem_item(SMEM_SMSM_SHARED_STATE, &size); if (size == SMSM_V1_SIZE || size == SMSM_V2_SIZE) { - smd_info.state = (unsigned)state; + smd_info.state = state; break; } } diff --git a/trunk/arch/arm/mach-msm/timer.c b/trunk/arch/arm/mach-msm/timer.c index 812808254936..476549a8a709 100644 --- a/trunk/arch/arm/mach-msm/timer.c +++ b/trunk/arch/arm/mach-msm/timer.c @@ -1,7 +1,7 @@ /* * * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. + * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -20,15 +20,16 @@ #include #include #include +#include +#include +#include #include #include #include #include -#include -#include -#include +#include "common.h" #define TIMER_MATCH_VAL 0x0000 #define TIMER_COUNT_VAL 0x0004 @@ -36,7 +37,6 @@ #define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1) #define TIMER_ENABLE_EN BIT(0) #define TIMER_CLEAR 0x000C -#define DGT_CLK_CTL 0x0034 #define DGT_CLK_CTL_DIV_4 0x3 #define GPT_HZ 32768 @@ -101,7 +101,7 @@ static struct clock_event_device msm_clockevent = { static union { struct clock_event_device *evt; - struct clock_event_device __percpu **percpu_evt; + struct clock_event_device * __percpu *percpu_evt; } msm_evt; static void __iomem *source_base; @@ -151,7 +151,7 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt) *__this_cpu_ptr(msm_evt.percpu_evt) = evt; clockevents_register_device(evt); - enable_percpu_irq(evt->irq, 0); + enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING); return 0; } @@ -172,44 +172,21 @@ static notrace u32 msm_sched_clock_read(void) return msm_clocksource.read(&msm_clocksource); } -static void __init msm_timer_init(void) +static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq, + bool percpu) { struct clock_event_device *ce = &msm_clockevent; struct clocksource *cs = &msm_clocksource; int res; - u32 dgt_hz; - - if (cpu_is_msm7x01()) { - event_base = MSM_CSR_BASE; - source_base = MSM_CSR_BASE + 0x10; - dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */ - cs->read = msm_read_timer_count_shift; - cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)); - } else if (cpu_is_msm7x30()) { - event_base = MSM_CSR_BASE + 0x04; - source_base = MSM_CSR_BASE + 0x24; - dgt_hz = 24576000 / 4; - } else if (cpu_is_qsd8x50()) { - event_base = MSM_CSR_BASE; - source_base = MSM_CSR_BASE + 0x10; - dgt_hz = 19200000 / 4; - } else if (cpu_is_msm8x60() || cpu_is_msm8960()) { - event_base = MSM_TMR_BASE + 0x04; - /* Use CPU0's timer as the global clock source. */ - source_base = MSM_TMR0_BASE + 0x24; - dgt_hz = 27000000 / 4; - writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); - } else - BUG(); writel_relaxed(0, event_base + TIMER_ENABLE); writel_relaxed(0, event_base + TIMER_CLEAR); writel_relaxed(~0, event_base + TIMER_MATCH_VAL); ce->cpumask = cpumask_of(0); + ce->irq = irq; - ce->irq = INT_GP_TIMER_EXP; clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff); - if (cpu_is_msm8x60() || cpu_is_msm8960()) { + if (percpu) { msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *); if (!msm_evt.percpu_evt) { pr_err("memory allocation failed for %s\n", ce->name); @@ -219,7 +196,7 @@ static void __init msm_timer_init(void) res = request_percpu_irq(ce->irq, msm_timer_interrupt, ce->name, msm_evt.percpu_evt); if (!res) { - enable_percpu_irq(ce->irq, 0); + enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING); #ifdef CONFIG_LOCAL_TIMERS local_timer_register(&msm_local_timer_ops); #endif @@ -238,10 +215,143 @@ static void __init msm_timer_init(void) res = clocksource_register_hz(cs, dgt_hz); if (res) pr_err("clocksource_register failed\n"); - setup_sched_clock(msm_sched_clock_read, - cpu_is_msm7x01() ? 32 - MSM_DGT_SHIFT : 32, dgt_hz); + setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz); } -struct sys_timer msm_timer = { - .init = msm_timer_init +#ifdef CONFIG_OF +static const struct of_device_id msm_dgt_match[] __initconst = { + { .compatible = "qcom,msm-dgt" }, + { }, +}; + +static const struct of_device_id msm_gpt_match[] __initconst = { + { .compatible = "qcom,msm-gpt" }, + { }, +}; + +static void __init msm_dt_timer_init(void) +{ + struct device_node *np; + u32 freq; + int irq; + struct resource res; + u32 percpu_offset; + void __iomem *dgt_clk_ctl; + + np = of_find_matching_node(NULL, msm_gpt_match); + if (!np) { + pr_err("Can't find GPT DT node\n"); + return; + } + + event_base = of_iomap(np, 0); + if (!event_base) { + pr_err("Failed to map event base\n"); + return; + } + + irq = irq_of_parse_and_map(np, 0); + if (irq <= 0) { + pr_err("Can't get irq\n"); + return; + } + of_node_put(np); + + np = of_find_matching_node(NULL, msm_dgt_match); + if (!np) { + pr_err("Can't find DGT DT node\n"); + return; + } + + if (of_property_read_u32(np, "cpu-offset", &percpu_offset)) + percpu_offset = 0; + + if (of_address_to_resource(np, 0, &res)) { + pr_err("Failed to parse DGT resource\n"); + return; + } + + source_base = ioremap(res.start + percpu_offset, resource_size(&res)); + if (!source_base) { + pr_err("Failed to map source base\n"); + return; + } + + if (!of_address_to_resource(np, 1, &res)) { + dgt_clk_ctl = ioremap(res.start + percpu_offset, + resource_size(&res)); + if (!dgt_clk_ctl) { + pr_err("Failed to map DGT control base\n"); + return; + } + writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl); + iounmap(dgt_clk_ctl); + } + + if (of_property_read_u32(np, "clock-frequency", &freq)) { + pr_err("Unknown frequency\n"); + return; + } + of_node_put(np); + + msm_timer_init(freq, 32, irq, !!percpu_offset); +} + +struct sys_timer msm_dt_timer = { + .init = msm_dt_timer_init +}; +#endif + +static int __init msm_timer_map(phys_addr_t event, phys_addr_t source) +{ + event_base = ioremap(event, SZ_64); + if (!event_base) { + pr_err("Failed to map event base\n"); + return 1; + } + source_base = ioremap(source, SZ_64); + if (!source_base) { + pr_err("Failed to map source base\n"); + return 1; + } + return 0; +} + +static void __init msm7x01_timer_init(void) +{ + struct clocksource *cs = &msm_clocksource; + + if (msm_timer_map(0xc0100000, 0xc0100010)) + return; + cs->read = msm_read_timer_count_shift; + cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)); + /* 600 KHz */ + msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7, + false); +} + +struct sys_timer msm7x01_timer = { + .init = msm7x01_timer_init +}; + +static void __init msm7x30_timer_init(void) +{ + if (msm_timer_map(0xc0100004, 0xc0100024)) + return; + msm_timer_init(24576000 / 4, 32, 1, false); +} + +struct sys_timer msm7x30_timer = { + .init = msm7x30_timer_init +}; + +static void __init qsd8x50_timer_init(void) +{ + if (msm_timer_map(0xAC100000, 0xAC100010)) + return; + msm_timer_init(19200000 / 4, 32, 7, false); +} + +struct sys_timer qsd8x50_timer = { + .init = qsd8x50_timer_init }; diff --git a/trunk/arch/arm/mach-mv78xx0/addr-map.c b/trunk/arch/arm/mach-mv78xx0/addr-map.c index a9bc84180d21..137e479d15a0 100644 --- a/trunk/arch/arm/mach-mv78xx0/addr-map.c +++ b/trunk/arch/arm/mach-mv78xx0/addr-map.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "common.h" /* @@ -81,7 +82,7 @@ void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, int maj, int min) { orion_setup_cpu_win(&addr_map_cfg, window, base, size, - TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1); + TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0); } void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, diff --git a/trunk/arch/arm/mach-mv78xx0/common.c b/trunk/arch/arm/mach-mv78xx0/common.c index 3057f7d4329a..6b0c38735527 100644 --- a/trunk/arch/arm/mach-mv78xx0/common.c +++ b/trunk/arch/arm/mach-mv78xx0/common.c @@ -134,11 +134,6 @@ static struct map_desc mv78xx0_io_desc[] __initdata = { .pfn = 0, .length = MV78XX0_CORE_REGS_SIZE, .type = MT_DEVICE, - }, { - .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), - .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), - .length = MV78XX0_PCIE_IO_SIZE * 8, - .type = MT_DEVICE, }, { .virtual = MV78XX0_REGS_VIRT_BASE, .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), diff --git a/trunk/arch/arm/mach-mv78xx0/include/mach/io.h b/trunk/arch/arm/mach-mv78xx0/include/mach/io.h deleted file mode 100644 index c7d9d00d8fc1..000000000000 --- a/trunk/arch/arm/mach-mv78xx0/include/mach/io.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/io.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include "mv78xx0.h" - -#define IO_SPACE_LIMIT 0xffffffff - -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0)) - + MV78XX0_PCIE_IO_VIRT_BASE(0)); -} - -#define __io(a) __io(a) - -#endif diff --git a/trunk/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/trunk/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index e807c4c52a0b..bd03fed1128e 100644 --- a/trunk/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/trunk/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -29,15 +29,15 @@ * * virt phys size * fe400000 f102x000 16K core-specific peripheral registers - * fe700000 f0800000 1M PCIe #0 I/O space - * fe800000 f0900000 1M PCIe #1 I/O space - * fe900000 f0a00000 1M PCIe #2 I/O space - * fea00000 f0b00000 1M PCIe #3 I/O space - * feb00000 f0c00000 1M PCIe #4 I/O space - * fec00000 f0d00000 1M PCIe #5 I/O space - * fed00000 f0e00000 1M PCIe #6 I/O space - * fee00000 f0f00000 1M PCIe #7 I/O space - * fef00000 f1000000 1M on-chip peripheral registers + * fee00000 f0800000 64K PCIe #0 I/O space + * fee10000 f0900000 64K PCIe #1 I/O space + * fee20000 f0a00000 64K PCIe #2 I/O space + * fee30000 f0b00000 64K PCIe #3 I/O space + * fee40000 f0c00000 64K PCIe #4 I/O space + * fee50000 f0d00000 64K PCIe #5 I/O space + * fee60000 f0e00000 64K PCIe #6 I/O space + * fee70000 f0f00000 64K PCIe #7 I/O space + * fd000000 f1000000 1M on-chip peripheral registers */ #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 @@ -46,11 +46,10 @@ #define MV78XX0_CORE_REGS_SIZE SZ_16K #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) -#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) #define MV78XX0_PCIE_IO_SIZE SZ_1M #define MV78XX0_REGS_PHYS_BASE 0xf1000000 -#define MV78XX0_REGS_VIRT_BASE 0xfef00000 +#define MV78XX0_REGS_VIRT_BASE 0xfd000000 #define MV78XX0_REGS_SIZE SZ_1M #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 diff --git a/trunk/arch/arm/mach-mv78xx0/irq.c b/trunk/arch/arm/mach-mv78xx0/irq.c index eff9a750bbe2..4d720f2aedba 100644 --- a/trunk/arch/arm/mach-mv78xx0/irq.c +++ b/trunk/arch/arm/mach-mv78xx0/irq.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include "common.h" diff --git a/trunk/arch/arm/mach-mv78xx0/pcie.c b/trunk/arch/arm/mach-mv78xx0/pcie.c index 2e56e86b6d68..26a059b4f472 100644 --- a/trunk/arch/arm/mach-mv78xx0/pcie.c +++ b/trunk/arch/arm/mach-mv78xx0/pcie.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "common.h" struct pcie_port { @@ -23,16 +24,13 @@ struct pcie_port { u8 root_bus_nr; void __iomem *base; spinlock_t conf_lock; - char io_space_name[16]; char mem_space_name[16]; - struct resource res[2]; + struct resource res; }; static struct pcie_port pcie_port[8]; static int num_pcie_ports; static struct resource pcie_io_space; -static struct resource pcie_mem_space; - void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) { @@ -40,102 +38,59 @@ void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE); } +u32 pcie_port_size[8] = { + 0, + 0x30000000, + 0x10000000, + 0x10000000, + 0x08000000, + 0x08000000, + 0x08000000, + 0x04000000, +}; + static void __init mv78xx0_pcie_preinit(void) { int i; u32 size_each; u32 start; - int win; + int win = 0; pcie_io_space.name = "PCIe I/O Space"; pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0); pcie_io_space.end = MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1; - pcie_io_space.flags = IORESOURCE_IO; + pcie_io_space.flags = IORESOURCE_MEM; if (request_resource(&iomem_resource, &pcie_io_space)) panic("can't allocate PCIe I/O space"); - pcie_mem_space.name = "PCIe MEM Space"; - pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE; - pcie_mem_space.end = - MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1; - pcie_mem_space.flags = IORESOURCE_MEM; - if (request_resource(&iomem_resource, &pcie_mem_space)) - panic("can't allocate PCIe MEM space"); + if (num_pcie_ports > 7) + panic("invalid number of PCIe ports"); + + size_each = pcie_port_size[num_pcie_ports]; + start = MV78XX0_PCIE_MEM_PHYS_BASE; for (i = 0; i < num_pcie_ports; i++) { struct pcie_port *pp = pcie_port + i; - snprintf(pp->io_space_name, sizeof(pp->io_space_name), - "PCIe %d.%d I/O", pp->maj, pp->min); - pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; - pp->res[0].name = pp->io_space_name; - pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i); - pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1; - pp->res[0].flags = IORESOURCE_IO; - snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), "PCIe %d.%d MEM", pp->maj, pp->min); pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; - pp->res[1].name = pp->mem_space_name; - pp->res[1].flags = IORESOURCE_MEM; - } - - switch (num_pcie_ports) { - case 0: - size_each = 0; - break; - - case 1: - size_each = 0x30000000; - break; - - case 2 ... 3: - size_each = 0x10000000; - break; - - case 4 ... 6: - size_each = 0x08000000; - break; - - case 7: - size_each = 0x04000000; - break; - - default: - panic("invalid number of PCIe ports"); - } - - start = MV78XX0_PCIE_MEM_PHYS_BASE; - for (i = 0; i < num_pcie_ports; i++) { - struct pcie_port *pp = pcie_port + i; - - pp->res[1].start = start; - pp->res[1].end = start + size_each - 1; + pp->res.name = pp->mem_space_name; + pp->res.flags = IORESOURCE_MEM; + pp->res.start = start; + pp->res.end = start + size_each - 1; start += size_each; - } - - for (i = 0; i < num_pcie_ports; i++) { - struct pcie_port *pp = pcie_port + i; - if (request_resource(&pcie_io_space, &pp->res[0])) - panic("can't allocate PCIe I/O sub-space"); - - if (request_resource(&pcie_mem_space, &pp->res[1])) + if (request_resource(&iomem_resource, &pp->res)) panic("can't allocate PCIe MEM sub-space"); - } - win = 0; - for (i = 0; i < num_pcie_ports; i++) { - struct pcie_port *pp = pcie_port + i; + mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start, + resource_size(&pp->res), + pp->maj, pp->min); - mv78xx0_setup_pcie_io_win(win++, pp->res[0].start, - resource_size(&pp->res[0]), + mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K, pp->maj, pp->min); - - mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start, - resource_size(&pp->res[1]), - pp->maj, pp->min); } } @@ -156,8 +111,9 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) orion_pcie_set_local_bus_nr(pp->base, sys->busnr); orion_pcie_setup(pp->base); - pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); - pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); + pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr)); + + pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); return 1; } @@ -281,7 +237,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base) pp->root_bus_nr = -1; pp->base = (void __iomem *)base; spin_lock_init(&pp->conf_lock); - memset(pp->res, 0, sizeof(pp->res)); + memset(&pp->res, 0, sizeof(pp->res)); } else { printk("link down, ignoring\n"); } diff --git a/trunk/arch/arm/mach-mvebu/Kconfig b/trunk/arch/arm/mach-mvebu/Kconfig index caa2c5e734fe..7b270358536e 100644 --- a/trunk/arch/arm/mach-mvebu/Kconfig +++ b/trunk/arch/arm/mach-mvebu/Kconfig @@ -1,3 +1,13 @@ +config ARCH_MVEBU + bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7 + select CLKSRC_MMIO + select COMMON_CLK + select GENERIC_CLOCKEVENTS + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN + select MULTI_IRQ_HANDLER + select SPARSE_IRQ + if ARCH_MVEBU menu "Marvell SOC with device tree" diff --git a/trunk/arch/arm/mach-mvebu/Makefile b/trunk/arch/arm/mach-mvebu/Makefile index e61d2b8fdf50..6ea8998ab8f1 100644 --- a/trunk/arch/arm/mach-mvebu/Makefile +++ b/trunk/arch/arm/mach-mvebu/Makefile @@ -1,2 +1,4 @@ +ccflags-$(ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include + obj-y += system-controller.o obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o diff --git a/trunk/arch/arm/mach-mvebu/Makefile.boot b/trunk/arch/arm/mach-mvebu/Makefile.boot deleted file mode 100644 index 2579a2fc2334..000000000000 --- a/trunk/arch/arm/mach-mvebu/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ -zreladdr-y := 0x00008000 -dtb-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-db.dtb -dtb-$(CONFIG_MACH_ARMADA_370_XP) += armada-xp-db.dtb diff --git a/trunk/arch/arm/mach-mvebu/armada-370-xp.c b/trunk/arch/arm/mach-mvebu/armada-370-xp.c index 4ef923b032ec..b46418a8b352 100644 --- a/trunk/arch/arm/mach-mvebu/armada-370-xp.c +++ b/trunk/arch/arm/mach-mvebu/armada-370-xp.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include "armada-370-xp.h" #include "common.h" static struct map_desc armada_370_xp_io_desc[] __initdata = { diff --git a/trunk/arch/arm/mach-mvebu/include/mach/armada-370-xp.h b/trunk/arch/arm/mach-mvebu/armada-370-xp.h similarity index 100% rename from trunk/arch/arm/mach-mvebu/include/mach/armada-370-xp.h rename to trunk/arch/arm/mach-mvebu/armada-370-xp.h diff --git a/trunk/arch/arm/mach-mvebu/include/mach/timex.h b/trunk/arch/arm/mach-mvebu/include/mach/timex.h deleted file mode 100644 index ab324a3748f2..000000000000 --- a/trunk/arch/arm/mach-mvebu/include/mach/timex.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Marvell Armada SoC time definitions - * - * Copyright (C) 2012 Marvell - * - * Lior Amsalem - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define CLOCK_TICK_RATE (100 * HZ) diff --git a/trunk/arch/arm/mach-mvebu/include/mach/uncompress.h b/trunk/arch/arm/mach-mvebu/include/mach/uncompress.h deleted file mode 100644 index d6a100ccf302..000000000000 --- a/trunk/arch/arm/mach-mvebu/include/mach/uncompress.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Marvell Armada SoC kernel uncompression UART routines - * - * Copyright (C) 2012 Marvell - * - * Lior Amsalem - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include - -#define UART_THR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\ - + 0x12000)) -#define UART_LSR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\ - + 0x12014)) - -#define LSR_THRE 0x20 - -static void putc(const char c) -{ - int i; - - for (i = 0; i < 0x1000; i++) { - /* Transmit fifo not full? */ - if (*UART_LSR & LSR_THRE) - break; - } - - *UART_THR = c; -} - -static void flush(void) -{ -} - -/* - * nothing to do - */ -#define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/trunk/arch/arm/mach-mxs/Kconfig b/trunk/arch/arm/mach-mxs/Kconfig index 9a8bbda195b2..ecc431909d6f 100644 --- a/trunk/arch/arm/mach-mxs/Kconfig +++ b/trunk/arch/arm/mach-mxs/Kconfig @@ -1,7 +1,5 @@ if ARCH_MXS -source "arch/arm/mach-mxs/devices/Kconfig" - config SOC_IMX23 bool select ARM_AMBA @@ -27,91 +25,4 @@ config MACH_MXS_DT Include support for Freescale MXS platforms(i.MX23 and i.MX28) using the device tree for discovery -config MACH_STMP378X_DEVB - bool "Support STMP378x_devb Platform" - select SOC_IMX23 - select MXS_HAVE_AMBA_DUART - select MXS_HAVE_PLATFORM_AUART - select MXS_HAVE_PLATFORM_MXS_MMC - select MXS_HAVE_PLATFORM_RTC_STMP3XXX - help - Include support for STMP378x-devb platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX23EVK - bool "Support MX23EVK Platform" - select SOC_IMX23 - select MXS_HAVE_AMBA_DUART - select MXS_HAVE_PLATFORM_AUART - select MXS_HAVE_PLATFORM_MXS_MMC - select MXS_HAVE_PLATFORM_MXSFB - select MXS_HAVE_PLATFORM_RTC_STMP3XXX - help - Include support for MX23EVK platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX28EVK - bool "Support MX28EVK Platform" - select SOC_IMX28 - select LEDS_GPIO_REGISTER - select MXS_HAVE_AMBA_DUART - select MXS_HAVE_PLATFORM_AUART - select MXS_HAVE_PLATFORM_FEC - select MXS_HAVE_PLATFORM_FLEXCAN - select MXS_HAVE_PLATFORM_MXS_MMC - select MXS_HAVE_PLATFORM_MXSFB - select MXS_HAVE_PLATFORM_MXS_SAIF - select MXS_HAVE_PLATFORM_MXS_I2C - select MXS_HAVE_PLATFORM_RTC_STMP3XXX - help - Include support for MX28EVK platform. This includes specific - configurations for the board and its peripherals. - -config MODULE_TX28 - bool - select SOC_IMX28 - select LEDS_GPIO_REGISTER - select MXS_HAVE_AMBA_DUART - select MXS_HAVE_PLATFORM_AUART - select MXS_HAVE_PLATFORM_FEC - select MXS_HAVE_PLATFORM_MXS_I2C - select MXS_HAVE_PLATFORM_MXS_MMC - select MXS_HAVE_PLATFORM_MXS_PWM - select MXS_HAVE_PLATFORM_RTC_STMP3XXX - -config MODULE_M28 - bool - select SOC_IMX28 - select LEDS_GPIO_REGISTER - select MXS_HAVE_AMBA_DUART - select MXS_HAVE_PLATFORM_AUART - select MXS_HAVE_PLATFORM_FEC - select MXS_HAVE_PLATFORM_FLEXCAN - select MXS_HAVE_PLATFORM_MXS_I2C - select MXS_HAVE_PLATFORM_MXS_MMC - select MXS_HAVE_PLATFORM_MXSFB - -config MODULE_APX4 - bool - select SOC_IMX28 - select LEDS_GPIO_REGISTER - select MXS_HAVE_AMBA_DUART - select MXS_HAVE_PLATFORM_AUART - select MXS_HAVE_PLATFORM_FEC - select MXS_HAVE_PLATFORM_MXS_I2C - select MXS_HAVE_PLATFORM_MXS_MMC - select MXS_HAVE_PLATFORM_MXS_SAIF - -config MACH_TX28 - bool "Ka-Ro TX28 module" - select MODULE_TX28 - -config MACH_M28EVK - bool "Support DENX M28EVK Platform" - select MODULE_M28 - -config MACH_APX4DEVKIT - bool "Support Bluegiga APX4 Development Kit" - select MODULE_APX4 - endif diff --git a/trunk/arch/arm/mach-mxs/Makefile b/trunk/arch/arm/mach-mxs/Makefile index fed3695a1339..3d3c8a973062 100644 --- a/trunk/arch/arm/mach-mxs/Makefile +++ b/trunk/arch/arm/mach-mxs/Makefile @@ -1,15 +1,6 @@ # Common support -obj-y := devices.o icoll.o iomux.o ocotp.o system.o timer.o mm.o +obj-y := icoll.o ocotp.o system.o timer.o mm.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o -obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o -obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o -obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o -obj-$(CONFIG_MACH_M28EVK) += mach-m28evk.o -obj-$(CONFIG_MACH_APX4DEVKIT) += mach-apx4devkit.o -obj-$(CONFIG_MODULE_TX28) += module-tx28.o -obj-$(CONFIG_MACH_TX28) += mach-tx28.o - -obj-y += devices/ diff --git a/trunk/arch/arm/mach-mxs/Makefile.boot b/trunk/arch/arm/mach-mxs/Makefile.boot index 4582999cf080..07b11fe6453f 100644 --- a/trunk/arch/arm/mach-mxs/Makefile.boot +++ b/trunk/arch/arm/mach-mxs/Makefile.boot @@ -1,10 +1 @@ zreladdr-y += 0x40008000 - -dtb-y += imx23-evk.dtb \ - imx23-olinuxino.dtb \ - imx23-stmp378x_devb.dtb \ - imx28-apx4devkit.dtb \ - imx28-cfa10036.dtb \ - imx28-evk.dtb \ - imx28-m28evk.dtb \ - imx28-tx28.dtb \ diff --git a/trunk/arch/arm/mach-mxs/devices-mx23.h b/trunk/arch/arm/mach-mxs/devices-mx23.h deleted file mode 100644 index 9ee5cede3d42..000000000000 --- a/trunk/arch/arm/mach-mxs/devices-mx23.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig - * - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include -#include -#include - -static inline int mx23_add_duart(void) -{ - struct amba_device *d; - - d = amba_ahb_device_add(NULL, "duart", MX23_DUART_BASE_ADDR, SZ_8K, - MX23_INT_DUART, 0, 0, 0); - return IS_ERR(d) ? PTR_ERR(d) : 0; -} - -extern const struct mxs_auart_data mx23_auart_data[] __initconst; -#define mx23_add_auart(id) mxs_add_auart(&mx23_auart_data[id]) -#define mx23_add_auart0() mx23_add_auart(0) -#define mx23_add_auart1() mx23_add_auart(1) - -extern const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst; -#define mx23_add_gpmi_nand(pdata) \ - mxs_add_gpmi_nand(pdata, &mx23_gpmi_nand_data) - -extern const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst; -#define mx23_add_mxs_mmc(id, pdata) \ - mxs_add_mxs_mmc(&mx23_mxs_mmc_data[id], pdata) - -#define mx23_add_mxs_pwm(id) mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id) - -struct platform_device *__init mx23_add_mxsfb( - const struct mxsfb_platform_data *pdata); - -struct platform_device *__init mx23_add_rtc_stmp3xxx(void); diff --git a/trunk/arch/arm/mach-mxs/devices-mx28.h b/trunk/arch/arm/mach-mxs/devices-mx28.h deleted file mode 100644 index fcab431060f4..000000000000 --- a/trunk/arch/arm/mach-mxs/devices-mx28.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig - * - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include -#include -#include - -static inline int mx28_add_duart(void) -{ - struct amba_device *d; - - d = amba_ahb_device_add(NULL, "duart", MX28_DUART_BASE_ADDR, SZ_8K, - MX28_INT_DUART, 0, 0, 0); - return IS_ERR(d) ? PTR_ERR(d) : 0; -} - -extern const struct mxs_auart_data mx28_auart_data[] __initconst; -#define mx28_add_auart(id) mxs_add_auart(&mx28_auart_data[id]) -#define mx28_add_auart0() mx28_add_auart(0) -#define mx28_add_auart1() mx28_add_auart(1) -#define mx28_add_auart2() mx28_add_auart(2) -#define mx28_add_auart3() mx28_add_auart(3) -#define mx28_add_auart4() mx28_add_auart(4) - -extern const struct mxs_fec_data mx28_fec_data[] __initconst; -#define mx28_add_fec(id, pdata) \ - mxs_add_fec(&mx28_fec_data[id], pdata) - -extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst; -#define mx28_add_flexcan(id, pdata) \ - mxs_add_flexcan(&mx28_flexcan_data[id], pdata) -#define mx28_add_flexcan0(pdata) mx28_add_flexcan(0, pdata) -#define mx28_add_flexcan1(pdata) mx28_add_flexcan(1, pdata) - -extern const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst; -#define mx28_add_gpmi_nand(pdata) \ - mxs_add_gpmi_nand(pdata, &mx28_gpmi_nand_data) - -extern const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst; -#define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id]) - -extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst; -#define mx28_add_mxs_mmc(id, pdata) \ - mxs_add_mxs_mmc(&mx28_mxs_mmc_data[id], pdata) - -#define mx28_add_mxs_pwm(id) mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id) - -struct platform_device *__init mx28_add_mxsfb( - const struct mxsfb_platform_data *pdata); - -extern const struct mxs_saif_data mx28_saif_data[] __initconst; -#define mx28_add_saif(id, pdata) \ - mxs_add_saif(&mx28_saif_data[id], pdata) - -struct platform_device *__init mx28_add_rtc_stmp3xxx(void); diff --git a/trunk/arch/arm/mach-mxs/devices.c b/trunk/arch/arm/mach-mxs/devices.c deleted file mode 100644 index cf50b5a66dda..000000000000 --- a/trunk/arch/arm/mach-mxs/devices.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright 2008 Sascha Hauer, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. - */ - -#include -#include -#include -#include -#include - -struct platform_device *__init mxs_add_platform_device_dmamask( - const char *name, int id, - const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data, u64 dmamask) -{ - int ret = -ENOMEM; - struct platform_device *pdev; - - pdev = platform_device_alloc(name, id); - if (!pdev) - goto err; - - if (dmamask) { - /* - * This memory isn't freed when the device is put, - * I don't have a nice idea for that though. Conceptually - * dma_mask in struct device should not be a pointer. - * See http://thread.gmane.org/gmane.linux.kernel.pci/9081 - */ - pdev->dev.dma_mask = - kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); - if (!pdev->dev.dma_mask) - /* ret is still -ENOMEM; */ - goto err; - - *pdev->dev.dma_mask = dmamask; - pdev->dev.coherent_dma_mask = dmamask; - } - - if (res) { - ret = platform_device_add_resources(pdev, res, num_resources); - if (ret) - goto err; - } - - if (data) { - ret = platform_device_add_data(pdev, data, size_data); - if (ret) - goto err; - } - - ret = platform_device_add(pdev); - if (ret) { -err: - if (dmamask) - kfree(pdev->dev.dma_mask); - platform_device_put(pdev); - return ERR_PTR(ret); - } - - return pdev; -} - -struct device mxs_apbh_bus = { - .init_name = "mxs_apbh", - .parent = &platform_bus, -}; - -static int __init mxs_device_init(void) -{ - return device_register(&mxs_apbh_bus); -} -core_initcall(mxs_device_init); diff --git a/trunk/arch/arm/mach-mxs/devices/Kconfig b/trunk/arch/arm/mach-mxs/devices/Kconfig deleted file mode 100644 index 19659de1c4e8..000000000000 --- a/trunk/arch/arm/mach-mxs/devices/Kconfig +++ /dev/null @@ -1,33 +0,0 @@ -config MXS_HAVE_AMBA_DUART - bool - -config MXS_HAVE_PLATFORM_AUART - bool - -config MXS_HAVE_PLATFORM_FEC - bool - -config MXS_HAVE_PLATFORM_FLEXCAN - select HAVE_CAN_FLEXCAN if CAN - bool - -config MXS_HAVE_PLATFORM_GPMI_NAND - bool - -config MXS_HAVE_PLATFORM_MXS_I2C - bool - -config MXS_HAVE_PLATFORM_MXS_MMC - bool - -config MXS_HAVE_PLATFORM_MXS_PWM - bool - -config MXS_HAVE_PLATFORM_MXSFB - bool - -config MXS_HAVE_PLATFORM_MXS_SAIF - bool - -config MXS_HAVE_PLATFORM_RTC_STMP3XXX - bool diff --git a/trunk/arch/arm/mach-mxs/devices/Makefile b/trunk/arch/arm/mach-mxs/devices/Makefile deleted file mode 100644 index 5f72d9787444..000000000000 --- a/trunk/arch/arm/mach-mxs/devices/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o -obj-y += platform-dma.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_GPMI_NAND) += platform-gpmi-nand.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o -obj-y += platform-gpio-mxs.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_SAIF) += platform-mxs-saif.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_RTC_STMP3XXX) += platform-rtc-stmp3xxx.o diff --git a/trunk/arch/arm/mach-mxs/devices/platform-auart.c b/trunk/arch/arm/mach-mxs/devices/platform-auart.c deleted file mode 100644 index 27608f5d2ac8..000000000000 --- a/trunk/arch/arm/mach-mxs/devices/platform-auart.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Sascha Hauer - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include -#include -#include -#include - -#define mxs_auart_data_entry_single(soc, _id, hwid) \ - { \ - .id = _id, \ - .iobase = soc ## _AUART ## hwid ## _BASE_ADDR, \ - .irq = soc ## _INT_AUART ## hwid, \ - } - -#define mxs_auart_data_entry(soc, _id, hwid) \ - [_id] = mxs_auart_data_entry_single(soc, _id, hwid) - -#ifdef CONFIG_SOC_IMX23 -const struct mxs_auart_data mx23_auart_data[] __initconst = { -#define mx23_auart_data_entry(_id, hwid) \ - mxs_auart_data_entry(MX23, _id, hwid) - mx23_auart_data_entry(0, 1), - mx23_auart_data_entry(1, 2), -}; -#endif - -#ifdef CONFIG_SOC_IMX28 -const struct mxs_auart_data mx28_auart_data[] __initconst = { -#define mx28_auart_data_entry(_id) \ - mxs_auart_data_entry(MX28, _id, _id) - mx28_auart_data_entry(0), - mx28_auart_data_entry(1), - mx28_auart_data_entry(2), - mx28_auart_data_entry(3), - mx28_auart_data_entry(4), -}; -#endif - -struct platform_device *__init mxs_add_auart( - const struct mxs_auart_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return mxs_add_platform_device_dmamask("mxs-auart", data->id, - res, ARRAY_SIZE(res), NULL, 0, - DMA_BIT_MASK(32)); -} - diff --git a/trunk/arch/arm/mach-mxs/devices/platform-dma.c b/trunk/arch/arm/mach-mxs/devices/platform-dma.c deleted file mode 100644 index 46824501de00..000000000000 --- a/trunk/arch/arm/mach-mxs/devices/platform-dma.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include -#include -#include - -#include -#include -#include - -struct platform_device *__init mxs_add_dma(const char *devid, - resource_size_t base) -{ - struct resource res[] = { - { - .start = base, - .end = base + SZ_8K - 1, - .flags = IORESOURCE_MEM, - } - }; - - return mxs_add_platform_device_dmamask(devid, -1, - res, ARRAY_SIZE(res), NULL, 0, - DMA_BIT_MASK(32)); -} diff --git a/trunk/arch/arm/mach-mxs/devices/platform-fec.c b/trunk/arch/arm/mach-mxs/devices/platform-fec.c deleted file mode 100644 index ae96a4fd8f14..000000000000 --- a/trunk/arch/arm/mach-mxs/devices/platform-fec.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include -#include -#include - -#define mxs_fec_data_entry_single(soc, _id) \ - { \ - .id = _id, \ - .iobase = soc ## _ENET_MAC ## _id ## _BASE_ADDR, \ - .irq = soc ## _INT_ENET_MAC ## _id, \ - } - -#define mxs_fec_data_entry(soc, _id) \ - [_id] = mxs_fec_data_entry_single(soc, _id) - -#ifdef CONFIG_SOC_IMX28 -const struct mxs_fec_data mx28_fec_data[] __initconst = { -#define mx28_fec_data_entry(_id) \ - mxs_fec_data_entry(MX28, _id) - mx28_fec_data_entry(0), - mx28_fec_data_entry(1), -}; -#endif - -struct platform_device *__init mxs_add_fec( - const struct mxs_fec_data *data, - const struct fec_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return mxs_add_platform_device_dmamask("imx28-fec", data->id, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata), - DMA_BIT_MASK(32)); -} diff --git a/trunk/arch/arm/mach-mxs/devices/platform-flexcan.c b/trunk/arch/arm/mach-mxs/devices/platform-flexcan.c deleted file mode 100644 index 43a6b4bae6fe..000000000000 --- a/trunk/arch/arm/mach-mxs/devices/platform-flexcan.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (C) 2010, 2011 Pengutronix, - * Marc Kleine-Budde - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include -#include - -#define mxs_flexcan_data_entry_single(soc, _id, _hwid, _size) \ - { \ - .id = _id, \ - .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_CAN ## _hwid, \ - } - -#define mxs_flexcan_data_entry(soc, _id, _hwid, _size) \ - [_id] = mxs_flexcan_data_entry_single(soc, _id, _hwid, _size) - -#ifdef CONFIG_SOC_IMX28 -const struct mxs_flexcan_data mx28_flexcan_data[] __initconst = { -#define mx28_flexcan_data_entry(_id, _hwid) \ - mxs_flexcan_data_entry_single(MX28, _id, _hwid, SZ_8K) - mx28_flexcan_data_entry(0, 0), - mx28_flexcan_data_entry(1, 1), -}; -#endif /* ifdef CONFIG_SOC_IMX28 */ - -struct platform_device *__init mxs_add_flexcan( - const struct mxs_flexcan_data *data, - const struct flexcan_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return mxs_add_platform_device("flexcan", data->id, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/trunk/arch/arm/mach-mxs/devices/platform-gpio-mxs.c b/trunk/arch/arm/mach-mxs/devices/platform-gpio-mxs.c deleted file mode 100644 index cd99f19ec637..000000000000 --- a/trunk/arch/arm/mach-mxs/devices/platform-gpio-mxs.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include -#include - -#include -#include -#include - -struct platform_device *__init mxs_add_gpio( - char *name, int id, resource_size_t iobase, int irq) -{ - struct resource res[] = { - { - .start = iobase, - .end = iobase + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = irq, - .end = irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return platform_device_register_resndata(&mxs_apbh_bus, - name, id, res, ARRAY_SIZE(res), NULL, 0); -} diff --git a/trunk/arch/arm/mach-mxs/devices/platform-gpmi-nand.c b/trunk/arch/arm/mach-mxs/devices/platform-gpmi-nand.c deleted file mode 100644 index 3e22df5944a8..000000000000 --- a/trunk/arch/arm/mach-mxs/devices/platform-gpmi-nand.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ -#include -#include -#include -#include -#include - -#ifdef CONFIG_SOC_IMX23 -const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst = { - .devid = "imx23-gpmi-nand", - .res = { - /* GPMI */ - DEFINE_RES_MEM_NAMED(MX23_GPMI_BASE_ADDR, SZ_8K, - GPMI_NAND_GPMI_REGS_ADDR_RES_NAME), - DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_ATTENTION, - GPMI_NAND_GPMI_INTERRUPT_RES_NAME), - /* BCH */ - DEFINE_RES_MEM_NAMED(MX23_BCH_BASE_ADDR, SZ_8K, - GPMI_NAND_BCH_REGS_ADDR_RES_NAME), - DEFINE_RES_IRQ_NAMED(MX23_INT_BCH, - GPMI_NAND_BCH_INTERRUPT_RES_NAME), - /* DMA */ - DEFINE_RES_NAMED(MX23_DMA_GPMI0, - MX23_DMA_GPMI3 - MX23_DMA_GPMI0 + 1, - GPMI_NAND_DMA_CHANNELS_RES_NAME, - IORESOURCE_DMA), - DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_DMA, - GPMI_NAND_DMA_INTERRUPT_RES_NAME), - }, -}; -#endif - -#ifdef CONFIG_SOC_IMX28 -const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst = { - .devid = "imx28-gpmi-nand", - .res = { - /* GPMI */ - DEFINE_RES_MEM_NAMED(MX28_GPMI_BASE_ADDR, SZ_8K, - GPMI_NAND_GPMI_REGS_ADDR_RES_NAME), - DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI, - GPMI_NAND_GPMI_INTERRUPT_RES_NAME), - /* BCH */ - DEFINE_RES_MEM_NAMED(MX28_BCH_BASE_ADDR, SZ_8K, - GPMI_NAND_BCH_REGS_ADDR_RES_NAME), - DEFINE_RES_IRQ_NAMED(MX28_INT_BCH, - GPMI_NAND_BCH_INTERRUPT_RES_NAME), - /* DMA */ - DEFINE_RES_NAMED(MX28_DMA_GPMI0, - MX28_DMA_GPMI7 - MX28_DMA_GPMI0 + 1, - GPMI_NAND_DMA_CHANNELS_RES_NAME, - IORESOURCE_DMA), - DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI_DMA, - GPMI_NAND_DMA_INTERRUPT_RES_NAME), - }, -}; -#endif - -struct platform_device *__init -mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata, - const struct mxs_gpmi_nand_data *data) -{ - return mxs_add_platform_device_dmamask(data->devid, -1, - data->res, GPMI_NAND_RES_SIZE, - pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} diff --git a/trunk/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/trunk/arch/arm/mach-mxs/devices/platform-mxs-i2c.c deleted file mode 100644 index 79222ec8ede1..000000000000 --- a/trunk/arch/arm/mach-mxs/devices/platform-mxs-i2c.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2011 Pengutronix - * Wolfram Sang - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include -#include - -#define mxs_i2c_data_entry_single(soc, _id) \ - { \ - .id = _id, \ - .iobase = soc ## _I2C ## _id ## _BASE_ADDR, \ - .errirq = soc ## _INT_I2C ## _id ## _ERROR, \ - .dmairq = soc ## _INT_I2C ## _id ## _DMA, \ - } - -#define mxs_i2c_data_entry(soc, _id) \ - [_id] = mxs_i2c_data_entry_single(soc, _id) - -#ifdef CONFIG_SOC_IMX28 -const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst = { - mxs_i2c_data_entry(MX28, 0), - mxs_i2c_data_entry(MX28, 1), -}; -#endif - -struct platform_device *__init mxs_add_mxs_i2c( - const struct mxs_mxs_i2c_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->errirq, - .end = data->errirq, - .flags = IORESOURCE_IRQ, - }, { - .start = data->dmairq, - .end = data->dmairq, - .flags = IORESOURCE_IRQ, - }, - }; - - return mxs_add_platform_device("mxs-i2c", data->id, res, - ARRAY_SIZE(res), NULL, 0); -} diff --git a/trunk/arch/arm/mach-mxs/devices/platform-mxs-mmc.c b/trunk/arch/arm/mach-mxs/devices/platform-mxs-mmc.c deleted file mode 100644 index b33c9d05c552..000000000000 --- a/trunk/arch/arm/mach-mxs/devices/platform-mxs-mmc.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig - * - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ - -#include -#include -#include - -#include -#include -#include - -#define mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid) \ - { \ - .devid = _devid, \ - .id = _id, \ - .iobase = soc ## _SSP ## hwid ## _BASE_ADDR, \ - .dma = soc ## _DMA_SSP ## hwid, \ - .irq_err = soc ## _INT_SSP ## hwid ## _ERROR, \ - .irq_dma = soc ## _INT_SSP ## hwid ## _DMA, \ - } - -#define mxs_mxs_mmc_data_entry(soc, _devid, _id, hwid) \ - [_id] = mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid) - - -#ifdef CONFIG_SOC_IMX23 -const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst = { - mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 0, 1), - mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 1, 2), -}; -#endif - -#ifdef CONFIG_SOC_IMX28 -const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst = { - mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 0, 0), - mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 1, 1), - mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 2, 2), - mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 3, 3), -}; -#endif - -struct platform_device *__init mxs_add_mxs_mmc( - const struct mxs_mxs_mmc_data *data, - const struct mxs_mmc_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->dma, - .end = data->dma, - .flags = IORESOURCE_DMA, - }, { - .start = data->irq_err, - .end = data->irq_err, - .flags = IORESOURCE_IRQ, - }, { - .start = data->irq_dma, - .end = data->irq_dma, - .flags = IORESOURCE_IRQ, - }, - }; - - return mxs_add_platform_device(data->devid, data->id, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/trunk/arch/arm/mach-mxs/devices/platform-mxs-pwm.c b/trunk/arch/arm/mach-mxs/devices/platform-mxs-pwm.c deleted file mode 100644 index 680f5a902936..000000000000 --- a/trunk/arch/arm/mach-mxs/devices/platform-mxs-pwm.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Sascha Hauer - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include - -struct platform_device *__init mxs_add_mxs_pwm(resource_size_t iobase, int id) -{ - struct resource res = { - .flags = IORESOURCE_MEM, - }; - - res.start = iobase + 0x10 + 0x20 * id; - res.end = res.start + 0x1f; - - return mxs_add_platform_device("mxs-pwm", id, &res, 1, NULL, 0); -} diff --git a/trunk/arch/arm/mach-mxs/devices/platform-mxs-saif.c b/trunk/arch/arm/mach-mxs/devices/platform-mxs-saif.c deleted file mode 100644 index f6e3a60b4201..000000000000 --- a/trunk/arch/arm/mach-mxs/devices/platform-mxs-saif.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include -#include - -#include -#include -#include - -#define mxs_saif_data_entry_single(soc, _id) \ - { \ - .id = _id, \ - .iobase = soc ## _SAIF ## _id ## _BASE_ADDR, \ - .irq = soc ## _INT_SAIF ## _id, \ - .dma = soc ## _DMA_SAIF ## _id, \ - .dmairq = soc ## _INT_SAIF ## _id ##_DMA, \ - } - -#define mxs_saif_data_entry(soc, _id) \ - [_id] = mxs_saif_data_entry_single(soc, _id) - -#ifdef CONFIG_SOC_IMX28 -const struct mxs_saif_data mx28_saif_data[] __initconst = { - mxs_saif_data_entry(MX28, 0), - mxs_saif_data_entry(MX28, 1), -}; -#endif - -struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data, - const struct mxs_saif_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, { - .start = data->dma, - .end = data->dma, - .flags = IORESOURCE_DMA, - }, { - .start = data->dmairq, - .end = data->dmairq, - .flags = IORESOURCE_IRQ, - }, - - }; - - return mxs_add_platform_device("mxs-saif", data->id, res, - ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/trunk/arch/arm/mach-mxs/devices/platform-mxsfb.c b/trunk/arch/arm/mach-mxs/devices/platform-mxsfb.c deleted file mode 100644 index 76b53f73418e..000000000000 --- a/trunk/arch/arm/mach-mxs/devices/platform-mxsfb.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2011 Pengutronix, Sascha Hauer - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SOC_IMX23 -struct platform_device *__init mx23_add_mxsfb( - const struct mxsfb_platform_data *pdata) -{ - struct resource res[] = { - { - .start = MX23_LCDIF_BASE_ADDR, - .end = MX23_LCDIF_BASE_ADDR + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - }; - - return mxs_add_platform_device_dmamask("imx23-fb", -1, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} -#endif /* ifdef CONFIG_SOC_IMX23 */ - -#ifdef CONFIG_SOC_IMX28 -struct platform_device *__init mx28_add_mxsfb( - const struct mxsfb_platform_data *pdata) -{ - struct resource res[] = { - { - .start = MX28_LCDIF_BASE_ADDR, - .end = MX28_LCDIF_BASE_ADDR + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - }; - - return mxs_add_platform_device_dmamask("imx28-fb", -1, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} -#endif /* ifdef CONFIG_SOC_IMX28 */ diff --git a/trunk/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c b/trunk/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c deleted file mode 100644 index 639eaee15553..000000000000 --- a/trunk/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (C) 2011 Pengutronix, Wolfram Sang - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include -#include -#include - -#ifdef CONFIG_SOC_IMX23 -struct platform_device *__init mx23_add_rtc_stmp3xxx(void) -{ - struct resource res[] = { - { - .start = MX23_RTC_BASE_ADDR, - .end = MX23_RTC_BASE_ADDR + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MX23_INT_RTC_ALARM, - .end = MX23_INT_RTC_ALARM, - .flags = IORESOURCE_IRQ, - }, - }; - - return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res), - NULL, 0); -} -#endif /* CONFIG_SOC_IMX23 */ - -#ifdef CONFIG_SOC_IMX28 -struct platform_device *__init mx28_add_rtc_stmp3xxx(void) -{ - struct resource res[] = { - { - .start = MX28_RTC_BASE_ADDR, - .end = MX28_RTC_BASE_ADDR + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MX28_INT_RTC_ALARM, - .end = MX28_INT_RTC_ALARM, - .flags = IORESOURCE_IRQ, - }, - }; - - return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res), - NULL, 0); -} -#endif /* CONFIG_SOC_IMX28 */ diff --git a/trunk/arch/arm/mach-mxs/include/mach/common.h b/trunk/arch/arm/mach-mxs/include/mach/common.h index de6c7ba42544..4dec79563f19 100644 --- a/trunk/arch/arm/mach-mxs/include/mach/common.h +++ b/trunk/arch/arm/mach-mxs/include/mach/common.h @@ -17,21 +17,12 @@ extern void mxs_timer_init(int); extern void mxs_restart(char, const char *); extern int mxs_saif_clkmux_select(unsigned int clkmux); -extern void mx23_soc_init(void); extern int mx23_clocks_init(void); extern void mx23_map_io(void); -extern void mx23_init_irq(void); -extern void mx28_soc_init(void); extern int mx28_clocks_init(void); extern void mx28_map_io(void); -extern void mx28_init_irq(void); extern void icoll_init_irq(void); -extern struct platform_device *mxs_add_dma(const char *devid, - resource_size_t base); -extern struct platform_device *mxs_add_gpio(char *name, int id, - resource_size_t iobase, int irq); - #endif /* __MACH_MXS_COMMON_H__ */ diff --git a/trunk/arch/arm/mach-mxs/include/mach/devices-common.h b/trunk/arch/arm/mach-mxs/include/mach/devices-common.h deleted file mode 100644 index e8b1d958240b..000000000000 --- a/trunk/arch/arm/mach-mxs/include/mach/devices-common.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include -#include -#include - -extern struct device mxs_apbh_bus; - -struct platform_device *mxs_add_platform_device_dmamask( - const char *name, int id, - const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data, u64 dmamask); - -static inline struct platform_device *mxs_add_platform_device( - const char *name, int id, - const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data) -{ - return mxs_add_platform_device_dmamask( - name, id, res, num_resources, data, size_data, 0); -} - -/* auart */ -struct mxs_auart_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init mxs_add_auart( - const struct mxs_auart_data *data); - -/* fec */ -#include -struct mxs_fec_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init mxs_add_fec( - const struct mxs_fec_data *data, - const struct fec_platform_data *pdata); - -/* flexcan */ -#include -struct mxs_flexcan_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init mxs_add_flexcan( - const struct mxs_flexcan_data *data, - const struct flexcan_platform_data *pdata); - -/* gpmi-nand */ -#include -struct mxs_gpmi_nand_data { - const char *devid; - const struct resource res[GPMI_NAND_RES_SIZE]; -}; -struct platform_device *__init -mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata, - const struct mxs_gpmi_nand_data *data); - -/* i2c */ -struct mxs_mxs_i2c_data { - int id; - resource_size_t iobase; - resource_size_t errirq; - resource_size_t dmairq; -}; -struct platform_device * __init mxs_add_mxs_i2c( - const struct mxs_mxs_i2c_data *data); - -/* mmc */ -#include -struct mxs_mxs_mmc_data { - const char *devid; - int id; - resource_size_t iobase; - resource_size_t dma; - resource_size_t irq_err; - resource_size_t irq_dma; -}; -struct platform_device *__init mxs_add_mxs_mmc( - const struct mxs_mxs_mmc_data *data, - const struct mxs_mmc_platform_data *pdata); - -/* pwm */ -struct platform_device *__init mxs_add_mxs_pwm( - resource_size_t iobase, int id); - -/* saif */ -#include -struct mxs_saif_data { - int id; - resource_size_t iobase; - resource_size_t irq; - resource_size_t dma; - resource_size_t dmairq; -}; - -struct platform_device *__init mxs_add_saif( - const struct mxs_saif_data *data, - const struct mxs_saif_platform_data *pdata); diff --git a/trunk/arch/arm/mach-mxs/include/mach/gpio.h b/trunk/arch/arm/mach-mxs/include/mach/gpio.h deleted file mode 100644 index 40a8c178f10d..000000000000 --- a/trunk/arch/arm/mach-mxs/include/mach/gpio.h +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/trunk/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/trunk/arch/arm/mach-mxs/include/mach/iomux-mx23.h deleted file mode 100644 index b0190a4822f2..000000000000 --- a/trunk/arch/arm/mach-mxs/include/mach/iomux-mx23.h +++ /dev/null @@ -1,355 +0,0 @@ -/* - * Copyright (C) 2009-2010 Amit Kucheria - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __MACH_IOMUX_MX23_H__ -#define __MACH_IOMUX_MX23_H__ - -#include - -/* - * The naming convention for the pad modes is MX23_PAD___ - * If or refers to a GPIO, it is named GPIO__ - * See also iomux.h - * - * BANK PIN MUX - */ -/* MUXSEL_0 */ -#define MX23_PAD_GPMI_D00__GPMI_D00 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D01__GPMI_D01 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D02__GPMI_D02 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D03__GPMI_D03 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D04__GPMI_D04 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D05__GPMI_D05 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D06__GPMI_D06 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D07__GPMI_D07 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D08__GPMI_D08 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D09__GPMI_D09 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D10__GPMI_D10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D11__GPMI_D11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D12__GPMI_D12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D13__GPMI_D13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D14__GPMI_D14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D15__GPMI_D15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_WPN__GPMI_WPN MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0) -#define MX23_PAD_I2C_SCL__I2C_SCL MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0) -#define MX23_PAD_I2C_SDA__I2C_SDA MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0) - -#define MX23_PAD_LCD_D00__LCD_D00 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D01__LCD_D01 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D02__LCD_D02 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D03__LCD_D03 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D04__LCD_D04 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D05__LCD_D05 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D06__LCD_D06 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D07__LCD_D07 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D08__LCD_D08 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D09__LCD_D09 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) -#define MX23_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) -#define MX23_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) -#define MX23_PAD_LCD_WR__LCD_WR MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) -#define MX23_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) -#define MX23_PAD_LCD_DOTCK__LCD_DOTCK MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) -#define MX23_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) -#define MX23_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) -#define MX23_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) -#define MX23_PAD_PWM0__PWM0 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) -#define MX23_PAD_PWM1__PWM1 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) -#define MX23_PAD_PWM2__PWM2 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) -#define MX23_PAD_PWM3__PWM3 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) -#define MX23_PAD_PWM4__PWM4 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) - -#define MX23_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DETECT__SSP1_DETECT MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) -#define MX23_PAD_ROTARYA__ROTARYA MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) -#define MX23_PAD_ROTARYB__ROTARYB MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A00__EMI_A00 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A01__EMI_A01 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A02__EMI_A02 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A03__EMI_A03 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A04__EMI_A04 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A05__EMI_A05 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A06__EMI_A06 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A07__EMI_A07 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A08__EMI_A08 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A09__EMI_A09 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A10__EMI_A10 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A11__EMI_A11 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A12__EMI_A12 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) -#define MX23_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0) -#define MX23_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0) -#define MX23_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0) -#define MX23_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0) - -#define MX23_PAD_EMI_D00__EMI_D00 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D01__EMI_D01 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D02__EMI_D02 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D03__EMI_D03 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D04__EMI_D04 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D05__EMI_D05 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D06__EMI_D06 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D07__EMI_D07 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D08__EMI_D08 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D09__EMI_D09 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D10__EMI_D10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D11__EMI_D11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D12__EMI_D12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D13__EMI_D13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D14__EMI_D14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D15__EMI_D15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CLKN__EMI_CLKN MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) - -/* MUXSEL_1 */ -#define MX23_PAD_GPMI_D00__LCD_D8 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D01__LCD_D9 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D02__LCD_D10 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D03__LCD_D11 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D04__LCD_D12 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D05__LCD_D13 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D06__LCD_D14 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D07__LCD_D15 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D08__LCD_D18 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D09__LCD_D19 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D10__LCD_D20 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D11__LCD_D21 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D12__LCD_D22 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D13__LCD_D23 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D14__AUART2_RX MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D15__AUART2_TX MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_CLE__LCD_D16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_ALE__LCD_D17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_CE2N__ATA_A2 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_RTS__IR_CLK MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_RX__IR_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_TX__IR_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1) -#define MX23_PAD_I2C_SCL__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1) -#define MX23_PAD_I2C_SDA__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1) - -#define MX23_PAD_LCD_D00__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D01__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D02__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D03__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D04__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D05__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D06__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D07__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D08__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D09__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D10__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D11__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D12__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D13__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D14__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D15__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1) -#define MX23_PAD_LCD_RESET__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1) -#define MX23_PAD_LCD_RS__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1) -#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) -#define MX23_PAD_LCD_ENABLE__I2C_SCL MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) -#define MX23_PAD_LCD_HSYNC__I2C_SDA MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) -#define MX23_PAD_LCD_VSYNC__LCD_BUSY MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) -#define MX23_PAD_PWM0__ROTARYA MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) -#define MX23_PAD_PWM1__ROTARYB MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) -#define MX23_PAD_PWM2__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) -#define MX23_PAD_PWM3__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) -#define MX23_PAD_PWM4__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) - -#define MX23_PAD_SSP1_DETECT__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_1) -#define MX23_PAD_SSP1_DATA1__I2C_SCL MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_1) -#define MX23_PAD_SSP1_DATA2__I2C_SDA MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) -#define MX23_PAD_ROTARYA__AUART2_RTS MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) -#define MX23_PAD_ROTARYB__AUART2_CTS MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_1) - -/* MUXSEL_2 */ -#define MX23_PAD_GPMI_D00__SSP2_DATA0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D01__SSP2_DATA1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D02__SSP2_DATA2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D03__SSP2_DATA3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D04__SSP2_DATA4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D05__SSP2_DATA5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D06__SSP2_DATA6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D07__SSP2_DATA7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D08__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D09__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D10__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D11__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D15__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_RDY0__SSP2_DETECT MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_RDY1__SSP2_CMD MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_WRN__SSP2_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_CTS__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_RTS__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_RX__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_TX__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2) -#define MX23_PAD_I2C_SCL__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2) -#define MX23_PAD_I2C_SDA__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2) - -#define MX23_PAD_LCD_D08__SAIF2_SDATA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D09__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D11__SAIF_LRCLK MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D12__SAIF2_SDATA1 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D13__SAIF2_SDATA2 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D14__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D15__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) -#define MX23_PAD_LCD_RESET__GPMI_CE3N MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) -#define MX23_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2) -#define MX23_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2) -#define MX23_PAD_PWM3__AUART1_CTS MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) -#define MX23_PAD_PWM4__AUART1_RTS MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) - -#define MX23_PAD_SSP1_CMD__JTAG_TDO MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DETECT__USB_OTG_ID MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA0__JTAG_TDI MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA1__JTAG_TCLK MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA2__JTAG_RTCK MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA3__JTAG_TMS MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_SCK__JTAG_TRST MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_2) -#define MX23_PAD_ROTARYA__SPDIF MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_2) -#define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2) - -/* MUXSEL_GPIO */ -#define MX23_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D08__GPIO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D09__GPIO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D10__GPIO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D11__GPIO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D12__GPIO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D13__GPIO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D14__GPIO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D15__GPIO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CLE__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_ALE__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY0__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY1__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY2__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY3__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_WPN__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_WRN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_CTS__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_RTS__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_RX__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_TX__GPIO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_I2C_SCL__GPIO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO) -#define MX23_PAD_I2C_SDA__GPIO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO) - -#define MX23_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_RESET__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_RS__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_WR__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_CS__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_DOTCK__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_ENABLE__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_HSYNC__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_VSYNC__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM0__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM1__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM2__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM3__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM4__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) - -#define MX23_PAD_SSP1_CMD__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DETECT__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA0__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA1__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA2__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA3__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_SCK__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_ROTARYA__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_ROTARYB__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A00__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A01__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A02__GPIO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A03__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A04__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A05__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A06__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A07__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A08__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A09__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A10__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A11__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A12__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_BA0__GPIO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_BA1__GPIO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CASN__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CE0N__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CE1N__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE1N__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE0N__GPIO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CKE__GPIO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_RASN__GPIO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_WEN__GPIO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO) - -#endif /* __MACH_IOMUX_MX23_H__ */ diff --git a/trunk/arch/arm/mach-mxs/include/mach/iomux-mx28.h b/trunk/arch/arm/mach-mxs/include/mach/iomux-mx28.h deleted file mode 100644 index f50fefd10520..000000000000 --- a/trunk/arch/arm/mach-mxs/include/mach/iomux-mx28.h +++ /dev/null @@ -1,537 +0,0 @@ -/* - * Copyright (C) 2009-2010 Amit Kucheria - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __MACH_IOMUX_MX28_H__ -#define __MACH_IOMUX_MX28_H__ - -#include - -/* - * The naming convention for the pad modes is MX28_PAD___ - * If or refers to a GPIO, it is named GPIO__ - * See also iomux.h - * - * BANK PIN MUX - */ -/* MUXSEL_0 */ -#define MX28_PAD_GPMI_D00__GPMI_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D01__GPMI_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D02__GPMI_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D04__GPMI_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D05__GPMI_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D07__GPMI_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE3N__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY0__GPMI_READY0 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY1__GPMI_READY1 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY2__GPMI_READY2 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY3__GPMI_READY3 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RESETN__GPMI_RESETN MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) - -#define MX28_PAD_LCD_D00__LCD_D0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D01__LCD_D1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D02__LCD_D2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D04__LCD_D4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D05__LCD_D5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D07__LCD_D7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D08__LCD_D8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D09__LCD_D9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D18__LCD_D18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D19__LCD_D19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D20__LCD_D20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D21__LCD_D21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D22__LCD_D22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D23__LCD_D23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RD_E__LCD_RD_E MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) -#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) -#define MX28_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) -#define MX28_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) -#define MX28_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) -#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) -#define MX28_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0) - -#define MX28_PAD_SSP0_DATA0__SSP0_D0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA1__SSP0_D1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA2__SSP0_D2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA4__SSP0_D4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA5__SSP0_D5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA7__SSP0_D7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_CMD__SSP0_CMD MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_SCK__SSP0_SCK MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_DATA0__SSP1_D0 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_DATA3__SSP1_D3 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SCK__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_MOSI__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_MISO__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS0__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS1__SSP2_D4 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS2__SSP2_D5 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_SCK__SSP3_SCK MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_MOSI__SSP3_CMD MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_MISO__SSP3_D0 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_SS0__SSP3_D3 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) - -#define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_RX__AUART2_RX MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_TX__AUART2_TX MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_CTS__AUART2_CTS MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_RTS__AUART2_RTS MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_RX__AUART3_RX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_TX__AUART3_TX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_CTS__AUART3_CTS MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_RTS__AUART3_RTS MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) -#define MX28_PAD_PWM0__PWM_0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) -#define MX28_PAD_PWM1__PWM_1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) -#define MX28_PAD_PWM2__PWM_2 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0) -#define MX28_PAD_I2C0_SCL__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0) -#define MX28_PAD_I2C0_SDA__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0) -#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0) -#define MX28_PAD_SPDIF__SPDIF_TX MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0) -#define MX28_PAD_PWM3__PWM_3 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0) -#define MX28_PAD_PWM4__PWM_4 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0) - -#define MX28_PAD_ENET0_MDC__ENET0_MDC MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_MDIO__ENET0_MDIO MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_COL__ENET0_COL MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_CRS__ENET0_CRS MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0) -#define MX28_PAD_ENET_CLK__CLKCTRL_ENET MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0) -#define MX28_PAD_JTAG_RTCK__JTAG_RTCK MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0) - -#define MX28_PAD_EMI_D00__EMI_DATA0 MXS_IOMUX_PAD_NAKED(5, 0, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D01__EMI_DATA1 MXS_IOMUX_PAD_NAKED(5, 1, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D02__EMI_DATA2 MXS_IOMUX_PAD_NAKED(5, 2, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D03__EMI_DATA3 MXS_IOMUX_PAD_NAKED(5, 3, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D04__EMI_DATA4 MXS_IOMUX_PAD_NAKED(5, 4, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D05__EMI_DATA5 MXS_IOMUX_PAD_NAKED(5, 5, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D07__EMI_DATA7 MXS_IOMUX_PAD_NAKED(5, 7, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D08__EMI_DATA8 MXS_IOMUX_PAD_NAKED(5, 8, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D09__EMI_DATA9 MXS_IOMUX_PAD_NAKED(5, 9, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D10__EMI_DATA10 MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D11__EMI_DATA11 MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D12__EMI_DATA12 MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D13__EMI_DATA13 MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D14__EMI_DATA14 MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D15__EMI_DATA15 MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0) -#define MX28_PAD_EMI_ODT0__EMI_ODT0 MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0) -#define MX28_PAD_EMI_ODT1__EMI_ODT1 MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0) - -#define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A04__EMI_ADDR4 MXS_IOMUX_PAD_NAKED(6, 4, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A05__EMI_ADDR5 MXS_IOMUX_PAD_NAKED(6, 5, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A06__EMI_ADDR6 MXS_IOMUX_PAD_NAKED(6, 6, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A07__EMI_ADDR7 MXS_IOMUX_PAD_NAKED(6, 7, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A08__EMI_ADDR8 MXS_IOMUX_PAD_NAKED(6, 8, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A09__EMI_ADDR9 MXS_IOMUX_PAD_NAKED(6, 9, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A10__EMI_ADDR10 MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A11__EMI_ADDR11 MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A12__EMI_ADDR12 MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A13__EMI_ADDR13 MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A14__EMI_ADDR14 MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA2__EMI_BA2 MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0) -#define MX28_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0) -#define MX28_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0) - -/* MUXSEL_1 */ -#define MX28_PAD_GPMI_D00__SSP1_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D01__SSP1_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D02__SSP1_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D03__SSP1_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D04__SSP1_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D05__SSP1_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D06__SSP1_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D07__SSP1_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE0N__SSP3_D0 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE1N__SSP3_D3 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE2N__CAN1_TX MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE3N__CAN1_RX MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY1__SSP1_CMD MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY2__CAN0_TX MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY3__CAN0_RX MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDN__SSP3_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_WRN__SSP1_SCK MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_ALE__SSP3_D1 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CLE__SSP3_D2 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RESETN__SSP3_CMD MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) - -#define MX28_PAD_LCD_D03__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D04__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D08__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D09__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RD_E__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) -#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RS__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) -#define MX28_PAD_LCD_CS__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) -#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) -#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) -#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) - -#define MX28_PAD_SSP0_DATA4__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA5__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA6__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA7__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_SCK__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_CMD__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_DATA0__SSP2_D6 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_DATA3__SSP2_D7 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SCK__AUART2_RX MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_MOSI__AUART2_TX MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_MISO__AUART3_RX MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS0__AUART3_TX MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS1__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS2__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_SCK__AUART4_TX MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_MOSI__AUART4_RX MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_MISO__AUART4_RTS MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_SS0__AUART4_CTS MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1) - -#define MX28_PAD_AUART0_RX__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_TX__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_CTS__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_RTS__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_RTS__USB0_ID MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_RX__SSP3_D1 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_TX__SSP3_D2 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_CTS__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_RTS__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_RX__CAN0_TX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_TX__CAN0_RX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_CTS__CAN1_TX MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_RTS__CAN1_RX MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1) -#define MX28_PAD_PWM0__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1) -#define MX28_PAD_PWM1__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1) -#define MX28_PAD_PWM2__USB0_ID MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_MCLK__PWM_3 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_LRCLK__PWM_4 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_BITCLK__PWM_5 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_SDATA0__PWM_6 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1) -#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1) -#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1) -#define MX28_PAD_SAIF1_SDATA0__PWM_7 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RESET__LCD_VSYNC MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1) - -#define MX28_PAD_ENET0_MDC__GPMI_CE4N MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_MDIO__GPMI_CE5N MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD0__GPMI_CE7N MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD1__GPMI_READY4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD0__GPMI_READY6 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD1__GPMI_READY7 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_COL__ENET1_TX_EN MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_CRS__ENET1_RX_EN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1) - -/* MUXSEL_2 */ -#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY0__USB0_ID MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_ALE__SSP3_D4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_CLE__SSP3_D5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) - -#define MX28_PAD_LCD_D00__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D01__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D02__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D03__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D04__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D05__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D06__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D07__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D08__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D09__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D10__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D11__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D12__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D13__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D14__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D15__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D16__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D17__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D18__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D19__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D20__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D21__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D22__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D23__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2) -#define MX28_PAD_LCD_RD_E__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2) -#define MX28_PAD_LCD_WR_RWN__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2) -#define MX28_PAD_LCD_HSYNC__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) -#define MX28_PAD_LCD_DOTCLK__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) - -#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2) - -#define MX28_PAD_AUART0_RX__DUART_CTS MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_TX__DUART_RTS MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_CTS__DUART_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_RTS__DUART_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_RX__PWM_0 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_TX__PWM_1 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_RX__SSP3_D4 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_TX__SSP3_D5 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2) -#define MX28_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2) -#define MX28_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2) -#define MX28_PAD_PWM2__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_MCLK__AUART4_CTS MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_BITCLK__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_SDATA0__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2) -#define MX28_PAD_I2C0_SCL__DUART_RX MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2) -#define MX28_PAD_I2C0_SDA__DUART_TX MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2) -#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2) -#define MX28_PAD_SPDIF__ENET1_RX_ER MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2) - -#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2) - -/* MUXSEL_GPIO */ -#define MX28_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE0N__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE1N__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE3N__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY0__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY1__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY2__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY3__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_WRN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_ALE__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CLE__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RESETN__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) - -#define MX28_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D18__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D19__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D20__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D21__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D22__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D23__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RD_E__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RS__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_CS__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_VSYNC__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_HSYNC__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_ENABLE__GPIO_1_31 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO) - -#define MX28_PAD_SSP0_DATA0__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA1__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA2__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA3__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA4__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA5__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA6__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA7__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_CMD__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DETECT__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_SCK__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_SCK__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_CMD__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_DATA0__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_DATA3__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SCK__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_MOSI__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_MISO__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS0__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS1__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS2__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_SCK__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_MOSI__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_MISO__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_SS0__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) - -#define MX28_PAD_AUART0_RX__GPIO_3_0 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_TX__GPIO_3_1 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_CTS__GPIO_3_2 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_RTS__GPIO_3_3 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_RX__GPIO_3_4 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_TX__GPIO_3_5 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_CTS__GPIO_3_6 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_RTS__GPIO_3_7 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_RX__GPIO_3_8 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_TX__GPIO_3_9 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_CTS__GPIO_3_10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_RTS__GPIO_3_11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_RX__GPIO_3_12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_TX__GPIO_3_13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_CTS__GPIO_3_14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_RTS__GPIO_3_15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM0__GPIO_3_16 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM1__GPIO_3_17 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM2__GPIO_3_18 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_I2C0_SCL__GPIO_3_24 MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_I2C0_SDA__GPIO_3_25 MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_SPDIF__GPIO_3_27 MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM3__GPIO_3_28 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM4__GPIO_3_29 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RESET__GPIO_3_30 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO) - -#define MX28_PAD_ENET0_MDC__GPIO_4_0 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_MDIO__GPIO_4_1 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD0__GPIO_4_3 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD1__GPIO_4_4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD0__GPIO_4_7 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD1__GPIO_4_8 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD2__GPIO_4_9 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD3__GPIO_4_10 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD2__GPIO_4_11 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD3__GPIO_4_12 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_COL__GPIO_4_14 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_CRS__GPIO_4_15 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET_CLK__GPIO_4_16 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_JTAG_RTCK__GPIO_4_20 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO) - -#endif /* __MACH_IOMUX_MX28_H__ */ diff --git a/trunk/arch/arm/mach-mxs/include/mach/iomux.h b/trunk/arch/arm/mach-mxs/include/mach/iomux.h deleted file mode 100644 index 7abdf58b8bb7..000000000000 --- a/trunk/arch/arm/mach-mxs/include/mach/iomux.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_MXS_IOMUX_H__ -#define __MACH_MXS_IOMUX_H__ - -/* - * IOMUX/PAD Bit field definitions - * - * PAD_BANK: 0..2 (3) - * PAD_PIN: 3..7 (5) - * PAD_MUXSEL: 8..9 (2) - * PAD_MA: 10..11 (2) - * PAD_MA_VALID: 12 (1) - * PAD_VOL: 13 (1) - * PAD_VOL_VALID: 14 (1) - * PAD_PULL: 15 (1) - * PAD_PULL_VALID: 16 (1) - * RESERVED: 17..31 (15) - */ -typedef u32 iomux_cfg_t; - -#define MXS_PAD_BANK_SHIFT 0 -#define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT) -#define MXS_PAD_PIN_SHIFT 3 -#define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT) -#define MXS_PAD_MUXSEL_SHIFT 8 -#define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT) -#define MXS_PAD_MA_SHIFT 10 -#define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT) -#define MXS_PAD_MA_VALID_SHIFT 12 -#define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT) -#define MXS_PAD_VOL_SHIFT 13 -#define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT) -#define MXS_PAD_VOL_VALID_SHIFT 14 -#define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT) -#define MXS_PAD_PULL_SHIFT 15 -#define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT) -#define MXS_PAD_PULL_VALID_SHIFT 16 -#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT) - -#define PAD_MUXSEL_0 0 -#define PAD_MUXSEL_1 1 -#define PAD_MUXSEL_2 2 -#define PAD_MUXSEL_GPIO 3 - -#define PAD_4MA 0 -#define PAD_8MA 1 -#define PAD_12MA 2 -#define PAD_16MA 3 - -#define PAD_1V8 0 -#define PAD_3V3 1 - -#define PAD_NOPULL 0 -#define PAD_PULLUP 1 - -#define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_8MA ((PAD_8MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_12MA ((PAD_12MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_16MA ((PAD_16MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) - -#define MXS_PAD_1V8 ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \ - MXS_PAD_VOL_VALID_MASK) -#define MXS_PAD_3V3 ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \ - MXS_PAD_VOL_VALID_MASK) - -#define MXS_PAD_NOPULL ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \ - MXS_PAD_PULL_VALID_MASK) -#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ - MXS_PAD_PULL_VALID_MASK) - -/* generic pad control used in most cases */ -#define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL) - -#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ - (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ - ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ - ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \ - ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \ - ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \ - ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT)) - -/* - * A pad becomes naked, when none of mA, vol or pull - * validity bits is set. - */ -#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \ - MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0) - -static inline unsigned int PAD_BANK(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT; -} - -static inline unsigned int PAD_PIN(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT; -} - -static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT; -} - -static inline unsigned int PAD_MA(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT; -} - -static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT; -} - -static inline unsigned int PAD_VOL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT; -} - -static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT; -} - -static inline unsigned int PAD_PULL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT; -} - -static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT; -} - -/* - * configures a single pad in the iomuxer - */ -int mxs_iomux_setup_pad(iomux_cfg_t pad); - -/* - * configures multiple pads - * convenient way to call the above function with tables - */ -int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count); - -#endif /* __MACH_MXS_IOMUX_H__*/ diff --git a/trunk/arch/arm/mach-mxs/iomux.c b/trunk/arch/arm/mach-mxs/iomux.c deleted file mode 100644 index 0e804e2f11f4..000000000000 --- a/trunk/arch/arm/mach-mxs/iomux.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -/* - * configures a single pad in the iomuxer - */ -int mxs_iomux_setup_pad(iomux_cfg_t pad) -{ - u32 reg, ofs, bp, bm; - void __iomem *iomux_base = MXS_IO_ADDRESS(MXS_PINCTRL_BASE_ADDR); - - /* muxsel */ - ofs = 0x100; - ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10; - bp = PAD_PIN(pad) % 16 * 2; - bm = 0x3 << bp; - reg = __raw_readl(iomux_base + ofs); - reg &= ~bm; - reg |= PAD_MUXSEL(pad) << bp; - __raw_writel(reg, iomux_base + ofs); - - /* drive */ - ofs = cpu_is_mx23() ? 0x200 : 0x300; - ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10; - /* mA */ - if (PAD_MA_VALID(pad)) { - bp = PAD_PIN(pad) % 8 * 4; - bm = 0x3 << bp; - reg = __raw_readl(iomux_base + ofs); - reg &= ~bm; - reg |= PAD_MA(pad) << bp; - __raw_writel(reg, iomux_base + ofs); - } - /* vol */ - if (PAD_VOL_VALID(pad)) { - bp = PAD_PIN(pad) % 8 * 4 + 2; - if (PAD_VOL(pad)) - __mxs_setl(1 << bp, iomux_base + ofs); - else - __mxs_clrl(1 << bp, iomux_base + ofs); - } - - /* pull */ - if (PAD_PULL_VALID(pad)) { - ofs = cpu_is_mx23() ? 0x400 : 0x600; - ofs += PAD_BANK(pad) * 0x10; - bp = PAD_PIN(pad); - if (PAD_PULL(pad)) - __mxs_setl(1 << bp, iomux_base + ofs); - else - __mxs_clrl(1 << bp, iomux_base + ofs); - } - - return 0; -} - -int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count) -{ - const iomux_cfg_t *p = pad_list; - int i; - int ret; - - for (i = 0; i < count; i++) { - ret = mxs_iomux_setup_pad(*p); - if (ret) - return ret; - p++; - } - - return 0; -} diff --git a/trunk/arch/arm/mach-mxs/mach-apx4devkit.c b/trunk/arch/arm/mach-mxs/mach-apx4devkit.c deleted file mode 100644 index f5f061757deb..000000000000 --- a/trunk/arch/arm/mach-mxs/mach-apx4devkit.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (C) 2011-2012 - * Lauri Hintsala, Bluegiga, - * Veli-Pekka Peltola, Bluegiga, - * - * based on: mach-mx28evk.c - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "devices-mx28.h" - -#define APX4DEVKIT_GPIO_USERLED MXS_GPIO_NR(3, 28) - -static const iomux_cfg_t apx4devkit_pads[] __initconst = { - /* duart */ - MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, - MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL, - - /* auart0 */ - MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL, - MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL, - MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL, - MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL, - - /* auart1 */ - MX28_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL, - MX28_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL, - - /* auart2 */ - MX28_PAD_SSP2_SCK__AUART2_RX | MXS_PAD_CTRL, - MX28_PAD_SSP2_MOSI__AUART2_TX | MXS_PAD_CTRL, - - /* auart3 */ - MX28_PAD_SSP2_MISO__AUART3_RX | MXS_PAD_CTRL, - MX28_PAD_SSP2_SS0__AUART3_TX | MXS_PAD_CTRL, - -#define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP) - /* fec0 */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC, - - /* i2c */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - - /* mmc0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA1__SSP0_D1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA2__SSP0_D2 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA3__SSP0_D3 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA4__SSP0_D4 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA5__SSP0_D5 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA6__SSP0_D6 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA7__SSP0_D7 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_CMD__SSP0_CMD | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - - /* led */ - MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL, - - /* saif0 & saif1 */ - MX28_PAD_SAIF0_MCLK__SAIF0_MCLK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), -}; - -/* led */ -static const struct gpio_led apx4devkit_leds[] __initconst = { - { - .name = "user-led", - .default_trigger = "heartbeat", - .gpio = APX4DEVKIT_GPIO_USERLED, - }, -}; - -static const struct gpio_led_platform_data apx4devkit_led_data __initconst = { - .leds = apx4devkit_leds, - .num_leds = ARRAY_SIZE(apx4devkit_leds), -}; - -static const struct fec_platform_data mx28_fec_pdata __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static const struct mxs_mmc_platform_data apx4devkit_mmc_pdata __initconst = { - .wp_gpio = -EINVAL, - .flags = SLOTF_4_BIT_CAPABLE, -}; - -static const struct i2c_board_info apx4devkit_i2c_boardinfo[] __initconst = { - { I2C_BOARD_INFO("sgtl5000", 0x0a) }, /* ASoC */ - { I2C_BOARD_INFO("pcf8563", 0x51) }, /* RTC */ -}; - -#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || \ - defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) -static struct regulator_consumer_supply apx4devkit_audio_consumer_supplies[] = { - REGULATOR_SUPPLY("VDDA", "0-000a"), - REGULATOR_SUPPLY("VDDIO", "0-000a"), -}; - -static struct regulator_init_data apx4devkit_vdd_reg_init_data = { - .constraints = { - .name = "3V3", - .always_on = 1, - }, - .consumer_supplies = apx4devkit_audio_consumer_supplies, - .num_consumer_supplies = ARRAY_SIZE(apx4devkit_audio_consumer_supplies), -}; - -static struct fixed_voltage_config apx4devkit_vdd_pdata = { - .supply_name = "board-3V3", - .microvolts = 3300000, - .gpio = -EINVAL, - .enabled_at_boot = 1, - .init_data = &apx4devkit_vdd_reg_init_data, -}; - -static struct platform_device apx4devkit_voltage_regulator = { - .name = "reg-fixed-voltage", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &apx4devkit_vdd_pdata, - }, -}; - -static void __init apx4devkit_add_regulators(void) -{ - platform_device_register(&apx4devkit_voltage_regulator); -} -#else -static void __init apx4devkit_add_regulators(void) {} -#endif - -static const struct mxs_saif_platform_data - apx4devkit_mxs_saif_pdata[] __initconst = { - /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */ - { - .master_mode = 1, - .master_id = 0, - }, { - .master_mode = 0, - .master_id = 0, - }, -}; - -static int apx4devkit_phy_fixup(struct phy_device *phy) -{ - phy->dev_flags |= MICREL_PHY_50MHZ_CLK; - return 0; -} - -static void __init apx4devkit_fec_phy_clk_enable(void) -{ - struct clk *clk; - - /* Enable fec phy clock */ - clk = clk_get_sys("enet_out", NULL); - if (!IS_ERR(clk)) - clk_prepare_enable(clk); -} - -static void __init apx4devkit_init(void) -{ - mx28_soc_init(); - - mxs_iomux_setup_multiple_pads(apx4devkit_pads, - ARRAY_SIZE(apx4devkit_pads)); - - mx28_add_duart(); - mx28_add_auart0(); - mx28_add_auart1(); - mx28_add_auart2(); - mx28_add_auart3(); - - /* - * Register fixup for the Micrel KS8031 PHY clock - * (shares same ID with KS8051) - */ - phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK, - apx4devkit_phy_fixup); - - apx4devkit_fec_phy_clk_enable(); - mx28_add_fec(0, &mx28_fec_pdata); - - mx28_add_mxs_mmc(0, &apx4devkit_mmc_pdata); - - gpio_led_register_device(0, &apx4devkit_led_data); - - mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); - mx28_add_saif(0, &apx4devkit_mxs_saif_pdata[0]); - mx28_add_saif(1, &apx4devkit_mxs_saif_pdata[1]); - - apx4devkit_add_regulators(); - - mx28_add_mxs_i2c(0); - i2c_register_board_info(0, apx4devkit_i2c_boardinfo, - ARRAY_SIZE(apx4devkit_i2c_boardinfo)); - - mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0, NULL, 0); -} - -static void __init apx4devkit_timer_init(void) -{ - mx28_clocks_init(); -} - -static struct sys_timer apx4devkit_timer = { - .init = apx4devkit_timer_init, -}; - -MACHINE_START(APX4DEVKIT, "Bluegiga APX4 Development Kit") - .map_io = mx28_map_io, - .init_irq = mx28_init_irq, - .timer = &apx4devkit_timer, - .init_machine = apx4devkit_init, - .restart = mxs_restart, -MACHINE_END diff --git a/trunk/arch/arm/mach-mxs/mach-m28evk.c b/trunk/arch/arm/mach-mxs/mach-m28evk.c deleted file mode 100644 index 4c00c879b893..000000000000 --- a/trunk/arch/arm/mach-mxs/mach-m28evk.c +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, - * - * based on: mach-mx28_evk.c - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include "devices-mx28.h" - -#define M28EVK_GPIO_USERLED1 MXS_GPIO_NR(3, 16) -#define M28EVK_GPIO_USERLED2 MXS_GPIO_NR(3, 17) - -#define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18) -#define M28EVK_LCD_ENABLE MXS_GPIO_NR(3, 28) - -#define MX28EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(2, 12) -#define MX28EVK_MMC1_WRITE_PROTECT MXS_GPIO_NR(0, 28) - -static const iomux_cfg_t m28evk_pads[] __initconst = { - /* duart */ - MX28_PAD_AUART0_CTS__DUART_RX | MXS_PAD_CTRL, - MX28_PAD_AUART0_RTS__DUART_TX | MXS_PAD_CTRL, - - /* auart0 */ - MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL, - MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL, - - /* auart3 */ - MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL, - MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL, - MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL, - MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL, - -#define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP) - /* fec0 */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC, - /* fec1 */ - MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC, - MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC, - - /* flexcan0 */ - MX28_PAD_GPMI_RDY2__CAN0_TX, - MX28_PAD_GPMI_RDY3__CAN0_RX, - - /* flexcan1 */ - MX28_PAD_GPMI_CE2N__CAN1_TX, - MX28_PAD_GPMI_CE3N__CAN1_RX, - - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - - /* mxsfb (lcdif) */ - MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL, - MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL, - MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL, - MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL, - MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL, - MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL, - MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL, - MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL, - MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL, - MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL, - MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL, - MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL, - MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL, - MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL, - MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL, - MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL, - MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL, - MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL, - MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL, - MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL, - MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL, - MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL, - MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL, - MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL, - - MX28_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL, - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL, - - /* mmc0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA1__SSP0_D1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA2__SSP0_D2 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA3__SSP0_D3 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA4__SSP0_D4 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA5__SSP0_D5 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA6__SSP0_D6 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA7__SSP0_D7 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_CMD__SSP0_CMD | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - - /* mmc1 */ - MX28_PAD_GPMI_D00__SSP1_D0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D01__SSP1_D1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D02__SSP1_D2 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D03__SSP1_D3 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D04__SSP1_D4 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D05__SSP1_D5 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D06__SSP1_D6 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D07__SSP1_D7 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_RDY1__SSP1_CMD | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_WRN__SSP1_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* write protect */ - MX28_PAD_GPMI_RESETN__GPIO_0_28 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* slot power enable */ - MX28_PAD_PWM4__GPIO_3_29 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - - /* led */ - MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL, - MX28_PAD_PWM1__GPIO_3_17 | MXS_PAD_CTRL, - - /* nand */ - MX28_PAD_GPMI_D00__GPMI_D0 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_D01__GPMI_D1 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_D02__GPMI_D2 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_D03__GPMI_D3 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_D04__GPMI_D4 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_D05__GPMI_D5 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_D06__GPMI_D6 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_D07__GPMI_D7 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_CE0N__GPMI_CE0N | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_RDY0__GPMI_READY0 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_RDN__GPMI_RDN | - (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_WRN__GPMI_WRN | - (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_ALE__GPMI_ALE | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_CLE__GPMI_CLE | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_RESETN__GPMI_RESETN | - (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), - - /* Backlight */ - MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL, -}; - -/* led */ -static const struct gpio_led m28evk_leds[] __initconst = { - { - .name = "user-led1", - .default_trigger = "heartbeat", - .gpio = M28EVK_GPIO_USERLED1, - }, - { - .name = "user-led2", - .default_trigger = "heartbeat", - .gpio = M28EVK_GPIO_USERLED2, - }, -}; - -static const struct gpio_led_platform_data m28evk_led_data __initconst = { - .leds = m28evk_leds, - .num_leds = ARRAY_SIZE(m28evk_leds), -}; - -static struct fec_platform_data mx28_fec_pdata[] __initdata = { - { - /* fec0 */ - .phy = PHY_INTERFACE_MODE_RMII, - }, { - /* fec1 */ - .phy = PHY_INTERFACE_MODE_RMII, - }, -}; - -static int __init m28evk_fec_get_mac(void) -{ - int i; - u32 val; - const u32 *ocotp = mxs_get_ocotp(); - - if (!ocotp) - return -ETIMEDOUT; - - /* - * OCOTP only stores the last 4 octets for each mac address, - * so hard-code DENX OUI (C0:E5:4E) here. - */ - for (i = 0; i < 2; i++) { - val = ocotp[i]; - mx28_fec_pdata[i].mac[0] = 0xC0; - mx28_fec_pdata[i].mac[1] = 0xE5; - mx28_fec_pdata[i].mac[2] = 0x4E; - mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff; - mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff; - mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff; - } - - return 0; -} - -/* mxsfb (lcdif) */ -static struct fb_videomode m28evk_video_modes[] = { - { - .name = "Ampire AM-800480R2TMQW-T01H", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 30066, /* picosecond (33.26 MHz) */ - .left_margin = 0, - .right_margin = 256, - .upper_margin = 0, - .lower_margin = 45, - .hsync_len = 1, - .vsync_len = 1, - .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, - }, -}; - -static const struct mxsfb_platform_data m28evk_mxsfb_pdata __initconst = { - .mode_list = m28evk_video_modes, - .mode_count = ARRAY_SIZE(m28evk_video_modes), - .default_bpp = 16, - .ld_intf_width = STMLCDIF_18BIT, -}; - -static struct at24_platform_data m28evk_eeprom = { - .byte_len = 16384, - .page_size = 32, - .flags = AT24_FLAG_ADDR16, -}; - -static struct i2c_board_info m28_stk5v3_i2c_boardinfo[] __initdata = { - { - I2C_BOARD_INFO("at24", 0x51), /* E0=1, E1=0, E2=0 */ - .platform_data = &m28evk_eeprom, - }, -}; - -static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = { - { - /* mmc0 */ - .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT, - .flags = SLOTF_8_BIT_CAPABLE, - }, { - /* mmc1 */ - .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT, - .flags = SLOTF_8_BIT_CAPABLE, - }, -}; - -static void __init m28evk_init(void) -{ - mx28_soc_init(); - - mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads)); - - mx28_add_duart(); - mx28_add_auart0(); - mx28_add_auart3(); - - if (!m28evk_fec_get_mac()) { - mx28_add_fec(0, &mx28_fec_pdata[0]); - mx28_add_fec(1, &mx28_fec_pdata[1]); - } - - mx28_add_flexcan(0, NULL); - mx28_add_flexcan(1, NULL); - - mx28_add_mxsfb(&m28evk_mxsfb_pdata); - - mx28_add_mxs_mmc(0, &m28evk_mmc_pdata[0]); - mx28_add_mxs_mmc(1, &m28evk_mmc_pdata[1]); - - gpio_led_register_device(0, &m28evk_led_data); - - /* I2C */ - mx28_add_mxs_i2c(0); - i2c_register_board_info(0, m28_stk5v3_i2c_boardinfo, - ARRAY_SIZE(m28_stk5v3_i2c_boardinfo)); -} - -static void __init m28evk_timer_init(void) -{ - mx28_clocks_init(); -} - -static struct sys_timer m28evk_timer = { - .init = m28evk_timer_init, -}; - -MACHINE_START(M28EVK, "DENX M28 EVK") - .map_io = mx28_map_io, - .init_irq = mx28_init_irq, - .timer = &m28evk_timer, - .init_machine = m28evk_init, - .restart = mxs_restart, -MACHINE_END diff --git a/trunk/arch/arm/mach-mxs/mach-mx23evk.c b/trunk/arch/arm/mach-mxs/mach-mx23evk.c deleted file mode 100644 index e7272a41939d..000000000000 --- a/trunk/arch/arm/mach-mxs/mach-mx23evk.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include "devices-mx23.h" - -#define MX23EVK_LCD_ENABLE MXS_GPIO_NR(1, 18) -#define MX23EVK_BL_ENABLE MXS_GPIO_NR(1, 28) -#define MX23EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30) -#define MX23EVK_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29) - -static const iomux_cfg_t mx23evk_pads[] __initconst = { - /* duart */ - MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, - MX23_PAD_PWM1__DUART_TX | MXS_PAD_CTRL, - - /* auart */ - MX23_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL, - MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL, - MX23_PAD_AUART1_CTS__AUART1_CTS | MXS_PAD_CTRL, - MX23_PAD_AUART1_RTS__AUART1_RTS | MXS_PAD_CTRL, - - /* mxsfb (lcdif) */ - MX23_PAD_LCD_D00__LCD_D00 | MXS_PAD_CTRL, - MX23_PAD_LCD_D01__LCD_D01 | MXS_PAD_CTRL, - MX23_PAD_LCD_D02__LCD_D02 | MXS_PAD_CTRL, - MX23_PAD_LCD_D03__LCD_D03 | MXS_PAD_CTRL, - MX23_PAD_LCD_D04__LCD_D04 | MXS_PAD_CTRL, - MX23_PAD_LCD_D05__LCD_D05 | MXS_PAD_CTRL, - MX23_PAD_LCD_D06__LCD_D06 | MXS_PAD_CTRL, - MX23_PAD_LCD_D07__LCD_D07 | MXS_PAD_CTRL, - MX23_PAD_LCD_D08__LCD_D08 | MXS_PAD_CTRL, - MX23_PAD_LCD_D09__LCD_D09 | MXS_PAD_CTRL, - MX23_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL, - MX23_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL, - MX23_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL, - MX23_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL, - MX23_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL, - MX23_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL, - MX23_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL, - MX23_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL, - MX23_PAD_GPMI_D08__LCD_D18 | MXS_PAD_CTRL, - MX23_PAD_GPMI_D09__LCD_D19 | MXS_PAD_CTRL, - MX23_PAD_GPMI_D10__LCD_D20 | MXS_PAD_CTRL, - MX23_PAD_GPMI_D11__LCD_D21 | MXS_PAD_CTRL, - MX23_PAD_GPMI_D12__LCD_D22 | MXS_PAD_CTRL, - MX23_PAD_GPMI_D13__LCD_D23 | MXS_PAD_CTRL, - MX23_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL, - MX23_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL, - MX23_PAD_LCD_DOTCK__LCD_DOTCK | MXS_PAD_CTRL, - MX23_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL, - /* LCD panel enable */ - MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL, - /* backlight control */ - MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL, - - /* mmc */ - MX23_PAD_SSP1_DATA0__SSP1_DATA0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_DATA1__SSP1_DATA1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_DATA2__SSP1_DATA2 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_DATA3__SSP1_DATA3 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_GPMI_D08__SSP1_DATA4 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_GPMI_D09__SSP1_DATA5 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_GPMI_D10__SSP1_DATA6 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_GPMI_D11__SSP1_DATA7 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_CMD__SSP1_CMD | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_DETECT__SSP1_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX23_PAD_SSP1_SCK__SSP1_SCK | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* write protect */ - MX23_PAD_PWM4__GPIO_1_30 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* slot power enable */ - MX23_PAD_PWM3__GPIO_1_29 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), -}; - -/* mxsfb (lcdif) */ -static struct fb_videomode mx23evk_video_modes[] = { - { - .name = "Samsung-LMS430HF02", - .refresh = 60, - .xres = 480, - .yres = 272, - .pixclock = 108096, /* picosecond (9.2 MHz) */ - .left_margin = 15, - .right_margin = 8, - .upper_margin = 12, - .lower_margin = 4, - .hsync_len = 1, - .vsync_len = 1, - .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | - FB_SYNC_DOTCLK_FAILING_ACT, - }, -}; - -static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = { - .mode_list = mx23evk_video_modes, - .mode_count = ARRAY_SIZE(mx23evk_video_modes), - .default_bpp = 32, - .ld_intf_width = STMLCDIF_24BIT, -}; - -static struct mxs_mmc_platform_data mx23evk_mmc_pdata __initdata = { - .wp_gpio = MX23EVK_MMC0_WRITE_PROTECT, - .flags = SLOTF_8_BIT_CAPABLE, -}; - -static void __init mx23evk_init(void) -{ - int ret; - - mx23_soc_init(); - - mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads)); - - mx23_add_duart(); - mx23_add_auart0(); - - /* power on mmc slot by writing 0 to the gpio */ - ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, - "mmc0-slot-power"); - if (ret) - pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret); - mx23_add_mxs_mmc(0, &mx23evk_mmc_pdata); - - ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable"); - if (ret) - pr_warn("failed to request gpio lcd-enable: %d\n", ret); - else - gpio_set_value(MX23EVK_LCD_ENABLE, 1); - - ret = gpio_request_one(MX23EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable"); - if (ret) - pr_warn("failed to request gpio bl-enable: %d\n", ret); - else - gpio_set_value(MX23EVK_BL_ENABLE, 1); - - mx23_add_mxsfb(&mx23evk_mxsfb_pdata); - mx23_add_rtc_stmp3xxx(); -} - -static void __init mx23evk_timer_init(void) -{ - mx23_clocks_init(); -} - -static struct sys_timer mx23evk_timer = { - .init = mx23evk_timer_init, -}; - -MACHINE_START(MX23EVK, "Freescale MX23 EVK") - /* Maintainer: Freescale Semiconductor, Inc. */ - .map_io = mx23_map_io, - .init_irq = mx23_init_irq, - .timer = &mx23evk_timer, - .init_machine = mx23evk_init, - .restart = mxs_restart, -MACHINE_END diff --git a/trunk/arch/arm/mach-mxs/mach-mx28evk.c b/trunk/arch/arm/mach-mxs/mach-mx28evk.c deleted file mode 100644 index dafd48e86c8c..000000000000 --- a/trunk/arch/arm/mach-mxs/mach-mx28evk.c +++ /dev/null @@ -1,477 +0,0 @@ -/* - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "devices-mx28.h" - -#define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13) -#define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15) -#define MX28EVK_GPIO_LED MXS_GPIO_NR(3, 5) -#define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18) -#define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30) -#define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) - -#define MX28EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(2, 12) -#define MX28EVK_MMC1_WRITE_PROTECT MXS_GPIO_NR(0, 28) -#define MX28EVK_MMC0_SLOT_POWER MXS_GPIO_NR(3, 28) -#define MX28EVK_MMC1_SLOT_POWER MXS_GPIO_NR(3, 29) - -static const iomux_cfg_t mx28evk_pads[] __initconst = { - /* duart */ - MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, - MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL, - - /* auart0 */ - MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL, - MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL, - MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL, - MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL, - /* auart3 */ - MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL, - MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL, - MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL, - MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL, - -#define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP) - /* fec0 */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC, - /* fec1 */ - MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC, - MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC, - /* phy power line */ - MX28_PAD_SSP1_DATA3__GPIO_2_15 | MXS_PAD_CTRL, - /* phy reset line */ - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MXS_PAD_CTRL, - - /* flexcan0 */ - MX28_PAD_GPMI_RDY2__CAN0_TX, - MX28_PAD_GPMI_RDY3__CAN0_RX, - /* flexcan1 */ - MX28_PAD_GPMI_CE2N__CAN1_TX, - MX28_PAD_GPMI_CE3N__CAN1_RX, - /* transceiver power control */ - MX28_PAD_SSP1_CMD__GPIO_2_13, - - /* mxsfb (lcdif) */ - MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL, - MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL, - MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL, - MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL, - MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL, - MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL, - MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL, - MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL, - MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL, - MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL, - MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL, - MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL, - MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL, - MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL, - MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL, - MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL, - MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL, - MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL, - MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL, - MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL, - MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL, - MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL, - MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL, - MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL, - MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL, - MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL, - MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL, - MX28_PAD_LCD_CS__LCD_ENABLE | MXS_PAD_CTRL, - /* LCD panel enable */ - MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL, - /* backlight control */ - MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL, - /* mmc0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA1__SSP0_D1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA2__SSP0_D2 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA3__SSP0_D3 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA4__SSP0_D4 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA5__SSP0_D5 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA6__SSP0_D6 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA7__SSP0_D7 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_CMD__SSP0_CMD | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* write protect */ - MX28_PAD_SSP1_SCK__GPIO_2_12 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* slot power enable */ - MX28_PAD_PWM3__GPIO_3_28 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - - /* mmc1 */ - MX28_PAD_GPMI_D00__SSP1_D0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D01__SSP1_D1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D02__SSP1_D2 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D03__SSP1_D3 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D04__SSP1_D4 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D05__SSP1_D5 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D06__SSP1_D6 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D07__SSP1_D7 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_RDY1__SSP1_CMD | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_WRN__SSP1_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* write protect */ - MX28_PAD_GPMI_RESETN__GPIO_0_28 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* slot power enable */ - MX28_PAD_PWM4__GPIO_3_29 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - - /* led */ - MX28_PAD_AUART1_TX__GPIO_3_5 | MXS_PAD_CTRL, - - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_I2C0_SDA__I2C0_SDA | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - - /* saif0 & saif1 */ - MX28_PAD_SAIF0_MCLK__SAIF0_MCLK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), -}; - -/* led */ -static const struct gpio_led mx28evk_leds[] __initconst = { - { - .name = "GPIO-LED", - .default_trigger = "heartbeat", - .gpio = MX28EVK_GPIO_LED, - }, -}; - -static const struct gpio_led_platform_data mx28evk_led_data __initconst = { - .leds = mx28evk_leds, - .num_leds = ARRAY_SIZE(mx28evk_leds), -}; - -/* fec */ -static void __init mx28evk_fec_reset(void) -{ - struct clk *clk; - - /* Enable fec phy clock */ - clk = clk_get_sys("enet_out", NULL); - if (!IS_ERR(clk)) - clk_prepare_enable(clk); - - gpio_set_value(MX28EVK_FEC_PHY_RESET, 0); - mdelay(1); - gpio_set_value(MX28EVK_FEC_PHY_RESET, 1); -} - -static struct fec_platform_data mx28_fec_pdata[] __initdata = { - { - /* fec0 */ - .phy = PHY_INTERFACE_MODE_RMII, - }, { - /* fec1 */ - .phy = PHY_INTERFACE_MODE_RMII, - }, -}; - -static int __init mx28evk_fec_get_mac(void) -{ - int i; - u32 val; - const u32 *ocotp = mxs_get_ocotp(); - - if (!ocotp) - return -ETIMEDOUT; - - /* - * OCOTP only stores the last 4 octets for each mac address, - * so hard-code Freescale OUI (00:04:9f) here. - */ - for (i = 0; i < 2; i++) { - val = ocotp[i]; - mx28_fec_pdata[i].mac[0] = 0x00; - mx28_fec_pdata[i].mac[1] = 0x04; - mx28_fec_pdata[i].mac[2] = 0x9f; - mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff; - mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff; - mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff; - } - - return 0; -} - -/* - * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers - */ -static int flexcan0_en, flexcan1_en; - -static void mx28evk_flexcan_switch(void) -{ - if (flexcan0_en || flexcan1_en) - gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1); - else - gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0); -} - -static void mx28evk_flexcan0_switch(int enable) -{ - flexcan0_en = enable; - mx28evk_flexcan_switch(); -} - -static void mx28evk_flexcan1_switch(int enable) -{ - flexcan1_en = enable; - mx28evk_flexcan_switch(); -} - -static const struct flexcan_platform_data - mx28evk_flexcan_pdata[] __initconst = { - { - .transceiver_switch = mx28evk_flexcan0_switch, - }, { - .transceiver_switch = mx28evk_flexcan1_switch, - } -}; - -/* mxsfb (lcdif) */ -static struct fb_videomode mx28evk_video_modes[] = { - { - .name = "Seiko-43WVF1G", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 29851, /* picosecond (33.5 MHz) */ - .left_margin = 89, - .right_margin = 164, - .upper_margin = 23, - .lower_margin = 10, - .hsync_len = 10, - .vsync_len = 10, - .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | - FB_SYNC_DOTCLK_FAILING_ACT, - }, -}; - -static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = { - .mode_list = mx28evk_video_modes, - .mode_count = ARRAY_SIZE(mx28evk_video_modes), - .default_bpp = 32, - .ld_intf_width = STMLCDIF_24BIT, -}; - -static struct mxs_mmc_platform_data mx28evk_mmc_pdata[] __initdata = { - { - /* mmc0 */ - .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT, - .flags = SLOTF_8_BIT_CAPABLE, - }, { - /* mmc1 */ - .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT, - .flags = SLOTF_8_BIT_CAPABLE, - }, -}; - -static struct i2c_board_info mxs_i2c0_board_info[] __initdata = { - { - I2C_BOARD_INFO("sgtl5000", 0x0a), - }, -}; - -#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) -static struct regulator_consumer_supply mx28evk_audio_consumer_supplies[] = { - REGULATOR_SUPPLY("VDDA", "0-000a"), - REGULATOR_SUPPLY("VDDIO", "0-000a"), -}; - -static struct regulator_init_data mx28evk_vdd_reg_init_data = { - .constraints = { - .name = "3V3", - .always_on = 1, - }, - .consumer_supplies = mx28evk_audio_consumer_supplies, - .num_consumer_supplies = ARRAY_SIZE(mx28evk_audio_consumer_supplies), -}; - -static struct fixed_voltage_config mx28evk_vdd_pdata = { - .supply_name = "board-3V3", - .microvolts = 3300000, - .gpio = -EINVAL, - .enabled_at_boot = 1, - .init_data = &mx28evk_vdd_reg_init_data, -}; -static struct platform_device mx28evk_voltage_regulator = { - .name = "reg-fixed-voltage", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &mx28evk_vdd_pdata, - }, -}; -static void __init mx28evk_add_regulators(void) -{ - platform_device_register(&mx28evk_voltage_regulator); -} -#else -static void __init mx28evk_add_regulators(void) {} -#endif - -static const struct gpio mx28evk_gpios[] __initconst = { - { MX28EVK_LCD_ENABLE, GPIOF_OUT_INIT_HIGH, "lcd-enable" }, - { MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" }, - { MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT, "flexcan-switch" }, - { MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc0-slot-power" }, - { MX28EVK_MMC1_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc1-slot-power" }, - { MX28EVK_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" }, - { MX28EVK_FEC_PHY_RESET, GPIOF_DIR_OUT, "fec-phy-reset" }, -}; - -static const struct mxs_saif_platform_data - mx28evk_mxs_saif_pdata[] __initconst = { - /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */ - { - .master_mode = 1, - .master_id = 0, - }, { - .master_mode = 0, - .master_id = 0, - }, -}; - -static void __init mx28evk_init(void) -{ - int ret; - - mx28_soc_init(); - - mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads)); - - mx28_add_duart(); - mx28_add_auart0(); - mx28_add_auart3(); - - if (mx28evk_fec_get_mac()) - pr_warn("%s: failed on fec mac setup\n", __func__); - - ret = gpio_request_array(mx28evk_gpios, ARRAY_SIZE(mx28evk_gpios)); - if (ret) - pr_err("One or more GPIOs failed to be requested: %d\n", ret); - - mx28evk_fec_reset(); - mx28_add_fec(0, &mx28_fec_pdata[0]); - mx28_add_fec(1, &mx28_fec_pdata[1]); - - mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]); - mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]); - - mx28_add_mxsfb(&mx28evk_mxsfb_pdata); - - mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); - mx28_add_saif(0, &mx28evk_mxs_saif_pdata[0]); - mx28_add_saif(1, &mx28evk_mxs_saif_pdata[1]); - - mx28_add_mxs_i2c(0); - i2c_register_board_info(0, mxs_i2c0_board_info, - ARRAY_SIZE(mxs_i2c0_board_info)); - - mx28evk_add_regulators(); - - mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0, - NULL, 0); - - mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]); - mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]); - - mx28_add_rtc_stmp3xxx(); - - gpio_led_register_device(0, &mx28evk_led_data); -} - -static void __init mx28evk_timer_init(void) -{ - mx28_clocks_init(); -} - -static struct sys_timer mx28evk_timer = { - .init = mx28evk_timer_init, -}; - -MACHINE_START(MX28EVK, "Freescale MX28 EVK") - /* Maintainer: Freescale Semiconductor, Inc. */ - .map_io = mx28_map_io, - .init_irq = mx28_init_irq, - .timer = &mx28evk_timer, - .init_machine = mx28evk_init, - .restart = mxs_restart, -MACHINE_END diff --git a/trunk/arch/arm/mach-mxs/mach-mxs.c b/trunk/arch/arm/mach-mxs/mach-mxs.c index 8dabfe81d07c..433af893ad8a 100644 --- a/trunk/arch/arm/mach-mxs/mach-mxs.c +++ b/trunk/arch/arm/mach-mxs/mach-mxs.c @@ -12,8 +12,10 @@ #include #include +#include +#include #include -#include +#include #include #include #include @@ -21,9 +23,12 @@ #include #include #include +#include #include #include #include +#include +#include static struct fb_videomode mx23evk_video_modes[] = { { @@ -99,9 +104,40 @@ static struct fb_videomode apx4devkit_video_modes[] = { static struct mxsfb_platform_data mxsfb_pdata __initdata; +/* + * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers + */ +#define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13) + +static int flexcan0_en, flexcan1_en; + +static void mx28evk_flexcan_switch(void) +{ + if (flexcan0_en || flexcan1_en) + gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1); + else + gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0); +} + +static void mx28evk_flexcan0_switch(int enable) +{ + flexcan0_en = enable; + mx28evk_flexcan_switch(); +} + +static void mx28evk_flexcan1_switch(int enable) +{ + flexcan1_en = enable; + mx28evk_flexcan_switch(); +} + +static struct flexcan_platform_data flexcan_pdata[2]; + static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata), OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata), + OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80032000, NULL, &flexcan_pdata[0]), + OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80034000, NULL, &flexcan_pdata[1]), { /* sentinel */ } }; @@ -237,13 +273,21 @@ static void __init imx28_evk_init(void) mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes); mxsfb_pdata.default_bpp = 32; mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; + + mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); } -static void __init m28evk_init(void) +static void __init imx28_evk_post_init(void) { - enable_clk_enet_out(); - update_fec_mac_prop(OUI_DENX); + if (!gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT, + "flexcan-switch")) { + flexcan_pdata[0].transceiver_switch = mx28evk_flexcan0_switch; + flexcan_pdata[1].transceiver_switch = mx28evk_flexcan1_switch; + } +} +static void __init m28evk_init(void) +{ mxsfb_pdata.mode_list = m28evk_video_modes; mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes); mxsfb_pdata.default_bpp = 16; @@ -270,6 +314,80 @@ static void __init apx4devkit_init(void) mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; } +#define ENET0_MDC__GPIO_4_0 MXS_GPIO_NR(4, 0) +#define ENET0_MDIO__GPIO_4_1 MXS_GPIO_NR(4, 1) +#define ENET0_RX_EN__GPIO_4_2 MXS_GPIO_NR(4, 2) +#define ENET0_RXD0__GPIO_4_3 MXS_GPIO_NR(4, 3) +#define ENET0_RXD1__GPIO_4_4 MXS_GPIO_NR(4, 4) +#define ENET0_TX_EN__GPIO_4_6 MXS_GPIO_NR(4, 6) +#define ENET0_TXD0__GPIO_4_7 MXS_GPIO_NR(4, 7) +#define ENET0_TXD1__GPIO_4_8 MXS_GPIO_NR(4, 8) +#define ENET_CLK__GPIO_4_16 MXS_GPIO_NR(4, 16) + +#define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29) +#define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13) +#define TX28_FEC_nINT MXS_GPIO_NR(4, 5) + +static const struct gpio tx28_gpios[] __initconst = { + { ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" }, + { ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" }, + { ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" }, + { ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" }, + { ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" }, + { ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" }, + { ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" }, + { ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" }, + { ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" }, + { TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" }, + { TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" }, + { TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" }, +}; + +static void __init tx28_post_init(void) +{ + struct device_node *np; + struct platform_device *pdev; + struct pinctrl *pctl; + int ret; + + enable_clk_enet_out(); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec"); + pdev = of_find_device_by_node(np); + if (!pdev) { + pr_err("%s: failed to find fec device\n", __func__); + return; + } + + pctl = pinctrl_get_select(&pdev->dev, "gpio_mode"); + if (IS_ERR(pctl)) { + pr_err("%s: failed to get pinctrl state\n", __func__); + return; + } + + ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios)); + if (ret) { + pr_err("%s: failed to request gpios: %d\n", __func__, ret); + return; + } + + /* Power up fec phy */ + gpio_set_value(TX28_FEC_PHY_POWER, 1); + msleep(26); /* 25ms according to data sheet */ + + /* Mode strap pins */ + gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1); + gpio_set_value(ENET0_RXD0__GPIO_4_3, 1); + gpio_set_value(ENET0_RXD1__GPIO_4_4, 1); + + udelay(100); /* minimum assertion time for nRST */ + + /* Deasserting FEC PHY RESET */ + gpio_set_value(TX28_FEC_PHY_RESET, 1); + + pinctrl_put(pctl); +} + static void __init mxs_machine_init(void) { if (of_machine_is_compatible("fsl,imx28-evk")) @@ -283,22 +401,20 @@ static void __init mxs_machine_init(void) of_platform_populate(NULL, of_default_bus_match_table, mxs_auxdata_lookup, NULL); + + if (of_machine_is_compatible("karo,tx28")) + tx28_post_init(); + + if (of_machine_is_compatible("fsl,imx28-evk")) + imx28_evk_post_init(); } static const char *imx23_dt_compat[] __initdata = { - "fsl,imx23-evk", - "fsl,stmp378x_devb" - "olimex,imx23-olinuxino", "fsl,imx23", NULL, }; static const char *imx28_dt_compat[] __initdata = { - "bluegiga,apx4devkit", - "crystalfontz,cfa10036", - "denx,m28evk", - "fsl,imx28-evk", - "karo,tx28", "fsl,imx28", NULL, }; diff --git a/trunk/arch/arm/mach-mxs/mach-stmp378x_devb.c b/trunk/arch/arm/mach-mxs/mach-stmp378x_devb.c deleted file mode 100644 index 6548965e4a76..000000000000 --- a/trunk/arch/arm/mach-mxs/mach-stmp378x_devb.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * board setup for STMP378x-Development-Board - * - * based on mx23evk board setup and information gained form the original - * plat-stmp based board setup, now converted to mach-mxs. - * - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include "devices-mx23.h" - -#define STMP378X_DEVB_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30) -#define STMP378X_DEVB_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29) - -#define STMP378X_DEVB_PAD_AUART (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL) - -static const iomux_cfg_t stmp378x_dvb_pads[] __initconst = { - /* duart (extended setup missing in old boardcode, too */ - MX23_PAD_PWM0__DUART_RX, - MX23_PAD_PWM1__DUART_TX, - - /* auart */ - MX23_PAD_AUART1_RX__AUART1_RX | STMP378X_DEVB_PAD_AUART, - MX23_PAD_AUART1_TX__AUART1_TX | STMP378X_DEVB_PAD_AUART, - MX23_PAD_AUART1_CTS__AUART1_CTS | STMP378X_DEVB_PAD_AUART, - MX23_PAD_AUART1_RTS__AUART1_RTS | STMP378X_DEVB_PAD_AUART, - - /* mmc */ - MX23_PAD_SSP1_DATA0__SSP1_DATA0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_DATA1__SSP1_DATA1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_DATA2__SSP1_DATA2 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_DATA3__SSP1_DATA3 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_CMD__SSP1_CMD | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_DETECT__SSP1_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX23_PAD_SSP1_SCK__SSP1_SCK | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX23_PAD_PWM4__GPIO_1_30 | MXS_PAD_CTRL, /* write protect */ - MX23_PAD_PWM3__GPIO_1_29 | MXS_PAD_CTRL, /* power enable */ -}; - -static struct mxs_mmc_platform_data stmp378x_dvb_mmc_pdata __initdata = { - .wp_gpio = STMP378X_DEVB_MMC0_WRITE_PROTECT, -}; - -static struct spi_board_info spi_board_info[] __initdata = { -#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) - { - .modalias = "enc28j60", - .max_speed_hz = 6 * 1000 * 1000, - .bus_num = 1, - .chip_select = 0, - .platform_data = NULL, - }, -#endif -}; - -static void __init stmp378x_dvb_init(void) -{ - int ret; - - mx23_soc_init(); - - mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads, - ARRAY_SIZE(stmp378x_dvb_pads)); - - mx23_add_duart(); - mx23_add_auart0(); - mx23_add_rtc_stmp3xxx(); - - /* power on mmc slot */ - ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER, - GPIOF_OUT_INIT_LOW, "mmc0-slot-power"); - if (ret) - pr_warn("could not power mmc (%d)\n", ret); - - mx23_add_mxs_mmc(0, &stmp378x_dvb_mmc_pdata); - - spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); -} - -static void __init stmp378x_dvb_timer_init(void) -{ - mx23_clocks_init(); -} - -static struct sys_timer stmp378x_dvb_timer = { - .init = stmp378x_dvb_timer_init, -}; - -MACHINE_START(STMP378X, "STMP378X") - .map_io = mx23_map_io, - .init_irq = mx23_init_irq, - .timer = &stmp378x_dvb_timer, - .init_machine = stmp378x_dvb_init, - .restart = mxs_restart, -MACHINE_END diff --git a/trunk/arch/arm/mach-mxs/mach-tx28.c b/trunk/arch/arm/mach-mxs/mach-tx28.c deleted file mode 100644 index 8837029de1a4..000000000000 --- a/trunk/arch/arm/mach-mxs/mach-tx28.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (C) 2010 - * - * based on: mach-mx28_evk.c - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include "devices-mx28.h" -#include "module-tx28.h" - -#define TX28_STK5_GPIO_LED MXS_GPIO_NR(4, 10) - -static const iomux_cfg_t tx28_stk5v3_pads[] __initconst = { - /* LED */ - MX28_PAD_ENET0_RXD3__GPIO_4_10 | - MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL, - - /* framebuffer */ -#define LCD_MODE (MXS_PAD_3V3 | MXS_PAD_4MA) - MX28_PAD_LCD_D00__LCD_D0 | LCD_MODE, - MX28_PAD_LCD_D01__LCD_D1 | LCD_MODE, - MX28_PAD_LCD_D02__LCD_D2 | LCD_MODE, - MX28_PAD_LCD_D03__LCD_D3 | LCD_MODE, - MX28_PAD_LCD_D04__LCD_D4 | LCD_MODE, - MX28_PAD_LCD_D05__LCD_D5 | LCD_MODE, - MX28_PAD_LCD_D06__LCD_D6 | LCD_MODE, - MX28_PAD_LCD_D07__LCD_D7 | LCD_MODE, - MX28_PAD_LCD_D08__LCD_D8 | LCD_MODE, - MX28_PAD_LCD_D09__LCD_D9 | LCD_MODE, - MX28_PAD_LCD_D10__LCD_D10 | LCD_MODE, - MX28_PAD_LCD_D11__LCD_D11 | LCD_MODE, - MX28_PAD_LCD_D12__LCD_D12 | LCD_MODE, - MX28_PAD_LCD_D13__LCD_D13 | LCD_MODE, - MX28_PAD_LCD_D14__LCD_D14 | LCD_MODE, - MX28_PAD_LCD_D15__LCD_D15 | LCD_MODE, - MX28_PAD_LCD_D16__LCD_D16 | LCD_MODE, - MX28_PAD_LCD_D17__LCD_D17 | LCD_MODE, - MX28_PAD_LCD_D18__LCD_D18 | LCD_MODE, - MX28_PAD_LCD_D19__LCD_D19 | LCD_MODE, - MX28_PAD_LCD_D20__LCD_D20 | LCD_MODE, - MX28_PAD_LCD_D21__LCD_D21 | LCD_MODE, - MX28_PAD_LCD_D22__LCD_D22 | LCD_MODE, - MX28_PAD_LCD_D23__LCD_D23 | LCD_MODE, - MX28_PAD_LCD_RD_E__LCD_VSYNC | LCD_MODE, - MX28_PAD_LCD_WR_RWN__LCD_HSYNC | LCD_MODE, - MX28_PAD_LCD_RS__LCD_DOTCLK | LCD_MODE, - MX28_PAD_LCD_CS__LCD_CS | LCD_MODE, - MX28_PAD_LCD_VSYNC__LCD_VSYNC | LCD_MODE, - MX28_PAD_LCD_HSYNC__LCD_HSYNC | LCD_MODE, - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | LCD_MODE, - MX28_PAD_LCD_ENABLE__GPIO_1_31 | LCD_MODE, - MX28_PAD_LCD_RESET__GPIO_3_30 | LCD_MODE, - MX28_PAD_PWM0__PWM_0 | LCD_MODE, - - /* UART1 */ - MX28_PAD_AUART0_CTS__DUART_RX, - MX28_PAD_AUART0_RTS__DUART_TX, - MX28_PAD_AUART0_TX__DUART_RTS, - MX28_PAD_AUART0_RX__DUART_CTS, - - /* UART2 */ - MX28_PAD_AUART1_RX__AUART1_RX, - MX28_PAD_AUART1_TX__AUART1_TX, - MX28_PAD_AUART1_RTS__AUART1_RTS, - MX28_PAD_AUART1_CTS__AUART1_CTS, - - /* CAN */ - MX28_PAD_GPMI_RDY2__CAN0_TX, - MX28_PAD_GPMI_RDY3__CAN0_RX, - - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - - /* TSC2007 */ - MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP, - - /* MMC0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA1__SSP0_D1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA2__SSP0_D2 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA3__SSP0_D3 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_CMD__SSP0_CMD | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), -}; - -static const struct gpio_led tx28_stk5v3_leds[] __initconst = { - { - .name = "GPIO-LED", - .default_trigger = "heartbeat", - .gpio = TX28_STK5_GPIO_LED, - }, -}; - -static const struct gpio_led_platform_data tx28_stk5v3_led_data __initconst = { - .leds = tx28_stk5v3_leds, - .num_leds = ARRAY_SIZE(tx28_stk5v3_leds), -}; - -static struct spi_board_info tx28_spi_board_info[] = { - { - .modalias = "spidev", - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 1, - .controller_data = (void *)SPI_GPIO_NO_CHIPSELECT, - .mode = SPI_MODE_0, - }, -}; - -static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = { - { - I2C_BOARD_INFO("ds1339", 0x68), - }, -}; - -static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = { - .wp_gpio = -EINVAL, - .flags = SLOTF_4_BIT_CAPABLE, -}; - -static void __init tx28_stk5v3_init(void) -{ - mx28_soc_init(); - - mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads, - ARRAY_SIZE(tx28_stk5v3_pads)); - - mx28_add_duart(); /* UART1 */ - mx28_add_auart(1); /* UART2 */ - - tx28_add_fec0(); - /* spi via ssp will be added when available */ - spi_register_board_info(tx28_spi_board_info, - ARRAY_SIZE(tx28_spi_board_info)); - gpio_led_register_device(0, &tx28_stk5v3_led_data); - mx28_add_mxs_i2c(0); - i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo, - ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo)); - mx28_add_mxs_mmc(0, &tx28_mmc0_pdata); - mx28_add_rtc_stmp3xxx(); -} - -static void __init tx28_timer_init(void) -{ - mx28_clocks_init(); -} - -static struct sys_timer tx28_timer = { - .init = tx28_timer_init, -}; - -MACHINE_START(TX28, "Ka-Ro electronics TX28 module") - .map_io = mx28_map_io, - .init_irq = mx28_init_irq, - .timer = &tx28_timer, - .init_machine = tx28_stk5v3_init, - .restart = mxs_restart, -MACHINE_END diff --git a/trunk/arch/arm/mach-mxs/mm.c b/trunk/arch/arm/mach-mxs/mm.c index dccb67a9e7c4..a4294aa9f301 100644 --- a/trunk/arch/arm/mach-mxs/mm.c +++ b/trunk/arch/arm/mach-mxs/mm.c @@ -13,14 +13,11 @@ #include #include -#include #include #include #include -#include -#include /* * Define the MX23 memory map. @@ -48,43 +45,7 @@ void __init mx23_map_io(void) iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc)); } -void __init mx23_init_irq(void) -{ - icoll_init_irq(); -} - void __init mx28_map_io(void) { iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); } - -void __init mx28_init_irq(void) -{ - icoll_init_irq(); -} - -void __init mx23_soc_init(void) -{ - pinctrl_provide_dummies(); - - mxs_add_dma("imx23-dma-apbh", MX23_APBH_DMA_BASE_ADDR); - mxs_add_dma("imx23-dma-apbx", MX23_APBX_DMA_BASE_ADDR); - - mxs_add_gpio("imx23-gpio", 0, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO0); - mxs_add_gpio("imx23-gpio", 1, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO1); - mxs_add_gpio("imx23-gpio", 2, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO2); -} - -void __init mx28_soc_init(void) -{ - pinctrl_provide_dummies(); - - mxs_add_dma("imx28-dma-apbh", MX23_APBH_DMA_BASE_ADDR); - mxs_add_dma("imx28-dma-apbx", MX23_APBX_DMA_BASE_ADDR); - - mxs_add_gpio("imx28-gpio", 0, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO0); - mxs_add_gpio("imx28-gpio", 1, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO1); - mxs_add_gpio("imx28-gpio", 2, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO2); - mxs_add_gpio("imx28-gpio", 3, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO3); - mxs_add_gpio("imx28-gpio", 4, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO4); -} diff --git a/trunk/arch/arm/mach-mxs/module-tx28.c b/trunk/arch/arm/mach-mxs/module-tx28.c deleted file mode 100644 index 0f71f82101cc..000000000000 --- a/trunk/arch/arm/mach-mxs/module-tx28.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (C) 2010 - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ - -#include -#include -#include - -#include -#include "devices-mx28.h" - -#include "module-tx28.h" - -#define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29) -#define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13) - -static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = { - /* PHY POWER */ - MX28_PAD_PWM4__GPIO_3_29 | - MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3, - /* PHY RESET */ - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | - MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3, - /* Mode strap pins 0-2 */ - MX28_PAD_ENET0_RXD0__GPIO_4_3 | - MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3, - MX28_PAD_ENET0_RXD1__GPIO_4_4 | - MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3, - MX28_PAD_ENET0_RX_EN__GPIO_4_2 | - MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3, - /* nINT */ - MX28_PAD_ENET0_TX_CLK__GPIO_4_5 | - MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3, - - MX28_PAD_ENET0_MDC__GPIO_4_0, - MX28_PAD_ENET0_MDIO__GPIO_4_1, - MX28_PAD_ENET0_TX_EN__GPIO_4_6, - MX28_PAD_ENET0_TXD0__GPIO_4_7, - MX28_PAD_ENET0_TXD1__GPIO_4_8, - MX28_PAD_ENET_CLK__GPIO_4_16, -}; - -#define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3) -static const iomux_cfg_t tx28_fec0_pads[] __initconst = { - MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | FEC_MODE, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | FEC_MODE, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | FEC_MODE, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | FEC_MODE, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | FEC_MODE, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE, -}; - -static const iomux_cfg_t tx28_fec1_pads[] __initconst = { - MX28_PAD_ENET0_RXD2__ENET1_RXD0, - MX28_PAD_ENET0_RXD3__ENET1_RXD1, - MX28_PAD_ENET0_TXD2__ENET1_TXD0, - MX28_PAD_ENET0_TXD3__ENET1_TXD1, - MX28_PAD_ENET0_COL__ENET1_TX_EN, - MX28_PAD_ENET0_CRS__ENET1_RX_EN, -}; - -static const struct fec_platform_data tx28_fec0_data __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static const struct fec_platform_data tx28_fec1_data __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -int __init tx28_add_fec0(void) -{ - int i, ret; - - pr_debug("%s: Switching FEC PHY power off\n", __func__); - ret = mxs_iomux_setup_multiple_pads(tx28_fec_gpio_pads, - ARRAY_SIZE(tx28_fec_gpio_pads)); - for (i = 0; i < ARRAY_SIZE(tx28_fec_gpio_pads); i++) { - unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]), - PAD_PIN(tx28_fec_gpio_pads[i])); - - ret = gpio_request(gpio, "FEC"); - if (ret) { - pr_err("Failed to request GPIO_%d_%d: %d\n", - PAD_BANK(tx28_fec_gpio_pads[i]), - PAD_PIN(tx28_fec_gpio_pads[i]), ret); - goto free_gpios; - } - ret = gpio_direction_output(gpio, 0); - if (ret) { - pr_err("Failed to set direction of GPIO_%d_%d to output: %d\n", - gpio / 32 + 1, gpio % 32, ret); - goto free_gpios; - } - } - - /* Power up fec phy */ - pr_debug("%s: Switching FEC PHY power on\n", __func__); - ret = gpio_direction_output(TX28_FEC_PHY_POWER, 1); - if (ret) { - pr_err("Failed to power on PHY: %d\n", ret); - goto free_gpios; - } - mdelay(26); /* 25ms according to data sheet */ - - /* nINT */ - gpio_direction_input(MXS_GPIO_NR(4, 5)); - /* Mode strap pins */ - gpio_direction_output(MXS_GPIO_NR(4, 2), 1); - gpio_direction_output(MXS_GPIO_NR(4, 3), 1); - gpio_direction_output(MXS_GPIO_NR(4, 4), 1); - - udelay(100); /* minimum assertion time for nRST */ - - pr_debug("%s: Deasserting FEC PHY RESET\n", __func__); - gpio_set_value(TX28_FEC_PHY_RESET, 1); - - ret = mxs_iomux_setup_multiple_pads(tx28_fec0_pads, - ARRAY_SIZE(tx28_fec0_pads)); - if (ret) { - pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n", - __func__, ret); - goto free_gpios; - } - pr_debug("%s: Registering FEC0 device\n", __func__); - mx28_add_fec(0, &tx28_fec0_data); - return 0; - -free_gpios: - while (--i >= 0) { - unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]), - PAD_PIN(tx28_fec_gpio_pads[i])); - - gpio_free(gpio); - } - - return ret; -} - -int __init tx28_add_fec1(void) -{ - int ret; - - ret = mxs_iomux_setup_multiple_pads(tx28_fec1_pads, - ARRAY_SIZE(tx28_fec1_pads)); - if (ret) { - pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n", - __func__, ret); - return ret; - } - pr_debug("%s: Registering FEC1 device\n", __func__); - mx28_add_fec(1, &tx28_fec1_data); - return 0; -} diff --git a/trunk/arch/arm/mach-mxs/module-tx28.h b/trunk/arch/arm/mach-mxs/module-tx28.h deleted file mode 100644 index 8ed425457d30..000000000000 --- a/trunk/arch/arm/mach-mxs/module-tx28.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -int __init tx28_add_fec0(void); -int __init tx28_add_fec1(void); diff --git a/trunk/arch/arm/mach-nomadik/include/mach/gpio.h b/trunk/arch/arm/mach-nomadik/include/mach/gpio.h deleted file mode 100644 index efdde0ae0a4f..000000000000 --- a/trunk/arch/arm/mach-nomadik/include/mach/gpio.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H - -#endif /* __ASM_ARCH_GPIO_H */ diff --git a/trunk/arch/arm/mach-nomadik/include/mach/hardware.h b/trunk/arch/arm/mach-nomadik/include/mach/hardware.h index 6316dba3bfc8..02035e459f50 100644 --- a/trunk/arch/arm/mach-nomadik/include/mach/hardware.h +++ b/trunk/arch/arm/mach-nomadik/include/mach/hardware.h @@ -30,7 +30,7 @@ - NOMADIK_IO_VIRTUAL + NOMADIK_IO_PHYSICAL) /* used in asm code, so no casts */ -#define IO_ADDRESS(x) ((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL) +#define IO_ADDRESS(x) IOMEM((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL) /* * Base address defination for Nomadik Onchip Logic Block diff --git a/trunk/arch/arm/mach-nomadik/include/mach/uncompress.h b/trunk/arch/arm/mach-nomadik/include/mach/uncompress.h index 071003bc8456..7d4687e9cbdf 100644 --- a/trunk/arch/arm/mach-nomadik/include/mach/uncompress.h +++ b/trunk/arch/arm/mach-nomadik/include/mach/uncompress.h @@ -27,10 +27,10 @@ struct amba_device; #include -#define NOMADIK_UART_DR 0x101FB000 -#define NOMADIK_UART_LCRH 0x101FB02c -#define NOMADIK_UART_CR 0x101FB030 -#define NOMADIK_UART_FR 0x101FB018 +#define NOMADIK_UART_DR (void __iomem *)0x101FB000 +#define NOMADIK_UART_LCRH (void __iomem *)0x101FB02c +#define NOMADIK_UART_CR (void __iomem *)0x101FB030 +#define NOMADIK_UART_FR (void __iomem *)0x101FB018 static void putc(const char c) { diff --git a/trunk/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/trunk/arch/arm/mach-omap1/ams-delta-fiq-handler.S index d2b6acce8fc1..3d1e1c250a1a 100644 --- a/trunk/arch/arm/mach-omap1/ams-delta-fiq-handler.S +++ b/trunk/arch/arm/mach-omap1/ams-delta-fiq-handler.S @@ -16,7 +16,7 @@ #include #include -#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/ams-delta-fiq.c b/trunk/arch/arm/mach-omap1/ams-delta-fiq.c index 68e8e5654c0a..f12a12af3523 100644 --- a/trunk/arch/arm/mach-omap1/ams-delta-fiq.c +++ b/trunk/arch/arm/mach-omap1/ams-delta-fiq.c @@ -19,7 +19,7 @@ #include #include -#include +#include #include diff --git a/trunk/arch/arm/mach-omap1/board-ams-delta.c b/trunk/arch/arm/mach-omap1/board-ams-delta.c index 6f192c4900b1..9518bf5996dc 100644 --- a/trunk/arch/arm/mach-omap1/board-ams-delta.c +++ b/trunk/arch/arm/mach-omap1/board-ams-delta.c @@ -35,9 +35,9 @@ #include #include -#include -#include -#include +#include +#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-fsample.c b/trunk/arch/arm/mach-omap1/board-fsample.c index 6d985521a39e..4b6de70c47a6 100644 --- a/trunk/arch/arm/mach-omap1/board-fsample.c +++ b/trunk/arch/arm/mach-omap1/board-fsample.c @@ -28,10 +28,10 @@ #include #include -#include -#include +#include +#include #include -#include +#include #include diff --git a/trunk/arch/arm/mach-omap1/board-generic.c b/trunk/arch/arm/mach-omap1/board-generic.c index 04b5fdaff831..4ec579fdd366 100644 --- a/trunk/arch/arm/mach-omap1/board-generic.c +++ b/trunk/arch/arm/mach-omap1/board-generic.c @@ -22,7 +22,7 @@ #include #include -#include +#include #include diff --git a/trunk/arch/arm/mach-omap1/board-h2.c b/trunk/arch/arm/mach-omap1/board-h2.c index fe79c56b2dc0..af283a2bc7c7 100644 --- a/trunk/arch/arm/mach-omap1/board-h2.c +++ b/trunk/arch/arm/mach-omap1/board-h2.c @@ -37,12 +37,12 @@ #include #include -#include +#include #include #include -#include -#include -#include +#include +#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-h3.c b/trunk/arch/arm/mach-omap1/board-h3.c index 6c46f33894fb..06d11b1ee9c6 100644 --- a/trunk/arch/arm/mach-omap1/board-h3.c +++ b/trunk/arch/arm/mach-omap1/board-h3.c @@ -39,11 +39,11 @@ #include #include -#include +#include #include -#include +#include #include -#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-htcherald.c b/trunk/arch/arm/mach-omap1/board-htcherald.c index 1dcb751b8fe5..87ab2086ef96 100644 --- a/trunk/arch/arm/mach-omap1/board-htcherald.c +++ b/trunk/arch/arm/mach-omap1/board-htcherald.c @@ -37,12 +37,12 @@ #include #include #include +#include #include #include #include -#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-innovator.c b/trunk/arch/arm/mach-omap1/board-innovator.c index f21c2966daad..db5f7d2976e7 100644 --- a/trunk/arch/arm/mach-omap1/board-innovator.c +++ b/trunk/arch/arm/mach-omap1/board-innovator.c @@ -31,11 +31,11 @@ #include #include -#include -#include +#include +#include #include #include -#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-nokia770.c b/trunk/arch/arm/mach-omap1/board-nokia770.c index ec01f03d0446..7d5c06d6a52a 100644 --- a/trunk/arch/arm/mach-omap1/board-nokia770.c +++ b/trunk/arch/arm/mach-omap1/board-nokia770.c @@ -21,13 +21,14 @@ #include #include +#include +#include + #include #include #include -#include -#include -#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-osk.c b/trunk/arch/arm/mach-omap1/board-osk.c index 3b2d9071022a..2f1f9b967576 100644 --- a/trunk/arch/arm/mach-omap1/board-osk.c +++ b/trunk/arch/arm/mach-omap1/board-osk.c @@ -46,8 +46,8 @@ #include #include -#include -#include +#include +#include #include #include @@ -304,7 +304,7 @@ static struct omap_lcd_config osk_lcd_config __initdata = { #include #include -#include +#include static struct at24_platform_data at24c04 = { .byte_len = SZ_4K / 8, diff --git a/trunk/arch/arm/mach-omap1/board-palmte.c b/trunk/arch/arm/mach-omap1/board-palmte.c index 49f8d745ea1f..1c578d58923a 100644 --- a/trunk/arch/arm/mach-omap1/board-palmte.c +++ b/trunk/arch/arm/mach-omap1/board-palmte.c @@ -34,12 +34,12 @@ #include #include -#include -#include +#include +#include #include #include -#include -#include +#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-palmtt.c b/trunk/arch/arm/mach-omap1/board-palmtt.c index 01523cd78e58..97158095083c 100644 --- a/trunk/arch/arm/mach-omap1/board-palmtt.c +++ b/trunk/arch/arm/mach-omap1/board-palmtt.c @@ -34,12 +34,12 @@ #include #include -#include -#include +#include +#include #include #include -#include -#include +#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-palmz71.c b/trunk/arch/arm/mach-omap1/board-palmz71.c index a7abce69043a..e311032e7eeb 100644 --- a/trunk/arch/arm/mach-omap1/board-palmz71.c +++ b/trunk/arch/arm/mach-omap1/board-palmz71.c @@ -36,12 +36,12 @@ #include #include -#include -#include +#include +#include #include #include -#include -#include +#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-perseus2.c b/trunk/arch/arm/mach-omap1/board-perseus2.c index 277e0bc60a43..198b05417bfc 100644 --- a/trunk/arch/arm/mach-omap1/board-perseus2.c +++ b/trunk/arch/arm/mach-omap1/board-perseus2.c @@ -22,16 +22,16 @@ #include #include #include +#include #include #include #include #include -#include +#include #include -#include -#include +#include #include diff --git a/trunk/arch/arm/mach-omap1/board-sx1-mmc.c b/trunk/arch/arm/mach-omap1/board-sx1-mmc.c index b59f78850e69..5932d56e17bf 100644 --- a/trunk/arch/arm/mach-omap1/board-sx1-mmc.c +++ b/trunk/arch/arm/mach-omap1/board-sx1-mmc.c @@ -17,7 +17,7 @@ #include #include -#include +#include #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) diff --git a/trunk/arch/arm/mach-omap1/board-sx1.c b/trunk/arch/arm/mach-omap1/board-sx1.c index 2e1fff26a2f3..13bf2cc56814 100644 --- a/trunk/arch/arm/mach-omap1/board-sx1.c +++ b/trunk/arch/arm/mach-omap1/board-sx1.c @@ -28,18 +28,18 @@ #include #include #include +#include #include #include #include -#include -#include +#include +#include #include -#include +#include #include -#include -#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-voiceblue.c b/trunk/arch/arm/mach-omap1/board-voiceblue.c index 1668af3017de..ad75e3411d46 100644 --- a/trunk/arch/arm/mach-omap1/board-voiceblue.c +++ b/trunk/arch/arm/mach-omap1/board-voiceblue.c @@ -31,9 +31,9 @@ #include #include -#include -#include -#include +#include +#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/devices.c b/trunk/arch/arm/mach-omap1/devices.c index 7a5a3285e965..0cc54dd553e3 100644 --- a/trunk/arch/arm/mach-omap1/devices.c +++ b/trunk/arch/arm/mach-omap1/devices.c @@ -20,7 +20,7 @@ #include #include -#include +#include #include #include @@ -357,33 +357,6 @@ static inline void omap_init_uwire(void) {} #endif -#define OMAP1_RNG_BASE 0xfffe5000 - -static struct resource omap1_rng_resources[] = { - { - .start = OMAP1_RNG_BASE, - .end = OMAP1_RNG_BASE + 0x4f, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device omap1_rng_device = { - .name = "omap_rng", - .id = -1, - .num_resources = ARRAY_SIZE(omap1_rng_resources), - .resource = omap1_rng_resources, -}; - -static void omap1_init_rng(void) -{ - if (!cpu_is_omap16xx()) - return; - - (void) platform_device_register(&omap1_rng_device); -} - -/*-------------------------------------------------------------------------*/ - /* * This gets called after board-specific INIT_MACHINE, and initializes most * on-chip peripherals accessible on this board (except for few like USB): @@ -422,7 +395,6 @@ static int __init omap1_init_devices(void) omap_init_spi100k(); omap_init_sti(); omap_init_uwire(); - omap1_init_rng(); return 0; } diff --git a/trunk/arch/arm/mach-omap1/flash.c b/trunk/arch/arm/mach-omap1/flash.c index 401eb3c080c2..73ae6169aa4a 100644 --- a/trunk/arch/arm/mach-omap1/flash.c +++ b/trunk/arch/arm/mach-omap1/flash.c @@ -11,7 +11,7 @@ #include #include -#include +#include #include diff --git a/trunk/arch/arm/mach-omap1/i2c.c b/trunk/arch/arm/mach-omap1/i2c.c index 5446c9912641..a0551a6d7451 100644 --- a/trunk/arch/arm/mach-omap1/i2c.c +++ b/trunk/arch/arm/mach-omap1/i2c.c @@ -20,7 +20,7 @@ */ #include -#include +#include #include void __init omap1_i2c_mux_pins(int bus_id) diff --git a/trunk/arch/arm/plat-omap/include/plat/board-ams-delta.h b/trunk/arch/arm/mach-omap1/include/mach/board-ams-delta.h similarity index 100% rename from trunk/arch/arm/plat-omap/include/plat/board-ams-delta.h rename to trunk/arch/arm/mach-omap1/include/mach/board-ams-delta.h diff --git a/trunk/arch/arm/plat-omap/include/plat/board-sx1.h b/trunk/arch/arm/mach-omap1/include/mach/board-sx1.h similarity index 100% rename from trunk/arch/arm/plat-omap/include/plat/board-sx1.h rename to trunk/arch/arm/mach-omap1/include/mach/board-sx1.h diff --git a/trunk/arch/arm/plat-omap/include/plat/board-voiceblue.h b/trunk/arch/arm/mach-omap1/include/mach/board-voiceblue.h similarity index 100% rename from trunk/arch/arm/plat-omap/include/plat/board-voiceblue.h rename to trunk/arch/arm/mach-omap1/include/mach/board-voiceblue.h diff --git a/trunk/arch/arm/plat-omap/include/plat/flash.h b/trunk/arch/arm/mach-omap1/include/mach/flash.h similarity index 100% rename from trunk/arch/arm/plat-omap/include/plat/flash.h rename to trunk/arch/arm/mach-omap1/include/mach/flash.h diff --git a/trunk/arch/arm/plat-omap/include/plat/irda.h b/trunk/arch/arm/mach-omap1/include/mach/irda.h similarity index 100% rename from trunk/arch/arm/plat-omap/include/plat/irda.h rename to trunk/arch/arm/mach-omap1/include/mach/irda.h diff --git a/trunk/arch/arm/plat-omap/include/plat/mux.h b/trunk/arch/arm/mach-omap1/include/mach/mux.h similarity index 100% rename from trunk/arch/arm/plat-omap/include/plat/mux.h rename to trunk/arch/arm/mach-omap1/include/mach/mux.h diff --git a/trunk/arch/arm/mach-omap1/include/mach/smp.h b/trunk/arch/arm/mach-omap1/include/mach/smp.h deleted file mode 100644 index 80a371c06e59..000000000000 --- a/trunk/arch/arm/mach-omap1/include/mach/smp.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * arch/arm/mach-omap1/include/mach/smp.h - */ - -#include diff --git a/trunk/arch/arm/mach-omap1/io.c b/trunk/arch/arm/mach-omap1/io.c index 6c95a59f0f16..6a5baab1f4cb 100644 --- a/trunk/arch/arm/mach-omap1/io.c +++ b/trunk/arch/arm/mach-omap1/io.c @@ -16,7 +16,7 @@ #include #include -#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/leds.c b/trunk/arch/arm/mach-omap1/leds.c index 7b1a3833165d..4071479f7106 100644 --- a/trunk/arch/arm/mach-omap1/leds.c +++ b/trunk/arch/arm/mach-omap1/leds.c @@ -11,7 +11,7 @@ #include #include -#include +#include #include "leds.h" diff --git a/trunk/arch/arm/mach-omap1/mcbsp.c b/trunk/arch/arm/mach-omap1/mcbsp.c index adf00975b9bb..bdc2e7541adb 100644 --- a/trunk/arch/arm/mach-omap1/mcbsp.c +++ b/trunk/arch/arm/mach-omap1/mcbsp.c @@ -20,9 +20,9 @@ #include #include -#include +#include #include -#include +#include #include diff --git a/trunk/arch/arm/mach-omap1/mux.c b/trunk/arch/arm/mach-omap1/mux.c index e9cc52d4cb28..667ce5027f63 100644 --- a/trunk/arch/arm/mach-omap1/mux.c +++ b/trunk/arch/arm/mach-omap1/mux.c @@ -29,7 +29,7 @@ #include -#include +#include #ifdef CONFIG_OMAP_MUX @@ -451,6 +451,56 @@ static int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) #endif } +static struct omap_mux_cfg *mux_cfg; + +int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg) +{ + if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0 + || !arch_mux_cfg->cfg_reg) { + printk(KERN_ERR "Invalid pin table\n"); + return -EINVAL; + } + + mux_cfg = arch_mux_cfg; + + return 0; +} + +/* + * Sets the Omap MUX and PULL_DWN registers based on the table + */ +int __init_or_module omap_cfg_reg(const unsigned long index) +{ + struct pin_config *reg; + + if (!cpu_class_is_omap1()) { + printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n", + index); + WARN_ON(1); + return -EINVAL; + } + + if (mux_cfg == NULL) { + printk(KERN_ERR "Pin mux table not initialized\n"); + return -ENODEV; + } + + if (index >= mux_cfg->size) { + printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", + index, mux_cfg->size); + dump_stack(); + return -ENODEV; + } + + reg = &mux_cfg->pins[index]; + + if (!mux_cfg->cfg_reg) + return -ENODEV; + + return mux_cfg->cfg_reg(reg); +} +EXPORT_SYMBOL(omap_cfg_reg); + int __init omap1_mux_init(void) { if (cpu_is_omap7xx()) { @@ -468,4 +518,8 @@ int __init omap1_mux_init(void) return omap_mux_register(&arch_mux_cfg); } -#endif +#else +#define omap_mux_init() do {} while(0) +#define omap_cfg_reg(x) do {} while(0) +#endif /* CONFIG_OMAP_MUX */ + diff --git a/trunk/arch/arm/mach-omap1/pm.c b/trunk/arch/arm/mach-omap1/pm.c index b2560d32b3a0..47ec16155483 100644 --- a/trunk/arch/arm/mach-omap1/pm.c +++ b/trunk/arch/arm/mach-omap1/pm.c @@ -53,7 +53,7 @@ #include #include #include -#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/serial.c b/trunk/arch/arm/mach-omap1/serial.c index 0d1709b1a6fe..b9d6834af835 100644 --- a/trunk/arch/arm/mach-omap1/serial.c +++ b/trunk/arch/arm/mach-omap1/serial.c @@ -22,7 +22,7 @@ #include -#include +#include #include #include "pm.h" diff --git a/trunk/arch/arm/mach-omap1/timer.c b/trunk/arch/arm/mach-omap1/timer.c index cdeb9d3ef640..aa81593db1af 100644 --- a/trunk/arch/arm/mach-omap1/timer.c +++ b/trunk/arch/arm/mach-omap1/timer.c @@ -141,7 +141,7 @@ static int __init omap1_dm_timer_init(void) pdata->set_timer_src = omap1_dm_timer_set_src; pdata->timer_capability = OMAP_TIMER_ALWON | - OMAP_TIMER_NEEDS_RESET | OMAP_TIMER_HAS_DSP_IRQ; + OMAP_TIMER_NEEDS_RESET; ret = platform_device_add_data(pdev, pdata, sizeof(*pdata)); if (ret) { diff --git a/trunk/arch/arm/mach-omap1/usb.c b/trunk/arch/arm/mach-omap1/usb.c index 65f88176fba8..84267edd9421 100644 --- a/trunk/arch/arm/mach-omap1/usb.c +++ b/trunk/arch/arm/mach-omap1/usb.c @@ -26,7 +26,7 @@ #include -#include +#include #include diff --git a/trunk/arch/arm/mach-omap2/Kconfig b/trunk/arch/arm/mach-omap2/Kconfig index 346fd26f3aa6..eef99b77c40b 100644 --- a/trunk/arch/arm/mach-omap2/Kconfig +++ b/trunk/arch/arm/mach-omap2/Kconfig @@ -18,6 +18,7 @@ config ARCH_OMAP2PLUS_TYPICAL select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 select HIGHMEM + select PINCTRL help Compile a kernel suitable for booting most boards diff --git a/trunk/arch/arm/mach-omap2/Makefile b/trunk/arch/arm/mach-omap2/Makefile index 0deb30072977..845202358ddc 100644 --- a/trunk/arch/arm/mach-omap2/Makefile +++ b/trunk/arch/arm/mach-omap2/Makefile @@ -4,36 +4,30 @@ # Common support obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \ - common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o + common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o -omap-2-3-common = irq.o -hwmod-common = omap_hwmod.o \ - omap_hwmod_common_data.o -clock-common = clock.o clock_common_data.o \ - clkt_dpll.o clkt_clksel.o -secure-common = omap-smc.o omap-secure.o +# INTCPS IP block support - XXX should be moved to drivers/ +obj-$(CONFIG_ARCH_OMAP2) += irq.o +obj-$(CONFIG_ARCH_OMAP3) += irq.o +obj-$(CONFIG_SOC_AM33XX) += irq.o -obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) -obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) -obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) -obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) -obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) +# Secure monitor API support +obj-$(CONFIG_ARCH_OMAP3) += omap-smc.o omap-secure.o +obj-$(CONFIG_ARCH_OMAP4) += omap-smc.o omap-secure.o +obj-$(CONFIG_SOC_OMAP5) += omap-smc.o omap-secure.o ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) obj-y += mcbsp.o endif -obj-$(CONFIG_TWL4030_CORE) += omap_twl.o -obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o +obj-$(CONFIG_TWL4030_CORE) += omap_twl.o # SMP support ONLY available for OMAP4 obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o -omap-4-5-common = omap4-common.o omap-wakeupgen.o \ - sleep44xx.o -obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) -obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) +obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o +obj-$(CONFIG_SOC_OMAP5) += omap4-common.o omap-wakeupgen.o plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) @@ -58,6 +52,7 @@ obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o # SMS/SDRC obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o +obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o # OPP table initialization ifeq ($(CONFIG_PM_OPP),y) @@ -68,15 +63,15 @@ endif # Power Management ifeq ($(CONFIG_PM),y) -obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o -obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o +obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o -obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o +obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o +obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o sleep44xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o -obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o +obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec) @@ -88,92 +83,76 @@ endif endif ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o -obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o +obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o +obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o endif # PRCM -omap-prcm-4-5-common = prcm.o cminst44xx.o cm44xx.o \ - prcm_mpu44xx.o prminst44xx.o \ - vc44xx_data.o vp44xx_data.o -obj-y += prm_common.o -obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o -obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o +obj-y += prcm.o prm_common.o +obj-$(CONFIG_ARCH_OMAP2) += cm2xxx_3xxx.o prm2xxx_3xxx.o +obj-$(CONFIG_ARCH_OMAP3) += cm2xxx_3xxx.o prm2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o -obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o -obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) prm44xx.o +obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o +omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ + prcm_mpu44xx.o prminst44xx.o \ + vc44xx_data.o vp44xx_data.o \ + prm44xx.o +obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) # OMAP voltage domains -voltagedomain-common := voltage.o vc.o vp.o -obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common) +obj-y += voltage.o vc.o vp.o obj-$(CONFIG_ARCH_OMAP2) += voltagedomains2xxx_data.o -obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o -obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) -obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o -obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common) +obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o # OMAP powerdomain framework -powerdomain-common += powerdomain.o powerdomain-common.o -obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common) +obj-y += powerdomain.o powerdomain-common.o obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_data.o obj-$(CONFIG_ARCH_OMAP2) += powerdomain2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_3xxx_data.o -obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP3) += powerdomain2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP3) += powerdomains3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o -obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o -obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) obj-$(CONFIG_SOC_OMAP5) += powerdomain44xx.o # PRCM clockdomain control -clockdomain-common += clockdomain.o -obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common) +obj-y += clockdomain.o obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o -obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o -obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o -obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) obj-$(CONFIG_SOC_OMAP5) += clockdomain44xx.o # Clock framework -obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o +obj-y += clock.o clock_common_data.o \ + clkt_dpll.o clkt_clksel.o +obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o +obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o clkt2xxx_sys.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o -obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o +obj-$(CONFIG_ARCH_OMAP3) += clock3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o -obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o +obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o clkt_iclk.o obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o -obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o -obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o +obj-$(CONFIG_ARCH_OMAP4) += clock44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o -obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o -obj-$(CONFIG_SOC_AM33XX) += clock33xx_data.o -obj-$(CONFIG_SOC_OMAP5) += $(clock-common) +obj-$(CONFIG_SOC_AM33XX) += dpll3xxx.o clock33xx_data.o obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o # OMAP2 clock rate set data (old "OPP" data) @@ -181,6 +160,7 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o # hwmod data +obj-y += omap_hwmod_common_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o @@ -199,7 +179,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o # EMU peripherals obj-$(CONFIG_OMAP3_EMU) += emu.o -obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o # L3 interconnect obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o @@ -231,10 +210,10 @@ obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o -obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o +obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o -obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o -obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o +obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o +obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o obj-$(CONFIG_MACH_ENCORE) += board-omap3encore.o obj-$(CONFIG_MACH_OVERO) += board-overo.o obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o diff --git a/trunk/arch/arm/mach-omap2/am35xx-emac.c b/trunk/arch/arm/mach-omap2/am35xx-emac.c index 2c90ac686686..d0c54c573d34 100644 --- a/trunk/arch/arm/mach-omap2/am35xx-emac.c +++ b/trunk/arch/arm/mach-omap2/am35xx-emac.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include "am35xx.h" #include "control.h" #include "am35xx-emac.h" diff --git a/trunk/arch/arm/mach-omap2/include/mach/am35xx.h b/trunk/arch/arm/mach-omap2/am35xx.h similarity index 100% rename from trunk/arch/arm/mach-omap2/include/mach/am35xx.h rename to trunk/arch/arm/mach-omap2/am35xx.h diff --git a/trunk/arch/arm/mach-omap2/board-2430sdp.c b/trunk/arch/arm/mach-omap2/board-2430sdp.c index 0900eac57d56..95b384d54f8a 100644 --- a/trunk/arch/arm/mach-omap2/board-2430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-2430sdp.c @@ -36,7 +36,7 @@ #include "common.h" #include #include -#include +#include "gpmc-smc91x.h" #include