From 029b5d9b9a30235387053a9b27567684b79f48c0 Mon Sep 17 00:00:00 2001
From: Hiroshi Doyu <hdoyu@nvidia.com>
Date: Thu, 14 Mar 2013 11:12:10 +0200
Subject: [PATCH] --- yaml --- r: 363084 b: refs/heads/master c:
 9f7345b7a7cbf4c78a8161cba21de1772d5ad56e h: refs/heads/master v: v3

---
 [refs]                            | 2 +-
 trunk/drivers/memory/tegra30-mc.c | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 2d487a4409d6..1167b3ecf0ec 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: aafae7ecd80181983403de13db0b4895acdc233d
+refs/heads/master: 9f7345b7a7cbf4c78a8161cba21de1772d5ad56e
diff --git a/trunk/drivers/memory/tegra30-mc.c b/trunk/drivers/memory/tegra30-mc.c
index 0b975986777d..f4ae074badc3 100644
--- a/trunk/drivers/memory/tegra30-mc.c
+++ b/trunk/drivers/memory/tegra30-mc.c
@@ -268,6 +268,7 @@ static const u32 tegra30_mc_ctx[] = {
 	MC_INTMASK,
 };
 
+#ifdef CONFIG_PM
 static int tegra30_mc_suspend(struct device *dev)
 {
 	int i;
@@ -291,6 +292,7 @@ static int tegra30_mc_resume(struct device *dev)
 	mc_readl(mc, MC_TIMING_CONTROL);
 	return 0;
 }
+#endif
 
 static UNIVERSAL_DEV_PM_OPS(tegra30_mc_pm,
 			    tegra30_mc_suspend,