From 02f69ef5bd21c70f82bc2772f7c0ea85ad7b4f36 Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Fri, 31 Aug 2012 15:07:20 +0530 Subject: [PATCH] --- yaml --- r: 339867 b: refs/heads/master c: efeedcf2a9137c9be0b833cb76b05315fe231197 h: refs/heads/master i: 339865: 4270d58d070659f3583d81b2925ea9e37d0b0c20 339863: 63b5001059319d86acc74a95b29008946159ffc1 v: v3 --- [refs] | 2 +- trunk/arch/arm/boot/dts/am335x-bone.dts | 6 ++++++ trunk/arch/arm/boot/dts/am335x-evm.dts | 6 ++++++ trunk/arch/arm/boot/dts/am33xx.dtsi | 15 +++++++++++++++ 4 files changed, 28 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index a76d7308efdd..47c363e1c649 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 5a8095e9d02da19f3bab738e82c0520ecd62d6af +refs/heads/master: efeedcf2a9137c9be0b833cb76b05315fe231197 diff --git a/trunk/arch/arm/boot/dts/am335x-bone.dts b/trunk/arch/arm/boot/dts/am335x-bone.dts index c634f87e230e..91eee97371ea 100644 --- a/trunk/arch/arm/boot/dts/am335x-bone.dts +++ b/trunk/arch/arm/boot/dts/am335x-bone.dts @@ -13,6 +13,12 @@ model = "TI AM335x BeagleBone"; compatible = "ti,am335x-bone", "ti,am33xx"; + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + memory { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ diff --git a/trunk/arch/arm/boot/dts/am335x-evm.dts b/trunk/arch/arm/boot/dts/am335x-evm.dts index 185d6325a458..4707cda9e4fe 100644 --- a/trunk/arch/arm/boot/dts/am335x-evm.dts +++ b/trunk/arch/arm/boot/dts/am335x-evm.dts @@ -13,6 +13,12 @@ model = "TI AM335x EVM"; compatible = "ti,am335x-evm", "ti,am33xx"; + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + memory { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ diff --git a/trunk/arch/arm/boot/dts/am33xx.dtsi b/trunk/arch/arm/boot/dts/am33xx.dtsi index bb31bff01998..b4e3e4793b95 100644 --- a/trunk/arch/arm/boot/dts/am33xx.dtsi +++ b/trunk/arch/arm/boot/dts/am33xx.dtsi @@ -25,6 +25,21 @@ cpus { cpu@0 { compatible = "arm,cortex-a8"; + + /* + * To consider voltage drop between PMIC and SoC, + * tolerance value is reduced to 2% from 4% and + * voltage value is increased as a precaution. + */ + operating-points = < + /* kHz uV */ + 720000 1285000 + 600000 1225000 + 500000 1125000 + 275000 1125000 + >; + voltage-tolerance = <2>; /* 2 percentage */ + clock-latency = <300000>; /* From omap-cpufreq driver */ }; };