From 039801dfe8069228594e495a72f1d1a0755bf0f7 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 28 Jan 2009 12:08:11 -0700 Subject: [PATCH] --- yaml --- r: 137334 b: refs/heads/master c: f0587b63c24e0c7539c6e77f1bfc68e6053608c7 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-omap2/clock34xx.c | 13 ++++++++----- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/[refs] b/[refs] index d817ad89f3b9..17836d5a6a80 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f266950d0234599cc6d4a5602e43d0fb782de1d2 +refs/heads/master: f0587b63c24e0c7539c6e77f1bfc68e6053608c7 diff --git a/trunk/arch/arm/mach-omap2/clock34xx.c b/trunk/arch/arm/mach-omap2/clock34xx.c index cb5e068feb56..fdfc7d582913 100644 --- a/trunk/arch/arm/mach-omap2/clock34xx.c +++ b/trunk/arch/arm/mach-omap2/clock34xx.c @@ -563,14 +563,17 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ _omap3_noncore_dpll_bypass(clk); + /* Set jitter correction */ + v = __raw_readl(dd->control_reg); + v &= ~dd->freqsel_mask; + v |= freqsel << __ffs(dd->freqsel_mask); + __raw_writel(v, dd->control_reg); + + /* Set DPLL multiplier, divider */ v = __raw_readl(dd->mult_div1_reg); v &= ~(dd->mult_mask | dd->div1_mask); - - /* Set mult (M), div1 (N), freqsel */ v |= m << __ffs(dd->mult_mask); - v |= n << __ffs(dd->div1_mask); - v |= freqsel << __ffs(dd->freqsel_mask); - + v |= (n - 1) << __ffs(dd->div1_mask); __raw_writel(v, dd->mult_div1_reg); /* We let the clock framework set the other output dividers later */