From 03ff8545db46cae8b395a237f5d8ee07e876d23f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 24 Oct 2011 12:57:57 -0400 Subject: [PATCH] --- yaml --- r: 274984 b: refs/heads/master c: 06c9c2332cc3bffcc184f32ee503dc0a4eb83de0 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/radeon/evergreen_blit_kms.c | 11 +++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index c3e176c8c02e..9e741d1b9a3e 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 9bb7703c5ea62ca1925cbfa0cd776f04de96fcf2 +refs/heads/master: 06c9c2332cc3bffcc184f32ee503dc0a4eb83de0 diff --git a/trunk/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/trunk/drivers/gpu/drm/radeon/evergreen_blit_kms.c index 879f7335029e..551e76f283f7 100644 --- a/trunk/drivers/gpu/drm/radeon/evergreen_blit_kms.c +++ b/trunk/drivers/gpu/drm/radeon/evergreen_blit_kms.c @@ -94,6 +94,15 @@ cp_set_surface_sync(struct radeon_device *rdev, else cp_coher_size = ((size + 255) >> 8); + if (rdev->family >= CHIP_CAYMAN) { + /* CP_COHER_CNTL2 has to be set manually when submitting a surface_sync + * to the RB directly. For IBs, the CP programs this as part of the + * surface_sync packet. + */ + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); + radeon_ring_write(rdev, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2); + radeon_ring_write(rdev, 0); /* CP_COHER_CNTL2 */ + } radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); radeon_ring_write(rdev, sync_type); radeon_ring_write(rdev, cp_coher_size); @@ -621,6 +630,8 @@ int evergreen_blit_init(struct radeon_device *rdev) rdev->r600_blit.ring_size_common += 10; /* fence emit for done copy */ rdev->r600_blit.ring_size_per_loop = 74; + if (rdev->family >= CHIP_CAYMAN) + rdev->r600_blit.ring_size_per_loop += 9; /* additional DWs for surface sync */ rdev->r600_blit.max_dim = 16384;