From 042e0488e3ff0cb2f6277944836116ab36d740c9 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Tue, 16 Aug 2011 11:49:08 +0200 Subject: [PATCH] --- yaml --- r: 272916 b: refs/heads/master c: 476b679a5d785d1244f6b43ad26877acf278cd18 h: refs/heads/master v: v3 --- [refs] | 2 +- .../devicetree/bindings/arm/omap/dsp.txt | 14 ++++++++++ .../devicetree/bindings/arm/omap/iva.txt | 19 +++++++++++++ .../devicetree/bindings/arm/omap/mpu.txt | 27 +++++++++++++++++++ trunk/arch/arm/boot/dts/omap3.dtsi | 19 +++++++++++++ trunk/arch/arm/boot/dts/omap4.dtsi | 23 ++++++++++++++++ trunk/arch/arm/mach-omap2/pm.c | 3 ++- 7 files changed, 105 insertions(+), 2 deletions(-) create mode 100644 trunk/Documentation/devicetree/bindings/arm/omap/dsp.txt create mode 100644 trunk/Documentation/devicetree/bindings/arm/omap/iva.txt create mode 100644 trunk/Documentation/devicetree/bindings/arm/omap/mpu.txt diff --git a/[refs] b/[refs] index 169f2379c0f8..52ac267dd90c 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: ad8dfac66fb1995014060302bda19a15bc62bd6d +refs/heads/master: 476b679a5d785d1244f6b43ad26877acf278cd18 diff --git a/trunk/Documentation/devicetree/bindings/arm/omap/dsp.txt b/trunk/Documentation/devicetree/bindings/arm/omap/dsp.txt new file mode 100644 index 000000000000..d3830a32ce08 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/arm/omap/dsp.txt @@ -0,0 +1,14 @@ +* TI - DSP (Digital Signal Processor) + +TI DSP included in OMAP SoC + +Required properties: +- compatible : Should be "ti,omap3-c64" for OMAP3 & 4 +- ti,hwmods: "dsp" + +Examples: + +dsp { + compatible = "ti,omap3-c64"; + ti,hwmods = "dsp"; +}; diff --git a/trunk/Documentation/devicetree/bindings/arm/omap/iva.txt b/trunk/Documentation/devicetree/bindings/arm/omap/iva.txt new file mode 100644 index 000000000000..6d6295171358 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/arm/omap/iva.txt @@ -0,0 +1,19 @@ +* TI - IVA (Imaging and Video Accelerator) subsystem + +The IVA contain various audio, video or imaging HW accelerator +depending of the version. + +Required properties: +- compatible : Should be: + - "ti,ivahd" for OMAP4 + - "ti,iva2.2" for OMAP3 + - "ti,iva2.1" for OMAP2430 + - "ti,iva1" for OMAP2420 +- ti,hwmods: "iva" + +Examples: + +iva { + compatible = "ti,ivahd", "ti,iva"; + ti,hwmods = "iva"; +}; diff --git a/trunk/Documentation/devicetree/bindings/arm/omap/mpu.txt b/trunk/Documentation/devicetree/bindings/arm/omap/mpu.txt new file mode 100644 index 000000000000..1a5a42ce21bb --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/arm/omap/mpu.txt @@ -0,0 +1,27 @@ +* TI - MPU (Main Processor Unit) subsystem + +The MPU subsystem contain one or several ARM cores +depending of the version. +The MPU contain CPUs, GIC, L2 cache and a local PRCM. + +Required properties: +- compatible : Should be "ti,omap3-mpu" for OMAP3 + Should be "ti,omap4-mpu" for OMAP4 +- ti,hwmods: "mpu" + +Examples: + +- For an OMAP4 SMP system: + +mpu { + compatible = "ti,omap4-mpu"; + ti,hwmods = "mpu"; +}; + + +- For an OMAP3 monocore system: + +mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; +}; diff --git a/trunk/arch/arm/boot/dts/omap3.dtsi b/trunk/arch/arm/boot/dts/omap3.dtsi index d558785c8b2c..d202bb5ec7ef 100644 --- a/trunk/arch/arm/boot/dts/omap3.dtsi +++ b/trunk/arch/arm/boot/dts/omap3.dtsi @@ -13,12 +13,31 @@ / { compatible = "ti,omap3430", "ti,omap3"; + cpus { + cpu@0 { + compatible = "arm,cortex-a8"; + }; + }; + /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. */ soc { compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; + }; + + iva { + compatible = "ti,iva2.2"; + ti,hwmods = "iva"; + + dsp { + compatible = "ti,omap3-c64"; + }; + }; }; /* diff --git a/trunk/arch/arm/boot/dts/omap4.dtsi b/trunk/arch/arm/boot/dts/omap4.dtsi index b85a39debbea..4c61c829043a 100644 --- a/trunk/arch/arm/boot/dts/omap4.dtsi +++ b/trunk/arch/arm/boot/dts/omap4.dtsi @@ -23,12 +23,35 @@ aliases { }; + cpus { + cpu@0 { + compatible = "arm,cortex-a9"; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + }; + }; + /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. */ soc { compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap4-mpu"; + ti,hwmods = "mpu"; + }; + + dsp { + compatible = "ti,omap3-c64"; + ti,hwmods = "dsp"; + }; + + iva { + compatible = "ti,ivahd"; + ti,hwmods = "iva"; + }; }; /* diff --git a/trunk/arch/arm/mach-omap2/pm.c b/trunk/arch/arm/mach-omap2/pm.c index 9e78261fbfba..2ab7a9e17fe2 100644 --- a/trunk/arch/arm/mach-omap2/pm.c +++ b/trunk/arch/arm/mach-omap2/pm.c @@ -215,7 +215,8 @@ static void __init omap4_init_voltages(void) static int __init omap2_common_pm_init(void) { - omap2_init_processor_devices(); + if (!of_have_populated_dt()) + omap2_init_processor_devices(); omap_pm_if_init(); return 0;