From 0457191c86f2b5b10c785f3521ef64dad4a7b844 Mon Sep 17 00:00:00 2001 From: Lee Revell Date: Sun, 1 May 2005 08:58:49 -0700 Subject: [PATCH] --- yaml --- r: 669 b: refs/heads/master c: a6954ba2e8d344a07e066737827116eb7bc0fdcd h: refs/heads/master i: 667: 1c7b2d1a811f0fda0f8c82690ec9ee3eee312e86 v: v3 --- [refs] | 2 +- trunk/arch/i386/kernel/cpu/mtrr/main.c | 14 +++++++++----- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/[refs] b/[refs] index 39b3139c72c3..20a09a4cd450 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 48c88211a65bc30f030fe228bda30fda870deb90 +refs/heads/master: a6954ba2e8d344a07e066737827116eb7bc0fdcd diff --git a/trunk/arch/i386/kernel/cpu/mtrr/main.c b/trunk/arch/i386/kernel/cpu/mtrr/main.c index 54999e4c55fd..e1c2042b9b7e 100644 --- a/trunk/arch/i386/kernel/cpu/mtrr/main.c +++ b/trunk/arch/i386/kernel/cpu/mtrr/main.c @@ -72,17 +72,21 @@ void set_mtrr_ops(struct mtrr_ops * ops) static int have_wrcomb(void) { struct pci_dev *dev; + u8 rev; if ((dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) { - /* ServerWorks LE chipsets have problems with write-combining + /* ServerWorks LE chipsets < rev 6 have problems with write-combining Don't allow it and leave room for other chipsets to be tagged */ if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS && dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) { - printk(KERN_INFO "mtrr: Serverworks LE detected. Write-combining disabled.\n"); - pci_dev_put(dev); - return 0; + pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); + if (rev <= 5) { + printk(KERN_INFO "mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n"); + pci_dev_put(dev); + return 0; + } } - /* Intel 450NX errata # 23. Non ascending cachline evictions to + /* Intel 450NX errata # 23. Non ascending cacheline evictions to write combining memory may resulting in data corruption */ if (dev->vendor == PCI_VENDOR_ID_INTEL && dev->device == PCI_DEVICE_ID_INTEL_82451NX) {