From 045bc75a14fbcc15cbc5760d529359386b2eb61d Mon Sep 17 00:00:00 2001
From: Will Deacon <will.deacon@arm.com>
Date: Tue, 22 Jan 2013 19:11:38 +0000
Subject: [PATCH] --- yaml --- r: 362681 b: refs/heads/master c:
 794fe85da484353dedcb5dc6da14d923d0645fc3 h: refs/heads/master i:   362679:
 2acb7a81e65b9ff8ef7d3722b88b038fdf4bb76f v: v3

---
 [refs]                       | 2 +-
 trunk/arch/arm/mm/cache-v4.S | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index 931bf3f724c0..d634ca8eb2a7 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 3ef52f2a00efc5f83ae6d40e55cae96ce275893f
+refs/heads/master: 794fe85da484353dedcb5dc6da14d923d0645fc3
diff --git a/trunk/arch/arm/mm/cache-v4.S b/trunk/arch/arm/mm/cache-v4.S
index 43e5d77be677..a7ba68f59f0c 100644
--- a/trunk/arch/arm/mm/cache-v4.S
+++ b/trunk/arch/arm/mm/cache-v4.S
@@ -58,7 +58,7 @@ ENTRY(v4_flush_kern_cache_all)
 ENTRY(v4_flush_user_cache_range)
 #ifdef CONFIG_CPU_CP15
 	mov	ip, #0
-	mcreq	p15, 0, ip, c7, c7, 0		@ flush ID cache
+	mcr	p15, 0, ip, c7, c7, 0		@ flush ID cache
 	mov	pc, lr
 #else
 	/* FALLTHROUGH */