From 05295ece1114d1a8ea69cfeb4af8f782f6c7148b Mon Sep 17 00:00:00 2001 From: Juergen Beisert Date: Fri, 2 Oct 2009 11:24:49 +0200 Subject: [PATCH] --- yaml --- r: 172465 b: refs/heads/master c: 9e0afdf8f32f34f7e67db4d4622cb13e39a0e5db h: refs/heads/master i: 172463: 76c37f280c25c90c9f5a93a503b76357839609fc v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-mx3/clock-imx35.c | 30 +++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index f277c345829f..a6f49be03f50 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 060d20d32ae7c6a20a8eac465795ed5bc9b37f7c +refs/heads/master: 9e0afdf8f32f34f7e67db4d4622cb13e39a0e5db diff --git a/trunk/arch/arm/mach-mx3/clock-imx35.c b/trunk/arch/arm/mach-mx3/clock-imx35.c index c595260ec1f9..33a23e7c7e92 100644 --- a/trunk/arch/arm/mach-mx3/clock-imx35.c +++ b/trunk/arch/arm/mach-mx3/clock-imx35.c @@ -387,6 +387,35 @@ DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL); DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL); DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL); +static int clk_dummy_enable(struct clk *clk) +{ + return 0; +} + +static void clk_dummy_disable(struct clk *clk) +{ +} + +static unsigned long get_rate_nfc(struct clk *clk) +{ + unsigned long div1; + + div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1; + + return get_rate_ahb(NULL) / div1; +} + +/* NAND Controller: It seems it can't be disabled */ +static struct clk nfc_clk = { + .id = 0, + .enable_reg = 0, + .enable_shift = 0, + .get_rate = get_rate_nfc, + .set_rate = NULL, /* set_rate_nfc, */ + .enable = clk_dummy_enable, + .disable = clk_dummy_disable +}; + #define _REGISTER_CLOCK(d, n, c) \ { \ .dev_id = d, \ @@ -449,6 +478,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "csi", csi_clk) _REGISTER_CLOCK(NULL, "iim", iim_clk) _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk) + _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) }; int __init mx35_clocks_init()