From 05bbc0a3ef62ce6a882ec47390da099e6bea3327 Mon Sep 17 00:00:00 2001 From: Josh Boyer Date: Fri, 24 Apr 2009 08:57:47 -0400 Subject: [PATCH] --- yaml --- r: 144258 b: refs/heads/master c: 9ae2ccf26416ed52874718e2b0c8e6813253263a h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/MAINTAINERS | 2 +- trunk/arch/powerpc/boot/dts/gef_ppc9a.dts | 1 - trunk/arch/powerpc/include/asm/mmu.h | 6 ++++++ trunk/arch/powerpc/include/asm/ppc-opcode.h | 11 ++++++++++- trunk/arch/powerpc/kernel/cputable.c | 2 +- trunk/arch/powerpc/mm/tlb_nohash_low.S | 16 ++++++++++++++-- 7 files changed, 33 insertions(+), 7 deletions(-) diff --git a/[refs] b/[refs] index eefc2a27d010..245adb4fdc4f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 28853da20c840f0d147674ac850c539d3306109f +refs/heads/master: 9ae2ccf26416ed52874718e2b0c8e6813253263a diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index e133ba4de416..53d6e611eadd 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -3375,7 +3375,7 @@ P: Matt Porter M: mporter@kernel.crashing.org W: http://www.penguinppc.org/ L: linuxppc-dev@ozlabs.org -T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git S: Maintained LINUX FOR POWERPC EMBEDDED XILINX VIRTEX diff --git a/trunk/arch/powerpc/boot/dts/gef_ppc9a.dts b/trunk/arch/powerpc/boot/dts/gef_ppc9a.dts index 53a7a6255909..d47ad0718759 100644 --- a/trunk/arch/powerpc/boot/dts/gef_ppc9a.dts +++ b/trunk/arch/powerpc/boot/dts/gef_ppc9a.dts @@ -161,7 +161,6 @@ #address-cells = <1>; #size-cells = <1>; #interrupt-cells = <2>; - device_type = "soc"; compatible = "fsl,mpc8641-soc", "simple-bus"; ranges = <0x0 0xfef00000 0x00100000>; reg = <0xfef00000 0x100000>; // CCSRBAR 1M diff --git a/trunk/arch/powerpc/include/asm/mmu.h b/trunk/arch/powerpc/include/asm/mmu.h index cbf154387091..86d2366ab6a1 100644 --- a/trunk/arch/powerpc/include/asm/mmu.h +++ b/trunk/arch/powerpc/include/asm/mmu.h @@ -52,6 +52,12 @@ */ #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) +/* This indicates that the processor uses the wrong opcode for tlbilx + * instructions. During the ISA 2.06 development the opcode for tlbilx + * changed and some early implementations used to old opcode + */ +#define MMU_FTR_TLBILX_EARLY_OPCODE ASM_CONST(0x00400000) + #ifndef __ASSEMBLY__ #include diff --git a/trunk/arch/powerpc/include/asm/ppc-opcode.h b/trunk/arch/powerpc/include/asm/ppc-opcode.h index 640ccbbc0977..ef4da37f3c10 100644 --- a/trunk/arch/powerpc/include/asm/ppc-opcode.h +++ b/trunk/arch/powerpc/include/asm/ppc-opcode.h @@ -44,6 +44,7 @@ #define PPC_INST_STSWI 0x7c0005aa #define PPC_INST_STSWX 0x7c00052a #define PPC_INST_TLBILX 0x7c000024 +#define PPC_INST_TLBILX_EARLY 0x7c000626 #define PPC_INST_WAIT 0x7c00007c /* macros to insert fields into opcodes */ @@ -63,10 +64,18 @@ #define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) #define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \ - __PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b)) + __PPC_T_TLB(t) | \ + __PPC_RA(a) | __PPC_RB(b)) #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) + +#define PPC_TLBILX_EARLY(t, a, b) stringify_in_c(.long PPC_INST_TLBILX_EARLY | \ + __PPC_T_TLB(t) | \ + __PPC_RA(a) | __PPC_RB(b)) +#define PPC_TLBILX_ALL_EARLY(a, b) PPC_TLBILX_EARLY(0, a, b) +#define PPC_TLBILX_PID_EARLY(a, b) PPC_TLBILX_EARLY(1, a, b) +#define PPC_TLBILX_VA_EARLY(a, b) PPC_TLBILX_EARLY(3, a, b) #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ __PPC_WC(w)) diff --git a/trunk/arch/powerpc/kernel/cputable.c b/trunk/arch/powerpc/kernel/cputable.c index cd1b687544f3..57db50f40289 100644 --- a/trunk/arch/powerpc/kernel/cputable.c +++ b/trunk/arch/powerpc/kernel/cputable.c @@ -1766,7 +1766,7 @@ static struct cpu_spec __initdata cpu_specs[] = { .cpu_features = CPU_FTRS_E500MC, .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | - MMU_FTR_USE_TLBILX, + MMU_FTR_USE_TLBILX | MMU_FTR_TLBILX_EARLY_OPCODE, .icache_bsize = 64, .dcache_bsize = 64, .num_pmcs = 4, diff --git a/trunk/arch/powerpc/mm/tlb_nohash_low.S b/trunk/arch/powerpc/mm/tlb_nohash_low.S index 3037911279b1..45fed3698349 100644 --- a/trunk/arch/powerpc/mm/tlb_nohash_low.S +++ b/trunk/arch/powerpc/mm/tlb_nohash_low.S @@ -138,7 +138,11 @@ BEGIN_MMU_FTR_SECTION andi. r3,r3,MMUCSR0_TLBFI@l bne 1b MMU_FTR_SECTION_ELSE - PPC_TLBILX_ALL(0,0) + BEGIN_MMU_FTR_SECTION_NESTED(96) + PPC_TLBILX_ALL(0,r3) + MMU_FTR_SECTION_ELSE_NESTED(96) + PPC_TLBILX_ALL_EARLY(0,r3) + ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) msync isync @@ -151,7 +155,11 @@ BEGIN_MMU_FTR_SECTION wrteei 0 mfspr r4,SPRN_MAS6 /* save MAS6 */ mtspr SPRN_MAS6,r3 + BEGIN_MMU_FTR_SECTION_NESTED(96) PPC_TLBILX_PID(0,0) + MMU_FTR_SECTION_ELSE_NESTED(96) + PPC_TLBILX_PID_EARLY(0,0) + ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) mtspr SPRN_MAS6,r4 /* restore MAS6 */ wrtee r10 MMU_FTR_SECTION_ELSE @@ -185,12 +193,16 @@ BEGIN_MMU_FTR_SECTION mtspr SPRN_MAS1,r4 tlbwe MMU_FTR_SECTION_ELSE + BEGIN_MMU_FTR_SECTION_NESTED(96) PPC_TLBILX_VA(0,r3) + MMU_FTR_SECTION_ELSE_NESTED(96) + PPC_TLBILX_VA_EARLY(0,r3) + ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) msync isync 1: wrtee r10 blr -#else +#elif #error Unsupported processor type ! #endif