From 06011d316d41c133ced5dedc6ed321cda00a5f7a Mon Sep 17 00:00:00 2001
From: Mark Zhang <markz@nvidia.com>
Date: Tue, 16 Oct 2012 16:31:49 +0800
Subject: [PATCH] --- yaml --- r: 334619 b: refs/heads/master c:
 786621308cfbb9421a54773e57dbdbe504c417cc h: refs/heads/master i:   334617:
 13da4963d7211bb5f3e3d831a4026571e90dc4b3   334615:
 362fb9dd67178959d5ad69837d693ef9a09b5215 v: v3

---
 [refs]                                        |  2 +-
 trunk/arch/arm/boot/dts/Makefile              |  2 --
 trunk/arch/arm/boot/dts/imx6q-arm2.dts        | 10 +--------
 trunk/arch/arm/boot/dts/wm8505.dtsi           |  4 ++--
 .../arm/mach-shmobile/board-armadillo800eva.c |  2 +-
 trunk/arch/arm/mach-shmobile/clock-r8a7779.c  | 22 +++++++++----------
 trunk/arch/arm/mach-tegra/tegra30_clocks.c    |  2 +-
 7 files changed, 17 insertions(+), 27 deletions(-)

diff --git a/[refs] b/[refs]
index fe13bb2051b9..a2366c3c8547 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 69648ae885e7de8be223362ea6e95c79066069e7
+refs/heads/master: 786621308cfbb9421a54773e57dbdbe504c417cc
diff --git a/trunk/arch/arm/boot/dts/Makefile b/trunk/arch/arm/boot/dts/Makefile
index f37cf9fa5fa0..c1ce813fcc4a 100644
--- a/trunk/arch/arm/boot/dts/Makefile
+++ b/trunk/arch/arm/boot/dts/Makefile
@@ -25,8 +25,6 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
 	exynos4210-trats.dtb \
 	exynos5250-smdk5250.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
-dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
-	integratorcp.dtb
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
 	kirkwood-dns325.dtb \
diff --git a/trunk/arch/arm/boot/dts/imx6q-arm2.dts b/trunk/arch/arm/boot/dts/imx6q-arm2.dts
index 5bfa02a3f85c..15df4c105e89 100644
--- a/trunk/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/trunk/arch/arm/boot/dts/imx6q-arm2.dts
@@ -37,13 +37,6 @@
 					pinctrl_hog: hoggrp {
 						fsl,pins = <
 							176  0x80000000	/* MX6Q_PAD_EIM_D25__GPIO_3_25 */
-						>;
-					};
-				};
-
-				arm2 {
-					pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
-						fsl,pins = <
 							1363 0x80000000	/* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
 							1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
 						>;
@@ -65,8 +58,7 @@
 				wp-gpios = <&gpio6 14 0>;
 				vmmc-supply = <&reg_3p3v>;
 				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_usdhc3_1
-					     &pinctrl_usdhc3_arm2>;
+				pinctrl-0 = <&pinctrl_usdhc3_1>;
 				status = "okay";
 			};
 
diff --git a/trunk/arch/arm/boot/dts/wm8505.dtsi b/trunk/arch/arm/boot/dts/wm8505.dtsi
index 330f833ac3b0..b459691655ab 100644
--- a/trunk/arch/arm/boot/dts/wm8505.dtsi
+++ b/trunk/arch/arm/boot/dts/wm8505.dtsi
@@ -71,13 +71,13 @@
 		ehci@d8007100 {
 			compatible = "via,vt8500-ehci";
 			reg = <0xd8007100 0x200>;
-			interrupts = <1>;
+			interrupts = <43>;
 		};
 
 		uhci@d8007300 {
 			compatible = "platform-uhci";
 			reg = <0xd8007300 0x200>;
-			interrupts = <0>;
+			interrupts = <43>;
 		};
 
 		fb@d8050800 {
diff --git a/trunk/arch/arm/mach-shmobile/board-armadillo800eva.c b/trunk/arch/arm/mach-shmobile/board-armadillo800eva.c
index 3cc8b1c21da9..2912eab3b967 100644
--- a/trunk/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/trunk/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1196,7 +1196,7 @@ static void __init eva_init(void)
 
 #ifdef CONFIG_CACHE_L2X0
 	/* Early BRESP enable, Shared attribute override enable, 32K*8way */
-	l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
+	l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff);
 #endif
 
 	i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
diff --git a/trunk/arch/arm/mach-shmobile/clock-r8a7779.c b/trunk/arch/arm/mach-shmobile/clock-r8a7779.c
index 37b2a3133b3b..3cafb6ab5e9a 100644
--- a/trunk/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/trunk/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -24,17 +24,17 @@
 #include <linux/clkdev.h>
 #include <mach/common.h>
 
-#define FRQMR		IOMEM(0xffc80014)
-#define MSTPCR0		IOMEM(0xffc80030)
-#define MSTPCR1		IOMEM(0xffc80034)
-#define MSTPCR3		IOMEM(0xffc8003c)
-#define MSTPSR1		IOMEM(0xffc80044)
-#define MSTPSR4		IOMEM(0xffc80048)
-#define MSTPSR6		IOMEM(0xffc8004c)
-#define MSTPCR4		IOMEM(0xffc80050)
-#define MSTPCR5		IOMEM(0xffc80054)
-#define MSTPCR6		IOMEM(0xffc80058)
-#define MSTPCR7		IOMEM(0xffc80040)
+#define FRQMR   0xffc80014
+#define MSTPCR0 0xffc80030
+#define MSTPCR1 0xffc80034
+#define MSTPCR3 0xffc8003c
+#define MSTPSR1 0xffc80044
+#define MSTPSR4 0xffc80048
+#define MSTPSR6 0xffc8004c
+#define MSTPCR4 0xffc80050
+#define MSTPCR5 0xffc80054
+#define MSTPCR6 0xffc80058
+#define MSTPCR7 0xffc80040
 
 /* ioremap() through clock mapping mandatory to avoid
  * collision with ARM coherent DMA virtual memory range.
diff --git a/trunk/arch/arm/mach-tegra/tegra30_clocks.c b/trunk/arch/arm/mach-tegra/tegra30_clocks.c
index 5cd502c27163..e9de5dfd94ec 100644
--- a/trunk/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/trunk/arch/arm/mach-tegra/tegra30_clocks.c
@@ -1199,7 +1199,7 @@ static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 {
 	struct clk_tegra *c = to_clk_tegra(hw);
 	unsigned long input_rate = *prate;
-	unsigned long output_rate = *prate;
+	u64 output_rate = *prate;
 	const struct clk_pll_freq_table *sel;
 	struct clk_pll_freq_table cfg;
 	int mul;