From 06127a5c971e99ee5732b213012cc28501fce435 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Fri, 3 Jun 2011 17:38:49 +0100 Subject: [PATCH] --- yaml --- r: 258314 b: refs/heads/master c: 7b35fa47eecd0c746924a6d6c2a897d2cec778ba h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/kernel/perf_event_v7.c | 10 ---------- 2 files changed, 1 insertion(+), 11 deletions(-) diff --git a/[refs] b/[refs] index 36f61953683e..c9176fb2acc7 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 7665d9d2df2eb26284467c2f8591004bd511c75f +refs/heads/master: 7b35fa47eecd0c746924a6d6c2a897d2cec778ba diff --git a/trunk/arch/arm/kernel/perf_event_v7.c b/trunk/arch/arm/kernel/perf_event_v7.c index 4960686afb58..554eba3dbf65 100644 --- a/trunk/arch/arm/kernel/perf_event_v7.c +++ b/trunk/arch/arm/kernel/perf_event_v7.c @@ -207,11 +207,6 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] }, }, [C(DTLB)] = { - /* - * Only ITLB misses and DTLB refills are supported. - * If users want the DTLB refills misses a raw counter - * must be used. - */ [C(OP_READ)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, @@ -323,11 +318,6 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] }, }, [C(DTLB)] = { - /* - * Only ITLB misses and DTLB refills are supported. - * If users want the DTLB refills misses a raw counter - * must be used. - */ [C(OP_READ)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,