From 06592ce4a774cd06dcc3206c541c18cab9cc5ca2 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Wed, 6 Mar 2013 20:03:18 -0300 Subject: [PATCH] --- yaml --- r: 371196 b: refs/heads/master c: 86d52df633869b54a6f0b9a8f088be9c89a42c3d h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_drv.h | 1 + trunk/drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 7feba81f4383..bcfee540d714 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: ca291363ccc7c0e9b337fe3b46f732247238537e +refs/heads/master: 86d52df633869b54a6f0b9a8f088be9c89a42c3d diff --git a/trunk/drivers/gpu/drm/i915/i915_drv.h b/trunk/drivers/gpu/drm/i915/i915_drv.h index ca6b215c090c..71f285c56f1e 100644 --- a/trunk/drivers/gpu/drm/i915/i915_drv.h +++ b/trunk/drivers/gpu/drm/i915/i915_drv.h @@ -1339,6 +1339,7 @@ struct drm_i915_file_private { #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) #define HAS_DDI(dev) (IS_HASWELL(dev)) +#define HAS_POWER_WELL(dev) (IS_HASWELL(dev)) #define INTEL_PCH_DEVICE_ID_MASK 0xff00 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 diff --git a/trunk/drivers/gpu/drm/i915/intel_pm.c b/trunk/drivers/gpu/drm/i915/intel_pm.c index be43f7107c99..44a23b9b8e53 100644 --- a/trunk/drivers/gpu/drm/i915/intel_pm.c +++ b/trunk/drivers/gpu/drm/i915/intel_pm.c @@ -4076,7 +4076,7 @@ void intel_set_power_well(struct drm_device *dev, bool enable) bool is_enabled, enable_requested; uint32_t tmp; - if (!IS_HASWELL(dev)) + if (!HAS_POWER_WELL(dev)) return; tmp = I915_READ(HSW_PWR_WELL_DRIVER); @@ -4111,7 +4111,7 @@ void intel_init_power_well(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (!IS_HASWELL(dev)) + if (!HAS_POWER_WELL(dev)) return; /* For now, we need the power well to be always enabled. */