From 066f02d749a1901e9d7db9bbb9387025445ad90c Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Wed, 4 Jul 2007 01:38:13 +0200 Subject: [PATCH] --- yaml --- r: 58192 b: refs/heads/master c: 5dcccd8d7eae870d85c3f175fd0823d3da07d0e3 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/i386/kernel/cpu/perfctr-watchdog.c | 35 +++++++++++++++++-- 2 files changed, 34 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 8f4c597f3737..240b4f451cfc 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 0f8dc2f06560e2ca126d1670a24126ba08357d38 +refs/heads/master: 5dcccd8d7eae870d85c3f175fd0823d3da07d0e3 diff --git a/trunk/arch/i386/kernel/cpu/perfctr-watchdog.c b/trunk/arch/i386/kernel/cpu/perfctr-watchdog.c index f0b67630b90d..4d26d514c56f 100644 --- a/trunk/arch/i386/kernel/cpu/perfctr-watchdog.c +++ b/trunk/arch/i386/kernel/cpu/perfctr-watchdog.c @@ -55,14 +55,45 @@ static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk); /* converts an msr to an appropriate reservation bit */ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr) { - return wd_ops ? msr - wd_ops->perfctr : 0; + /* returns the bit offset of the performance counter register */ + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_AMD: + return (msr - MSR_K7_PERFCTR0); + case X86_VENDOR_INTEL: + if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) + return (msr - MSR_ARCH_PERFMON_PERFCTR0); + + switch (boot_cpu_data.x86) { + case 6: + return (msr - MSR_P6_PERFCTR0); + case 15: + return (msr - MSR_P4_BPU_PERFCTR0); + } + } + return 0; } /* converts an msr to an appropriate reservation bit */ /* returns the bit offset of the event selection register */ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr) { - return wd_ops ? msr - wd_ops->evntsel : 0; + /* returns the bit offset of the event selection register */ + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_AMD: + return (msr - MSR_K7_EVNTSEL0); + case X86_VENDOR_INTEL: + if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) + return (msr - MSR_ARCH_PERFMON_EVENTSEL0); + + switch (boot_cpu_data.x86) { + case 6: + return (msr - MSR_P6_EVNTSEL0); + case 15: + return (msr - MSR_P4_BSU_ESCR0); + } + } + return 0; + } /* checks for a bit availability (hack for oprofile) */