From 0671f8b8a29ee1b7adc90b8fdd0f24d8ab0e18c9 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Thu, 26 May 2011 11:20:19 +0100 Subject: [PATCH] --- yaml --- r: 252402 b: refs/heads/master c: a248b13b21ae00b97638b4f435c8df3075808b5d h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mm/cache-v6.S | 1 + trunk/arch/arm/mm/cache-v7.S | 2 ++ 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index e6faf93d96fe..0a834cb8e861 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: a85fab1c795c88675ba3e23e68d821c57e9920fc +refs/heads/master: a248b13b21ae00b97638b4f435c8df3075808b5d diff --git a/trunk/arch/arm/mm/cache-v6.S b/trunk/arch/arm/mm/cache-v6.S index c96fa1b3f49f..73b4a8b66a57 100644 --- a/trunk/arch/arm/mm/cache-v6.S +++ b/trunk/arch/arm/mm/cache-v6.S @@ -176,6 +176,7 @@ ENDPROC(v6_coherent_kern_range) */ ENTRY(v6_flush_kern_dcache_area) add r1, r0, r1 + bic r0, r0, #D_CACHE_LINE_SIZE - 1 1: #ifdef HARVARD_CACHE mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line diff --git a/trunk/arch/arm/mm/cache-v7.S b/trunk/arch/arm/mm/cache-v7.S index dc18d81ef8ce..d32f02b61866 100644 --- a/trunk/arch/arm/mm/cache-v7.S +++ b/trunk/arch/arm/mm/cache-v7.S @@ -221,6 +221,8 @@ ENDPROC(v7_coherent_user_range) ENTRY(v7_flush_kern_dcache_area) dcache_line_size r2, r3 add r1, r0, r1 + sub r3, r2, #1 + bic r0, r0, r3 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line add r0, r0, r2