From 068649492e61c6b944ba182c0f34feba71ca510d Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 13 Apr 2011 18:57:57 -0400 Subject: [PATCH] --- yaml --- r: 251384 b: refs/heads/master c: 44491fbc5a228f3c2e61d842fd9fee0bfb839373 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/blackfin/kernel/setup.c | 4 ++-- trunk/arch/blackfin/mach-bf561/smp.c | 3 --- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/[refs] b/[refs] index b8af8fda5779..6ccc9aa89970 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 8d011f70b08f563b007743fd446a6022f0329cd4 +refs/heads/master: 44491fbc5a228f3c2e61d842fd9fee0bfb839373 diff --git a/trunk/arch/blackfin/kernel/setup.c b/trunk/arch/blackfin/kernel/setup.c index 6b09f5cf6313..11eff2c3e980 100644 --- a/trunk/arch/blackfin/kernel/setup.c +++ b/trunk/arch/blackfin/kernel/setup.c @@ -105,6 +105,8 @@ void __cpuinit bfin_setup_caches(unsigned int cpu) bfin_dcache_init(dcplb_tbl[cpu]); #endif + bfin_setup_cpudata(cpu); + /* * In cache coherence emulation mode, we need to have the * D-cache enabled before running any atomic operation which @@ -1036,8 +1038,6 @@ void __init setup_arch(char **cmdline_p) static int __init topology_init(void) { unsigned int cpu; - /* Record CPU-private information for the boot processor. */ - bfin_setup_cpudata(0); for_each_possible_cpu(cpu) { register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu); diff --git a/trunk/arch/blackfin/mach-bf561/smp.c b/trunk/arch/blackfin/mach-bf561/smp.c index 7b07740cf68c..390accf17ebc 100644 --- a/trunk/arch/blackfin/mach-bf561/smp.c +++ b/trunk/arch/blackfin/mach-bf561/smp.c @@ -62,9 +62,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu) bfin_write_SICB_IWR1(IWR_DISABLE_ALL); SSYNC(); - /* Store CPU-private information to the cpu_data array. */ - bfin_setup_cpudata(cpu); - /* We are done with local CPU inits, unblock the boot CPU. */ set_cpu_online(cpu, true); spin_lock(&boot_lock);