From 06a9710c7f900da0639fe45d3befff685d400415 Mon Sep 17 00:00:00 2001
From: Markus Pargmann <mpa@pengutronix.de>
Date: Sun, 7 Apr 2013 21:56:45 +0200
Subject: [PATCH] --- yaml --- r: 370491 b: refs/heads/master c:
 6f9d62d4f4d00a39332b24c128bd13ccfa259cba h: refs/heads/master i:   370489:
 3059f824f7da95fb033d77aaee659eb4b139b20c   370487:
 4c3dfc6d98713930451ca30fbdeffa00add774f7 v: v3

---
 [refs]                             |  2 +-
 trunk/arch/arm/boot/dts/imx51.dtsi | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 17047edab8b4..d28e27d11add 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 4617d2f0fb52a3e2c427be5ee6e79ecdc4b4ac1a
+refs/heads/master: 6f9d62d4f4d00a39332b24c128bd13ccfa259cba
diff --git a/trunk/arch/arm/boot/dts/imx51.dtsi b/trunk/arch/arm/boot/dts/imx51.dtsi
index 58204ee7d6d9..21bb786c5b31 100644
--- a/trunk/arch/arm/boot/dts/imx51.dtsi
+++ b/trunk/arch/arm/boot/dts/imx51.dtsi
@@ -56,6 +56,24 @@
 		};
 	};
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a8";
+			reg = <0>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			clocks = <&clks 24>;
+			clock-names = "cpu";
+			operating-points = <
+				/* kHz  uV (No regulator support) */
+				160000  0
+				800000  0
+			>;
+		};
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;