diff --git a/[refs] b/[refs]
index 9699ccf2a1d0..941d8be86d13 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
---
-refs/heads/master: 78ca7c37efaa541006269aa3d3e560ea7926e245
+refs/heads/master: 91ab9bf7c5322128d3b29c04393268658631e26a
diff --git a/trunk/Documentation/DocBook/kgdb.tmpl b/trunk/Documentation/DocBook/kgdb.tmpl
index 490d862c5f0d..d71b57fcf116 100644
--- a/trunk/Documentation/DocBook/kgdb.tmpl
+++ b/trunk/Documentation/DocBook/kgdb.tmpl
@@ -710,7 +710,18 @@ Task Addr Pid Parent [*] cpu State Thread Command
A simple shell
The kdb core command set
A registration API to register additional kdb shell commands.
- A good example of a self-contained kdb module is the "ftdump" command for dumping the ftrace buffer. See: kernel/trace/trace_kdb.c
+
+ A good example of a self-contained kdb module
+ is the "ftdump" command for dumping the ftrace buffer. See:
+ kernel/trace/trace_kdb.c
+ For an example of how to dynamically register
+ a new kdb command you can build the kdb_hello.ko kernel module
+ from samples/kdb/kdb_hello.c. To build this example you can
+ set CONFIG_SAMPLES=y and CONFIG_SAMPLE_KDB=m in your kernel
+ config. Later run "modprobe kdb_hello" and the next time you
+ enter the kdb shell, you can run the "hello"
+ command.
+
The implementation for kdb_printf() which
emits messages directly to I/O drivers, bypassing the kernel
log.
diff --git a/trunk/Makefile b/trunk/Makefile
index 6b23f1b15fc4..519db43052a0 100644
--- a/trunk/Makefile
+++ b/trunk/Makefile
@@ -204,6 +204,9 @@ ifeq ($(ARCH),x86_64)
endif
# Additional ARCH settings for sparc
+ifeq ($(ARCH),sparc32)
+ SRCARCH := sparc
+endif
ifeq ($(ARCH),sparc64)
SRCARCH := sparc
endif
diff --git a/trunk/arch/arm/include/asm/kgdb.h b/trunk/arch/arm/include/asm/kgdb.h
index 08265993227f..48066ce9ea34 100644
--- a/trunk/arch/arm/include/asm/kgdb.h
+++ b/trunk/arch/arm/include/asm/kgdb.h
@@ -70,7 +70,8 @@ extern int kgdb_fault_expected;
#define _GP_REGS 16
#define _FP_REGS 8
#define _EXTRA_REGS 2
-#define DBG_MAX_REG_NUM (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS)
+#define GDB_MAX_REGS (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS)
+#define DBG_MAX_REG_NUM (_GP_REGS + _FP_REGS + _EXTRA_REGS)
#define KGDB_MAX_NO_CPUS 1
#define BUFMAX 400
@@ -93,7 +94,7 @@ extern int kgdb_fault_expected;
#define _SPT 13
#define _LR 14
#define _PC 15
-#define _CPSR (DBG_MAX_REG_NUM - 1)
+#define _CPSR (GDB_MAX_REGS - 1)
/*
* So that we can denote the end of a frame for tracing,
diff --git a/trunk/arch/arm/kernel/kgdb.c b/trunk/arch/arm/kernel/kgdb.c
index d6e8b4d2e60d..778c2f7024ff 100644
--- a/trunk/arch/arm/kernel/kgdb.c
+++ b/trunk/arch/arm/kernel/kgdb.c
@@ -79,7 +79,7 @@ sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *task)
return;
/* Initialize to zero */
- for (regno = 0; regno < DBG_MAX_REG_NUM; regno++)
+ for (regno = 0; regno < GDB_MAX_REGS; regno++)
gdb_regs[regno] = 0;
/* Otherwise, we have only some registers from switch_to() */
diff --git a/trunk/arch/blackfin/kernel/kgdb.c b/trunk/arch/blackfin/kernel/kgdb.c
index 08bc44ea6883..edae461b1c54 100644
--- a/trunk/arch/blackfin/kernel/kgdb.c
+++ b/trunk/arch/blackfin/kernel/kgdb.c
@@ -320,7 +320,7 @@ static void bfin_correct_hw_break(void)
}
}
-void kgdb_disable_hw_debug(struct pt_regs *regs)
+static void bfin_disable_hw_debug(struct pt_regs *regs)
{
/* Disable hardware debugging while we are in kgdb */
bfin_write_WPIACTL(0);
@@ -406,6 +406,7 @@ struct kgdb_arch arch_kgdb_ops = {
#endif
.set_hw_breakpoint = bfin_set_hw_break,
.remove_hw_breakpoint = bfin_remove_hw_break,
+ .disable_hw_break = bfin_disable_hw_debug,
.remove_all_hw_break = bfin_remove_all_hw_break,
.correct_hw_break = bfin_correct_hw_break,
};
diff --git a/trunk/arch/ia64/kernel/perfmon.c b/trunk/arch/ia64/kernel/perfmon.c
index 6b1852f7f972..39e534f5a3b0 100644
--- a/trunk/arch/ia64/kernel/perfmon.c
+++ b/trunk/arch/ia64/kernel/perfmon.c
@@ -618,16 +618,15 @@ pfm_get_unmapped_area(struct file *file, unsigned long addr, unsigned long len,
}
-static int
-pfmfs_get_sb(struct file_system_type *fs_type, int flags, const char *dev_name, void *data,
- struct vfsmount *mnt)
+static struct dentry *
+pfmfs_mount(struct file_system_type *fs_type, int flags, const char *dev_name, void *data)
{
- return get_sb_pseudo(fs_type, "pfm:", NULL, PFMFS_MAGIC, mnt);
+ return mount_pseudo(fs_type, "pfm:", NULL, PFMFS_MAGIC);
}
static struct file_system_type pfm_fs_type = {
.name = "pfmfs",
- .get_sb = pfmfs_get_sb,
+ .mount = pfmfs_mount,
.kill_sb = kill_anon_super,
};
diff --git a/trunk/arch/mips/Kconfig b/trunk/arch/mips/Kconfig
index cf8d0945530c..67a2fa2caa49 100644
--- a/trunk/arch/mips/Kconfig
+++ b/trunk/arch/mips/Kconfig
@@ -4,16 +4,21 @@ config MIPS
select HAVE_GENERIC_DMA_COHERENT
select HAVE_IDE
select HAVE_OPROFILE
+ select HAVE_PERF_EVENTS
+ select PERF_USE_VMALLOC
select HAVE_ARCH_KGDB
select HAVE_FUNCTION_TRACER
select HAVE_FUNCTION_TRACE_MCOUNT_TEST
select HAVE_DYNAMIC_FTRACE
select HAVE_FTRACE_MCOUNT_RECORD
+ select HAVE_C_RECORDMCOUNT
select HAVE_FUNCTION_GRAPH_TRACER
select HAVE_KPROBES
select HAVE_KRETPROBES
select RTC_LIB if !MACH_LOONGSON
select GENERIC_ATOMIC64 if !64BIT
+ select HAVE_DMA_ATTRS
+ select HAVE_DMA_API_DEBUG
menu "Machine selection"
@@ -691,6 +696,9 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
select SWAP_IO_SPACE
select HW_HAS_PCI
select ARCH_SUPPORTS_MSI
+ select ZONE_DMA32
+ select USB_ARCH_HAS_OHCI
+ select USB_ARCH_HAS_EHCI
help
This option supports all of the Octeon reference boards from Cavium
Networks. It builds a kernel that dynamically determines the Octeon
@@ -1334,6 +1342,57 @@ config CPU_CAVIUM_OCTEON
can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
Full details can be found at http://www.caviumnetworks.com.
+config CPU_BMIPS3300
+ bool "BMIPS3300"
+ depends on SYS_HAS_CPU_BMIPS3300
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ select SWAP_IO_SPACE
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select WEAK_ORDERING
+ help
+ Broadcom BMIPS3300 processors.
+
+config CPU_BMIPS4350
+ bool "BMIPS4350"
+ depends on SYS_HAS_CPU_BMIPS4350
+ select CPU_SUPPORTS_32BIT_KERNEL
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ select SWAP_IO_SPACE
+ select SYS_SUPPORTS_SMP
+ select SYS_SUPPORTS_HOTPLUG_CPU
+ select WEAK_ORDERING
+ help
+ Broadcom BMIPS4350 ("VIPER") processors.
+
+config CPU_BMIPS4380
+ bool "BMIPS4380"
+ depends on SYS_HAS_CPU_BMIPS4380
+ select CPU_SUPPORTS_32BIT_KERNEL
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ select SWAP_IO_SPACE
+ select SYS_SUPPORTS_SMP
+ select SYS_SUPPORTS_HOTPLUG_CPU
+ select WEAK_ORDERING
+ help
+ Broadcom BMIPS4380 processors.
+
+config CPU_BMIPS5000
+ bool "BMIPS5000"
+ depends on SYS_HAS_CPU_BMIPS5000
+ select CPU_SUPPORTS_32BIT_KERNEL
+ select CPU_SUPPORTS_HIGHMEM
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ select SWAP_IO_SPACE
+ select SYS_SUPPORTS_SMP
+ select SYS_SUPPORTS_HOTPLUG_CPU
+ select WEAK_ORDERING
+ help
+ Broadcom BMIPS5000 processors.
+
endchoice
if CPU_LOONGSON2F
@@ -1452,6 +1511,18 @@ config SYS_HAS_CPU_SB1
config SYS_HAS_CPU_CAVIUM_OCTEON
bool
+config SYS_HAS_CPU_BMIPS3300
+ bool
+
+config SYS_HAS_CPU_BMIPS4350
+ bool
+
+config SYS_HAS_CPU_BMIPS4380
+ bool
+
+config SYS_HAS_CPU_BMIPS5000
+ bool
+
#
# CPU may reorder R->R, R->W, W->R, W->W
# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
@@ -1928,6 +1999,14 @@ config NODES_SHIFT
default "6"
depends on NEED_MULTIPLE_NODES
+config HW_PERF_EVENTS
+ bool "Enable hardware performance counter support for perf events"
+ depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && CPU_MIPS32
+ default y
+ help
+ Enable hardware performance counter support for perf events. If
+ disabled, perf events will use software events only.
+
source "mm/Kconfig"
config SMP
diff --git a/trunk/arch/mips/Kconfig.debug b/trunk/arch/mips/Kconfig.debug
index 43dc27997730..f437cd1fafb8 100644
--- a/trunk/arch/mips/Kconfig.debug
+++ b/trunk/arch/mips/Kconfig.debug
@@ -67,6 +67,15 @@ config CMDLINE_OVERRIDE
Normally, you will choose 'N' here.
+config DEBUG_STACKOVERFLOW
+ bool "Check for stack overflows"
+ depends on DEBUG_KERNEL
+ help
+ This option will cause messages to be printed if free stack space
+ drops below a certain limit(2GB on MIPS). The debugging option
+ provides another way to check stack overflow happened on kernel mode
+ stack usually caused by nested interruption.
+
config DEBUG_STACK_USAGE
bool "Enable stack utilization instrumentation"
depends on DEBUG_KERNEL
diff --git a/trunk/arch/mips/Makefile b/trunk/arch/mips/Makefile
index f4a4b663ebb3..7c1102e41fe2 100644
--- a/trunk/arch/mips/Makefile
+++ b/trunk/arch/mips/Makefile
@@ -48,9 +48,6 @@ ifneq ($(SUBARCH),$(ARCH))
endif
endif
-ifndef CONFIG_FUNCTION_TRACER
-cflags-y := -ffunction-sections
-endif
ifdef CONFIG_FUNCTION_GRAPH_TRACER
ifndef KBUILD_MCOUNT_RA_ADDRESS
ifeq ($(call cc-option-yn,-mmcount-ra-address), y)
@@ -159,6 +156,7 @@ cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap
ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))
cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
endif
+cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
diff --git a/trunk/arch/mips/ar7/gpio.c b/trunk/arch/mips/ar7/gpio.c
index c32fbb57441a..425dfa5d6e12 100644
--- a/trunk/arch/mips/ar7/gpio.c
+++ b/trunk/arch/mips/ar7/gpio.c
@@ -1,7 +1,7 @@
/*
* Copyright (C) 2007 Felix Fietkau
* Copyright (C) 2007 Eugene Konev
- * Copyright (C) 2009 Florian Fainelli
+ * Copyright (C) 2009-2010 Florian Fainelli
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -37,6 +37,16 @@ static int ar7_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
return readl(gpio_in) & (1 << gpio);
}
+static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
+{
+ struct ar7_gpio_chip *gpch =
+ container_of(chip, struct ar7_gpio_chip, chip);
+ void __iomem *gpio_in0 = gpch->regs + TITAN_GPIO_INPUT_0;
+ void __iomem *gpio_in1 = gpch->regs + TITAN_GPIO_INPUT_1;
+
+ return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
+}
+
static void ar7_gpio_set_value(struct gpio_chip *chip,
unsigned gpio, int value)
{
@@ -51,6 +61,21 @@ static void ar7_gpio_set_value(struct gpio_chip *chip,
writel(tmp, gpio_out);
}
+static void titan_gpio_set_value(struct gpio_chip *chip,
+ unsigned gpio, int value)
+{
+ struct ar7_gpio_chip *gpch =
+ container_of(chip, struct ar7_gpio_chip, chip);
+ void __iomem *gpio_out0 = gpch->regs + TITAN_GPIO_OUTPUT_0;
+ void __iomem *gpio_out1 = gpch->regs + TITAN_GPIO_OUTPUT_1;
+ unsigned tmp;
+
+ tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
+ if (value)
+ tmp |= 1 << (gpio & 0x1f);
+ writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
+}
+
static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
struct ar7_gpio_chip *gpch =
@@ -62,6 +87,21 @@ static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
return 0;
}
+static int titan_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+ struct ar7_gpio_chip *gpch =
+ container_of(chip, struct ar7_gpio_chip, chip);
+ void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
+ void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
+
+ if (gpio >= TITAN_GPIO_MAX)
+ return -EINVAL;
+
+ writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
+ gpio >> 5 ? gpio_dir1 : gpio_dir0);
+ return 0;
+}
+
static int ar7_gpio_direction_output(struct gpio_chip *chip,
unsigned gpio, int value)
{
@@ -75,6 +115,24 @@ static int ar7_gpio_direction_output(struct gpio_chip *chip,
return 0;
}
+static int titan_gpio_direction_output(struct gpio_chip *chip,
+ unsigned gpio, int value)
+{
+ struct ar7_gpio_chip *gpch =
+ container_of(chip, struct ar7_gpio_chip, chip);
+ void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
+ void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
+
+ if (gpio >= TITAN_GPIO_MAX)
+ return -EINVAL;
+
+ titan_gpio_set_value(chip, gpio, value);
+ writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
+ (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
+
+ return 0;
+}
+
static struct ar7_gpio_chip ar7_gpio_chip = {
.chip = {
.label = "ar7-gpio",
@@ -87,7 +145,19 @@ static struct ar7_gpio_chip ar7_gpio_chip = {
}
};
-int ar7_gpio_enable(unsigned gpio)
+static struct ar7_gpio_chip titan_gpio_chip = {
+ .chip = {
+ .label = "titan-gpio",
+ .direction_input = titan_gpio_direction_input,
+ .direction_output = titan_gpio_direction_output,
+ .set = titan_gpio_set_value,
+ .get = titan_gpio_get_value,
+ .base = 0,
+ .ngpio = TITAN_GPIO_MAX,
+ }
+};
+
+static inline int ar7_gpio_enable_ar7(unsigned gpio)
{
void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
@@ -95,9 +165,26 @@ int ar7_gpio_enable(unsigned gpio)
return 0;
}
+
+static inline int ar7_gpio_enable_titan(unsigned gpio)
+{
+ void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
+ void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
+
+ writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
+ gpio >> 5 ? gpio_en1 : gpio_en0);
+
+ return 0;
+}
+
+int ar7_gpio_enable(unsigned gpio)
+{
+ return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
+ ar7_gpio_enable_ar7(gpio);
+}
EXPORT_SYMBOL(ar7_gpio_enable);
-int ar7_gpio_disable(unsigned gpio)
+static inline int ar7_gpio_disable_ar7(unsigned gpio)
{
void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
@@ -105,27 +192,159 @@ int ar7_gpio_disable(unsigned gpio)
return 0;
}
+
+static inline int ar7_gpio_disable_titan(unsigned gpio)
+{
+ void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
+ void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
+
+ writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
+ gpio >> 5 ? gpio_en1 : gpio_en0);
+
+ return 0;
+}
+
+int ar7_gpio_disable(unsigned gpio)
+{
+ return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
+ ar7_gpio_disable_ar7(gpio);
+}
EXPORT_SYMBOL(ar7_gpio_disable);
-static int __init ar7_gpio_init(void)
+struct titan_gpio_cfg {
+ u32 reg;
+ u32 shift;
+ u32 func;
+};
+
+static struct titan_gpio_cfg titan_gpio_table[] = {
+ /* reg, start bit, mux value */
+ {4, 24, 1},
+ {4, 26, 1},
+ {4, 28, 1},
+ {4, 30, 1},
+ {5, 6, 1},
+ {5, 8, 1},
+ {5, 10, 1},
+ {5, 12, 1},
+ {7, 14, 3},
+ {7, 16, 3},
+ {7, 18, 3},
+ {7, 20, 3},
+ {7, 22, 3},
+ {7, 26, 3},
+ {7, 28, 3},
+ {7, 30, 3},
+ {8, 0, 3},
+ {8, 2, 3},
+ {8, 4, 3},
+ {8, 10, 3},
+ {8, 14, 3},
+ {8, 16, 3},
+ {8, 18, 3},
+ {8, 20, 3},
+ {9, 8, 3},
+ {9, 10, 3},
+ {9, 12, 3},
+ {9, 14, 3},
+ {9, 18, 3},
+ {9, 20, 3},
+ {9, 24, 3},
+ {9, 26, 3},
+ {9, 28, 3},
+ {9, 30, 3},
+ {10, 0, 3},
+ {10, 2, 3},
+ {10, 8, 3},
+ {10, 10, 3},
+ {10, 12, 3},
+ {10, 14, 3},
+ {13, 12, 3},
+ {13, 14, 3},
+ {13, 16, 3},
+ {13, 18, 3},
+ {13, 24, 3},
+ {13, 26, 3},
+ {13, 28, 3},
+ {13, 30, 3},
+ {14, 2, 3},
+ {14, 6, 3},
+ {14, 8, 3},
+ {14, 12, 3}
+};
+
+static int titan_gpio_pinsel(unsigned gpio)
+{
+ struct titan_gpio_cfg gpio_cfg;
+ u32 mux_status, pin_sel_reg, tmp;
+ void __iomem *pin_sel = (void __iomem *)KSEG1ADDR(AR7_REGS_PINSEL);
+
+ if (gpio >= ARRAY_SIZE(titan_gpio_table))
+ return -EINVAL;
+
+ gpio_cfg = titan_gpio_table[gpio];
+ pin_sel_reg = gpio_cfg.reg - 1;
+
+ mux_status = (readl(pin_sel + pin_sel_reg) >> gpio_cfg.shift) & 0x3;
+
+ /* Check the mux status */
+ if (!((mux_status == 0) || (mux_status == gpio_cfg.func)))
+ return 0;
+
+ /* Set the pin sel value */
+ tmp = readl(pin_sel + pin_sel_reg);
+ tmp |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
+ writel(tmp, pin_sel + pin_sel_reg);
+
+ return 0;
+}
+
+/* Perform minimal Titan GPIO configuration */
+static void titan_gpio_init(void)
+{
+ unsigned i;
+
+ for (i = 44; i < 48; i++) {
+ titan_gpio_pinsel(i);
+ ar7_gpio_enable_titan(i);
+ titan_gpio_direction_input(&titan_gpio_chip.chip, i);
+ }
+}
+
+int __init ar7_gpio_init(void)
{
int ret;
+ struct ar7_gpio_chip *gpch;
+ unsigned size;
+
+ if (!ar7_is_titan()) {
+ gpch = &ar7_gpio_chip;
+ size = 0x10;
+ } else {
+ gpch = &titan_gpio_chip;
+ size = 0x1f;
+ }
- ar7_gpio_chip.regs = ioremap_nocache(AR7_REGS_GPIO,
+ gpch->regs = ioremap_nocache(AR7_REGS_GPIO,
AR7_REGS_GPIO + 0x10);
- if (!ar7_gpio_chip.regs) {
- printk(KERN_ERR "ar7-gpio: failed to ioremap regs\n");
+ if (!gpch->regs) {
+ printk(KERN_ERR "%s: failed to ioremap regs\n",
+ gpch->chip.label);
return -ENOMEM;
}
- ret = gpiochip_add(&ar7_gpio_chip.chip);
+ ret = gpiochip_add(&gpch->chip);
if (ret) {
- printk(KERN_ERR "ar7-gpio: failed to add gpiochip\n");
+ printk(KERN_ERR "%s: failed to add gpiochip\n",
+ gpch->chip.label);
return ret;
}
- printk(KERN_INFO "ar7-gpio: registered %d GPIOs\n",
- ar7_gpio_chip.chip.ngpio);
+ printk(KERN_INFO "%s: registered %d GPIOs\n",
+ gpch->chip.label, gpch->chip.ngpio);
+
+ if (ar7_is_titan())
+ titan_gpio_init();
+
return ret;
}
-arch_initcall(ar7_gpio_init);
diff --git a/trunk/arch/mips/ar7/platform.c b/trunk/arch/mips/ar7/platform.c
index 0da5b2b8dd88..7d2fab392327 100644
--- a/trunk/arch/mips/ar7/platform.c
+++ b/trunk/arch/mips/ar7/platform.c
@@ -357,6 +357,11 @@ static struct gpio_led default_leds[] = {
},
};
+static struct gpio_led titan_leds[] = {
+ { .name = "status", .gpio = 8, .active_low = 1, },
+ { .name = "wifi", .gpio = 13, .active_low = 1, },
+};
+
static struct gpio_led dsl502t_leds[] = {
{
.name = "status",
@@ -495,6 +500,9 @@ static void __init detect_leds(void)
} else if (strstr(prid, "DG834")) {
ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds);
ar7_led_data.leds = dg834g_leds;
+ } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) {
+ ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);
+ ar7_led_data.leds = titan_leds;
}
}
@@ -560,6 +568,51 @@ static int __init ar7_register_uarts(void)
return 0;
}
+static void __init titan_fixup_devices(void)
+{
+ /* Set vlynq0 data */
+ vlynq_low_data.reset_bit = 15;
+ vlynq_low_data.gpio_bit = 14;
+
+ /* Set vlynq1 data */
+ vlynq_high_data.reset_bit = 16;
+ vlynq_high_data.gpio_bit = 7;
+
+ /* Set vlynq0 resources */
+ vlynq_low_res[0].start = TITAN_REGS_VLYNQ0;
+ vlynq_low_res[0].end = TITAN_REGS_VLYNQ0 + 0xff;
+ vlynq_low_res[1].start = 33;
+ vlynq_low_res[1].end = 33;
+ vlynq_low_res[2].start = 0x0c000000;
+ vlynq_low_res[2].end = 0x0fffffff;
+ vlynq_low_res[3].start = 80;
+ vlynq_low_res[3].end = 111;
+
+ /* Set vlynq1 resources */
+ vlynq_high_res[0].start = TITAN_REGS_VLYNQ1;
+ vlynq_high_res[0].end = TITAN_REGS_VLYNQ1 + 0xff;
+ vlynq_high_res[1].start = 34;
+ vlynq_high_res[1].end = 34;
+ vlynq_high_res[2].start = 0x40000000;
+ vlynq_high_res[2].end = 0x43ffffff;
+ vlynq_high_res[3].start = 112;
+ vlynq_high_res[3].end = 143;
+
+ /* Set cpmac0 data */
+ cpmac_low_data.phy_mask = 0x40000000;
+
+ /* Set cpmac1 data */
+ cpmac_high_data.phy_mask = 0x80000000;
+
+ /* Set cpmac0 resources */
+ cpmac_low_res[0].start = TITAN_REGS_MAC0;
+ cpmac_low_res[0].end = TITAN_REGS_MAC0 + 0x7ff;
+
+ /* Set cpmac1 resources */
+ cpmac_high_res[0].start = TITAN_REGS_MAC1;
+ cpmac_high_res[0].end = TITAN_REGS_MAC1 + 0x7ff;
+}
+
static int __init ar7_register_devices(void)
{
void __iomem *bootcr;
@@ -574,6 +627,9 @@ static int __init ar7_register_devices(void)
if (res)
pr_warning("unable to register physmap-flash: %d\n", res);
+ if (ar7_is_titan())
+ titan_fixup_devices();
+
ar7_device_disable(vlynq_low_data.reset_bit);
res = platform_device_register(&vlynq_low);
if (res)
diff --git a/trunk/arch/mips/ar7/prom.c b/trunk/arch/mips/ar7/prom.c
index 52385790e5c1..23818d299127 100644
--- a/trunk/arch/mips/ar7/prom.c
+++ b/trunk/arch/mips/ar7/prom.c
@@ -246,6 +246,8 @@ void __init prom_init(void)
ar7_init_cmdline(fw_arg0, (char **)fw_arg1);
ar7_init_env((struct env_var *)fw_arg2);
console_config();
+
+ ar7_gpio_init();
}
#define PORT(offset) (KSEG1ADDR(AR7_REGS_UART0 + (offset * 4)))
diff --git a/trunk/arch/mips/ar7/setup.c b/trunk/arch/mips/ar7/setup.c
index 3a801d2cb6e5..f20b53e597c4 100644
--- a/trunk/arch/mips/ar7/setup.c
+++ b/trunk/arch/mips/ar7/setup.c
@@ -23,6 +23,7 @@
#include
#include
#include
+#include
static void ar7_machine_restart(char *command)
{
@@ -49,6 +50,8 @@ static void ar7_machine_power_off(void)
const char *get_system_type(void)
{
u16 chip_id = ar7_chip_id();
+ u16 titan_variant_id = titan_chip_id();
+
switch (chip_id) {
case AR7_CHIP_7100:
return "TI AR7 (TNETD7100)";
@@ -56,6 +59,17 @@ const char *get_system_type(void)
return "TI AR7 (TNETD7200)";
case AR7_CHIP_7300:
return "TI AR7 (TNETD7300)";
+ case AR7_CHIP_TITAN:
+ switch (titan_variant_id) {
+ case TITAN_CHIP_1050:
+ return "TI AR7 (TNETV1050)";
+ case TITAN_CHIP_1055:
+ return "TI AR7 (TNETV1055)";
+ case TITAN_CHIP_1056:
+ return "TI AR7 (TNETV1056)";
+ case TITAN_CHIP_1060:
+ return "TI AR7 (TNETV1060)";
+ }
default:
return "TI AR7 (unknown)";
}
diff --git a/trunk/arch/mips/bcm63xx/cpu.c b/trunk/arch/mips/bcm63xx/cpu.c
index cbb7caf86d77..7c7e4d4486ce 100644
--- a/trunk/arch/mips/bcm63xx/cpu.c
+++ b/trunk/arch/mips/bcm63xx/cpu.c
@@ -10,7 +10,9 @@
#include
#include
#include
+#include
#include
+#include
#include
#include
#include
@@ -296,26 +298,24 @@ void __init bcm63xx_cpu_init(void)
expected_cpu_id = 0;
switch (c->cputype) {
- /*
- * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c
- */
- case CPU_BCM3302:
- __cpu_name[cpu] = "Broadcom BCM6338";
- expected_cpu_id = BCM6338_CPU_ID;
- bcm63xx_regs_base = bcm96338_regs_base;
- bcm63xx_irqs = bcm96338_irqs;
+ case CPU_BMIPS3300:
+ if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
+ expected_cpu_id = BCM6348_CPU_ID;
+ bcm63xx_regs_base = bcm96348_regs_base;
+ bcm63xx_irqs = bcm96348_irqs;
+ } else {
+ __cpu_name[cpu] = "Broadcom BCM6338";
+ expected_cpu_id = BCM6338_CPU_ID;
+ bcm63xx_regs_base = bcm96338_regs_base;
+ bcm63xx_irqs = bcm96338_irqs;
+ }
break;
- case CPU_BCM6345:
+ case CPU_BMIPS32:
expected_cpu_id = BCM6345_CPU_ID;
bcm63xx_regs_base = bcm96345_regs_base;
bcm63xx_irqs = bcm96345_irqs;
break;
- case CPU_BCM6348:
- expected_cpu_id = BCM6348_CPU_ID;
- bcm63xx_regs_base = bcm96348_regs_base;
- bcm63xx_irqs = bcm96348_irqs;
- break;
- case CPU_BCM6358:
+ case CPU_BMIPS4350:
expected_cpu_id = BCM6358_CPU_ID;
bcm63xx_regs_base = bcm96358_regs_base;
bcm63xx_irqs = bcm96358_irqs;
diff --git a/trunk/arch/mips/cavium-octeon/Kconfig b/trunk/arch/mips/cavium-octeon/Kconfig
index 47323ca452dc..caae22858163 100644
--- a/trunk/arch/mips/cavium-octeon/Kconfig
+++ b/trunk/arch/mips/cavium-octeon/Kconfig
@@ -3,6 +3,17 @@ config CAVIUM_OCTEON_SPECIFIC_OPTIONS
depends on CPU_CAVIUM_OCTEON
default "y"
+config CAVIUM_CN63XXP1
+ bool "Enable CN63XXP1 errata worarounds"
+ depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
+ default "n"
+ help
+ The CN63XXP1 chip requires build time workarounds to
+ function reliably, select this option to enable them. These
+ workarounds will cause a slight decrease in performance on
+ non-CN63XXP1 hardware, so it is recommended to select "n"
+ unless it is known the workarounds are needed.
+
config CAVIUM_OCTEON_2ND_KERNEL
bool "Build the kernel to be used as a 2nd kernel on the same chip"
depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
@@ -87,3 +98,15 @@ config ARCH_SPARSEMEM_ENABLE
config CAVIUM_OCTEON_HELPER
def_bool y
depends on OCTEON_ETHERNET || PCI
+
+config IOMMU_HELPER
+ bool
+
+config NEED_SG_DMA_LENGTH
+ bool
+
+config SWIOTLB
+ def_bool y
+ depends on CPU_CAVIUM_OCTEON
+ select IOMMU_HELPER
+ select NEED_SG_DMA_LENGTH
diff --git a/trunk/arch/mips/cavium-octeon/csrc-octeon.c b/trunk/arch/mips/cavium-octeon/csrc-octeon.c
index b6847c8e0ddd..26bf71130bf8 100644
--- a/trunk/arch/mips/cavium-octeon/csrc-octeon.c
+++ b/trunk/arch/mips/cavium-octeon/csrc-octeon.c
@@ -4,14 +4,18 @@
* for more details.
*
* Copyright (C) 2007 by Ralf Baechle
+ * Copyright (C) 2009, 2010 Cavium Networks, Inc.
*/
#include
#include
+#include
+#include
#include
#include
#include
+#include
/*
* Set the current core's cvmcount counter to the value of the
@@ -19,11 +23,23 @@
* on-line. This allows for a read from a local cpu register to
* access a synchronized counter.
*
+ * On CPU_CAVIUM_OCTEON2 the IPD_CLK_COUNT is scaled by rdiv/sdiv.
*/
void octeon_init_cvmcount(void)
{
unsigned long flags;
unsigned loops = 2;
+ u64 f = 0;
+ u64 rdiv = 0;
+ u64 sdiv = 0;
+ if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
+ union cvmx_mio_rst_boot rst_boot;
+ rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
+ rdiv = rst_boot.s.c_mul; /* CPU clock */
+ sdiv = rst_boot.s.pnr_mul; /* I/O clock */
+ f = (0x8000000000000000ull / sdiv) * 2;
+ }
+
/* Clobber loops so GCC will not unroll the following while loop. */
asm("" : "+r" (loops));
@@ -33,8 +49,20 @@ void octeon_init_cvmcount(void)
* Loop several times so we are executing from the cache,
* which should give more deterministic timing.
*/
- while (loops--)
- write_c0_cvmcount(cvmx_read_csr(CVMX_IPD_CLK_COUNT));
+ while (loops--) {
+ u64 ipd_clk_count = cvmx_read_csr(CVMX_IPD_CLK_COUNT);
+ if (rdiv != 0) {
+ ipd_clk_count *= rdiv;
+ if (f != 0) {
+ asm("dmultu\t%[cnt],%[f]\n\t"
+ "mfhi\t%[cnt]"
+ : [cnt] "+r" (ipd_clk_count),
+ [f] "=r" (f)
+ : : "hi", "lo");
+ }
+ }
+ write_c0_cvmcount(ipd_clk_count);
+ }
local_irq_restore(flags);
}
@@ -77,7 +105,7 @@ unsigned long long notrace sched_clock(void)
void __init plat_time_init(void)
{
clocksource_mips.rating = 300;
- clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
+ clocksource_set_clock(&clocksource_mips, octeon_get_clock_rate());
clocksource_register(&clocksource_mips);
}
diff --git a/trunk/arch/mips/cavium-octeon/dma-octeon.c b/trunk/arch/mips/cavium-octeon/dma-octeon.c
index d22b5a2d64f4..1abb66caaa1d 100644
--- a/trunk/arch/mips/cavium-octeon/dma-octeon.c
+++ b/trunk/arch/mips/cavium-octeon/dma-octeon.c
@@ -8,335 +8,342 @@
* Copyright (C) 2005 Ilya A. Volynets-Evenbakh
* swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
* IP32 changes by Ilya.
- * Cavium Networks: Create new dma setup for Cavium Networks Octeon based on
- * the kernels original.
+ * Copyright (C) 2010 Cavium Networks, Inc.
*/
-#include
-#include
-#include
-#include
#include
-#include
#include
+#include
+#include
+#include
+#include
+#include
-#include
-#include
+#include
#include
+
+#ifdef CONFIG_PCI
+#include
#include
#include
-#include
+static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr)
+{
+ if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE))
+ return paddr - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
+ else
+ return paddr;
+}
-#ifdef CONFIG_PCI
-#include
-#endif
+static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr)
+{
+ if (daddr >= CVMX_PCIE_BAR1_RC_BASE)
+ return daddr + CVMX_PCIE_BAR1_PHYS_BASE - CVMX_PCIE_BAR1_RC_BASE;
+ else
+ return daddr;
+}
+
+static dma_addr_t octeon_gen1_phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+ if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
+ paddr -= 0x400000000ull;
+ return octeon_hole_phys_to_dma(paddr);
+}
-#define BAR2_PCI_ADDRESS 0x8000000000ul
+static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+ daddr = octeon_hole_dma_to_phys(daddr);
-struct bar1_index_state {
- int16_t ref_count; /* Number of PCI mappings using this index */
- uint16_t address_bits; /* Upper bits of physical address. This is
- shifted 22 bits */
-};
+ if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
+ daddr += 0x400000000ull;
-#ifdef CONFIG_PCI
-static DEFINE_RAW_SPINLOCK(bar1_lock);
-static struct bar1_index_state bar1_state[32];
-#endif
+ return daddr;
+}
-dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
+static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
{
-#ifndef CONFIG_PCI
- /* Without PCI/PCIe this function can be called for Octeon internal
- devices such as USB. These devices all support 64bit addressing */
+ if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
+ paddr -= 0x400000000ull;
+
+ /* Anything in the BAR1 hole or above goes via BAR2 */
+ if (paddr >= 0xf0000000ull)
+ paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
+
+ return paddr;
+}
+
+static phys_addr_t octeon_big_dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+ if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
+ daddr -= OCTEON_BAR2_PCI_ADDRESS;
+
+ if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
+ daddr += 0x400000000ull;
+ return daddr;
+}
+
+static dma_addr_t octeon_small_phys_to_dma(struct device *dev,
+ phys_addr_t paddr)
+{
+ if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
+ paddr -= 0x400000000ull;
+
+ /* Anything not in the BAR1 range goes via BAR2 */
+ if (paddr >= octeon_bar1_pci_phys && paddr < octeon_bar1_pci_phys + 0x8000000ull)
+ paddr = paddr - octeon_bar1_pci_phys;
+ else
+ paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
+
+ return paddr;
+}
+
+static phys_addr_t octeon_small_dma_to_phys(struct device *dev,
+ dma_addr_t daddr)
+{
+ if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
+ daddr -= OCTEON_BAR2_PCI_ADDRESS;
+ else
+ daddr += octeon_bar1_pci_phys;
+
+ if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
+ daddr += 0x400000000ull;
+ return daddr;
+}
+
+#endif /* CONFIG_PCI */
+
+static dma_addr_t octeon_dma_map_page(struct device *dev, struct page *page,
+ unsigned long offset, size_t size, enum dma_data_direction direction,
+ struct dma_attrs *attrs)
+{
+ dma_addr_t daddr = swiotlb_map_page(dev, page, offset, size,
+ direction, attrs);
mb();
- return virt_to_phys(ptr);
-#else
- unsigned long flags;
- uint64_t dma_mask;
- int64_t start_index;
- dma_addr_t result = -1;
- uint64_t physical = virt_to_phys(ptr);
- int64_t index;
+ return daddr;
+}
+
+static int octeon_dma_map_sg(struct device *dev, struct scatterlist *sg,
+ int nents, enum dma_data_direction direction, struct dma_attrs *attrs)
+{
+ int r = swiotlb_map_sg_attrs(dev, sg, nents, direction, attrs);
mb();
- /*
- * Use the DMA masks to determine the allowed memory
- * region. For us it doesn't limit the actual memory, just the
- * address visible over PCI. Devices with limits need to use
- * lower indexed Bar1 entries.
- */
- if (dev) {
- dma_mask = dev->coherent_dma_mask;
- if (dev->dma_mask)
- dma_mask = *dev->dma_mask;
- } else {
- dma_mask = 0xfffffffful;
- }
+ return r;
+}
- /*
- * Platform devices, such as the internal USB, skip all
- * translation and use Octeon physical addresses directly.
- */
- if (!dev || dev->bus == &platform_bus_type)
- return physical;
+static void octeon_dma_sync_single_for_device(struct device *dev,
+ dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
+{
+ swiotlb_sync_single_for_device(dev, dma_handle, size, direction);
+ mb();
+}
- switch (octeon_dma_bar_type) {
- case OCTEON_DMA_BAR_TYPE_PCIE:
- if (unlikely(physical < (16ul << 10)))
- panic("dma_map_single: Not allowed to map first 16KB."
- " It interferes with BAR0 special area\n");
- else if ((physical + size >= (256ul << 20)) &&
- (physical < (512ul << 20)))
- panic("dma_map_single: Not allowed to map bootbus\n");
- else if ((physical + size >= 0x400000000ull) &&
- physical < 0x410000000ull)
- panic("dma_map_single: "
- "Attempt to map illegal memory address 0x%llx\n",
- physical);
- else if (physical >= 0x420000000ull)
- panic("dma_map_single: "
- "Attempt to map illegal memory address 0x%llx\n",
- physical);
- else if (physical >= CVMX_PCIE_BAR1_PHYS_BASE &&
- physical + size < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE)) {
- result = physical - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
-
- if (((result+size-1) & dma_mask) != result+size-1)
- panic("dma_map_single: Attempt to map address 0x%llx-0x%llx, which can't be accessed according to the dma mask 0x%llx\n",
- physical, physical+size-1, dma_mask);
- goto done;
- }
-
- /* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */
- if ((physical >= 0x410000000ull) && physical < 0x420000000ull)
- result = physical - 0x400000000ull;
- else
- result = physical;
- if (((result+size-1) & dma_mask) != result+size-1)
- panic("dma_map_single: Attempt to map address "
- "0x%llx-0x%llx, which can't be accessed "
- "according to the dma mask 0x%llx\n",
- physical, physical+size-1, dma_mask);
- goto done;
+static void octeon_dma_sync_sg_for_device(struct device *dev,
+ struct scatterlist *sg, int nelems, enum dma_data_direction direction)
+{
+ swiotlb_sync_sg_for_device(dev, sg, nelems, direction);
+ mb();
+}
- case OCTEON_DMA_BAR_TYPE_BIG:
-#ifdef CONFIG_64BIT
- /* If the device supports 64bit addressing, then use BAR2 */
- if (dma_mask > BAR2_PCI_ADDRESS) {
- result = physical + BAR2_PCI_ADDRESS;
- goto done;
- }
-#endif
- if (unlikely(physical < (4ul << 10))) {
- panic("dma_map_single: Not allowed to map first 4KB. "
- "It interferes with BAR0 special area\n");
- } else if (physical < (256ul << 20)) {
- if (unlikely(physical + size > (256ul << 20)))
- panic("dma_map_single: Requested memory spans "
- "Bar0 0:256MB and bootbus\n");
- result = physical;
- goto done;
- } else if (unlikely(physical < (512ul << 20))) {
- panic("dma_map_single: Not allowed to map bootbus\n");
- } else if (physical < (2ul << 30)) {
- if (unlikely(physical + size > (2ul << 30)))
- panic("dma_map_single: Requested memory spans "
- "Bar0 512MB:2GB and BAR1\n");
- result = physical;
- goto done;
- } else if (physical < (2ul << 30) + (128 << 20)) {
- /* Fall through */
- } else if (physical <
- (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)) {
- if (unlikely
- (physical + size >
- (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)))
- panic("dma_map_single: Requested memory "
- "extends past Bar1 (4GB-%luMB)\n",
- OCTEON_PCI_BAR1_HOLE_SIZE);
- result = physical;
- goto done;
- } else if ((physical >= 0x410000000ull) &&
- (physical < 0x420000000ull)) {
- if (unlikely(physical + size > 0x420000000ull))
- panic("dma_map_single: Requested memory spans "
- "non existant memory\n");
- /* BAR0 fixed mapping 256MB:512MB ->
- * 16GB+256MB:16GB+512MB */
- result = physical - 0x400000000ull;
- goto done;
- } else {
- /* Continued below switch statement */
- }
- break;
+static void *octeon_dma_alloc_coherent(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t gfp)
+{
+ void *ret;
- case OCTEON_DMA_BAR_TYPE_SMALL:
-#ifdef CONFIG_64BIT
- /* If the device supports 64bit addressing, then use BAR2 */
- if (dma_mask > BAR2_PCI_ADDRESS) {
- result = physical + BAR2_PCI_ADDRESS;
- goto done;
- }
+ if (dma_alloc_from_coherent(dev, size, dma_handle, &ret))
+ return ret;
+
+ /* ignore region specifiers */
+ gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
+
+#ifdef CONFIG_ZONE_DMA
+ if (dev == NULL)
+ gfp |= __GFP_DMA;
+ else if (dev->coherent_dma_mask <= DMA_BIT_MASK(24))
+ gfp |= __GFP_DMA;
+ else
#endif
- /* Continued below switch statement */
- break;
+#ifdef CONFIG_ZONE_DMA32
+ if (dev->coherent_dma_mask <= DMA_BIT_MASK(32))
+ gfp |= __GFP_DMA32;
+ else
+#endif
+ ;
- default:
- panic("dma_map_single: Invalid octeon_dma_bar_type\n");
- }
+ /* Don't invoke OOM killer */
+ gfp |= __GFP_NORETRY;
- /* Don't allow mapping to span multiple Bar entries. The hardware guys
- won't guarantee that DMA across boards work */
- if (unlikely((physical >> 22) != ((physical + size - 1) >> 22)))
- panic("dma_map_single: "
- "Requested memory spans more than one Bar1 entry\n");
+ ret = swiotlb_alloc_coherent(dev, size, dma_handle, gfp);
- if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
- start_index = 31;
- else if (unlikely(dma_mask < (1ul << 27)))
- start_index = (dma_mask >> 22);
- else
- start_index = 31;
-
- /* Only one processor can access the Bar register at once */
- raw_spin_lock_irqsave(&bar1_lock, flags);
-
- /* Look through Bar1 for existing mapping that will work */
- for (index = start_index; index >= 0; index--) {
- if ((bar1_state[index].address_bits == physical >> 22) &&
- (bar1_state[index].ref_count)) {
- /* An existing mapping will work, use it */
- bar1_state[index].ref_count++;
- if (unlikely(bar1_state[index].ref_count < 0))
- panic("dma_map_single: "
- "Bar1[%d] reference count overflowed\n",
- (int) index);
- result = (index << 22) | (physical & ((1 << 22) - 1));
- /* Large BAR1 is offset at 2GB */
- if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
- result += 2ul << 30;
- goto done_unlock;
- }
- }
+ mb();
- /* No existing mappings, look for a free entry */
- for (index = start_index; index >= 0; index--) {
- if (unlikely(bar1_state[index].ref_count == 0)) {
- union cvmx_pci_bar1_indexx bar1_index;
- /* We have a free entry, use it */
- bar1_state[index].ref_count = 1;
- bar1_state[index].address_bits = physical >> 22;
- bar1_index.u32 = 0;
- /* Address bits[35:22] sent to L2C */
- bar1_index.s.addr_idx = physical >> 22;
- /* Don't put PCI accesses in L2. */
- bar1_index.s.ca = 1;
- /* Endian Swap Mode */
- bar1_index.s.end_swp = 1;
- /* Set '1' when the selected address range is valid. */
- bar1_index.s.addr_v = 1;
- octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
- bar1_index.u32);
- /* An existing mapping will work, use it */
- result = (index << 22) | (physical & ((1 << 22) - 1));
- /* Large BAR1 is offset at 2GB */
- if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
- result += 2ul << 30;
- goto done_unlock;
- }
- }
+ return ret;
+}
- pr_err("dma_map_single: "
- "Can't find empty BAR1 index for physical mapping 0x%llx\n",
- (unsigned long long) physical);
+static void octeon_dma_free_coherent(struct device *dev, size_t size,
+ void *vaddr, dma_addr_t dma_handle)
+{
+ int order = get_order(size);
-done_unlock:
- raw_spin_unlock_irqrestore(&bar1_lock, flags);
-done:
- pr_debug("dma_map_single 0x%llx->0x%llx\n", physical, result);
- return result;
-#endif
+ if (dma_release_from_coherent(dev, order, vaddr))
+ return;
+
+ swiotlb_free_coherent(dev, size, vaddr, dma_handle);
}
-void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+static dma_addr_t octeon_unity_phys_to_dma(struct device *dev, phys_addr_t paddr)
{
-#ifndef CONFIG_PCI
- /*
- * Without PCI/PCIe this function can be called for Octeon internal
- * devices such as USB. These devices all support 64bit addressing.
- */
- return;
-#else
- unsigned long flags;
- uint64_t index;
+ return paddr;
+}
+static phys_addr_t octeon_unity_dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+ return daddr;
+}
+
+struct octeon_dma_map_ops {
+ struct dma_map_ops dma_map_ops;
+ dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr);
+ phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
+};
+
+dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+ struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
+ struct octeon_dma_map_ops,
+ dma_map_ops);
+
+ return ops->phys_to_dma(dev, paddr);
+}
+EXPORT_SYMBOL(phys_to_dma);
+
+phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+ struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
+ struct octeon_dma_map_ops,
+ dma_map_ops);
+
+ return ops->dma_to_phys(dev, daddr);
+}
+EXPORT_SYMBOL(dma_to_phys);
+
+static struct octeon_dma_map_ops octeon_linear_dma_map_ops = {
+ .dma_map_ops = {
+ .alloc_coherent = octeon_dma_alloc_coherent,
+ .free_coherent = octeon_dma_free_coherent,
+ .map_page = octeon_dma_map_page,
+ .unmap_page = swiotlb_unmap_page,
+ .map_sg = octeon_dma_map_sg,
+ .unmap_sg = swiotlb_unmap_sg_attrs,
+ .sync_single_for_cpu = swiotlb_sync_single_for_cpu,
+ .sync_single_for_device = octeon_dma_sync_single_for_device,
+ .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
+ .sync_sg_for_device = octeon_dma_sync_sg_for_device,
+ .mapping_error = swiotlb_dma_mapping_error,
+ .dma_supported = swiotlb_dma_supported
+ },
+ .phys_to_dma = octeon_unity_phys_to_dma,
+ .dma_to_phys = octeon_unity_dma_to_phys
+};
+
+char *octeon_swiotlb;
+
+void __init plat_swiotlb_setup(void)
+{
+ int i;
+ phys_t max_addr;
+ phys_t addr_size;
+ size_t swiotlbsize;
+ unsigned long swiotlb_nslabs;
+
+ max_addr = 0;
+ addr_size = 0;
+
+ for (i = 0 ; i < boot_mem_map.nr_map; i++) {
+ struct boot_mem_map_entry *e = &boot_mem_map.map[i];
+ if (e->type != BOOT_MEM_RAM)
+ continue;
+
+ /* These addresses map low for PCI. */
+ if (e->addr > 0x410000000ull)
+ continue;
+
+ addr_size += e->size;
+
+ if (max_addr < e->addr + e->size)
+ max_addr = e->addr + e->size;
+
+ }
+
+ swiotlbsize = PAGE_SIZE;
+
+#ifdef CONFIG_PCI
/*
- * Platform devices, such as the internal USB, skip all
- * translation and use Octeon physical addresses directly.
+ * For OCTEON_DMA_BAR_TYPE_SMALL, size the iotlb at 1/4 memory
+ * size to a maximum of 64MB
*/
- if (dev->bus == &platform_bus_type)
- return;
+ if (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ || OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
+ swiotlbsize = addr_size / 4;
+ if (swiotlbsize > 64 * (1<<20))
+ swiotlbsize = 64 * (1<<20);
+ } else if (max_addr > 0xf0000000ul) {
+ /*
+ * Otherwise only allocate a big iotlb if there is
+ * memory past the BAR1 hole.
+ */
+ swiotlbsize = 64 * (1<<20);
+ }
+#endif
+ swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
+ swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
+ swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT;
+
+ octeon_swiotlb = alloc_bootmem_low_pages(swiotlbsize);
+ swiotlb_init_with_tbl(octeon_swiotlb, swiotlb_nslabs, 1);
+
+ mips_dma_map_ops = &octeon_linear_dma_map_ops.dma_map_ops;
+}
+
+#ifdef CONFIG_PCI
+static struct octeon_dma_map_ops _octeon_pci_dma_map_ops = {
+ .dma_map_ops = {
+ .alloc_coherent = octeon_dma_alloc_coherent,
+ .free_coherent = octeon_dma_free_coherent,
+ .map_page = octeon_dma_map_page,
+ .unmap_page = swiotlb_unmap_page,
+ .map_sg = octeon_dma_map_sg,
+ .unmap_sg = swiotlb_unmap_sg_attrs,
+ .sync_single_for_cpu = swiotlb_sync_single_for_cpu,
+ .sync_single_for_device = octeon_dma_sync_single_for_device,
+ .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
+ .sync_sg_for_device = octeon_dma_sync_sg_for_device,
+ .mapping_error = swiotlb_dma_mapping_error,
+ .dma_supported = swiotlb_dma_supported
+ },
+};
+
+struct dma_map_ops *octeon_pci_dma_map_ops;
+
+void __init octeon_pci_dma_init(void)
+{
switch (octeon_dma_bar_type) {
case OCTEON_DMA_BAR_TYPE_PCIE:
- /* Nothing to do, all mappings are static */
- goto done;
-
+ _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma;
+ _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys;
+ break;
case OCTEON_DMA_BAR_TYPE_BIG:
-#ifdef CONFIG_64BIT
- /* Nothing to do for addresses using BAR2 */
- if (dma_addr >= BAR2_PCI_ADDRESS)
- goto done;
-#endif
- if (unlikely(dma_addr < (4ul << 10)))
- panic("dma_unmap_single: Unexpect DMA address 0x%llx\n",
- dma_addr);
- else if (dma_addr < (2ul << 30))
- /* Nothing to do for addresses using BAR0 */
- goto done;
- else if (dma_addr < (2ul << 30) + (128ul << 20))
- /* Need to unmap, fall through */
- index = (dma_addr - (2ul << 30)) >> 22;
- else if (dma_addr <
- (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20))
- goto done; /* Nothing to do for the rest of BAR1 */
- else
- panic("dma_unmap_single: Unexpect DMA address 0x%llx\n",
- dma_addr);
- /* Continued below switch statement */
+ _octeon_pci_dma_map_ops.phys_to_dma = octeon_big_phys_to_dma;
+ _octeon_pci_dma_map_ops.dma_to_phys = octeon_big_dma_to_phys;
break;
-
case OCTEON_DMA_BAR_TYPE_SMALL:
-#ifdef CONFIG_64BIT
- /* Nothing to do for addresses using BAR2 */
- if (dma_addr >= BAR2_PCI_ADDRESS)
- goto done;
-#endif
- index = dma_addr >> 22;
- /* Continued below switch statement */
+ _octeon_pci_dma_map_ops.phys_to_dma = octeon_small_phys_to_dma;
+ _octeon_pci_dma_map_ops.dma_to_phys = octeon_small_dma_to_phys;
break;
-
default:
- panic("dma_unmap_single: Invalid octeon_dma_bar_type\n");
+ BUG();
}
-
- if (unlikely(index > 31))
- panic("dma_unmap_single: "
- "Attempt to unmap an invalid address (0x%llx)\n",
- dma_addr);
-
- raw_spin_lock_irqsave(&bar1_lock, flags);
- bar1_state[index].ref_count--;
- if (bar1_state[index].ref_count == 0)
- octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
- else if (unlikely(bar1_state[index].ref_count < 0))
- panic("dma_unmap_single: Bar1[%u] reference count < 0\n",
- (int) index);
- raw_spin_unlock_irqrestore(&bar1_lock, flags);
-done:
- pr_debug("dma_unmap_single 0x%llx\n", dma_addr);
- return;
-#endif
+ octeon_pci_dma_map_ops = &_octeon_pci_dma_map_ops.dma_map_ops;
}
+#endif /* CONFIG_PCI */
diff --git a/trunk/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/trunk/arch/mips/cavium-octeon/executive/cvmx-l2c.c
index 6abe56f1e097..d38246e33ddb 100644
--- a/trunk/arch/mips/cavium-octeon/executive/cvmx-l2c.c
+++ b/trunk/arch/mips/cavium-octeon/executive/cvmx-l2c.c
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -26,8 +26,8 @@
***********************license end**************************************/
/*
- * Implementation of the Level 2 Cache (L2C) control, measurement, and
- * debugging facilities.
+ * Implementation of the Level 2 Cache (L2C) control,
+ * measurement, and debugging facilities.
*/
#include
@@ -42,13 +42,7 @@
* if multiple applications or operating systems are running, then it
* is up to the user program to coordinate between them.
*/
-static cvmx_spinlock_t cvmx_l2c_spinlock;
-
-static inline int l2_size_half(void)
-{
- uint64_t val = cvmx_read_csr(CVMX_L2D_FUS3);
- return !!(val & (1ull << 34));
-}
+cvmx_spinlock_t cvmx_l2c_spinlock;
int cvmx_l2c_get_core_way_partition(uint32_t core)
{
@@ -58,6 +52,9 @@ int cvmx_l2c_get_core_way_partition(uint32_t core)
if (core >= cvmx_octeon_num_cores())
return -1;
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+ return cvmx_read_csr(CVMX_L2C_WPAR_PPX(core)) & 0xffff;
+
/*
* Use the lower two bits of the coreNumber to determine the
* bit offset of the UMSK[] field in the L2C_SPAR register.
@@ -71,17 +68,13 @@ int cvmx_l2c_get_core_way_partition(uint32_t core)
switch (core & 0xC) {
case 0x0:
- return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >>
- field;
+ return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >> field;
case 0x4:
- return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >>
- field;
+ return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >> field;
case 0x8:
- return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >>
- field;
+ return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >> field;
case 0xC:
- return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >>
- field;
+ return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >> field;
}
return 0;
}
@@ -95,48 +88,50 @@ int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask)
mask &= valid_mask;
- /* A UMSK setting which blocks all L2C Ways is an error. */
- if (mask == valid_mask)
+ /* A UMSK setting which blocks all L2C Ways is an error on some chips */
+ if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX))
return -1;
/* Validate the core number */
if (core >= cvmx_octeon_num_cores())
return -1;
- /* Check to make sure current mask & new mask don't block all ways */
- if (((mask | cvmx_l2c_get_core_way_partition(core)) & valid_mask) ==
- valid_mask)
- return -1;
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+ cvmx_write_csr(CVMX_L2C_WPAR_PPX(core), mask);
+ return 0;
+ }
- /* Use the lower two bits of core to determine the bit offset of the
+ /*
+ * Use the lower two bits of core to determine the bit offset of the
* UMSK[] field in the L2C_SPAR register.
*/
field = (core & 0x3) * 8;
- /* Assign the new mask setting to the UMSK[] field in the appropriate
+ /*
+ * Assign the new mask setting to the UMSK[] field in the appropriate
* L2C_SPAR register based on the core_num.
*
*/
switch (core & 0xC) {
case 0x0:
cvmx_write_csr(CVMX_L2C_SPAR0,
- (cvmx_read_csr(CVMX_L2C_SPAR0) &
- ~(0xFF << field)) | mask << field);
+ (cvmx_read_csr(CVMX_L2C_SPAR0) & ~(0xFF << field)) |
+ mask << field);
break;
case 0x4:
cvmx_write_csr(CVMX_L2C_SPAR1,
- (cvmx_read_csr(CVMX_L2C_SPAR1) &
- ~(0xFF << field)) | mask << field);
+ (cvmx_read_csr(CVMX_L2C_SPAR1) & ~(0xFF << field)) |
+ mask << field);
break;
case 0x8:
cvmx_write_csr(CVMX_L2C_SPAR2,
- (cvmx_read_csr(CVMX_L2C_SPAR2) &
- ~(0xFF << field)) | mask << field);
+ (cvmx_read_csr(CVMX_L2C_SPAR2) & ~(0xFF << field)) |
+ mask << field);
break;
case 0xC:
cvmx_write_csr(CVMX_L2C_SPAR3,
- (cvmx_read_csr(CVMX_L2C_SPAR3) &
- ~(0xFF << field)) | mask << field);
+ (cvmx_read_csr(CVMX_L2C_SPAR3) & ~(0xFF << field)) |
+ mask << field);
break;
}
return 0;
@@ -146,84 +141,137 @@ int cvmx_l2c_set_hw_way_partition(uint32_t mask)
{
uint32_t valid_mask;
- valid_mask = 0xff;
-
- if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)) {
- if (l2_size_half())
- valid_mask = 0xf;
- } else if (l2_size_half())
- valid_mask = 0x3;
-
+ valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1;
mask &= valid_mask;
- /* A UMSK setting which blocks all L2C Ways is an error. */
- if (mask == valid_mask)
- return -1;
- /* Check to make sure current mask & new mask don't block all ways */
- if (((mask | cvmx_l2c_get_hw_way_partition()) & valid_mask) ==
- valid_mask)
+ /* A UMSK setting which blocks all L2C Ways is an error on some chips */
+ if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX))
return -1;
- cvmx_write_csr(CVMX_L2C_SPAR4,
- (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+ cvmx_write_csr(CVMX_L2C_WPAR_IOBX(0), mask);
+ else
+ cvmx_write_csr(CVMX_L2C_SPAR4,
+ (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);
return 0;
}
int cvmx_l2c_get_hw_way_partition(void)
{
- return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF);
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+ return cvmx_read_csr(CVMX_L2C_WPAR_IOBX(0)) & 0xffff;
+ else
+ return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF);
}
void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event,
uint32_t clear_on_read)
{
- union cvmx_l2c_pfctl pfctl;
+ if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
+ union cvmx_l2c_pfctl pfctl;
- pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL);
+ pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL);
- switch (counter) {
- case 0:
- pfctl.s.cnt0sel = event;
- pfctl.s.cnt0ena = 1;
- if (!cvmx_octeon_is_pass1())
+ switch (counter) {
+ case 0:
+ pfctl.s.cnt0sel = event;
+ pfctl.s.cnt0ena = 1;
pfctl.s.cnt0rdclr = clear_on_read;
- break;
- case 1:
- pfctl.s.cnt1sel = event;
- pfctl.s.cnt1ena = 1;
- if (!cvmx_octeon_is_pass1())
+ break;
+ case 1:
+ pfctl.s.cnt1sel = event;
+ pfctl.s.cnt1ena = 1;
pfctl.s.cnt1rdclr = clear_on_read;
- break;
- case 2:
- pfctl.s.cnt2sel = event;
- pfctl.s.cnt2ena = 1;
- if (!cvmx_octeon_is_pass1())
+ break;
+ case 2:
+ pfctl.s.cnt2sel = event;
+ pfctl.s.cnt2ena = 1;
pfctl.s.cnt2rdclr = clear_on_read;
- break;
- case 3:
- default:
- pfctl.s.cnt3sel = event;
- pfctl.s.cnt3ena = 1;
- if (!cvmx_octeon_is_pass1())
+ break;
+ case 3:
+ default:
+ pfctl.s.cnt3sel = event;
+ pfctl.s.cnt3ena = 1;
pfctl.s.cnt3rdclr = clear_on_read;
- break;
- }
+ break;
+ }
- cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64);
+ cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64);
+ } else {
+ union cvmx_l2c_tadx_prf l2c_tadx_prf;
+ int tad;
+
+ cvmx_dprintf("L2C performance counter events are different for this chip, mapping 'event' to cvmx_l2c_tad_event_t\n");
+ if (clear_on_read)
+ cvmx_dprintf("L2C counters don't support clear on read for this chip\n");
+
+ l2c_tadx_prf.u64 = cvmx_read_csr(CVMX_L2C_TADX_PRF(0));
+
+ switch (counter) {
+ case 0:
+ l2c_tadx_prf.s.cnt0sel = event;
+ break;
+ case 1:
+ l2c_tadx_prf.s.cnt1sel = event;
+ break;
+ case 2:
+ l2c_tadx_prf.s.cnt2sel = event;
+ break;
+ default:
+ case 3:
+ l2c_tadx_prf.s.cnt3sel = event;
+ break;
+ }
+ for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+ cvmx_write_csr(CVMX_L2C_TADX_PRF(tad),
+ l2c_tadx_prf.u64);
+ }
}
uint64_t cvmx_l2c_read_perf(uint32_t counter)
{
switch (counter) {
case 0:
- return cvmx_read_csr(CVMX_L2C_PFC0);
+ if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+ return cvmx_read_csr(CVMX_L2C_PFC0);
+ else {
+ uint64_t counter = 0;
+ int tad;
+ for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+ counter += cvmx_read_csr(CVMX_L2C_TADX_PFC0(tad));
+ return counter;
+ }
case 1:
- return cvmx_read_csr(CVMX_L2C_PFC1);
+ if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+ return cvmx_read_csr(CVMX_L2C_PFC1);
+ else {
+ uint64_t counter = 0;
+ int tad;
+ for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+ counter += cvmx_read_csr(CVMX_L2C_TADX_PFC1(tad));
+ return counter;
+ }
case 2:
- return cvmx_read_csr(CVMX_L2C_PFC2);
+ if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+ return cvmx_read_csr(CVMX_L2C_PFC2);
+ else {
+ uint64_t counter = 0;
+ int tad;
+ for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+ counter += cvmx_read_csr(CVMX_L2C_TADX_PFC2(tad));
+ return counter;
+ }
case 3:
default:
- return cvmx_read_csr(CVMX_L2C_PFC3);
+ if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+ return cvmx_read_csr(CVMX_L2C_PFC3);
+ else {
+ uint64_t counter = 0;
+ int tad;
+ for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+ counter += cvmx_read_csr(CVMX_L2C_TADX_PFC3(tad));
+ return counter;
+ }
}
}
@@ -240,7 +288,7 @@ static void fault_in(uint64_t addr, int len)
volatile char dummy;
/*
* Adjust addr and length so we get all cache lines even for
- * small ranges spanning two cache lines
+ * small ranges spanning two cache lines.
*/
len += addr & CVMX_CACHE_LINE_MASK;
addr &= ~CVMX_CACHE_LINE_MASK;
@@ -259,67 +307,100 @@ static void fault_in(uint64_t addr, int len)
int cvmx_l2c_lock_line(uint64_t addr)
{
- int retval = 0;
- union cvmx_l2c_dbg l2cdbg;
- union cvmx_l2c_lckbase lckbase;
- union cvmx_l2c_lckoff lckoff;
- union cvmx_l2t_err l2t_err;
- l2cdbg.u64 = 0;
- lckbase.u64 = 0;
- lckoff.u64 = 0;
-
- cvmx_spinlock_lock(&cvmx_l2c_spinlock);
-
- /* Clear l2t error bits if set */
- l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
- l2t_err.s.lckerr = 1;
- l2t_err.s.lckerr2 = 1;
- cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+ int shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT;
+ uint64_t assoc = cvmx_l2c_get_num_assoc();
+ uint64_t tag = addr >> shift;
+ uint64_t index = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, cvmx_l2c_address_to_index(addr) << CVMX_L2C_IDX_ADDR_SHIFT);
+ uint64_t way;
+ union cvmx_l2c_tadx_tag l2c_tadx_tag;
+
+ CVMX_CACHE_LCKL2(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, addr), 0);
+
+ /* Make sure we were able to lock the line */
+ for (way = 0; way < assoc; way++) {
+ CVMX_CACHE_LTGL2I(index | (way << shift), 0);
+ /* make sure CVMX_L2C_TADX_TAG is updated */
+ CVMX_SYNC;
+ l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
+ if (l2c_tadx_tag.s.valid && l2c_tadx_tag.s.tag == tag)
+ break;
+ }
- addr &= ~CVMX_CACHE_LINE_MASK;
+ /* Check if a valid line is found */
+ if (way >= assoc) {
+ /* cvmx_dprintf("ERROR: cvmx_l2c_lock_line: line not found for locking at 0x%llx address\n", (unsigned long long)addr); */
+ return -1;
+ }
- /* Set this core as debug core */
- l2cdbg.s.ppnum = cvmx_get_core_num();
- CVMX_SYNC;
- cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
- cvmx_read_csr(CVMX_L2C_DBG);
-
- lckoff.s.lck_offset = 0; /* Only lock 1 line at a time */
- cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64);
- cvmx_read_csr(CVMX_L2C_LCKOFF);
-
- if (((union cvmx_l2c_cfg) (cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) {
- int alias_shift =
- CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
- uint64_t addr_tmp =
- addr ^ (addr & ((1 << alias_shift) - 1)) >>
- CVMX_L2_SET_BITS;
- lckbase.s.lck_base = addr_tmp >> 7;
+ /* Check if lock bit is not set */
+ if (!l2c_tadx_tag.s.lock) {
+ /* cvmx_dprintf("ERROR: cvmx_l2c_lock_line: Not able to lock at 0x%llx address\n", (unsigned long long)addr); */
+ return -1;
+ }
+ return way;
} else {
- lckbase.s.lck_base = addr >> 7;
- }
+ int retval = 0;
+ union cvmx_l2c_dbg l2cdbg;
+ union cvmx_l2c_lckbase lckbase;
+ union cvmx_l2c_lckoff lckoff;
+ union cvmx_l2t_err l2t_err;
- lckbase.s.lck_ena = 1;
- cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
- cvmx_read_csr(CVMX_L2C_LCKBASE); /* Make sure it gets there */
+ cvmx_spinlock_lock(&cvmx_l2c_spinlock);
- fault_in(addr, CVMX_CACHE_LINE_SIZE);
+ l2cdbg.u64 = 0;
+ lckbase.u64 = 0;
+ lckoff.u64 = 0;
- lckbase.s.lck_ena = 0;
- cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
- cvmx_read_csr(CVMX_L2C_LCKBASE); /* Make sure it gets there */
+ /* Clear l2t error bits if set */
+ l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+ l2t_err.s.lckerr = 1;
+ l2t_err.s.lckerr2 = 1;
+ cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
- /* Stop being debug core */
- cvmx_write_csr(CVMX_L2C_DBG, 0);
- cvmx_read_csr(CVMX_L2C_DBG);
+ addr &= ~CVMX_CACHE_LINE_MASK;
- l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
- if (l2t_err.s.lckerr || l2t_err.s.lckerr2)
- retval = 1; /* We were unable to lock the line */
+ /* Set this core as debug core */
+ l2cdbg.s.ppnum = cvmx_get_core_num();
+ CVMX_SYNC;
+ cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
+ cvmx_read_csr(CVMX_L2C_DBG);
+
+ lckoff.s.lck_offset = 0; /* Only lock 1 line at a time */
+ cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64);
+ cvmx_read_csr(CVMX_L2C_LCKOFF);
+
+ if (((union cvmx_l2c_cfg)(cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) {
+ int alias_shift = CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
+ uint64_t addr_tmp = addr ^ (addr & ((1 << alias_shift) - 1)) >> CVMX_L2_SET_BITS;
+ lckbase.s.lck_base = addr_tmp >> 7;
+ } else {
+ lckbase.s.lck_base = addr >> 7;
+ }
- cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+ lckbase.s.lck_ena = 1;
+ cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
+ /* Make sure it gets there */
+ cvmx_read_csr(CVMX_L2C_LCKBASE);
- return retval;
+ fault_in(addr, CVMX_CACHE_LINE_SIZE);
+
+ lckbase.s.lck_ena = 0;
+ cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
+ /* Make sure it gets there */
+ cvmx_read_csr(CVMX_L2C_LCKBASE);
+
+ /* Stop being debug core */
+ cvmx_write_csr(CVMX_L2C_DBG, 0);
+ cvmx_read_csr(CVMX_L2C_DBG);
+
+ l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+ if (l2t_err.s.lckerr || l2t_err.s.lckerr2)
+ retval = 1; /* We were unable to lock the line */
+
+ cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+ return retval;
+ }
}
int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len)
@@ -336,7 +417,6 @@ int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len)
start += CVMX_CACHE_LINE_SIZE;
len -= CVMX_CACHE_LINE_SIZE;
}
-
return retval;
}
@@ -344,80 +424,73 @@ void cvmx_l2c_flush(void)
{
uint64_t assoc, set;
uint64_t n_assoc, n_set;
- union cvmx_l2c_dbg l2cdbg;
-
- cvmx_spinlock_lock(&cvmx_l2c_spinlock);
- l2cdbg.u64 = 0;
- if (!OCTEON_IS_MODEL(OCTEON_CN30XX))
- l2cdbg.s.ppnum = cvmx_get_core_num();
- l2cdbg.s.finv = 1;
- n_set = CVMX_L2_SETS;
- n_assoc = l2_size_half() ? (CVMX_L2_ASSOC / 2) : CVMX_L2_ASSOC;
- for (set = 0; set < n_set; set++) {
- for (assoc = 0; assoc < n_assoc; assoc++) {
- l2cdbg.s.set = assoc;
- /* Enter debug mode, and make sure all other
- ** writes complete before we enter debug
- ** mode */
- CVMX_SYNCW;
- cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
- cvmx_read_csr(CVMX_L2C_DBG);
-
- CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG
- (CVMX_MIPS_SPACE_XKPHYS,
- set * CVMX_CACHE_LINE_SIZE), 0);
- CVMX_SYNCW; /* Push STF out to L2 */
- /* Exit debug mode */
- CVMX_SYNC;
- cvmx_write_csr(CVMX_L2C_DBG, 0);
- cvmx_read_csr(CVMX_L2C_DBG);
+ n_set = cvmx_l2c_get_num_sets();
+ n_assoc = cvmx_l2c_get_num_assoc();
+
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+ uint64_t address;
+ /* These may look like constants, but they aren't... */
+ int assoc_shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT;
+ int set_shift = CVMX_L2C_IDX_ADDR_SHIFT;
+ for (set = 0; set < n_set; set++) {
+ for (assoc = 0; assoc < n_assoc; assoc++) {
+ address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+ (assoc << assoc_shift) | (set << set_shift));
+ CVMX_CACHE_WBIL2I(address, 0);
+ }
}
+ } else {
+ for (set = 0; set < n_set; set++)
+ for (assoc = 0; assoc < n_assoc; assoc++)
+ cvmx_l2c_flush_line(assoc, set);
}
-
- cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
}
+
int cvmx_l2c_unlock_line(uint64_t address)
{
- int assoc;
- union cvmx_l2c_tag tag;
- union cvmx_l2c_dbg l2cdbg;
- uint32_t tag_addr;
- uint32_t index = cvmx_l2c_address_to_index(address);
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+ int assoc;
+ union cvmx_l2c_tag tag;
+ uint32_t tag_addr;
+ uint32_t index = cvmx_l2c_address_to_index(address);
+
+ tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
+
+ /*
+ * For 63XX, we can flush a line by using the physical
+ * address directly, so finding the cache line used by
+ * the address is only required to provide the proper
+ * return value for the function.
+ */
+ for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) {
+ tag = cvmx_l2c_get_tag(assoc, index);
+
+ if (tag.s.V && (tag.s.addr == tag_addr)) {
+ CVMX_CACHE_WBIL2(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, address), 0);
+ return tag.s.L;
+ }
+ }
+ } else {
+ int assoc;
+ union cvmx_l2c_tag tag;
+ uint32_t tag_addr;
- cvmx_spinlock_lock(&cvmx_l2c_spinlock);
- /* Compute portion of address that is stored in tag */
- tag_addr =
- ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) &
- ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
- for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) {
- tag = cvmx_get_l2c_tag(assoc, index);
+ uint32_t index = cvmx_l2c_address_to_index(address);
- if (tag.s.V && (tag.s.addr == tag_addr)) {
- l2cdbg.u64 = 0;
- l2cdbg.s.ppnum = cvmx_get_core_num();
- l2cdbg.s.set = assoc;
- l2cdbg.s.finv = 1;
+ /* Compute portion of address that is stored in tag */
+ tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
+ for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) {
+ tag = cvmx_l2c_get_tag(assoc, index);
- CVMX_SYNC;
- /* Enter debug mode */
- cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
- cvmx_read_csr(CVMX_L2C_DBG);
-
- CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG
- (CVMX_MIPS_SPACE_XKPHYS,
- address), 0);
- CVMX_SYNC;
- /* Exit debug mode */
- cvmx_write_csr(CVMX_L2C_DBG, 0);
- cvmx_read_csr(CVMX_L2C_DBG);
- cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
- return tag.s.L;
+ if (tag.s.V && (tag.s.addr == tag_addr)) {
+ cvmx_l2c_flush_line(assoc, index);
+ return tag.s.L;
+ }
}
}
- cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
return 0;
}
@@ -445,48 +518,49 @@ union __cvmx_l2c_tag {
uint64_t u64;
struct cvmx_l2c_tag_cn50xx {
uint64_t reserved:40;
- uint64_t V:1; /* Line valid */
- uint64_t D:1; /* Line dirty */
- uint64_t L:1; /* Line locked */
- uint64_t U:1; /* Use, LRU eviction */
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
uint64_t addr:20; /* Phys mem addr (33..14) */
} cn50xx;
struct cvmx_l2c_tag_cn30xx {
uint64_t reserved:41;
- uint64_t V:1; /* Line valid */
- uint64_t D:1; /* Line dirty */
- uint64_t L:1; /* Line locked */
- uint64_t U:1; /* Use, LRU eviction */
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
uint64_t addr:19; /* Phys mem addr (33..15) */
} cn30xx;
struct cvmx_l2c_tag_cn31xx {
uint64_t reserved:42;
- uint64_t V:1; /* Line valid */
- uint64_t D:1; /* Line dirty */
- uint64_t L:1; /* Line locked */
- uint64_t U:1; /* Use, LRU eviction */
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
uint64_t addr:18; /* Phys mem addr (33..16) */
} cn31xx;
struct cvmx_l2c_tag_cn38xx {
uint64_t reserved:43;
- uint64_t V:1; /* Line valid */
- uint64_t D:1; /* Line dirty */
- uint64_t L:1; /* Line locked */
- uint64_t U:1; /* Use, LRU eviction */
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
uint64_t addr:17; /* Phys mem addr (33..17) */
} cn38xx;
struct cvmx_l2c_tag_cn58xx {
uint64_t reserved:44;
- uint64_t V:1; /* Line valid */
- uint64_t D:1; /* Line dirty */
- uint64_t L:1; /* Line locked */
- uint64_t U:1; /* Use, LRU eviction */
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
uint64_t addr:16; /* Phys mem addr (33..18) */
} cn58xx;
struct cvmx_l2c_tag_cn58xx cn56xx; /* 2048 sets */
struct cvmx_l2c_tag_cn31xx cn52xx; /* 512 sets */
};
+
/**
* @INTERNAL
* Function to read a L2C tag. This code make the current core
@@ -503,7 +577,7 @@ union __cvmx_l2c_tag {
static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
{
- uint64_t debug_tag_addr = (((1ULL << 63) | (index << 7)) + 96);
+ uint64_t debug_tag_addr = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, (index << 7) + 96);
uint64_t core = cvmx_get_core_num();
union __cvmx_l2c_tag tag_val;
uint64_t dbg_addr = CVMX_L2C_DBG;
@@ -512,12 +586,15 @@ static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
union cvmx_l2c_dbg debug_val;
debug_val.u64 = 0;
/*
- * For low core count parts, the core number is always small enough
- * to stay in the correct field and not set any reserved bits.
+ * For low core count parts, the core number is always small
+ * enough to stay in the correct field and not set any
+ * reserved bits.
*/
debug_val.s.ppnum = core;
debug_val.s.l2t = 1;
debug_val.s.set = assoc;
+
+ local_irq_save(flags);
/*
* Make sure core is quiet (no prefetches, etc.) before
* entering debug mode.
@@ -526,112 +603,139 @@ static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
/* Flush L1 to make sure debug load misses L1 */
CVMX_DCACHE_INVALIDATE;
- local_irq_save(flags);
-
/*
* The following must be done in assembly as when in debug
* mode all data loads from L2 return special debug data, not
- * normal memory contents. Also, interrupts must be
- * disabled, since if an interrupt occurs while in debug mode
- * the ISR will get debug data from all its memory reads
- * instead of the contents of memory
+ * normal memory contents. Also, interrupts must be disabled,
+ * since if an interrupt occurs while in debug mode the ISR
+ * will get debug data from all its memory * reads instead of
+ * the contents of memory.
*/
- asm volatile (".set push \n"
- " .set mips64 \n"
- " .set noreorder \n"
- /* Enter debug mode, wait for store */
- " sd %[dbg_val], 0(%[dbg_addr]) \n"
- " ld $0, 0(%[dbg_addr]) \n"
- /* Read L2C tag data */
- " ld %[tag_val], 0(%[tag_addr]) \n"
- /* Exit debug mode, wait for store */
- " sd $0, 0(%[dbg_addr]) \n"
- " ld $0, 0(%[dbg_addr]) \n"
- /* Invalidate dcache to discard debug data */
- " cache 9, 0($0) \n"
- " .set pop" :
- [tag_val] "=r"(tag_val.u64) : [dbg_addr] "r"(dbg_addr),
- [dbg_val] "r"(debug_val.u64),
- [tag_addr] "r"(debug_tag_addr) : "memory");
+ asm volatile (
+ ".set push\n\t"
+ ".set mips64\n\t"
+ ".set noreorder\n\t"
+ "sd %[dbg_val], 0(%[dbg_addr])\n\t" /* Enter debug mode, wait for store */
+ "ld $0, 0(%[dbg_addr])\n\t"
+ "ld %[tag_val], 0(%[tag_addr])\n\t" /* Read L2C tag data */
+ "sd $0, 0(%[dbg_addr])\n\t" /* Exit debug mode, wait for store */
+ "ld $0, 0(%[dbg_addr])\n\t"
+ "cache 9, 0($0)\n\t" /* Invalidate dcache to discard debug data */
+ ".set pop"
+ : [tag_val] "=r" (tag_val)
+ : [dbg_addr] "r" (dbg_addr), [dbg_val] "r" (debug_val), [tag_addr] "r" (debug_tag_addr)
+ : "memory");
local_irq_restore(flags);
- return tag_val;
+ return tag_val;
}
+
union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index)
{
- union __cvmx_l2c_tag tmp_tag;
union cvmx_l2c_tag tag;
tag.u64 = 0;
if ((int)association >= cvmx_l2c_get_num_assoc()) {
- cvmx_dprintf
- ("ERROR: cvmx_get_l2c_tag association out of range\n");
+ cvmx_dprintf("ERROR: cvmx_l2c_get_tag association out of range\n");
return tag;
}
if ((int)index >= cvmx_l2c_get_num_sets()) {
- cvmx_dprintf("ERROR: cvmx_get_l2c_tag "
- "index out of range (arg: %d, max: %d\n",
- index, cvmx_l2c_get_num_sets());
+ cvmx_dprintf("ERROR: cvmx_l2c_get_tag index out of range (arg: %d, max: %d)\n",
+ (int)index, cvmx_l2c_get_num_sets());
return tag;
}
- /* __read_l2_tag is intended for internal use only */
- tmp_tag = __read_l2_tag(association, index);
-
- /*
- * Convert all tag structure types to generic version, as it
- * can represent all models.
- */
- if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
- tag.s.V = tmp_tag.cn58xx.V;
- tag.s.D = tmp_tag.cn58xx.D;
- tag.s.L = tmp_tag.cn58xx.L;
- tag.s.U = tmp_tag.cn58xx.U;
- tag.s.addr = tmp_tag.cn58xx.addr;
- } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
- tag.s.V = tmp_tag.cn38xx.V;
- tag.s.D = tmp_tag.cn38xx.D;
- tag.s.L = tmp_tag.cn38xx.L;
- tag.s.U = tmp_tag.cn38xx.U;
- tag.s.addr = tmp_tag.cn38xx.addr;
- } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
- || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
- tag.s.V = tmp_tag.cn31xx.V;
- tag.s.D = tmp_tag.cn31xx.D;
- tag.s.L = tmp_tag.cn31xx.L;
- tag.s.U = tmp_tag.cn31xx.U;
- tag.s.addr = tmp_tag.cn31xx.addr;
- } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
- tag.s.V = tmp_tag.cn30xx.V;
- tag.s.D = tmp_tag.cn30xx.D;
- tag.s.L = tmp_tag.cn30xx.L;
- tag.s.U = tmp_tag.cn30xx.U;
- tag.s.addr = tmp_tag.cn30xx.addr;
- } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
- tag.s.V = tmp_tag.cn50xx.V;
- tag.s.D = tmp_tag.cn50xx.D;
- tag.s.L = tmp_tag.cn50xx.L;
- tag.s.U = tmp_tag.cn50xx.U;
- tag.s.addr = tmp_tag.cn50xx.addr;
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+ union cvmx_l2c_tadx_tag l2c_tadx_tag;
+ uint64_t address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+ (association << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) |
+ (index << CVMX_L2C_IDX_ADDR_SHIFT));
+ /*
+ * Use L2 cache Index load tag cache instruction, as
+ * hardware loads the virtual tag for the L2 cache
+ * block with the contents of L2C_TAD0_TAG
+ * register.
+ */
+ CVMX_CACHE_LTGL2I(address, 0);
+ CVMX_SYNC; /* make sure CVMX_L2C_TADX_TAG is updated */
+ l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
+
+ tag.s.V = l2c_tadx_tag.s.valid;
+ tag.s.D = l2c_tadx_tag.s.dirty;
+ tag.s.L = l2c_tadx_tag.s.lock;
+ tag.s.U = l2c_tadx_tag.s.use;
+ tag.s.addr = l2c_tadx_tag.s.tag;
} else {
- cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
+ union __cvmx_l2c_tag tmp_tag;
+ /* __read_l2_tag is intended for internal use only */
+ tmp_tag = __read_l2_tag(association, index);
+
+ /*
+ * Convert all tag structure types to generic version,
+ * as it can represent all models.
+ */
+ if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
+ tag.s.V = tmp_tag.cn58xx.V;
+ tag.s.D = tmp_tag.cn58xx.D;
+ tag.s.L = tmp_tag.cn58xx.L;
+ tag.s.U = tmp_tag.cn58xx.U;
+ tag.s.addr = tmp_tag.cn58xx.addr;
+ } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
+ tag.s.V = tmp_tag.cn38xx.V;
+ tag.s.D = tmp_tag.cn38xx.D;
+ tag.s.L = tmp_tag.cn38xx.L;
+ tag.s.U = tmp_tag.cn38xx.U;
+ tag.s.addr = tmp_tag.cn38xx.addr;
+ } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
+ tag.s.V = tmp_tag.cn31xx.V;
+ tag.s.D = tmp_tag.cn31xx.D;
+ tag.s.L = tmp_tag.cn31xx.L;
+ tag.s.U = tmp_tag.cn31xx.U;
+ tag.s.addr = tmp_tag.cn31xx.addr;
+ } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
+ tag.s.V = tmp_tag.cn30xx.V;
+ tag.s.D = tmp_tag.cn30xx.D;
+ tag.s.L = tmp_tag.cn30xx.L;
+ tag.s.U = tmp_tag.cn30xx.U;
+ tag.s.addr = tmp_tag.cn30xx.addr;
+ } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
+ tag.s.V = tmp_tag.cn50xx.V;
+ tag.s.D = tmp_tag.cn50xx.D;
+ tag.s.L = tmp_tag.cn50xx.L;
+ tag.s.U = tmp_tag.cn50xx.U;
+ tag.s.addr = tmp_tag.cn50xx.addr;
+ } else {
+ cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
+ }
}
-
return tag;
}
uint32_t cvmx_l2c_address_to_index(uint64_t addr)
{
uint64_t idx = addr >> CVMX_L2C_IDX_ADDR_SHIFT;
- union cvmx_l2c_cfg l2c_cfg;
- l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+ int indxalias = 0;
- if (l2c_cfg.s.idxalias) {
- idx ^=
- ((addr & CVMX_L2C_ALIAS_MASK) >>
- CVMX_L2C_TAG_ADDR_ALIAS_SHIFT);
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+ union cvmx_l2c_ctl l2c_ctl;
+ l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
+ indxalias = !l2c_ctl.s.disidxalias;
+ } else {
+ union cvmx_l2c_cfg l2c_cfg;
+ l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+ indxalias = l2c_cfg.s.idxalias;
+ }
+
+ if (indxalias) {
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+ uint32_t a_14_12 = (idx / (CVMX_L2C_MEMBANK_SELECT_SIZE/(1<> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT);
+ }
}
idx &= CVMX_L2C_IDX_MASK;
return idx;
@@ -652,10 +756,9 @@ int cvmx_l2c_get_set_bits(void)
int l2_set_bits;
if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
l2_set_bits = 11; /* 2048 sets */
- else if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+ else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
l2_set_bits = 10; /* 1024 sets */
- else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
- || OCTEON_IS_MODEL(OCTEON_CN52XX))
+ else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
l2_set_bits = 9; /* 512 sets */
else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
l2_set_bits = 8; /* 256 sets */
@@ -666,7 +769,6 @@ int cvmx_l2c_get_set_bits(void)
l2_set_bits = 11; /* 2048 sets */
}
return l2_set_bits;
-
}
/* Return the number of sets in the L2 Cache */
@@ -682,8 +784,11 @@ int cvmx_l2c_get_num_assoc(void)
if (OCTEON_IS_MODEL(OCTEON_CN56XX) ||
OCTEON_IS_MODEL(OCTEON_CN52XX) ||
OCTEON_IS_MODEL(OCTEON_CN58XX) ||
- OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN38XX))
+ OCTEON_IS_MODEL(OCTEON_CN50XX) ||
+ OCTEON_IS_MODEL(OCTEON_CN38XX))
l2_assoc = 8;
+ else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+ l2_assoc = 16;
else if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
OCTEON_IS_MODEL(OCTEON_CN30XX))
l2_assoc = 4;
@@ -693,11 +798,42 @@ int cvmx_l2c_get_num_assoc(void)
}
/* Check to see if part of the cache is disabled */
- if (cvmx_fuse_read(265))
- l2_assoc = l2_assoc >> 2;
- else if (cvmx_fuse_read(264))
- l2_assoc = l2_assoc >> 1;
-
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+ union cvmx_mio_fus_dat3 mio_fus_dat3;
+
+ mio_fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
+ /*
+ * cvmx_mio_fus_dat3.s.l2c_crip fuses map as follows
+ * <2> will be not used for 63xx
+ * <1> disables 1/2 ways
+ * <0> disables 1/4 ways
+ * They are cumulative, so for 63xx:
+ * <1> <0>
+ * 0 0 16-way 2MB cache
+ * 0 1 12-way 1.5MB cache
+ * 1 0 8-way 1MB cache
+ * 1 1 4-way 512KB cache
+ */
+
+ if (mio_fus_dat3.s.l2c_crip == 3)
+ l2_assoc = 4;
+ else if (mio_fus_dat3.s.l2c_crip == 2)
+ l2_assoc = 8;
+ else if (mio_fus_dat3.s.l2c_crip == 1)
+ l2_assoc = 12;
+ } else {
+ union cvmx_l2d_fus3 val;
+ val.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
+ /*
+ * Using shifts here, as bit position names are
+ * different for each model but they all mean the
+ * same.
+ */
+ if ((val.u64 >> 35) & 0x1)
+ l2_assoc = l2_assoc >> 2;
+ else if ((val.u64 >> 34) & 0x1)
+ l2_assoc = l2_assoc >> 1;
+ }
return l2_assoc;
}
@@ -711,24 +847,54 @@ int cvmx_l2c_get_num_assoc(void)
*/
void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index)
{
- union cvmx_l2c_dbg l2cdbg;
+ /* Check the range of the index. */
+ if (index > (uint32_t)cvmx_l2c_get_num_sets()) {
+ cvmx_dprintf("ERROR: cvmx_l2c_flush_line index out of range.\n");
+ return;
+ }
- l2cdbg.u64 = 0;
- l2cdbg.s.ppnum = cvmx_get_core_num();
- l2cdbg.s.finv = 1;
+ /* Check the range of association. */
+ if (assoc > (uint32_t)cvmx_l2c_get_num_assoc()) {
+ cvmx_dprintf("ERROR: cvmx_l2c_flush_line association out of range.\n");
+ return;
+ }
- l2cdbg.s.set = assoc;
- /*
- * Enter debug mode, and make sure all other writes complete
- * before we enter debug mode.
- */
- asm volatile ("sync" : : : "memory");
- cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
- cvmx_read_csr(CVMX_L2C_DBG);
-
- CVMX_PREPARE_FOR_STORE(((1ULL << 63) + (index) * 128), 0);
- /* Exit debug mode */
- asm volatile ("sync" : : : "memory");
- cvmx_write_csr(CVMX_L2C_DBG, 0);
- cvmx_read_csr(CVMX_L2C_DBG);
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+ uint64_t address;
+ /* Create the address based on index and association.
+ * Bits<20:17> select the way of the cache block involved in
+ * the operation
+ * Bits<16:7> of the effect address select the index
+ */
+ address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+ (assoc << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) |
+ (index << CVMX_L2C_IDX_ADDR_SHIFT));
+ CVMX_CACHE_WBIL2I(address, 0);
+ } else {
+ union cvmx_l2c_dbg l2cdbg;
+
+ l2cdbg.u64 = 0;
+ if (!OCTEON_IS_MODEL(OCTEON_CN30XX))
+ l2cdbg.s.ppnum = cvmx_get_core_num();
+ l2cdbg.s.finv = 1;
+
+ l2cdbg.s.set = assoc;
+ cvmx_spinlock_lock(&cvmx_l2c_spinlock);
+ /*
+ * Enter debug mode, and make sure all other writes
+ * complete before we enter debug mode
+ */
+ CVMX_SYNC;
+ cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
+ cvmx_read_csr(CVMX_L2C_DBG);
+
+ CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+ index * CVMX_CACHE_LINE_SIZE),
+ 0);
+ /* Exit debug mode */
+ CVMX_SYNC;
+ cvmx_write_csr(CVMX_L2C_DBG, 0);
+ cvmx_read_csr(CVMX_L2C_DBG);
+ cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+ }
}
diff --git a/trunk/arch/mips/cavium-octeon/octeon-platform.c b/trunk/arch/mips/cavium-octeon/octeon-platform.c
index 62ac30eef5e8..cecaf62aef32 100644
--- a/trunk/arch/mips/cavium-octeon/octeon-platform.c
+++ b/trunk/arch/mips/cavium-octeon/octeon-platform.c
@@ -3,13 +3,15 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2004-2009 Cavium Networks
+ * Copyright (C) 2004-2010 Cavium Networks
* Copyright (C) 2008 Wind River Systems
*/
#include
#include
#include
+#include
+#include
#include
#include
@@ -198,7 +200,7 @@ static int __init octeon_i2c_device_init(void)
num_ports = 1;
for (port = 0; port < num_ports; port++) {
- octeon_i2c_data[port].sys_freq = octeon_get_clock_rate();
+ octeon_i2c_data[port].sys_freq = octeon_get_io_clock_rate();
/*FIXME: should be examined. At the moment is set for 100Khz */
octeon_i2c_data[port].i2c_freq = 100000;
@@ -301,6 +303,10 @@ static int __init octeon_mgmt_device_init(void)
ret = -ENOMEM;
goto out;
}
+ /* No DMA restrictions */
+ pd->dev.coherent_dma_mask = DMA_BIT_MASK(64);
+ pd->dev.dma_mask = &pd->dev.coherent_dma_mask;
+
switch (port) {
case 0:
mgmt_port_resource.start = OCTEON_IRQ_MII0;
@@ -332,6 +338,108 @@ static int __init octeon_mgmt_device_init(void)
}
device_initcall(octeon_mgmt_device_init);
+#ifdef CONFIG_USB
+
+static int __init octeon_ehci_device_init(void)
+{
+ struct platform_device *pd;
+ int ret = 0;
+
+ struct resource usb_resources[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ }, {
+ .flags = IORESOURCE_IRQ,
+ }
+ };
+
+ /* Only Octeon2 has ehci/ohci */
+ if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
+ return 0;
+
+ if (octeon_is_simulation() || usb_disabled())
+ return 0; /* No USB in the simulator. */
+
+ pd = platform_device_alloc("octeon-ehci", 0);
+ if (!pd) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ usb_resources[0].start = 0x00016F0000000000ULL;
+ usb_resources[0].end = usb_resources[0].start + 0x100;
+
+ usb_resources[1].start = OCTEON_IRQ_USB0;
+ usb_resources[1].end = OCTEON_IRQ_USB0;
+
+ ret = platform_device_add_resources(pd, usb_resources,
+ ARRAY_SIZE(usb_resources));
+ if (ret)
+ goto fail;
+
+ ret = platform_device_add(pd);
+ if (ret)
+ goto fail;
+
+ return ret;
+fail:
+ platform_device_put(pd);
+out:
+ return ret;
+}
+device_initcall(octeon_ehci_device_init);
+
+static int __init octeon_ohci_device_init(void)
+{
+ struct platform_device *pd;
+ int ret = 0;
+
+ struct resource usb_resources[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ }, {
+ .flags = IORESOURCE_IRQ,
+ }
+ };
+
+ /* Only Octeon2 has ehci/ohci */
+ if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
+ return 0;
+
+ if (octeon_is_simulation() || usb_disabled())
+ return 0; /* No USB in the simulator. */
+
+ pd = platform_device_alloc("octeon-ohci", 0);
+ if (!pd) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ usb_resources[0].start = 0x00016F0000000400ULL;
+ usb_resources[0].end = usb_resources[0].start + 0x100;
+
+ usb_resources[1].start = OCTEON_IRQ_USB0;
+ usb_resources[1].end = OCTEON_IRQ_USB0;
+
+ ret = platform_device_add_resources(pd, usb_resources,
+ ARRAY_SIZE(usb_resources));
+ if (ret)
+ goto fail;
+
+ ret = platform_device_add(pd);
+ if (ret)
+ goto fail;
+
+ return ret;
+fail:
+ platform_device_put(pd);
+out:
+ return ret;
+}
+device_initcall(octeon_ohci_device_init);
+
+#endif /* CONFIG_USB */
+
MODULE_AUTHOR("David Daney ");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Platform driver for Octeon SOC");
diff --git a/trunk/arch/mips/cavium-octeon/serial.c b/trunk/arch/mips/cavium-octeon/serial.c
index 12dbf533b77d..057f0ae88c99 100644
--- a/trunk/arch/mips/cavium-octeon/serial.c
+++ b/trunk/arch/mips/cavium-octeon/serial.c
@@ -66,7 +66,7 @@ static void __init octeon_uart_set_common(struct plat_serial8250_port *p)
/* Make simulator output fast*/
p->uartclk = 115200 * 16;
else
- p->uartclk = mips_hpt_frequency;
+ p->uartclk = octeon_get_io_clock_rate();
p->serial_in = octeon_serial_in;
p->serial_out = octeon_serial_out;
}
diff --git a/trunk/arch/mips/cavium-octeon/setup.c b/trunk/arch/mips/cavium-octeon/setup.c
index 69197cb6c7ea..b0c3686c96dd 100644
--- a/trunk/arch/mips/cavium-octeon/setup.c
+++ b/trunk/arch/mips/cavium-octeon/setup.c
@@ -33,6 +33,7 @@
#include
#include
+#include
#ifdef CONFIG_CAVIUM_DECODE_RSL
extern void cvmx_interrupt_rsl_decode(void);
@@ -96,12 +97,21 @@ int octeon_is_pci_host(void)
*/
uint64_t octeon_get_clock_rate(void)
{
- if (octeon_is_simulation())
- octeon_bootinfo->eclock_hz = 6000000;
- return octeon_bootinfo->eclock_hz;
+ struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
+
+ return sysinfo->cpu_clock_hz;
}
EXPORT_SYMBOL(octeon_get_clock_rate);
+static u64 octeon_io_clock_rate;
+
+u64 octeon_get_io_clock_rate(void)
+{
+ return octeon_io_clock_rate;
+}
+EXPORT_SYMBOL(octeon_get_io_clock_rate);
+
+
/**
* Write to the LCD display connected to the bootbus. This display
* exists on most Cavium evaluation boards. If it doesn't exist, then
@@ -346,8 +356,18 @@ void octeon_user_io_init(void)
cvmmemctl.s.wbfltime = 0;
/* R/W If set, do not put Istream in the L2 cache. */
cvmmemctl.s.istrnol2 = 0;
- /* R/W The write buffer threshold. */
- cvmmemctl.s.wbthresh = 10;
+
+ /*
+ * R/W The write buffer threshold. As per erratum Core-14752
+ * for CN63XX, a sc/scd might fail if the write buffer is
+ * full. Lowering WBTHRESH greatly lowers the chances of the
+ * write buffer ever being full and triggering the erratum.
+ */
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+ cvmmemctl.s.wbthresh = 4;
+ else
+ cvmmemctl.s.wbthresh = 10;
+
/* R/W If set, CVMSEG is available for loads/stores in
* kernel/debug mode. */
#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
@@ -365,14 +385,13 @@ void octeon_user_io_init(void)
* is max legal value. */
cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
+ write_c0_cvmmemctl(cvmmemctl.u64);
if (smp_processor_id() == 0)
pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
- write_c0_cvmmemctl(cvmmemctl.u64);
-
/* Move the performance counter interrupts to IRQ 6 */
cvmctl = read_c0_cvmctl();
cvmctl &= ~(7 << 7);
@@ -416,6 +435,41 @@ void __init prom_init(void)
cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
+ sysinfo = cvmx_sysinfo_get();
+ memset(sysinfo, 0, sizeof(*sysinfo));
+ sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
+ sysinfo->phy_mem_desc_ptr =
+ cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
+ sysinfo->core_mask = octeon_bootinfo->core_mask;
+ sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
+ sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
+ sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
+ sysinfo->board_type = octeon_bootinfo->board_type;
+ sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
+ sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
+ memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
+ sizeof(sysinfo->mac_addr_base));
+ sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
+ memcpy(sysinfo->board_serial_number,
+ octeon_bootinfo->board_serial_number,
+ sizeof(sysinfo->board_serial_number));
+ sysinfo->compact_flash_common_base_addr =
+ octeon_bootinfo->compact_flash_common_base_addr;
+ sysinfo->compact_flash_attribute_base_addr =
+ octeon_bootinfo->compact_flash_attribute_base_addr;
+ sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
+ sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
+ sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
+
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+ /* I/O clock runs at a different rate than the CPU. */
+ union cvmx_mio_rst_boot rst_boot;
+ rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
+ octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
+ } else {
+ octeon_io_clock_rate = sysinfo->cpu_clock_hz;
+ }
+
/*
* Only enable the LED controller if we're running on a CN38XX, CN58XX,
* or CN56XX. The CN30XX and CN31XX don't have an LED controller.
@@ -479,33 +533,6 @@ void __init prom_init(void)
}
#endif
- sysinfo = cvmx_sysinfo_get();
- memset(sysinfo, 0, sizeof(*sysinfo));
- sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
- sysinfo->phy_mem_desc_ptr =
- cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
- sysinfo->core_mask = octeon_bootinfo->core_mask;
- sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
- sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
- sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
- sysinfo->board_type = octeon_bootinfo->board_type;
- sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
- sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
- memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
- sizeof(sysinfo->mac_addr_base));
- sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
- memcpy(sysinfo->board_serial_number,
- octeon_bootinfo->board_serial_number,
- sizeof(sysinfo->board_serial_number));
- sysinfo->compact_flash_common_base_addr =
- octeon_bootinfo->compact_flash_common_base_addr;
- sysinfo->compact_flash_attribute_base_addr =
- octeon_bootinfo->compact_flash_attribute_base_addr;
- sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
- sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
- sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
-
-
octeon_check_cpu_bist();
octeon_uart = octeon_get_boot_uart();
@@ -740,6 +767,31 @@ EXPORT_SYMBOL(prom_putchar);
void prom_free_prom_memory(void)
{
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) {
+ /* Check for presence of Core-14449 fix. */
+ u32 insn;
+ u32 *foo;
+
+ foo = &insn;
+
+ asm volatile("# before" : : : "memory");
+ prefetch(foo);
+ asm volatile(
+ ".set push\n\t"
+ ".set noreorder\n\t"
+ "bal 1f\n\t"
+ "nop\n"
+ "1:\tlw %0,-12($31)\n\t"
+ ".set pop\n\t"
+ : "=r" (insn) : : "$31", "memory");
+
+ if ((insn >> 26) != 0x33)
+ panic("No PREF instruction at Core-14449 probe point.\n");
+
+ if (((insn >> 16) & 0x1f) != 28)
+ panic("Core-14449 WAR not in place (%04x).\n"
+ "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).\n", insn);
+ }
#ifdef CONFIG_CAVIUM_DECODE_RSL
cvmx_interrupt_rsl_enable();
diff --git a/trunk/arch/mips/include/asm/atomic.h b/trunk/arch/mips/include/asm/atomic.h
index 47d87da379f9..4a02fe891ab6 100644
--- a/trunk/arch/mips/include/asm/atomic.h
+++ b/trunk/arch/mips/include/asm/atomic.h
@@ -64,18 +64,16 @@ static __inline__ void atomic_add(int i, atomic_t * v)
} else if (kernel_uses_llsc) {
int temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %0, %1 # atomic_add \n"
- " addu %0, %2 \n"
- " sc %0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " ll %0, %1 # atomic_add \n"
+ " addu %0, %2 \n"
+ " sc %0, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter));
+ } while (unlikely(!temp));
} else {
unsigned long flags;
@@ -109,18 +107,16 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
} else if (kernel_uses_llsc) {
int temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %0, %1 # atomic_sub \n"
- " subu %0, %2 \n"
- " sc %0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " ll %0, %1 # atomic_sub \n"
+ " subu %0, %2 \n"
+ " sc %0, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter));
+ } while (unlikely(!temp));
} else {
unsigned long flags;
@@ -156,20 +152,19 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
} else if (kernel_uses_llsc) {
int temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %1, %2 # atomic_add_return \n"
- " addu %0, %1, %3 \n"
- " sc %0, %2 \n"
- " beqz %0, 2f \n"
- " addu %0, %1, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " ll %1, %2 # atomic_add_return \n"
+ " addu %0, %1, %3 \n"
+ " sc %0, %2 \n"
+ " .set mips0 \n"
+ : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter)
+ : "memory");
+ } while (unlikely(!result));
+
+ result = temp + i;
} else {
unsigned long flags;
@@ -205,23 +200,24 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
+
+ result = temp - i;
} else if (kernel_uses_llsc) {
int temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %1, %2 # atomic_sub_return \n"
- " subu %0, %1, %3 \n"
- " sc %0, %2 \n"
- " beqz %0, 2f \n"
- " subu %0, %1, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " ll %1, %2 # atomic_sub_return \n"
+ " subu %0, %1, %3 \n"
+ " sc %0, %2 \n"
+ " .set mips0 \n"
+ : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter)
+ : "memory");
+ } while (unlikely(!result));
+
+ result = temp - i;
} else {
unsigned long flags;
@@ -279,12 +275,9 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
" bltz %0, 1f \n"
" sc %0, %2 \n"
" .set noreorder \n"
- " beqz %0, 2f \n"
+ " beqz %0, 1b \n"
" subu %0, %1, %3 \n"
" .set reorder \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
"1: \n"
" .set mips0 \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
@@ -443,18 +436,16 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
} else if (kernel_uses_llsc) {
long temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %0, %1 # atomic64_add \n"
- " daddu %0, %2 \n"
- " scd %0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " lld %0, %1 # atomic64_add \n"
+ " daddu %0, %2 \n"
+ " scd %0, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter));
+ } while (unlikely(!temp));
} else {
unsigned long flags;
@@ -488,18 +479,16 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
} else if (kernel_uses_llsc) {
long temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %0, %1 # atomic64_sub \n"
- " dsubu %0, %2 \n"
- " scd %0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " lld %0, %1 # atomic64_sub \n"
+ " dsubu %0, %2 \n"
+ " scd %0, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter));
+ } while (unlikely(!temp));
} else {
unsigned long flags;
@@ -535,20 +524,19 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
} else if (kernel_uses_llsc) {
long temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %1, %2 # atomic64_add_return \n"
- " daddu %0, %1, %3 \n"
- " scd %0, %2 \n"
- " beqz %0, 2f \n"
- " daddu %0, %1, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " lld %1, %2 # atomic64_add_return \n"
+ " daddu %0, %1, %3 \n"
+ " scd %0, %2 \n"
+ " .set mips0 \n"
+ : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter)
+ : "memory");
+ } while (unlikely(!result));
+
+ result = temp + i;
} else {
unsigned long flags;
@@ -587,20 +575,19 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
} else if (kernel_uses_llsc) {
long temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %1, %2 # atomic64_sub_return \n"
- " dsubu %0, %1, %3 \n"
- " scd %0, %2 \n"
- " beqz %0, 2f \n"
- " dsubu %0, %1, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " lld %1, %2 # atomic64_sub_return \n"
+ " dsubu %0, %1, %3 \n"
+ " scd %0, %2 \n"
+ " .set mips0 \n"
+ : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter)
+ : "memory");
+ } while (unlikely(!result));
+
+ result = temp - i;
} else {
unsigned long flags;
@@ -658,12 +645,9 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
" bltz %0, 1f \n"
" scd %0, %2 \n"
" .set noreorder \n"
- " beqz %0, 2f \n"
+ " beqz %0, 1b \n"
" dsubu %0, %1, %3 \n"
" .set reorder \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
"1: \n"
" .set mips0 \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
diff --git a/trunk/arch/mips/include/asm/bitops.h b/trunk/arch/mips/include/asm/bitops.h
index b0ce7ca2851f..50b4ef288c53 100644
--- a/trunk/arch/mips/include/asm/bitops.h
+++ b/trunk/arch/mips/include/asm/bitops.h
@@ -73,30 +73,26 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
: "ir" (1UL << bit), "m" (*m));
#ifdef CONFIG_CPU_MIPSR2
} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
- __asm__ __volatile__(
- "1: " __LL "%0, %1 # set_bit \n"
- " " __INS "%0, %4, %2, 1 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (bit), "m" (*m), "r" (~0));
+ do {
+ __asm__ __volatile__(
+ " " __LL "%0, %1 # set_bit \n"
+ " " __INS "%0, %3, %2, 1 \n"
+ " " __SC "%0, %1 \n"
+ : "=&r" (temp), "+m" (*m)
+ : "ir" (bit), "r" (~0));
+ } while (unlikely(!temp));
#endif /* CONFIG_CPU_MIPSR2 */
} else if (kernel_uses_llsc) {
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: " __LL "%0, %1 # set_bit \n"
- " or %0, %2 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (1UL << bit), "m" (*m));
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " " __LL "%0, %1 # set_bit \n"
+ " or %0, %2 \n"
+ " " __SC "%0, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "+m" (*m)
+ : "ir" (1UL << bit));
+ } while (unlikely(!temp));
} else {
volatile unsigned long *a = addr;
unsigned long mask;
@@ -134,34 +130,30 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
" " __SC "%0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (~(1UL << bit)), "m" (*m));
+ : "=&r" (temp), "+m" (*m)
+ : "ir" (~(1UL << bit)));
#ifdef CONFIG_CPU_MIPSR2
} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
- __asm__ __volatile__(
- "1: " __LL "%0, %1 # clear_bit \n"
- " " __INS "%0, $0, %2, 1 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (bit), "m" (*m));
+ do {
+ __asm__ __volatile__(
+ " " __LL "%0, %1 # clear_bit \n"
+ " " __INS "%0, $0, %2, 1 \n"
+ " " __SC "%0, %1 \n"
+ : "=&r" (temp), "+m" (*m)
+ : "ir" (bit));
+ } while (unlikely(!temp));
#endif /* CONFIG_CPU_MIPSR2 */
} else if (kernel_uses_llsc) {
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: " __LL "%0, %1 # clear_bit \n"
- " and %0, %2 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (~(1UL << bit)), "m" (*m));
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " " __LL "%0, %1 # clear_bit \n"
+ " and %0, %2 \n"
+ " " __SC "%0, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "+m" (*m)
+ : "ir" (~(1UL << bit)));
+ } while (unlikely(!temp));
} else {
volatile unsigned long *a = addr;
unsigned long mask;
@@ -213,24 +205,22 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
" " __SC "%0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (1UL << bit), "m" (*m));
+ : "=&r" (temp), "+m" (*m)
+ : "ir" (1UL << bit));
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: " __LL "%0, %1 # change_bit \n"
- " xor %0, %2 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (1UL << bit), "m" (*m));
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " " __LL "%0, %1 # change_bit \n"
+ " xor %0, %2 \n"
+ " " __SC "%0, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "+m" (*m)
+ : "ir" (1UL << bit));
+ } while (unlikely(!temp));
} else {
volatile unsigned long *a = addr;
unsigned long mask;
@@ -272,30 +262,26 @@ static inline int test_and_set_bit(unsigned long nr,
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "r" (1UL << bit)
: "memory");
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
- __asm__ __volatile__(
- " .set push \n"
- " .set noreorder \n"
- " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_set_bit \n"
- " or %2, %0, %3 \n"
- " " __SC "%2, %1 \n"
- " beqz %2, 2f \n"
- " and %2, %0, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " nop \n"
- " .previous \n"
- " .set pop \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " " __LL "%0, %1 # test_and_set_bit \n"
+ " or %2, %0, %3 \n"
+ " " __SC "%2, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "r" (1UL << bit)
+ : "memory");
+ } while (unlikely(!res));
+
+ res = temp & (1UL << bit);
} else {
volatile unsigned long *a = addr;
unsigned long mask;
@@ -340,30 +326,26 @@ static inline int test_and_set_bit_lock(unsigned long nr,
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "r" (1UL << bit)
: "memory");
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
- __asm__ __volatile__(
- " .set push \n"
- " .set noreorder \n"
- " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_set_bit \n"
- " or %2, %0, %3 \n"
- " " __SC "%2, %1 \n"
- " beqz %2, 2f \n"
- " and %2, %0, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " nop \n"
- " .previous \n"
- " .set pop \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " " __LL "%0, %1 # test_and_set_bit \n"
+ " or %2, %0, %3 \n"
+ " " __SC "%2, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "r" (1UL << bit)
+ : "memory");
+ } while (unlikely(!res));
+
+ res = temp & (1UL << bit);
} else {
volatile unsigned long *a = addr;
unsigned long mask;
@@ -410,49 +392,43 @@ static inline int test_and_clear_bit(unsigned long nr,
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "r" (1UL << bit)
: "memory");
#ifdef CONFIG_CPU_MIPSR2
} else if (kernel_uses_llsc && __builtin_constant_p(nr)) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
- __asm__ __volatile__(
- "1: " __LL "%0, %1 # test_and_clear_bit \n"
- " " __EXT "%2, %0, %3, 1 \n"
- " " __INS "%0, $0, %3, 1 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "ir" (bit), "m" (*m)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " " __LL "%0, %1 # test_and_clear_bit \n"
+ " " __EXT "%2, %0, %3, 1 \n"
+ " " __INS "%0, $0, %3, 1 \n"
+ " " __SC "%0, %1 \n"
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "ir" (bit)
+ : "memory");
+ } while (unlikely(!temp));
#endif
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
- __asm__ __volatile__(
- " .set push \n"
- " .set noreorder \n"
- " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_clear_bit \n"
- " or %2, %0, %3 \n"
- " xor %2, %3 \n"
- " " __SC "%2, %1 \n"
- " beqz %2, 2f \n"
- " and %2, %0, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " nop \n"
- " .previous \n"
- " .set pop \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " " __LL "%0, %1 # test_and_clear_bit \n"
+ " or %2, %0, %3 \n"
+ " xor %2, %3 \n"
+ " " __SC "%2, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "r" (1UL << bit)
+ : "memory");
+ } while (unlikely(!res));
+
+ res = temp & (1UL << bit);
} else {
volatile unsigned long *a = addr;
unsigned long mask;
@@ -499,30 +475,26 @@ static inline int test_and_change_bit(unsigned long nr,
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "r" (1UL << bit)
: "memory");
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
- __asm__ __volatile__(
- " .set push \n"
- " .set noreorder \n"
- " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_change_bit \n"
- " xor %2, %0, %3 \n"
- " " __SC "\t%2, %1 \n"
- " beqz %2, 2f \n"
- " and %2, %0, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " nop \n"
- " .previous \n"
- " .set pop \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " " __LL "%0, %1 # test_and_change_bit \n"
+ " xor %2, %0, %3 \n"
+ " " __SC "\t%2, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "r" (1UL << bit)
+ : "memory");
+ } while (unlikely(!res));
+
+ res = temp & (1UL << bit);
} else {
volatile unsigned long *a = addr;
unsigned long mask;
diff --git a/trunk/arch/mips/include/asm/bootinfo.h b/trunk/arch/mips/include/asm/bootinfo.h
index 15a8ef0707c6..35cd1bab69c3 100644
--- a/trunk/arch/mips/include/asm/bootinfo.h
+++ b/trunk/arch/mips/include/asm/bootinfo.h
@@ -125,4 +125,16 @@ extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
*/
extern void plat_mem_setup(void);
+#ifdef CONFIG_SWIOTLB
+/*
+ * Optional platform hook to call swiotlb_setup().
+ */
+extern void plat_swiotlb_setup(void);
+
+#else
+
+static inline void plat_swiotlb_setup(void) {}
+
+#endif /* CONFIG_SWIOTLB */
+
#endif /* _ASM_BOOTINFO_H */
diff --git a/trunk/arch/mips/include/asm/cmpxchg.h b/trunk/arch/mips/include/asm/cmpxchg.h
index 2d28017e95d0..d8d1c2805ac7 100644
--- a/trunk/arch/mips/include/asm/cmpxchg.h
+++ b/trunk/arch/mips/include/asm/cmpxchg.h
@@ -44,12 +44,9 @@
" move $1, %z4 \n" \
" .set mips3 \n" \
" " st " $1, %1 \n" \
- " beqz $1, 3f \n" \
- "2: \n" \
- " .subsection 2 \n" \
- "3: b 1b \n" \
- " .previous \n" \
+ " beqz $1, 1b \n" \
" .set pop \n" \
+ "2: \n" \
: "=&r" (__ret), "=R" (*m) \
: "R" (*m), "Jr" (old), "Jr" (new) \
: "memory"); \
diff --git a/trunk/arch/mips/include/asm/cpu.h b/trunk/arch/mips/include/asm/cpu.h
index b201a8f5b127..06d59dcbe243 100644
--- a/trunk/arch/mips/include/asm/cpu.h
+++ b/trunk/arch/mips/include/asm/cpu.h
@@ -111,14 +111,16 @@
* These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
*/
-#define PRID_IMP_BCM4710 0x4000
-#define PRID_IMP_BCM3302 0x9000
-#define PRID_IMP_BCM6338 0x9000
-#define PRID_IMP_BCM6345 0x8000
-#define PRID_IMP_BCM6348 0x9100
-#define PRID_IMP_BCM4350 0xA000
-#define PRID_REV_BCM6358 0x0010
-#define PRID_REV_BCM6368 0x0030
+#define PRID_IMP_BMIPS4KC 0x4000
+#define PRID_IMP_BMIPS32 0x8000
+#define PRID_IMP_BMIPS3300 0x9000
+#define PRID_IMP_BMIPS3300_ALT 0x9100
+#define PRID_IMP_BMIPS3300_BUG 0x0000
+#define PRID_IMP_BMIPS43XX 0xa000
+#define PRID_IMP_BMIPS5000 0x5a00
+
+#define PRID_REV_BMIPS4380_LO 0x0040
+#define PRID_REV_BMIPS4380_HI 0x006f
/*
* These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
@@ -131,6 +133,7 @@
#define PRID_IMP_CAVIUM_CN56XX 0x0400
#define PRID_IMP_CAVIUM_CN50XX 0x0600
#define PRID_IMP_CAVIUM_CN52XX 0x0700
+#define PRID_IMP_CAVIUM_CN63XX 0x9000
/*
* These are the PRID's for when 23:16 == PRID_COMP_INGENIC
@@ -223,15 +226,14 @@ enum cpu_type_enum {
* MIPS32 class processors
*/
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
- CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
- CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
- CPU_JZRISC,
+ CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
+ CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC,
/*
* MIPS64 class processors
*/
CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
- CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
+ CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
CPU_LAST
};
diff --git a/trunk/arch/mips/include/asm/device.h b/trunk/arch/mips/include/asm/device.h
index 06746c5e8099..c94fafba9e62 100644
--- a/trunk/arch/mips/include/asm/device.h
+++ b/trunk/arch/mips/include/asm/device.h
@@ -3,4 +3,17 @@
*
* This file is released under the GPLv2
*/
-#include
+#ifndef _ASM_MIPS_DEVICE_H
+#define _ASM_MIPS_DEVICE_H
+
+struct dma_map_ops;
+
+struct dev_archdata {
+ /* DMA operations on that device */
+ struct dma_map_ops *dma_ops;
+};
+
+struct pdev_archdata {
+};
+
+#endif /* _ASM_MIPS_DEVICE_H*/
diff --git a/trunk/arch/mips/include/asm/dma-mapping.h b/trunk/arch/mips/include/asm/dma-mapping.h
index 18fbf7af8e93..655f849bd08d 100644
--- a/trunk/arch/mips/include/asm/dma-mapping.h
+++ b/trunk/arch/mips/include/asm/dma-mapping.h
@@ -5,51 +5,41 @@
#include
#include
-void *dma_alloc_noncoherent(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t flag);
+#include
-void dma_free_noncoherent(struct device *dev, size_t size,
- void *vaddr, dma_addr_t dma_handle);
+extern struct dma_map_ops *mips_dma_map_ops;
-void *dma_alloc_coherent(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t flag);
+static inline struct dma_map_ops *get_dma_ops(struct device *dev)
+{
+ if (dev && dev->archdata.dma_ops)
+ return dev->archdata.dma_ops;
+ else
+ return mips_dma_map_ops;
+}
-void dma_free_coherent(struct device *dev, size_t size,
- void *vaddr, dma_addr_t dma_handle);
+static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
+{
+ if (!dev->dma_mask)
+ return 0;
-extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
- enum dma_data_direction direction);
-extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
- size_t size, enum dma_data_direction direction);
-extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
- enum dma_data_direction direction);
-extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size, enum dma_data_direction direction);
-
-static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
- size_t size, enum dma_data_direction direction)
+ return addr + size <= *dev->dma_mask;
+}
+
+static inline void dma_mark_clean(void *addr, size_t size) {}
+
+#include
+
+static inline int dma_supported(struct device *dev, u64 mask)
{
- dma_unmap_single(dev, dma_address, size, direction);
+ struct dma_map_ops *ops = get_dma_ops(dev);
+ return ops->dma_supported(dev, mask);
}
-extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
- int nhwentries, enum dma_data_direction direction);
-extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
- size_t size, enum dma_data_direction direction);
-extern void dma_sync_single_for_device(struct device *dev,
- dma_addr_t dma_handle, size_t size, enum dma_data_direction direction);
-extern void dma_sync_single_range_for_cpu(struct device *dev,
- dma_addr_t dma_handle, unsigned long offset, size_t size,
- enum dma_data_direction direction);
-extern void dma_sync_single_range_for_device(struct device *dev,
- dma_addr_t dma_handle, unsigned long offset, size_t size,
- enum dma_data_direction direction);
-extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
- int nelems, enum dma_data_direction direction);
-extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
- int nelems, enum dma_data_direction direction);
-extern int dma_mapping_error(struct device *dev, dma_addr_t dma_addr);
-extern int dma_supported(struct device *dev, u64 mask);
+static inline int dma_mapping_error(struct device *dev, u64 mask)
+{
+ struct dma_map_ops *ops = get_dma_ops(dev);
+ return ops->mapping_error(dev, mask);
+}
static inline int
dma_set_mask(struct device *dev, u64 mask)
@@ -65,4 +55,34 @@ dma_set_mask(struct device *dev, u64 mask)
extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
enum dma_data_direction direction);
+static inline void *dma_alloc_coherent(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t gfp)
+{
+ void *ret;
+ struct dma_map_ops *ops = get_dma_ops(dev);
+
+ ret = ops->alloc_coherent(dev, size, dma_handle, gfp);
+
+ debug_dma_alloc_coherent(dev, size, *dma_handle, ret);
+
+ return ret;
+}
+
+static inline void dma_free_coherent(struct device *dev, size_t size,
+ void *vaddr, dma_addr_t dma_handle)
+{
+ struct dma_map_ops *ops = get_dma_ops(dev);
+
+ ops->free_coherent(dev, size, vaddr, dma_handle);
+
+ debug_dma_free_coherent(dev, size, vaddr, dma_handle);
+}
+
+
+void *dma_alloc_noncoherent(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t flag);
+
+void dma_free_noncoherent(struct device *dev, size_t size,
+ void *vaddr, dma_addr_t dma_handle);
+
#endif /* _ASM_DMA_MAPPING_H */
diff --git a/trunk/arch/mips/include/asm/dma.h b/trunk/arch/mips/include/asm/dma.h
index 1353c81065d1..2d47da62d5a7 100644
--- a/trunk/arch/mips/include/asm/dma.h
+++ b/trunk/arch/mips/include/asm/dma.h
@@ -91,7 +91,10 @@
#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000)
#endif
#define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
+
+#ifndef MAX_DMA32_PFN
#define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
+#endif
/* 8237 DMA controllers */
#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
diff --git a/trunk/arch/mips/include/asm/local.h b/trunk/arch/mips/include/asm/local.h
index bdcdef02d147..fffc8307a80a 100644
--- a/trunk/arch/mips/include/asm/local.h
+++ b/trunk/arch/mips/include/asm/local.h
@@ -117,7 +117,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
#define local_cmpxchg(l, o, n) \
((long)cmpxchg_local(&((l)->a.counter), (o), (n)))
-#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
+#define local_xchg(l, n) (atomic_long_xchg((&(l)->a), (n)))
/**
* local_add_unless - add unless the number is a given value
diff --git a/trunk/arch/mips/include/asm/mach-ar7/ar7.h b/trunk/arch/mips/include/asm/mach-ar7/ar7.h
index 483ffea9ecb1..7919d76186bf 100644
--- a/trunk/arch/mips/include/asm/mach-ar7/ar7.h
+++ b/trunk/arch/mips/include/asm/mach-ar7/ar7.h
@@ -39,6 +39,7 @@
#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
+#define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C)
#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00)
#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
@@ -50,6 +51,14 @@
#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
+/* Titan registers */
+#define TITAN_REGS_ESWITCH_BASE (0x08640000)
+#define TITAN_REGS_MAC0 (TITAN_REGS_ESWITCH_BASE)
+#define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800)
+#define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000)
+#define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00)
+#define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300)
+
#define AR7_RESET_PERIPHERAL 0x0
#define AR7_RESET_SOFTWARE 0x4
#define AR7_RESET_STATUS 0x8
@@ -59,15 +68,30 @@
#define AR7_RESET_BIT_MDIO 22
#define AR7_RESET_BIT_EPHY 26
+#define TITAN_RESET_BIT_EPHY1 28
+
/* GPIO control registers */
#define AR7_GPIO_INPUT 0x0
#define AR7_GPIO_OUTPUT 0x4
#define AR7_GPIO_DIR 0x8
#define AR7_GPIO_ENABLE 0xc
+#define TITAN_GPIO_INPUT_0 0x0
+#define TITAN_GPIO_INPUT_1 0x4
+#define TITAN_GPIO_OUTPUT_0 0x8
+#define TITAN_GPIO_OUTPUT_1 0xc
+#define TITAN_GPIO_DIR_0 0x10
+#define TITAN_GPIO_DIR_1 0x14
+#define TITAN_GPIO_ENBL_0 0x18
+#define TITAN_GPIO_ENBL_1 0x1c
#define AR7_CHIP_7100 0x18
#define AR7_CHIP_7200 0x2b
#define AR7_CHIP_7300 0x05
+#define AR7_CHIP_TITAN 0x07
+#define TITAN_CHIP_1050 0x0f
+#define TITAN_CHIP_1055 0x0e
+#define TITAN_CHIP_1056 0x0d
+#define TITAN_CHIP_1060 0x07
/* Interrupts */
#define AR7_IRQ_UART0 15
@@ -95,14 +119,29 @@ struct plat_dsl_data {
extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
+static inline int ar7_is_titan(void)
+{
+ return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
+ AR7_CHIP_TITAN;
+}
+
static inline u16 ar7_chip_id(void)
{
- return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
+ return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
+ KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
+}
+
+static inline u16 titan_chip_id(void)
+{
+ unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO +
+ TITAN_GPIO_INPUT_1));
+ return ((val >> 12) & 0x0f);
}
static inline u8 ar7_chip_rev(void)
{
- return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
+ return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
+ 0x14))) >> 16) & 0xff;
}
struct clk {
@@ -161,4 +200,8 @@ static inline void ar7_device_off(u32 bit)
msleep(20);
}
+int __init ar7_gpio_init(void);
+
+int __init ar7_gpio_init(void);
+
#endif /* __AR7_H__ */
diff --git a/trunk/arch/mips/include/asm/mach-ar7/gpio.h b/trunk/arch/mips/include/asm/mach-ar7/gpio.h
index abc317c0372e..c177cd1eed25 100644
--- a/trunk/arch/mips/include/asm/mach-ar7/gpio.h
+++ b/trunk/arch/mips/include/asm/mach-ar7/gpio.h
@@ -22,7 +22,8 @@
#include
#define AR7_GPIO_MAX 32
-#define NR_BUILTIN_GPIO AR7_GPIO_MAX
+#define TITAN_GPIO_MAX 51
+#define NR_BUILTIN_GPIO TITAN_GPIO_MAX
#define gpio_to_irq(gpio) -1
diff --git a/trunk/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/trunk/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index b952fc7215e2..0d5a42b5f47a 100644
--- a/trunk/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/trunk/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -59,7 +59,7 @@
#define cpu_has_veic 0
#define cpu_hwrena_impl_bits 0xc0000000
-#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
+#define kernel_uses_smartmips_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
#define ARCH_HAS_IRQ_PER_CPU 1
#define ARCH_HAS_SPINLOCK_PREFETCH 1
@@ -81,4 +81,10 @@ static inline int octeon_has_saa(void)
return id >= 0x000d0300;
}
+/*
+ * The last 256MB are reserved for device to device mappings and the
+ * BAR1 hole.
+ */
+#define MAX_DMA32_PFN (((1ULL << 32) - (1ULL << 28)) >> PAGE_SHIFT)
+
#endif
diff --git a/trunk/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/trunk/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
index 17d579471ec4..be8fb4240cec 100644
--- a/trunk/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
+++ b/trunk/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -15,41 +15,40 @@
struct device;
-dma_addr_t octeon_map_dma_mem(struct device *, void *, size_t);
-void octeon_unmap_dma_mem(struct device *, dma_addr_t);
+extern void octeon_pci_dma_init(void);
static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
size_t size)
{
- return octeon_map_dma_mem(dev, addr, size);
+ BUG();
}
static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
struct page *page)
{
- return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE);
+ BUG();
}
static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
- return dma_addr;
+ BUG();
}
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{
- octeon_unmap_dma_mem(dev, dma_addr);
+ BUG();
}
static inline int plat_dma_supported(struct device *dev, u64 mask)
{
- return 1;
+ BUG();
}
static inline void plat_extra_sync_for_device(struct device *dev)
{
- mb();
+ BUG();
}
static inline int plat_device_is_coherent(struct device *dev)
@@ -60,7 +59,14 @@ static inline int plat_device_is_coherent(struct device *dev)
static inline int plat_dma_mapping_error(struct device *dev,
dma_addr_t dma_addr)
{
- return dma_addr == -1;
+ BUG();
}
+dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
+phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
+
+struct dma_map_ops;
+extern struct dma_map_ops *octeon_pci_dma_map_ops;
+extern char *octeon_swiotlb;
+
#endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */
diff --git a/trunk/arch/mips/include/asm/mach-ip27/dma-coherence.h b/trunk/arch/mips/include/asm/mach-ip27/dma-coherence.h
index d3d04018a858..016d0989b141 100644
--- a/trunk/arch/mips/include/asm/mach-ip27/dma-coherence.h
+++ b/trunk/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -26,14 +26,15 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
return pa;
}
-static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+ struct page *page)
{
dma_addr_t pa = dev_to_baddr(dev, page_to_phys(page));
return pa;
}
-static unsigned long plat_dma_addr_to_phys(struct device *dev,
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
return dma_addr & ~(0xffUL << 56);
diff --git a/trunk/arch/mips/include/asm/mach-ip32/dma-coherence.h b/trunk/arch/mips/include/asm/mach-ip32/dma-coherence.h
index 37855955b313..c8fb5aacf50a 100644
--- a/trunk/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/trunk/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -37,7 +37,8 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
return pa;
}
-static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+ struct page *page)
{
dma_addr_t pa;
@@ -50,7 +51,7 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
}
/* This is almost certainly wrong but it's what dma-ip32.c used to use */
-static unsigned long plat_dma_addr_to_phys(struct device *dev,
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
unsigned long addr = dma_addr & RAM_OFFSET_MASK;
diff --git a/trunk/arch/mips/include/asm/mach-jazz/dma-coherence.h b/trunk/arch/mips/include/asm/mach-jazz/dma-coherence.h
index f93aee59454a..302101b54acb 100644
--- a/trunk/arch/mips/include/asm/mach-jazz/dma-coherence.h
+++ b/trunk/arch/mips/include/asm/mach-jazz/dma-coherence.h
@@ -12,23 +12,24 @@
struct device;
-static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
{
return vdma_alloc(virt_to_phys(addr), size);
}
-static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+ struct page *page)
{
return vdma_alloc(page_to_phys(page), PAGE_SIZE);
}
-static unsigned long plat_dma_addr_to_phys(struct device *dev,
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
return vdma_log2phys(dma_addr);
}
-static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{
vdma_free(dma_addr);
diff --git a/trunk/arch/mips/include/asm/mipsregs.h b/trunk/arch/mips/include/asm/mipsregs.h
index 335474c155f6..4d9870975382 100644
--- a/trunk/arch/mips/include/asm/mipsregs.h
+++ b/trunk/arch/mips/include/asm/mipsregs.h
@@ -1040,6 +1040,12 @@ do { \
#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
+#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
+#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
+
+#define read_c0_staglo() __read_32bit_c0_register($28, 4)
+#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
+
#define read_c0_taghi() __read_32bit_c0_register($29, 0)
#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
@@ -1082,6 +1088,51 @@ do { \
#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
+/* BMIPS3300 */
+#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
+#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
+
+/* BMIPS4380 */
+#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
+#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
+#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
+#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
+#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
+
+#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
+#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
+
+/* BMIPS5000 */
+#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
+#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
+#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
+#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
+#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
+
/*
* Macros to access the floating point coprocessor control registers
*/
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-agl-defs.h
index ec94b9ab7be1..30d68f2365e0 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-agl-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-agl-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,152 +28,100 @@
#ifndef __CVMX_AGL_DEFS_H__
#define __CVMX_AGL_DEFS_H__
-#define CVMX_AGL_GMX_BAD_REG \
- CVMX_ADD_IO_SEG(0x00011800E0000518ull)
-#define CVMX_AGL_GMX_BIST \
- CVMX_ADD_IO_SEG(0x00011800E0000400ull)
-#define CVMX_AGL_GMX_DRV_CTL \
- CVMX_ADD_IO_SEG(0x00011800E00007F0ull)
-#define CVMX_AGL_GMX_INF_MODE \
- CVMX_ADD_IO_SEG(0x00011800E00007F8ull)
-#define CVMX_AGL_GMX_PRTX_CFG(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000010ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000180ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000188ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000190ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000198ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00001A0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00001A8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000108ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000100ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_DECISION(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000040ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000020ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000018ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000030ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000028ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_IFG(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000058ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_INT_EN(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000008ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_INT_REG(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000000ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_JABBER(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000038ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000068ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000050ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000088ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000098ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00000A8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00000B8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000080ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00000C0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000090ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00000A0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00000B0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000048ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RX_BP_DROPX(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000420ull + (((offset) & 1) * 8))
-#define CVMX_AGL_GMX_RX_BP_OFFX(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000460ull + (((offset) & 1) * 8))
-#define CVMX_AGL_GMX_RX_BP_ONX(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000440ull + (((offset) & 1) * 8))
-#define CVMX_AGL_GMX_RX_PRT_INFO \
- CVMX_ADD_IO_SEG(0x00011800E00004E8ull)
-#define CVMX_AGL_GMX_RX_TX_STATUS \
- CVMX_ADD_IO_SEG(0x00011800E00007E8ull)
-#define CVMX_AGL_GMX_SMACX(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000230ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_STAT_BP \
- CVMX_ADD_IO_SEG(0x00011800E0000520ull)
-#define CVMX_AGL_GMX_TXX_APPEND(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000218ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_CTL(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000270ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000240ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000248ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000238ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000258ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000260ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000250ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT0(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000280ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT1(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000288ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT2(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000290ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT3(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000298ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT4(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00002A0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT5(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00002A8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT6(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00002B0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT7(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00002B8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT8(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00002C0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT9(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00002C8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000268ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_THRESH(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000210ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TX_BP \
- CVMX_ADD_IO_SEG(0x00011800E00004D0ull)
-#define CVMX_AGL_GMX_TX_COL_ATTEMPT \
- CVMX_ADD_IO_SEG(0x00011800E0000498ull)
-#define CVMX_AGL_GMX_TX_IFG \
- CVMX_ADD_IO_SEG(0x00011800E0000488ull)
-#define CVMX_AGL_GMX_TX_INT_EN \
- CVMX_ADD_IO_SEG(0x00011800E0000508ull)
-#define CVMX_AGL_GMX_TX_INT_REG \
- CVMX_ADD_IO_SEG(0x00011800E0000500ull)
-#define CVMX_AGL_GMX_TX_JAM \
- CVMX_ADD_IO_SEG(0x00011800E0000490ull)
-#define CVMX_AGL_GMX_TX_LFSR \
- CVMX_ADD_IO_SEG(0x00011800E00004F8ull)
-#define CVMX_AGL_GMX_TX_OVR_BP \
- CVMX_ADD_IO_SEG(0x00011800E00004C8ull)
-#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC \
- CVMX_ADD_IO_SEG(0x00011800E00004A0ull)
-#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE \
- CVMX_ADD_IO_SEG(0x00011800E00004A8ull)
+#define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull))
+#define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull))
+#define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull))
+#define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull))
+#define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_DECISION(offset) (CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_IFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_INT_REG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_RX_INBND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RX_BP_DROPX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8)
+#define CVMX_AGL_GMX_RX_BP_OFFX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8)
+#define CVMX_AGL_GMX_RX_BP_ONX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8)
+#define CVMX_AGL_GMX_RX_PRT_INFO (CVMX_ADD_IO_SEG(0x00011800E00004E8ull))
+#define CVMX_AGL_GMX_RX_TX_STATUS (CVMX_ADD_IO_SEG(0x00011800E00007E8ull))
+#define CVMX_AGL_GMX_SMACX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_STAT_BP (CVMX_ADD_IO_SEG(0x00011800E0000520ull))
+#define CVMX_AGL_GMX_TXX_APPEND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_CLK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) (CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) (CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_THRESH(offset) (CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TX_BP (CVMX_ADD_IO_SEG(0x00011800E00004D0ull))
+#define CVMX_AGL_GMX_TX_COL_ATTEMPT (CVMX_ADD_IO_SEG(0x00011800E0000498ull))
+#define CVMX_AGL_GMX_TX_IFG (CVMX_ADD_IO_SEG(0x00011800E0000488ull))
+#define CVMX_AGL_GMX_TX_INT_EN (CVMX_ADD_IO_SEG(0x00011800E0000508ull))
+#define CVMX_AGL_GMX_TX_INT_REG (CVMX_ADD_IO_SEG(0x00011800E0000500ull))
+#define CVMX_AGL_GMX_TX_JAM (CVMX_ADD_IO_SEG(0x00011800E0000490ull))
+#define CVMX_AGL_GMX_TX_LFSR (CVMX_ADD_IO_SEG(0x00011800E00004F8ull))
+#define CVMX_AGL_GMX_TX_OVR_BP (CVMX_ADD_IO_SEG(0x00011800E00004C8ull))
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC (CVMX_ADD_IO_SEG(0x00011800E00004A0ull))
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE (CVMX_ADD_IO_SEG(0x00011800E00004A8ull))
+#define CVMX_AGL_PRTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8)
union cvmx_agl_gmx_bad_reg {
uint64_t u64;
struct cvmx_agl_gmx_bad_reg_s {
+ uint64_t reserved_38_63:26;
+ uint64_t txpsh1:1;
+ uint64_t txpop1:1;
+ uint64_t ovrflw1:1;
+ uint64_t txpsh:1;
+ uint64_t txpop:1;
+ uint64_t ovrflw:1;
+ uint64_t reserved_27_31:5;
+ uint64_t statovr:1;
+ uint64_t reserved_24_25:2;
+ uint64_t loststat:2;
+ uint64_t reserved_4_21:18;
+ uint64_t out_ovr:2;
+ uint64_t reserved_0_1:2;
+ } s;
+ struct cvmx_agl_gmx_bad_reg_cn52xx {
uint64_t reserved_38_63:26;
uint64_t txpsh1:1;
uint64_t txpop1:1;
@@ -188,9 +136,8 @@ union cvmx_agl_gmx_bad_reg {
uint64_t reserved_4_21:18;
uint64_t out_ovr:2;
uint64_t reserved_0_1:2;
- } s;
- struct cvmx_agl_gmx_bad_reg_s cn52xx;
- struct cvmx_agl_gmx_bad_reg_s cn52xxp1;
+ } cn52xx;
+ struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1;
struct cvmx_agl_gmx_bad_reg_cn56xx {
uint64_t reserved_35_63:29;
uint64_t txpsh:1;
@@ -205,18 +152,25 @@ union cvmx_agl_gmx_bad_reg {
uint64_t reserved_0_1:2;
} cn56xx;
struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_bad_reg_s cn63xx;
+ struct cvmx_agl_gmx_bad_reg_s cn63xxp1;
};
union cvmx_agl_gmx_bist {
uint64_t u64;
struct cvmx_agl_gmx_bist_s {
+ uint64_t reserved_25_63:39;
+ uint64_t status:25;
+ } s;
+ struct cvmx_agl_gmx_bist_cn52xx {
uint64_t reserved_10_63:54;
uint64_t status:10;
- } s;
- struct cvmx_agl_gmx_bist_s cn52xx;
- struct cvmx_agl_gmx_bist_s cn52xxp1;
- struct cvmx_agl_gmx_bist_s cn56xx;
- struct cvmx_agl_gmx_bist_s cn56xxp1;
+ } cn52xx;
+ struct cvmx_agl_gmx_bist_cn52xx cn52xxp1;
+ struct cvmx_agl_gmx_bist_cn52xx cn56xx;
+ struct cvmx_agl_gmx_bist_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_bist_s cn63xx;
+ struct cvmx_agl_gmx_bist_s cn63xxp1;
};
union cvmx_agl_gmx_drv_ctl {
@@ -264,7 +218,13 @@ union cvmx_agl_gmx_inf_mode {
union cvmx_agl_gmx_prtx_cfg {
uint64_t u64;
struct cvmx_agl_gmx_prtx_cfg_s {
- uint64_t reserved_6_63:58;
+ uint64_t reserved_14_63:50;
+ uint64_t tx_idle:1;
+ uint64_t rx_idle:1;
+ uint64_t reserved_9_11:3;
+ uint64_t speed_msb:1;
+ uint64_t reserved_7_7:1;
+ uint64_t burst:1;
uint64_t tx_en:1;
uint64_t rx_en:1;
uint64_t slottime:1;
@@ -272,10 +232,20 @@ union cvmx_agl_gmx_prtx_cfg {
uint64_t speed:1;
uint64_t en:1;
} s;
- struct cvmx_agl_gmx_prtx_cfg_s cn52xx;
- struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1;
- struct cvmx_agl_gmx_prtx_cfg_s cn56xx;
- struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1;
+ struct cvmx_agl_gmx_prtx_cfg_cn52xx {
+ uint64_t reserved_6_63:58;
+ uint64_t tx_en:1;
+ uint64_t rx_en:1;
+ uint64_t slottime:1;
+ uint64_t duplex:1;
+ uint64_t speed:1;
+ uint64_t en:1;
+ } cn52xx;
+ struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1;
+ struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx;
+ struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_prtx_cfg_s cn63xx;
+ struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam0 {
@@ -287,6 +257,8 @@ union cvmx_agl_gmx_rxx_adr_cam0 {
struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx;
+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam1 {
@@ -298,6 +270,8 @@ union cvmx_agl_gmx_rxx_adr_cam1 {
struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx;
+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam2 {
@@ -309,6 +283,8 @@ union cvmx_agl_gmx_rxx_adr_cam2 {
struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx;
+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam3 {
@@ -320,6 +296,8 @@ union cvmx_agl_gmx_rxx_adr_cam3 {
struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx;
+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam4 {
@@ -331,6 +309,8 @@ union cvmx_agl_gmx_rxx_adr_cam4 {
struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx;
+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam5 {
@@ -342,6 +322,8 @@ union cvmx_agl_gmx_rxx_adr_cam5 {
struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx;
+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam_en {
@@ -354,6 +336,8 @@ union cvmx_agl_gmx_rxx_adr_cam_en {
struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx;
+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_adr_ctl {
@@ -368,6 +352,8 @@ union cvmx_agl_gmx_rxx_adr_ctl {
struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx;
+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_decision {
@@ -380,11 +366,26 @@ union cvmx_agl_gmx_rxx_decision {
struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
struct cvmx_agl_gmx_rxx_decision_s cn56xx;
struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_decision_s cn63xx;
+ struct cvmx_agl_gmx_rxx_decision_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_frm_chk {
uint64_t u64;
struct cvmx_agl_gmx_rxx_frm_chk_s {
+ uint64_t reserved_10_63:54;
+ uint64_t niberr:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t lenerr:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t maxerr:1;
+ uint64_t carext:1;
+ uint64_t minerr:1;
+ } s;
+ struct cvmx_agl_gmx_rxx_frm_chk_cn52xx {
uint64_t reserved_9_63:55;
uint64_t skperr:1;
uint64_t rcverr:1;
@@ -395,17 +396,21 @@ union cvmx_agl_gmx_rxx_frm_chk {
uint64_t maxerr:1;
uint64_t reserved_1_1:1;
uint64_t minerr:1;
- } s;
- struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx;
- struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx;
- struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1;
+ } cn52xx;
+ struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1;
+ struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx;
+ struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx;
+ struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_frm_ctl {
uint64_t u64;
struct cvmx_agl_gmx_rxx_frm_ctl_s {
- uint64_t reserved_10_63:54;
+ uint64_t reserved_13_63:51;
+ uint64_t ptp_mode:1;
+ uint64_t reserved_11_11:1;
+ uint64_t null_dis:1;
uint64_t pre_align:1;
uint64_t pad_len:1;
uint64_t vlan_len:1;
@@ -417,10 +422,24 @@ union cvmx_agl_gmx_rxx_frm_ctl {
uint64_t pre_strp:1;
uint64_t pre_chk:1;
} s;
- struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx;
- struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx;
- struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx {
+ uint64_t reserved_10_63:54;
+ uint64_t pre_align:1;
+ uint64_t pad_len:1;
+ uint64_t vlan_len:1;
+ uint64_t pre_free:1;
+ uint64_t ctl_smac:1;
+ uint64_t ctl_mcst:1;
+ uint64_t ctl_bck:1;
+ uint64_t ctl_drp:1;
+ uint64_t pre_strp:1;
+ uint64_t pre_chk:1;
+ } cn52xx;
+ struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1;
+ struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx;
+ struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx;
+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_frm_max {
@@ -433,6 +452,8 @@ union cvmx_agl_gmx_rxx_frm_max {
struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_frm_max_s cn63xx;
+ struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_frm_min {
@@ -445,6 +466,8 @@ union cvmx_agl_gmx_rxx_frm_min {
struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_frm_min_s cn63xx;
+ struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_ifg {
@@ -457,11 +480,36 @@ union cvmx_agl_gmx_rxx_ifg {
struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_ifg_s cn63xx;
+ struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_int_en {
uint64_t u64;
struct cvmx_agl_gmx_rxx_int_en_s {
+ uint64_t reserved_20_63:44;
+ uint64_t pause_drp:1;
+ uint64_t phy_dupx:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_link:1;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t niberr:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t lenerr:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t maxerr:1;
+ uint64_t carext:1;
+ uint64_t minerr:1;
+ } s;
+ struct cvmx_agl_gmx_rxx_int_en_cn52xx {
uint64_t reserved_20_63:44;
uint64_t pause_drp:1;
uint64_t reserved_16_18:3;
@@ -481,16 +529,40 @@ union cvmx_agl_gmx_rxx_int_en {
uint64_t maxerr:1;
uint64_t reserved_1_1:1;
uint64_t minerr:1;
- } s;
- struct cvmx_agl_gmx_rxx_int_en_s cn52xx;
- struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_int_en_s cn56xx;
- struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1;
+ } cn52xx;
+ struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1;
+ struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx;
+ struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_rxx_int_en_s cn63xx;
+ struct cvmx_agl_gmx_rxx_int_en_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_int_reg {
uint64_t u64;
struct cvmx_agl_gmx_rxx_int_reg_s {
+ uint64_t reserved_20_63:44;
+ uint64_t pause_drp:1;
+ uint64_t phy_dupx:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_link:1;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t niberr:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t lenerr:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t maxerr:1;
+ uint64_t carext:1;
+ uint64_t minerr:1;
+ } s;
+ struct cvmx_agl_gmx_rxx_int_reg_cn52xx {
uint64_t reserved_20_63:44;
uint64_t pause_drp:1;
uint64_t reserved_16_18:3;
@@ -510,11 +582,12 @@ union cvmx_agl_gmx_rxx_int_reg {
uint64_t maxerr:1;
uint64_t reserved_1_1:1;
uint64_t minerr:1;
- } s;
- struct cvmx_agl_gmx_rxx_int_reg_s cn52xx;
- struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_int_reg_s cn56xx;
- struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1;
+ } cn52xx;
+ struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1;
+ struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx;
+ struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_rxx_int_reg_s cn63xx;
+ struct cvmx_agl_gmx_rxx_int_reg_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_jabber {
@@ -527,6 +600,8 @@ union cvmx_agl_gmx_rxx_jabber {
struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_jabber_s cn63xx;
+ struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_pause_drop_time {
@@ -539,6 +614,20 @@ union cvmx_agl_gmx_rxx_pause_drop_time {
struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx;
+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1;
+};
+
+union cvmx_agl_gmx_rxx_rx_inbnd {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_rx_inbnd_s {
+ uint64_t reserved_4_63:60;
+ uint64_t duplex:1;
+ uint64_t speed:2;
+ uint64_t status:1;
+ } s;
+ struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx;
+ struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_ctl {
@@ -551,6 +640,8 @@ union cvmx_agl_gmx_rxx_stats_ctl {
struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_octs {
@@ -563,6 +654,8 @@ union cvmx_agl_gmx_rxx_stats_octs {
struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_octs_ctl {
@@ -575,6 +668,8 @@ union cvmx_agl_gmx_rxx_stats_octs_ctl {
struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_octs_dmac {
@@ -587,6 +682,8 @@ union cvmx_agl_gmx_rxx_stats_octs_dmac {
struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_octs_drp {
@@ -599,6 +696,8 @@ union cvmx_agl_gmx_rxx_stats_octs_drp {
struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_pkts {
@@ -611,6 +710,8 @@ union cvmx_agl_gmx_rxx_stats_pkts {
struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_pkts_bad {
@@ -623,6 +724,8 @@ union cvmx_agl_gmx_rxx_stats_pkts_bad {
struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_pkts_ctl {
@@ -635,6 +738,8 @@ union cvmx_agl_gmx_rxx_stats_pkts_ctl {
struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_pkts_dmac {
@@ -647,6 +752,8 @@ union cvmx_agl_gmx_rxx_stats_pkts_dmac {
struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_pkts_drp {
@@ -659,6 +766,8 @@ union cvmx_agl_gmx_rxx_stats_pkts_drp {
struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_udd_skp {
@@ -673,6 +782,8 @@ union cvmx_agl_gmx_rxx_udd_skp {
struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx;
+ struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1;
};
union cvmx_agl_gmx_rx_bp_dropx {
@@ -685,6 +796,8 @@ union cvmx_agl_gmx_rx_bp_dropx {
struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
+ struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx;
+ struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1;
};
union cvmx_agl_gmx_rx_bp_offx {
@@ -697,6 +810,8 @@ union cvmx_agl_gmx_rx_bp_offx {
struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
+ struct cvmx_agl_gmx_rx_bp_offx_s cn63xx;
+ struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1;
};
union cvmx_agl_gmx_rx_bp_onx {
@@ -709,6 +824,8 @@ union cvmx_agl_gmx_rx_bp_onx {
struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
+ struct cvmx_agl_gmx_rx_bp_onx_s cn63xx;
+ struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1;
};
union cvmx_agl_gmx_rx_prt_info {
@@ -728,6 +845,8 @@ union cvmx_agl_gmx_rx_prt_info {
uint64_t commit:1;
} cn56xx;
struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_rx_prt_info_s cn63xx;
+ struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1;
};
union cvmx_agl_gmx_rx_tx_status {
@@ -747,6 +866,8 @@ union cvmx_agl_gmx_rx_tx_status {
uint64_t rx:1;
} cn56xx;
struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_rx_tx_status_s cn63xx;
+ struct cvmx_agl_gmx_rx_tx_status_s cn63xxp1;
};
union cvmx_agl_gmx_smacx {
@@ -759,6 +880,8 @@ union cvmx_agl_gmx_smacx {
struct cvmx_agl_gmx_smacx_s cn52xxp1;
struct cvmx_agl_gmx_smacx_s cn56xx;
struct cvmx_agl_gmx_smacx_s cn56xxp1;
+ struct cvmx_agl_gmx_smacx_s cn63xx;
+ struct cvmx_agl_gmx_smacx_s cn63xxp1;
};
union cvmx_agl_gmx_stat_bp {
@@ -772,6 +895,8 @@ union cvmx_agl_gmx_stat_bp {
struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
struct cvmx_agl_gmx_stat_bp_s cn56xx;
struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
+ struct cvmx_agl_gmx_stat_bp_s cn63xx;
+ struct cvmx_agl_gmx_stat_bp_s cn63xxp1;
};
union cvmx_agl_gmx_txx_append {
@@ -787,6 +912,18 @@ union cvmx_agl_gmx_txx_append {
struct cvmx_agl_gmx_txx_append_s cn52xxp1;
struct cvmx_agl_gmx_txx_append_s cn56xx;
struct cvmx_agl_gmx_txx_append_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_append_s cn63xx;
+ struct cvmx_agl_gmx_txx_append_s cn63xxp1;
+};
+
+union cvmx_agl_gmx_txx_clk {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_clk_s {
+ uint64_t reserved_6_63:58;
+ uint64_t clk_cnt:6;
+ } s;
+ struct cvmx_agl_gmx_txx_clk_s cn63xx;
+ struct cvmx_agl_gmx_txx_clk_s cn63xxp1;
};
union cvmx_agl_gmx_txx_ctl {
@@ -800,6 +937,8 @@ union cvmx_agl_gmx_txx_ctl {
struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
struct cvmx_agl_gmx_txx_ctl_s cn56xx;
struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_ctl_s cn63xx;
+ struct cvmx_agl_gmx_txx_ctl_s cn63xxp1;
};
union cvmx_agl_gmx_txx_min_pkt {
@@ -812,6 +951,8 @@ union cvmx_agl_gmx_txx_min_pkt {
struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_min_pkt_s cn63xx;
+ struct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1;
};
union cvmx_agl_gmx_txx_pause_pkt_interval {
@@ -824,6 +965,8 @@ union cvmx_agl_gmx_txx_pause_pkt_interval {
struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx;
+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1;
};
union cvmx_agl_gmx_txx_pause_pkt_time {
@@ -836,6 +979,8 @@ union cvmx_agl_gmx_txx_pause_pkt_time {
struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx;
+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1;
};
union cvmx_agl_gmx_txx_pause_togo {
@@ -848,6 +993,8 @@ union cvmx_agl_gmx_txx_pause_togo {
struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_pause_togo_s cn63xx;
+ struct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1;
};
union cvmx_agl_gmx_txx_pause_zero {
@@ -860,6 +1007,8 @@ union cvmx_agl_gmx_txx_pause_zero {
struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_pause_zero_s cn63xx;
+ struct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1;
};
union cvmx_agl_gmx_txx_soft_pause {
@@ -872,6 +1021,8 @@ union cvmx_agl_gmx_txx_soft_pause {
struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_soft_pause_s cn63xx;
+ struct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat0 {
@@ -884,6 +1035,8 @@ union cvmx_agl_gmx_txx_stat0 {
struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat0_s cn56xx;
struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat0_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat0_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat1 {
@@ -896,6 +1049,8 @@ union cvmx_agl_gmx_txx_stat1 {
struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat1_s cn56xx;
struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat1_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat1_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat2 {
@@ -908,6 +1063,8 @@ union cvmx_agl_gmx_txx_stat2 {
struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat2_s cn56xx;
struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat2_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat2_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat3 {
@@ -920,6 +1077,8 @@ union cvmx_agl_gmx_txx_stat3 {
struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat3_s cn56xx;
struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat3_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat3_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat4 {
@@ -932,6 +1091,8 @@ union cvmx_agl_gmx_txx_stat4 {
struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat4_s cn56xx;
struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat4_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat4_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat5 {
@@ -944,6 +1105,8 @@ union cvmx_agl_gmx_txx_stat5 {
struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat5_s cn56xx;
struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat5_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat5_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat6 {
@@ -956,6 +1119,8 @@ union cvmx_agl_gmx_txx_stat6 {
struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat6_s cn56xx;
struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat6_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat6_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat7 {
@@ -968,6 +1133,8 @@ union cvmx_agl_gmx_txx_stat7 {
struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat7_s cn56xx;
struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat7_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat7_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat8 {
@@ -980,6 +1147,8 @@ union cvmx_agl_gmx_txx_stat8 {
struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat8_s cn56xx;
struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat8_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat8_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat9 {
@@ -992,6 +1161,8 @@ union cvmx_agl_gmx_txx_stat9 {
struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat9_s cn56xx;
struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat9_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat9_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stats_ctl {
@@ -1004,6 +1175,8 @@ union cvmx_agl_gmx_txx_stats_ctl {
struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stats_ctl_s cn63xx;
+ struct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1;
};
union cvmx_agl_gmx_txx_thresh {
@@ -1016,6 +1189,8 @@ union cvmx_agl_gmx_txx_thresh {
struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
struct cvmx_agl_gmx_txx_thresh_s cn56xx;
struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_thresh_s cn63xx;
+ struct cvmx_agl_gmx_txx_thresh_s cn63xxp1;
};
union cvmx_agl_gmx_tx_bp {
@@ -1031,6 +1206,8 @@ union cvmx_agl_gmx_tx_bp {
uint64_t bp:1;
} cn56xx;
struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_tx_bp_s cn63xx;
+ struct cvmx_agl_gmx_tx_bp_s cn63xxp1;
};
union cvmx_agl_gmx_tx_col_attempt {
@@ -1043,6 +1220,8 @@ union cvmx_agl_gmx_tx_col_attempt {
struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_col_attempt_s cn63xx;
+ struct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1;
};
union cvmx_agl_gmx_tx_ifg {
@@ -1056,12 +1235,16 @@ union cvmx_agl_gmx_tx_ifg {
struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
struct cvmx_agl_gmx_tx_ifg_s cn56xx;
struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_ifg_s cn63xx;
+ struct cvmx_agl_gmx_tx_ifg_s cn63xxp1;
};
union cvmx_agl_gmx_tx_int_en {
uint64_t u64;
struct cvmx_agl_gmx_tx_int_en_s {
- uint64_t reserved_18_63:46;
+ uint64_t reserved_22_63:42;
+ uint64_t ptp_lost:2;
+ uint64_t reserved_18_19:2;
uint64_t late_col:2;
uint64_t reserved_14_15:2;
uint64_t xsdef:2;
@@ -1072,8 +1255,19 @@ union cvmx_agl_gmx_tx_int_en {
uint64_t reserved_1_1:1;
uint64_t pko_nxa:1;
} s;
- struct cvmx_agl_gmx_tx_int_en_s cn52xx;
- struct cvmx_agl_gmx_tx_int_en_s cn52xxp1;
+ struct cvmx_agl_gmx_tx_int_en_cn52xx {
+ uint64_t reserved_18_63:46;
+ uint64_t late_col:2;
+ uint64_t reserved_14_15:2;
+ uint64_t xsdef:2;
+ uint64_t reserved_10_11:2;
+ uint64_t xscol:2;
+ uint64_t reserved_4_7:4;
+ uint64_t undflw:2;
+ uint64_t reserved_1_1:1;
+ uint64_t pko_nxa:1;
+ } cn52xx;
+ struct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1;
struct cvmx_agl_gmx_tx_int_en_cn56xx {
uint64_t reserved_17_63:47;
uint64_t late_col:1;
@@ -1087,12 +1281,16 @@ union cvmx_agl_gmx_tx_int_en {
uint64_t pko_nxa:1;
} cn56xx;
struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_tx_int_en_s cn63xx;
+ struct cvmx_agl_gmx_tx_int_en_s cn63xxp1;
};
union cvmx_agl_gmx_tx_int_reg {
uint64_t u64;
struct cvmx_agl_gmx_tx_int_reg_s {
- uint64_t reserved_18_63:46;
+ uint64_t reserved_22_63:42;
+ uint64_t ptp_lost:2;
+ uint64_t reserved_18_19:2;
uint64_t late_col:2;
uint64_t reserved_14_15:2;
uint64_t xsdef:2;
@@ -1103,8 +1301,19 @@ union cvmx_agl_gmx_tx_int_reg {
uint64_t reserved_1_1:1;
uint64_t pko_nxa:1;
} s;
- struct cvmx_agl_gmx_tx_int_reg_s cn52xx;
- struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1;
+ struct cvmx_agl_gmx_tx_int_reg_cn52xx {
+ uint64_t reserved_18_63:46;
+ uint64_t late_col:2;
+ uint64_t reserved_14_15:2;
+ uint64_t xsdef:2;
+ uint64_t reserved_10_11:2;
+ uint64_t xscol:2;
+ uint64_t reserved_4_7:4;
+ uint64_t undflw:2;
+ uint64_t reserved_1_1:1;
+ uint64_t pko_nxa:1;
+ } cn52xx;
+ struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1;
struct cvmx_agl_gmx_tx_int_reg_cn56xx {
uint64_t reserved_17_63:47;
uint64_t late_col:1;
@@ -1118,6 +1327,8 @@ union cvmx_agl_gmx_tx_int_reg {
uint64_t pko_nxa:1;
} cn56xx;
struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_tx_int_reg_s cn63xx;
+ struct cvmx_agl_gmx_tx_int_reg_s cn63xxp1;
};
union cvmx_agl_gmx_tx_jam {
@@ -1130,6 +1341,8 @@ union cvmx_agl_gmx_tx_jam {
struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
struct cvmx_agl_gmx_tx_jam_s cn56xx;
struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_jam_s cn63xx;
+ struct cvmx_agl_gmx_tx_jam_s cn63xxp1;
};
union cvmx_agl_gmx_tx_lfsr {
@@ -1142,6 +1355,8 @@ union cvmx_agl_gmx_tx_lfsr {
struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_lfsr_s cn63xx;
+ struct cvmx_agl_gmx_tx_lfsr_s cn63xxp1;
};
union cvmx_agl_gmx_tx_ovr_bp {
@@ -1165,6 +1380,8 @@ union cvmx_agl_gmx_tx_ovr_bp {
uint64_t ign_full:1;
} cn56xx;
struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_tx_ovr_bp_s cn63xx;
+ struct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1;
};
union cvmx_agl_gmx_tx_pause_pkt_dmac {
@@ -1177,6 +1394,8 @@ union cvmx_agl_gmx_tx_pause_pkt_dmac {
struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx;
+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1;
};
union cvmx_agl_gmx_tx_pause_pkt_type {
@@ -1189,6 +1408,39 @@ union cvmx_agl_gmx_tx_pause_pkt_type {
struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx;
+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1;
+};
+
+union cvmx_agl_prtx_ctl {
+ uint64_t u64;
+ struct cvmx_agl_prtx_ctl_s {
+ uint64_t drv_byp:1;
+ uint64_t reserved_62_62:1;
+ uint64_t cmp_pctl:6;
+ uint64_t reserved_54_55:2;
+ uint64_t cmp_nctl:6;
+ uint64_t reserved_46_47:2;
+ uint64_t drv_pctl:6;
+ uint64_t reserved_38_39:2;
+ uint64_t drv_nctl:6;
+ uint64_t reserved_29_31:3;
+ uint64_t clk_set:5;
+ uint64_t clkrx_byp:1;
+ uint64_t reserved_21_22:2;
+ uint64_t clkrx_set:5;
+ uint64_t clktx_byp:1;
+ uint64_t reserved_13_14:2;
+ uint64_t clktx_set:5;
+ uint64_t reserved_5_7:3;
+ uint64_t dllrst:1;
+ uint64_t comp:1;
+ uint64_t enable:1;
+ uint64_t clkrst:1;
+ uint64_t mode:1;
+ } s;
+ struct cvmx_agl_prtx_ctl_s cn63xx;
+ struct cvmx_agl_prtx_ctl_s cn63xxp1;
};
#endif
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-asm.h b/trunk/arch/mips/include/asm/octeon/cvmx-asm.h
index b21d3fc1ef91..5de5de95311b 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-asm.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-asm.h
@@ -114,6 +114,17 @@
#define CVMX_DCACHE_INVALIDATE \
{ CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); }
+#define CVMX_CACHE(op, address, offset) \
+ asm volatile ("cache " CVMX_TMP_STR(op) ", " CVMX_TMP_STR(offset) "(%[rbase])" \
+ : : [rbase] "d" (address) )
+/* fetch and lock the state. */
+#define CVMX_CACHE_LCKL2(address, offset) CVMX_CACHE(31, address, offset)
+/* unlock the state. */
+#define CVMX_CACHE_WBIL2(address, offset) CVMX_CACHE(23, address, offset)
+/* invalidate the cache block and clear the USED bits for the block */
+#define CVMX_CACHE_WBIL2I(address, offset) CVMX_CACHE(3, address, offset)
+/* load virtual tag and data for the L2 cache block into L2C_TAD0_TAG register */
+#define CVMX_CACHE_LTGL2I(address, offset) CVMX_CACHE(7, address, offset)
#define CVMX_POP(result, input) \
asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-ciu-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
index f8f05b7764b7..27cead370411 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,87 +28,61 @@
#ifndef __CVMX_CIU_DEFS_H__
#define __CVMX_CIU_DEFS_H__
-#define CVMX_CIU_BIST \
- CVMX_ADD_IO_SEG(0x0001070000000730ull)
-#define CVMX_CIU_DINT \
- CVMX_ADD_IO_SEG(0x0001070000000720ull)
-#define CVMX_CIU_FUSE \
- CVMX_ADD_IO_SEG(0x0001070000000728ull)
-#define CVMX_CIU_GSTOP \
- CVMX_ADD_IO_SEG(0x0001070000000710ull)
-#define CVMX_CIU_INTX_EN0(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000200ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN0_W1C(offset) \
- CVMX_ADD_IO_SEG(0x0001070000002200ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN0_W1S(offset) \
- CVMX_ADD_IO_SEG(0x0001070000006200ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN1(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000208ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN1_W1C(offset) \
- CVMX_ADD_IO_SEG(0x0001070000002208ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN1_W1S(offset) \
- CVMX_ADD_IO_SEG(0x0001070000006208ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN4_0(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000C80ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_0_W1C(offset) \
- CVMX_ADD_IO_SEG(0x0001070000002C80ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_0_W1S(offset) \
- CVMX_ADD_IO_SEG(0x0001070000006C80ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_1(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000C88ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_1_W1C(offset) \
- CVMX_ADD_IO_SEG(0x0001070000002C88ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_1_W1S(offset) \
- CVMX_ADD_IO_SEG(0x0001070000006C88ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_SUM0(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000000ull + (((offset) & 63) * 8))
-#define CVMX_CIU_INTX_SUM4(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000C00ull + (((offset) & 15) * 8))
-#define CVMX_CIU_INT_SUM1 \
- CVMX_ADD_IO_SEG(0x0001070000000108ull)
-#define CVMX_CIU_MBOX_CLRX(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000680ull + (((offset) & 15) * 8))
-#define CVMX_CIU_MBOX_SETX(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000600ull + (((offset) & 15) * 8))
-#define CVMX_CIU_NMI \
- CVMX_ADD_IO_SEG(0x0001070000000718ull)
-#define CVMX_CIU_PCI_INTA \
- CVMX_ADD_IO_SEG(0x0001070000000750ull)
-#define CVMX_CIU_PP_DBG \
- CVMX_ADD_IO_SEG(0x0001070000000708ull)
-#define CVMX_CIU_PP_POKEX(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000580ull + (((offset) & 15) * 8))
-#define CVMX_CIU_PP_RST \
- CVMX_ADD_IO_SEG(0x0001070000000700ull)
-#define CVMX_CIU_QLM_DCOK \
- CVMX_ADD_IO_SEG(0x0001070000000760ull)
-#define CVMX_CIU_QLM_JTGC \
- CVMX_ADD_IO_SEG(0x0001070000000768ull)
-#define CVMX_CIU_QLM_JTGD \
- CVMX_ADD_IO_SEG(0x0001070000000770ull)
-#define CVMX_CIU_SOFT_BIST \
- CVMX_ADD_IO_SEG(0x0001070000000738ull)
-#define CVMX_CIU_SOFT_PRST \
- CVMX_ADD_IO_SEG(0x0001070000000748ull)
-#define CVMX_CIU_SOFT_PRST1 \
- CVMX_ADD_IO_SEG(0x0001070000000758ull)
-#define CVMX_CIU_SOFT_RST \
- CVMX_ADD_IO_SEG(0x0001070000000740ull)
-#define CVMX_CIU_TIMX(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000480ull + (((offset) & 3) * 8))
-#define CVMX_CIU_WDOGX(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000500ull + (((offset) & 15) * 8))
+#define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull))
+#define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull))
+#define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull))
+#define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull))
+#define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull))
+#define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull))
+#define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN1(offset) (CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN4_0(offset) (CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_1(offset) (CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_SUM0(offset) (CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8)
+#define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull))
+#define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull))
+#define CVMX_CIU_MBOX_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_MBOX_SETX(offset) (CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull))
+#define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull))
+#define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull))
+#define CVMX_CIU_PP_POKEX(offset) (CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull))
+#define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull))
+#define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull))
+#define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull))
+#define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull))
+#define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull))
+#define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull))
+#define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull))
+#define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull))
+#define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull))
+#define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull))
+#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8)
+#define CVMX_CIU_WDOGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8)
union cvmx_ciu_bist {
uint64_t u64;
struct cvmx_ciu_bist_s {
+ uint64_t reserved_5_63:59;
+ uint64_t bist:5;
+ } s;
+ struct cvmx_ciu_bist_cn30xx {
uint64_t reserved_4_63:60;
uint64_t bist:4;
- } s;
- struct cvmx_ciu_bist_s cn30xx;
- struct cvmx_ciu_bist_s cn31xx;
- struct cvmx_ciu_bist_s cn38xx;
- struct cvmx_ciu_bist_s cn38xxp2;
+ } cn30xx;
+ struct cvmx_ciu_bist_cn30xx cn31xx;
+ struct cvmx_ciu_bist_cn30xx cn38xx;
+ struct cvmx_ciu_bist_cn30xx cn38xxp2;
struct cvmx_ciu_bist_cn50xx {
uint64_t reserved_2_63:62;
uint64_t bist:2;
@@ -118,10 +92,57 @@ union cvmx_ciu_bist {
uint64_t bist:3;
} cn52xx;
struct cvmx_ciu_bist_cn52xx cn52xxp1;
- struct cvmx_ciu_bist_s cn56xx;
- struct cvmx_ciu_bist_s cn56xxp1;
- struct cvmx_ciu_bist_s cn58xx;
- struct cvmx_ciu_bist_s cn58xxp1;
+ struct cvmx_ciu_bist_cn30xx cn56xx;
+ struct cvmx_ciu_bist_cn30xx cn56xxp1;
+ struct cvmx_ciu_bist_cn30xx cn58xx;
+ struct cvmx_ciu_bist_cn30xx cn58xxp1;
+ struct cvmx_ciu_bist_s cn63xx;
+ struct cvmx_ciu_bist_s cn63xxp1;
+};
+
+union cvmx_ciu_block_int {
+ uint64_t u64;
+ struct cvmx_ciu_block_int_s {
+ uint64_t reserved_43_63:21;
+ uint64_t ptp:1;
+ uint64_t dpi:1;
+ uint64_t dfm:1;
+ uint64_t reserved_34_39:6;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t reserved_31_31:1;
+ uint64_t iob:1;
+ uint64_t reserved_29_29:1;
+ uint64_t agl:1;
+ uint64_t reserved_27_27:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t reserved_23_24:2;
+ uint64_t asxpcs0:1;
+ uint64_t reserved_21_21:1;
+ uint64_t pip:1;
+ uint64_t reserved_18_19:2;
+ uint64_t lmc0:1;
+ uint64_t l2c:1;
+ uint64_t reserved_15_15:1;
+ uint64_t rad:1;
+ uint64_t usb:1;
+ uint64_t pow:1;
+ uint64_t tim:1;
+ uint64_t pko:1;
+ uint64_t ipd:1;
+ uint64_t reserved_8_8:1;
+ uint64_t zip:1;
+ uint64_t dfa:1;
+ uint64_t fpa:1;
+ uint64_t key:1;
+ uint64_t sli:1;
+ uint64_t reserved_2_2:1;
+ uint64_t gmx0:1;
+ uint64_t mio:1;
+ } s;
+ struct cvmx_ciu_block_int_s cn63xx;
+ struct cvmx_ciu_block_int_s cn63xxp1;
};
union cvmx_ciu_dint {
@@ -153,6 +174,11 @@ union cvmx_ciu_dint {
struct cvmx_ciu_dint_cn56xx cn56xxp1;
struct cvmx_ciu_dint_s cn58xx;
struct cvmx_ciu_dint_s cn58xxp1;
+ struct cvmx_ciu_dint_cn63xx {
+ uint64_t reserved_6_63:58;
+ uint64_t dint:6;
+ } cn63xx;
+ struct cvmx_ciu_dint_cn63xx cn63xxp1;
};
union cvmx_ciu_fuse {
@@ -184,6 +210,11 @@ union cvmx_ciu_fuse {
struct cvmx_ciu_fuse_cn56xx cn56xxp1;
struct cvmx_ciu_fuse_s cn58xx;
struct cvmx_ciu_fuse_s cn58xxp1;
+ struct cvmx_ciu_fuse_cn63xx {
+ uint64_t reserved_6_63:58;
+ uint64_t fuse:6;
+ } cn63xx;
+ struct cvmx_ciu_fuse_cn63xx cn63xxp1;
};
union cvmx_ciu_gstop {
@@ -203,6 +234,8 @@ union cvmx_ciu_gstop {
struct cvmx_ciu_gstop_s cn56xxp1;
struct cvmx_ciu_gstop_s cn58xx;
struct cvmx_ciu_gstop_s cn58xxp1;
+ struct cvmx_ciu_gstop_s cn63xx;
+ struct cvmx_ciu_gstop_s cn63xxp1;
};
union cvmx_ciu_intx_en0 {
@@ -343,6 +376,8 @@ union cvmx_ciu_intx_en0 {
struct cvmx_ciu_intx_en0_cn56xx cn56xxp1;
struct cvmx_ciu_intx_en0_cn38xx cn58xx;
struct cvmx_ciu_intx_en0_cn38xx cn58xxp1;
+ struct cvmx_ciu_intx_en0_cn52xx cn63xx;
+ struct cvmx_ciu_intx_en0_cn52xx cn63xxp1;
};
union cvmx_ciu_intx_en0_w1c {
@@ -412,6 +447,8 @@ union cvmx_ciu_intx_en0_w1c {
uint64_t gpio:16;
uint64_t workq:16;
} cn58xx;
+ struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx;
+ struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1;
};
union cvmx_ciu_intx_en0_w1s {
@@ -481,12 +518,42 @@ union cvmx_ciu_intx_en0_w1s {
uint64_t gpio:16;
uint64_t workq:16;
} cn58xx;
+ struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx;
+ struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1;
};
union cvmx_ciu_intx_en1 {
uint64_t u64;
struct cvmx_ciu_intx_en1_s {
- uint64_t reserved_20_63:44;
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
uint64_t nand:1;
uint64_t mii1:1;
uint64_t usb1:1;
@@ -531,12 +598,76 @@ union cvmx_ciu_intx_en1 {
struct cvmx_ciu_intx_en1_cn56xx cn56xxp1;
struct cvmx_ciu_intx_en1_cn38xx cn58xx;
struct cvmx_ciu_intx_en1_cn38xx cn58xxp1;
+ struct cvmx_ciu_intx_en1_cn63xx {
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t reserved_6_17:12;
+ uint64_t wdog:6;
+ } cn63xx;
+ struct cvmx_ciu_intx_en1_cn63xx cn63xxp1;
};
union cvmx_ciu_intx_en1_w1c {
uint64_t u64;
struct cvmx_ciu_intx_en1_w1c_s {
- uint64_t reserved_20_63:44;
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
uint64_t nand:1;
uint64_t mii1:1;
uint64_t usb1:1;
@@ -560,12 +691,76 @@ union cvmx_ciu_intx_en1_w1c {
uint64_t reserved_16_63:48;
uint64_t wdog:16;
} cn58xx;
+ struct cvmx_ciu_intx_en1_w1c_cn63xx {
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t reserved_6_17:12;
+ uint64_t wdog:6;
+ } cn63xx;
+ struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1;
};
union cvmx_ciu_intx_en1_w1s {
uint64_t u64;
struct cvmx_ciu_intx_en1_w1s_s {
- uint64_t reserved_20_63:44;
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
uint64_t nand:1;
uint64_t mii1:1;
uint64_t usb1:1;
@@ -589,6 +784,42 @@ union cvmx_ciu_intx_en1_w1s {
uint64_t reserved_16_63:48;
uint64_t wdog:16;
} cn58xx;
+ struct cvmx_ciu_intx_en1_w1s_cn63xx {
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t reserved_6_17:12;
+ uint64_t wdog:6;
+ } cn63xx;
+ struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1;
};
union cvmx_ciu_intx_en4_0 {
@@ -705,6 +936,8 @@ union cvmx_ciu_intx_en4_0 {
uint64_t workq:16;
} cn58xx;
struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1;
+ struct cvmx_ciu_intx_en4_0_cn52xx cn63xx;
+ struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1;
};
union cvmx_ciu_intx_en4_0_w1c {
@@ -774,6 +1007,8 @@ union cvmx_ciu_intx_en4_0_w1c {
uint64_t gpio:16;
uint64_t workq:16;
} cn58xx;
+ struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx;
+ struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1;
};
union cvmx_ciu_intx_en4_0_w1s {
@@ -843,12 +1078,42 @@ union cvmx_ciu_intx_en4_0_w1s {
uint64_t gpio:16;
uint64_t workq:16;
} cn58xx;
+ struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx;
+ struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1;
};
union cvmx_ciu_intx_en4_1 {
uint64_t u64;
struct cvmx_ciu_intx_en4_1_s {
- uint64_t reserved_20_63:44;
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
uint64_t nand:1;
uint64_t mii1:1;
uint64_t usb1:1;
@@ -886,12 +1151,76 @@ union cvmx_ciu_intx_en4_1 {
uint64_t wdog:16;
} cn58xx;
struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1;
+ struct cvmx_ciu_intx_en4_1_cn63xx {
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t reserved_6_17:12;
+ uint64_t wdog:6;
+ } cn63xx;
+ struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1;
};
union cvmx_ciu_intx_en4_1_w1c {
uint64_t u64;
struct cvmx_ciu_intx_en4_1_w1c_s {
- uint64_t reserved_20_63:44;
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
uint64_t nand:1;
uint64_t mii1:1;
uint64_t usb1:1;
@@ -915,12 +1244,76 @@ union cvmx_ciu_intx_en4_1_w1c {
uint64_t reserved_16_63:48;
uint64_t wdog:16;
} cn58xx;
+ struct cvmx_ciu_intx_en4_1_w1c_cn63xx {
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t reserved_6_17:12;
+ uint64_t wdog:6;
+ } cn63xx;
+ struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1;
};
union cvmx_ciu_intx_en4_1_w1s {
uint64_t u64;
struct cvmx_ciu_intx_en4_1_w1s_s {
- uint64_t reserved_20_63:44;
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
uint64_t nand:1;
uint64_t mii1:1;
uint64_t usb1:1;
@@ -944,6 +1337,42 @@ union cvmx_ciu_intx_en4_1_w1s {
uint64_t reserved_16_63:48;
uint64_t wdog:16;
} cn58xx;
+ struct cvmx_ciu_intx_en4_1_w1s_cn63xx {
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t reserved_6_17:12;
+ uint64_t wdog:6;
+ } cn63xx;
+ struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1;
};
union cvmx_ciu_intx_sum0 {
@@ -1084,6 +1513,8 @@ union cvmx_ciu_intx_sum0 {
struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1;
struct cvmx_ciu_intx_sum0_cn38xx cn58xx;
struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1;
+ struct cvmx_ciu_intx_sum0_cn52xx cn63xx;
+ struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1;
};
union cvmx_ciu_intx_sum4 {
@@ -1200,12 +1631,85 @@ union cvmx_ciu_intx_sum4 {
uint64_t workq:16;
} cn58xx;
struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1;
+ struct cvmx_ciu_intx_sum4_cn52xx cn63xx;
+ struct cvmx_ciu_intx_sum4_cn52xx cn63xxp1;
+};
+
+union cvmx_ciu_int33_sum0 {
+ uint64_t u64;
+ struct cvmx_ciu_int33_sum0_s {
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t reserved_51_51:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t gmx_drp:1;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t wdog_sum:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+ } s;
+ struct cvmx_ciu_int33_sum0_s cn63xx;
+ struct cvmx_ciu_int33_sum0_s cn63xxp1;
+};
+
+union cvmx_ciu_int_dbg_sel {
+ uint64_t u64;
+ struct cvmx_ciu_int_dbg_sel_s {
+ uint64_t reserved_19_63:45;
+ uint64_t sel:3;
+ uint64_t reserved_10_15:6;
+ uint64_t irq:2;
+ uint64_t reserved_3_7:5;
+ uint64_t pp:3;
+ } s;
+ struct cvmx_ciu_int_dbg_sel_s cn63xx;
};
union cvmx_ciu_int_sum1 {
uint64_t u64;
struct cvmx_ciu_int_sum1_s {
- uint64_t reserved_20_63:44;
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
uint64_t nand:1;
uint64_t mii1:1;
uint64_t usb1:1;
@@ -1250,6 +1754,42 @@ union cvmx_ciu_int_sum1 {
struct cvmx_ciu_int_sum1_cn56xx cn56xxp1;
struct cvmx_ciu_int_sum1_cn38xx cn58xx;
struct cvmx_ciu_int_sum1_cn38xx cn58xxp1;
+ struct cvmx_ciu_int_sum1_cn63xx {
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t reserved_6_17:12;
+ uint64_t wdog:6;
+ } cn63xx;
+ struct cvmx_ciu_int_sum1_cn63xx cn63xxp1;
};
union cvmx_ciu_mbox_clrx {
@@ -1269,6 +1809,8 @@ union cvmx_ciu_mbox_clrx {
struct cvmx_ciu_mbox_clrx_s cn56xxp1;
struct cvmx_ciu_mbox_clrx_s cn58xx;
struct cvmx_ciu_mbox_clrx_s cn58xxp1;
+ struct cvmx_ciu_mbox_clrx_s cn63xx;
+ struct cvmx_ciu_mbox_clrx_s cn63xxp1;
};
union cvmx_ciu_mbox_setx {
@@ -1288,6 +1830,8 @@ union cvmx_ciu_mbox_setx {
struct cvmx_ciu_mbox_setx_s cn56xxp1;
struct cvmx_ciu_mbox_setx_s cn58xx;
struct cvmx_ciu_mbox_setx_s cn58xxp1;
+ struct cvmx_ciu_mbox_setx_s cn63xx;
+ struct cvmx_ciu_mbox_setx_s cn63xxp1;
};
union cvmx_ciu_nmi {
@@ -1319,6 +1863,11 @@ union cvmx_ciu_nmi {
struct cvmx_ciu_nmi_cn56xx cn56xxp1;
struct cvmx_ciu_nmi_s cn58xx;
struct cvmx_ciu_nmi_s cn58xxp1;
+ struct cvmx_ciu_nmi_cn63xx {
+ uint64_t reserved_6_63:58;
+ uint64_t nmi:6;
+ } cn63xx;
+ struct cvmx_ciu_nmi_cn63xx cn63xxp1;
};
union cvmx_ciu_pci_inta {
@@ -1338,6 +1887,8 @@ union cvmx_ciu_pci_inta {
struct cvmx_ciu_pci_inta_s cn56xxp1;
struct cvmx_ciu_pci_inta_s cn58xx;
struct cvmx_ciu_pci_inta_s cn58xxp1;
+ struct cvmx_ciu_pci_inta_s cn63xx;
+ struct cvmx_ciu_pci_inta_s cn63xxp1;
};
union cvmx_ciu_pp_dbg {
@@ -1369,12 +1920,17 @@ union cvmx_ciu_pp_dbg {
struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1;
struct cvmx_ciu_pp_dbg_s cn58xx;
struct cvmx_ciu_pp_dbg_s cn58xxp1;
+ struct cvmx_ciu_pp_dbg_cn63xx {
+ uint64_t reserved_6_63:58;
+ uint64_t ppdbg:6;
+ } cn63xx;
+ struct cvmx_ciu_pp_dbg_cn63xx cn63xxp1;
};
union cvmx_ciu_pp_pokex {
uint64_t u64;
struct cvmx_ciu_pp_pokex_s {
- uint64_t reserved_0_63:64;
+ uint64_t poke:64;
} s;
struct cvmx_ciu_pp_pokex_s cn30xx;
struct cvmx_ciu_pp_pokex_s cn31xx;
@@ -1387,6 +1943,8 @@ union cvmx_ciu_pp_pokex {
struct cvmx_ciu_pp_pokex_s cn56xxp1;
struct cvmx_ciu_pp_pokex_s cn58xx;
struct cvmx_ciu_pp_pokex_s cn58xxp1;
+ struct cvmx_ciu_pp_pokex_s cn63xx;
+ struct cvmx_ciu_pp_pokex_s cn63xxp1;
};
union cvmx_ciu_pp_rst {
@@ -1422,6 +1980,97 @@ union cvmx_ciu_pp_rst {
struct cvmx_ciu_pp_rst_cn56xx cn56xxp1;
struct cvmx_ciu_pp_rst_s cn58xx;
struct cvmx_ciu_pp_rst_s cn58xxp1;
+ struct cvmx_ciu_pp_rst_cn63xx {
+ uint64_t reserved_6_63:58;
+ uint64_t rst:5;
+ uint64_t rst0:1;
+ } cn63xx;
+ struct cvmx_ciu_pp_rst_cn63xx cn63xxp1;
+};
+
+union cvmx_ciu_qlm0 {
+ uint64_t u64;
+ struct cvmx_ciu_qlm0_s {
+ uint64_t g2bypass:1;
+ uint64_t reserved_53_62:10;
+ uint64_t g2deemph:5;
+ uint64_t reserved_45_47:3;
+ uint64_t g2margin:5;
+ uint64_t reserved_32_39:8;
+ uint64_t txbypass:1;
+ uint64_t reserved_21_30:10;
+ uint64_t txdeemph:5;
+ uint64_t reserved_13_15:3;
+ uint64_t txmargin:5;
+ uint64_t reserved_4_7:4;
+ uint64_t lane_en:4;
+ } s;
+ struct cvmx_ciu_qlm0_s cn63xx;
+ struct cvmx_ciu_qlm0_cn63xxp1 {
+ uint64_t reserved_32_63:32;
+ uint64_t txbypass:1;
+ uint64_t reserved_20_30:11;
+ uint64_t txdeemph:4;
+ uint64_t reserved_13_15:3;
+ uint64_t txmargin:5;
+ uint64_t reserved_4_7:4;
+ uint64_t lane_en:4;
+ } cn63xxp1;
+};
+
+union cvmx_ciu_qlm1 {
+ uint64_t u64;
+ struct cvmx_ciu_qlm1_s {
+ uint64_t g2bypass:1;
+ uint64_t reserved_53_62:10;
+ uint64_t g2deemph:5;
+ uint64_t reserved_45_47:3;
+ uint64_t g2margin:5;
+ uint64_t reserved_32_39:8;
+ uint64_t txbypass:1;
+ uint64_t reserved_21_30:10;
+ uint64_t txdeemph:5;
+ uint64_t reserved_13_15:3;
+ uint64_t txmargin:5;
+ uint64_t reserved_4_7:4;
+ uint64_t lane_en:4;
+ } s;
+ struct cvmx_ciu_qlm1_s cn63xx;
+ struct cvmx_ciu_qlm1_cn63xxp1 {
+ uint64_t reserved_32_63:32;
+ uint64_t txbypass:1;
+ uint64_t reserved_20_30:11;
+ uint64_t txdeemph:4;
+ uint64_t reserved_13_15:3;
+ uint64_t txmargin:5;
+ uint64_t reserved_4_7:4;
+ uint64_t lane_en:4;
+ } cn63xxp1;
+};
+
+union cvmx_ciu_qlm2 {
+ uint64_t u64;
+ struct cvmx_ciu_qlm2_s {
+ uint64_t reserved_32_63:32;
+ uint64_t txbypass:1;
+ uint64_t reserved_21_30:10;
+ uint64_t txdeemph:5;
+ uint64_t reserved_13_15:3;
+ uint64_t txmargin:5;
+ uint64_t reserved_4_7:4;
+ uint64_t lane_en:4;
+ } s;
+ struct cvmx_ciu_qlm2_s cn63xx;
+ struct cvmx_ciu_qlm2_cn63xxp1 {
+ uint64_t reserved_32_63:32;
+ uint64_t txbypass:1;
+ uint64_t reserved_20_30:11;
+ uint64_t txdeemph:4;
+ uint64_t reserved_13_15:3;
+ uint64_t txmargin:5;
+ uint64_t reserved_4_7:4;
+ uint64_t lane_en:4;
+ } cn63xxp1;
};
union cvmx_ciu_qlm_dcok {
@@ -1459,6 +2108,15 @@ union cvmx_ciu_qlm_jtgc {
struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1;
struct cvmx_ciu_qlm_jtgc_s cn56xx;
struct cvmx_ciu_qlm_jtgc_s cn56xxp1;
+ struct cvmx_ciu_qlm_jtgc_cn63xx {
+ uint64_t reserved_11_63:53;
+ uint64_t clk_div:3;
+ uint64_t reserved_6_7:2;
+ uint64_t mux_sel:2;
+ uint64_t reserved_3_3:1;
+ uint64_t bypass:3;
+ } cn63xx;
+ struct cvmx_ciu_qlm_jtgc_cn63xx cn63xxp1;
};
union cvmx_ciu_qlm_jtgd {
@@ -1493,6 +2151,17 @@ union cvmx_ciu_qlm_jtgd {
uint64_t shft_cnt:5;
uint64_t shft_reg:32;
} cn56xxp1;
+ struct cvmx_ciu_qlm_jtgd_cn63xx {
+ uint64_t capture:1;
+ uint64_t shift:1;
+ uint64_t update:1;
+ uint64_t reserved_43_60:18;
+ uint64_t select:3;
+ uint64_t reserved_37_39:3;
+ uint64_t shft_cnt:5;
+ uint64_t shft_reg:32;
+ } cn63xx;
+ struct cvmx_ciu_qlm_jtgd_cn63xx cn63xxp1;
};
union cvmx_ciu_soft_bist {
@@ -1512,6 +2181,8 @@ union cvmx_ciu_soft_bist {
struct cvmx_ciu_soft_bist_s cn56xxp1;
struct cvmx_ciu_soft_bist_s cn58xx;
struct cvmx_ciu_soft_bist_s cn58xxp1;
+ struct cvmx_ciu_soft_bist_s cn63xx;
+ struct cvmx_ciu_soft_bist_s cn63xxp1;
};
union cvmx_ciu_soft_prst {
@@ -1536,6 +2207,8 @@ union cvmx_ciu_soft_prst {
struct cvmx_ciu_soft_prst_cn52xx cn56xxp1;
struct cvmx_ciu_soft_prst_s cn58xx;
struct cvmx_ciu_soft_prst_s cn58xxp1;
+ struct cvmx_ciu_soft_prst_cn52xx cn63xx;
+ struct cvmx_ciu_soft_prst_cn52xx cn63xxp1;
};
union cvmx_ciu_soft_prst1 {
@@ -1548,6 +2221,8 @@ union cvmx_ciu_soft_prst1 {
struct cvmx_ciu_soft_prst1_s cn52xxp1;
struct cvmx_ciu_soft_prst1_s cn56xx;
struct cvmx_ciu_soft_prst1_s cn56xxp1;
+ struct cvmx_ciu_soft_prst1_s cn63xx;
+ struct cvmx_ciu_soft_prst1_s cn63xxp1;
};
union cvmx_ciu_soft_rst {
@@ -1567,6 +2242,8 @@ union cvmx_ciu_soft_rst {
struct cvmx_ciu_soft_rst_s cn56xxp1;
struct cvmx_ciu_soft_rst_s cn58xx;
struct cvmx_ciu_soft_rst_s cn58xxp1;
+ struct cvmx_ciu_soft_rst_s cn63xx;
+ struct cvmx_ciu_soft_rst_s cn63xxp1;
};
union cvmx_ciu_timx {
@@ -1587,6 +2264,8 @@ union cvmx_ciu_timx {
struct cvmx_ciu_timx_s cn56xxp1;
struct cvmx_ciu_timx_s cn58xx;
struct cvmx_ciu_timx_s cn58xxp1;
+ struct cvmx_ciu_timx_s cn63xx;
+ struct cvmx_ciu_timx_s cn63xxp1;
};
union cvmx_ciu_wdogx {
@@ -1611,6 +2290,8 @@ union cvmx_ciu_wdogx {
struct cvmx_ciu_wdogx_s cn56xxp1;
struct cvmx_ciu_wdogx_s cn58xx;
struct cvmx_ciu_wdogx_s cn58xxp1;
+ struct cvmx_ciu_wdogx_s cn63xx;
+ struct cvmx_ciu_wdogx_s cn63xxp1;
};
#endif
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-gpio-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
index 5fdd6ba48a05..395564e8d1f0 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,29 +28,22 @@
#ifndef __CVMX_GPIO_DEFS_H__
#define __CVMX_GPIO_DEFS_H__
-#define CVMX_GPIO_BIT_CFGX(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000800ull + (((offset) & 15) * 8))
-#define CVMX_GPIO_BOOT_ENA \
- CVMX_ADD_IO_SEG(0x00010700000008A8ull)
-#define CVMX_GPIO_CLK_GENX(offset) \
- CVMX_ADD_IO_SEG(0x00010700000008C0ull + (((offset) & 3) * 8))
-#define CVMX_GPIO_DBG_ENA \
- CVMX_ADD_IO_SEG(0x00010700000008A0ull)
-#define CVMX_GPIO_INT_CLR \
- CVMX_ADD_IO_SEG(0x0001070000000898ull)
-#define CVMX_GPIO_RX_DAT \
- CVMX_ADD_IO_SEG(0x0001070000000880ull)
-#define CVMX_GPIO_TX_CLR \
- CVMX_ADD_IO_SEG(0x0001070000000890ull)
-#define CVMX_GPIO_TX_SET \
- CVMX_ADD_IO_SEG(0x0001070000000888ull)
-#define CVMX_GPIO_XBIT_CFGX(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000900ull + (((offset) & 31) * 8) - 8 * 16)
+#define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
+#define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))
+#define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
+#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
+#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
+#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
+#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
+#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
+#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
+#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
union cvmx_gpio_bit_cfgx {
uint64_t u64;
struct cvmx_gpio_bit_cfgx_s {
- uint64_t reserved_15_63:49;
+ uint64_t reserved_17_63:47;
+ uint64_t synce_sel:2;
uint64_t clk_gen:1;
uint64_t clk_sel:2;
uint64_t fil_sel:4;
@@ -73,12 +66,24 @@ union cvmx_gpio_bit_cfgx {
struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
- struct cvmx_gpio_bit_cfgx_s cn52xx;
- struct cvmx_gpio_bit_cfgx_s cn52xxp1;
- struct cvmx_gpio_bit_cfgx_s cn56xx;
- struct cvmx_gpio_bit_cfgx_s cn56xxp1;
+ struct cvmx_gpio_bit_cfgx_cn52xx {
+ uint64_t reserved_15_63:49;
+ uint64_t clk_gen:1;
+ uint64_t clk_sel:2;
+ uint64_t fil_sel:4;
+ uint64_t fil_cnt:4;
+ uint64_t int_type:1;
+ uint64_t int_en:1;
+ uint64_t rx_xor:1;
+ uint64_t tx_oe:1;
+ } cn52xx;
+ struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1;
+ struct cvmx_gpio_bit_cfgx_cn52xx cn56xx;
+ struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1;
struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
+ struct cvmx_gpio_bit_cfgx_s cn63xx;
+ struct cvmx_gpio_bit_cfgx_s cn63xxp1;
};
union cvmx_gpio_boot_ena {
@@ -103,6 +108,19 @@ union cvmx_gpio_clk_genx {
struct cvmx_gpio_clk_genx_s cn52xxp1;
struct cvmx_gpio_clk_genx_s cn56xx;
struct cvmx_gpio_clk_genx_s cn56xxp1;
+ struct cvmx_gpio_clk_genx_s cn63xx;
+ struct cvmx_gpio_clk_genx_s cn63xxp1;
+};
+
+union cvmx_gpio_clk_qlmx {
+ uint64_t u64;
+ struct cvmx_gpio_clk_qlmx_s {
+ uint64_t reserved_3_63:61;
+ uint64_t div:1;
+ uint64_t lane_sel:2;
+ } s;
+ struct cvmx_gpio_clk_qlmx_s cn63xx;
+ struct cvmx_gpio_clk_qlmx_s cn63xxp1;
};
union cvmx_gpio_dbg_ena {
@@ -133,6 +151,8 @@ union cvmx_gpio_int_clr {
struct cvmx_gpio_int_clr_s cn56xxp1;
struct cvmx_gpio_int_clr_s cn58xx;
struct cvmx_gpio_int_clr_s cn58xxp1;
+ struct cvmx_gpio_int_clr_s cn63xx;
+ struct cvmx_gpio_int_clr_s cn63xxp1;
};
union cvmx_gpio_rx_dat {
@@ -155,6 +175,8 @@ union cvmx_gpio_rx_dat {
struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
struct cvmx_gpio_rx_dat_cn38xx cn58xx;
struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
+ struct cvmx_gpio_rx_dat_cn38xx cn63xx;
+ struct cvmx_gpio_rx_dat_cn38xx cn63xxp1;
};
union cvmx_gpio_tx_clr {
@@ -177,6 +199,8 @@ union cvmx_gpio_tx_clr {
struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
struct cvmx_gpio_tx_clr_cn38xx cn58xx;
struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
+ struct cvmx_gpio_tx_clr_cn38xx cn63xx;
+ struct cvmx_gpio_tx_clr_cn38xx cn63xxp1;
};
union cvmx_gpio_tx_set {
@@ -199,6 +223,8 @@ union cvmx_gpio_tx_set {
struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
struct cvmx_gpio_tx_set_cn38xx cn58xx;
struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
+ struct cvmx_gpio_tx_set_cn38xx cn63xx;
+ struct cvmx_gpio_tx_set_cn38xx cn63xxp1;
};
union cvmx_gpio_xbit_cfgx {
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-iob-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-iob-defs.h
index 0ee36baec500..d7d856c2483d 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-iob-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-iob-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,55 +28,39 @@
#ifndef __CVMX_IOB_DEFS_H__
#define __CVMX_IOB_DEFS_H__
-#define CVMX_IOB_BIST_STATUS \
- CVMX_ADD_IO_SEG(0x00011800F00007F8ull)
-#define CVMX_IOB_CTL_STATUS \
- CVMX_ADD_IO_SEG(0x00011800F0000050ull)
-#define CVMX_IOB_DWB_PRI_CNT \
- CVMX_ADD_IO_SEG(0x00011800F0000028ull)
-#define CVMX_IOB_FAU_TIMEOUT \
- CVMX_ADD_IO_SEG(0x00011800F0000000ull)
-#define CVMX_IOB_I2C_PRI_CNT \
- CVMX_ADD_IO_SEG(0x00011800F0000010ull)
-#define CVMX_IOB_INB_CONTROL_MATCH \
- CVMX_ADD_IO_SEG(0x00011800F0000078ull)
-#define CVMX_IOB_INB_CONTROL_MATCH_ENB \
- CVMX_ADD_IO_SEG(0x00011800F0000088ull)
-#define CVMX_IOB_INB_DATA_MATCH \
- CVMX_ADD_IO_SEG(0x00011800F0000070ull)
-#define CVMX_IOB_INB_DATA_MATCH_ENB \
- CVMX_ADD_IO_SEG(0x00011800F0000080ull)
-#define CVMX_IOB_INT_ENB \
- CVMX_ADD_IO_SEG(0x00011800F0000060ull)
-#define CVMX_IOB_INT_SUM \
- CVMX_ADD_IO_SEG(0x00011800F0000058ull)
-#define CVMX_IOB_N2C_L2C_PRI_CNT \
- CVMX_ADD_IO_SEG(0x00011800F0000020ull)
-#define CVMX_IOB_N2C_RSP_PRI_CNT \
- CVMX_ADD_IO_SEG(0x00011800F0000008ull)
-#define CVMX_IOB_OUTB_COM_PRI_CNT \
- CVMX_ADD_IO_SEG(0x00011800F0000040ull)
-#define CVMX_IOB_OUTB_CONTROL_MATCH \
- CVMX_ADD_IO_SEG(0x00011800F0000098ull)
-#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB \
- CVMX_ADD_IO_SEG(0x00011800F00000A8ull)
-#define CVMX_IOB_OUTB_DATA_MATCH \
- CVMX_ADD_IO_SEG(0x00011800F0000090ull)
-#define CVMX_IOB_OUTB_DATA_MATCH_ENB \
- CVMX_ADD_IO_SEG(0x00011800F00000A0ull)
-#define CVMX_IOB_OUTB_FPA_PRI_CNT \
- CVMX_ADD_IO_SEG(0x00011800F0000048ull)
-#define CVMX_IOB_OUTB_REQ_PRI_CNT \
- CVMX_ADD_IO_SEG(0x00011800F0000038ull)
-#define CVMX_IOB_P2C_REQ_PRI_CNT \
- CVMX_ADD_IO_SEG(0x00011800F0000018ull)
-#define CVMX_IOB_PKT_ERR \
- CVMX_ADD_IO_SEG(0x00011800F0000068ull)
+#define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull))
+#define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull))
+#define CVMX_IOB_DWB_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000028ull))
+#define CVMX_IOB_FAU_TIMEOUT (CVMX_ADD_IO_SEG(0x00011800F0000000ull))
+#define CVMX_IOB_I2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000010ull))
+#define CVMX_IOB_INB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000078ull))
+#define CVMX_IOB_INB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000088ull))
+#define CVMX_IOB_INB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000070ull))
+#define CVMX_IOB_INB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000080ull))
+#define CVMX_IOB_INT_ENB (CVMX_ADD_IO_SEG(0x00011800F0000060ull))
+#define CVMX_IOB_INT_SUM (CVMX_ADD_IO_SEG(0x00011800F0000058ull))
+#define CVMX_IOB_N2C_L2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000020ull))
+#define CVMX_IOB_N2C_RSP_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000008ull))
+#define CVMX_IOB_OUTB_COM_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000040ull))
+#define CVMX_IOB_OUTB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000098ull))
+#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A8ull))
+#define CVMX_IOB_OUTB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000090ull))
+#define CVMX_IOB_OUTB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A0ull))
+#define CVMX_IOB_OUTB_FPA_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000048ull))
+#define CVMX_IOB_OUTB_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000038ull))
+#define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull))
+#define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull))
+#define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull))
union cvmx_iob_bist_status {
uint64_t u64;
struct cvmx_iob_bist_status_s {
- uint64_t reserved_18_63:46;
+ uint64_t reserved_23_63:41;
+ uint64_t xmdfif:1;
+ uint64_t xmcfif:1;
+ uint64_t iorfif:1;
+ uint64_t rsdfif:1;
+ uint64_t iocfif:1;
uint64_t icnrcb:1;
uint64_t icr0:1;
uint64_t icr1:1;
@@ -96,40 +80,81 @@ union cvmx_iob_bist_status {
uint64_t ibd:1;
uint64_t icd:1;
} s;
- struct cvmx_iob_bist_status_s cn30xx;
- struct cvmx_iob_bist_status_s cn31xx;
- struct cvmx_iob_bist_status_s cn38xx;
- struct cvmx_iob_bist_status_s cn38xxp2;
- struct cvmx_iob_bist_status_s cn50xx;
- struct cvmx_iob_bist_status_s cn52xx;
- struct cvmx_iob_bist_status_s cn52xxp1;
- struct cvmx_iob_bist_status_s cn56xx;
- struct cvmx_iob_bist_status_s cn56xxp1;
- struct cvmx_iob_bist_status_s cn58xx;
- struct cvmx_iob_bist_status_s cn58xxp1;
+ struct cvmx_iob_bist_status_cn30xx {
+ uint64_t reserved_18_63:46;
+ uint64_t icnrcb:1;
+ uint64_t icr0:1;
+ uint64_t icr1:1;
+ uint64_t icnr1:1;
+ uint64_t icnr0:1;
+ uint64_t ibdr0:1;
+ uint64_t ibdr1:1;
+ uint64_t ibr0:1;
+ uint64_t ibr1:1;
+ uint64_t icnrt:1;
+ uint64_t ibrq0:1;
+ uint64_t ibrq1:1;
+ uint64_t icrn0:1;
+ uint64_t icrn1:1;
+ uint64_t icrp0:1;
+ uint64_t icrp1:1;
+ uint64_t ibd:1;
+ uint64_t icd:1;
+ } cn30xx;
+ struct cvmx_iob_bist_status_cn30xx cn31xx;
+ struct cvmx_iob_bist_status_cn30xx cn38xx;
+ struct cvmx_iob_bist_status_cn30xx cn38xxp2;
+ struct cvmx_iob_bist_status_cn30xx cn50xx;
+ struct cvmx_iob_bist_status_cn30xx cn52xx;
+ struct cvmx_iob_bist_status_cn30xx cn52xxp1;
+ struct cvmx_iob_bist_status_cn30xx cn56xx;
+ struct cvmx_iob_bist_status_cn30xx cn56xxp1;
+ struct cvmx_iob_bist_status_cn30xx cn58xx;
+ struct cvmx_iob_bist_status_cn30xx cn58xxp1;
+ struct cvmx_iob_bist_status_s cn63xx;
+ struct cvmx_iob_bist_status_s cn63xxp1;
};
union cvmx_iob_ctl_status {
uint64_t u64;
struct cvmx_iob_ctl_status_s {
- uint64_t reserved_5_63:59;
+ uint64_t reserved_10_63:54;
+ uint64_t xmc_per:4;
+ uint64_t rr_mode:1;
uint64_t outb_mat:1;
uint64_t inb_mat:1;
uint64_t pko_enb:1;
uint64_t dwb_enb:1;
uint64_t fau_end:1;
} s;
- struct cvmx_iob_ctl_status_s cn30xx;
- struct cvmx_iob_ctl_status_s cn31xx;
- struct cvmx_iob_ctl_status_s cn38xx;
- struct cvmx_iob_ctl_status_s cn38xxp2;
- struct cvmx_iob_ctl_status_s cn50xx;
- struct cvmx_iob_ctl_status_s cn52xx;
- struct cvmx_iob_ctl_status_s cn52xxp1;
- struct cvmx_iob_ctl_status_s cn56xx;
- struct cvmx_iob_ctl_status_s cn56xxp1;
- struct cvmx_iob_ctl_status_s cn58xx;
- struct cvmx_iob_ctl_status_s cn58xxp1;
+ struct cvmx_iob_ctl_status_cn30xx {
+ uint64_t reserved_5_63:59;
+ uint64_t outb_mat:1;
+ uint64_t inb_mat:1;
+ uint64_t pko_enb:1;
+ uint64_t dwb_enb:1;
+ uint64_t fau_end:1;
+ } cn30xx;
+ struct cvmx_iob_ctl_status_cn30xx cn31xx;
+ struct cvmx_iob_ctl_status_cn30xx cn38xx;
+ struct cvmx_iob_ctl_status_cn30xx cn38xxp2;
+ struct cvmx_iob_ctl_status_cn30xx cn50xx;
+ struct cvmx_iob_ctl_status_cn52xx {
+ uint64_t reserved_6_63:58;
+ uint64_t rr_mode:1;
+ uint64_t outb_mat:1;
+ uint64_t inb_mat:1;
+ uint64_t pko_enb:1;
+ uint64_t dwb_enb:1;
+ uint64_t fau_end:1;
+ } cn52xx;
+ struct cvmx_iob_ctl_status_cn30xx cn52xxp1;
+ struct cvmx_iob_ctl_status_cn30xx cn56xx;
+ struct cvmx_iob_ctl_status_cn30xx cn56xxp1;
+ struct cvmx_iob_ctl_status_cn30xx cn58xx;
+ struct cvmx_iob_ctl_status_cn30xx cn58xxp1;
+ struct cvmx_iob_ctl_status_s cn63xx;
+ struct cvmx_iob_ctl_status_s cn63xxp1;
};
union cvmx_iob_dwb_pri_cnt {
@@ -147,6 +172,8 @@ union cvmx_iob_dwb_pri_cnt {
struct cvmx_iob_dwb_pri_cnt_s cn56xxp1;
struct cvmx_iob_dwb_pri_cnt_s cn58xx;
struct cvmx_iob_dwb_pri_cnt_s cn58xxp1;
+ struct cvmx_iob_dwb_pri_cnt_s cn63xx;
+ struct cvmx_iob_dwb_pri_cnt_s cn63xxp1;
};
union cvmx_iob_fau_timeout {
@@ -167,6 +194,8 @@ union cvmx_iob_fau_timeout {
struct cvmx_iob_fau_timeout_s cn56xxp1;
struct cvmx_iob_fau_timeout_s cn58xx;
struct cvmx_iob_fau_timeout_s cn58xxp1;
+ struct cvmx_iob_fau_timeout_s cn63xx;
+ struct cvmx_iob_fau_timeout_s cn63xxp1;
};
union cvmx_iob_i2c_pri_cnt {
@@ -184,6 +213,8 @@ union cvmx_iob_i2c_pri_cnt {
struct cvmx_iob_i2c_pri_cnt_s cn56xxp1;
struct cvmx_iob_i2c_pri_cnt_s cn58xx;
struct cvmx_iob_i2c_pri_cnt_s cn58xxp1;
+ struct cvmx_iob_i2c_pri_cnt_s cn63xx;
+ struct cvmx_iob_i2c_pri_cnt_s cn63xxp1;
};
union cvmx_iob_inb_control_match {
@@ -206,6 +237,8 @@ union cvmx_iob_inb_control_match {
struct cvmx_iob_inb_control_match_s cn56xxp1;
struct cvmx_iob_inb_control_match_s cn58xx;
struct cvmx_iob_inb_control_match_s cn58xxp1;
+ struct cvmx_iob_inb_control_match_s cn63xx;
+ struct cvmx_iob_inb_control_match_s cn63xxp1;
};
union cvmx_iob_inb_control_match_enb {
@@ -228,6 +261,8 @@ union cvmx_iob_inb_control_match_enb {
struct cvmx_iob_inb_control_match_enb_s cn56xxp1;
struct cvmx_iob_inb_control_match_enb_s cn58xx;
struct cvmx_iob_inb_control_match_enb_s cn58xxp1;
+ struct cvmx_iob_inb_control_match_enb_s cn63xx;
+ struct cvmx_iob_inb_control_match_enb_s cn63xxp1;
};
union cvmx_iob_inb_data_match {
@@ -246,6 +281,8 @@ union cvmx_iob_inb_data_match {
struct cvmx_iob_inb_data_match_s cn56xxp1;
struct cvmx_iob_inb_data_match_s cn58xx;
struct cvmx_iob_inb_data_match_s cn58xxp1;
+ struct cvmx_iob_inb_data_match_s cn63xx;
+ struct cvmx_iob_inb_data_match_s cn63xxp1;
};
union cvmx_iob_inb_data_match_enb {
@@ -264,6 +301,8 @@ union cvmx_iob_inb_data_match_enb {
struct cvmx_iob_inb_data_match_enb_s cn56xxp1;
struct cvmx_iob_inb_data_match_enb_s cn58xx;
struct cvmx_iob_inb_data_match_enb_s cn58xxp1;
+ struct cvmx_iob_inb_data_match_enb_s cn63xx;
+ struct cvmx_iob_inb_data_match_enb_s cn63xxp1;
};
union cvmx_iob_int_enb {
@@ -294,6 +333,8 @@ union cvmx_iob_int_enb {
struct cvmx_iob_int_enb_s cn56xxp1;
struct cvmx_iob_int_enb_s cn58xx;
struct cvmx_iob_int_enb_s cn58xxp1;
+ struct cvmx_iob_int_enb_s cn63xx;
+ struct cvmx_iob_int_enb_s cn63xxp1;
};
union cvmx_iob_int_sum {
@@ -324,6 +365,8 @@ union cvmx_iob_int_sum {
struct cvmx_iob_int_sum_s cn56xxp1;
struct cvmx_iob_int_sum_s cn58xx;
struct cvmx_iob_int_sum_s cn58xxp1;
+ struct cvmx_iob_int_sum_s cn63xx;
+ struct cvmx_iob_int_sum_s cn63xxp1;
};
union cvmx_iob_n2c_l2c_pri_cnt {
@@ -341,6 +384,8 @@ union cvmx_iob_n2c_l2c_pri_cnt {
struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1;
struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx;
struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1;
+ struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xx;
+ struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xxp1;
};
union cvmx_iob_n2c_rsp_pri_cnt {
@@ -358,6 +403,8 @@ union cvmx_iob_n2c_rsp_pri_cnt {
struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1;
struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx;
struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1;
+ struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xx;
+ struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xxp1;
};
union cvmx_iob_outb_com_pri_cnt {
@@ -375,6 +422,8 @@ union cvmx_iob_outb_com_pri_cnt {
struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1;
struct cvmx_iob_outb_com_pri_cnt_s cn58xx;
struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1;
+ struct cvmx_iob_outb_com_pri_cnt_s cn63xx;
+ struct cvmx_iob_outb_com_pri_cnt_s cn63xxp1;
};
union cvmx_iob_outb_control_match {
@@ -397,6 +446,8 @@ union cvmx_iob_outb_control_match {
struct cvmx_iob_outb_control_match_s cn56xxp1;
struct cvmx_iob_outb_control_match_s cn58xx;
struct cvmx_iob_outb_control_match_s cn58xxp1;
+ struct cvmx_iob_outb_control_match_s cn63xx;
+ struct cvmx_iob_outb_control_match_s cn63xxp1;
};
union cvmx_iob_outb_control_match_enb {
@@ -419,6 +470,8 @@ union cvmx_iob_outb_control_match_enb {
struct cvmx_iob_outb_control_match_enb_s cn56xxp1;
struct cvmx_iob_outb_control_match_enb_s cn58xx;
struct cvmx_iob_outb_control_match_enb_s cn58xxp1;
+ struct cvmx_iob_outb_control_match_enb_s cn63xx;
+ struct cvmx_iob_outb_control_match_enb_s cn63xxp1;
};
union cvmx_iob_outb_data_match {
@@ -437,6 +490,8 @@ union cvmx_iob_outb_data_match {
struct cvmx_iob_outb_data_match_s cn56xxp1;
struct cvmx_iob_outb_data_match_s cn58xx;
struct cvmx_iob_outb_data_match_s cn58xxp1;
+ struct cvmx_iob_outb_data_match_s cn63xx;
+ struct cvmx_iob_outb_data_match_s cn63xxp1;
};
union cvmx_iob_outb_data_match_enb {
@@ -455,6 +510,8 @@ union cvmx_iob_outb_data_match_enb {
struct cvmx_iob_outb_data_match_enb_s cn56xxp1;
struct cvmx_iob_outb_data_match_enb_s cn58xx;
struct cvmx_iob_outb_data_match_enb_s cn58xxp1;
+ struct cvmx_iob_outb_data_match_enb_s cn63xx;
+ struct cvmx_iob_outb_data_match_enb_s cn63xxp1;
};
union cvmx_iob_outb_fpa_pri_cnt {
@@ -472,6 +529,8 @@ union cvmx_iob_outb_fpa_pri_cnt {
struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1;
struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx;
struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1;
+ struct cvmx_iob_outb_fpa_pri_cnt_s cn63xx;
+ struct cvmx_iob_outb_fpa_pri_cnt_s cn63xxp1;
};
union cvmx_iob_outb_req_pri_cnt {
@@ -489,6 +548,8 @@ union cvmx_iob_outb_req_pri_cnt {
struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1;
struct cvmx_iob_outb_req_pri_cnt_s cn58xx;
struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1;
+ struct cvmx_iob_outb_req_pri_cnt_s cn63xx;
+ struct cvmx_iob_outb_req_pri_cnt_s cn63xxp1;
};
union cvmx_iob_p2c_req_pri_cnt {
@@ -506,25 +567,46 @@ union cvmx_iob_p2c_req_pri_cnt {
struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1;
struct cvmx_iob_p2c_req_pri_cnt_s cn58xx;
struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1;
+ struct cvmx_iob_p2c_req_pri_cnt_s cn63xx;
+ struct cvmx_iob_p2c_req_pri_cnt_s cn63xxp1;
};
union cvmx_iob_pkt_err {
uint64_t u64;
struct cvmx_iob_pkt_err_s {
+ uint64_t reserved_12_63:52;
+ uint64_t vport:6;
+ uint64_t port:6;
+ } s;
+ struct cvmx_iob_pkt_err_cn30xx {
uint64_t reserved_6_63:58;
uint64_t port:6;
+ } cn30xx;
+ struct cvmx_iob_pkt_err_cn30xx cn31xx;
+ struct cvmx_iob_pkt_err_cn30xx cn38xx;
+ struct cvmx_iob_pkt_err_cn30xx cn38xxp2;
+ struct cvmx_iob_pkt_err_cn30xx cn50xx;
+ struct cvmx_iob_pkt_err_cn30xx cn52xx;
+ struct cvmx_iob_pkt_err_cn30xx cn52xxp1;
+ struct cvmx_iob_pkt_err_cn30xx cn56xx;
+ struct cvmx_iob_pkt_err_cn30xx cn56xxp1;
+ struct cvmx_iob_pkt_err_cn30xx cn58xx;
+ struct cvmx_iob_pkt_err_cn30xx cn58xxp1;
+ struct cvmx_iob_pkt_err_s cn63xx;
+ struct cvmx_iob_pkt_err_s cn63xxp1;
+};
+
+union cvmx_iob_to_cmb_credits {
+ uint64_t u64;
+ struct cvmx_iob_to_cmb_credits_s {
+ uint64_t reserved_9_63:55;
+ uint64_t pko_rd:3;
+ uint64_t ncb_rd:3;
+ uint64_t ncb_wr:3;
} s;
- struct cvmx_iob_pkt_err_s cn30xx;
- struct cvmx_iob_pkt_err_s cn31xx;
- struct cvmx_iob_pkt_err_s cn38xx;
- struct cvmx_iob_pkt_err_s cn38xxp2;
- struct cvmx_iob_pkt_err_s cn50xx;
- struct cvmx_iob_pkt_err_s cn52xx;
- struct cvmx_iob_pkt_err_s cn52xxp1;
- struct cvmx_iob_pkt_err_s cn56xx;
- struct cvmx_iob_pkt_err_s cn56xxp1;
- struct cvmx_iob_pkt_err_s cn58xx;
- struct cvmx_iob_pkt_err_s cn58xxp1;
+ struct cvmx_iob_to_cmb_credits_s cn52xx;
+ struct cvmx_iob_to_cmb_credits_s cn63xx;
+ struct cvmx_iob_to_cmb_credits_s cn63xxp1;
};
#endif
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-ipd-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
index f8b8fc657d2c..e0a5bfe88d04 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,104 +28,57 @@
#ifndef __CVMX_IPD_DEFS_H__
#define __CVMX_IPD_DEFS_H__
-#define CVMX_IPD_1ST_MBUFF_SKIP \
- CVMX_ADD_IO_SEG(0x00014F0000000000ull)
-#define CVMX_IPD_1st_NEXT_PTR_BACK \
- CVMX_ADD_IO_SEG(0x00014F0000000150ull)
-#define CVMX_IPD_2nd_NEXT_PTR_BACK \
- CVMX_ADD_IO_SEG(0x00014F0000000158ull)
-#define CVMX_IPD_BIST_STATUS \
- CVMX_ADD_IO_SEG(0x00014F00000007F8ull)
-#define CVMX_IPD_BP_PRT_RED_END \
- CVMX_ADD_IO_SEG(0x00014F0000000328ull)
-#define CVMX_IPD_CLK_COUNT \
- CVMX_ADD_IO_SEG(0x00014F0000000338ull)
-#define CVMX_IPD_CTL_STATUS \
- CVMX_ADD_IO_SEG(0x00014F0000000018ull)
-#define CVMX_IPD_INT_ENB \
- CVMX_ADD_IO_SEG(0x00014F0000000160ull)
-#define CVMX_IPD_INT_SUM \
- CVMX_ADD_IO_SEG(0x00014F0000000168ull)
-#define CVMX_IPD_NOT_1ST_MBUFF_SKIP \
- CVMX_ADD_IO_SEG(0x00014F0000000008ull)
-#define CVMX_IPD_PACKET_MBUFF_SIZE \
- CVMX_ADD_IO_SEG(0x00014F0000000010ull)
-#define CVMX_IPD_PKT_PTR_VALID \
- CVMX_ADD_IO_SEG(0x00014F0000000358ull)
-#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) \
- CVMX_ADD_IO_SEG(0x00014F0000000028ull + (((offset) & 63) * 8))
-#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) \
- CVMX_ADD_IO_SEG(0x00014F0000000368ull + (((offset) & 63) * 8) - 8 * 36)
-#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) \
- CVMX_ADD_IO_SEG(0x00014F0000000388ull + (((offset) & 63) * 8) - 8 * 36)
-#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) \
- CVMX_ADD_IO_SEG(0x00014F00000001B8ull + (((offset) & 63) * 8))
-#define CVMX_IPD_PORT_QOS_INTX(offset) \
- CVMX_ADD_IO_SEG(0x00014F0000000808ull + (((offset) & 7) * 8))
-#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) \
- CVMX_ADD_IO_SEG(0x00014F0000000848ull + (((offset) & 7) * 8))
-#define CVMX_IPD_PORT_QOS_X_CNT(offset) \
- CVMX_ADD_IO_SEG(0x00014F0000000888ull + (((offset) & 511) * 8))
-#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL \
- CVMX_ADD_IO_SEG(0x00014F0000000348ull)
-#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL \
- CVMX_ADD_IO_SEG(0x00014F0000000350ull)
-#define CVMX_IPD_PTR_COUNT \
- CVMX_ADD_IO_SEG(0x00014F0000000320ull)
-#define CVMX_IPD_PWP_PTR_FIFO_CTL \
- CVMX_ADD_IO_SEG(0x00014F0000000340ull)
-#define CVMX_IPD_QOS0_RED_MARKS \
- CVMX_ADD_IO_SEG(0x00014F0000000178ull)
-#define CVMX_IPD_QOS1_RED_MARKS \
- CVMX_ADD_IO_SEG(0x00014F0000000180ull)
-#define CVMX_IPD_QOS2_RED_MARKS \
- CVMX_ADD_IO_SEG(0x00014F0000000188ull)
-#define CVMX_IPD_QOS3_RED_MARKS \
- CVMX_ADD_IO_SEG(0x00014F0000000190ull)
-#define CVMX_IPD_QOS4_RED_MARKS \
- CVMX_ADD_IO_SEG(0x00014F0000000198ull)
-#define CVMX_IPD_QOS5_RED_MARKS \
- CVMX_ADD_IO_SEG(0x00014F00000001A0ull)
-#define CVMX_IPD_QOS6_RED_MARKS \
- CVMX_ADD_IO_SEG(0x00014F00000001A8ull)
-#define CVMX_IPD_QOS7_RED_MARKS \
- CVMX_ADD_IO_SEG(0x00014F00000001B0ull)
-#define CVMX_IPD_QOSX_RED_MARKS(offset) \
- CVMX_ADD_IO_SEG(0x00014F0000000178ull + (((offset) & 7) * 8))
-#define CVMX_IPD_QUE0_FREE_PAGE_CNT \
- CVMX_ADD_IO_SEG(0x00014F0000000330ull)
-#define CVMX_IPD_RED_PORT_ENABLE \
- CVMX_ADD_IO_SEG(0x00014F00000002D8ull)
-#define CVMX_IPD_RED_PORT_ENABLE2 \
- CVMX_ADD_IO_SEG(0x00014F00000003A8ull)
-#define CVMX_IPD_RED_QUE0_PARAM \
- CVMX_ADD_IO_SEG(0x00014F00000002E0ull)
-#define CVMX_IPD_RED_QUE1_PARAM \
- CVMX_ADD_IO_SEG(0x00014F00000002E8ull)
-#define CVMX_IPD_RED_QUE2_PARAM \
- CVMX_ADD_IO_SEG(0x00014F00000002F0ull)
-#define CVMX_IPD_RED_QUE3_PARAM \
- CVMX_ADD_IO_SEG(0x00014F00000002F8ull)
-#define CVMX_IPD_RED_QUE4_PARAM \
- CVMX_ADD_IO_SEG(0x00014F0000000300ull)
-#define CVMX_IPD_RED_QUE5_PARAM \
- CVMX_ADD_IO_SEG(0x00014F0000000308ull)
-#define CVMX_IPD_RED_QUE6_PARAM \
- CVMX_ADD_IO_SEG(0x00014F0000000310ull)
-#define CVMX_IPD_RED_QUE7_PARAM \
- CVMX_ADD_IO_SEG(0x00014F0000000318ull)
-#define CVMX_IPD_RED_QUEX_PARAM(offset) \
- CVMX_ADD_IO_SEG(0x00014F00000002E0ull + (((offset) & 7) * 8))
-#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT \
- CVMX_ADD_IO_SEG(0x00014F0000000148ull)
-#define CVMX_IPD_SUB_PORT_FCS \
- CVMX_ADD_IO_SEG(0x00014F0000000170ull)
-#define CVMX_IPD_SUB_PORT_QOS_CNT \
- CVMX_ADD_IO_SEG(0x00014F0000000800ull)
-#define CVMX_IPD_WQE_FPA_QUEUE \
- CVMX_ADD_IO_SEG(0x00014F0000000020ull)
-#define CVMX_IPD_WQE_PTR_VALID \
- CVMX_ADD_IO_SEG(0x00014F0000000360ull)
+#define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull))
+#define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull))
+#define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull))
+#define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull))
+#define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull))
+#define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull))
+#define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull))
+#define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull))
+#define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull))
+#define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull))
+#define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull))
+#define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull))
+#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8)
+#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36)
+#define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40)
+#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36)
+#define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40)
+#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8)
+#define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8)
+#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull))
+#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull))
+#define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull))
+#define CVMX_IPD_PWP_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000340ull))
+#define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0)
+#define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1)
+#define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2)
+#define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3)
+#define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4)
+#define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5)
+#define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6)
+#define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7)
+#define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull))
+#define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull))
+#define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull))
+#define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0)
+#define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1)
+#define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2)
+#define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3)
+#define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4)
+#define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5)
+#define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6)
+#define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7)
+#define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull))
+#define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull))
+#define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull))
+#define CVMX_IPD_WQE_FPA_QUEUE (CVMX_ADD_IO_SEG(0x00014F0000000020ull))
+#define CVMX_IPD_WQE_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000360ull))
union cvmx_ipd_1st_mbuff_skip {
uint64_t u64;
@@ -144,6 +97,8 @@ union cvmx_ipd_1st_mbuff_skip {
struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1;
struct cvmx_ipd_1st_mbuff_skip_s cn58xx;
struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1;
+ struct cvmx_ipd_1st_mbuff_skip_s cn63xx;
+ struct cvmx_ipd_1st_mbuff_skip_s cn63xxp1;
};
union cvmx_ipd_1st_next_ptr_back {
@@ -163,6 +118,8 @@ union cvmx_ipd_1st_next_ptr_back {
struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1;
struct cvmx_ipd_1st_next_ptr_back_s cn58xx;
struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1;
+ struct cvmx_ipd_1st_next_ptr_back_s cn63xx;
+ struct cvmx_ipd_1st_next_ptr_back_s cn63xxp1;
};
union cvmx_ipd_2nd_next_ptr_back {
@@ -182,6 +139,8 @@ union cvmx_ipd_2nd_next_ptr_back {
struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1;
struct cvmx_ipd_2nd_next_ptr_back_s cn58xx;
struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1;
+ struct cvmx_ipd_2nd_next_ptr_back_s cn63xx;
+ struct cvmx_ipd_2nd_next_ptr_back_s cn63xxp1;
};
union cvmx_ipd_bist_status {
@@ -236,13 +195,15 @@ union cvmx_ipd_bist_status {
struct cvmx_ipd_bist_status_s cn56xxp1;
struct cvmx_ipd_bist_status_cn30xx cn58xx;
struct cvmx_ipd_bist_status_cn30xx cn58xxp1;
+ struct cvmx_ipd_bist_status_s cn63xx;
+ struct cvmx_ipd_bist_status_s cn63xxp1;
};
union cvmx_ipd_bp_prt_red_end {
uint64_t u64;
struct cvmx_ipd_bp_prt_red_end_s {
- uint64_t reserved_40_63:24;
- uint64_t prt_enb:40;
+ uint64_t reserved_44_63:20;
+ uint64_t prt_enb:44;
} s;
struct cvmx_ipd_bp_prt_red_end_cn30xx {
uint64_t reserved_36_63:28;
@@ -252,12 +213,17 @@ union cvmx_ipd_bp_prt_red_end {
struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx;
struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2;
struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx;
- struct cvmx_ipd_bp_prt_red_end_s cn52xx;
- struct cvmx_ipd_bp_prt_red_end_s cn52xxp1;
- struct cvmx_ipd_bp_prt_red_end_s cn56xx;
- struct cvmx_ipd_bp_prt_red_end_s cn56xxp1;
+ struct cvmx_ipd_bp_prt_red_end_cn52xx {
+ uint64_t reserved_40_63:24;
+ uint64_t prt_enb:40;
+ } cn52xx;
+ struct cvmx_ipd_bp_prt_red_end_cn52xx cn52xxp1;
+ struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xx;
+ struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xxp1;
struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx;
struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1;
+ struct cvmx_ipd_bp_prt_red_end_s cn63xx;
+ struct cvmx_ipd_bp_prt_red_end_s cn63xxp1;
};
union cvmx_ipd_clk_count {
@@ -276,12 +242,17 @@ union cvmx_ipd_clk_count {
struct cvmx_ipd_clk_count_s cn56xxp1;
struct cvmx_ipd_clk_count_s cn58xx;
struct cvmx_ipd_clk_count_s cn58xxp1;
+ struct cvmx_ipd_clk_count_s cn63xx;
+ struct cvmx_ipd_clk_count_s cn63xxp1;
};
union cvmx_ipd_ctl_status {
uint64_t u64;
struct cvmx_ipd_ctl_status_s {
- uint64_t reserved_15_63:49;
+ uint64_t reserved_18_63:46;
+ uint64_t use_sop:1;
+ uint64_t rst_done:1;
+ uint64_t clken:1;
uint64_t no_wptr:1;
uint64_t pq_apkt:1;
uint64_t pq_nabuf:1;
@@ -322,11 +293,27 @@ union cvmx_ipd_ctl_status {
uint64_t opc_mode:2;
uint64_t ipd_en:1;
} cn38xxp2;
- struct cvmx_ipd_ctl_status_s cn50xx;
- struct cvmx_ipd_ctl_status_s cn52xx;
- struct cvmx_ipd_ctl_status_s cn52xxp1;
- struct cvmx_ipd_ctl_status_s cn56xx;
- struct cvmx_ipd_ctl_status_s cn56xxp1;
+ struct cvmx_ipd_ctl_status_cn50xx {
+ uint64_t reserved_15_63:49;
+ uint64_t no_wptr:1;
+ uint64_t pq_apkt:1;
+ uint64_t pq_nabuf:1;
+ uint64_t ipd_full:1;
+ uint64_t pkt_off:1;
+ uint64_t len_m8:1;
+ uint64_t reset:1;
+ uint64_t addpkt:1;
+ uint64_t naddbuf:1;
+ uint64_t pkt_lend:1;
+ uint64_t wqe_lend:1;
+ uint64_t pbp_en:1;
+ uint64_t opc_mode:2;
+ uint64_t ipd_en:1;
+ } cn50xx;
+ struct cvmx_ipd_ctl_status_cn50xx cn52xx;
+ struct cvmx_ipd_ctl_status_cn50xx cn52xxp1;
+ struct cvmx_ipd_ctl_status_cn50xx cn56xx;
+ struct cvmx_ipd_ctl_status_cn50xx cn56xxp1;
struct cvmx_ipd_ctl_status_cn58xx {
uint64_t reserved_12_63:52;
uint64_t ipd_full:1;
@@ -342,6 +329,25 @@ union cvmx_ipd_ctl_status {
uint64_t ipd_en:1;
} cn58xx;
struct cvmx_ipd_ctl_status_cn58xx cn58xxp1;
+ struct cvmx_ipd_ctl_status_s cn63xx;
+ struct cvmx_ipd_ctl_status_cn63xxp1 {
+ uint64_t reserved_16_63:48;
+ uint64_t clken:1;
+ uint64_t no_wptr:1;
+ uint64_t pq_apkt:1;
+ uint64_t pq_nabuf:1;
+ uint64_t ipd_full:1;
+ uint64_t pkt_off:1;
+ uint64_t len_m8:1;
+ uint64_t reset:1;
+ uint64_t addpkt:1;
+ uint64_t naddbuf:1;
+ uint64_t pkt_lend:1;
+ uint64_t wqe_lend:1;
+ uint64_t pbp_en:1;
+ uint64_t opc_mode:2;
+ uint64_t ipd_en:1;
+ } cn63xxp1;
};
union cvmx_ipd_int_enb {
@@ -391,6 +397,8 @@ union cvmx_ipd_int_enb {
struct cvmx_ipd_int_enb_s cn56xxp1;
struct cvmx_ipd_int_enb_cn38xx cn58xx;
struct cvmx_ipd_int_enb_cn38xx cn58xxp1;
+ struct cvmx_ipd_int_enb_s cn63xx;
+ struct cvmx_ipd_int_enb_s cn63xxp1;
};
union cvmx_ipd_int_sum {
@@ -440,6 +448,8 @@ union cvmx_ipd_int_sum {
struct cvmx_ipd_int_sum_s cn56xxp1;
struct cvmx_ipd_int_sum_cn38xx cn58xx;
struct cvmx_ipd_int_sum_cn38xx cn58xxp1;
+ struct cvmx_ipd_int_sum_s cn63xx;
+ struct cvmx_ipd_int_sum_s cn63xxp1;
};
union cvmx_ipd_not_1st_mbuff_skip {
@@ -459,6 +469,8 @@ union cvmx_ipd_not_1st_mbuff_skip {
struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1;
struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx;
struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1;
+ struct cvmx_ipd_not_1st_mbuff_skip_s cn63xx;
+ struct cvmx_ipd_not_1st_mbuff_skip_s cn63xxp1;
};
union cvmx_ipd_packet_mbuff_size {
@@ -478,6 +490,8 @@ union cvmx_ipd_packet_mbuff_size {
struct cvmx_ipd_packet_mbuff_size_s cn56xxp1;
struct cvmx_ipd_packet_mbuff_size_s cn58xx;
struct cvmx_ipd_packet_mbuff_size_s cn58xxp1;
+ struct cvmx_ipd_packet_mbuff_size_s cn63xx;
+ struct cvmx_ipd_packet_mbuff_size_s cn63xxp1;
};
union cvmx_ipd_pkt_ptr_valid {
@@ -496,6 +510,8 @@ union cvmx_ipd_pkt_ptr_valid {
struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1;
struct cvmx_ipd_pkt_ptr_valid_s cn58xx;
struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1;
+ struct cvmx_ipd_pkt_ptr_valid_s cn63xx;
+ struct cvmx_ipd_pkt_ptr_valid_s cn63xxp1;
};
union cvmx_ipd_portx_bp_page_cnt {
@@ -516,6 +532,8 @@ union cvmx_ipd_portx_bp_page_cnt {
struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1;
struct cvmx_ipd_portx_bp_page_cnt_s cn58xx;
struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1;
+ struct cvmx_ipd_portx_bp_page_cnt_s cn63xx;
+ struct cvmx_ipd_portx_bp_page_cnt_s cn63xxp1;
};
union cvmx_ipd_portx_bp_page_cnt2 {
@@ -529,6 +547,19 @@ union cvmx_ipd_portx_bp_page_cnt2 {
struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1;
struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx;
struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1;
+ struct cvmx_ipd_portx_bp_page_cnt2_s cn63xx;
+ struct cvmx_ipd_portx_bp_page_cnt2_s cn63xxp1;
+};
+
+union cvmx_ipd_portx_bp_page_cnt3 {
+ uint64_t u64;
+ struct cvmx_ipd_portx_bp_page_cnt3_s {
+ uint64_t reserved_18_63:46;
+ uint64_t bp_enb:1;
+ uint64_t page_cnt:17;
+ } s;
+ struct cvmx_ipd_portx_bp_page_cnt3_s cn63xx;
+ struct cvmx_ipd_portx_bp_page_cnt3_s cn63xxp1;
};
union cvmx_ipd_port_bp_counters2_pairx {
@@ -541,6 +572,18 @@ union cvmx_ipd_port_bp_counters2_pairx {
struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1;
struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx;
struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1;
+ struct cvmx_ipd_port_bp_counters2_pairx_s cn63xx;
+ struct cvmx_ipd_port_bp_counters2_pairx_s cn63xxp1;
+};
+
+union cvmx_ipd_port_bp_counters3_pairx {
+ uint64_t u64;
+ struct cvmx_ipd_port_bp_counters3_pairx_s {
+ uint64_t reserved_25_63:39;
+ uint64_t cnt_val:25;
+ } s;
+ struct cvmx_ipd_port_bp_counters3_pairx_s cn63xx;
+ struct cvmx_ipd_port_bp_counters3_pairx_s cn63xxp1;
};
union cvmx_ipd_port_bp_counters_pairx {
@@ -560,6 +603,8 @@ union cvmx_ipd_port_bp_counters_pairx {
struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1;
struct cvmx_ipd_port_bp_counters_pairx_s cn58xx;
struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1;
+ struct cvmx_ipd_port_bp_counters_pairx_s cn63xx;
+ struct cvmx_ipd_port_bp_counters_pairx_s cn63xxp1;
};
union cvmx_ipd_port_qos_x_cnt {
@@ -572,6 +617,8 @@ union cvmx_ipd_port_qos_x_cnt {
struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1;
struct cvmx_ipd_port_qos_x_cnt_s cn56xx;
struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1;
+ struct cvmx_ipd_port_qos_x_cnt_s cn63xx;
+ struct cvmx_ipd_port_qos_x_cnt_s cn63xxp1;
};
union cvmx_ipd_port_qos_intx {
@@ -583,6 +630,8 @@ union cvmx_ipd_port_qos_intx {
struct cvmx_ipd_port_qos_intx_s cn52xxp1;
struct cvmx_ipd_port_qos_intx_s cn56xx;
struct cvmx_ipd_port_qos_intx_s cn56xxp1;
+ struct cvmx_ipd_port_qos_intx_s cn63xx;
+ struct cvmx_ipd_port_qos_intx_s cn63xxp1;
};
union cvmx_ipd_port_qos_int_enbx {
@@ -594,6 +643,8 @@ union cvmx_ipd_port_qos_int_enbx {
struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1;
struct cvmx_ipd_port_qos_int_enbx_s cn56xx;
struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1;
+ struct cvmx_ipd_port_qos_int_enbx_s cn63xx;
+ struct cvmx_ipd_port_qos_int_enbx_s cn63xxp1;
};
union cvmx_ipd_prc_hold_ptr_fifo_ctl {
@@ -616,6 +667,8 @@ union cvmx_ipd_prc_hold_ptr_fifo_ctl {
struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1;
struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx;
struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1;
+ struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xx;
+ struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xxp1;
};
union cvmx_ipd_prc_port_ptr_fifo_ctl {
@@ -637,6 +690,8 @@ union cvmx_ipd_prc_port_ptr_fifo_ctl {
struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1;
struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx;
struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1;
+ struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xx;
+ struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xxp1;
};
union cvmx_ipd_ptr_count {
@@ -660,6 +715,8 @@ union cvmx_ipd_ptr_count {
struct cvmx_ipd_ptr_count_s cn56xxp1;
struct cvmx_ipd_ptr_count_s cn58xx;
struct cvmx_ipd_ptr_count_s cn58xxp1;
+ struct cvmx_ipd_ptr_count_s cn63xx;
+ struct cvmx_ipd_ptr_count_s cn63xxp1;
};
union cvmx_ipd_pwp_ptr_fifo_ctl {
@@ -683,6 +740,8 @@ union cvmx_ipd_pwp_ptr_fifo_ctl {
struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1;
struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx;
struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1;
+ struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xx;
+ struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xxp1;
};
union cvmx_ipd_qosx_red_marks {
@@ -702,6 +761,8 @@ union cvmx_ipd_qosx_red_marks {
struct cvmx_ipd_qosx_red_marks_s cn56xxp1;
struct cvmx_ipd_qosx_red_marks_s cn58xx;
struct cvmx_ipd_qosx_red_marks_s cn58xxp1;
+ struct cvmx_ipd_qosx_red_marks_s cn63xx;
+ struct cvmx_ipd_qosx_red_marks_s cn63xxp1;
};
union cvmx_ipd_que0_free_page_cnt {
@@ -721,6 +782,8 @@ union cvmx_ipd_que0_free_page_cnt {
struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1;
struct cvmx_ipd_que0_free_page_cnt_s cn58xx;
struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1;
+ struct cvmx_ipd_que0_free_page_cnt_s cn63xx;
+ struct cvmx_ipd_que0_free_page_cnt_s cn63xxp1;
};
union cvmx_ipd_red_port_enable {
@@ -741,18 +804,25 @@ union cvmx_ipd_red_port_enable {
struct cvmx_ipd_red_port_enable_s cn56xxp1;
struct cvmx_ipd_red_port_enable_s cn58xx;
struct cvmx_ipd_red_port_enable_s cn58xxp1;
+ struct cvmx_ipd_red_port_enable_s cn63xx;
+ struct cvmx_ipd_red_port_enable_s cn63xxp1;
};
union cvmx_ipd_red_port_enable2 {
uint64_t u64;
struct cvmx_ipd_red_port_enable2_s {
+ uint64_t reserved_8_63:56;
+ uint64_t prt_enb:8;
+ } s;
+ struct cvmx_ipd_red_port_enable2_cn52xx {
uint64_t reserved_4_63:60;
uint64_t prt_enb:4;
- } s;
- struct cvmx_ipd_red_port_enable2_s cn52xx;
- struct cvmx_ipd_red_port_enable2_s cn52xxp1;
- struct cvmx_ipd_red_port_enable2_s cn56xx;
- struct cvmx_ipd_red_port_enable2_s cn56xxp1;
+ } cn52xx;
+ struct cvmx_ipd_red_port_enable2_cn52xx cn52xxp1;
+ struct cvmx_ipd_red_port_enable2_cn52xx cn56xx;
+ struct cvmx_ipd_red_port_enable2_cn52xx cn56xxp1;
+ struct cvmx_ipd_red_port_enable2_s cn63xx;
+ struct cvmx_ipd_red_port_enable2_s cn63xxp1;
};
union cvmx_ipd_red_quex_param {
@@ -775,6 +845,8 @@ union cvmx_ipd_red_quex_param {
struct cvmx_ipd_red_quex_param_s cn56xxp1;
struct cvmx_ipd_red_quex_param_s cn58xx;
struct cvmx_ipd_red_quex_param_s cn58xxp1;
+ struct cvmx_ipd_red_quex_param_s cn63xx;
+ struct cvmx_ipd_red_quex_param_s cn63xxp1;
};
union cvmx_ipd_sub_port_bp_page_cnt {
@@ -795,6 +867,8 @@ union cvmx_ipd_sub_port_bp_page_cnt {
struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1;
struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx;
struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1;
+ struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xx;
+ struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xxp1;
};
union cvmx_ipd_sub_port_fcs {
@@ -822,6 +896,8 @@ union cvmx_ipd_sub_port_fcs {
struct cvmx_ipd_sub_port_fcs_s cn56xxp1;
struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx;
struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1;
+ struct cvmx_ipd_sub_port_fcs_s cn63xx;
+ struct cvmx_ipd_sub_port_fcs_s cn63xxp1;
};
union cvmx_ipd_sub_port_qos_cnt {
@@ -835,6 +911,8 @@ union cvmx_ipd_sub_port_qos_cnt {
struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1;
struct cvmx_ipd_sub_port_qos_cnt_s cn56xx;
struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1;
+ struct cvmx_ipd_sub_port_qos_cnt_s cn63xx;
+ struct cvmx_ipd_sub_port_qos_cnt_s cn63xxp1;
};
union cvmx_ipd_wqe_fpa_queue {
@@ -854,6 +932,8 @@ union cvmx_ipd_wqe_fpa_queue {
struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1;
struct cvmx_ipd_wqe_fpa_queue_s cn58xx;
struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1;
+ struct cvmx_ipd_wqe_fpa_queue_s cn63xx;
+ struct cvmx_ipd_wqe_fpa_queue_s cn63xxp1;
};
union cvmx_ipd_wqe_ptr_valid {
@@ -872,6 +952,8 @@ union cvmx_ipd_wqe_ptr_valid {
struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1;
struct cvmx_ipd_wqe_ptr_valid_s cn58xx;
struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1;
+ struct cvmx_ipd_wqe_ptr_valid_s cn63xx;
+ struct cvmx_ipd_wqe_ptr_valid_s cn63xxp1;
};
#endif
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-l2c-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
index 337583842b51..7a50a0beb472 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,70 +28,113 @@
#ifndef __CVMX_L2C_DEFS_H__
#define __CVMX_L2C_DEFS_H__
-#define CVMX_L2C_BST0 \
- CVMX_ADD_IO_SEG(0x00011800800007F8ull)
-#define CVMX_L2C_BST1 \
- CVMX_ADD_IO_SEG(0x00011800800007F0ull)
-#define CVMX_L2C_BST2 \
- CVMX_ADD_IO_SEG(0x00011800800007E8ull)
-#define CVMX_L2C_CFG \
- CVMX_ADD_IO_SEG(0x0001180080000000ull)
-#define CVMX_L2C_DBG \
- CVMX_ADD_IO_SEG(0x0001180080000030ull)
-#define CVMX_L2C_DUT \
- CVMX_ADD_IO_SEG(0x0001180080000050ull)
-#define CVMX_L2C_GRPWRR0 \
- CVMX_ADD_IO_SEG(0x00011800800000C8ull)
-#define CVMX_L2C_GRPWRR1 \
- CVMX_ADD_IO_SEG(0x00011800800000D0ull)
-#define CVMX_L2C_INT_EN \
- CVMX_ADD_IO_SEG(0x0001180080000100ull)
-#define CVMX_L2C_INT_STAT \
- CVMX_ADD_IO_SEG(0x00011800800000F8ull)
-#define CVMX_L2C_LCKBASE \
- CVMX_ADD_IO_SEG(0x0001180080000058ull)
-#define CVMX_L2C_LCKOFF \
- CVMX_ADD_IO_SEG(0x0001180080000060ull)
-#define CVMX_L2C_LFB0 \
- CVMX_ADD_IO_SEG(0x0001180080000038ull)
-#define CVMX_L2C_LFB1 \
- CVMX_ADD_IO_SEG(0x0001180080000040ull)
-#define CVMX_L2C_LFB2 \
- CVMX_ADD_IO_SEG(0x0001180080000048ull)
-#define CVMX_L2C_LFB3 \
- CVMX_ADD_IO_SEG(0x00011800800000B8ull)
-#define CVMX_L2C_OOB \
- CVMX_ADD_IO_SEG(0x00011800800000D8ull)
-#define CVMX_L2C_OOB1 \
- CVMX_ADD_IO_SEG(0x00011800800000E0ull)
-#define CVMX_L2C_OOB2 \
- CVMX_ADD_IO_SEG(0x00011800800000E8ull)
-#define CVMX_L2C_OOB3 \
- CVMX_ADD_IO_SEG(0x00011800800000F0ull)
-#define CVMX_L2C_PFC0 \
- CVMX_ADD_IO_SEG(0x0001180080000098ull)
-#define CVMX_L2C_PFC1 \
- CVMX_ADD_IO_SEG(0x00011800800000A0ull)
-#define CVMX_L2C_PFC2 \
- CVMX_ADD_IO_SEG(0x00011800800000A8ull)
-#define CVMX_L2C_PFC3 \
- CVMX_ADD_IO_SEG(0x00011800800000B0ull)
-#define CVMX_L2C_PFCTL \
- CVMX_ADD_IO_SEG(0x0001180080000090ull)
-#define CVMX_L2C_PFCX(offset) \
- CVMX_ADD_IO_SEG(0x0001180080000098ull + (((offset) & 3) * 8))
-#define CVMX_L2C_PPGRP \
- CVMX_ADD_IO_SEG(0x00011800800000C0ull)
-#define CVMX_L2C_SPAR0 \
- CVMX_ADD_IO_SEG(0x0001180080000068ull)
-#define CVMX_L2C_SPAR1 \
- CVMX_ADD_IO_SEG(0x0001180080000070ull)
-#define CVMX_L2C_SPAR2 \
- CVMX_ADD_IO_SEG(0x0001180080000078ull)
-#define CVMX_L2C_SPAR3 \
- CVMX_ADD_IO_SEG(0x0001180080000080ull)
-#define CVMX_L2C_SPAR4 \
- CVMX_ADD_IO_SEG(0x0001180080000088ull)
+#define CVMX_L2C_BIG_CTL (CVMX_ADD_IO_SEG(0x0001180080800030ull))
+#define CVMX_L2C_BST (CVMX_ADD_IO_SEG(0x00011800808007F8ull))
+#define CVMX_L2C_BST0 (CVMX_ADD_IO_SEG(0x00011800800007F8ull))
+#define CVMX_L2C_BST1 (CVMX_ADD_IO_SEG(0x00011800800007F0ull))
+#define CVMX_L2C_BST2 (CVMX_ADD_IO_SEG(0x00011800800007E8ull))
+#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull))
+#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull))
+#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull))
+#define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull))
+#define CVMX_L2C_COP0_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080940000ull) + ((offset) & 16383) * 8)
+#define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull))
+#define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull))
+#define CVMX_L2C_DUT (CVMX_ADD_IO_SEG(0x0001180080000050ull))
+#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 2047) * 8)
+#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull))
+#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull))
+#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull))
+#define CVMX_L2C_ERR_XMC (CVMX_ADD_IO_SEG(0x00011800808007D8ull))
+#define CVMX_L2C_GRPWRR0 (CVMX_ADD_IO_SEG(0x00011800800000C8ull))
+#define CVMX_L2C_GRPWRR1 (CVMX_ADD_IO_SEG(0x00011800800000D0ull))
+#define CVMX_L2C_INT_EN (CVMX_ADD_IO_SEG(0x0001180080000100ull))
+#define CVMX_L2C_INT_ENA (CVMX_ADD_IO_SEG(0x0001180080800020ull))
+#define CVMX_L2C_INT_REG (CVMX_ADD_IO_SEG(0x0001180080800018ull))
+#define CVMX_L2C_INT_STAT (CVMX_ADD_IO_SEG(0x00011800800000F8ull))
+#define CVMX_L2C_IOCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800420ull))
+#define CVMX_L2C_IORX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800428ull))
+#define CVMX_L2C_LCKBASE (CVMX_ADD_IO_SEG(0x0001180080000058ull))
+#define CVMX_L2C_LCKOFF (CVMX_ADD_IO_SEG(0x0001180080000060ull))
+#define CVMX_L2C_LFB0 (CVMX_ADD_IO_SEG(0x0001180080000038ull))
+#define CVMX_L2C_LFB1 (CVMX_ADD_IO_SEG(0x0001180080000040ull))
+#define CVMX_L2C_LFB2 (CVMX_ADD_IO_SEG(0x0001180080000048ull))
+#define CVMX_L2C_LFB3 (CVMX_ADD_IO_SEG(0x00011800800000B8ull))
+#define CVMX_L2C_OOB (CVMX_ADD_IO_SEG(0x00011800800000D8ull))
+#define CVMX_L2C_OOB1 (CVMX_ADD_IO_SEG(0x00011800800000E0ull))
+#define CVMX_L2C_OOB2 (CVMX_ADD_IO_SEG(0x00011800800000E8ull))
+#define CVMX_L2C_OOB3 (CVMX_ADD_IO_SEG(0x00011800800000F0ull))
+#define CVMX_L2C_PFC0 CVMX_L2C_PFCX(0)
+#define CVMX_L2C_PFC1 CVMX_L2C_PFCX(1)
+#define CVMX_L2C_PFC2 CVMX_L2C_PFCX(2)
+#define CVMX_L2C_PFC3 CVMX_L2C_PFCX(3)
+#define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull))
+#define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + ((offset) & 3) * 8)
+#define CVMX_L2C_PPGRP (CVMX_ADD_IO_SEG(0x00011800800000C0ull))
+#define CVMX_L2C_QOS_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080880200ull))
+#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 7) * 8)
+#define CVMX_L2C_QOS_WGT (CVMX_ADD_IO_SEG(0x0001180080800008ull))
+#define CVMX_L2C_RSCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800410ull))
+#define CVMX_L2C_RSDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800418ull))
+#define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull))
+#define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull))
+#define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull))
+#define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull))
+#define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull))
+#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull))
+#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull))
+#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull))
+#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull))
+#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull))
+#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull))
+#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull))
+#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull))
+#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull))
+#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull))
+#define CVMX_L2C_VER_ID (CVMX_ADD_IO_SEG(0x00011800808007E0ull))
+#define CVMX_L2C_VER_IOB (CVMX_ADD_IO_SEG(0x00011800808007F0ull))
+#define CVMX_L2C_VER_MSC (CVMX_ADD_IO_SEG(0x00011800808007D0ull))
+#define CVMX_L2C_VER_PP (CVMX_ADD_IO_SEG(0x00011800808007E8ull))
+#define CVMX_L2C_VIRTID_IOBX(block_id) (CVMX_ADD_IO_SEG(0x00011800808C0200ull))
+#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 7) * 8)
+#define CVMX_L2C_VRT_CTL (CVMX_ADD_IO_SEG(0x0001180080800010ull))
+#define CVMX_L2C_VRT_MEMX(offset) (CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8)
+#define CVMX_L2C_WPAR_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080840200ull))
+#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 7) * 8)
+#define CVMX_L2C_XMCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800400ull))
+#define CVMX_L2C_XMC_CMD (CVMX_ADD_IO_SEG(0x0001180080800028ull))
+#define CVMX_L2C_XMDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800408ull))
+
+union cvmx_l2c_big_ctl {
+ uint64_t u64;
+ struct cvmx_l2c_big_ctl_s {
+ uint64_t reserved_8_63:56;
+ uint64_t maxdram:4;
+ uint64_t reserved_1_3:3;
+ uint64_t disable:1;
+ } s;
+ struct cvmx_l2c_big_ctl_s cn63xx;
+};
+
+union cvmx_l2c_bst {
+ uint64_t u64;
+ struct cvmx_l2c_bst_s {
+ uint64_t reserved_38_63:26;
+ uint64_t dutfl:6;
+ uint64_t reserved_17_31:15;
+ uint64_t ioccmdfl:1;
+ uint64_t reserved_13_15:3;
+ uint64_t iocdatfl:1;
+ uint64_t reserved_9_11:3;
+ uint64_t dutresfl:1;
+ uint64_t reserved_5_7:3;
+ uint64_t vrtfl:1;
+ uint64_t reserved_1_3:3;
+ uint64_t tdffl:1;
+ } s;
+ struct cvmx_l2c_bst_s cn63xx;
+ struct cvmx_l2c_bst_s cn63xxp1;
+};
union cvmx_l2c_bst0 {
uint64_t u64;
@@ -253,6 +296,48 @@ union cvmx_l2c_bst2 {
struct cvmx_l2c_bst2_cn56xx cn58xxp1;
};
+union cvmx_l2c_bst_memx {
+ uint64_t u64;
+ struct cvmx_l2c_bst_memx_s {
+ uint64_t start_bist:1;
+ uint64_t clear_bist:1;
+ uint64_t reserved_5_61:57;
+ uint64_t rdffl:1;
+ uint64_t vbffl:4;
+ } s;
+ struct cvmx_l2c_bst_memx_s cn63xx;
+ struct cvmx_l2c_bst_memx_s cn63xxp1;
+};
+
+union cvmx_l2c_bst_tdtx {
+ uint64_t u64;
+ struct cvmx_l2c_bst_tdtx_s {
+ uint64_t reserved_32_63:32;
+ uint64_t fbfrspfl:8;
+ uint64_t sbffl:8;
+ uint64_t fbffl:8;
+ uint64_t l2dfl:8;
+ } s;
+ struct cvmx_l2c_bst_tdtx_s cn63xx;
+ struct cvmx_l2c_bst_tdtx_cn63xxp1 {
+ uint64_t reserved_24_63:40;
+ uint64_t sbffl:8;
+ uint64_t fbffl:8;
+ uint64_t l2dfl:8;
+ } cn63xxp1;
+};
+
+union cvmx_l2c_bst_ttgx {
+ uint64_t u64;
+ struct cvmx_l2c_bst_ttgx_s {
+ uint64_t reserved_17_63:47;
+ uint64_t lrufl:1;
+ uint64_t tagfl:16;
+ } s;
+ struct cvmx_l2c_bst_ttgx_s cn63xx;
+ struct cvmx_l2c_bst_ttgx_s cn63xxp1;
+};
+
union cvmx_l2c_cfg {
uint64_t u64;
struct cvmx_l2c_cfg_s {
@@ -333,6 +418,49 @@ union cvmx_l2c_cfg {
} cn58xxp1;
};
+union cvmx_l2c_cop0_mapx {
+ uint64_t u64;
+ struct cvmx_l2c_cop0_mapx_s {
+ uint64_t data:64;
+ } s;
+ struct cvmx_l2c_cop0_mapx_s cn63xx;
+ struct cvmx_l2c_cop0_mapx_s cn63xxp1;
+};
+
+union cvmx_l2c_ctl {
+ uint64_t u64;
+ struct cvmx_l2c_ctl_s {
+ uint64_t reserved_28_63:36;
+ uint64_t disstgl2i:1;
+ uint64_t l2dfsbe:1;
+ uint64_t l2dfdbe:1;
+ uint64_t discclk:1;
+ uint64_t maxvab:4;
+ uint64_t maxlfb:4;
+ uint64_t rsp_arb_mode:1;
+ uint64_t xmc_arb_mode:1;
+ uint64_t ef_ena:1;
+ uint64_t ef_cnt:7;
+ uint64_t vab_thresh:4;
+ uint64_t disecc:1;
+ uint64_t disidxalias:1;
+ } s;
+ struct cvmx_l2c_ctl_s cn63xx;
+ struct cvmx_l2c_ctl_cn63xxp1 {
+ uint64_t reserved_25_63:39;
+ uint64_t discclk:1;
+ uint64_t maxvab:4;
+ uint64_t maxlfb:4;
+ uint64_t rsp_arb_mode:1;
+ uint64_t xmc_arb_mode:1;
+ uint64_t ef_ena:1;
+ uint64_t ef_cnt:7;
+ uint64_t vab_thresh:4;
+ uint64_t disecc:1;
+ uint64_t disidxalias:1;
+ } cn63xxp1;
+};
+
union cvmx_l2c_dbg {
uint64_t u64;
struct cvmx_l2c_dbg_s {
@@ -349,7 +477,9 @@ union cvmx_l2c_dbg {
uint64_t reserved_13_63:51;
uint64_t lfb_enum:2;
uint64_t lfb_dmp:1;
- uint64_t reserved_5_9:5;
+ uint64_t reserved_7_9:3;
+ uint64_t ppnum:1;
+ uint64_t reserved_5_5:1;
uint64_t set:2;
uint64_t finv:1;
uint64_t l2d:1;
@@ -420,6 +550,79 @@ union cvmx_l2c_dut {
struct cvmx_l2c_dut_s cn58xxp1;
};
+union cvmx_l2c_dut_mapx {
+ uint64_t u64;
+ struct cvmx_l2c_dut_mapx_s {
+ uint64_t reserved_38_63:26;
+ uint64_t tag:28;
+ uint64_t reserved_1_9:9;
+ uint64_t valid:1;
+ } s;
+ struct cvmx_l2c_dut_mapx_s cn63xx;
+ struct cvmx_l2c_dut_mapx_s cn63xxp1;
+};
+
+union cvmx_l2c_err_tdtx {
+ uint64_t u64;
+ struct cvmx_l2c_err_tdtx_s {
+ uint64_t dbe:1;
+ uint64_t sbe:1;
+ uint64_t vdbe:1;
+ uint64_t vsbe:1;
+ uint64_t syn:10;
+ uint64_t reserved_21_49:29;
+ uint64_t wayidx:17;
+ uint64_t reserved_2_3:2;
+ uint64_t type:2;
+ } s;
+ struct cvmx_l2c_err_tdtx_s cn63xx;
+ struct cvmx_l2c_err_tdtx_s cn63xxp1;
+};
+
+union cvmx_l2c_err_ttgx {
+ uint64_t u64;
+ struct cvmx_l2c_err_ttgx_s {
+ uint64_t dbe:1;
+ uint64_t sbe:1;
+ uint64_t noway:1;
+ uint64_t reserved_56_60:5;
+ uint64_t syn:6;
+ uint64_t reserved_21_49:29;
+ uint64_t wayidx:14;
+ uint64_t reserved_2_6:5;
+ uint64_t type:2;
+ } s;
+ struct cvmx_l2c_err_ttgx_s cn63xx;
+ struct cvmx_l2c_err_ttgx_s cn63xxp1;
+};
+
+union cvmx_l2c_err_vbfx {
+ uint64_t u64;
+ struct cvmx_l2c_err_vbfx_s {
+ uint64_t reserved_62_63:2;
+ uint64_t vdbe:1;
+ uint64_t vsbe:1;
+ uint64_t vsyn:10;
+ uint64_t reserved_2_49:48;
+ uint64_t type:2;
+ } s;
+ struct cvmx_l2c_err_vbfx_s cn63xx;
+ struct cvmx_l2c_err_vbfx_s cn63xxp1;
+};
+
+union cvmx_l2c_err_xmc {
+ uint64_t u64;
+ struct cvmx_l2c_err_xmc_s {
+ uint64_t cmd:6;
+ uint64_t reserved_52_57:6;
+ uint64_t sid:4;
+ uint64_t reserved_38_47:10;
+ uint64_t addr:38;
+ } s;
+ struct cvmx_l2c_err_xmc_s cn63xx;
+ struct cvmx_l2c_err_xmc_s cn63xxp1;
+};
+
union cvmx_l2c_grpwrr0 {
uint64_t u64;
struct cvmx_l2c_grpwrr0_s {
@@ -464,6 +667,60 @@ union cvmx_l2c_int_en {
struct cvmx_l2c_int_en_s cn56xxp1;
};
+union cvmx_l2c_int_ena {
+ uint64_t u64;
+ struct cvmx_l2c_int_ena_s {
+ uint64_t reserved_8_63:56;
+ uint64_t bigrd:1;
+ uint64_t bigwr:1;
+ uint64_t vrtpe:1;
+ uint64_t vrtadrng:1;
+ uint64_t vrtidrng:1;
+ uint64_t vrtwr:1;
+ uint64_t holewr:1;
+ uint64_t holerd:1;
+ } s;
+ struct cvmx_l2c_int_ena_s cn63xx;
+ struct cvmx_l2c_int_ena_cn63xxp1 {
+ uint64_t reserved_6_63:58;
+ uint64_t vrtpe:1;
+ uint64_t vrtadrng:1;
+ uint64_t vrtidrng:1;
+ uint64_t vrtwr:1;
+ uint64_t holewr:1;
+ uint64_t holerd:1;
+ } cn63xxp1;
+};
+
+union cvmx_l2c_int_reg {
+ uint64_t u64;
+ struct cvmx_l2c_int_reg_s {
+ uint64_t reserved_17_63:47;
+ uint64_t tad0:1;
+ uint64_t reserved_8_15:8;
+ uint64_t bigrd:1;
+ uint64_t bigwr:1;
+ uint64_t vrtpe:1;
+ uint64_t vrtadrng:1;
+ uint64_t vrtidrng:1;
+ uint64_t vrtwr:1;
+ uint64_t holewr:1;
+ uint64_t holerd:1;
+ } s;
+ struct cvmx_l2c_int_reg_s cn63xx;
+ struct cvmx_l2c_int_reg_cn63xxp1 {
+ uint64_t reserved_17_63:47;
+ uint64_t tad0:1;
+ uint64_t reserved_6_15:10;
+ uint64_t vrtpe:1;
+ uint64_t vrtadrng:1;
+ uint64_t vrtidrng:1;
+ uint64_t vrtwr:1;
+ uint64_t holewr:1;
+ uint64_t holerd:1;
+ } cn63xxp1;
+};
+
union cvmx_l2c_int_stat {
uint64_t u64;
struct cvmx_l2c_int_stat_s {
@@ -484,6 +741,24 @@ union cvmx_l2c_int_stat {
struct cvmx_l2c_int_stat_s cn56xxp1;
};
+union cvmx_l2c_iocx_pfc {
+ uint64_t u64;
+ struct cvmx_l2c_iocx_pfc_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_iocx_pfc_s cn63xx;
+ struct cvmx_l2c_iocx_pfc_s cn63xxp1;
+};
+
+union cvmx_l2c_iorx_pfc {
+ uint64_t u64;
+ struct cvmx_l2c_iorx_pfc_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_iorx_pfc_s cn63xx;
+ struct cvmx_l2c_iorx_pfc_s cn63xxp1;
+};
+
union cvmx_l2c_lckbase {
uint64_t u64;
struct cvmx_l2c_lckbase_s {
@@ -855,6 +1130,59 @@ union cvmx_l2c_ppgrp {
struct cvmx_l2c_ppgrp_s cn56xxp1;
};
+union cvmx_l2c_qos_iobx {
+ uint64_t u64;
+ struct cvmx_l2c_qos_iobx_s {
+ uint64_t reserved_6_63:58;
+ uint64_t dwblvl:2;
+ uint64_t reserved_2_3:2;
+ uint64_t lvl:2;
+ } s;
+ struct cvmx_l2c_qos_iobx_s cn63xx;
+ struct cvmx_l2c_qos_iobx_s cn63xxp1;
+};
+
+union cvmx_l2c_qos_ppx {
+ uint64_t u64;
+ struct cvmx_l2c_qos_ppx_s {
+ uint64_t reserved_2_63:62;
+ uint64_t lvl:2;
+ } s;
+ struct cvmx_l2c_qos_ppx_s cn63xx;
+ struct cvmx_l2c_qos_ppx_s cn63xxp1;
+};
+
+union cvmx_l2c_qos_wgt {
+ uint64_t u64;
+ struct cvmx_l2c_qos_wgt_s {
+ uint64_t reserved_32_63:32;
+ uint64_t wgt3:8;
+ uint64_t wgt2:8;
+ uint64_t wgt1:8;
+ uint64_t wgt0:8;
+ } s;
+ struct cvmx_l2c_qos_wgt_s cn63xx;
+ struct cvmx_l2c_qos_wgt_s cn63xxp1;
+};
+
+union cvmx_l2c_rscx_pfc {
+ uint64_t u64;
+ struct cvmx_l2c_rscx_pfc_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_rscx_pfc_s cn63xx;
+ struct cvmx_l2c_rscx_pfc_s cn63xxp1;
+};
+
+union cvmx_l2c_rsdx_pfc {
+ uint64_t u64;
+ struct cvmx_l2c_rsdx_pfc_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_rsdx_pfc_s cn63xx;
+ struct cvmx_l2c_rsdx_pfc_s cn63xxp1;
+};
+
union cvmx_l2c_spar0 {
uint64_t u64;
struct cvmx_l2c_spar0_s {
@@ -960,4 +1288,282 @@ union cvmx_l2c_spar4 {
struct cvmx_l2c_spar4_s cn58xxp1;
};
+union cvmx_l2c_tadx_ecc0 {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_ecc0_s {
+ uint64_t reserved_58_63:6;
+ uint64_t ow3ecc:10;
+ uint64_t reserved_42_47:6;
+ uint64_t ow2ecc:10;
+ uint64_t reserved_26_31:6;
+ uint64_t ow1ecc:10;
+ uint64_t reserved_10_15:6;
+ uint64_t ow0ecc:10;
+ } s;
+ struct cvmx_l2c_tadx_ecc0_s cn63xx;
+ struct cvmx_l2c_tadx_ecc0_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_ecc1 {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_ecc1_s {
+ uint64_t reserved_58_63:6;
+ uint64_t ow7ecc:10;
+ uint64_t reserved_42_47:6;
+ uint64_t ow6ecc:10;
+ uint64_t reserved_26_31:6;
+ uint64_t ow5ecc:10;
+ uint64_t reserved_10_15:6;
+ uint64_t ow4ecc:10;
+ } s;
+ struct cvmx_l2c_tadx_ecc1_s cn63xx;
+ struct cvmx_l2c_tadx_ecc1_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_ien {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_ien_s {
+ uint64_t reserved_9_63:55;
+ uint64_t wrdislmc:1;
+ uint64_t rddislmc:1;
+ uint64_t noway:1;
+ uint64_t vbfdbe:1;
+ uint64_t vbfsbe:1;
+ uint64_t tagdbe:1;
+ uint64_t tagsbe:1;
+ uint64_t l2ddbe:1;
+ uint64_t l2dsbe:1;
+ } s;
+ struct cvmx_l2c_tadx_ien_s cn63xx;
+ struct cvmx_l2c_tadx_ien_cn63xxp1 {
+ uint64_t reserved_7_63:57;
+ uint64_t noway:1;
+ uint64_t vbfdbe:1;
+ uint64_t vbfsbe:1;
+ uint64_t tagdbe:1;
+ uint64_t tagsbe:1;
+ uint64_t l2ddbe:1;
+ uint64_t l2dsbe:1;
+ } cn63xxp1;
+};
+
+union cvmx_l2c_tadx_int {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_int_s {
+ uint64_t reserved_9_63:55;
+ uint64_t wrdislmc:1;
+ uint64_t rddislmc:1;
+ uint64_t noway:1;
+ uint64_t vbfdbe:1;
+ uint64_t vbfsbe:1;
+ uint64_t tagdbe:1;
+ uint64_t tagsbe:1;
+ uint64_t l2ddbe:1;
+ uint64_t l2dsbe:1;
+ } s;
+ struct cvmx_l2c_tadx_int_s cn63xx;
+};
+
+union cvmx_l2c_tadx_pfc0 {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_pfc0_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_tadx_pfc0_s cn63xx;
+ struct cvmx_l2c_tadx_pfc0_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_pfc1 {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_pfc1_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_tadx_pfc1_s cn63xx;
+ struct cvmx_l2c_tadx_pfc1_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_pfc2 {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_pfc2_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_tadx_pfc2_s cn63xx;
+ struct cvmx_l2c_tadx_pfc2_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_pfc3 {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_pfc3_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_tadx_pfc3_s cn63xx;
+ struct cvmx_l2c_tadx_pfc3_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_prf {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_prf_s {
+ uint64_t reserved_32_63:32;
+ uint64_t cnt3sel:8;
+ uint64_t cnt2sel:8;
+ uint64_t cnt1sel:8;
+ uint64_t cnt0sel:8;
+ } s;
+ struct cvmx_l2c_tadx_prf_s cn63xx;
+ struct cvmx_l2c_tadx_prf_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_tag {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_tag_s {
+ uint64_t reserved_46_63:18;
+ uint64_t ecc:6;
+ uint64_t reserved_36_39:4;
+ uint64_t tag:19;
+ uint64_t reserved_4_16:13;
+ uint64_t use:1;
+ uint64_t valid:1;
+ uint64_t dirty:1;
+ uint64_t lock:1;
+ } s;
+ struct cvmx_l2c_tadx_tag_s cn63xx;
+ struct cvmx_l2c_tadx_tag_s cn63xxp1;
+};
+
+union cvmx_l2c_ver_id {
+ uint64_t u64;
+ struct cvmx_l2c_ver_id_s {
+ uint64_t mask:64;
+ } s;
+ struct cvmx_l2c_ver_id_s cn63xx;
+ struct cvmx_l2c_ver_id_s cn63xxp1;
+};
+
+union cvmx_l2c_ver_iob {
+ uint64_t u64;
+ struct cvmx_l2c_ver_iob_s {
+ uint64_t reserved_1_63:63;
+ uint64_t mask:1;
+ } s;
+ struct cvmx_l2c_ver_iob_s cn63xx;
+ struct cvmx_l2c_ver_iob_s cn63xxp1;
+};
+
+union cvmx_l2c_ver_msc {
+ uint64_t u64;
+ struct cvmx_l2c_ver_msc_s {
+ uint64_t reserved_2_63:62;
+ uint64_t invl2:1;
+ uint64_t dwb:1;
+ } s;
+ struct cvmx_l2c_ver_msc_s cn63xx;
+};
+
+union cvmx_l2c_ver_pp {
+ uint64_t u64;
+ struct cvmx_l2c_ver_pp_s {
+ uint64_t reserved_6_63:58;
+ uint64_t mask:6;
+ } s;
+ struct cvmx_l2c_ver_pp_s cn63xx;
+ struct cvmx_l2c_ver_pp_s cn63xxp1;
+};
+
+union cvmx_l2c_virtid_iobx {
+ uint64_t u64;
+ struct cvmx_l2c_virtid_iobx_s {
+ uint64_t reserved_14_63:50;
+ uint64_t dwbid:6;
+ uint64_t reserved_6_7:2;
+ uint64_t id:6;
+ } s;
+ struct cvmx_l2c_virtid_iobx_s cn63xx;
+ struct cvmx_l2c_virtid_iobx_s cn63xxp1;
+};
+
+union cvmx_l2c_virtid_ppx {
+ uint64_t u64;
+ struct cvmx_l2c_virtid_ppx_s {
+ uint64_t reserved_6_63:58;
+ uint64_t id:6;
+ } s;
+ struct cvmx_l2c_virtid_ppx_s cn63xx;
+ struct cvmx_l2c_virtid_ppx_s cn63xxp1;
+};
+
+union cvmx_l2c_vrt_ctl {
+ uint64_t u64;
+ struct cvmx_l2c_vrt_ctl_s {
+ uint64_t reserved_9_63:55;
+ uint64_t ooberr:1;
+ uint64_t reserved_7_7:1;
+ uint64_t memsz:3;
+ uint64_t numid:3;
+ uint64_t enable:1;
+ } s;
+ struct cvmx_l2c_vrt_ctl_s cn63xx;
+ struct cvmx_l2c_vrt_ctl_s cn63xxp1;
+};
+
+union cvmx_l2c_vrt_memx {
+ uint64_t u64;
+ struct cvmx_l2c_vrt_memx_s {
+ uint64_t reserved_36_63:28;
+ uint64_t parity:4;
+ uint64_t data:32;
+ } s;
+ struct cvmx_l2c_vrt_memx_s cn63xx;
+ struct cvmx_l2c_vrt_memx_s cn63xxp1;
+};
+
+union cvmx_l2c_wpar_iobx {
+ uint64_t u64;
+ struct cvmx_l2c_wpar_iobx_s {
+ uint64_t reserved_16_63:48;
+ uint64_t mask:16;
+ } s;
+ struct cvmx_l2c_wpar_iobx_s cn63xx;
+ struct cvmx_l2c_wpar_iobx_s cn63xxp1;
+};
+
+union cvmx_l2c_wpar_ppx {
+ uint64_t u64;
+ struct cvmx_l2c_wpar_ppx_s {
+ uint64_t reserved_16_63:48;
+ uint64_t mask:16;
+ } s;
+ struct cvmx_l2c_wpar_ppx_s cn63xx;
+ struct cvmx_l2c_wpar_ppx_s cn63xxp1;
+};
+
+union cvmx_l2c_xmcx_pfc {
+ uint64_t u64;
+ struct cvmx_l2c_xmcx_pfc_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_xmcx_pfc_s cn63xx;
+ struct cvmx_l2c_xmcx_pfc_s cn63xxp1;
+};
+
+union cvmx_l2c_xmc_cmd {
+ uint64_t u64;
+ struct cvmx_l2c_xmc_cmd_s {
+ uint64_t inuse:1;
+ uint64_t cmd:6;
+ uint64_t reserved_38_56:19;
+ uint64_t addr:38;
+ } s;
+ struct cvmx_l2c_xmc_cmd_s cn63xx;
+ struct cvmx_l2c_xmc_cmd_s cn63xxp1;
+};
+
+union cvmx_l2c_xmdx_pfc {
+ uint64_t u64;
+ struct cvmx_l2c_xmdx_pfc_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_xmdx_pfc_s cn63xx;
+ struct cvmx_l2c_xmdx_pfc_s cn63xxp1;
+};
+
#endif
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-l2c.h b/trunk/arch/mips/include/asm/octeon/cvmx-l2c.h
index 2a8c0902ea50..0b32c5b118e2 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-l2c.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-l2c.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -26,7 +26,6 @@
***********************license end**************************************/
/*
- *
* Interface to the Level 2 Cache (L2C) control, measurement, and debugging
* facilities.
*/
@@ -34,93 +33,126 @@
#ifndef __CVMX_L2C_H__
#define __CVMX_L2C_H__
-/* Deprecated macro, use function */
-#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc()
-
-/* Deprecated macro, use function */
-#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits()
+#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro, use function */
+#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro, use function */
+#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro, use function */
-/* Deprecated macro, use function */
-#define CVMX_L2_SETS cvmx_l2c_get_num_sets()
#define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */
#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
/* Defines for index aliasing computations */
-#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT \
- (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
+#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
+#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
+#define CVMX_L2C_MEMBANK_SELECT_SIZE 4096
-#define CVMX_L2C_ALIAS_MASK \
- (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
+/* Defines for Virtualizations, valid only from Octeon II onwards. */
+#define CVMX_L2C_VRT_MAX_VIRTID_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 64 : 0)
+#define CVMX_L2C_VRT_MAX_MEMSZ_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 32 : 0)
union cvmx_l2c_tag {
uint64_t u64;
struct {
uint64_t reserved:28;
- uint64_t V:1; /* Line valid */
- uint64_t D:1; /* Line dirty */
- uint64_t L:1; /* Line locked */
- uint64_t U:1; /* Use, LRU eviction */
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
uint64_t addr:32; /* Phys mem (not all bits valid) */
} s;
};
+/* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
+#define CVMX_L2C_TADS 1
+
/* L2C Performance Counter events. */
enum cvmx_l2c_event {
- CVMX_L2C_EVENT_CYCLES = 0,
- CVMX_L2C_EVENT_INSTRUCTION_MISS = 1,
- CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
- CVMX_L2C_EVENT_DATA_MISS = 3,
- CVMX_L2C_EVENT_DATA_HIT = 4,
- CVMX_L2C_EVENT_MISS = 5,
- CVMX_L2C_EVENT_HIT = 6,
- CVMX_L2C_EVENT_VICTIM_HIT = 7,
- CVMX_L2C_EVENT_INDEX_CONFLICT = 8,
- CVMX_L2C_EVENT_TAG_PROBE = 9,
- CVMX_L2C_EVENT_TAG_UPDATE = 10,
- CVMX_L2C_EVENT_TAG_COMPLETE = 11,
- CVMX_L2C_EVENT_TAG_DIRTY = 12,
- CVMX_L2C_EVENT_DATA_STORE_NOP = 13,
- CVMX_L2C_EVENT_DATA_STORE_READ = 14,
+ CVMX_L2C_EVENT_CYCLES = 0,
+ CVMX_L2C_EVENT_INSTRUCTION_MISS = 1,
+ CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
+ CVMX_L2C_EVENT_DATA_MISS = 3,
+ CVMX_L2C_EVENT_DATA_HIT = 4,
+ CVMX_L2C_EVENT_MISS = 5,
+ CVMX_L2C_EVENT_HIT = 6,
+ CVMX_L2C_EVENT_VICTIM_HIT = 7,
+ CVMX_L2C_EVENT_INDEX_CONFLICT = 8,
+ CVMX_L2C_EVENT_TAG_PROBE = 9,
+ CVMX_L2C_EVENT_TAG_UPDATE = 10,
+ CVMX_L2C_EVENT_TAG_COMPLETE = 11,
+ CVMX_L2C_EVENT_TAG_DIRTY = 12,
+ CVMX_L2C_EVENT_DATA_STORE_NOP = 13,
+ CVMX_L2C_EVENT_DATA_STORE_READ = 14,
CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,
- CVMX_L2C_EVENT_FILL_DATA_VALID = 16,
- CVMX_L2C_EVENT_WRITE_REQUEST = 17,
- CVMX_L2C_EVENT_READ_REQUEST = 18,
+ CVMX_L2C_EVENT_FILL_DATA_VALID = 16,
+ CVMX_L2C_EVENT_WRITE_REQUEST = 17,
+ CVMX_L2C_EVENT_READ_REQUEST = 18,
CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,
- CVMX_L2C_EVENT_XMC_NOP = 20,
- CVMX_L2C_EVENT_XMC_LDT = 21,
- CVMX_L2C_EVENT_XMC_LDI = 22,
- CVMX_L2C_EVENT_XMC_LDD = 23,
- CVMX_L2C_EVENT_XMC_STF = 24,
- CVMX_L2C_EVENT_XMC_STT = 25,
- CVMX_L2C_EVENT_XMC_STP = 26,
- CVMX_L2C_EVENT_XMC_STC = 27,
- CVMX_L2C_EVENT_XMC_DWB = 28,
- CVMX_L2C_EVENT_XMC_PL2 = 29,
- CVMX_L2C_EVENT_XMC_PSL1 = 30,
- CVMX_L2C_EVENT_XMC_IOBLD = 31,
- CVMX_L2C_EVENT_XMC_IOBST = 32,
- CVMX_L2C_EVENT_XMC_IOBDMA = 33,
- CVMX_L2C_EVENT_XMC_IOBRSP = 34,
- CVMX_L2C_EVENT_XMC_BUS_VALID = 35,
- CVMX_L2C_EVENT_XMC_MEM_DATA = 36,
- CVMX_L2C_EVENT_XMC_REFL_DATA = 37,
- CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38,
- CVMX_L2C_EVENT_RSC_NOP = 39,
- CVMX_L2C_EVENT_RSC_STDN = 40,
- CVMX_L2C_EVENT_RSC_FILL = 41,
- CVMX_L2C_EVENT_RSC_REFL = 42,
- CVMX_L2C_EVENT_RSC_STIN = 43,
- CVMX_L2C_EVENT_RSC_SCIN = 44,
- CVMX_L2C_EVENT_RSC_SCFL = 45,
- CVMX_L2C_EVENT_RSC_SCDN = 46,
- CVMX_L2C_EVENT_RSC_DATA_VALID = 47,
- CVMX_L2C_EVENT_RSC_VALID_FILL = 48,
- CVMX_L2C_EVENT_RSC_VALID_STRSP = 49,
- CVMX_L2C_EVENT_RSC_VALID_REFL = 50,
- CVMX_L2C_EVENT_LRF_REQ = 51,
- CVMX_L2C_EVENT_DT_RD_ALLOC = 52,
- CVMX_L2C_EVENT_DT_WR_INVAL = 53
+ CVMX_L2C_EVENT_XMC_NOP = 20,
+ CVMX_L2C_EVENT_XMC_LDT = 21,
+ CVMX_L2C_EVENT_XMC_LDI = 22,
+ CVMX_L2C_EVENT_XMC_LDD = 23,
+ CVMX_L2C_EVENT_XMC_STF = 24,
+ CVMX_L2C_EVENT_XMC_STT = 25,
+ CVMX_L2C_EVENT_XMC_STP = 26,
+ CVMX_L2C_EVENT_XMC_STC = 27,
+ CVMX_L2C_EVENT_XMC_DWB = 28,
+ CVMX_L2C_EVENT_XMC_PL2 = 29,
+ CVMX_L2C_EVENT_XMC_PSL1 = 30,
+ CVMX_L2C_EVENT_XMC_IOBLD = 31,
+ CVMX_L2C_EVENT_XMC_IOBST = 32,
+ CVMX_L2C_EVENT_XMC_IOBDMA = 33,
+ CVMX_L2C_EVENT_XMC_IOBRSP = 34,
+ CVMX_L2C_EVENT_XMC_BUS_VALID = 35,
+ CVMX_L2C_EVENT_XMC_MEM_DATA = 36,
+ CVMX_L2C_EVENT_XMC_REFL_DATA = 37,
+ CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38,
+ CVMX_L2C_EVENT_RSC_NOP = 39,
+ CVMX_L2C_EVENT_RSC_STDN = 40,
+ CVMX_L2C_EVENT_RSC_FILL = 41,
+ CVMX_L2C_EVENT_RSC_REFL = 42,
+ CVMX_L2C_EVENT_RSC_STIN = 43,
+ CVMX_L2C_EVENT_RSC_SCIN = 44,
+ CVMX_L2C_EVENT_RSC_SCFL = 45,
+ CVMX_L2C_EVENT_RSC_SCDN = 46,
+ CVMX_L2C_EVENT_RSC_DATA_VALID = 47,
+ CVMX_L2C_EVENT_RSC_VALID_FILL = 48,
+ CVMX_L2C_EVENT_RSC_VALID_STRSP = 49,
+ CVMX_L2C_EVENT_RSC_VALID_REFL = 50,
+ CVMX_L2C_EVENT_LRF_REQ = 51,
+ CVMX_L2C_EVENT_DT_RD_ALLOC = 52,
+ CVMX_L2C_EVENT_DT_WR_INVAL = 53,
+ CVMX_L2C_EVENT_MAX
+};
+
+/* L2C Performance Counter events for Octeon2. */
+enum cvmx_l2c_tad_event {
+ CVMX_L2C_TAD_EVENT_NONE = 0,
+ CVMX_L2C_TAD_EVENT_TAG_HIT = 1,
+ CVMX_L2C_TAD_EVENT_TAG_MISS = 2,
+ CVMX_L2C_TAD_EVENT_TAG_NOALLOC = 3,
+ CVMX_L2C_TAD_EVENT_TAG_VICTIM = 4,
+ CVMX_L2C_TAD_EVENT_SC_FAIL = 5,
+ CVMX_L2C_TAD_EVENT_SC_PASS = 6,
+ CVMX_L2C_TAD_EVENT_LFB_VALID = 7,
+ CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB = 8,
+ CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB = 9,
+ CVMX_L2C_TAD_EVENT_QUAD0_INDEX = 128,
+ CVMX_L2C_TAD_EVENT_QUAD0_READ = 129,
+ CVMX_L2C_TAD_EVENT_QUAD0_BANK = 130,
+ CVMX_L2C_TAD_EVENT_QUAD0_WDAT = 131,
+ CVMX_L2C_TAD_EVENT_QUAD1_INDEX = 144,
+ CVMX_L2C_TAD_EVENT_QUAD1_READ = 145,
+ CVMX_L2C_TAD_EVENT_QUAD1_BANK = 146,
+ CVMX_L2C_TAD_EVENT_QUAD1_WDAT = 147,
+ CVMX_L2C_TAD_EVENT_QUAD2_INDEX = 160,
+ CVMX_L2C_TAD_EVENT_QUAD2_READ = 161,
+ CVMX_L2C_TAD_EVENT_QUAD2_BANK = 162,
+ CVMX_L2C_TAD_EVENT_QUAD2_WDAT = 163,
+ CVMX_L2C_TAD_EVENT_QUAD3_INDEX = 176,
+ CVMX_L2C_TAD_EVENT_QUAD3_READ = 177,
+ CVMX_L2C_TAD_EVENT_QUAD3_BANK = 178,
+ CVMX_L2C_TAD_EVENT_QUAD3_WDAT = 179,
+ CVMX_L2C_TAD_EVENT_MAX
};
/**
@@ -132,10 +164,10 @@ enum cvmx_l2c_event {
* @clear_on_read: When asserted, any read of the performance counter
* clears the counter.
*
- * The routine does not clear the counter.
+ * @note The routine does not clear the counter.
*/
-void cvmx_l2c_config_perf(uint32_t counter,
- enum cvmx_l2c_event event, uint32_t clear_on_read);
+void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event, uint32_t clear_on_read);
+
/**
* Read the given L2 Cache performance counter. The counter must be configured
* before reading, but this routine does not enforce this requirement.
@@ -160,18 +192,18 @@ int cvmx_l2c_get_core_way_partition(uint32_t core);
/**
* Partitions the L2 cache for a core
*
- * @core: The core that the partitioning applies to.
+ * @core: The core that the partitioning applies to.
+ * @mask: The partitioning of the ways expressed as a binary
+ * mask. A 0 bit allows the core to evict cache lines from
+ * a way, while a 1 bit blocks the core from evicting any
+ * lines from that way. There must be at least one allowed
+ * way (0 bit) in the mask.
*
- * @mask: The partitioning of the ways expressed as a binary mask. A 0
- * bit allows the core to evict cache lines from a way, while a
- * 1 bit blocks the core from evicting any lines from that
- * way. There must be at least one allowed way (0 bit) in the
- * mask.
- *
- * If any ways are blocked for all cores and the HW blocks, then those
- * ways will never have any cache lines evicted from them. All cores
- * and the hardware blocks are free to read from all ways regardless
- * of the partitioning.
+
+ * @note If any ways are blocked for all cores and the HW blocks, then
+ * those ways will never have any cache lines evicted from them.
+ * All cores and the hardware blocks are free to read from all
+ * ways regardless of the partitioning.
*/
int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
@@ -187,19 +219,21 @@ int cvmx_l2c_get_hw_way_partition(void);
/**
* Partitions the L2 cache for the hardware blocks.
*
- * @mask: The partitioning of the ways expressed as a binary mask. A 0
- * bit allows the core to evict cache lines from a way, while a
- * 1 bit blocks the core from evicting any lines from that
- * way. There must be at least one allowed way (0 bit) in the
- * mask.
+ * @mask: The partitioning of the ways expressed as a binary
+ * mask. A 0 bit allows the core to evict cache lines from
+ * a way, while a 1 bit blocks the core from evicting any
+ * lines from that way. There must be at least one allowed
+ * way (0 bit) in the mask.
*
- * If any ways are blocked for all cores and the HW blocks, then those
- * ways will never have any cache lines evicted from them. All cores
- * and the hardware blocks are free to read from all ways regardless
- * of the partitioning.
+
+ * @note If any ways are blocked for all cores and the HW blocks, then
+ * those ways will never have any cache lines evicted from them.
+ * All cores and the hardware blocks are free to read from all
+ * ways regardless of the partitioning.
*/
int cvmx_l2c_set_hw_way_partition(uint32_t mask);
+
/**
* Locks a line in the L2 cache at the specified physical address
*
@@ -263,13 +297,14 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
*/
union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index);
-/* Wrapper around deprecated old function name */
-static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association,
- uint32_t index)
+/* Wrapper providing a deprecated old function name */
+static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index) __attribute__((deprecated));
+static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index)
{
return cvmx_l2c_get_tag(association, index);
}
+
/**
* Returns the cache index for a given physical address
*
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-l2d-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
index d7102d455e1b..60543e0e77fc 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,30 +28,18 @@
#ifndef __CVMX_L2D_DEFS_H__
#define __CVMX_L2D_DEFS_H__
-#define CVMX_L2D_BST0 \
- CVMX_ADD_IO_SEG(0x0001180080000780ull)
-#define CVMX_L2D_BST1 \
- CVMX_ADD_IO_SEG(0x0001180080000788ull)
-#define CVMX_L2D_BST2 \
- CVMX_ADD_IO_SEG(0x0001180080000790ull)
-#define CVMX_L2D_BST3 \
- CVMX_ADD_IO_SEG(0x0001180080000798ull)
-#define CVMX_L2D_ERR \
- CVMX_ADD_IO_SEG(0x0001180080000010ull)
-#define CVMX_L2D_FADR \
- CVMX_ADD_IO_SEG(0x0001180080000018ull)
-#define CVMX_L2D_FSYN0 \
- CVMX_ADD_IO_SEG(0x0001180080000020ull)
-#define CVMX_L2D_FSYN1 \
- CVMX_ADD_IO_SEG(0x0001180080000028ull)
-#define CVMX_L2D_FUS0 \
- CVMX_ADD_IO_SEG(0x00011800800007A0ull)
-#define CVMX_L2D_FUS1 \
- CVMX_ADD_IO_SEG(0x00011800800007A8ull)
-#define CVMX_L2D_FUS2 \
- CVMX_ADD_IO_SEG(0x00011800800007B0ull)
-#define CVMX_L2D_FUS3 \
- CVMX_ADD_IO_SEG(0x00011800800007B8ull)
+#define CVMX_L2D_BST0 (CVMX_ADD_IO_SEG(0x0001180080000780ull))
+#define CVMX_L2D_BST1 (CVMX_ADD_IO_SEG(0x0001180080000788ull))
+#define CVMX_L2D_BST2 (CVMX_ADD_IO_SEG(0x0001180080000790ull))
+#define CVMX_L2D_BST3 (CVMX_ADD_IO_SEG(0x0001180080000798ull))
+#define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull))
+#define CVMX_L2D_FADR (CVMX_ADD_IO_SEG(0x0001180080000018ull))
+#define CVMX_L2D_FSYN0 (CVMX_ADD_IO_SEG(0x0001180080000020ull))
+#define CVMX_L2D_FSYN1 (CVMX_ADD_IO_SEG(0x0001180080000028ull))
+#define CVMX_L2D_FUS0 (CVMX_ADD_IO_SEG(0x00011800800007A0ull))
+#define CVMX_L2D_FUS1 (CVMX_ADD_IO_SEG(0x00011800800007A8ull))
+#define CVMX_L2D_FUS2 (CVMX_ADD_IO_SEG(0x00011800800007B0ull))
+#define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
union cvmx_l2d_bst0 {
uint64_t u64;
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
index 2639a3f5ffc2..873968f55eeb 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,8 +28,7 @@
#ifndef __CVMX_L2T_DEFS_H__
#define __CVMX_L2T_DEFS_H__
-#define CVMX_L2T_ERR \
- CVMX_ADD_IO_SEG(0x0001180080000008ull)
+#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull))
union cvmx_l2t_err {
uint64_t u64;
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-led-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-led-defs.h
index 16f174a4dadf..e25173bb8bb7 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-led-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-led-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,32 +28,19 @@
#ifndef __CVMX_LED_DEFS_H__
#define __CVMX_LED_DEFS_H__
-#define CVMX_LED_BLINK \
- CVMX_ADD_IO_SEG(0x0001180000001A48ull)
-#define CVMX_LED_CLK_PHASE \
- CVMX_ADD_IO_SEG(0x0001180000001A08ull)
-#define CVMX_LED_CYLON \
- CVMX_ADD_IO_SEG(0x0001180000001AF8ull)
-#define CVMX_LED_DBG \
- CVMX_ADD_IO_SEG(0x0001180000001A18ull)
-#define CVMX_LED_EN \
- CVMX_ADD_IO_SEG(0x0001180000001A00ull)
-#define CVMX_LED_POLARITY \
- CVMX_ADD_IO_SEG(0x0001180000001A50ull)
-#define CVMX_LED_PRT \
- CVMX_ADD_IO_SEG(0x0001180000001A10ull)
-#define CVMX_LED_PRT_FMT \
- CVMX_ADD_IO_SEG(0x0001180000001A30ull)
-#define CVMX_LED_PRT_STATUSX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001A80ull + (((offset) & 7) * 8))
-#define CVMX_LED_UDD_CNTX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001A20ull + (((offset) & 1) * 8))
-#define CVMX_LED_UDD_DATX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001A38ull + (((offset) & 1) * 8))
-#define CVMX_LED_UDD_DAT_CLRX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001AC8ull + (((offset) & 1) * 16))
-#define CVMX_LED_UDD_DAT_SETX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001AC0ull + (((offset) & 1) * 16))
+#define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull))
+#define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull))
+#define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull))
+#define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull))
+#define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull))
+#define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull))
+#define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull))
+#define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull))
+#define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8)
+#define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8)
+#define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8)
+#define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16)
+#define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16)
union cvmx_led_blink {
uint64_t u64;
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-mio-defs.h
index 6555f0530988..52b14a333ad4 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-mio-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-mio-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,191 +28,117 @@
#ifndef __CVMX_MIO_DEFS_H__
#define __CVMX_MIO_DEFS_H__
-#define CVMX_MIO_BOOT_BIST_STAT \
- CVMX_ADD_IO_SEG(0x00011800000000F8ull)
-#define CVMX_MIO_BOOT_COMP \
- CVMX_ADD_IO_SEG(0x00011800000000B8ull)
-#define CVMX_MIO_BOOT_DMA_CFGX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000100ull + (((offset) & 3) * 8))
-#define CVMX_MIO_BOOT_DMA_INTX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000138ull + (((offset) & 3) * 8))
-#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000150ull + (((offset) & 3) * 8))
-#define CVMX_MIO_BOOT_DMA_TIMX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000120ull + (((offset) & 3) * 8))
-#define CVMX_MIO_BOOT_ERR \
- CVMX_ADD_IO_SEG(0x00011800000000A0ull)
-#define CVMX_MIO_BOOT_INT \
- CVMX_ADD_IO_SEG(0x00011800000000A8ull)
-#define CVMX_MIO_BOOT_LOC_ADR \
- CVMX_ADD_IO_SEG(0x0001180000000090ull)
-#define CVMX_MIO_BOOT_LOC_CFGX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000080ull + (((offset) & 1) * 8))
-#define CVMX_MIO_BOOT_LOC_DAT \
- CVMX_ADD_IO_SEG(0x0001180000000098ull)
-#define CVMX_MIO_BOOT_PIN_DEFS \
- CVMX_ADD_IO_SEG(0x00011800000000C0ull)
-#define CVMX_MIO_BOOT_REG_CFGX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000000ull + (((offset) & 7) * 8))
-#define CVMX_MIO_BOOT_REG_TIMX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000040ull + (((offset) & 7) * 8))
-#define CVMX_MIO_BOOT_THR \
- CVMX_ADD_IO_SEG(0x00011800000000B0ull)
-#define CVMX_MIO_FUS_BNK_DATX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001520ull + (((offset) & 3) * 8))
-#define CVMX_MIO_FUS_DAT0 \
- CVMX_ADD_IO_SEG(0x0001180000001400ull)
-#define CVMX_MIO_FUS_DAT1 \
- CVMX_ADD_IO_SEG(0x0001180000001408ull)
-#define CVMX_MIO_FUS_DAT2 \
- CVMX_ADD_IO_SEG(0x0001180000001410ull)
-#define CVMX_MIO_FUS_DAT3 \
- CVMX_ADD_IO_SEG(0x0001180000001418ull)
-#define CVMX_MIO_FUS_EMA \
- CVMX_ADD_IO_SEG(0x0001180000001550ull)
-#define CVMX_MIO_FUS_PDF \
- CVMX_ADD_IO_SEG(0x0001180000001420ull)
-#define CVMX_MIO_FUS_PLL \
- CVMX_ADD_IO_SEG(0x0001180000001580ull)
-#define CVMX_MIO_FUS_PROG \
- CVMX_ADD_IO_SEG(0x0001180000001510ull)
-#define CVMX_MIO_FUS_PROG_TIMES \
- CVMX_ADD_IO_SEG(0x0001180000001518ull)
-#define CVMX_MIO_FUS_RCMD \
- CVMX_ADD_IO_SEG(0x0001180000001500ull)
-#define CVMX_MIO_FUS_SPR_REPAIR_RES \
- CVMX_ADD_IO_SEG(0x0001180000001548ull)
-#define CVMX_MIO_FUS_SPR_REPAIR_SUM \
- CVMX_ADD_IO_SEG(0x0001180000001540ull)
-#define CVMX_MIO_FUS_UNLOCK \
- CVMX_ADD_IO_SEG(0x0001180000001578ull)
-#define CVMX_MIO_FUS_WADR \
- CVMX_ADD_IO_SEG(0x0001180000001508ull)
-#define CVMX_MIO_NDF_DMA_CFG \
- CVMX_ADD_IO_SEG(0x0001180000000168ull)
-#define CVMX_MIO_NDF_DMA_INT \
- CVMX_ADD_IO_SEG(0x0001180000000170ull)
-#define CVMX_MIO_NDF_DMA_INT_EN \
- CVMX_ADD_IO_SEG(0x0001180000000178ull)
-#define CVMX_MIO_PLL_CTL \
- CVMX_ADD_IO_SEG(0x0001180000001448ull)
-#define CVMX_MIO_PLL_SETTING \
- CVMX_ADD_IO_SEG(0x0001180000001440ull)
-#define CVMX_MIO_TWSX_INT(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001010ull + (((offset) & 1) * 512))
-#define CVMX_MIO_TWSX_SW_TWSI(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001000ull + (((offset) & 1) * 512))
-#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001018ull + (((offset) & 1) * 512))
-#define CVMX_MIO_TWSX_TWSI_SW(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001008ull + (((offset) & 1) * 512))
-#define CVMX_MIO_UART2_DLH \
- CVMX_ADD_IO_SEG(0x0001180000000488ull)
-#define CVMX_MIO_UART2_DLL \
- CVMX_ADD_IO_SEG(0x0001180000000480ull)
-#define CVMX_MIO_UART2_FAR \
- CVMX_ADD_IO_SEG(0x0001180000000520ull)
-#define CVMX_MIO_UART2_FCR \
- CVMX_ADD_IO_SEG(0x0001180000000450ull)
-#define CVMX_MIO_UART2_HTX \
- CVMX_ADD_IO_SEG(0x0001180000000708ull)
-#define CVMX_MIO_UART2_IER \
- CVMX_ADD_IO_SEG(0x0001180000000408ull)
-#define CVMX_MIO_UART2_IIR \
- CVMX_ADD_IO_SEG(0x0001180000000410ull)
-#define CVMX_MIO_UART2_LCR \
- CVMX_ADD_IO_SEG(0x0001180000000418ull)
-#define CVMX_MIO_UART2_LSR \
- CVMX_ADD_IO_SEG(0x0001180000000428ull)
-#define CVMX_MIO_UART2_MCR \
- CVMX_ADD_IO_SEG(0x0001180000000420ull)
-#define CVMX_MIO_UART2_MSR \
- CVMX_ADD_IO_SEG(0x0001180000000430ull)
-#define CVMX_MIO_UART2_RBR \
- CVMX_ADD_IO_SEG(0x0001180000000400ull)
-#define CVMX_MIO_UART2_RFL \
- CVMX_ADD_IO_SEG(0x0001180000000608ull)
-#define CVMX_MIO_UART2_RFW \
- CVMX_ADD_IO_SEG(0x0001180000000530ull)
-#define CVMX_MIO_UART2_SBCR \
- CVMX_ADD_IO_SEG(0x0001180000000620ull)
-#define CVMX_MIO_UART2_SCR \
- CVMX_ADD_IO_SEG(0x0001180000000438ull)
-#define CVMX_MIO_UART2_SFE \
- CVMX_ADD_IO_SEG(0x0001180000000630ull)
-#define CVMX_MIO_UART2_SRR \
- CVMX_ADD_IO_SEG(0x0001180000000610ull)
-#define CVMX_MIO_UART2_SRT \
- CVMX_ADD_IO_SEG(0x0001180000000638ull)
-#define CVMX_MIO_UART2_SRTS \
- CVMX_ADD_IO_SEG(0x0001180000000618ull)
-#define CVMX_MIO_UART2_STT \
- CVMX_ADD_IO_SEG(0x0001180000000700ull)
-#define CVMX_MIO_UART2_TFL \
- CVMX_ADD_IO_SEG(0x0001180000000600ull)
-#define CVMX_MIO_UART2_TFR \
- CVMX_ADD_IO_SEG(0x0001180000000528ull)
-#define CVMX_MIO_UART2_THR \
- CVMX_ADD_IO_SEG(0x0001180000000440ull)
-#define CVMX_MIO_UART2_USR \
- CVMX_ADD_IO_SEG(0x0001180000000538ull)
-#define CVMX_MIO_UARTX_DLH(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000888ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_DLL(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000880ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_FAR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000920ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_FCR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000850ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_HTX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000B08ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_IER(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000808ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_IIR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000810ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_LCR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000818ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_LSR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000828ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_MCR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000820ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_MSR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000830ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_RBR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000800ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_RFL(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000A08ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_RFW(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000930ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SBCR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000A20ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SCR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000838ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SFE(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000A30ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SRR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000A10ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SRT(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000A38ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SRTS(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000A18ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_STT(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000B00ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_TFL(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000A00ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_TFR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000928ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_THR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000840ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_USR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000938ull + (((offset) & 1) * 1024))
+#define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull))
+#define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull))
+#define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_DMA_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_ERR (CVMX_ADD_IO_SEG(0x00011800000000A0ull))
+#define CVMX_MIO_BOOT_INT (CVMX_ADD_IO_SEG(0x00011800000000A8ull))
+#define CVMX_MIO_BOOT_LOC_ADR (CVMX_ADD_IO_SEG(0x0001180000000090ull))
+#define CVMX_MIO_BOOT_LOC_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8)
+#define CVMX_MIO_BOOT_LOC_DAT (CVMX_ADD_IO_SEG(0x0001180000000098ull))
+#define CVMX_MIO_BOOT_PIN_DEFS (CVMX_ADD_IO_SEG(0x00011800000000C0ull))
+#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
+#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
+#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
+#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
+#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
+#define CVMX_MIO_FUS_DAT2 (CVMX_ADD_IO_SEG(0x0001180000001410ull))
+#define CVMX_MIO_FUS_DAT3 (CVMX_ADD_IO_SEG(0x0001180000001418ull))
+#define CVMX_MIO_FUS_EMA (CVMX_ADD_IO_SEG(0x0001180000001550ull))
+#define CVMX_MIO_FUS_PDF (CVMX_ADD_IO_SEG(0x0001180000001420ull))
+#define CVMX_MIO_FUS_PLL (CVMX_ADD_IO_SEG(0x0001180000001580ull))
+#define CVMX_MIO_FUS_PROG (CVMX_ADD_IO_SEG(0x0001180000001510ull))
+#define CVMX_MIO_FUS_PROG_TIMES (CVMX_ADD_IO_SEG(0x0001180000001518ull))
+#define CVMX_MIO_FUS_RCMD (CVMX_ADD_IO_SEG(0x0001180000001500ull))
+#define CVMX_MIO_FUS_READ_TIMES (CVMX_ADD_IO_SEG(0x0001180000001570ull))
+#define CVMX_MIO_FUS_REPAIR_RES0 (CVMX_ADD_IO_SEG(0x0001180000001558ull))
+#define CVMX_MIO_FUS_REPAIR_RES1 (CVMX_ADD_IO_SEG(0x0001180000001560ull))
+#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
+#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
+#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
+#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
+#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
+#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
+#define CVMX_MIO_NDF_DMA_CFG (CVMX_ADD_IO_SEG(0x0001180000000168ull))
+#define CVMX_MIO_NDF_DMA_INT (CVMX_ADD_IO_SEG(0x0001180000000170ull))
+#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
+#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
+#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
+#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
+#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
+#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
+#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
+#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
+#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
+#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
+#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
+#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
+#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
+#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
+#define CVMX_MIO_RST_INT_EN (CVMX_ADD_IO_SEG(0x0001180000001630ull))
+#define CVMX_MIO_TWSX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_TWSX_SW_TWSI(offset) (CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) (CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_TWSX_TWSI_SW(offset) (CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_UART2_DLH (CVMX_ADD_IO_SEG(0x0001180000000488ull))
+#define CVMX_MIO_UART2_DLL (CVMX_ADD_IO_SEG(0x0001180000000480ull))
+#define CVMX_MIO_UART2_FAR (CVMX_ADD_IO_SEG(0x0001180000000520ull))
+#define CVMX_MIO_UART2_FCR (CVMX_ADD_IO_SEG(0x0001180000000450ull))
+#define CVMX_MIO_UART2_HTX (CVMX_ADD_IO_SEG(0x0001180000000708ull))
+#define CVMX_MIO_UART2_IER (CVMX_ADD_IO_SEG(0x0001180000000408ull))
+#define CVMX_MIO_UART2_IIR (CVMX_ADD_IO_SEG(0x0001180000000410ull))
+#define CVMX_MIO_UART2_LCR (CVMX_ADD_IO_SEG(0x0001180000000418ull))
+#define CVMX_MIO_UART2_LSR (CVMX_ADD_IO_SEG(0x0001180000000428ull))
+#define CVMX_MIO_UART2_MCR (CVMX_ADD_IO_SEG(0x0001180000000420ull))
+#define CVMX_MIO_UART2_MSR (CVMX_ADD_IO_SEG(0x0001180000000430ull))
+#define CVMX_MIO_UART2_RBR (CVMX_ADD_IO_SEG(0x0001180000000400ull))
+#define CVMX_MIO_UART2_RFL (CVMX_ADD_IO_SEG(0x0001180000000608ull))
+#define CVMX_MIO_UART2_RFW (CVMX_ADD_IO_SEG(0x0001180000000530ull))
+#define CVMX_MIO_UART2_SBCR (CVMX_ADD_IO_SEG(0x0001180000000620ull))
+#define CVMX_MIO_UART2_SCR (CVMX_ADD_IO_SEG(0x0001180000000438ull))
+#define CVMX_MIO_UART2_SFE (CVMX_ADD_IO_SEG(0x0001180000000630ull))
+#define CVMX_MIO_UART2_SRR (CVMX_ADD_IO_SEG(0x0001180000000610ull))
+#define CVMX_MIO_UART2_SRT (CVMX_ADD_IO_SEG(0x0001180000000638ull))
+#define CVMX_MIO_UART2_SRTS (CVMX_ADD_IO_SEG(0x0001180000000618ull))
+#define CVMX_MIO_UART2_STT (CVMX_ADD_IO_SEG(0x0001180000000700ull))
+#define CVMX_MIO_UART2_TFL (CVMX_ADD_IO_SEG(0x0001180000000600ull))
+#define CVMX_MIO_UART2_TFR (CVMX_ADD_IO_SEG(0x0001180000000528ull))
+#define CVMX_MIO_UART2_THR (CVMX_ADD_IO_SEG(0x0001180000000440ull))
+#define CVMX_MIO_UART2_USR (CVMX_ADD_IO_SEG(0x0001180000000538ull))
+#define CVMX_MIO_UARTX_DLH(offset) (CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_DLL(offset) (CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_FAR(offset) (CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_FCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_HTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_IER(offset) (CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_IIR(offset) (CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_LCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_LSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_MCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_MSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_RBR(offset) (CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_RFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_RFW(offset) (CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SBCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SFE(offset) (CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SRR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SRT(offset) (CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SRTS(offset) (CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_STT(offset) (CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_TFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_TFR(offset) (CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_THR(offset) (CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_USR(offset) (CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024)
union cvmx_mio_boot_bist_stat {
uint64_t u64;
struct cvmx_mio_boot_bist_stat_s {
- uint64_t reserved_2_63:62;
- uint64_t loc:1;
- uint64_t ncbi:1;
+ uint64_t reserved_0_63:64;
} s;
struct cvmx_mio_boot_bist_stat_cn30xx {
uint64_t reserved_4_63:60;
@@ -257,20 +183,33 @@ union cvmx_mio_boot_bist_stat {
struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
+ struct cvmx_mio_boot_bist_stat_cn63xx {
+ uint64_t reserved_9_63:55;
+ uint64_t stat:9;
+ } cn63xx;
+ struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1;
};
union cvmx_mio_boot_comp {
uint64_t u64;
struct cvmx_mio_boot_comp_s {
+ uint64_t reserved_0_63:64;
+ } s;
+ struct cvmx_mio_boot_comp_cn50xx {
uint64_t reserved_10_63:54;
uint64_t pctl:5;
uint64_t nctl:5;
- } s;
- struct cvmx_mio_boot_comp_s cn50xx;
- struct cvmx_mio_boot_comp_s cn52xx;
- struct cvmx_mio_boot_comp_s cn52xxp1;
- struct cvmx_mio_boot_comp_s cn56xx;
- struct cvmx_mio_boot_comp_s cn56xxp1;
+ } cn50xx;
+ struct cvmx_mio_boot_comp_cn50xx cn52xx;
+ struct cvmx_mio_boot_comp_cn50xx cn52xxp1;
+ struct cvmx_mio_boot_comp_cn50xx cn56xx;
+ struct cvmx_mio_boot_comp_cn50xx cn56xxp1;
+ struct cvmx_mio_boot_comp_cn63xx {
+ uint64_t reserved_12_63:52;
+ uint64_t pctl:6;
+ uint64_t nctl:6;
+ } cn63xx;
+ struct cvmx_mio_boot_comp_cn63xx cn63xxp1;
};
union cvmx_mio_boot_dma_cfgx {
@@ -291,6 +230,8 @@ union cvmx_mio_boot_dma_cfgx {
struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
struct cvmx_mio_boot_dma_cfgx_s cn56xx;
struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
+ struct cvmx_mio_boot_dma_cfgx_s cn63xx;
+ struct cvmx_mio_boot_dma_cfgx_s cn63xxp1;
};
union cvmx_mio_boot_dma_intx {
@@ -304,6 +245,8 @@ union cvmx_mio_boot_dma_intx {
struct cvmx_mio_boot_dma_intx_s cn52xxp1;
struct cvmx_mio_boot_dma_intx_s cn56xx;
struct cvmx_mio_boot_dma_intx_s cn56xxp1;
+ struct cvmx_mio_boot_dma_intx_s cn63xx;
+ struct cvmx_mio_boot_dma_intx_s cn63xxp1;
};
union cvmx_mio_boot_dma_int_enx {
@@ -317,6 +260,8 @@ union cvmx_mio_boot_dma_int_enx {
struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
struct cvmx_mio_boot_dma_int_enx_s cn56xx;
struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
+ struct cvmx_mio_boot_dma_int_enx_s cn63xx;
+ struct cvmx_mio_boot_dma_int_enx_s cn63xxp1;
};
union cvmx_mio_boot_dma_timx {
@@ -342,6 +287,8 @@ union cvmx_mio_boot_dma_timx {
struct cvmx_mio_boot_dma_timx_s cn52xxp1;
struct cvmx_mio_boot_dma_timx_s cn56xx;
struct cvmx_mio_boot_dma_timx_s cn56xxp1;
+ struct cvmx_mio_boot_dma_timx_s cn63xx;
+ struct cvmx_mio_boot_dma_timx_s cn63xxp1;
};
union cvmx_mio_boot_err {
@@ -362,6 +309,8 @@ union cvmx_mio_boot_err {
struct cvmx_mio_boot_err_s cn56xxp1;
struct cvmx_mio_boot_err_s cn58xx;
struct cvmx_mio_boot_err_s cn58xxp1;
+ struct cvmx_mio_boot_err_s cn63xx;
+ struct cvmx_mio_boot_err_s cn63xxp1;
};
union cvmx_mio_boot_int {
@@ -382,6 +331,8 @@ union cvmx_mio_boot_int {
struct cvmx_mio_boot_int_s cn56xxp1;
struct cvmx_mio_boot_int_s cn58xx;
struct cvmx_mio_boot_int_s cn58xxp1;
+ struct cvmx_mio_boot_int_s cn63xx;
+ struct cvmx_mio_boot_int_s cn63xxp1;
};
union cvmx_mio_boot_loc_adr {
@@ -402,6 +353,8 @@ union cvmx_mio_boot_loc_adr {
struct cvmx_mio_boot_loc_adr_s cn56xxp1;
struct cvmx_mio_boot_loc_adr_s cn58xx;
struct cvmx_mio_boot_loc_adr_s cn58xxp1;
+ struct cvmx_mio_boot_loc_adr_s cn63xx;
+ struct cvmx_mio_boot_loc_adr_s cn63xxp1;
};
union cvmx_mio_boot_loc_cfgx {
@@ -424,6 +377,8 @@ union cvmx_mio_boot_loc_cfgx {
struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
struct cvmx_mio_boot_loc_cfgx_s cn58xx;
struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
+ struct cvmx_mio_boot_loc_cfgx_s cn63xx;
+ struct cvmx_mio_boot_loc_cfgx_s cn63xxp1;
};
union cvmx_mio_boot_loc_dat {
@@ -442,6 +397,8 @@ union cvmx_mio_boot_loc_dat {
struct cvmx_mio_boot_loc_dat_s cn56xxp1;
struct cvmx_mio_boot_loc_dat_s cn58xx;
struct cvmx_mio_boot_loc_dat_s cn58xxp1;
+ struct cvmx_mio_boot_loc_dat_s cn63xx;
+ struct cvmx_mio_boot_loc_dat_s cn63xxp1;
};
union cvmx_mio_boot_pin_defs {
@@ -478,6 +435,8 @@ union cvmx_mio_boot_pin_defs {
uint64_t term:2;
uint64_t reserved_0_8:9;
} cn56xx;
+ struct cvmx_mio_boot_pin_defs_cn52xx cn63xx;
+ struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1;
};
union cvmx_mio_boot_reg_cfgx {
@@ -539,6 +498,8 @@ union cvmx_mio_boot_reg_cfgx {
struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
+ struct cvmx_mio_boot_reg_cfgx_s cn63xx;
+ struct cvmx_mio_boot_reg_cfgx_s cn63xxp1;
};
union cvmx_mio_boot_reg_timx {
@@ -583,6 +544,8 @@ union cvmx_mio_boot_reg_timx {
struct cvmx_mio_boot_reg_timx_s cn56xxp1;
struct cvmx_mio_boot_reg_timx_s cn58xx;
struct cvmx_mio_boot_reg_timx_s cn58xxp1;
+ struct cvmx_mio_boot_reg_timx_s cn63xx;
+ struct cvmx_mio_boot_reg_timx_s cn63xxp1;
};
union cvmx_mio_boot_thr {
@@ -611,6 +574,8 @@ union cvmx_mio_boot_thr {
struct cvmx_mio_boot_thr_s cn56xxp1;
struct cvmx_mio_boot_thr_cn30xx cn58xx;
struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
+ struct cvmx_mio_boot_thr_s cn63xx;
+ struct cvmx_mio_boot_thr_s cn63xxp1;
};
union cvmx_mio_fus_bnk_datx {
@@ -625,6 +590,8 @@ union cvmx_mio_fus_bnk_datx {
struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
struct cvmx_mio_fus_bnk_datx_s cn58xx;
struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
+ struct cvmx_mio_fus_bnk_datx_s cn63xx;
+ struct cvmx_mio_fus_bnk_datx_s cn63xxp1;
};
union cvmx_mio_fus_dat0 {
@@ -644,6 +611,8 @@ union cvmx_mio_fus_dat0 {
struct cvmx_mio_fus_dat0_s cn56xxp1;
struct cvmx_mio_fus_dat0_s cn58xx;
struct cvmx_mio_fus_dat0_s cn58xxp1;
+ struct cvmx_mio_fus_dat0_s cn63xx;
+ struct cvmx_mio_fus_dat0_s cn63xxp1;
};
union cvmx_mio_fus_dat1 {
@@ -663,12 +632,15 @@ union cvmx_mio_fus_dat1 {
struct cvmx_mio_fus_dat1_s cn56xxp1;
struct cvmx_mio_fus_dat1_s cn58xx;
struct cvmx_mio_fus_dat1_s cn58xxp1;
+ struct cvmx_mio_fus_dat1_s cn63xx;
+ struct cvmx_mio_fus_dat1_s cn63xxp1;
};
union cvmx_mio_fus_dat2 {
uint64_t u64;
struct cvmx_mio_fus_dat2_s {
- uint64_t reserved_34_63:30;
+ uint64_t reserved_35_63:29;
+ uint64_t dorm_crypto:1;
uint64_t fus318:1;
uint64_t raid_en:1;
uint64_t reserved_30_31:2;
@@ -775,14 +747,38 @@ union cvmx_mio_fus_dat2 {
uint64_t pp_dis:16;
} cn58xx;
struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
+ struct cvmx_mio_fus_dat2_cn63xx {
+ uint64_t reserved_35_63:29;
+ uint64_t dorm_crypto:1;
+ uint64_t fus318:1;
+ uint64_t raid_en:1;
+ uint64_t reserved_29_31:3;
+ uint64_t nodfa_cp2:1;
+ uint64_t nomul:1;
+ uint64_t nocrypto:1;
+ uint64_t reserved_24_25:2;
+ uint64_t chip_id:8;
+ uint64_t reserved_6_15:10;
+ uint64_t pp_dis:6;
+ } cn63xx;
+ struct cvmx_mio_fus_dat2_cn63xx cn63xxp1;
};
union cvmx_mio_fus_dat3 {
uint64_t u64;
struct cvmx_mio_fus_dat3_s {
- uint64_t reserved_32_63:32;
+ uint64_t reserved_58_63:6;
+ uint64_t pll_ctl:10;
+ uint64_t dfa_info_dte:3;
+ uint64_t dfa_info_clm:4;
+ uint64_t reserved_40_40:1;
+ uint64_t ema:2;
+ uint64_t efus_lck_rsv:1;
+ uint64_t efus_lck_man:1;
+ uint64_t pll_half_dis:1;
+ uint64_t l2c_crip:3;
uint64_t pll_div4:1;
- uint64_t zip_crip:2;
+ uint64_t reserved_29_30:2;
uint64_t bar2_en:1;
uint64_t efus_lck:1;
uint64_t efus_ign:1;
@@ -801,7 +797,17 @@ union cvmx_mio_fus_dat3 {
uint64_t nodfa_dte:1;
uint64_t icache:24;
} cn30xx;
- struct cvmx_mio_fus_dat3_s cn31xx;
+ struct cvmx_mio_fus_dat3_cn31xx {
+ uint64_t reserved_32_63:32;
+ uint64_t pll_div4:1;
+ uint64_t zip_crip:2;
+ uint64_t bar2_en:1;
+ uint64_t efus_lck:1;
+ uint64_t efus_ign:1;
+ uint64_t nozip:1;
+ uint64_t nodfa_dte:1;
+ uint64_t icache:24;
+ } cn31xx;
struct cvmx_mio_fus_dat3_cn38xx {
uint64_t reserved_31_63:33;
uint64_t zip_crip:2;
@@ -828,6 +834,27 @@ union cvmx_mio_fus_dat3 {
struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
struct cvmx_mio_fus_dat3_cn38xx cn58xx;
struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
+ struct cvmx_mio_fus_dat3_cn63xx {
+ uint64_t reserved_58_63:6;
+ uint64_t pll_ctl:10;
+ uint64_t dfa_info_dte:3;
+ uint64_t dfa_info_clm:4;
+ uint64_t reserved_40_40:1;
+ uint64_t ema:2;
+ uint64_t efus_lck_rsv:1;
+ uint64_t efus_lck_man:1;
+ uint64_t pll_half_dis:1;
+ uint64_t l2c_crip:3;
+ uint64_t reserved_31_31:1;
+ uint64_t zip_info:2;
+ uint64_t bar2_en:1;
+ uint64_t efus_lck:1;
+ uint64_t efus_ign:1;
+ uint64_t nozip:1;
+ uint64_t nodfa_dte:1;
+ uint64_t reserved_0_23:24;
+ } cn63xx;
+ struct cvmx_mio_fus_dat3_cn63xx cn63xxp1;
};
union cvmx_mio_fus_ema {
@@ -848,6 +875,8 @@ union cvmx_mio_fus_ema {
uint64_t ema:2;
} cn58xx;
struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
+ struct cvmx_mio_fus_ema_s cn63xx;
+ struct cvmx_mio_fus_ema_s cn63xxp1;
};
union cvmx_mio_fus_pdf {
@@ -861,60 +890,96 @@ union cvmx_mio_fus_pdf {
struct cvmx_mio_fus_pdf_s cn56xx;
struct cvmx_mio_fus_pdf_s cn56xxp1;
struct cvmx_mio_fus_pdf_s cn58xx;
+ struct cvmx_mio_fus_pdf_s cn63xx;
+ struct cvmx_mio_fus_pdf_s cn63xxp1;
};
union cvmx_mio_fus_pll {
uint64_t u64;
struct cvmx_mio_fus_pll_s {
- uint64_t reserved_2_63:62;
+ uint64_t reserved_8_63:56;
+ uint64_t c_cout_rst:1;
+ uint64_t c_cout_sel:2;
+ uint64_t pnr_cout_rst:1;
+ uint64_t pnr_cout_sel:2;
uint64_t rfslip:1;
uint64_t fbslip:1;
} s;
- struct cvmx_mio_fus_pll_s cn50xx;
- struct cvmx_mio_fus_pll_s cn52xx;
- struct cvmx_mio_fus_pll_s cn52xxp1;
- struct cvmx_mio_fus_pll_s cn56xx;
- struct cvmx_mio_fus_pll_s cn56xxp1;
- struct cvmx_mio_fus_pll_s cn58xx;
- struct cvmx_mio_fus_pll_s cn58xxp1;
+ struct cvmx_mio_fus_pll_cn50xx {
+ uint64_t reserved_2_63:62;
+ uint64_t rfslip:1;
+ uint64_t fbslip:1;
+ } cn50xx;
+ struct cvmx_mio_fus_pll_cn50xx cn52xx;
+ struct cvmx_mio_fus_pll_cn50xx cn52xxp1;
+ struct cvmx_mio_fus_pll_cn50xx cn56xx;
+ struct cvmx_mio_fus_pll_cn50xx cn56xxp1;
+ struct cvmx_mio_fus_pll_cn50xx cn58xx;
+ struct cvmx_mio_fus_pll_cn50xx cn58xxp1;
+ struct cvmx_mio_fus_pll_s cn63xx;
+ struct cvmx_mio_fus_pll_s cn63xxp1;
};
union cvmx_mio_fus_prog {
uint64_t u64;
struct cvmx_mio_fus_prog_s {
- uint64_t reserved_1_63:63;
+ uint64_t reserved_2_63:62;
+ uint64_t soft:1;
uint64_t prog:1;
} s;
- struct cvmx_mio_fus_prog_s cn30xx;
- struct cvmx_mio_fus_prog_s cn31xx;
- struct cvmx_mio_fus_prog_s cn38xx;
- struct cvmx_mio_fus_prog_s cn38xxp2;
- struct cvmx_mio_fus_prog_s cn50xx;
- struct cvmx_mio_fus_prog_s cn52xx;
- struct cvmx_mio_fus_prog_s cn52xxp1;
- struct cvmx_mio_fus_prog_s cn56xx;
- struct cvmx_mio_fus_prog_s cn56xxp1;
- struct cvmx_mio_fus_prog_s cn58xx;
- struct cvmx_mio_fus_prog_s cn58xxp1;
+ struct cvmx_mio_fus_prog_cn30xx {
+ uint64_t reserved_1_63:63;
+ uint64_t prog:1;
+ } cn30xx;
+ struct cvmx_mio_fus_prog_cn30xx cn31xx;
+ struct cvmx_mio_fus_prog_cn30xx cn38xx;
+ struct cvmx_mio_fus_prog_cn30xx cn38xxp2;
+ struct cvmx_mio_fus_prog_cn30xx cn50xx;
+ struct cvmx_mio_fus_prog_cn30xx cn52xx;
+ struct cvmx_mio_fus_prog_cn30xx cn52xxp1;
+ struct cvmx_mio_fus_prog_cn30xx cn56xx;
+ struct cvmx_mio_fus_prog_cn30xx cn56xxp1;
+ struct cvmx_mio_fus_prog_cn30xx cn58xx;
+ struct cvmx_mio_fus_prog_cn30xx cn58xxp1;
+ struct cvmx_mio_fus_prog_s cn63xx;
+ struct cvmx_mio_fus_prog_s cn63xxp1;
};
union cvmx_mio_fus_prog_times {
uint64_t u64;
struct cvmx_mio_fus_prog_times_s {
+ uint64_t reserved_35_63:29;
+ uint64_t vgate_pin:1;
+ uint64_t fsrc_pin:1;
+ uint64_t prog_pin:1;
+ uint64_t reserved_6_31:26;
+ uint64_t setup:6;
+ } s;
+ struct cvmx_mio_fus_prog_times_cn50xx {
uint64_t reserved_33_63:31;
uint64_t prog_pin:1;
uint64_t out:8;
uint64_t sclk_lo:4;
uint64_t sclk_hi:12;
uint64_t setup:8;
- } s;
- struct cvmx_mio_fus_prog_times_s cn50xx;
- struct cvmx_mio_fus_prog_times_s cn52xx;
- struct cvmx_mio_fus_prog_times_s cn52xxp1;
- struct cvmx_mio_fus_prog_times_s cn56xx;
- struct cvmx_mio_fus_prog_times_s cn56xxp1;
- struct cvmx_mio_fus_prog_times_s cn58xx;
- struct cvmx_mio_fus_prog_times_s cn58xxp1;
+ } cn50xx;
+ struct cvmx_mio_fus_prog_times_cn50xx cn52xx;
+ struct cvmx_mio_fus_prog_times_cn50xx cn52xxp1;
+ struct cvmx_mio_fus_prog_times_cn50xx cn56xx;
+ struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1;
+ struct cvmx_mio_fus_prog_times_cn50xx cn58xx;
+ struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1;
+ struct cvmx_mio_fus_prog_times_cn63xx {
+ uint64_t reserved_35_63:29;
+ uint64_t vgate_pin:1;
+ uint64_t fsrc_pin:1;
+ uint64_t prog_pin:1;
+ uint64_t out:7;
+ uint64_t sclk_lo:4;
+ uint64_t sclk_hi:15;
+ uint64_t setup:6;
+ } cn63xx;
+ struct cvmx_mio_fus_prog_times_cn63xx cn63xxp1;
};
union cvmx_mio_fus_rcmd {
@@ -948,6 +1013,57 @@ union cvmx_mio_fus_rcmd {
struct cvmx_mio_fus_rcmd_s cn56xxp1;
struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
+ struct cvmx_mio_fus_rcmd_s cn63xx;
+ struct cvmx_mio_fus_rcmd_s cn63xxp1;
+};
+
+union cvmx_mio_fus_read_times {
+ uint64_t u64;
+ struct cvmx_mio_fus_read_times_s {
+ uint64_t reserved_26_63:38;
+ uint64_t sch:4;
+ uint64_t fsh:4;
+ uint64_t prh:4;
+ uint64_t sdh:4;
+ uint64_t setup:10;
+ } s;
+ struct cvmx_mio_fus_read_times_s cn63xx;
+ struct cvmx_mio_fus_read_times_s cn63xxp1;
+};
+
+union cvmx_mio_fus_repair_res0 {
+ uint64_t u64;
+ struct cvmx_mio_fus_repair_res0_s {
+ uint64_t reserved_55_63:9;
+ uint64_t too_many:1;
+ uint64_t repair2:18;
+ uint64_t repair1:18;
+ uint64_t repair0:18;
+ } s;
+ struct cvmx_mio_fus_repair_res0_s cn63xx;
+ struct cvmx_mio_fus_repair_res0_s cn63xxp1;
+};
+
+union cvmx_mio_fus_repair_res1 {
+ uint64_t u64;
+ struct cvmx_mio_fus_repair_res1_s {
+ uint64_t reserved_54_63:10;
+ uint64_t repair5:18;
+ uint64_t repair4:18;
+ uint64_t repair3:18;
+ } s;
+ struct cvmx_mio_fus_repair_res1_s cn63xx;
+ struct cvmx_mio_fus_repair_res1_s cn63xxp1;
+};
+
+union cvmx_mio_fus_repair_res2 {
+ uint64_t u64;
+ struct cvmx_mio_fus_repair_res2_s {
+ uint64_t reserved_18_63:46;
+ uint64_t repair6:18;
+ } s;
+ struct cvmx_mio_fus_repair_res2_s cn63xx;
+ struct cvmx_mio_fus_repair_res2_s cn63xxp1;
};
union cvmx_mio_fus_spr_repair_res {
@@ -968,6 +1084,8 @@ union cvmx_mio_fus_spr_repair_res {
struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
struct cvmx_mio_fus_spr_repair_res_s cn58xx;
struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
+ struct cvmx_mio_fus_spr_repair_res_s cn63xx;
+ struct cvmx_mio_fus_spr_repair_res_s cn63xxp1;
};
union cvmx_mio_fus_spr_repair_sum {
@@ -986,6 +1104,8 @@ union cvmx_mio_fus_spr_repair_sum {
struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
+ struct cvmx_mio_fus_spr_repair_sum_s cn63xx;
+ struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1;
};
union cvmx_mio_fus_unlock {
@@ -1021,6 +1141,22 @@ union cvmx_mio_fus_wadr {
struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
struct cvmx_mio_fus_wadr_cn50xx cn58xx;
struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
+ struct cvmx_mio_fus_wadr_cn63xx {
+ uint64_t reserved_4_63:60;
+ uint64_t addr:4;
+ } cn63xx;
+ struct cvmx_mio_fus_wadr_cn63xx cn63xxp1;
+};
+
+union cvmx_mio_gpio_comp {
+ uint64_t u64;
+ struct cvmx_mio_gpio_comp_s {
+ uint64_t reserved_12_63:52;
+ uint64_t pctl:6;
+ uint64_t nctl:6;
+ } s;
+ struct cvmx_mio_gpio_comp_s cn63xx;
+ struct cvmx_mio_gpio_comp_s cn63xxp1;
};
union cvmx_mio_ndf_dma_cfg {
@@ -1038,6 +1174,8 @@ union cvmx_mio_ndf_dma_cfg {
uint64_t adr:36;
} s;
struct cvmx_mio_ndf_dma_cfg_s cn52xx;
+ struct cvmx_mio_ndf_dma_cfg_s cn63xx;
+ struct cvmx_mio_ndf_dma_cfg_s cn63xxp1;
};
union cvmx_mio_ndf_dma_int {
@@ -1047,6 +1185,8 @@ union cvmx_mio_ndf_dma_int {
uint64_t done:1;
} s;
struct cvmx_mio_ndf_dma_int_s cn52xx;
+ struct cvmx_mio_ndf_dma_int_s cn63xx;
+ struct cvmx_mio_ndf_dma_int_s cn63xxp1;
};
union cvmx_mio_ndf_dma_int_en {
@@ -1056,6 +1196,8 @@ union cvmx_mio_ndf_dma_int_en {
uint64_t done:1;
} s;
struct cvmx_mio_ndf_dma_int_en_s cn52xx;
+ struct cvmx_mio_ndf_dma_int_en_s cn63xx;
+ struct cvmx_mio_ndf_dma_int_en_s cn63xxp1;
};
union cvmx_mio_pll_ctl {
@@ -1078,6 +1220,173 @@ union cvmx_mio_pll_setting {
struct cvmx_mio_pll_setting_s cn31xx;
};
+union cvmx_mio_ptp_clock_cfg {
+ uint64_t u64;
+ struct cvmx_mio_ptp_clock_cfg_s {
+ uint64_t reserved_24_63:40;
+ uint64_t evcnt_in:6;
+ uint64_t evcnt_edge:1;
+ uint64_t evcnt_en:1;
+ uint64_t tstmp_in:6;
+ uint64_t tstmp_edge:1;
+ uint64_t tstmp_en:1;
+ uint64_t ext_clk_in:6;
+ uint64_t ext_clk_en:1;
+ uint64_t ptp_en:1;
+ } s;
+ struct cvmx_mio_ptp_clock_cfg_s cn63xx;
+ struct cvmx_mio_ptp_clock_cfg_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_clock_comp {
+ uint64_t u64;
+ struct cvmx_mio_ptp_clock_comp_s {
+ uint64_t nanosec:32;
+ uint64_t frnanosec:32;
+ } s;
+ struct cvmx_mio_ptp_clock_comp_s cn63xx;
+ struct cvmx_mio_ptp_clock_comp_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_clock_hi {
+ uint64_t u64;
+ struct cvmx_mio_ptp_clock_hi_s {
+ uint64_t nanosec:64;
+ } s;
+ struct cvmx_mio_ptp_clock_hi_s cn63xx;
+ struct cvmx_mio_ptp_clock_hi_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_clock_lo {
+ uint64_t u64;
+ struct cvmx_mio_ptp_clock_lo_s {
+ uint64_t reserved_32_63:32;
+ uint64_t frnanosec:32;
+ } s;
+ struct cvmx_mio_ptp_clock_lo_s cn63xx;
+ struct cvmx_mio_ptp_clock_lo_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_evt_cnt {
+ uint64_t u64;
+ struct cvmx_mio_ptp_evt_cnt_s {
+ uint64_t cntr:64;
+ } s;
+ struct cvmx_mio_ptp_evt_cnt_s cn63xx;
+ struct cvmx_mio_ptp_evt_cnt_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_timestamp {
+ uint64_t u64;
+ struct cvmx_mio_ptp_timestamp_s {
+ uint64_t nanosec:64;
+ } s;
+ struct cvmx_mio_ptp_timestamp_s cn63xx;
+ struct cvmx_mio_ptp_timestamp_s cn63xxp1;
+};
+
+union cvmx_mio_rst_boot {
+ uint64_t u64;
+ struct cvmx_mio_rst_boot_s {
+ uint64_t reserved_36_63:28;
+ uint64_t c_mul:6;
+ uint64_t pnr_mul:6;
+ uint64_t qlm2_spd:4;
+ uint64_t qlm1_spd:4;
+ uint64_t qlm0_spd:4;
+ uint64_t lboot:10;
+ uint64_t rboot:1;
+ uint64_t rboot_pin:1;
+ } s;
+ struct cvmx_mio_rst_boot_s cn63xx;
+ struct cvmx_mio_rst_boot_s cn63xxp1;
+};
+
+union cvmx_mio_rst_cfg {
+ uint64_t u64;
+ struct cvmx_mio_rst_cfg_s {
+ uint64_t bist_delay:58;
+ uint64_t reserved_3_5:3;
+ uint64_t cntl_clr_bist:1;
+ uint64_t warm_clr_bist:1;
+ uint64_t soft_clr_bist:1;
+ } s;
+ struct cvmx_mio_rst_cfg_s cn63xx;
+ struct cvmx_mio_rst_cfg_cn63xxp1 {
+ uint64_t bist_delay:58;
+ uint64_t reserved_2_5:4;
+ uint64_t warm_clr_bist:1;
+ uint64_t soft_clr_bist:1;
+ } cn63xxp1;
+};
+
+union cvmx_mio_rst_ctlx {
+ uint64_t u64;
+ struct cvmx_mio_rst_ctlx_s {
+ uint64_t reserved_10_63:54;
+ uint64_t prst_link:1;
+ uint64_t rst_done:1;
+ uint64_t rst_link:1;
+ uint64_t host_mode:1;
+ uint64_t prtmode:2;
+ uint64_t rst_drv:1;
+ uint64_t rst_rcv:1;
+ uint64_t rst_chip:1;
+ uint64_t rst_val:1;
+ } s;
+ struct cvmx_mio_rst_ctlx_s cn63xx;
+ struct cvmx_mio_rst_ctlx_cn63xxp1 {
+ uint64_t reserved_9_63:55;
+ uint64_t rst_done:1;
+ uint64_t rst_link:1;
+ uint64_t host_mode:1;
+ uint64_t prtmode:2;
+ uint64_t rst_drv:1;
+ uint64_t rst_rcv:1;
+ uint64_t rst_chip:1;
+ uint64_t rst_val:1;
+ } cn63xxp1;
+};
+
+union cvmx_mio_rst_delay {
+ uint64_t u64;
+ struct cvmx_mio_rst_delay_s {
+ uint64_t reserved_32_63:32;
+ uint64_t soft_rst_dly:16;
+ uint64_t warm_rst_dly:16;
+ } s;
+ struct cvmx_mio_rst_delay_s cn63xx;
+ struct cvmx_mio_rst_delay_s cn63xxp1;
+};
+
+union cvmx_mio_rst_int {
+ uint64_t u64;
+ struct cvmx_mio_rst_int_s {
+ uint64_t reserved_10_63:54;
+ uint64_t perst1:1;
+ uint64_t perst0:1;
+ uint64_t reserved_2_7:6;
+ uint64_t rst_link1:1;
+ uint64_t rst_link0:1;
+ } s;
+ struct cvmx_mio_rst_int_s cn63xx;
+ struct cvmx_mio_rst_int_s cn63xxp1;
+};
+
+union cvmx_mio_rst_int_en {
+ uint64_t u64;
+ struct cvmx_mio_rst_int_en_s {
+ uint64_t reserved_10_63:54;
+ uint64_t perst1:1;
+ uint64_t perst0:1;
+ uint64_t reserved_2_7:6;
+ uint64_t rst_link1:1;
+ uint64_t rst_link0:1;
+ } s;
+ struct cvmx_mio_rst_int_en_s cn63xx;
+ struct cvmx_mio_rst_int_en_s cn63xxp1;
+};
+
union cvmx_mio_twsx_int {
uint64_t u64;
struct cvmx_mio_twsx_int_s {
@@ -1115,6 +1424,8 @@ union cvmx_mio_twsx_int {
struct cvmx_mio_twsx_int_s cn56xxp1;
struct cvmx_mio_twsx_int_s cn58xx;
struct cvmx_mio_twsx_int_s cn58xxp1;
+ struct cvmx_mio_twsx_int_s cn63xx;
+ struct cvmx_mio_twsx_int_s cn63xxp1;
};
union cvmx_mio_twsx_sw_twsi {
@@ -1144,6 +1455,8 @@ union cvmx_mio_twsx_sw_twsi {
struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
struct cvmx_mio_twsx_sw_twsi_s cn58xx;
struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
+ struct cvmx_mio_twsx_sw_twsi_s cn63xx;
+ struct cvmx_mio_twsx_sw_twsi_s cn63xxp1;
};
union cvmx_mio_twsx_sw_twsi_ext {
@@ -1164,6 +1477,8 @@ union cvmx_mio_twsx_sw_twsi_ext {
struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
+ struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx;
+ struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1;
};
union cvmx_mio_twsx_twsi_sw {
@@ -1184,6 +1499,8 @@ union cvmx_mio_twsx_twsi_sw {
struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
struct cvmx_mio_twsx_twsi_sw_s cn58xx;
struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
+ struct cvmx_mio_twsx_twsi_sw_s cn63xx;
+ struct cvmx_mio_twsx_twsi_sw_s cn63xxp1;
};
union cvmx_mio_uartx_dlh {
@@ -1203,6 +1520,8 @@ union cvmx_mio_uartx_dlh {
struct cvmx_mio_uartx_dlh_s cn56xxp1;
struct cvmx_mio_uartx_dlh_s cn58xx;
struct cvmx_mio_uartx_dlh_s cn58xxp1;
+ struct cvmx_mio_uartx_dlh_s cn63xx;
+ struct cvmx_mio_uartx_dlh_s cn63xxp1;
};
union cvmx_mio_uartx_dll {
@@ -1222,6 +1541,8 @@ union cvmx_mio_uartx_dll {
struct cvmx_mio_uartx_dll_s cn56xxp1;
struct cvmx_mio_uartx_dll_s cn58xx;
struct cvmx_mio_uartx_dll_s cn58xxp1;
+ struct cvmx_mio_uartx_dll_s cn63xx;
+ struct cvmx_mio_uartx_dll_s cn63xxp1;
};
union cvmx_mio_uartx_far {
@@ -1241,6 +1562,8 @@ union cvmx_mio_uartx_far {
struct cvmx_mio_uartx_far_s cn56xxp1;
struct cvmx_mio_uartx_far_s cn58xx;
struct cvmx_mio_uartx_far_s cn58xxp1;
+ struct cvmx_mio_uartx_far_s cn63xx;
+ struct cvmx_mio_uartx_far_s cn63xxp1;
};
union cvmx_mio_uartx_fcr {
@@ -1265,6 +1588,8 @@ union cvmx_mio_uartx_fcr {
struct cvmx_mio_uartx_fcr_s cn56xxp1;
struct cvmx_mio_uartx_fcr_s cn58xx;
struct cvmx_mio_uartx_fcr_s cn58xxp1;
+ struct cvmx_mio_uartx_fcr_s cn63xx;
+ struct cvmx_mio_uartx_fcr_s cn63xxp1;
};
union cvmx_mio_uartx_htx {
@@ -1284,6 +1609,8 @@ union cvmx_mio_uartx_htx {
struct cvmx_mio_uartx_htx_s cn56xxp1;
struct cvmx_mio_uartx_htx_s cn58xx;
struct cvmx_mio_uartx_htx_s cn58xxp1;
+ struct cvmx_mio_uartx_htx_s cn63xx;
+ struct cvmx_mio_uartx_htx_s cn63xxp1;
};
union cvmx_mio_uartx_ier {
@@ -1308,6 +1635,8 @@ union cvmx_mio_uartx_ier {
struct cvmx_mio_uartx_ier_s cn56xxp1;
struct cvmx_mio_uartx_ier_s cn58xx;
struct cvmx_mio_uartx_ier_s cn58xxp1;
+ struct cvmx_mio_uartx_ier_s cn63xx;
+ struct cvmx_mio_uartx_ier_s cn63xxp1;
};
union cvmx_mio_uartx_iir {
@@ -1329,6 +1658,8 @@ union cvmx_mio_uartx_iir {
struct cvmx_mio_uartx_iir_s cn56xxp1;
struct cvmx_mio_uartx_iir_s cn58xx;
struct cvmx_mio_uartx_iir_s cn58xxp1;
+ struct cvmx_mio_uartx_iir_s cn63xx;
+ struct cvmx_mio_uartx_iir_s cn63xxp1;
};
union cvmx_mio_uartx_lcr {
@@ -1354,6 +1685,8 @@ union cvmx_mio_uartx_lcr {
struct cvmx_mio_uartx_lcr_s cn56xxp1;
struct cvmx_mio_uartx_lcr_s cn58xx;
struct cvmx_mio_uartx_lcr_s cn58xxp1;
+ struct cvmx_mio_uartx_lcr_s cn63xx;
+ struct cvmx_mio_uartx_lcr_s cn63xxp1;
};
union cvmx_mio_uartx_lsr {
@@ -1380,6 +1713,8 @@ union cvmx_mio_uartx_lsr {
struct cvmx_mio_uartx_lsr_s cn56xxp1;
struct cvmx_mio_uartx_lsr_s cn58xx;
struct cvmx_mio_uartx_lsr_s cn58xxp1;
+ struct cvmx_mio_uartx_lsr_s cn63xx;
+ struct cvmx_mio_uartx_lsr_s cn63xxp1;
};
union cvmx_mio_uartx_mcr {
@@ -1404,6 +1739,8 @@ union cvmx_mio_uartx_mcr {
struct cvmx_mio_uartx_mcr_s cn56xxp1;
struct cvmx_mio_uartx_mcr_s cn58xx;
struct cvmx_mio_uartx_mcr_s cn58xxp1;
+ struct cvmx_mio_uartx_mcr_s cn63xx;
+ struct cvmx_mio_uartx_mcr_s cn63xxp1;
};
union cvmx_mio_uartx_msr {
@@ -1430,6 +1767,8 @@ union cvmx_mio_uartx_msr {
struct cvmx_mio_uartx_msr_s cn56xxp1;
struct cvmx_mio_uartx_msr_s cn58xx;
struct cvmx_mio_uartx_msr_s cn58xxp1;
+ struct cvmx_mio_uartx_msr_s cn63xx;
+ struct cvmx_mio_uartx_msr_s cn63xxp1;
};
union cvmx_mio_uartx_rbr {
@@ -1449,6 +1788,8 @@ union cvmx_mio_uartx_rbr {
struct cvmx_mio_uartx_rbr_s cn56xxp1;
struct cvmx_mio_uartx_rbr_s cn58xx;
struct cvmx_mio_uartx_rbr_s cn58xxp1;
+ struct cvmx_mio_uartx_rbr_s cn63xx;
+ struct cvmx_mio_uartx_rbr_s cn63xxp1;
};
union cvmx_mio_uartx_rfl {
@@ -1468,6 +1809,8 @@ union cvmx_mio_uartx_rfl {
struct cvmx_mio_uartx_rfl_s cn56xxp1;
struct cvmx_mio_uartx_rfl_s cn58xx;
struct cvmx_mio_uartx_rfl_s cn58xxp1;
+ struct cvmx_mio_uartx_rfl_s cn63xx;
+ struct cvmx_mio_uartx_rfl_s cn63xxp1;
};
union cvmx_mio_uartx_rfw {
@@ -1489,6 +1832,8 @@ union cvmx_mio_uartx_rfw {
struct cvmx_mio_uartx_rfw_s cn56xxp1;
struct cvmx_mio_uartx_rfw_s cn58xx;
struct cvmx_mio_uartx_rfw_s cn58xxp1;
+ struct cvmx_mio_uartx_rfw_s cn63xx;
+ struct cvmx_mio_uartx_rfw_s cn63xxp1;
};
union cvmx_mio_uartx_sbcr {
@@ -1508,6 +1853,8 @@ union cvmx_mio_uartx_sbcr {
struct cvmx_mio_uartx_sbcr_s cn56xxp1;
struct cvmx_mio_uartx_sbcr_s cn58xx;
struct cvmx_mio_uartx_sbcr_s cn58xxp1;
+ struct cvmx_mio_uartx_sbcr_s cn63xx;
+ struct cvmx_mio_uartx_sbcr_s cn63xxp1;
};
union cvmx_mio_uartx_scr {
@@ -1527,6 +1874,8 @@ union cvmx_mio_uartx_scr {
struct cvmx_mio_uartx_scr_s cn56xxp1;
struct cvmx_mio_uartx_scr_s cn58xx;
struct cvmx_mio_uartx_scr_s cn58xxp1;
+ struct cvmx_mio_uartx_scr_s cn63xx;
+ struct cvmx_mio_uartx_scr_s cn63xxp1;
};
union cvmx_mio_uartx_sfe {
@@ -1546,6 +1895,8 @@ union cvmx_mio_uartx_sfe {
struct cvmx_mio_uartx_sfe_s cn56xxp1;
struct cvmx_mio_uartx_sfe_s cn58xx;
struct cvmx_mio_uartx_sfe_s cn58xxp1;
+ struct cvmx_mio_uartx_sfe_s cn63xx;
+ struct cvmx_mio_uartx_sfe_s cn63xxp1;
};
union cvmx_mio_uartx_srr {
@@ -1567,6 +1918,8 @@ union cvmx_mio_uartx_srr {
struct cvmx_mio_uartx_srr_s cn56xxp1;
struct cvmx_mio_uartx_srr_s cn58xx;
struct cvmx_mio_uartx_srr_s cn58xxp1;
+ struct cvmx_mio_uartx_srr_s cn63xx;
+ struct cvmx_mio_uartx_srr_s cn63xxp1;
};
union cvmx_mio_uartx_srt {
@@ -1586,6 +1939,8 @@ union cvmx_mio_uartx_srt {
struct cvmx_mio_uartx_srt_s cn56xxp1;
struct cvmx_mio_uartx_srt_s cn58xx;
struct cvmx_mio_uartx_srt_s cn58xxp1;
+ struct cvmx_mio_uartx_srt_s cn63xx;
+ struct cvmx_mio_uartx_srt_s cn63xxp1;
};
union cvmx_mio_uartx_srts {
@@ -1605,6 +1960,8 @@ union cvmx_mio_uartx_srts {
struct cvmx_mio_uartx_srts_s cn56xxp1;
struct cvmx_mio_uartx_srts_s cn58xx;
struct cvmx_mio_uartx_srts_s cn58xxp1;
+ struct cvmx_mio_uartx_srts_s cn63xx;
+ struct cvmx_mio_uartx_srts_s cn63xxp1;
};
union cvmx_mio_uartx_stt {
@@ -1624,6 +1981,8 @@ union cvmx_mio_uartx_stt {
struct cvmx_mio_uartx_stt_s cn56xxp1;
struct cvmx_mio_uartx_stt_s cn58xx;
struct cvmx_mio_uartx_stt_s cn58xxp1;
+ struct cvmx_mio_uartx_stt_s cn63xx;
+ struct cvmx_mio_uartx_stt_s cn63xxp1;
};
union cvmx_mio_uartx_tfl {
@@ -1643,6 +2002,8 @@ union cvmx_mio_uartx_tfl {
struct cvmx_mio_uartx_tfl_s cn56xxp1;
struct cvmx_mio_uartx_tfl_s cn58xx;
struct cvmx_mio_uartx_tfl_s cn58xxp1;
+ struct cvmx_mio_uartx_tfl_s cn63xx;
+ struct cvmx_mio_uartx_tfl_s cn63xxp1;
};
union cvmx_mio_uartx_tfr {
@@ -1662,6 +2023,8 @@ union cvmx_mio_uartx_tfr {
struct cvmx_mio_uartx_tfr_s cn56xxp1;
struct cvmx_mio_uartx_tfr_s cn58xx;
struct cvmx_mio_uartx_tfr_s cn58xxp1;
+ struct cvmx_mio_uartx_tfr_s cn63xx;
+ struct cvmx_mio_uartx_tfr_s cn63xxp1;
};
union cvmx_mio_uartx_thr {
@@ -1681,6 +2044,8 @@ union cvmx_mio_uartx_thr {
struct cvmx_mio_uartx_thr_s cn56xxp1;
struct cvmx_mio_uartx_thr_s cn58xx;
struct cvmx_mio_uartx_thr_s cn58xxp1;
+ struct cvmx_mio_uartx_thr_s cn63xx;
+ struct cvmx_mio_uartx_thr_s cn63xxp1;
};
union cvmx_mio_uartx_usr {
@@ -1704,6 +2069,8 @@ union cvmx_mio_uartx_usr {
struct cvmx_mio_uartx_usr_s cn56xxp1;
struct cvmx_mio_uartx_usr_s cn58xx;
struct cvmx_mio_uartx_usr_s cn58xxp1;
+ struct cvmx_mio_uartx_usr_s cn63xx;
+ struct cvmx_mio_uartx_usr_s cn63xxp1;
};
union cvmx_mio_uart2_dlh {
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
index dab6dca492f9..7057c447e69e 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,52 +28,52 @@
#ifndef __CVMX_MIXX_DEFS_H__
#define __CVMX_MIXX_DEFS_H__
-#define CVMX_MIXX_BIST(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_CTL(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_INTENA(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_IRCNT(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_IRHWM(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_IRING1(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_IRING2(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ISR(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ORCNT(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ORHWM(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ORING1(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ORING2(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_REMCNT(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048)
union cvmx_mixx_bist {
uint64_t u64;
struct cvmx_mixx_bist_s {
- uint64_t reserved_4_63:60;
+ uint64_t reserved_6_63:58;
+ uint64_t opfdat:1;
+ uint64_t mrgdat:1;
uint64_t mrqdat:1;
uint64_t ipfdat:1;
uint64_t irfdat:1;
uint64_t orfdat:1;
} s;
- struct cvmx_mixx_bist_s cn52xx;
- struct cvmx_mixx_bist_s cn52xxp1;
- struct cvmx_mixx_bist_s cn56xx;
- struct cvmx_mixx_bist_s cn56xxp1;
+ struct cvmx_mixx_bist_cn52xx {
+ uint64_t reserved_4_63:60;
+ uint64_t mrqdat:1;
+ uint64_t ipfdat:1;
+ uint64_t irfdat:1;
+ uint64_t orfdat:1;
+ } cn52xx;
+ struct cvmx_mixx_bist_cn52xx cn52xxp1;
+ struct cvmx_mixx_bist_cn52xx cn56xx;
+ struct cvmx_mixx_bist_cn52xx cn56xxp1;
+ struct cvmx_mixx_bist_s cn63xx;
+ struct cvmx_mixx_bist_s cn63xxp1;
};
union cvmx_mixx_ctl {
uint64_t u64;
struct cvmx_mixx_ctl_s {
- uint64_t reserved_8_63:56;
+ uint64_t reserved_12_63:52;
+ uint64_t ts_thresh:4;
uint64_t crc_strip:1;
uint64_t busy:1;
uint64_t en:1;
@@ -82,16 +82,28 @@ union cvmx_mixx_ctl {
uint64_t nbtarb:1;
uint64_t mrq_hwm:2;
} s;
- struct cvmx_mixx_ctl_s cn52xx;
- struct cvmx_mixx_ctl_s cn52xxp1;
- struct cvmx_mixx_ctl_s cn56xx;
- struct cvmx_mixx_ctl_s cn56xxp1;
+ struct cvmx_mixx_ctl_cn52xx {
+ uint64_t reserved_8_63:56;
+ uint64_t crc_strip:1;
+ uint64_t busy:1;
+ uint64_t en:1;
+ uint64_t reset:1;
+ uint64_t lendian:1;
+ uint64_t nbtarb:1;
+ uint64_t mrq_hwm:2;
+ } cn52xx;
+ struct cvmx_mixx_ctl_cn52xx cn52xxp1;
+ struct cvmx_mixx_ctl_cn52xx cn56xx;
+ struct cvmx_mixx_ctl_cn52xx cn56xxp1;
+ struct cvmx_mixx_ctl_s cn63xx;
+ struct cvmx_mixx_ctl_s cn63xxp1;
};
union cvmx_mixx_intena {
uint64_t u64;
struct cvmx_mixx_intena_s {
- uint64_t reserved_7_63:57;
+ uint64_t reserved_8_63:56;
+ uint64_t tsena:1;
uint64_t orunena:1;
uint64_t irunena:1;
uint64_t data_drpena:1;
@@ -100,10 +112,21 @@ union cvmx_mixx_intena {
uint64_t ivfena:1;
uint64_t ovfena:1;
} s;
- struct cvmx_mixx_intena_s cn52xx;
- struct cvmx_mixx_intena_s cn52xxp1;
- struct cvmx_mixx_intena_s cn56xx;
- struct cvmx_mixx_intena_s cn56xxp1;
+ struct cvmx_mixx_intena_cn52xx {
+ uint64_t reserved_7_63:57;
+ uint64_t orunena:1;
+ uint64_t irunena:1;
+ uint64_t data_drpena:1;
+ uint64_t ithena:1;
+ uint64_t othena:1;
+ uint64_t ivfena:1;
+ uint64_t ovfena:1;
+ } cn52xx;
+ struct cvmx_mixx_intena_cn52xx cn52xxp1;
+ struct cvmx_mixx_intena_cn52xx cn56xx;
+ struct cvmx_mixx_intena_cn52xx cn56xxp1;
+ struct cvmx_mixx_intena_s cn63xx;
+ struct cvmx_mixx_intena_s cn63xxp1;
};
union cvmx_mixx_ircnt {
@@ -116,6 +139,8 @@ union cvmx_mixx_ircnt {
struct cvmx_mixx_ircnt_s cn52xxp1;
struct cvmx_mixx_ircnt_s cn56xx;
struct cvmx_mixx_ircnt_s cn56xxp1;
+ struct cvmx_mixx_ircnt_s cn63xx;
+ struct cvmx_mixx_ircnt_s cn63xxp1;
};
union cvmx_mixx_irhwm {
@@ -129,21 +154,30 @@ union cvmx_mixx_irhwm {
struct cvmx_mixx_irhwm_s cn52xxp1;
struct cvmx_mixx_irhwm_s cn56xx;
struct cvmx_mixx_irhwm_s cn56xxp1;
+ struct cvmx_mixx_irhwm_s cn63xx;
+ struct cvmx_mixx_irhwm_s cn63xxp1;
};
union cvmx_mixx_iring1 {
uint64_t u64;
struct cvmx_mixx_iring1_s {
+ uint64_t reserved_60_63:4;
+ uint64_t isize:20;
+ uint64_t ibase:37;
+ uint64_t reserved_0_2:3;
+ } s;
+ struct cvmx_mixx_iring1_cn52xx {
uint64_t reserved_60_63:4;
uint64_t isize:20;
uint64_t reserved_36_39:4;
uint64_t ibase:33;
uint64_t reserved_0_2:3;
- } s;
- struct cvmx_mixx_iring1_s cn52xx;
- struct cvmx_mixx_iring1_s cn52xxp1;
- struct cvmx_mixx_iring1_s cn56xx;
- struct cvmx_mixx_iring1_s cn56xxp1;
+ } cn52xx;
+ struct cvmx_mixx_iring1_cn52xx cn52xxp1;
+ struct cvmx_mixx_iring1_cn52xx cn56xx;
+ struct cvmx_mixx_iring1_cn52xx cn56xxp1;
+ struct cvmx_mixx_iring1_s cn63xx;
+ struct cvmx_mixx_iring1_s cn63xxp1;
};
union cvmx_mixx_iring2 {
@@ -158,12 +192,15 @@ union cvmx_mixx_iring2 {
struct cvmx_mixx_iring2_s cn52xxp1;
struct cvmx_mixx_iring2_s cn56xx;
struct cvmx_mixx_iring2_s cn56xxp1;
+ struct cvmx_mixx_iring2_s cn63xx;
+ struct cvmx_mixx_iring2_s cn63xxp1;
};
union cvmx_mixx_isr {
uint64_t u64;
struct cvmx_mixx_isr_s {
- uint64_t reserved_7_63:57;
+ uint64_t reserved_8_63:56;
+ uint64_t ts:1;
uint64_t orun:1;
uint64_t irun:1;
uint64_t data_drp:1;
@@ -172,10 +209,21 @@ union cvmx_mixx_isr {
uint64_t idblovf:1;
uint64_t odblovf:1;
} s;
- struct cvmx_mixx_isr_s cn52xx;
- struct cvmx_mixx_isr_s cn52xxp1;
- struct cvmx_mixx_isr_s cn56xx;
- struct cvmx_mixx_isr_s cn56xxp1;
+ struct cvmx_mixx_isr_cn52xx {
+ uint64_t reserved_7_63:57;
+ uint64_t orun:1;
+ uint64_t irun:1;
+ uint64_t data_drp:1;
+ uint64_t irthresh:1;
+ uint64_t orthresh:1;
+ uint64_t idblovf:1;
+ uint64_t odblovf:1;
+ } cn52xx;
+ struct cvmx_mixx_isr_cn52xx cn52xxp1;
+ struct cvmx_mixx_isr_cn52xx cn56xx;
+ struct cvmx_mixx_isr_cn52xx cn56xxp1;
+ struct cvmx_mixx_isr_s cn63xx;
+ struct cvmx_mixx_isr_s cn63xxp1;
};
union cvmx_mixx_orcnt {
@@ -188,6 +236,8 @@ union cvmx_mixx_orcnt {
struct cvmx_mixx_orcnt_s cn52xxp1;
struct cvmx_mixx_orcnt_s cn56xx;
struct cvmx_mixx_orcnt_s cn56xxp1;
+ struct cvmx_mixx_orcnt_s cn63xx;
+ struct cvmx_mixx_orcnt_s cn63xxp1;
};
union cvmx_mixx_orhwm {
@@ -200,21 +250,30 @@ union cvmx_mixx_orhwm {
struct cvmx_mixx_orhwm_s cn52xxp1;
struct cvmx_mixx_orhwm_s cn56xx;
struct cvmx_mixx_orhwm_s cn56xxp1;
+ struct cvmx_mixx_orhwm_s cn63xx;
+ struct cvmx_mixx_orhwm_s cn63xxp1;
};
union cvmx_mixx_oring1 {
uint64_t u64;
struct cvmx_mixx_oring1_s {
+ uint64_t reserved_60_63:4;
+ uint64_t osize:20;
+ uint64_t obase:37;
+ uint64_t reserved_0_2:3;
+ } s;
+ struct cvmx_mixx_oring1_cn52xx {
uint64_t reserved_60_63:4;
uint64_t osize:20;
uint64_t reserved_36_39:4;
uint64_t obase:33;
uint64_t reserved_0_2:3;
- } s;
- struct cvmx_mixx_oring1_s cn52xx;
- struct cvmx_mixx_oring1_s cn52xxp1;
- struct cvmx_mixx_oring1_s cn56xx;
- struct cvmx_mixx_oring1_s cn56xxp1;
+ } cn52xx;
+ struct cvmx_mixx_oring1_cn52xx cn52xxp1;
+ struct cvmx_mixx_oring1_cn52xx cn56xx;
+ struct cvmx_mixx_oring1_cn52xx cn56xxp1;
+ struct cvmx_mixx_oring1_s cn63xx;
+ struct cvmx_mixx_oring1_s cn63xxp1;
};
union cvmx_mixx_oring2 {
@@ -229,6 +288,8 @@ union cvmx_mixx_oring2 {
struct cvmx_mixx_oring2_s cn52xxp1;
struct cvmx_mixx_oring2_s cn56xx;
struct cvmx_mixx_oring2_s cn56xxp1;
+ struct cvmx_mixx_oring2_s cn63xx;
+ struct cvmx_mixx_oring2_s cn63xxp1;
};
union cvmx_mixx_remcnt {
@@ -243,6 +304,31 @@ union cvmx_mixx_remcnt {
struct cvmx_mixx_remcnt_s cn52xxp1;
struct cvmx_mixx_remcnt_s cn56xx;
struct cvmx_mixx_remcnt_s cn56xxp1;
+ struct cvmx_mixx_remcnt_s cn63xx;
+ struct cvmx_mixx_remcnt_s cn63xxp1;
+};
+
+union cvmx_mixx_tsctl {
+ uint64_t u64;
+ struct cvmx_mixx_tsctl_s {
+ uint64_t reserved_21_63:43;
+ uint64_t tsavl:5;
+ uint64_t reserved_13_15:3;
+ uint64_t tstot:5;
+ uint64_t reserved_5_7:3;
+ uint64_t tscnt:5;
+ } s;
+ struct cvmx_mixx_tsctl_s cn63xx;
+ struct cvmx_mixx_tsctl_s cn63xxp1;
+};
+
+union cvmx_mixx_tstamp {
+ uint64_t u64;
+ struct cvmx_mixx_tstamp_s {
+ uint64_t tstamp:64;
+ } s;
+ struct cvmx_mixx_tstamp_s cn63xx;
+ struct cvmx_mixx_tstamp_s cn63xxp1;
};
#endif
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-npei-defs.h
index 4b347bb8ce80..9899a9d2ba72 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-npei-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,206 +28,114 @@
#ifndef __CVMX_NPEI_DEFS_H__
#define __CVMX_NPEI_DEFS_H__
-#define CVMX_NPEI_BAR1_INDEXX(offset) \
- (0x0000000000000000ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_BIST_STATUS \
- (0x0000000000000580ull)
-#define CVMX_NPEI_BIST_STATUS2 \
- (0x0000000000000680ull)
-#define CVMX_NPEI_CTL_PORT0 \
- (0x0000000000000250ull)
-#define CVMX_NPEI_CTL_PORT1 \
- (0x0000000000000260ull)
-#define CVMX_NPEI_CTL_STATUS \
- (0x0000000000000570ull)
-#define CVMX_NPEI_CTL_STATUS2 \
- (0x0000000000003C00ull)
-#define CVMX_NPEI_DATA_OUT_CNT \
- (0x00000000000005F0ull)
-#define CVMX_NPEI_DBG_DATA \
- (0x0000000000000510ull)
-#define CVMX_NPEI_DBG_SELECT \
- (0x0000000000000500ull)
-#define CVMX_NPEI_DMA0_INT_LEVEL \
- (0x00000000000005C0ull)
-#define CVMX_NPEI_DMA1_INT_LEVEL \
- (0x00000000000005D0ull)
-#define CVMX_NPEI_DMAX_COUNTS(offset) \
- (0x0000000000000450ull + (((offset) & 7) * 16))
-#define CVMX_NPEI_DMAX_DBELL(offset) \
- (0x00000000000003B0ull + (((offset) & 7) * 16))
-#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) \
- (0x0000000000000400ull + (((offset) & 7) * 16))
-#define CVMX_NPEI_DMAX_NADDR(offset) \
- (0x00000000000004A0ull + (((offset) & 7) * 16))
-#define CVMX_NPEI_DMA_CNTS \
- (0x00000000000005E0ull)
-#define CVMX_NPEI_DMA_CONTROL \
- (0x00000000000003A0ull)
-#define CVMX_NPEI_INT_A_ENB \
- (0x0000000000000560ull)
-#define CVMX_NPEI_INT_A_ENB2 \
- (0x0000000000003CE0ull)
-#define CVMX_NPEI_INT_A_SUM \
- (0x0000000000000550ull)
-#define CVMX_NPEI_INT_ENB \
- (0x0000000000000540ull)
-#define CVMX_NPEI_INT_ENB2 \
- (0x0000000000003CD0ull)
-#define CVMX_NPEI_INT_INFO \
- (0x0000000000000590ull)
-#define CVMX_NPEI_INT_SUM \
- (0x0000000000000530ull)
-#define CVMX_NPEI_INT_SUM2 \
- (0x0000000000003CC0ull)
-#define CVMX_NPEI_LAST_WIN_RDATA0 \
- (0x0000000000000600ull)
-#define CVMX_NPEI_LAST_WIN_RDATA1 \
- (0x0000000000000610ull)
-#define CVMX_NPEI_MEM_ACCESS_CTL \
- (0x00000000000004F0ull)
-#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) \
- (0x0000000000000340ull + (((offset) & 31) * 16) - 16 * 12)
-#define CVMX_NPEI_MSI_ENB0 \
- (0x0000000000003C50ull)
-#define CVMX_NPEI_MSI_ENB1 \
- (0x0000000000003C60ull)
-#define CVMX_NPEI_MSI_ENB2 \
- (0x0000000000003C70ull)
-#define CVMX_NPEI_MSI_ENB3 \
- (0x0000000000003C80ull)
-#define CVMX_NPEI_MSI_RCV0 \
- (0x0000000000003C10ull)
-#define CVMX_NPEI_MSI_RCV1 \
- (0x0000000000003C20ull)
-#define CVMX_NPEI_MSI_RCV2 \
- (0x0000000000003C30ull)
-#define CVMX_NPEI_MSI_RCV3 \
- (0x0000000000003C40ull)
-#define CVMX_NPEI_MSI_RD_MAP \
- (0x0000000000003CA0ull)
-#define CVMX_NPEI_MSI_W1C_ENB0 \
- (0x0000000000003CF0ull)
-#define CVMX_NPEI_MSI_W1C_ENB1 \
- (0x0000000000003D00ull)
-#define CVMX_NPEI_MSI_W1C_ENB2 \
- (0x0000000000003D10ull)
-#define CVMX_NPEI_MSI_W1C_ENB3 \
- (0x0000000000003D20ull)
-#define CVMX_NPEI_MSI_W1S_ENB0 \
- (0x0000000000003D30ull)
-#define CVMX_NPEI_MSI_W1S_ENB1 \
- (0x0000000000003D40ull)
-#define CVMX_NPEI_MSI_W1S_ENB2 \
- (0x0000000000003D50ull)
-#define CVMX_NPEI_MSI_W1S_ENB3 \
- (0x0000000000003D60ull)
-#define CVMX_NPEI_MSI_WR_MAP \
- (0x0000000000003C90ull)
-#define CVMX_NPEI_PCIE_CREDIT_CNT \
- (0x0000000000003D70ull)
-#define CVMX_NPEI_PCIE_MSI_RCV \
- (0x0000000000003CB0ull)
-#define CVMX_NPEI_PCIE_MSI_RCV_B1 \
- (0x0000000000000650ull)
-#define CVMX_NPEI_PCIE_MSI_RCV_B2 \
- (0x0000000000000660ull)
-#define CVMX_NPEI_PCIE_MSI_RCV_B3 \
- (0x0000000000000670ull)
-#define CVMX_NPEI_PKTX_CNTS(offset) \
- (0x0000000000002400ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) \
- (0x0000000000002800ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
- (0x0000000000002C00ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
- (0x0000000000003000ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) \
- (0x0000000000003400ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_IN_BP(offset) \
- (0x0000000000003800ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) \
- (0x0000000000001400ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
- (0x0000000000001800ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
- (0x0000000000001C00ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKT_CNT_INT \
- (0x0000000000001110ull)
-#define CVMX_NPEI_PKT_CNT_INT_ENB \
- (0x0000000000001130ull)
-#define CVMX_NPEI_PKT_DATA_OUT_ES \
- (0x00000000000010B0ull)
-#define CVMX_NPEI_PKT_DATA_OUT_NS \
- (0x00000000000010A0ull)
-#define CVMX_NPEI_PKT_DATA_OUT_ROR \
- (0x0000000000001090ull)
-#define CVMX_NPEI_PKT_DPADDR \
- (0x0000000000001080ull)
-#define CVMX_NPEI_PKT_INPUT_CONTROL \
- (0x0000000000001150ull)
-#define CVMX_NPEI_PKT_INSTR_ENB \
- (0x0000000000001000ull)
-#define CVMX_NPEI_PKT_INSTR_RD_SIZE \
- (0x0000000000001190ull)
-#define CVMX_NPEI_PKT_INSTR_SIZE \
- (0x0000000000001020ull)
-#define CVMX_NPEI_PKT_INT_LEVELS \
- (0x0000000000001100ull)
-#define CVMX_NPEI_PKT_IN_BP \
- (0x00000000000006B0ull)
-#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) \
- (0x0000000000002000ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKT_IN_INSTR_COUNTS \
- (0x00000000000006A0ull)
-#define CVMX_NPEI_PKT_IN_PCIE_PORT \
- (0x00000000000011A0ull)
-#define CVMX_NPEI_PKT_IPTR \
- (0x0000000000001070ull)
-#define CVMX_NPEI_PKT_OUTPUT_WMARK \
- (0x0000000000001160ull)
-#define CVMX_NPEI_PKT_OUT_BMODE \
- (0x00000000000010D0ull)
-#define CVMX_NPEI_PKT_OUT_ENB \
- (0x0000000000001010ull)
-#define CVMX_NPEI_PKT_PCIE_PORT \
- (0x00000000000010E0ull)
-#define CVMX_NPEI_PKT_PORT_IN_RST \
- (0x0000000000000690ull)
-#define CVMX_NPEI_PKT_SLIST_ES \
- (0x0000000000001050ull)
-#define CVMX_NPEI_PKT_SLIST_ID_SIZE \
- (0x0000000000001180ull)
-#define CVMX_NPEI_PKT_SLIST_NS \
- (0x0000000000001040ull)
-#define CVMX_NPEI_PKT_SLIST_ROR \
- (0x0000000000001030ull)
-#define CVMX_NPEI_PKT_TIME_INT \
- (0x0000000000001120ull)
-#define CVMX_NPEI_PKT_TIME_INT_ENB \
- (0x0000000000001140ull)
-#define CVMX_NPEI_RSL_INT_BLOCKS \
- (0x0000000000000520ull)
-#define CVMX_NPEI_SCRATCH_1 \
- (0x0000000000000270ull)
-#define CVMX_NPEI_STATE1 \
- (0x0000000000000620ull)
-#define CVMX_NPEI_STATE2 \
- (0x0000000000000630ull)
-#define CVMX_NPEI_STATE3 \
- (0x0000000000000640ull)
-#define CVMX_NPEI_WINDOW_CTL \
- (0x0000000000000380ull)
-#define CVMX_NPEI_WIN_RD_ADDR \
- (0x0000000000000210ull)
-#define CVMX_NPEI_WIN_RD_DATA \
- (0x0000000000000240ull)
-#define CVMX_NPEI_WIN_WR_ADDR \
- (0x0000000000000200ull)
-#define CVMX_NPEI_WIN_WR_DATA \
- (0x0000000000000220ull)
-#define CVMX_NPEI_WIN_WR_MASK \
- (0x0000000000000230ull)
+#define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull)
+#define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull)
+#define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull)
+#define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull)
+#define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull)
+#define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull)
+#define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull)
+#define CVMX_NPEI_DBG_DATA (0x0000000000000510ull)
+#define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull)
+#define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull)
+#define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull)
+#define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull)
+#define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull)
+#define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull)
+#define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull)
+#define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull)
+#define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull)
+#define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull)
+#define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull)
+#define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull)
+#define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull)
+#define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull)
+#define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull)
+#define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull)
+#define CVMX_NPEI_INT_ENB (0x0000000000000540ull)
+#define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull)
+#define CVMX_NPEI_INT_INFO (0x0000000000000590ull)
+#define CVMX_NPEI_INT_SUM (0x0000000000000530ull)
+#define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull)
+#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
+#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
+#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
+#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12)
+#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
+#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
+#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
+#define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull)
+#define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull)
+#define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull)
+#define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull)
+#define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull)
+#define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull)
+#define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
+#define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull)
+#define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull)
+#define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull)
+#define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull)
+#define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull)
+#define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull)
+#define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull)
+#define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull)
+#define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull)
+#define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
+#define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull)
+#define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull)
+#define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
+#define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
+#define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
+#define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull)
+#define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull)
+#define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull)
+#define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull)
+#define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull)
+#define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull)
+#define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull)
+#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull)
+#define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull)
+#define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull)
+#define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull)
+#define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull)
+#define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull)
+#define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull)
+#define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull)
+#define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull)
+#define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull)
+#define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull)
+#define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull)
+#define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull)
+#define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull)
+#define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull)
+#define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull)
+#define CVMX_NPEI_STATE1 (0x0000000000000620ull)
+#define CVMX_NPEI_STATE2 (0x0000000000000630ull)
+#define CVMX_NPEI_STATE3 (0x0000000000000640ull)
+#define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull)
+#define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull)
+#define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull)
+#define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull)
+#define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull)
+#define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull)
union cvmx_npei_bar1_indexx {
uint32_t u32;
@@ -248,9 +156,7 @@ union cvmx_npei_bist_status {
uint64_t u64;
struct cvmx_npei_bist_status_s {
uint64_t pkt_rdf:1;
- uint64_t pkt_pmem:1;
- uint64_t pkt_p1:1;
- uint64_t reserved_60_60:1;
+ uint64_t reserved_60_62:3;
uint64_t pcr_gim:1;
uint64_t pkt_pif:1;
uint64_t pcsr_int:1;
@@ -301,9 +207,7 @@ union cvmx_npei_bist_status {
} s;
struct cvmx_npei_bist_status_cn52xx {
uint64_t pkt_rdf:1;
- uint64_t pkt_pmem:1;
- uint64_t pkt_p1:1;
- uint64_t reserved_60_60:1;
+ uint64_t reserved_60_62:3;
uint64_t pcr_gim:1;
uint64_t pkt_pif:1;
uint64_t pcsr_int:1;
@@ -410,66 +314,7 @@ union cvmx_npei_bist_status {
uint64_t msi:1;
uint64_t ncb_cmd:1;
} cn52xxp1;
- struct cvmx_npei_bist_status_cn56xx {
- uint64_t pkt_rdf:1;
- uint64_t reserved_60_62:3;
- uint64_t pcr_gim:1;
- uint64_t pkt_pif:1;
- uint64_t pcsr_int:1;
- uint64_t pcsr_im:1;
- uint64_t pcsr_cnt:1;
- uint64_t pcsr_id:1;
- uint64_t pcsr_sl:1;
- uint64_t pkt_imem:1;
- uint64_t pkt_pfm:1;
- uint64_t pkt_pof:1;
- uint64_t reserved_48_49:2;
- uint64_t pkt_pop0:1;
- uint64_t pkt_pop1:1;
- uint64_t d0_mem:1;
- uint64_t d1_mem:1;
- uint64_t d2_mem:1;
- uint64_t d3_mem:1;
- uint64_t d4_mem:1;
- uint64_t ds_mem:1;
- uint64_t reserved_36_39:4;
- uint64_t d0_pst:1;
- uint64_t d1_pst:1;
- uint64_t d2_pst:1;
- uint64_t d3_pst:1;
- uint64_t d4_pst:1;
- uint64_t n2p0_c:1;
- uint64_t n2p0_o:1;
- uint64_t n2p1_c:1;
- uint64_t n2p1_o:1;
- uint64_t cpl_p0:1;
- uint64_t cpl_p1:1;
- uint64_t p2n1_po:1;
- uint64_t p2n1_no:1;
- uint64_t p2n1_co:1;
- uint64_t p2n0_po:1;
- uint64_t p2n0_no:1;
- uint64_t p2n0_co:1;
- uint64_t p2n0_c0:1;
- uint64_t p2n0_c1:1;
- uint64_t p2n0_n:1;
- uint64_t p2n0_p0:1;
- uint64_t p2n0_p1:1;
- uint64_t p2n1_c0:1;
- uint64_t p2n1_c1:1;
- uint64_t p2n1_n:1;
- uint64_t p2n1_p0:1;
- uint64_t p2n1_p1:1;
- uint64_t csm0:1;
- uint64_t csm1:1;
- uint64_t dif0:1;
- uint64_t dif1:1;
- uint64_t dif2:1;
- uint64_t dif3:1;
- uint64_t dif4:1;
- uint64_t msi:1;
- uint64_t ncb_cmd:1;
- } cn56xx;
+ struct cvmx_npei_bist_status_cn52xx cn56xx;
struct cvmx_npei_bist_status_cn56xxp1 {
uint64_t reserved_58_63:6;
uint64_t pcsr_int:1;
@@ -536,7 +381,16 @@ union cvmx_npei_bist_status {
union cvmx_npei_bist_status2 {
uint64_t u64;
struct cvmx_npei_bist_status2_s {
- uint64_t reserved_5_63:59;
+ uint64_t reserved_14_63:50;
+ uint64_t prd_tag:1;
+ uint64_t prd_st0:1;
+ uint64_t prd_st1:1;
+ uint64_t prd_err:1;
+ uint64_t nrd_st:1;
+ uint64_t nwe_st:1;
+ uint64_t nwe_wr0:1;
+ uint64_t nwe_wr1:1;
+ uint64_t pkt_rd:1;
uint64_t psc_p0:1;
uint64_t psc_p1:1;
uint64_t pkt_gd:1;
@@ -630,8 +484,7 @@ union cvmx_npei_ctl_status {
} cn52xxp1;
struct cvmx_npei_ctl_status_s cn56xx;
struct cvmx_npei_ctl_status_cn56xxp1 {
- uint64_t reserved_16_63:48;
- uint64_t ring_en:1;
+ uint64_t reserved_15_63:49;
uint64_t lnk_rst:1;
uint64_t arb:1;
uint64_t pkt_bp:4;
@@ -756,14 +609,14 @@ union cvmx_npei_dmax_ibuff_saddr {
uint64_t saddr:29;
uint64_t reserved_0_6:7;
} s;
- struct cvmx_npei_dmax_ibuff_saddr_cn52xx {
+ struct cvmx_npei_dmax_ibuff_saddr_s cn52xx;
+ struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 {
uint64_t reserved_36_63:28;
uint64_t saddr:29;
uint64_t reserved_0_6:7;
- } cn52xx;
- struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn52xxp1;
+ } cn52xxp1;
struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
- struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn56xxp1;
+ struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1;
};
union cvmx_npei_dmax_naddr {
@@ -817,7 +670,8 @@ union cvmx_npei_dma_cnts {
union cvmx_npei_dma_control {
uint64_t u64;
struct cvmx_npei_dma_control_s {
- uint64_t reserved_39_63:25;
+ uint64_t reserved_40_63:24;
+ uint64_t p_32b_m:1;
uint64_t dma4_enb:1;
uint64_t dma3_enb:1;
uint64_t dma2_enb:1;
@@ -853,7 +707,161 @@ union cvmx_npei_dma_control {
uint64_t csize:14;
} cn52xxp1;
struct cvmx_npei_dma_control_s cn56xx;
- struct cvmx_npei_dma_control_s cn56xxp1;
+ struct cvmx_npei_dma_control_cn56xxp1 {
+ uint64_t reserved_39_63:25;
+ uint64_t dma4_enb:1;
+ uint64_t dma3_enb:1;
+ uint64_t dma2_enb:1;
+ uint64_t dma1_enb:1;
+ uint64_t dma0_enb:1;
+ uint64_t b0_lend:1;
+ uint64_t dwb_denb:1;
+ uint64_t dwb_ichk:9;
+ uint64_t fpa_que:3;
+ uint64_t o_add1:1;
+ uint64_t o_ro:1;
+ uint64_t o_ns:1;
+ uint64_t o_es:2;
+ uint64_t o_mode:1;
+ uint64_t csize:14;
+ } cn56xxp1;
+};
+
+union cvmx_npei_dma_pcie_req_num {
+ uint64_t u64;
+ struct cvmx_npei_dma_pcie_req_num_s {
+ uint64_t dma_arb:1;
+ uint64_t reserved_53_62:10;
+ uint64_t pkt_cnt:5;
+ uint64_t reserved_45_47:3;
+ uint64_t dma4_cnt:5;
+ uint64_t reserved_37_39:3;
+ uint64_t dma3_cnt:5;
+ uint64_t reserved_29_31:3;
+ uint64_t dma2_cnt:5;
+ uint64_t reserved_21_23:3;
+ uint64_t dma1_cnt:5;
+ uint64_t reserved_13_15:3;
+ uint64_t dma0_cnt:5;
+ uint64_t reserved_5_7:3;
+ uint64_t dma_cnt:5;
+ } s;
+ struct cvmx_npei_dma_pcie_req_num_s cn52xx;
+ struct cvmx_npei_dma_pcie_req_num_s cn56xx;
+};
+
+union cvmx_npei_dma_state1 {
+ uint64_t u64;
+ struct cvmx_npei_dma_state1_s {
+ uint64_t reserved_40_63:24;
+ uint64_t d4_dwe:8;
+ uint64_t d3_dwe:8;
+ uint64_t d2_dwe:8;
+ uint64_t d1_dwe:8;
+ uint64_t d0_dwe:8;
+ } s;
+ struct cvmx_npei_dma_state1_s cn52xx;
+};
+
+union cvmx_npei_dma_state1_p1 {
+ uint64_t u64;
+ struct cvmx_npei_dma_state1_p1_s {
+ uint64_t reserved_60_63:4;
+ uint64_t d0_difst:7;
+ uint64_t d1_difst:7;
+ uint64_t d2_difst:7;
+ uint64_t d3_difst:7;
+ uint64_t d4_difst:7;
+ uint64_t d0_reqst:5;
+ uint64_t d1_reqst:5;
+ uint64_t d2_reqst:5;
+ uint64_t d3_reqst:5;
+ uint64_t d4_reqst:5;
+ } s;
+ struct cvmx_npei_dma_state1_p1_cn52xxp1 {
+ uint64_t reserved_60_63:4;
+ uint64_t d0_difst:7;
+ uint64_t d1_difst:7;
+ uint64_t d2_difst:7;
+ uint64_t d3_difst:7;
+ uint64_t reserved_25_31:7;
+ uint64_t d0_reqst:5;
+ uint64_t d1_reqst:5;
+ uint64_t d2_reqst:5;
+ uint64_t d3_reqst:5;
+ uint64_t reserved_0_4:5;
+ } cn52xxp1;
+ struct cvmx_npei_dma_state1_p1_s cn56xxp1;
+};
+
+union cvmx_npei_dma_state2 {
+ uint64_t u64;
+ struct cvmx_npei_dma_state2_s {
+ uint64_t reserved_28_63:36;
+ uint64_t ndwe:4;
+ uint64_t reserved_21_23:3;
+ uint64_t ndre:5;
+ uint64_t reserved_10_15:6;
+ uint64_t prd:10;
+ } s;
+ struct cvmx_npei_dma_state2_s cn52xx;
+};
+
+union cvmx_npei_dma_state2_p1 {
+ uint64_t u64;
+ struct cvmx_npei_dma_state2_p1_s {
+ uint64_t reserved_45_63:19;
+ uint64_t d0_dffst:9;
+ uint64_t d1_dffst:9;
+ uint64_t d2_dffst:9;
+ uint64_t d3_dffst:9;
+ uint64_t d4_dffst:9;
+ } s;
+ struct cvmx_npei_dma_state2_p1_cn52xxp1 {
+ uint64_t reserved_45_63:19;
+ uint64_t d0_dffst:9;
+ uint64_t d1_dffst:9;
+ uint64_t d2_dffst:9;
+ uint64_t d3_dffst:9;
+ uint64_t reserved_0_8:9;
+ } cn52xxp1;
+ struct cvmx_npei_dma_state2_p1_s cn56xxp1;
+};
+
+union cvmx_npei_dma_state3_p1 {
+ uint64_t u64;
+ struct cvmx_npei_dma_state3_p1_s {
+ uint64_t reserved_60_63:4;
+ uint64_t d0_drest:15;
+ uint64_t d1_drest:15;
+ uint64_t d2_drest:15;
+ uint64_t d3_drest:15;
+ } s;
+ struct cvmx_npei_dma_state3_p1_s cn52xxp1;
+ struct cvmx_npei_dma_state3_p1_s cn56xxp1;
+};
+
+union cvmx_npei_dma_state4_p1 {
+ uint64_t u64;
+ struct cvmx_npei_dma_state4_p1_s {
+ uint64_t reserved_52_63:12;
+ uint64_t d0_dwest:13;
+ uint64_t d1_dwest:13;
+ uint64_t d2_dwest:13;
+ uint64_t d3_dwest:13;
+ } s;
+ struct cvmx_npei_dma_state4_p1_s cn52xxp1;
+ struct cvmx_npei_dma_state4_p1_s cn56xxp1;
+};
+
+union cvmx_npei_dma_state5_p1 {
+ uint64_t u64;
+ struct cvmx_npei_dma_state5_p1_s {
+ uint64_t reserved_28_63:36;
+ uint64_t d4_drest:15;
+ uint64_t d4_dwest:13;
+ } s;
+ struct cvmx_npei_dma_state5_p1_s cn56xxp1;
};
union cvmx_npei_int_a_enb {
@@ -871,17 +879,7 @@ union cvmx_npei_int_a_enb {
uint64_t dma1_cpl:1;
uint64_t dma0_cpl:1;
} s;
- struct cvmx_npei_int_a_enb_cn52xx {
- uint64_t reserved_8_63:56;
- uint64_t p1_rdlk:1;
- uint64_t p0_rdlk:1;
- uint64_t pgl_err:1;
- uint64_t pdi_err:1;
- uint64_t pop_err:1;
- uint64_t pins_err:1;
- uint64_t dma1_cpl:1;
- uint64_t dma0_cpl:1;
- } cn52xx;
+ struct cvmx_npei_int_a_enb_s cn52xx;
struct cvmx_npei_int_a_enb_cn52xxp1 {
uint64_t reserved_2_63:62;
uint64_t dma1_cpl:1;
@@ -905,16 +903,7 @@ union cvmx_npei_int_a_enb2 {
uint64_t dma1_cpl:1;
uint64_t dma0_cpl:1;
} s;
- struct cvmx_npei_int_a_enb2_cn52xx {
- uint64_t reserved_8_63:56;
- uint64_t p1_rdlk:1;
- uint64_t p0_rdlk:1;
- uint64_t pgl_err:1;
- uint64_t pdi_err:1;
- uint64_t pop_err:1;
- uint64_t pins_err:1;
- uint64_t reserved_0_1:2;
- } cn52xx;
+ struct cvmx_npei_int_a_enb2_s cn52xx;
struct cvmx_npei_int_a_enb2_cn52xxp1 {
uint64_t reserved_2_63:62;
uint64_t dma1_cpl:1;
@@ -938,17 +927,7 @@ union cvmx_npei_int_a_sum {
uint64_t dma1_cpl:1;
uint64_t dma0_cpl:1;
} s;
- struct cvmx_npei_int_a_sum_cn52xx {
- uint64_t reserved_8_63:56;
- uint64_t p1_rdlk:1;
- uint64_t p0_rdlk:1;
- uint64_t pgl_err:1;
- uint64_t pdi_err:1;
- uint64_t pop_err:1;
- uint64_t pins_err:1;
- uint64_t dma1_cpl:1;
- uint64_t dma0_cpl:1;
- } cn52xx;
+ struct cvmx_npei_int_a_sum_s cn52xx;
struct cvmx_npei_int_a_sum_cn52xxp1 {
uint64_t reserved_2_63:62;
uint64_t dma1_cpl:1;
@@ -1550,10 +1529,7 @@ union cvmx_npei_int_sum {
uint64_t c0_se:1;
uint64_t reserved_20_20:1;
uint64_t c0_aeri:1;
- uint64_t ptime:1;
- uint64_t pcnt:1;
- uint64_t pidbof:1;
- uint64_t psldbof:1;
+ uint64_t reserved_15_18:4;
uint64_t dtime1:1;
uint64_t dtime0:1;
uint64_t dcnt1:1;
@@ -1959,7 +1935,6 @@ union cvmx_npei_pktx_cnts {
} s;
struct cvmx_npei_pktx_cnts_s cn52xx;
struct cvmx_npei_pktx_cnts_s cn56xx;
- struct cvmx_npei_pktx_cnts_s cn56xxp1;
};
union cvmx_npei_pktx_in_bp {
@@ -1970,7 +1945,6 @@ union cvmx_npei_pktx_in_bp {
} s;
struct cvmx_npei_pktx_in_bp_s cn52xx;
struct cvmx_npei_pktx_in_bp_s cn56xx;
- struct cvmx_npei_pktx_in_bp_s cn56xxp1;
};
union cvmx_npei_pktx_instr_baddr {
@@ -1981,7 +1955,6 @@ union cvmx_npei_pktx_instr_baddr {
} s;
struct cvmx_npei_pktx_instr_baddr_s cn52xx;
struct cvmx_npei_pktx_instr_baddr_s cn56xx;
- struct cvmx_npei_pktx_instr_baddr_s cn56xxp1;
};
union cvmx_npei_pktx_instr_baoff_dbell {
@@ -1992,7 +1965,6 @@ union cvmx_npei_pktx_instr_baoff_dbell {
} s;
struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
- struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xxp1;
};
union cvmx_npei_pktx_instr_fifo_rsize {
@@ -2006,7 +1978,6 @@ union cvmx_npei_pktx_instr_fifo_rsize {
} s;
struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
- struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xxp1;
};
union cvmx_npei_pktx_instr_header {
@@ -2014,21 +1985,20 @@ union cvmx_npei_pktx_instr_header {
struct cvmx_npei_pktx_instr_header_s {
uint64_t reserved_44_63:20;
uint64_t pbp:1;
- uint64_t rsv_f:5;
+ uint64_t reserved_38_42:5;
uint64_t rparmode:2;
- uint64_t rsv_e:1;
+ uint64_t reserved_35_35:1;
uint64_t rskp_len:7;
- uint64_t rsv_d:6;
+ uint64_t reserved_22_27:6;
uint64_t use_ihdr:1;
- uint64_t rsv_c:5;
+ uint64_t reserved_16_20:5;
uint64_t par_mode:2;
- uint64_t rsv_b:1;
+ uint64_t reserved_13_13:1;
uint64_t skp_len:7;
- uint64_t rsv_a:6;
+ uint64_t reserved_0_5:6;
} s;
struct cvmx_npei_pktx_instr_header_s cn52xx;
struct cvmx_npei_pktx_instr_header_s cn56xx;
- struct cvmx_npei_pktx_instr_header_s cn56xxp1;
};
union cvmx_npei_pktx_slist_baddr {
@@ -2039,7 +2009,6 @@ union cvmx_npei_pktx_slist_baddr {
} s;
struct cvmx_npei_pktx_slist_baddr_s cn52xx;
struct cvmx_npei_pktx_slist_baddr_s cn56xx;
- struct cvmx_npei_pktx_slist_baddr_s cn56xxp1;
};
union cvmx_npei_pktx_slist_baoff_dbell {
@@ -2050,7 +2019,6 @@ union cvmx_npei_pktx_slist_baoff_dbell {
} s;
struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
- struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xxp1;
};
union cvmx_npei_pktx_slist_fifo_rsize {
@@ -2061,7 +2029,6 @@ union cvmx_npei_pktx_slist_fifo_rsize {
} s;
struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
- struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xxp1;
};
union cvmx_npei_pkt_cnt_int {
@@ -2072,7 +2039,6 @@ union cvmx_npei_pkt_cnt_int {
} s;
struct cvmx_npei_pkt_cnt_int_s cn52xx;
struct cvmx_npei_pkt_cnt_int_s cn56xx;
- struct cvmx_npei_pkt_cnt_int_s cn56xxp1;
};
union cvmx_npei_pkt_cnt_int_enb {
@@ -2083,7 +2049,6 @@ union cvmx_npei_pkt_cnt_int_enb {
} s;
struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
- struct cvmx_npei_pkt_cnt_int_enb_s cn56xxp1;
};
union cvmx_npei_pkt_data_out_es {
@@ -2093,7 +2058,6 @@ union cvmx_npei_pkt_data_out_es {
} s;
struct cvmx_npei_pkt_data_out_es_s cn52xx;
struct cvmx_npei_pkt_data_out_es_s cn56xx;
- struct cvmx_npei_pkt_data_out_es_s cn56xxp1;
};
union cvmx_npei_pkt_data_out_ns {
@@ -2104,7 +2068,6 @@ union cvmx_npei_pkt_data_out_ns {
} s;
struct cvmx_npei_pkt_data_out_ns_s cn52xx;
struct cvmx_npei_pkt_data_out_ns_s cn56xx;
- struct cvmx_npei_pkt_data_out_ns_s cn56xxp1;
};
union cvmx_npei_pkt_data_out_ror {
@@ -2115,7 +2078,6 @@ union cvmx_npei_pkt_data_out_ror {
} s;
struct cvmx_npei_pkt_data_out_ror_s cn52xx;
struct cvmx_npei_pkt_data_out_ror_s cn56xx;
- struct cvmx_npei_pkt_data_out_ror_s cn56xxp1;
};
union cvmx_npei_pkt_dpaddr {
@@ -2126,7 +2088,6 @@ union cvmx_npei_pkt_dpaddr {
} s;
struct cvmx_npei_pkt_dpaddr_s cn52xx;
struct cvmx_npei_pkt_dpaddr_s cn56xx;
- struct cvmx_npei_pkt_dpaddr_s cn56xxp1;
};
union cvmx_npei_pkt_in_bp {
@@ -2135,6 +2096,7 @@ union cvmx_npei_pkt_in_bp {
uint64_t reserved_32_63:32;
uint64_t bp:32;
} s;
+ struct cvmx_npei_pkt_in_bp_s cn52xx;
struct cvmx_npei_pkt_in_bp_s cn56xx;
};
@@ -2146,7 +2108,6 @@ union cvmx_npei_pkt_in_donex_cnts {
} s;
struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
- struct cvmx_npei_pkt_in_donex_cnts_s cn56xxp1;
};
union cvmx_npei_pkt_in_instr_counts {
@@ -2184,7 +2145,6 @@ union cvmx_npei_pkt_input_control {
} s;
struct cvmx_npei_pkt_input_control_s cn52xx;
struct cvmx_npei_pkt_input_control_s cn56xx;
- struct cvmx_npei_pkt_input_control_s cn56xxp1;
};
union cvmx_npei_pkt_instr_enb {
@@ -2195,7 +2155,6 @@ union cvmx_npei_pkt_instr_enb {
} s;
struct cvmx_npei_pkt_instr_enb_s cn52xx;
struct cvmx_npei_pkt_instr_enb_s cn56xx;
- struct cvmx_npei_pkt_instr_enb_s cn56xxp1;
};
union cvmx_npei_pkt_instr_rd_size {
@@ -2215,7 +2174,6 @@ union cvmx_npei_pkt_instr_size {
} s;
struct cvmx_npei_pkt_instr_size_s cn52xx;
struct cvmx_npei_pkt_instr_size_s cn56xx;
- struct cvmx_npei_pkt_instr_size_s cn56xxp1;
};
union cvmx_npei_pkt_int_levels {
@@ -2227,7 +2185,6 @@ union cvmx_npei_pkt_int_levels {
} s;
struct cvmx_npei_pkt_int_levels_s cn52xx;
struct cvmx_npei_pkt_int_levels_s cn56xx;
- struct cvmx_npei_pkt_int_levels_s cn56xxp1;
};
union cvmx_npei_pkt_iptr {
@@ -2238,7 +2195,6 @@ union cvmx_npei_pkt_iptr {
} s;
struct cvmx_npei_pkt_iptr_s cn52xx;
struct cvmx_npei_pkt_iptr_s cn56xx;
- struct cvmx_npei_pkt_iptr_s cn56xxp1;
};
union cvmx_npei_pkt_out_bmode {
@@ -2249,7 +2205,6 @@ union cvmx_npei_pkt_out_bmode {
} s;
struct cvmx_npei_pkt_out_bmode_s cn52xx;
struct cvmx_npei_pkt_out_bmode_s cn56xx;
- struct cvmx_npei_pkt_out_bmode_s cn56xxp1;
};
union cvmx_npei_pkt_out_enb {
@@ -2260,7 +2215,6 @@ union cvmx_npei_pkt_out_enb {
} s;
struct cvmx_npei_pkt_out_enb_s cn52xx;
struct cvmx_npei_pkt_out_enb_s cn56xx;
- struct cvmx_npei_pkt_out_enb_s cn56xxp1;
};
union cvmx_npei_pkt_output_wmark {
@@ -2280,7 +2234,6 @@ union cvmx_npei_pkt_pcie_port {
} s;
struct cvmx_npei_pkt_pcie_port_s cn52xx;
struct cvmx_npei_pkt_pcie_port_s cn56xx;
- struct cvmx_npei_pkt_pcie_port_s cn56xxp1;
};
union cvmx_npei_pkt_port_in_rst {
@@ -2300,7 +2253,6 @@ union cvmx_npei_pkt_slist_es {
} s;
struct cvmx_npei_pkt_slist_es_s cn52xx;
struct cvmx_npei_pkt_slist_es_s cn56xx;
- struct cvmx_npei_pkt_slist_es_s cn56xxp1;
};
union cvmx_npei_pkt_slist_id_size {
@@ -2312,7 +2264,6 @@ union cvmx_npei_pkt_slist_id_size {
} s;
struct cvmx_npei_pkt_slist_id_size_s cn52xx;
struct cvmx_npei_pkt_slist_id_size_s cn56xx;
- struct cvmx_npei_pkt_slist_id_size_s cn56xxp1;
};
union cvmx_npei_pkt_slist_ns {
@@ -2323,7 +2274,6 @@ union cvmx_npei_pkt_slist_ns {
} s;
struct cvmx_npei_pkt_slist_ns_s cn52xx;
struct cvmx_npei_pkt_slist_ns_s cn56xx;
- struct cvmx_npei_pkt_slist_ns_s cn56xxp1;
};
union cvmx_npei_pkt_slist_ror {
@@ -2334,7 +2284,6 @@ union cvmx_npei_pkt_slist_ror {
} s;
struct cvmx_npei_pkt_slist_ror_s cn52xx;
struct cvmx_npei_pkt_slist_ror_s cn56xx;
- struct cvmx_npei_pkt_slist_ror_s cn56xxp1;
};
union cvmx_npei_pkt_time_int {
@@ -2345,7 +2294,6 @@ union cvmx_npei_pkt_time_int {
} s;
struct cvmx_npei_pkt_time_int_s cn52xx;
struct cvmx_npei_pkt_time_int_s cn56xx;
- struct cvmx_npei_pkt_time_int_s cn56xxp1;
};
union cvmx_npei_pkt_time_int_enb {
@@ -2356,7 +2304,6 @@ union cvmx_npei_pkt_time_int_enb {
} s;
struct cvmx_npei_pkt_time_int_enb_s cn52xx;
struct cvmx_npei_pkt_time_int_enb_s cn56xx;
- struct cvmx_npei_pkt_time_int_enb_s cn56xxp1;
};
union cvmx_npei_rsl_int_blocks {
@@ -2371,7 +2318,8 @@ union cvmx_npei_rsl_int_blocks {
uint64_t asxpcs0:1;
uint64_t reserved_21_21:1;
uint64_t pip:1;
- uint64_t reserved_18_19:2;
+ uint64_t spx1:1;
+ uint64_t spx0:1;
uint64_t lmc0:1;
uint64_t l2c:1;
uint64_t usb1:1;
@@ -2383,7 +2331,7 @@ union cvmx_npei_rsl_int_blocks {
uint64_t ipd:1;
uint64_t reserved_8_8:1;
uint64_t zip:1;
- uint64_t reserved_6_6:1;
+ uint64_t dfa:1;
uint64_t fpa:1;
uint64_t key:1;
uint64_t npei:1;
@@ -2393,37 +2341,8 @@ union cvmx_npei_rsl_int_blocks {
} s;
struct cvmx_npei_rsl_int_blocks_s cn52xx;
struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
- struct cvmx_npei_rsl_int_blocks_cn56xx {
- uint64_t reserved_31_63:33;
- uint64_t iob:1;
- uint64_t lmc1:1;
- uint64_t agl:1;
- uint64_t reserved_24_27:4;
- uint64_t asxpcs1:1;
- uint64_t asxpcs0:1;
- uint64_t reserved_21_21:1;
- uint64_t pip:1;
- uint64_t reserved_18_19:2;
- uint64_t lmc0:1;
- uint64_t l2c:1;
- uint64_t reserved_15_15:1;
- uint64_t rad:1;
- uint64_t usb:1;
- uint64_t pow:1;
- uint64_t tim:1;
- uint64_t pko:1;
- uint64_t ipd:1;
- uint64_t reserved_8_8:1;
- uint64_t zip:1;
- uint64_t reserved_6_6:1;
- uint64_t fpa:1;
- uint64_t key:1;
- uint64_t npei:1;
- uint64_t gmx1:1;
- uint64_t gmx0:1;
- uint64_t mio:1;
- } cn56xx;
- struct cvmx_npei_rsl_int_blocks_cn56xx cn56xxp1;
+ struct cvmx_npei_rsl_int_blocks_s cn56xx;
+ struct cvmx_npei_rsl_int_blocks_s cn56xxp1;
};
union cvmx_npei_scratch_1 {
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-npi-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-npi-defs.h
index 4e03cd8561e3..f089c780060f 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-npi-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-npi-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,246 +28,126 @@
#ifndef __CVMX_NPI_DEFS_H__
#define __CVMX_NPI_DEFS_H__
-#define CVMX_NPI_BASE_ADDR_INPUT0 \
- CVMX_ADD_IO_SEG(0x00011F0000000070ull)
-#define CVMX_NPI_BASE_ADDR_INPUT1 \
- CVMX_ADD_IO_SEG(0x00011F0000000080ull)
-#define CVMX_NPI_BASE_ADDR_INPUT2 \
- CVMX_ADD_IO_SEG(0x00011F0000000090ull)
-#define CVMX_NPI_BASE_ADDR_INPUT3 \
- CVMX_ADD_IO_SEG(0x00011F00000000A0ull)
-#define CVMX_NPI_BASE_ADDR_INPUTX(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000000070ull + (((offset) & 3) * 16))
-#define CVMX_NPI_BASE_ADDR_OUTPUT0 \
- CVMX_ADD_IO_SEG(0x00011F00000000B8ull)
-#define CVMX_NPI_BASE_ADDR_OUTPUT1 \
- CVMX_ADD_IO_SEG(0x00011F00000000C0ull)
-#define CVMX_NPI_BASE_ADDR_OUTPUT2 \
- CVMX_ADD_IO_SEG(0x00011F00000000C8ull)
-#define CVMX_NPI_BASE_ADDR_OUTPUT3 \
- CVMX_ADD_IO_SEG(0x00011F00000000D0ull)
-#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) \
- CVMX_ADD_IO_SEG(0x00011F00000000B8ull + (((offset) & 3) * 8))
-#define CVMX_NPI_BIST_STATUS \
- CVMX_ADD_IO_SEG(0x00011F00000003F8ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT0 \
- CVMX_ADD_IO_SEG(0x00011F00000000E0ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT1 \
- CVMX_ADD_IO_SEG(0x00011F00000000E8ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT2 \
- CVMX_ADD_IO_SEG(0x00011F00000000F0ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT3 \
- CVMX_ADD_IO_SEG(0x00011F00000000F8ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) \
- CVMX_ADD_IO_SEG(0x00011F00000000E0ull + (((offset) & 3) * 8))
-#define CVMX_NPI_COMP_CTL \
- CVMX_ADD_IO_SEG(0x00011F0000000218ull)
-#define CVMX_NPI_CTL_STATUS \
- CVMX_ADD_IO_SEG(0x00011F0000000010ull)
-#define CVMX_NPI_DBG_SELECT \
- CVMX_ADD_IO_SEG(0x00011F0000000008ull)
-#define CVMX_NPI_DMA_CONTROL \
- CVMX_ADD_IO_SEG(0x00011F0000000128ull)
-#define CVMX_NPI_DMA_HIGHP_COUNTS \
- CVMX_ADD_IO_SEG(0x00011F0000000148ull)
-#define CVMX_NPI_DMA_HIGHP_NADDR \
- CVMX_ADD_IO_SEG(0x00011F0000000158ull)
-#define CVMX_NPI_DMA_LOWP_COUNTS \
- CVMX_ADD_IO_SEG(0x00011F0000000140ull)
-#define CVMX_NPI_DMA_LOWP_NADDR \
- CVMX_ADD_IO_SEG(0x00011F0000000150ull)
-#define CVMX_NPI_HIGHP_DBELL \
- CVMX_ADD_IO_SEG(0x00011F0000000120ull)
-#define CVMX_NPI_HIGHP_IBUFF_SADDR \
- CVMX_ADD_IO_SEG(0x00011F0000000110ull)
-#define CVMX_NPI_INPUT_CONTROL \
- CVMX_ADD_IO_SEG(0x00011F0000000138ull)
-#define CVMX_NPI_INT_ENB \
- CVMX_ADD_IO_SEG(0x00011F0000000020ull)
-#define CVMX_NPI_INT_SUM \
- CVMX_ADD_IO_SEG(0x00011F0000000018ull)
-#define CVMX_NPI_LOWP_DBELL \
- CVMX_ADD_IO_SEG(0x00011F0000000118ull)
-#define CVMX_NPI_LOWP_IBUFF_SADDR \
- CVMX_ADD_IO_SEG(0x00011F0000000108ull)
-#define CVMX_NPI_MEM_ACCESS_SUBID3 \
- CVMX_ADD_IO_SEG(0x00011F0000000028ull)
-#define CVMX_NPI_MEM_ACCESS_SUBID4 \
- CVMX_ADD_IO_SEG(0x00011F0000000030ull)
-#define CVMX_NPI_MEM_ACCESS_SUBID5 \
- CVMX_ADD_IO_SEG(0x00011F0000000038ull)
-#define CVMX_NPI_MEM_ACCESS_SUBID6 \
- CVMX_ADD_IO_SEG(0x00011F0000000040ull)
-#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000000028ull + (((offset) & 7) * 8) - 8 * 3)
-#define CVMX_NPI_MSI_RCV \
- (0x0000000000000190ull)
-#define CVMX_NPI_NPI_MSI_RCV \
- CVMX_ADD_IO_SEG(0x00011F0000001190ull)
-#define CVMX_NPI_NUM_DESC_OUTPUT0 \
- CVMX_ADD_IO_SEG(0x00011F0000000050ull)
-#define CVMX_NPI_NUM_DESC_OUTPUT1 \
- CVMX_ADD_IO_SEG(0x00011F0000000058ull)
-#define CVMX_NPI_NUM_DESC_OUTPUT2 \
- CVMX_ADD_IO_SEG(0x00011F0000000060ull)
-#define CVMX_NPI_NUM_DESC_OUTPUT3 \
- CVMX_ADD_IO_SEG(0x00011F0000000068ull)
-#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000000050ull + (((offset) & 3) * 8))
-#define CVMX_NPI_OUTPUT_CONTROL \
- CVMX_ADD_IO_SEG(0x00011F0000000100ull)
-#define CVMX_NPI_P0_DBPAIR_ADDR \
- CVMX_ADD_IO_SEG(0x00011F0000000180ull)
-#define CVMX_NPI_P0_INSTR_ADDR \
- CVMX_ADD_IO_SEG(0x00011F00000001C0ull)
-#define CVMX_NPI_P0_INSTR_CNTS \
- CVMX_ADD_IO_SEG(0x00011F00000001A0ull)
-#define CVMX_NPI_P0_PAIR_CNTS \
- CVMX_ADD_IO_SEG(0x00011F0000000160ull)
-#define CVMX_NPI_P1_DBPAIR_ADDR \
- CVMX_ADD_IO_SEG(0x00011F0000000188ull)
-#define CVMX_NPI_P1_INSTR_ADDR \
- CVMX_ADD_IO_SEG(0x00011F00000001C8ull)
-#define CVMX_NPI_P1_INSTR_CNTS \
- CVMX_ADD_IO_SEG(0x00011F00000001A8ull)
-#define CVMX_NPI_P1_PAIR_CNTS \
- CVMX_ADD_IO_SEG(0x00011F0000000168ull)
-#define CVMX_NPI_P2_DBPAIR_ADDR \
- CVMX_ADD_IO_SEG(0x00011F0000000190ull)
-#define CVMX_NPI_P2_INSTR_ADDR \
- CVMX_ADD_IO_SEG(0x00011F00000001D0ull)
-#define CVMX_NPI_P2_INSTR_CNTS \
- CVMX_ADD_IO_SEG(0x00011F00000001B0ull)
-#define CVMX_NPI_P2_PAIR_CNTS \
- CVMX_ADD_IO_SEG(0x00011F0000000170ull)
-#define CVMX_NPI_P3_DBPAIR_ADDR \
- CVMX_ADD_IO_SEG(0x00011F0000000198ull)
-#define CVMX_NPI_P3_INSTR_ADDR \
- CVMX_ADD_IO_SEG(0x00011F00000001D8ull)
-#define CVMX_NPI_P3_INSTR_CNTS \
- CVMX_ADD_IO_SEG(0x00011F00000001B8ull)
-#define CVMX_NPI_P3_PAIR_CNTS \
- CVMX_ADD_IO_SEG(0x00011F0000000178ull)
-#define CVMX_NPI_PCI_BAR1_INDEXX(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000001100ull + (((offset) & 31) * 4))
-#define CVMX_NPI_PCI_BIST_REG \
- CVMX_ADD_IO_SEG(0x00011F00000011C0ull)
-#define CVMX_NPI_PCI_BURST_SIZE \
- CVMX_ADD_IO_SEG(0x00011F00000000D8ull)
-#define CVMX_NPI_PCI_CFG00 \
- CVMX_ADD_IO_SEG(0x00011F0000001800ull)
-#define CVMX_NPI_PCI_CFG01 \
- CVMX_ADD_IO_SEG(0x00011F0000001804ull)
-#define CVMX_NPI_PCI_CFG02 \
- CVMX_ADD_IO_SEG(0x00011F0000001808ull)
-#define CVMX_NPI_PCI_CFG03 \
- CVMX_ADD_IO_SEG(0x00011F000000180Cull)
-#define CVMX_NPI_PCI_CFG04 \
- CVMX_ADD_IO_SEG(0x00011F0000001810ull)
-#define CVMX_NPI_PCI_CFG05 \
- CVMX_ADD_IO_SEG(0x00011F0000001814ull)
-#define CVMX_NPI_PCI_CFG06 \
- CVMX_ADD_IO_SEG(0x00011F0000001818ull)
-#define CVMX_NPI_PCI_CFG07 \
- CVMX_ADD_IO_SEG(0x00011F000000181Cull)
-#define CVMX_NPI_PCI_CFG08 \
- CVMX_ADD_IO_SEG(0x00011F0000001820ull)
-#define CVMX_NPI_PCI_CFG09 \
- CVMX_ADD_IO_SEG(0x00011F0000001824ull)
-#define CVMX_NPI_PCI_CFG10 \
- CVMX_ADD_IO_SEG(0x00011F0000001828ull)
-#define CVMX_NPI_PCI_CFG11 \
- CVMX_ADD_IO_SEG(0x00011F000000182Cull)
-#define CVMX_NPI_PCI_CFG12 \
- CVMX_ADD_IO_SEG(0x00011F0000001830ull)
-#define CVMX_NPI_PCI_CFG13 \
- CVMX_ADD_IO_SEG(0x00011F0000001834ull)
-#define CVMX_NPI_PCI_CFG15 \
- CVMX_ADD_IO_SEG(0x00011F000000183Cull)
-#define CVMX_NPI_PCI_CFG16 \
- CVMX_ADD_IO_SEG(0x00011F0000001840ull)
-#define CVMX_NPI_PCI_CFG17 \
- CVMX_ADD_IO_SEG(0x00011F0000001844ull)
-#define CVMX_NPI_PCI_CFG18 \
- CVMX_ADD_IO_SEG(0x00011F0000001848ull)
-#define CVMX_NPI_PCI_CFG19 \
- CVMX_ADD_IO_SEG(0x00011F000000184Cull)
-#define CVMX_NPI_PCI_CFG20 \
- CVMX_ADD_IO_SEG(0x00011F0000001850ull)
-#define CVMX_NPI_PCI_CFG21 \
- CVMX_ADD_IO_SEG(0x00011F0000001854ull)
-#define CVMX_NPI_PCI_CFG22 \
- CVMX_ADD_IO_SEG(0x00011F0000001858ull)
-#define CVMX_NPI_PCI_CFG56 \
- CVMX_ADD_IO_SEG(0x00011F00000018E0ull)
-#define CVMX_NPI_PCI_CFG57 \
- CVMX_ADD_IO_SEG(0x00011F00000018E4ull)
-#define CVMX_NPI_PCI_CFG58 \
- CVMX_ADD_IO_SEG(0x00011F00000018E8ull)
-#define CVMX_NPI_PCI_CFG59 \
- CVMX_ADD_IO_SEG(0x00011F00000018ECull)
-#define CVMX_NPI_PCI_CFG60 \
- CVMX_ADD_IO_SEG(0x00011F00000018F0ull)
-#define CVMX_NPI_PCI_CFG61 \
- CVMX_ADD_IO_SEG(0x00011F00000018F4ull)
-#define CVMX_NPI_PCI_CFG62 \
- CVMX_ADD_IO_SEG(0x00011F00000018F8ull)
-#define CVMX_NPI_PCI_CFG63 \
- CVMX_ADD_IO_SEG(0x00011F00000018FCull)
-#define CVMX_NPI_PCI_CNT_REG \
- CVMX_ADD_IO_SEG(0x00011F00000011B8ull)
-#define CVMX_NPI_PCI_CTL_STATUS_2 \
- CVMX_ADD_IO_SEG(0x00011F000000118Cull)
-#define CVMX_NPI_PCI_INT_ARB_CFG \
- CVMX_ADD_IO_SEG(0x00011F0000000130ull)
-#define CVMX_NPI_PCI_INT_ENB2 \
- CVMX_ADD_IO_SEG(0x00011F00000011A0ull)
-#define CVMX_NPI_PCI_INT_SUM2 \
- CVMX_ADD_IO_SEG(0x00011F0000001198ull)
-#define CVMX_NPI_PCI_READ_CMD \
- CVMX_ADD_IO_SEG(0x00011F0000000048ull)
-#define CVMX_NPI_PCI_READ_CMD_6 \
- CVMX_ADD_IO_SEG(0x00011F0000001180ull)
-#define CVMX_NPI_PCI_READ_CMD_C \
- CVMX_ADD_IO_SEG(0x00011F0000001184ull)
-#define CVMX_NPI_PCI_READ_CMD_E \
- CVMX_ADD_IO_SEG(0x00011F0000001188ull)
-#define CVMX_NPI_PCI_SCM_REG \
- CVMX_ADD_IO_SEG(0x00011F00000011A8ull)
-#define CVMX_NPI_PCI_TSR_REG \
- CVMX_ADD_IO_SEG(0x00011F00000011B0ull)
-#define CVMX_NPI_PORT32_INSTR_HDR \
- CVMX_ADD_IO_SEG(0x00011F00000001F8ull)
-#define CVMX_NPI_PORT33_INSTR_HDR \
- CVMX_ADD_IO_SEG(0x00011F0000000200ull)
-#define CVMX_NPI_PORT34_INSTR_HDR \
- CVMX_ADD_IO_SEG(0x00011F0000000208ull)
-#define CVMX_NPI_PORT35_INSTR_HDR \
- CVMX_ADD_IO_SEG(0x00011F0000000210ull)
-#define CVMX_NPI_PORT_BP_CONTROL \
- CVMX_ADD_IO_SEG(0x00011F00000001F0ull)
-#define CVMX_NPI_PX_DBPAIR_ADDR(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000000180ull + (((offset) & 3) * 8))
-#define CVMX_NPI_PX_INSTR_ADDR(offset) \
- CVMX_ADD_IO_SEG(0x00011F00000001C0ull + (((offset) & 3) * 8))
-#define CVMX_NPI_PX_INSTR_CNTS(offset) \
- CVMX_ADD_IO_SEG(0x00011F00000001A0ull + (((offset) & 3) * 8))
-#define CVMX_NPI_PX_PAIR_CNTS(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000000160ull + (((offset) & 3) * 8))
-#define CVMX_NPI_RSL_INT_BLOCKS \
- CVMX_ADD_IO_SEG(0x00011F0000000000ull)
-#define CVMX_NPI_SIZE_INPUT0 \
- CVMX_ADD_IO_SEG(0x00011F0000000078ull)
-#define CVMX_NPI_SIZE_INPUT1 \
- CVMX_ADD_IO_SEG(0x00011F0000000088ull)
-#define CVMX_NPI_SIZE_INPUT2 \
- CVMX_ADD_IO_SEG(0x00011F0000000098ull)
-#define CVMX_NPI_SIZE_INPUT3 \
- CVMX_ADD_IO_SEG(0x00011F00000000A8ull)
-#define CVMX_NPI_SIZE_INPUTX(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000000078ull + (((offset) & 3) * 16))
-#define CVMX_NPI_WIN_READ_TO \
- CVMX_ADD_IO_SEG(0x00011F00000001E0ull)
+#define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
+#define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
+#define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
+#define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
+#define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16)
+#define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
+#define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
+#define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
+#define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
+#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull))
+#define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
+#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull))
+#define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull))
+#define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull))
+#define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull))
+#define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull))
+#define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull))
+#define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull))
+#define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull))
+#define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull))
+#define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull))
+#define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull))
+#define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull))
+#define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull))
+#define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull))
+#define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull))
+#define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
+#define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
+#define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
+#define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
+#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3)
+#define CVMX_NPI_MSI_RCV (0x0000000000000190ull)
+#define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull))
+#define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
+#define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
+#define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
+#define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
+#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull))
+#define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
+#define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
+#define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
+#define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
+#define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
+#define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
+#define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
+#define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
+#define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
+#define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
+#define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
+#define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
+#define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
+#define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
+#define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
+#define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
+#define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4)
+#define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull))
+#define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull))
+#define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull))
+#define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull))
+#define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull))
+#define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull))
+#define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull))
+#define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull))
+#define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull))
+#define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull))
+#define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull))
+#define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull))
+#define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull))
+#define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull))
+#define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull))
+#define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull))
+#define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull))
+#define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull))
+#define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull))
+#define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull))
+#define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull))
+#define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull))
+#define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull))
+#define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull))
+#define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull))
+#define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull))
+#define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull))
+#define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull))
+#define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull))
+#define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull))
+#define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull))
+#define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull))
+#define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull))
+#define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull))
+#define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull))
+#define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull))
+#define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull))
+#define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull))
+#define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull))
+#define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull))
+#define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull))
+#define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull))
+#define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull))
+#define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull))
+#define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull))
+#define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull))
+#define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull))
+#define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull))
+#define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull))
+#define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
+#define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
+#define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
+#define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
+#define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16)
+#define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull))
union cvmx_npi_base_addr_inputx {
uint64_t u64;
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-pci-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-pci-defs.h
index 90f8d6535753..6ff6d9d357ba 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-pci-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-pci-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,184 +28,91 @@
#ifndef __CVMX_PCI_DEFS_H__
#define __CVMX_PCI_DEFS_H__
-#define CVMX_PCI_BAR1_INDEXX(offset) \
- (0x0000000000000100ull + (((offset) & 31) * 4))
-#define CVMX_PCI_BIST_REG \
- (0x00000000000001C0ull)
-#define CVMX_PCI_CFG00 \
- (0x0000000000000000ull)
-#define CVMX_PCI_CFG01 \
- (0x0000000000000004ull)
-#define CVMX_PCI_CFG02 \
- (0x0000000000000008ull)
-#define CVMX_PCI_CFG03 \
- (0x000000000000000Cull)
-#define CVMX_PCI_CFG04 \
- (0x0000000000000010ull)
-#define CVMX_PCI_CFG05 \
- (0x0000000000000014ull)
-#define CVMX_PCI_CFG06 \
- (0x0000000000000018ull)
-#define CVMX_PCI_CFG07 \
- (0x000000000000001Cull)
-#define CVMX_PCI_CFG08 \
- (0x0000000000000020ull)
-#define CVMX_PCI_CFG09 \
- (0x0000000000000024ull)
-#define CVMX_PCI_CFG10 \
- (0x0000000000000028ull)
-#define CVMX_PCI_CFG11 \
- (0x000000000000002Cull)
-#define CVMX_PCI_CFG12 \
- (0x0000000000000030ull)
-#define CVMX_PCI_CFG13 \
- (0x0000000000000034ull)
-#define CVMX_PCI_CFG15 \
- (0x000000000000003Cull)
-#define CVMX_PCI_CFG16 \
- (0x0000000000000040ull)
-#define CVMX_PCI_CFG17 \
- (0x0000000000000044ull)
-#define CVMX_PCI_CFG18 \
- (0x0000000000000048ull)
-#define CVMX_PCI_CFG19 \
- (0x000000000000004Cull)
-#define CVMX_PCI_CFG20 \
- (0x0000000000000050ull)
-#define CVMX_PCI_CFG21 \
- (0x0000000000000054ull)
-#define CVMX_PCI_CFG22 \
- (0x0000000000000058ull)
-#define CVMX_PCI_CFG56 \
- (0x00000000000000E0ull)
-#define CVMX_PCI_CFG57 \
- (0x00000000000000E4ull)
-#define CVMX_PCI_CFG58 \
- (0x00000000000000E8ull)
-#define CVMX_PCI_CFG59 \
- (0x00000000000000ECull)
-#define CVMX_PCI_CFG60 \
- (0x00000000000000F0ull)
-#define CVMX_PCI_CFG61 \
- (0x00000000000000F4ull)
-#define CVMX_PCI_CFG62 \
- (0x00000000000000F8ull)
-#define CVMX_PCI_CFG63 \
- (0x00000000000000FCull)
-#define CVMX_PCI_CNT_REG \
- (0x00000000000001B8ull)
-#define CVMX_PCI_CTL_STATUS_2 \
- (0x000000000000018Cull)
-#define CVMX_PCI_DBELL_0 \
- (0x0000000000000080ull)
-#define CVMX_PCI_DBELL_1 \
- (0x0000000000000088ull)
-#define CVMX_PCI_DBELL_2 \
- (0x0000000000000090ull)
-#define CVMX_PCI_DBELL_3 \
- (0x0000000000000098ull)
-#define CVMX_PCI_DBELL_X(offset) \
- (0x0000000000000080ull + (((offset) & 3) * 8))
-#define CVMX_PCI_DMA_CNT0 \
- (0x00000000000000A0ull)
-#define CVMX_PCI_DMA_CNT1 \
- (0x00000000000000A8ull)
-#define CVMX_PCI_DMA_CNTX(offset) \
- (0x00000000000000A0ull + (((offset) & 1) * 8))
-#define CVMX_PCI_DMA_INT_LEV0 \
- (0x00000000000000A4ull)
-#define CVMX_PCI_DMA_INT_LEV1 \
- (0x00000000000000ACull)
-#define CVMX_PCI_DMA_INT_LEVX(offset) \
- (0x00000000000000A4ull + (((offset) & 1) * 8))
-#define CVMX_PCI_DMA_TIME0 \
- (0x00000000000000B0ull)
-#define CVMX_PCI_DMA_TIME1 \
- (0x00000000000000B4ull)
-#define CVMX_PCI_DMA_TIMEX(offset) \
- (0x00000000000000B0ull + (((offset) & 1) * 4))
-#define CVMX_PCI_INSTR_COUNT0 \
- (0x0000000000000084ull)
-#define CVMX_PCI_INSTR_COUNT1 \
- (0x000000000000008Cull)
-#define CVMX_PCI_INSTR_COUNT2 \
- (0x0000000000000094ull)
-#define CVMX_PCI_INSTR_COUNT3 \
- (0x000000000000009Cull)
-#define CVMX_PCI_INSTR_COUNTX(offset) \
- (0x0000000000000084ull + (((offset) & 3) * 8))
-#define CVMX_PCI_INT_ENB \
- (0x0000000000000038ull)
-#define CVMX_PCI_INT_ENB2 \
- (0x00000000000001A0ull)
-#define CVMX_PCI_INT_SUM \
- (0x0000000000000030ull)
-#define CVMX_PCI_INT_SUM2 \
- (0x0000000000000198ull)
-#define CVMX_PCI_MSI_RCV \
- (0x00000000000000F0ull)
-#define CVMX_PCI_PKTS_SENT0 \
- (0x0000000000000040ull)
-#define CVMX_PCI_PKTS_SENT1 \
- (0x0000000000000050ull)
-#define CVMX_PCI_PKTS_SENT2 \
- (0x0000000000000060ull)
-#define CVMX_PCI_PKTS_SENT3 \
- (0x0000000000000070ull)
-#define CVMX_PCI_PKTS_SENTX(offset) \
- (0x0000000000000040ull + (((offset) & 3) * 16))
-#define CVMX_PCI_PKTS_SENT_INT_LEV0 \
- (0x0000000000000048ull)
-#define CVMX_PCI_PKTS_SENT_INT_LEV1 \
- (0x0000000000000058ull)
-#define CVMX_PCI_PKTS_SENT_INT_LEV2 \
- (0x0000000000000068ull)
-#define CVMX_PCI_PKTS_SENT_INT_LEV3 \
- (0x0000000000000078ull)
-#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) \
- (0x0000000000000048ull + (((offset) & 3) * 16))
-#define CVMX_PCI_PKTS_SENT_TIME0 \
- (0x000000000000004Cull)
-#define CVMX_PCI_PKTS_SENT_TIME1 \
- (0x000000000000005Cull)
-#define CVMX_PCI_PKTS_SENT_TIME2 \
- (0x000000000000006Cull)
-#define CVMX_PCI_PKTS_SENT_TIME3 \
- (0x000000000000007Cull)
-#define CVMX_PCI_PKTS_SENT_TIMEX(offset) \
- (0x000000000000004Cull + (((offset) & 3) * 16))
-#define CVMX_PCI_PKT_CREDITS0 \
- (0x0000000000000044ull)
-#define CVMX_PCI_PKT_CREDITS1 \
- (0x0000000000000054ull)
-#define CVMX_PCI_PKT_CREDITS2 \
- (0x0000000000000064ull)
-#define CVMX_PCI_PKT_CREDITS3 \
- (0x0000000000000074ull)
-#define CVMX_PCI_PKT_CREDITSX(offset) \
- (0x0000000000000044ull + (((offset) & 3) * 16))
-#define CVMX_PCI_READ_CMD_6 \
- (0x0000000000000180ull)
-#define CVMX_PCI_READ_CMD_C \
- (0x0000000000000184ull)
-#define CVMX_PCI_READ_CMD_E \
- (0x0000000000000188ull)
-#define CVMX_PCI_READ_TIMEOUT \
- CVMX_ADD_IO_SEG(0x00011F00000000B0ull)
-#define CVMX_PCI_SCM_REG \
- (0x00000000000001A8ull)
-#define CVMX_PCI_TSR_REG \
- (0x00000000000001B0ull)
-#define CVMX_PCI_WIN_RD_ADDR \
- (0x0000000000000008ull)
-#define CVMX_PCI_WIN_RD_DATA \
- (0x0000000000000020ull)
-#define CVMX_PCI_WIN_WR_ADDR \
- (0x0000000000000000ull)
-#define CVMX_PCI_WIN_WR_DATA \
- (0x0000000000000010ull)
-#define CVMX_PCI_WIN_WR_MASK \
- (0x0000000000000018ull)
+#define CVMX_PCI_BAR1_INDEXX(offset) (0x0000000000000100ull + ((offset) & 31) * 4)
+#define CVMX_PCI_BIST_REG (0x00000000000001C0ull)
+#define CVMX_PCI_CFG00 (0x0000000000000000ull)
+#define CVMX_PCI_CFG01 (0x0000000000000004ull)
+#define CVMX_PCI_CFG02 (0x0000000000000008ull)
+#define CVMX_PCI_CFG03 (0x000000000000000Cull)
+#define CVMX_PCI_CFG04 (0x0000000000000010ull)
+#define CVMX_PCI_CFG05 (0x0000000000000014ull)
+#define CVMX_PCI_CFG06 (0x0000000000000018ull)
+#define CVMX_PCI_CFG07 (0x000000000000001Cull)
+#define CVMX_PCI_CFG08 (0x0000000000000020ull)
+#define CVMX_PCI_CFG09 (0x0000000000000024ull)
+#define CVMX_PCI_CFG10 (0x0000000000000028ull)
+#define CVMX_PCI_CFG11 (0x000000000000002Cull)
+#define CVMX_PCI_CFG12 (0x0000000000000030ull)
+#define CVMX_PCI_CFG13 (0x0000000000000034ull)
+#define CVMX_PCI_CFG15 (0x000000000000003Cull)
+#define CVMX_PCI_CFG16 (0x0000000000000040ull)
+#define CVMX_PCI_CFG17 (0x0000000000000044ull)
+#define CVMX_PCI_CFG18 (0x0000000000000048ull)
+#define CVMX_PCI_CFG19 (0x000000000000004Cull)
+#define CVMX_PCI_CFG20 (0x0000000000000050ull)
+#define CVMX_PCI_CFG21 (0x0000000000000054ull)
+#define CVMX_PCI_CFG22 (0x0000000000000058ull)
+#define CVMX_PCI_CFG56 (0x00000000000000E0ull)
+#define CVMX_PCI_CFG57 (0x00000000000000E4ull)
+#define CVMX_PCI_CFG58 (0x00000000000000E8ull)
+#define CVMX_PCI_CFG59 (0x00000000000000ECull)
+#define CVMX_PCI_CFG60 (0x00000000000000F0ull)
+#define CVMX_PCI_CFG61 (0x00000000000000F4ull)
+#define CVMX_PCI_CFG62 (0x00000000000000F8ull)
+#define CVMX_PCI_CFG63 (0x00000000000000FCull)
+#define CVMX_PCI_CNT_REG (0x00000000000001B8ull)
+#define CVMX_PCI_CTL_STATUS_2 (0x000000000000018Cull)
+#define CVMX_PCI_DBELL_X(offset) (0x0000000000000080ull + ((offset) & 3) * 8)
+#define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0)
+#define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1)
+#define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8)
+#define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0)
+#define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1)
+#define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8)
+#define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0)
+#define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1)
+#define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4)
+#define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0)
+#define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1)
+#define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2)
+#define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3)
+#define CVMX_PCI_INSTR_COUNTX(offset) (0x0000000000000084ull + ((offset) & 3) * 8)
+#define CVMX_PCI_INT_ENB (0x0000000000000038ull)
+#define CVMX_PCI_INT_ENB2 (0x00000000000001A0ull)
+#define CVMX_PCI_INT_SUM (0x0000000000000030ull)
+#define CVMX_PCI_INT_SUM2 (0x0000000000000198ull)
+#define CVMX_PCI_MSI_RCV (0x00000000000000F0ull)
+#define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0)
+#define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1)
+#define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2)
+#define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3)
+#define CVMX_PCI_PKTS_SENTX(offset) (0x0000000000000040ull + ((offset) & 3) * 16)
+#define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0)
+#define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1)
+#define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2)
+#define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3)
+#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) (0x0000000000000048ull + ((offset) & 3) * 16)
+#define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0)
+#define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1)
+#define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2)
+#define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3)
+#define CVMX_PCI_PKTS_SENT_TIMEX(offset) (0x000000000000004Cull + ((offset) & 3) * 16)
+#define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0)
+#define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1)
+#define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2)
+#define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3)
+#define CVMX_PCI_PKT_CREDITSX(offset) (0x0000000000000044ull + ((offset) & 3) * 16)
+#define CVMX_PCI_READ_CMD_6 (0x0000000000000180ull)
+#define CVMX_PCI_READ_CMD_C (0x0000000000000184ull)
+#define CVMX_PCI_READ_CMD_E (0x0000000000000188ull)
+#define CVMX_PCI_READ_TIMEOUT (CVMX_ADD_IO_SEG(0x00011F00000000B0ull))
+#define CVMX_PCI_SCM_REG (0x00000000000001A8ull)
+#define CVMX_PCI_TSR_REG (0x00000000000001B0ull)
+#define CVMX_PCI_WIN_RD_ADDR (0x0000000000000008ull)
+#define CVMX_PCI_WIN_RD_DATA (0x0000000000000020ull)
+#define CVMX_PCI_WIN_WR_ADDR (0x0000000000000000ull)
+#define CVMX_PCI_WIN_WR_DATA (0x0000000000000010ull)
+#define CVMX_PCI_WIN_WR_MASK (0x0000000000000018ull)
union cvmx_pci_bar1_indexx {
uint32_t u32;
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
index 75574c918942..f8cb88902efb 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,158 +28,83 @@
#ifndef __CVMX_PCIERCX_DEFS_H__
#define __CVMX_PCIERCX_DEFS_H__
-#define CVMX_PCIERCX_CFG000(offset) \
- (0x0000000000000000ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG001(offset) \
- (0x0000000000000004ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG002(offset) \
- (0x0000000000000008ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG003(offset) \
- (0x000000000000000Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG004(offset) \
- (0x0000000000000010ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG005(offset) \
- (0x0000000000000014ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG006(offset) \
- (0x0000000000000018ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG007(offset) \
- (0x000000000000001Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG008(offset) \
- (0x0000000000000020ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG009(offset) \
- (0x0000000000000024ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG010(offset) \
- (0x0000000000000028ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG011(offset) \
- (0x000000000000002Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG012(offset) \
- (0x0000000000000030ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG013(offset) \
- (0x0000000000000034ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG014(offset) \
- (0x0000000000000038ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG015(offset) \
- (0x000000000000003Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG016(offset) \
- (0x0000000000000040ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG017(offset) \
- (0x0000000000000044ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG020(offset) \
- (0x0000000000000050ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG021(offset) \
- (0x0000000000000054ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG022(offset) \
- (0x0000000000000058ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG023(offset) \
- (0x000000000000005Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG028(offset) \
- (0x0000000000000070ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG029(offset) \
- (0x0000000000000074ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG030(offset) \
- (0x0000000000000078ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG031(offset) \
- (0x000000000000007Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG032(offset) \
- (0x0000000000000080ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG033(offset) \
- (0x0000000000000084ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG034(offset) \
- (0x0000000000000088ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG035(offset) \
- (0x000000000000008Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG036(offset) \
- (0x0000000000000090ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG037(offset) \
- (0x0000000000000094ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG038(offset) \
- (0x0000000000000098ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG039(offset) \
- (0x000000000000009Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG040(offset) \
- (0x00000000000000A0ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG041(offset) \
- (0x00000000000000A4ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG042(offset) \
- (0x00000000000000A8ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG064(offset) \
- (0x0000000000000100ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG065(offset) \
- (0x0000000000000104ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG066(offset) \
- (0x0000000000000108ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG067(offset) \
- (0x000000000000010Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG068(offset) \
- (0x0000000000000110ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG069(offset) \
- (0x0000000000000114ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG070(offset) \
- (0x0000000000000118ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG071(offset) \
- (0x000000000000011Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG072(offset) \
- (0x0000000000000120ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG073(offset) \
- (0x0000000000000124ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG074(offset) \
- (0x0000000000000128ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG075(offset) \
- (0x000000000000012Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG076(offset) \
- (0x0000000000000130ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG077(offset) \
- (0x0000000000000134ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG448(offset) \
- (0x0000000000000700ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG449(offset) \
- (0x0000000000000704ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG450(offset) \
- (0x0000000000000708ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG451(offset) \
- (0x000000000000070Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG452(offset) \
- (0x0000000000000710ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG453(offset) \
- (0x0000000000000714ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG454(offset) \
- (0x0000000000000718ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG455(offset) \
- (0x000000000000071Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG456(offset) \
- (0x0000000000000720ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG458(offset) \
- (0x0000000000000728ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG459(offset) \
- (0x000000000000072Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG460(offset) \
- (0x0000000000000730ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG461(offset) \
- (0x0000000000000734ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG462(offset) \
- (0x0000000000000738ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG463(offset) \
- (0x000000000000073Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG464(offset) \
- (0x0000000000000740ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG465(offset) \
- (0x0000000000000744ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG466(offset) \
- (0x0000000000000748ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG467(offset) \
- (0x000000000000074Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG468(offset) \
- (0x0000000000000750ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG490(offset) \
- (0x00000000000007A8ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG491(offset) \
- (0x00000000000007ACull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG492(offset) \
- (0x00000000000007B0ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG516(offset) \
- (0x0000000000000810ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG517(offset) \
- (0x0000000000000814ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG000(block_id) (0x0000000000000000ull)
+#define CVMX_PCIERCX_CFG001(block_id) (0x0000000000000004ull)
+#define CVMX_PCIERCX_CFG002(block_id) (0x0000000000000008ull)
+#define CVMX_PCIERCX_CFG003(block_id) (0x000000000000000Cull)
+#define CVMX_PCIERCX_CFG004(block_id) (0x0000000000000010ull)
+#define CVMX_PCIERCX_CFG005(block_id) (0x0000000000000014ull)
+#define CVMX_PCIERCX_CFG006(block_id) (0x0000000000000018ull)
+#define CVMX_PCIERCX_CFG007(block_id) (0x000000000000001Cull)
+#define CVMX_PCIERCX_CFG008(block_id) (0x0000000000000020ull)
+#define CVMX_PCIERCX_CFG009(block_id) (0x0000000000000024ull)
+#define CVMX_PCIERCX_CFG010(block_id) (0x0000000000000028ull)
+#define CVMX_PCIERCX_CFG011(block_id) (0x000000000000002Cull)
+#define CVMX_PCIERCX_CFG012(block_id) (0x0000000000000030ull)
+#define CVMX_PCIERCX_CFG013(block_id) (0x0000000000000034ull)
+#define CVMX_PCIERCX_CFG014(block_id) (0x0000000000000038ull)
+#define CVMX_PCIERCX_CFG015(block_id) (0x000000000000003Cull)
+#define CVMX_PCIERCX_CFG016(block_id) (0x0000000000000040ull)
+#define CVMX_PCIERCX_CFG017(block_id) (0x0000000000000044ull)
+#define CVMX_PCIERCX_CFG020(block_id) (0x0000000000000050ull)
+#define CVMX_PCIERCX_CFG021(block_id) (0x0000000000000054ull)
+#define CVMX_PCIERCX_CFG022(block_id) (0x0000000000000058ull)
+#define CVMX_PCIERCX_CFG023(block_id) (0x000000000000005Cull)
+#define CVMX_PCIERCX_CFG028(block_id) (0x0000000000000070ull)
+#define CVMX_PCIERCX_CFG029(block_id) (0x0000000000000074ull)
+#define CVMX_PCIERCX_CFG030(block_id) (0x0000000000000078ull)
+#define CVMX_PCIERCX_CFG031(block_id) (0x000000000000007Cull)
+#define CVMX_PCIERCX_CFG032(block_id) (0x0000000000000080ull)
+#define CVMX_PCIERCX_CFG033(block_id) (0x0000000000000084ull)
+#define CVMX_PCIERCX_CFG034(block_id) (0x0000000000000088ull)
+#define CVMX_PCIERCX_CFG035(block_id) (0x000000000000008Cull)
+#define CVMX_PCIERCX_CFG036(block_id) (0x0000000000000090ull)
+#define CVMX_PCIERCX_CFG037(block_id) (0x0000000000000094ull)
+#define CVMX_PCIERCX_CFG038(block_id) (0x0000000000000098ull)
+#define CVMX_PCIERCX_CFG039(block_id) (0x000000000000009Cull)
+#define CVMX_PCIERCX_CFG040(block_id) (0x00000000000000A0ull)
+#define CVMX_PCIERCX_CFG041(block_id) (0x00000000000000A4ull)
+#define CVMX_PCIERCX_CFG042(block_id) (0x00000000000000A8ull)
+#define CVMX_PCIERCX_CFG064(block_id) (0x0000000000000100ull)
+#define CVMX_PCIERCX_CFG065(block_id) (0x0000000000000104ull)
+#define CVMX_PCIERCX_CFG066(block_id) (0x0000000000000108ull)
+#define CVMX_PCIERCX_CFG067(block_id) (0x000000000000010Cull)
+#define CVMX_PCIERCX_CFG068(block_id) (0x0000000000000110ull)
+#define CVMX_PCIERCX_CFG069(block_id) (0x0000000000000114ull)
+#define CVMX_PCIERCX_CFG070(block_id) (0x0000000000000118ull)
+#define CVMX_PCIERCX_CFG071(block_id) (0x000000000000011Cull)
+#define CVMX_PCIERCX_CFG072(block_id) (0x0000000000000120ull)
+#define CVMX_PCIERCX_CFG073(block_id) (0x0000000000000124ull)
+#define CVMX_PCIERCX_CFG074(block_id) (0x0000000000000128ull)
+#define CVMX_PCIERCX_CFG075(block_id) (0x000000000000012Cull)
+#define CVMX_PCIERCX_CFG076(block_id) (0x0000000000000130ull)
+#define CVMX_PCIERCX_CFG077(block_id) (0x0000000000000134ull)
+#define CVMX_PCIERCX_CFG448(block_id) (0x0000000000000700ull)
+#define CVMX_PCIERCX_CFG449(block_id) (0x0000000000000704ull)
+#define CVMX_PCIERCX_CFG450(block_id) (0x0000000000000708ull)
+#define CVMX_PCIERCX_CFG451(block_id) (0x000000000000070Cull)
+#define CVMX_PCIERCX_CFG452(block_id) (0x0000000000000710ull)
+#define CVMX_PCIERCX_CFG453(block_id) (0x0000000000000714ull)
+#define CVMX_PCIERCX_CFG454(block_id) (0x0000000000000718ull)
+#define CVMX_PCIERCX_CFG455(block_id) (0x000000000000071Cull)
+#define CVMX_PCIERCX_CFG456(block_id) (0x0000000000000720ull)
+#define CVMX_PCIERCX_CFG458(block_id) (0x0000000000000728ull)
+#define CVMX_PCIERCX_CFG459(block_id) (0x000000000000072Cull)
+#define CVMX_PCIERCX_CFG460(block_id) (0x0000000000000730ull)
+#define CVMX_PCIERCX_CFG461(block_id) (0x0000000000000734ull)
+#define CVMX_PCIERCX_CFG462(block_id) (0x0000000000000738ull)
+#define CVMX_PCIERCX_CFG463(block_id) (0x000000000000073Cull)
+#define CVMX_PCIERCX_CFG464(block_id) (0x0000000000000740ull)
+#define CVMX_PCIERCX_CFG465(block_id) (0x0000000000000744ull)
+#define CVMX_PCIERCX_CFG466(block_id) (0x0000000000000748ull)
+#define CVMX_PCIERCX_CFG467(block_id) (0x000000000000074Cull)
+#define CVMX_PCIERCX_CFG468(block_id) (0x0000000000000750ull)
+#define CVMX_PCIERCX_CFG490(block_id) (0x00000000000007A8ull)
+#define CVMX_PCIERCX_CFG491(block_id) (0x00000000000007ACull)
+#define CVMX_PCIERCX_CFG492(block_id) (0x00000000000007B0ull)
+#define CVMX_PCIERCX_CFG515(block_id) (0x000000000000080Cull)
+#define CVMX_PCIERCX_CFG516(block_id) (0x0000000000000810ull)
+#define CVMX_PCIERCX_CFG517(block_id) (0x0000000000000814ull)
union cvmx_pciercx_cfg000 {
uint32_t u32;
@@ -191,6 +116,8 @@ union cvmx_pciercx_cfg000 {
struct cvmx_pciercx_cfg000_s cn52xxp1;
struct cvmx_pciercx_cfg000_s cn56xx;
struct cvmx_pciercx_cfg000_s cn56xxp1;
+ struct cvmx_pciercx_cfg000_s cn63xx;
+ struct cvmx_pciercx_cfg000_s cn63xxp1;
};
union cvmx_pciercx_cfg001 {
@@ -225,6 +152,8 @@ union cvmx_pciercx_cfg001 {
struct cvmx_pciercx_cfg001_s cn52xxp1;
struct cvmx_pciercx_cfg001_s cn56xx;
struct cvmx_pciercx_cfg001_s cn56xxp1;
+ struct cvmx_pciercx_cfg001_s cn63xx;
+ struct cvmx_pciercx_cfg001_s cn63xxp1;
};
union cvmx_pciercx_cfg002 {
@@ -239,6 +168,8 @@ union cvmx_pciercx_cfg002 {
struct cvmx_pciercx_cfg002_s cn52xxp1;
struct cvmx_pciercx_cfg002_s cn56xx;
struct cvmx_pciercx_cfg002_s cn56xxp1;
+ struct cvmx_pciercx_cfg002_s cn63xx;
+ struct cvmx_pciercx_cfg002_s cn63xxp1;
};
union cvmx_pciercx_cfg003 {
@@ -254,6 +185,8 @@ union cvmx_pciercx_cfg003 {
struct cvmx_pciercx_cfg003_s cn52xxp1;
struct cvmx_pciercx_cfg003_s cn56xx;
struct cvmx_pciercx_cfg003_s cn56xxp1;
+ struct cvmx_pciercx_cfg003_s cn63xx;
+ struct cvmx_pciercx_cfg003_s cn63xxp1;
};
union cvmx_pciercx_cfg004 {
@@ -265,6 +198,8 @@ union cvmx_pciercx_cfg004 {
struct cvmx_pciercx_cfg004_s cn52xxp1;
struct cvmx_pciercx_cfg004_s cn56xx;
struct cvmx_pciercx_cfg004_s cn56xxp1;
+ struct cvmx_pciercx_cfg004_s cn63xx;
+ struct cvmx_pciercx_cfg004_s cn63xxp1;
};
union cvmx_pciercx_cfg005 {
@@ -276,6 +211,8 @@ union cvmx_pciercx_cfg005 {
struct cvmx_pciercx_cfg005_s cn52xxp1;
struct cvmx_pciercx_cfg005_s cn56xx;
struct cvmx_pciercx_cfg005_s cn56xxp1;
+ struct cvmx_pciercx_cfg005_s cn63xx;
+ struct cvmx_pciercx_cfg005_s cn63xxp1;
};
union cvmx_pciercx_cfg006 {
@@ -290,6 +227,8 @@ union cvmx_pciercx_cfg006 {
struct cvmx_pciercx_cfg006_s cn52xxp1;
struct cvmx_pciercx_cfg006_s cn56xx;
struct cvmx_pciercx_cfg006_s cn56xxp1;
+ struct cvmx_pciercx_cfg006_s cn63xx;
+ struct cvmx_pciercx_cfg006_s cn63xxp1;
};
union cvmx_pciercx_cfg007 {
@@ -317,6 +256,8 @@ union cvmx_pciercx_cfg007 {
struct cvmx_pciercx_cfg007_s cn52xxp1;
struct cvmx_pciercx_cfg007_s cn56xx;
struct cvmx_pciercx_cfg007_s cn56xxp1;
+ struct cvmx_pciercx_cfg007_s cn63xx;
+ struct cvmx_pciercx_cfg007_s cn63xxp1;
};
union cvmx_pciercx_cfg008 {
@@ -331,6 +272,8 @@ union cvmx_pciercx_cfg008 {
struct cvmx_pciercx_cfg008_s cn52xxp1;
struct cvmx_pciercx_cfg008_s cn56xx;
struct cvmx_pciercx_cfg008_s cn56xxp1;
+ struct cvmx_pciercx_cfg008_s cn63xx;
+ struct cvmx_pciercx_cfg008_s cn63xxp1;
};
union cvmx_pciercx_cfg009 {
@@ -347,6 +290,8 @@ union cvmx_pciercx_cfg009 {
struct cvmx_pciercx_cfg009_s cn52xxp1;
struct cvmx_pciercx_cfg009_s cn56xx;
struct cvmx_pciercx_cfg009_s cn56xxp1;
+ struct cvmx_pciercx_cfg009_s cn63xx;
+ struct cvmx_pciercx_cfg009_s cn63xxp1;
};
union cvmx_pciercx_cfg010 {
@@ -358,6 +303,8 @@ union cvmx_pciercx_cfg010 {
struct cvmx_pciercx_cfg010_s cn52xxp1;
struct cvmx_pciercx_cfg010_s cn56xx;
struct cvmx_pciercx_cfg010_s cn56xxp1;
+ struct cvmx_pciercx_cfg010_s cn63xx;
+ struct cvmx_pciercx_cfg010_s cn63xxp1;
};
union cvmx_pciercx_cfg011 {
@@ -369,6 +316,8 @@ union cvmx_pciercx_cfg011 {
struct cvmx_pciercx_cfg011_s cn52xxp1;
struct cvmx_pciercx_cfg011_s cn56xx;
struct cvmx_pciercx_cfg011_s cn56xxp1;
+ struct cvmx_pciercx_cfg011_s cn63xx;
+ struct cvmx_pciercx_cfg011_s cn63xxp1;
};
union cvmx_pciercx_cfg012 {
@@ -381,6 +330,8 @@ union cvmx_pciercx_cfg012 {
struct cvmx_pciercx_cfg012_s cn52xxp1;
struct cvmx_pciercx_cfg012_s cn56xx;
struct cvmx_pciercx_cfg012_s cn56xxp1;
+ struct cvmx_pciercx_cfg012_s cn63xx;
+ struct cvmx_pciercx_cfg012_s cn63xxp1;
};
union cvmx_pciercx_cfg013 {
@@ -393,6 +344,8 @@ union cvmx_pciercx_cfg013 {
struct cvmx_pciercx_cfg013_s cn52xxp1;
struct cvmx_pciercx_cfg013_s cn56xx;
struct cvmx_pciercx_cfg013_s cn56xxp1;
+ struct cvmx_pciercx_cfg013_s cn63xx;
+ struct cvmx_pciercx_cfg013_s cn63xxp1;
};
union cvmx_pciercx_cfg014 {
@@ -404,6 +357,8 @@ union cvmx_pciercx_cfg014 {
struct cvmx_pciercx_cfg014_s cn52xxp1;
struct cvmx_pciercx_cfg014_s cn56xx;
struct cvmx_pciercx_cfg014_s cn56xxp1;
+ struct cvmx_pciercx_cfg014_s cn63xx;
+ struct cvmx_pciercx_cfg014_s cn63xxp1;
};
union cvmx_pciercx_cfg015 {
@@ -429,6 +384,8 @@ union cvmx_pciercx_cfg015 {
struct cvmx_pciercx_cfg015_s cn52xxp1;
struct cvmx_pciercx_cfg015_s cn56xx;
struct cvmx_pciercx_cfg015_s cn56xxp1;
+ struct cvmx_pciercx_cfg015_s cn63xx;
+ struct cvmx_pciercx_cfg015_s cn63xxp1;
};
union cvmx_pciercx_cfg016 {
@@ -449,6 +406,8 @@ union cvmx_pciercx_cfg016 {
struct cvmx_pciercx_cfg016_s cn52xxp1;
struct cvmx_pciercx_cfg016_s cn56xx;
struct cvmx_pciercx_cfg016_s cn56xxp1;
+ struct cvmx_pciercx_cfg016_s cn63xx;
+ struct cvmx_pciercx_cfg016_s cn63xxp1;
};
union cvmx_pciercx_cfg017 {
@@ -471,6 +430,8 @@ union cvmx_pciercx_cfg017 {
struct cvmx_pciercx_cfg017_s cn52xxp1;
struct cvmx_pciercx_cfg017_s cn56xx;
struct cvmx_pciercx_cfg017_s cn56xxp1;
+ struct cvmx_pciercx_cfg017_s cn63xx;
+ struct cvmx_pciercx_cfg017_s cn63xxp1;
};
union cvmx_pciercx_cfg020 {
@@ -488,6 +449,8 @@ union cvmx_pciercx_cfg020 {
struct cvmx_pciercx_cfg020_s cn52xxp1;
struct cvmx_pciercx_cfg020_s cn56xx;
struct cvmx_pciercx_cfg020_s cn56xxp1;
+ struct cvmx_pciercx_cfg020_s cn63xx;
+ struct cvmx_pciercx_cfg020_s cn63xxp1;
};
union cvmx_pciercx_cfg021 {
@@ -500,6 +463,8 @@ union cvmx_pciercx_cfg021 {
struct cvmx_pciercx_cfg021_s cn52xxp1;
struct cvmx_pciercx_cfg021_s cn56xx;
struct cvmx_pciercx_cfg021_s cn56xxp1;
+ struct cvmx_pciercx_cfg021_s cn63xx;
+ struct cvmx_pciercx_cfg021_s cn63xxp1;
};
union cvmx_pciercx_cfg022 {
@@ -511,6 +476,8 @@ union cvmx_pciercx_cfg022 {
struct cvmx_pciercx_cfg022_s cn52xxp1;
struct cvmx_pciercx_cfg022_s cn56xx;
struct cvmx_pciercx_cfg022_s cn56xxp1;
+ struct cvmx_pciercx_cfg022_s cn63xx;
+ struct cvmx_pciercx_cfg022_s cn63xxp1;
};
union cvmx_pciercx_cfg023 {
@@ -523,6 +490,8 @@ union cvmx_pciercx_cfg023 {
struct cvmx_pciercx_cfg023_s cn52xxp1;
struct cvmx_pciercx_cfg023_s cn56xx;
struct cvmx_pciercx_cfg023_s cn56xxp1;
+ struct cvmx_pciercx_cfg023_s cn63xx;
+ struct cvmx_pciercx_cfg023_s cn63xxp1;
};
union cvmx_pciercx_cfg028 {
@@ -540,6 +509,8 @@ union cvmx_pciercx_cfg028 {
struct cvmx_pciercx_cfg028_s cn52xxp1;
struct cvmx_pciercx_cfg028_s cn56xx;
struct cvmx_pciercx_cfg028_s cn56xxp1;
+ struct cvmx_pciercx_cfg028_s cn63xx;
+ struct cvmx_pciercx_cfg028_s cn63xxp1;
};
union cvmx_pciercx_cfg029 {
@@ -561,6 +532,8 @@ union cvmx_pciercx_cfg029 {
struct cvmx_pciercx_cfg029_s cn52xxp1;
struct cvmx_pciercx_cfg029_s cn56xx;
struct cvmx_pciercx_cfg029_s cn56xxp1;
+ struct cvmx_pciercx_cfg029_s cn63xx;
+ struct cvmx_pciercx_cfg029_s cn63xxp1;
};
union cvmx_pciercx_cfg030 {
@@ -590,6 +563,8 @@ union cvmx_pciercx_cfg030 {
struct cvmx_pciercx_cfg030_s cn52xxp1;
struct cvmx_pciercx_cfg030_s cn56xx;
struct cvmx_pciercx_cfg030_s cn56xxp1;
+ struct cvmx_pciercx_cfg030_s cn63xx;
+ struct cvmx_pciercx_cfg030_s cn63xxp1;
};
union cvmx_pciercx_cfg031 {
@@ -611,6 +586,8 @@ union cvmx_pciercx_cfg031 {
struct cvmx_pciercx_cfg031_s cn52xxp1;
struct cvmx_pciercx_cfg031_s cn56xx;
struct cvmx_pciercx_cfg031_s cn56xxp1;
+ struct cvmx_pciercx_cfg031_s cn63xx;
+ struct cvmx_pciercx_cfg031_s cn63xxp1;
};
union cvmx_pciercx_cfg032 {
@@ -641,6 +618,8 @@ union cvmx_pciercx_cfg032 {
struct cvmx_pciercx_cfg032_s cn52xxp1;
struct cvmx_pciercx_cfg032_s cn56xx;
struct cvmx_pciercx_cfg032_s cn56xxp1;
+ struct cvmx_pciercx_cfg032_s cn63xx;
+ struct cvmx_pciercx_cfg032_s cn63xxp1;
};
union cvmx_pciercx_cfg033 {
@@ -663,6 +642,8 @@ union cvmx_pciercx_cfg033 {
struct cvmx_pciercx_cfg033_s cn52xxp1;
struct cvmx_pciercx_cfg033_s cn56xx;
struct cvmx_pciercx_cfg033_s cn56xxp1;
+ struct cvmx_pciercx_cfg033_s cn63xx;
+ struct cvmx_pciercx_cfg033_s cn63xxp1;
};
union cvmx_pciercx_cfg034 {
@@ -695,6 +676,8 @@ union cvmx_pciercx_cfg034 {
struct cvmx_pciercx_cfg034_s cn52xxp1;
struct cvmx_pciercx_cfg034_s cn56xx;
struct cvmx_pciercx_cfg034_s cn56xxp1;
+ struct cvmx_pciercx_cfg034_s cn63xx;
+ struct cvmx_pciercx_cfg034_s cn63xxp1;
};
union cvmx_pciercx_cfg035 {
@@ -713,6 +696,8 @@ union cvmx_pciercx_cfg035 {
struct cvmx_pciercx_cfg035_s cn52xxp1;
struct cvmx_pciercx_cfg035_s cn56xx;
struct cvmx_pciercx_cfg035_s cn56xxp1;
+ struct cvmx_pciercx_cfg035_s cn63xx;
+ struct cvmx_pciercx_cfg035_s cn63xxp1;
};
union cvmx_pciercx_cfg036 {
@@ -727,6 +712,8 @@ union cvmx_pciercx_cfg036 {
struct cvmx_pciercx_cfg036_s cn52xxp1;
struct cvmx_pciercx_cfg036_s cn56xx;
struct cvmx_pciercx_cfg036_s cn56xxp1;
+ struct cvmx_pciercx_cfg036_s cn63xx;
+ struct cvmx_pciercx_cfg036_s cn63xxp1;
};
union cvmx_pciercx_cfg037 {
@@ -740,6 +727,8 @@ union cvmx_pciercx_cfg037 {
struct cvmx_pciercx_cfg037_s cn52xxp1;
struct cvmx_pciercx_cfg037_s cn56xx;
struct cvmx_pciercx_cfg037_s cn56xxp1;
+ struct cvmx_pciercx_cfg037_s cn63xx;
+ struct cvmx_pciercx_cfg037_s cn63xxp1;
};
union cvmx_pciercx_cfg038 {
@@ -753,28 +742,51 @@ union cvmx_pciercx_cfg038 {
struct cvmx_pciercx_cfg038_s cn52xxp1;
struct cvmx_pciercx_cfg038_s cn56xx;
struct cvmx_pciercx_cfg038_s cn56xxp1;
+ struct cvmx_pciercx_cfg038_s cn63xx;
+ struct cvmx_pciercx_cfg038_s cn63xxp1;
};
union cvmx_pciercx_cfg039 {
uint32_t u32;
struct cvmx_pciercx_cfg039_s {
- uint32_t reserved_0_31:32;
+ uint32_t reserved_9_31:23;
+ uint32_t cls:1;
+ uint32_t slsv:7;
+ uint32_t reserved_0_0:1;
} s;
- struct cvmx_pciercx_cfg039_s cn52xx;
- struct cvmx_pciercx_cfg039_s cn52xxp1;
- struct cvmx_pciercx_cfg039_s cn56xx;
- struct cvmx_pciercx_cfg039_s cn56xxp1;
+ struct cvmx_pciercx_cfg039_cn52xx {
+ uint32_t reserved_0_31:32;
+ } cn52xx;
+ struct cvmx_pciercx_cfg039_cn52xx cn52xxp1;
+ struct cvmx_pciercx_cfg039_cn52xx cn56xx;
+ struct cvmx_pciercx_cfg039_cn52xx cn56xxp1;
+ struct cvmx_pciercx_cfg039_s cn63xx;
+ struct cvmx_pciercx_cfg039_cn52xx cn63xxp1;
};
union cvmx_pciercx_cfg040 {
uint32_t u32;
struct cvmx_pciercx_cfg040_s {
+ uint32_t reserved_17_31:15;
+ uint32_t cdl:1;
+ uint32_t reserved_13_15:3;
+ uint32_t cde:1;
+ uint32_t csos:1;
+ uint32_t emc:1;
+ uint32_t tm:3;
+ uint32_t sde:1;
+ uint32_t hasd:1;
+ uint32_t ec:1;
+ uint32_t tls:4;
+ } s;
+ struct cvmx_pciercx_cfg040_cn52xx {
uint32_t reserved_0_31:32;
- } s;
- struct cvmx_pciercx_cfg040_s cn52xx;
- struct cvmx_pciercx_cfg040_s cn52xxp1;
- struct cvmx_pciercx_cfg040_s cn56xx;
- struct cvmx_pciercx_cfg040_s cn56xxp1;
+ } cn52xx;
+ struct cvmx_pciercx_cfg040_cn52xx cn52xxp1;
+ struct cvmx_pciercx_cfg040_cn52xx cn56xx;
+ struct cvmx_pciercx_cfg040_cn52xx cn56xxp1;
+ struct cvmx_pciercx_cfg040_s cn63xx;
+ struct cvmx_pciercx_cfg040_s cn63xxp1;
};
union cvmx_pciercx_cfg041 {
@@ -786,6 +798,8 @@ union cvmx_pciercx_cfg041 {
struct cvmx_pciercx_cfg041_s cn52xxp1;
struct cvmx_pciercx_cfg041_s cn56xx;
struct cvmx_pciercx_cfg041_s cn56xxp1;
+ struct cvmx_pciercx_cfg041_s cn63xx;
+ struct cvmx_pciercx_cfg041_s cn63xxp1;
};
union cvmx_pciercx_cfg042 {
@@ -797,6 +811,8 @@ union cvmx_pciercx_cfg042 {
struct cvmx_pciercx_cfg042_s cn52xxp1;
struct cvmx_pciercx_cfg042_s cn56xx;
struct cvmx_pciercx_cfg042_s cn56xxp1;
+ struct cvmx_pciercx_cfg042_s cn63xx;
+ struct cvmx_pciercx_cfg042_s cn63xxp1;
};
union cvmx_pciercx_cfg064 {
@@ -810,6 +826,8 @@ union cvmx_pciercx_cfg064 {
struct cvmx_pciercx_cfg064_s cn52xxp1;
struct cvmx_pciercx_cfg064_s cn56xx;
struct cvmx_pciercx_cfg064_s cn56xxp1;
+ struct cvmx_pciercx_cfg064_s cn63xx;
+ struct cvmx_pciercx_cfg064_s cn63xxp1;
};
union cvmx_pciercx_cfg065 {
@@ -834,6 +852,8 @@ union cvmx_pciercx_cfg065 {
struct cvmx_pciercx_cfg065_s cn52xxp1;
struct cvmx_pciercx_cfg065_s cn56xx;
struct cvmx_pciercx_cfg065_s cn56xxp1;
+ struct cvmx_pciercx_cfg065_s cn63xx;
+ struct cvmx_pciercx_cfg065_s cn63xxp1;
};
union cvmx_pciercx_cfg066 {
@@ -858,6 +878,8 @@ union cvmx_pciercx_cfg066 {
struct cvmx_pciercx_cfg066_s cn52xxp1;
struct cvmx_pciercx_cfg066_s cn56xx;
struct cvmx_pciercx_cfg066_s cn56xxp1;
+ struct cvmx_pciercx_cfg066_s cn63xx;
+ struct cvmx_pciercx_cfg066_s cn63xxp1;
};
union cvmx_pciercx_cfg067 {
@@ -882,6 +904,8 @@ union cvmx_pciercx_cfg067 {
struct cvmx_pciercx_cfg067_s cn52xxp1;
struct cvmx_pciercx_cfg067_s cn56xx;
struct cvmx_pciercx_cfg067_s cn56xxp1;
+ struct cvmx_pciercx_cfg067_s cn63xx;
+ struct cvmx_pciercx_cfg067_s cn63xxp1;
};
union cvmx_pciercx_cfg068 {
@@ -901,6 +925,8 @@ union cvmx_pciercx_cfg068 {
struct cvmx_pciercx_cfg068_s cn52xxp1;
struct cvmx_pciercx_cfg068_s cn56xx;
struct cvmx_pciercx_cfg068_s cn56xxp1;
+ struct cvmx_pciercx_cfg068_s cn63xx;
+ struct cvmx_pciercx_cfg068_s cn63xxp1;
};
union cvmx_pciercx_cfg069 {
@@ -920,6 +946,8 @@ union cvmx_pciercx_cfg069 {
struct cvmx_pciercx_cfg069_s cn52xxp1;
struct cvmx_pciercx_cfg069_s cn56xx;
struct cvmx_pciercx_cfg069_s cn56xxp1;
+ struct cvmx_pciercx_cfg069_s cn63xx;
+ struct cvmx_pciercx_cfg069_s cn63xxp1;
};
union cvmx_pciercx_cfg070 {
@@ -936,6 +964,8 @@ union cvmx_pciercx_cfg070 {
struct cvmx_pciercx_cfg070_s cn52xxp1;
struct cvmx_pciercx_cfg070_s cn56xx;
struct cvmx_pciercx_cfg070_s cn56xxp1;
+ struct cvmx_pciercx_cfg070_s cn63xx;
+ struct cvmx_pciercx_cfg070_s cn63xxp1;
};
union cvmx_pciercx_cfg071 {
@@ -947,6 +977,8 @@ union cvmx_pciercx_cfg071 {
struct cvmx_pciercx_cfg071_s cn52xxp1;
struct cvmx_pciercx_cfg071_s cn56xx;
struct cvmx_pciercx_cfg071_s cn56xxp1;
+ struct cvmx_pciercx_cfg071_s cn63xx;
+ struct cvmx_pciercx_cfg071_s cn63xxp1;
};
union cvmx_pciercx_cfg072 {
@@ -958,6 +990,8 @@ union cvmx_pciercx_cfg072 {
struct cvmx_pciercx_cfg072_s cn52xxp1;
struct cvmx_pciercx_cfg072_s cn56xx;
struct cvmx_pciercx_cfg072_s cn56xxp1;
+ struct cvmx_pciercx_cfg072_s cn63xx;
+ struct cvmx_pciercx_cfg072_s cn63xxp1;
};
union cvmx_pciercx_cfg073 {
@@ -969,6 +1003,8 @@ union cvmx_pciercx_cfg073 {
struct cvmx_pciercx_cfg073_s cn52xxp1;
struct cvmx_pciercx_cfg073_s cn56xx;
struct cvmx_pciercx_cfg073_s cn56xxp1;
+ struct cvmx_pciercx_cfg073_s cn63xx;
+ struct cvmx_pciercx_cfg073_s cn63xxp1;
};
union cvmx_pciercx_cfg074 {
@@ -980,6 +1016,8 @@ union cvmx_pciercx_cfg074 {
struct cvmx_pciercx_cfg074_s cn52xxp1;
struct cvmx_pciercx_cfg074_s cn56xx;
struct cvmx_pciercx_cfg074_s cn56xxp1;
+ struct cvmx_pciercx_cfg074_s cn63xx;
+ struct cvmx_pciercx_cfg074_s cn63xxp1;
};
union cvmx_pciercx_cfg075 {
@@ -994,6 +1032,8 @@ union cvmx_pciercx_cfg075 {
struct cvmx_pciercx_cfg075_s cn52xxp1;
struct cvmx_pciercx_cfg075_s cn56xx;
struct cvmx_pciercx_cfg075_s cn56xxp1;
+ struct cvmx_pciercx_cfg075_s cn63xx;
+ struct cvmx_pciercx_cfg075_s cn63xxp1;
};
union cvmx_pciercx_cfg076 {
@@ -1013,6 +1053,8 @@ union cvmx_pciercx_cfg076 {
struct cvmx_pciercx_cfg076_s cn52xxp1;
struct cvmx_pciercx_cfg076_s cn56xx;
struct cvmx_pciercx_cfg076_s cn56xxp1;
+ struct cvmx_pciercx_cfg076_s cn63xx;
+ struct cvmx_pciercx_cfg076_s cn63xxp1;
};
union cvmx_pciercx_cfg077 {
@@ -1025,6 +1067,8 @@ union cvmx_pciercx_cfg077 {
struct cvmx_pciercx_cfg077_s cn52xxp1;
struct cvmx_pciercx_cfg077_s cn56xx;
struct cvmx_pciercx_cfg077_s cn56xxp1;
+ struct cvmx_pciercx_cfg077_s cn63xx;
+ struct cvmx_pciercx_cfg077_s cn63xxp1;
};
union cvmx_pciercx_cfg448 {
@@ -1037,6 +1081,8 @@ union cvmx_pciercx_cfg448 {
struct cvmx_pciercx_cfg448_s cn52xxp1;
struct cvmx_pciercx_cfg448_s cn56xx;
struct cvmx_pciercx_cfg448_s cn56xxp1;
+ struct cvmx_pciercx_cfg448_s cn63xx;
+ struct cvmx_pciercx_cfg448_s cn63xxp1;
};
union cvmx_pciercx_cfg449 {
@@ -1048,6 +1094,8 @@ union cvmx_pciercx_cfg449 {
struct cvmx_pciercx_cfg449_s cn52xxp1;
struct cvmx_pciercx_cfg449_s cn56xx;
struct cvmx_pciercx_cfg449_s cn56xxp1;
+ struct cvmx_pciercx_cfg449_s cn63xx;
+ struct cvmx_pciercx_cfg449_s cn63xxp1;
};
union cvmx_pciercx_cfg450 {
@@ -1064,6 +1112,8 @@ union cvmx_pciercx_cfg450 {
struct cvmx_pciercx_cfg450_s cn52xxp1;
struct cvmx_pciercx_cfg450_s cn56xx;
struct cvmx_pciercx_cfg450_s cn56xxp1;
+ struct cvmx_pciercx_cfg450_s cn63xx;
+ struct cvmx_pciercx_cfg450_s cn63xxp1;
};
union cvmx_pciercx_cfg451 {
@@ -1080,6 +1130,8 @@ union cvmx_pciercx_cfg451 {
struct cvmx_pciercx_cfg451_s cn52xxp1;
struct cvmx_pciercx_cfg451_s cn56xx;
struct cvmx_pciercx_cfg451_s cn56xxp1;
+ struct cvmx_pciercx_cfg451_s cn63xx;
+ struct cvmx_pciercx_cfg451_s cn63xxp1;
};
union cvmx_pciercx_cfg452 {
@@ -1103,6 +1155,8 @@ union cvmx_pciercx_cfg452 {
struct cvmx_pciercx_cfg452_s cn52xxp1;
struct cvmx_pciercx_cfg452_s cn56xx;
struct cvmx_pciercx_cfg452_s cn56xxp1;
+ struct cvmx_pciercx_cfg452_s cn63xx;
+ struct cvmx_pciercx_cfg452_s cn63xxp1;
};
union cvmx_pciercx_cfg453 {
@@ -1118,6 +1172,8 @@ union cvmx_pciercx_cfg453 {
struct cvmx_pciercx_cfg453_s cn52xxp1;
struct cvmx_pciercx_cfg453_s cn56xx;
struct cvmx_pciercx_cfg453_s cn56xxp1;
+ struct cvmx_pciercx_cfg453_s cn63xx;
+ struct cvmx_pciercx_cfg453_s cn63xxp1;
};
union cvmx_pciercx_cfg454 {
@@ -1136,6 +1192,8 @@ union cvmx_pciercx_cfg454 {
struct cvmx_pciercx_cfg454_s cn52xxp1;
struct cvmx_pciercx_cfg454_s cn56xx;
struct cvmx_pciercx_cfg454_s cn56xxp1;
+ struct cvmx_pciercx_cfg454_s cn63xx;
+ struct cvmx_pciercx_cfg454_s cn63xxp1;
};
union cvmx_pciercx_cfg455 {
@@ -1165,6 +1223,8 @@ union cvmx_pciercx_cfg455 {
struct cvmx_pciercx_cfg455_s cn52xxp1;
struct cvmx_pciercx_cfg455_s cn56xx;
struct cvmx_pciercx_cfg455_s cn56xxp1;
+ struct cvmx_pciercx_cfg455_s cn63xx;
+ struct cvmx_pciercx_cfg455_s cn63xxp1;
};
union cvmx_pciercx_cfg456 {
@@ -1178,6 +1238,8 @@ union cvmx_pciercx_cfg456 {
struct cvmx_pciercx_cfg456_s cn52xxp1;
struct cvmx_pciercx_cfg456_s cn56xx;
struct cvmx_pciercx_cfg456_s cn56xxp1;
+ struct cvmx_pciercx_cfg456_s cn63xx;
+ struct cvmx_pciercx_cfg456_s cn63xxp1;
};
union cvmx_pciercx_cfg458 {
@@ -1189,6 +1251,8 @@ union cvmx_pciercx_cfg458 {
struct cvmx_pciercx_cfg458_s cn52xxp1;
struct cvmx_pciercx_cfg458_s cn56xx;
struct cvmx_pciercx_cfg458_s cn56xxp1;
+ struct cvmx_pciercx_cfg458_s cn63xx;
+ struct cvmx_pciercx_cfg458_s cn63xxp1;
};
union cvmx_pciercx_cfg459 {
@@ -1200,6 +1264,8 @@ union cvmx_pciercx_cfg459 {
struct cvmx_pciercx_cfg459_s cn52xxp1;
struct cvmx_pciercx_cfg459_s cn56xx;
struct cvmx_pciercx_cfg459_s cn56xxp1;
+ struct cvmx_pciercx_cfg459_s cn63xx;
+ struct cvmx_pciercx_cfg459_s cn63xxp1;
};
union cvmx_pciercx_cfg460 {
@@ -1213,6 +1279,8 @@ union cvmx_pciercx_cfg460 {
struct cvmx_pciercx_cfg460_s cn52xxp1;
struct cvmx_pciercx_cfg460_s cn56xx;
struct cvmx_pciercx_cfg460_s cn56xxp1;
+ struct cvmx_pciercx_cfg460_s cn63xx;
+ struct cvmx_pciercx_cfg460_s cn63xxp1;
};
union cvmx_pciercx_cfg461 {
@@ -1226,6 +1294,8 @@ union cvmx_pciercx_cfg461 {
struct cvmx_pciercx_cfg461_s cn52xxp1;
struct cvmx_pciercx_cfg461_s cn56xx;
struct cvmx_pciercx_cfg461_s cn56xxp1;
+ struct cvmx_pciercx_cfg461_s cn63xx;
+ struct cvmx_pciercx_cfg461_s cn63xxp1;
};
union cvmx_pciercx_cfg462 {
@@ -1239,6 +1309,8 @@ union cvmx_pciercx_cfg462 {
struct cvmx_pciercx_cfg462_s cn52xxp1;
struct cvmx_pciercx_cfg462_s cn56xx;
struct cvmx_pciercx_cfg462_s cn56xxp1;
+ struct cvmx_pciercx_cfg462_s cn63xx;
+ struct cvmx_pciercx_cfg462_s cn63xxp1;
};
union cvmx_pciercx_cfg463 {
@@ -1253,6 +1325,8 @@ union cvmx_pciercx_cfg463 {
struct cvmx_pciercx_cfg463_s cn52xxp1;
struct cvmx_pciercx_cfg463_s cn56xx;
struct cvmx_pciercx_cfg463_s cn56xxp1;
+ struct cvmx_pciercx_cfg463_s cn63xx;
+ struct cvmx_pciercx_cfg463_s cn63xxp1;
};
union cvmx_pciercx_cfg464 {
@@ -1267,6 +1341,8 @@ union cvmx_pciercx_cfg464 {
struct cvmx_pciercx_cfg464_s cn52xxp1;
struct cvmx_pciercx_cfg464_s cn56xx;
struct cvmx_pciercx_cfg464_s cn56xxp1;
+ struct cvmx_pciercx_cfg464_s cn63xx;
+ struct cvmx_pciercx_cfg464_s cn63xxp1;
};
union cvmx_pciercx_cfg465 {
@@ -1281,6 +1357,8 @@ union cvmx_pciercx_cfg465 {
struct cvmx_pciercx_cfg465_s cn52xxp1;
struct cvmx_pciercx_cfg465_s cn56xx;
struct cvmx_pciercx_cfg465_s cn56xxp1;
+ struct cvmx_pciercx_cfg465_s cn63xx;
+ struct cvmx_pciercx_cfg465_s cn63xxp1;
};
union cvmx_pciercx_cfg466 {
@@ -1298,6 +1376,8 @@ union cvmx_pciercx_cfg466 {
struct cvmx_pciercx_cfg466_s cn52xxp1;
struct cvmx_pciercx_cfg466_s cn56xx;
struct cvmx_pciercx_cfg466_s cn56xxp1;
+ struct cvmx_pciercx_cfg466_s cn63xx;
+ struct cvmx_pciercx_cfg466_s cn63xxp1;
};
union cvmx_pciercx_cfg467 {
@@ -1313,6 +1393,8 @@ union cvmx_pciercx_cfg467 {
struct cvmx_pciercx_cfg467_s cn52xxp1;
struct cvmx_pciercx_cfg467_s cn56xx;
struct cvmx_pciercx_cfg467_s cn56xxp1;
+ struct cvmx_pciercx_cfg467_s cn63xx;
+ struct cvmx_pciercx_cfg467_s cn63xxp1;
};
union cvmx_pciercx_cfg468 {
@@ -1328,6 +1410,8 @@ union cvmx_pciercx_cfg468 {
struct cvmx_pciercx_cfg468_s cn52xxp1;
struct cvmx_pciercx_cfg468_s cn56xx;
struct cvmx_pciercx_cfg468_s cn56xxp1;
+ struct cvmx_pciercx_cfg468_s cn63xx;
+ struct cvmx_pciercx_cfg468_s cn63xxp1;
};
union cvmx_pciercx_cfg490 {
@@ -1342,6 +1426,8 @@ union cvmx_pciercx_cfg490 {
struct cvmx_pciercx_cfg490_s cn52xxp1;
struct cvmx_pciercx_cfg490_s cn56xx;
struct cvmx_pciercx_cfg490_s cn56xxp1;
+ struct cvmx_pciercx_cfg490_s cn63xx;
+ struct cvmx_pciercx_cfg490_s cn63xxp1;
};
union cvmx_pciercx_cfg491 {
@@ -1356,6 +1442,8 @@ union cvmx_pciercx_cfg491 {
struct cvmx_pciercx_cfg491_s cn52xxp1;
struct cvmx_pciercx_cfg491_s cn56xx;
struct cvmx_pciercx_cfg491_s cn56xxp1;
+ struct cvmx_pciercx_cfg491_s cn63xx;
+ struct cvmx_pciercx_cfg491_s cn63xxp1;
};
union cvmx_pciercx_cfg492 {
@@ -1370,6 +1458,23 @@ union cvmx_pciercx_cfg492 {
struct cvmx_pciercx_cfg492_s cn52xxp1;
struct cvmx_pciercx_cfg492_s cn56xx;
struct cvmx_pciercx_cfg492_s cn56xxp1;
+ struct cvmx_pciercx_cfg492_s cn63xx;
+ struct cvmx_pciercx_cfg492_s cn63xxp1;
+};
+
+union cvmx_pciercx_cfg515 {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg515_s {
+ uint32_t reserved_21_31:11;
+ uint32_t s_d_e:1;
+ uint32_t ctcrb:1;
+ uint32_t cpyts:1;
+ uint32_t dsc:1;
+ uint32_t le:9;
+ uint32_t n_fts:8;
+ } s;
+ struct cvmx_pciercx_cfg515_s cn63xx;
+ struct cvmx_pciercx_cfg515_s cn63xxp1;
};
union cvmx_pciercx_cfg516 {
@@ -1381,6 +1486,8 @@ union cvmx_pciercx_cfg516 {
struct cvmx_pciercx_cfg516_s cn52xxp1;
struct cvmx_pciercx_cfg516_s cn56xx;
struct cvmx_pciercx_cfg516_s cn56xxp1;
+ struct cvmx_pciercx_cfg516_s cn63xx;
+ struct cvmx_pciercx_cfg516_s cn63xxp1;
};
union cvmx_pciercx_cfg517 {
@@ -1392,6 +1499,8 @@ union cvmx_pciercx_cfg517 {
struct cvmx_pciercx_cfg517_s cn52xxp1;
struct cvmx_pciercx_cfg517_s cn56xx;
struct cvmx_pciercx_cfg517_s cn56xxp1;
+ struct cvmx_pciercx_cfg517_s cn63xx;
+ struct cvmx_pciercx_cfg517_s cn63xxp1;
};
#endif
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-pescx-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
index f40cfaf84454..aef84851a94c 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,38 +28,22 @@
#ifndef __CVMX_PESCX_DEFS_H__
#define __CVMX_PESCX_DEFS_H__
-#define CVMX_PESCX_BIST_STATUS(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000018ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_BIST_STATUS2(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000418ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CFG_RD(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000030ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CFG_WR(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000028ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CPL_LUT_VALID(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000098ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CTL_STATUS(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000000ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CTL_STATUS2(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000400ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_DBG_INFO(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000008ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_DBG_INFO_EN(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C80000A0ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_DIAG_STATUS(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000020ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2N_BAR0_START(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000080ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2N_BAR1_START(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000088ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2N_BAR2_START(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000090ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2P_BARX_END(offset, block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000048ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2P_BARX_START(offset, block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000040ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_TLP_CREDITS(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000038ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
+#define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
+#define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull)
union cvmx_pescx_bist_status {
uint64_t u64;
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
index 5ea5dc571b54..5ab8679d89af 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -35,195 +35,191 @@
#ifndef __CVMX_PEXP_DEFS_H__
#define __CVMX_PEXP_DEFS_H__
-#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000008000ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_BIST_STATUS \
- CVMX_ADD_IO_SEG(0x00011F0000008580ull)
-#define CVMX_PEXP_NPEI_BIST_STATUS2 \
- CVMX_ADD_IO_SEG(0x00011F0000008680ull)
-#define CVMX_PEXP_NPEI_CTL_PORT0 \
- CVMX_ADD_IO_SEG(0x00011F0000008250ull)
-#define CVMX_PEXP_NPEI_CTL_PORT1 \
- CVMX_ADD_IO_SEG(0x00011F0000008260ull)
-#define CVMX_PEXP_NPEI_CTL_STATUS \
- CVMX_ADD_IO_SEG(0x00011F0000008570ull)
-#define CVMX_PEXP_NPEI_CTL_STATUS2 \
- CVMX_ADD_IO_SEG(0x00011F000000BC00ull)
-#define CVMX_PEXP_NPEI_DATA_OUT_CNT \
- CVMX_ADD_IO_SEG(0x00011F00000085F0ull)
-#define CVMX_PEXP_NPEI_DBG_DATA \
- CVMX_ADD_IO_SEG(0x00011F0000008510ull)
-#define CVMX_PEXP_NPEI_DBG_SELECT \
- CVMX_ADD_IO_SEG(0x00011F0000008500ull)
-#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL \
- CVMX_ADD_IO_SEG(0x00011F00000085C0ull)
-#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL \
- CVMX_ADD_IO_SEG(0x00011F00000085D0ull)
-#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000008450ull + (((offset) & 7) * 16))
-#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) \
- CVMX_ADD_IO_SEG(0x00011F00000083B0ull + (((offset) & 7) * 16))
-#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000008400ull + (((offset) & 7) * 16))
-#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) \
- CVMX_ADD_IO_SEG(0x00011F00000084A0ull + (((offset) & 7) * 16))
-#define CVMX_PEXP_NPEI_DMA_CNTS \
- CVMX_ADD_IO_SEG(0x00011F00000085E0ull)
-#define CVMX_PEXP_NPEI_DMA_CONTROL \
- CVMX_ADD_IO_SEG(0x00011F00000083A0ull)
-#define CVMX_PEXP_NPEI_INT_A_ENB \
- CVMX_ADD_IO_SEG(0x00011F0000008560ull)
-#define CVMX_PEXP_NPEI_INT_A_ENB2 \
- CVMX_ADD_IO_SEG(0x00011F000000BCE0ull)
-#define CVMX_PEXP_NPEI_INT_A_SUM \
- CVMX_ADD_IO_SEG(0x00011F0000008550ull)
-#define CVMX_PEXP_NPEI_INT_ENB \
- CVMX_ADD_IO_SEG(0x00011F0000008540ull)
-#define CVMX_PEXP_NPEI_INT_ENB2 \
- CVMX_ADD_IO_SEG(0x00011F000000BCD0ull)
-#define CVMX_PEXP_NPEI_INT_INFO \
- CVMX_ADD_IO_SEG(0x00011F0000008590ull)
-#define CVMX_PEXP_NPEI_INT_SUM \
- CVMX_ADD_IO_SEG(0x00011F0000008530ull)
-#define CVMX_PEXP_NPEI_INT_SUM2 \
- CVMX_ADD_IO_SEG(0x00011F000000BCC0ull)
-#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 \
- CVMX_ADD_IO_SEG(0x00011F0000008600ull)
-#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 \
- CVMX_ADD_IO_SEG(0x00011F0000008610ull)
-#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL \
- CVMX_ADD_IO_SEG(0x00011F00000084F0ull)
-#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000008280ull + (((offset) & 31) * 16) - 16 * 12)
-#define CVMX_PEXP_NPEI_MSI_ENB0 \
- CVMX_ADD_IO_SEG(0x00011F000000BC50ull)
-#define CVMX_PEXP_NPEI_MSI_ENB1 \
- CVMX_ADD_IO_SEG(0x00011F000000BC60ull)
-#define CVMX_PEXP_NPEI_MSI_ENB2 \
- CVMX_ADD_IO_SEG(0x00011F000000BC70ull)
-#define CVMX_PEXP_NPEI_MSI_ENB3 \
- CVMX_ADD_IO_SEG(0x00011F000000BC80ull)
-#define CVMX_PEXP_NPEI_MSI_RCV0 \
- CVMX_ADD_IO_SEG(0x00011F000000BC10ull)
-#define CVMX_PEXP_NPEI_MSI_RCV1 \
- CVMX_ADD_IO_SEG(0x00011F000000BC20ull)
-#define CVMX_PEXP_NPEI_MSI_RCV2 \
- CVMX_ADD_IO_SEG(0x00011F000000BC30ull)
-#define CVMX_PEXP_NPEI_MSI_RCV3 \
- CVMX_ADD_IO_SEG(0x00011F000000BC40ull)
-#define CVMX_PEXP_NPEI_MSI_RD_MAP \
- CVMX_ADD_IO_SEG(0x00011F000000BCA0ull)
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 \
- CVMX_ADD_IO_SEG(0x00011F000000BCF0ull)
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 \
- CVMX_ADD_IO_SEG(0x00011F000000BD00ull)
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 \
- CVMX_ADD_IO_SEG(0x00011F000000BD10ull)
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 \
- CVMX_ADD_IO_SEG(0x00011F000000BD20ull)
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 \
- CVMX_ADD_IO_SEG(0x00011F000000BD30ull)
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 \
- CVMX_ADD_IO_SEG(0x00011F000000BD40ull)
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 \
- CVMX_ADD_IO_SEG(0x00011F000000BD50ull)
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 \
- CVMX_ADD_IO_SEG(0x00011F000000BD60ull)
-#define CVMX_PEXP_NPEI_MSI_WR_MAP \
- CVMX_ADD_IO_SEG(0x00011F000000BC90ull)
-#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT \
- CVMX_ADD_IO_SEG(0x00011F000000BD70ull)
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV \
- CVMX_ADD_IO_SEG(0x00011F000000BCB0ull)
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 \
- CVMX_ADD_IO_SEG(0x00011F0000008650ull)
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 \
- CVMX_ADD_IO_SEG(0x00011F0000008660ull)
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 \
- CVMX_ADD_IO_SEG(0x00011F0000008670ull)
-#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) \
- CVMX_ADD_IO_SEG(0x00011F000000A400ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) \
- CVMX_ADD_IO_SEG(0x00011F000000A800ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
- CVMX_ADD_IO_SEG(0x00011F000000AC00ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
- CVMX_ADD_IO_SEG(0x00011F000000B000ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) \
- CVMX_ADD_IO_SEG(0x00011F000000B400ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) \
- CVMX_ADD_IO_SEG(0x00011F000000B800ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000009400ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000009800ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000009C00ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKT_CNT_INT \
- CVMX_ADD_IO_SEG(0x00011F0000009110ull)
-#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB \
- CVMX_ADD_IO_SEG(0x00011F0000009130ull)
-#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES \
- CVMX_ADD_IO_SEG(0x00011F00000090B0ull)
-#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS \
- CVMX_ADD_IO_SEG(0x00011F00000090A0ull)
-#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR \
- CVMX_ADD_IO_SEG(0x00011F0000009090ull)
-#define CVMX_PEXP_NPEI_PKT_DPADDR \
- CVMX_ADD_IO_SEG(0x00011F0000009080ull)
-#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL \
- CVMX_ADD_IO_SEG(0x00011F0000009150ull)
-#define CVMX_PEXP_NPEI_PKT_INSTR_ENB \
- CVMX_ADD_IO_SEG(0x00011F0000009000ull)
-#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE \
- CVMX_ADD_IO_SEG(0x00011F0000009190ull)
-#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE \
- CVMX_ADD_IO_SEG(0x00011F0000009020ull)
-#define CVMX_PEXP_NPEI_PKT_INT_LEVELS \
- CVMX_ADD_IO_SEG(0x00011F0000009100ull)
-#define CVMX_PEXP_NPEI_PKT_IN_BP \
- CVMX_ADD_IO_SEG(0x00011F00000086B0ull)
-#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) \
- CVMX_ADD_IO_SEG(0x00011F000000A000ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS \
- CVMX_ADD_IO_SEG(0x00011F00000086A0ull)
-#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT \
- CVMX_ADD_IO_SEG(0x00011F00000091A0ull)
-#define CVMX_PEXP_NPEI_PKT_IPTR \
- CVMX_ADD_IO_SEG(0x00011F0000009070ull)
-#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK \
- CVMX_ADD_IO_SEG(0x00011F0000009160ull)
-#define CVMX_PEXP_NPEI_PKT_OUT_BMODE \
- CVMX_ADD_IO_SEG(0x00011F00000090D0ull)
-#define CVMX_PEXP_NPEI_PKT_OUT_ENB \
- CVMX_ADD_IO_SEG(0x00011F0000009010ull)
-#define CVMX_PEXP_NPEI_PKT_PCIE_PORT \
- CVMX_ADD_IO_SEG(0x00011F00000090E0ull)
-#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST \
- CVMX_ADD_IO_SEG(0x00011F0000008690ull)
-#define CVMX_PEXP_NPEI_PKT_SLIST_ES \
- CVMX_ADD_IO_SEG(0x00011F0000009050ull)
-#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE \
- CVMX_ADD_IO_SEG(0x00011F0000009180ull)
-#define CVMX_PEXP_NPEI_PKT_SLIST_NS \
- CVMX_ADD_IO_SEG(0x00011F0000009040ull)
-#define CVMX_PEXP_NPEI_PKT_SLIST_ROR \
- CVMX_ADD_IO_SEG(0x00011F0000009030ull)
-#define CVMX_PEXP_NPEI_PKT_TIME_INT \
- CVMX_ADD_IO_SEG(0x00011F0000009120ull)
-#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB \
- CVMX_ADD_IO_SEG(0x00011F0000009140ull)
-#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS \
- CVMX_ADD_IO_SEG(0x00011F0000008520ull)
-#define CVMX_PEXP_NPEI_SCRATCH_1 \
- CVMX_ADD_IO_SEG(0x00011F0000008270ull)
-#define CVMX_PEXP_NPEI_STATE1 \
- CVMX_ADD_IO_SEG(0x00011F0000008620ull)
-#define CVMX_PEXP_NPEI_STATE2 \
- CVMX_ADD_IO_SEG(0x00011F0000008630ull)
-#define CVMX_PEXP_NPEI_STATE3 \
- CVMX_ADD_IO_SEG(0x00011F0000008640ull)
-#define CVMX_PEXP_NPEI_WINDOW_CTL \
- CVMX_ADD_IO_SEG(0x00011F0000008380ull)
+#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
+#define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
+#define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
+#define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull))
+#define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull))
+#define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull))
+#define CVMX_PEXP_NPEI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000085F0ull))
+#define CVMX_PEXP_NPEI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000008510ull))
+#define CVMX_PEXP_NPEI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000008500ull))
+#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085C0ull))
+#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085D0ull))
+#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMA_CNTS (CVMX_ADD_IO_SEG(0x00011F00000085E0ull))
+#define CVMX_PEXP_NPEI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000083A0ull))
+#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM (CVMX_ADD_IO_SEG(0x00011F00000085B0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE1_P1 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
+#define CVMX_PEXP_NPEI_DMA_STATE2 (CVMX_ADD_IO_SEG(0x00011F00000086D0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE2_P1 (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
+#define CVMX_PEXP_NPEI_DMA_STATE3_P1 (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE4_P1 (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE5_P1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
+#define CVMX_PEXP_NPEI_INT_A_ENB (CVMX_ADD_IO_SEG(0x00011F0000008560ull))
+#define CVMX_PEXP_NPEI_INT_A_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCE0ull))
+#define CVMX_PEXP_NPEI_INT_A_SUM (CVMX_ADD_IO_SEG(0x00011F0000008550ull))
+#define CVMX_PEXP_NPEI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000008540ull))
+#define CVMX_PEXP_NPEI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCD0ull))
+#define CVMX_PEXP_NPEI_INT_INFO (CVMX_ADD_IO_SEG(0x00011F0000008590ull))
+#define CVMX_PEXP_NPEI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000008530ull))
+#define CVMX_PEXP_NPEI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F000000BCC0ull))
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000008600ull))
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000008610ull))
+#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000084F0ull))
+#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12)
+#define CVMX_PEXP_NPEI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BC50ull))
+#define CVMX_PEXP_NPEI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BC60ull))
+#define CVMX_PEXP_NPEI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BC70ull))
+#define CVMX_PEXP_NPEI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BC80ull))
+#define CVMX_PEXP_NPEI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F000000BC10ull))
+#define CVMX_PEXP_NPEI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F000000BC20ull))
+#define CVMX_PEXP_NPEI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F000000BC30ull))
+#define CVMX_PEXP_NPEI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F000000BC40ull))
+#define CVMX_PEXP_NPEI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F000000BCA0ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BCF0ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD00ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD10ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD20ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BD30ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD40ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD50ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD60ull))
+#define CVMX_PEXP_NPEI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F000000BC90ull))
+#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F000000BD70ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F000000BCB0ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000008650ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000008660ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000008670ull))
+#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000009110ull))
+#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009130ull))
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000090B0ull))
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000090A0ull))
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000009090ull))
+#define CVMX_PEXP_NPEI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000009080ull))
+#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000009150ull))
+#define CVMX_PEXP_NPEI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000009000ull))
+#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009190ull))
+#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009020ull))
+#define CVMX_PEXP_NPEI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000009100ull))
+#define CVMX_PEXP_NPEI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
+#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
+#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000091A0ull))
+#define CVMX_PEXP_NPEI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000009070ull))
+#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000009160ull))
+#define CVMX_PEXP_NPEI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000090D0ull))
+#define CVMX_PEXP_NPEI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009010ull))
+#define CVMX_PEXP_NPEI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000090E0ull))
+#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000009050ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009180ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000009040ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000009030ull))
+#define CVMX_PEXP_NPEI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000009120ull))
+#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009140ull))
+#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000008520ull))
+#define CVMX_PEXP_NPEI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F0000008270ull))
+#define CVMX_PEXP_NPEI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000008620ull))
+#define CVMX_PEXP_NPEI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000008630ull))
+#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
+#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
+#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
+#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
+#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
+#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
+#define CVMX_PEXP_SLI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000010300ull))
+#define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_DMAX_INT_LEVEL(offset) (CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_INT_ENB_CIU (CVMX_ADD_IO_SEG(0x00011F0000013CD0ull))
+#define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
+#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
+#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
+#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
+#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
+#define CVMX_PEXP_SLI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013C60ull))
+#define CVMX_PEXP_SLI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013C70ull))
+#define CVMX_PEXP_SLI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013C80ull))
+#define CVMX_PEXP_SLI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F0000013C10ull))
+#define CVMX_PEXP_SLI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F0000013C20ull))
+#define CVMX_PEXP_SLI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F0000013C30ull))
+#define CVMX_PEXP_SLI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F0000013C40ull))
+#define CVMX_PEXP_SLI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F0000013CA0ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013CF0ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D00ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D10ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D20ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013D30ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D40ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D50ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D60ull))
+#define CVMX_PEXP_SLI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F0000013C90ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000013CB0ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000010650ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000010660ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000010670ull))
+#define CVMX_PEXP_SLI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_OUT_SIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000011130ull))
+#define CVMX_PEXP_SLI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011150ull))
+#define CVMX_PEXP_SLI_PKT_CTL (CVMX_ADD_IO_SEG(0x00011F0000011220ull))
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000110B0ull))
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000110A0ull))
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000011090ull))
+#define CVMX_PEXP_SLI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000011080ull))
+#define CVMX_PEXP_SLI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000011170ull))
+#define CVMX_PEXP_SLI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000011000ull))
+#define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F00000111A0ull))
+#define CVMX_PEXP_SLI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000011020ull))
+#define CVMX_PEXP_SLI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000011120ull))
+#define CVMX_PEXP_SLI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F0000011210ull))
+#define CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000011200ull))
+#define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000111B0ull))
+#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
+#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
+#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
+#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
+#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
+#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
+#define CVMX_PEXP_SLI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000011050ull))
+#define CVMX_PEXP_SLI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000011040ull))
+#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
+#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
+#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
+#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
+#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
+#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
+#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
+#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
+#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
#endif
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-pow-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-pow-defs.h
index 2d82e24be51c..39fd75b03f77 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-pow-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-pow-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,52 +28,29 @@
#ifndef __CVMX_POW_DEFS_H__
#define __CVMX_POW_DEFS_H__
-#define CVMX_POW_BIST_STAT \
- CVMX_ADD_IO_SEG(0x00016700000003F8ull)
-#define CVMX_POW_DS_PC \
- CVMX_ADD_IO_SEG(0x0001670000000398ull)
-#define CVMX_POW_ECC_ERR \
- CVMX_ADD_IO_SEG(0x0001670000000218ull)
-#define CVMX_POW_INT_CTL \
- CVMX_ADD_IO_SEG(0x0001670000000220ull)
-#define CVMX_POW_IQ_CNTX(offset) \
- CVMX_ADD_IO_SEG(0x0001670000000340ull + (((offset) & 7) * 8))
-#define CVMX_POW_IQ_COM_CNT \
- CVMX_ADD_IO_SEG(0x0001670000000388ull)
-#define CVMX_POW_IQ_INT \
- CVMX_ADD_IO_SEG(0x0001670000000238ull)
-#define CVMX_POW_IQ_INT_EN \
- CVMX_ADD_IO_SEG(0x0001670000000240ull)
-#define CVMX_POW_IQ_THRX(offset) \
- CVMX_ADD_IO_SEG(0x00016700000003A0ull + (((offset) & 7) * 8))
-#define CVMX_POW_NOS_CNT \
- CVMX_ADD_IO_SEG(0x0001670000000228ull)
-#define CVMX_POW_NW_TIM \
- CVMX_ADD_IO_SEG(0x0001670000000210ull)
-#define CVMX_POW_PF_RST_MSK \
- CVMX_ADD_IO_SEG(0x0001670000000230ull)
-#define CVMX_POW_PP_GRP_MSKX(offset) \
- CVMX_ADD_IO_SEG(0x0001670000000000ull + (((offset) & 15) * 8))
-#define CVMX_POW_QOS_RNDX(offset) \
- CVMX_ADD_IO_SEG(0x00016700000001C0ull + (((offset) & 7) * 8))
-#define CVMX_POW_QOS_THRX(offset) \
- CVMX_ADD_IO_SEG(0x0001670000000180ull + (((offset) & 7) * 8))
-#define CVMX_POW_TS_PC \
- CVMX_ADD_IO_SEG(0x0001670000000390ull)
-#define CVMX_POW_WA_COM_PC \
- CVMX_ADD_IO_SEG(0x0001670000000380ull)
-#define CVMX_POW_WA_PCX(offset) \
- CVMX_ADD_IO_SEG(0x0001670000000300ull + (((offset) & 7) * 8))
-#define CVMX_POW_WQ_INT \
- CVMX_ADD_IO_SEG(0x0001670000000200ull)
-#define CVMX_POW_WQ_INT_CNTX(offset) \
- CVMX_ADD_IO_SEG(0x0001670000000100ull + (((offset) & 15) * 8))
-#define CVMX_POW_WQ_INT_PC \
- CVMX_ADD_IO_SEG(0x0001670000000208ull)
-#define CVMX_POW_WQ_INT_THRX(offset) \
- CVMX_ADD_IO_SEG(0x0001670000000080ull + (((offset) & 15) * 8))
-#define CVMX_POW_WS_PCX(offset) \
- CVMX_ADD_IO_SEG(0x0001670000000280ull + (((offset) & 15) * 8))
+#define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull))
+#define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull))
+#define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull))
+#define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull))
+#define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8)
+#define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull))
+#define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull))
+#define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull))
+#define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8)
+#define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull))
+#define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull))
+#define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull))
+#define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8)
+#define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8)
+#define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8)
+#define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull))
+#define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull))
+#define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8)
+#define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull))
+#define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8)
+#define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull))
+#define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8)
+#define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8)
union cvmx_pow_bist_stat {
uint64_t u64;
@@ -160,6 +137,19 @@ union cvmx_pow_bist_stat {
struct cvmx_pow_bist_stat_cn56xx cn56xxp1;
struct cvmx_pow_bist_stat_cn38xx cn58xx;
struct cvmx_pow_bist_stat_cn38xx cn58xxp1;
+ struct cvmx_pow_bist_stat_cn63xx {
+ uint64_t reserved_22_63:42;
+ uint64_t pp:6;
+ uint64_t reserved_12_15:4;
+ uint64_t cam:1;
+ uint64_t nbr:3;
+ uint64_t nbt:4;
+ uint64_t index:1;
+ uint64_t fidx:1;
+ uint64_t pend:1;
+ uint64_t adr:1;
+ } cn63xx;
+ struct cvmx_pow_bist_stat_cn63xx cn63xxp1;
};
union cvmx_pow_ds_pc {
@@ -179,6 +169,8 @@ union cvmx_pow_ds_pc {
struct cvmx_pow_ds_pc_s cn56xxp1;
struct cvmx_pow_ds_pc_s cn58xx;
struct cvmx_pow_ds_pc_s cn58xxp1;
+ struct cvmx_pow_ds_pc_s cn63xx;
+ struct cvmx_pow_ds_pc_s cn63xxp1;
};
union cvmx_pow_ecc_err {
@@ -219,6 +211,8 @@ union cvmx_pow_ecc_err {
struct cvmx_pow_ecc_err_s cn56xxp1;
struct cvmx_pow_ecc_err_s cn58xx;
struct cvmx_pow_ecc_err_s cn58xxp1;
+ struct cvmx_pow_ecc_err_s cn63xx;
+ struct cvmx_pow_ecc_err_s cn63xxp1;
};
union cvmx_pow_int_ctl {
@@ -239,6 +233,8 @@ union cvmx_pow_int_ctl {
struct cvmx_pow_int_ctl_s cn56xxp1;
struct cvmx_pow_int_ctl_s cn58xx;
struct cvmx_pow_int_ctl_s cn58xxp1;
+ struct cvmx_pow_int_ctl_s cn63xx;
+ struct cvmx_pow_int_ctl_s cn63xxp1;
};
union cvmx_pow_iq_cntx {
@@ -258,6 +254,8 @@ union cvmx_pow_iq_cntx {
struct cvmx_pow_iq_cntx_s cn56xxp1;
struct cvmx_pow_iq_cntx_s cn58xx;
struct cvmx_pow_iq_cntx_s cn58xxp1;
+ struct cvmx_pow_iq_cntx_s cn63xx;
+ struct cvmx_pow_iq_cntx_s cn63xxp1;
};
union cvmx_pow_iq_com_cnt {
@@ -277,6 +275,8 @@ union cvmx_pow_iq_com_cnt {
struct cvmx_pow_iq_com_cnt_s cn56xxp1;
struct cvmx_pow_iq_com_cnt_s cn58xx;
struct cvmx_pow_iq_com_cnt_s cn58xxp1;
+ struct cvmx_pow_iq_com_cnt_s cn63xx;
+ struct cvmx_pow_iq_com_cnt_s cn63xxp1;
};
union cvmx_pow_iq_int {
@@ -289,6 +289,8 @@ union cvmx_pow_iq_int {
struct cvmx_pow_iq_int_s cn52xxp1;
struct cvmx_pow_iq_int_s cn56xx;
struct cvmx_pow_iq_int_s cn56xxp1;
+ struct cvmx_pow_iq_int_s cn63xx;
+ struct cvmx_pow_iq_int_s cn63xxp1;
};
union cvmx_pow_iq_int_en {
@@ -301,6 +303,8 @@ union cvmx_pow_iq_int_en {
struct cvmx_pow_iq_int_en_s cn52xxp1;
struct cvmx_pow_iq_int_en_s cn56xx;
struct cvmx_pow_iq_int_en_s cn56xxp1;
+ struct cvmx_pow_iq_int_en_s cn63xx;
+ struct cvmx_pow_iq_int_en_s cn63xxp1;
};
union cvmx_pow_iq_thrx {
@@ -313,6 +317,8 @@ union cvmx_pow_iq_thrx {
struct cvmx_pow_iq_thrx_s cn52xxp1;
struct cvmx_pow_iq_thrx_s cn56xx;
struct cvmx_pow_iq_thrx_s cn56xxp1;
+ struct cvmx_pow_iq_thrx_s cn63xx;
+ struct cvmx_pow_iq_thrx_s cn63xxp1;
};
union cvmx_pow_nos_cnt {
@@ -341,6 +347,11 @@ union cvmx_pow_nos_cnt {
struct cvmx_pow_nos_cnt_s cn56xxp1;
struct cvmx_pow_nos_cnt_s cn58xx;
struct cvmx_pow_nos_cnt_s cn58xxp1;
+ struct cvmx_pow_nos_cnt_cn63xx {
+ uint64_t reserved_11_63:53;
+ uint64_t nos_cnt:11;
+ } cn63xx;
+ struct cvmx_pow_nos_cnt_cn63xx cn63xxp1;
};
union cvmx_pow_nw_tim {
@@ -360,6 +371,8 @@ union cvmx_pow_nw_tim {
struct cvmx_pow_nw_tim_s cn56xxp1;
struct cvmx_pow_nw_tim_s cn58xx;
struct cvmx_pow_nw_tim_s cn58xxp1;
+ struct cvmx_pow_nw_tim_s cn63xx;
+ struct cvmx_pow_nw_tim_s cn63xxp1;
};
union cvmx_pow_pf_rst_msk {
@@ -375,6 +388,8 @@ union cvmx_pow_pf_rst_msk {
struct cvmx_pow_pf_rst_msk_s cn56xxp1;
struct cvmx_pow_pf_rst_msk_s cn58xx;
struct cvmx_pow_pf_rst_msk_s cn58xxp1;
+ struct cvmx_pow_pf_rst_msk_s cn63xx;
+ struct cvmx_pow_pf_rst_msk_s cn63xxp1;
};
union cvmx_pow_pp_grp_mskx {
@@ -405,6 +420,8 @@ union cvmx_pow_pp_grp_mskx {
struct cvmx_pow_pp_grp_mskx_s cn56xxp1;
struct cvmx_pow_pp_grp_mskx_s cn58xx;
struct cvmx_pow_pp_grp_mskx_s cn58xxp1;
+ struct cvmx_pow_pp_grp_mskx_s cn63xx;
+ struct cvmx_pow_pp_grp_mskx_s cn63xxp1;
};
union cvmx_pow_qos_rndx {
@@ -427,6 +444,8 @@ union cvmx_pow_qos_rndx {
struct cvmx_pow_qos_rndx_s cn56xxp1;
struct cvmx_pow_qos_rndx_s cn58xx;
struct cvmx_pow_qos_rndx_s cn58xxp1;
+ struct cvmx_pow_qos_rndx_s cn63xx;
+ struct cvmx_pow_qos_rndx_s cn63xxp1;
};
union cvmx_pow_qos_thrx {
@@ -485,6 +504,19 @@ union cvmx_pow_qos_thrx {
struct cvmx_pow_qos_thrx_s cn56xxp1;
struct cvmx_pow_qos_thrx_s cn58xx;
struct cvmx_pow_qos_thrx_s cn58xxp1;
+ struct cvmx_pow_qos_thrx_cn63xx {
+ uint64_t reserved_59_63:5;
+ uint64_t des_cnt:11;
+ uint64_t reserved_47_47:1;
+ uint64_t buf_cnt:11;
+ uint64_t reserved_35_35:1;
+ uint64_t free_cnt:11;
+ uint64_t reserved_22_23:2;
+ uint64_t max_thr:10;
+ uint64_t reserved_10_11:2;
+ uint64_t min_thr:10;
+ } cn63xx;
+ struct cvmx_pow_qos_thrx_cn63xx cn63xxp1;
};
union cvmx_pow_ts_pc {
@@ -504,6 +536,8 @@ union cvmx_pow_ts_pc {
struct cvmx_pow_ts_pc_s cn56xxp1;
struct cvmx_pow_ts_pc_s cn58xx;
struct cvmx_pow_ts_pc_s cn58xxp1;
+ struct cvmx_pow_ts_pc_s cn63xx;
+ struct cvmx_pow_ts_pc_s cn63xxp1;
};
union cvmx_pow_wa_com_pc {
@@ -523,6 +557,8 @@ union cvmx_pow_wa_com_pc {
struct cvmx_pow_wa_com_pc_s cn56xxp1;
struct cvmx_pow_wa_com_pc_s cn58xx;
struct cvmx_pow_wa_com_pc_s cn58xxp1;
+ struct cvmx_pow_wa_com_pc_s cn63xx;
+ struct cvmx_pow_wa_com_pc_s cn63xxp1;
};
union cvmx_pow_wa_pcx {
@@ -542,6 +578,8 @@ union cvmx_pow_wa_pcx {
struct cvmx_pow_wa_pcx_s cn56xxp1;
struct cvmx_pow_wa_pcx_s cn58xx;
struct cvmx_pow_wa_pcx_s cn58xxp1;
+ struct cvmx_pow_wa_pcx_s cn63xx;
+ struct cvmx_pow_wa_pcx_s cn63xxp1;
};
union cvmx_pow_wq_int {
@@ -562,6 +600,8 @@ union cvmx_pow_wq_int {
struct cvmx_pow_wq_int_s cn56xxp1;
struct cvmx_pow_wq_int_s cn58xx;
struct cvmx_pow_wq_int_s cn58xxp1;
+ struct cvmx_pow_wq_int_s cn63xx;
+ struct cvmx_pow_wq_int_s cn63xxp1;
};
union cvmx_pow_wq_int_cntx {
@@ -604,6 +644,15 @@ union cvmx_pow_wq_int_cntx {
struct cvmx_pow_wq_int_cntx_s cn56xxp1;
struct cvmx_pow_wq_int_cntx_s cn58xx;
struct cvmx_pow_wq_int_cntx_s cn58xxp1;
+ struct cvmx_pow_wq_int_cntx_cn63xx {
+ uint64_t reserved_28_63:36;
+ uint64_t tc_cnt:4;
+ uint64_t reserved_23_23:1;
+ uint64_t ds_cnt:11;
+ uint64_t reserved_11_11:1;
+ uint64_t iq_cnt:11;
+ } cn63xx;
+ struct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1;
};
union cvmx_pow_wq_int_pc {
@@ -626,6 +675,8 @@ union cvmx_pow_wq_int_pc {
struct cvmx_pow_wq_int_pc_s cn56xxp1;
struct cvmx_pow_wq_int_pc_s cn58xx;
struct cvmx_pow_wq_int_pc_s cn58xxp1;
+ struct cvmx_pow_wq_int_pc_s cn63xx;
+ struct cvmx_pow_wq_int_pc_s cn63xxp1;
};
union cvmx_pow_wq_int_thrx {
@@ -674,6 +725,16 @@ union cvmx_pow_wq_int_thrx {
struct cvmx_pow_wq_int_thrx_s cn56xxp1;
struct cvmx_pow_wq_int_thrx_s cn58xx;
struct cvmx_pow_wq_int_thrx_s cn58xxp1;
+ struct cvmx_pow_wq_int_thrx_cn63xx {
+ uint64_t reserved_29_63:35;
+ uint64_t tc_en:1;
+ uint64_t tc_thr:4;
+ uint64_t reserved_22_23:2;
+ uint64_t ds_thr:10;
+ uint64_t reserved_10_11:2;
+ uint64_t iq_thr:10;
+ } cn63xx;
+ struct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1;
};
union cvmx_pow_ws_pcx {
@@ -693,6 +754,8 @@ union cvmx_pow_ws_pcx {
struct cvmx_pow_ws_pcx_s cn56xxp1;
struct cvmx_pow_ws_pcx_s cn58xx;
struct cvmx_pow_ws_pcx_s cn58xxp1;
+ struct cvmx_pow_ws_pcx_s cn63xx;
+ struct cvmx_pow_ws_pcx_s cn63xxp1;
};
#endif
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-rnm-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
index 4586958c97be..c45da1f35ea7 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -30,10 +30,11 @@
#include
-#define CVMX_RNM_BIST_STATUS \
- CVMX_ADD_IO_SEG(0x0001180040000008ull)
-#define CVMX_RNM_CTL_STATUS \
- CVMX_ADD_IO_SEG(0x0001180040000000ull)
+#define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull))
+#define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull))
+#define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull))
+#define CVMX_RNM_EER_KEY (CVMX_ADD_IO_SEG(0x0001180040000010ull))
+#define CVMX_RNM_SERIAL_NUM (CVMX_ADD_IO_SEG(0x0001180040000020ull))
union cvmx_rnm_bist_status {
uint64_t u64;
@@ -53,12 +54,16 @@ union cvmx_rnm_bist_status {
struct cvmx_rnm_bist_status_s cn56xxp1;
struct cvmx_rnm_bist_status_s cn58xx;
struct cvmx_rnm_bist_status_s cn58xxp1;
+ struct cvmx_rnm_bist_status_s cn63xx;
+ struct cvmx_rnm_bist_status_s cn63xxp1;
};
union cvmx_rnm_ctl_status {
uint64_t u64;
struct cvmx_rnm_ctl_status_s {
- uint64_t reserved_9_63:55;
+ uint64_t reserved_11_63:53;
+ uint64_t eer_lck:1;
+ uint64_t eer_val:1;
uint64_t ent_sel:4;
uint64_t exp_ent:1;
uint64_t rng_rst:1;
@@ -76,13 +81,49 @@ union cvmx_rnm_ctl_status {
struct cvmx_rnm_ctl_status_cn30xx cn31xx;
struct cvmx_rnm_ctl_status_cn30xx cn38xx;
struct cvmx_rnm_ctl_status_cn30xx cn38xxp2;
- struct cvmx_rnm_ctl_status_s cn50xx;
- struct cvmx_rnm_ctl_status_s cn52xx;
- struct cvmx_rnm_ctl_status_s cn52xxp1;
- struct cvmx_rnm_ctl_status_s cn56xx;
- struct cvmx_rnm_ctl_status_s cn56xxp1;
- struct cvmx_rnm_ctl_status_s cn58xx;
- struct cvmx_rnm_ctl_status_s cn58xxp1;
+ struct cvmx_rnm_ctl_status_cn50xx {
+ uint64_t reserved_9_63:55;
+ uint64_t ent_sel:4;
+ uint64_t exp_ent:1;
+ uint64_t rng_rst:1;
+ uint64_t rnm_rst:1;
+ uint64_t rng_en:1;
+ uint64_t ent_en:1;
+ } cn50xx;
+ struct cvmx_rnm_ctl_status_cn50xx cn52xx;
+ struct cvmx_rnm_ctl_status_cn50xx cn52xxp1;
+ struct cvmx_rnm_ctl_status_cn50xx cn56xx;
+ struct cvmx_rnm_ctl_status_cn50xx cn56xxp1;
+ struct cvmx_rnm_ctl_status_cn50xx cn58xx;
+ struct cvmx_rnm_ctl_status_cn50xx cn58xxp1;
+ struct cvmx_rnm_ctl_status_s cn63xx;
+ struct cvmx_rnm_ctl_status_s cn63xxp1;
+};
+
+union cvmx_rnm_eer_dbg {
+ uint64_t u64;
+ struct cvmx_rnm_eer_dbg_s {
+ uint64_t dat:64;
+ } s;
+ struct cvmx_rnm_eer_dbg_s cn63xx;
+ struct cvmx_rnm_eer_dbg_s cn63xxp1;
+};
+
+union cvmx_rnm_eer_key {
+ uint64_t u64;
+ struct cvmx_rnm_eer_key_s {
+ uint64_t key:64;
+ } s;
+ struct cvmx_rnm_eer_key_s cn63xx;
+ struct cvmx_rnm_eer_key_s cn63xxp1;
+};
+
+union cvmx_rnm_serial_num {
+ uint64_t u64;
+ struct cvmx_rnm_serial_num_s {
+ uint64_t dat:64;
+ } s;
+ struct cvmx_rnm_serial_num_s cn63xx;
};
#endif
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-smix-defs.h
index 9ae45fcbe3e3..4f3c0666e94a 100644
--- a/trunk/arch/mips/include/asm/octeon/cvmx-smix-defs.h
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-smix-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -28,16 +28,11 @@
#ifndef __CVMX_SMIX_DEFS_H__
#define __CVMX_SMIX_DEFS_H__
-#define CVMX_SMIX_CLK(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_CMD(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_EN(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_RD_DAT(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_WR_DAT(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
+#define CVMX_SMIX_CLK(offset) (CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_CMD(offset) (CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_EN(offset) (CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_RD_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_WR_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256)
union cvmx_smix_clk {
uint64_t u64;
@@ -56,7 +51,8 @@ union cvmx_smix_clk {
struct cvmx_smix_clk_cn30xx {
uint64_t reserved_21_63:43;
uint64_t sample_hi:5;
- uint64_t reserved_14_15:2;
+ uint64_t sample_mode:1;
+ uint64_t reserved_14_14:1;
uint64_t clk_idle:1;
uint64_t preamble:1;
uint64_t sample:4;
@@ -65,23 +61,15 @@ union cvmx_smix_clk {
struct cvmx_smix_clk_cn30xx cn31xx;
struct cvmx_smix_clk_cn30xx cn38xx;
struct cvmx_smix_clk_cn30xx cn38xxp2;
- struct cvmx_smix_clk_cn50xx {
- uint64_t reserved_25_63:39;
- uint64_t mode:1;
- uint64_t reserved_21_23:3;
- uint64_t sample_hi:5;
- uint64_t reserved_14_15:2;
- uint64_t clk_idle:1;
- uint64_t preamble:1;
- uint64_t sample:4;
- uint64_t phase:8;
- } cn50xx;
+ struct cvmx_smix_clk_s cn50xx;
struct cvmx_smix_clk_s cn52xx;
- struct cvmx_smix_clk_cn50xx cn52xxp1;
+ struct cvmx_smix_clk_s cn52xxp1;
struct cvmx_smix_clk_s cn56xx;
- struct cvmx_smix_clk_cn50xx cn56xxp1;
+ struct cvmx_smix_clk_s cn56xxp1;
struct cvmx_smix_clk_cn30xx cn58xx;
struct cvmx_smix_clk_cn30xx cn58xxp1;
+ struct cvmx_smix_clk_s cn63xx;
+ struct cvmx_smix_clk_s cn63xxp1;
};
union cvmx_smix_cmd {
@@ -112,6 +100,8 @@ union cvmx_smix_cmd {
struct cvmx_smix_cmd_s cn56xxp1;
struct cvmx_smix_cmd_cn30xx cn58xx;
struct cvmx_smix_cmd_cn30xx cn58xxp1;
+ struct cvmx_smix_cmd_s cn63xx;
+ struct cvmx_smix_cmd_s cn63xxp1;
};
union cvmx_smix_en {
@@ -131,6 +121,8 @@ union cvmx_smix_en {
struct cvmx_smix_en_s cn56xxp1;
struct cvmx_smix_en_s cn58xx;
struct cvmx_smix_en_s cn58xxp1;
+ struct cvmx_smix_en_s cn63xx;
+ struct cvmx_smix_en_s cn63xxp1;
};
union cvmx_smix_rd_dat {
@@ -152,6 +144,8 @@ union cvmx_smix_rd_dat {
struct cvmx_smix_rd_dat_s cn56xxp1;
struct cvmx_smix_rd_dat_s cn58xx;
struct cvmx_smix_rd_dat_s cn58xxp1;
+ struct cvmx_smix_rd_dat_s cn63xx;
+ struct cvmx_smix_rd_dat_s cn63xxp1;
};
union cvmx_smix_wr_dat {
@@ -173,6 +167,8 @@ union cvmx_smix_wr_dat {
struct cvmx_smix_wr_dat_s cn56xxp1;
struct cvmx_smix_wr_dat_s cn58xx;
struct cvmx_smix_wr_dat_s cn58xxp1;
+ struct cvmx_smix_wr_dat_s cn63xx;
+ struct cvmx_smix_wr_dat_s cn63xxp1;
};
#endif
diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
new file mode 100644
index 000000000000..594f1b68cd62
--- /dev/null
+++ b/trunk/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
@@ -0,0 +1,261 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2010 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT. See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_UCTLX_TYPEDEFS_H__
+#define __CVMX_UCTLX_TYPEDEFS_H__
+
+#define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
+#define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
+#define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull))
+#define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull))
+#define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull))
+#define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull))
+#define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull))
+#define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull))
+#define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull))
+#define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull))
+#define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull))
+#define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull))
+#define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
+
+union cvmx_uctlx_bist_status {
+ uint64_t u64;
+ struct cvmx_uctlx_bist_status_s {
+ uint64_t reserved_6_63:58;
+ uint64_t data_bis:1;
+ uint64_t desc_bis:1;
+ uint64_t erbm_bis:1;
+ uint64_t orbm_bis:1;
+ uint64_t wrbm_bis:1;
+ uint64_t ppaf_bis:1;
+ } s;
+ struct cvmx_uctlx_bist_status_s cn63xx;
+ struct cvmx_uctlx_bist_status_s cn63xxp1;
+};
+
+union cvmx_uctlx_clk_rst_ctl {
+ uint64_t u64;
+ struct cvmx_uctlx_clk_rst_ctl_s {
+ uint64_t reserved_25_63:39;
+ uint64_t clear_bist:1;
+ uint64_t start_bist:1;
+ uint64_t ehci_sm:1;
+ uint64_t ohci_clkcktrst:1;
+ uint64_t ohci_sm:1;
+ uint64_t ohci_susp_lgcy:1;
+ uint64_t app_start_clk:1;
+ uint64_t o_clkdiv_rst:1;
+ uint64_t h_clkdiv_byp:1;
+ uint64_t h_clkdiv_rst:1;
+ uint64_t h_clkdiv_en:1;
+ uint64_t o_clkdiv_en:1;
+ uint64_t h_div:4;
+ uint64_t p_refclk_sel:2;
+ uint64_t p_refclk_div:2;
+ uint64_t reserved_4_4:1;
+ uint64_t p_com_on:1;
+ uint64_t p_por:1;
+ uint64_t p_prst:1;
+ uint64_t hrst:1;
+ } s;
+ struct cvmx_uctlx_clk_rst_ctl_s cn63xx;
+ struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1;
+};
+
+union cvmx_uctlx_ehci_ctl {
+ uint64_t u64;
+ struct cvmx_uctlx_ehci_ctl_s {
+ uint64_t reserved_20_63:44;
+ uint64_t desc_rbm:1;
+ uint64_t reg_nb:1;
+ uint64_t l2c_dc:1;
+ uint64_t l2c_bc:1;
+ uint64_t l2c_0pag:1;
+ uint64_t l2c_stt:1;
+ uint64_t l2c_buff_emod:2;
+ uint64_t l2c_desc_emod:2;
+ uint64_t inv_reg_a2:1;
+ uint64_t ehci_64b_addr_en:1;
+ uint64_t l2c_addr_msb:8;
+ } s;
+ struct cvmx_uctlx_ehci_ctl_s cn63xx;
+ struct cvmx_uctlx_ehci_ctl_s cn63xxp1;
+};
+
+union cvmx_uctlx_ehci_fla {
+ uint64_t u64;
+ struct cvmx_uctlx_ehci_fla_s {
+ uint64_t reserved_6_63:58;
+ uint64_t fla:6;
+ } s;
+ struct cvmx_uctlx_ehci_fla_s cn63xx;
+ struct cvmx_uctlx_ehci_fla_s cn63xxp1;
+};
+
+union cvmx_uctlx_erto_ctl {
+ uint64_t u64;
+ struct cvmx_uctlx_erto_ctl_s {
+ uint64_t reserved_32_63:32;
+ uint64_t to_val:27;
+ uint64_t reserved_0_4:5;
+ } s;
+ struct cvmx_uctlx_erto_ctl_s cn63xx;
+ struct cvmx_uctlx_erto_ctl_s cn63xxp1;
+};
+
+union cvmx_uctlx_if_ena {
+ uint64_t u64;
+ struct cvmx_uctlx_if_ena_s {
+ uint64_t reserved_1_63:63;
+ uint64_t en:1;
+ } s;
+ struct cvmx_uctlx_if_ena_s cn63xx;
+ struct cvmx_uctlx_if_ena_s cn63xxp1;
+};
+
+union cvmx_uctlx_int_ena {
+ uint64_t u64;
+ struct cvmx_uctlx_int_ena_s {
+ uint64_t reserved_8_63:56;
+ uint64_t ec_ovf_e:1;
+ uint64_t oc_ovf_e:1;
+ uint64_t wb_pop_e:1;
+ uint64_t wb_psh_f:1;
+ uint64_t cf_psh_f:1;
+ uint64_t or_psh_f:1;
+ uint64_t er_psh_f:1;
+ uint64_t pp_psh_f:1;
+ } s;
+ struct cvmx_uctlx_int_ena_s cn63xx;
+ struct cvmx_uctlx_int_ena_s cn63xxp1;
+};
+
+union cvmx_uctlx_int_reg {
+ uint64_t u64;
+ struct cvmx_uctlx_int_reg_s {
+ uint64_t reserved_8_63:56;
+ uint64_t ec_ovf_e:1;
+ uint64_t oc_ovf_e:1;
+ uint64_t wb_pop_e:1;
+ uint64_t wb_psh_f:1;
+ uint64_t cf_psh_f:1;
+ uint64_t or_psh_f:1;
+ uint64_t er_psh_f:1;
+ uint64_t pp_psh_f:1;
+ } s;
+ struct cvmx_uctlx_int_reg_s cn63xx;
+ struct cvmx_uctlx_int_reg_s cn63xxp1;
+};
+
+union cvmx_uctlx_ohci_ctl {
+ uint64_t u64;
+ struct cvmx_uctlx_ohci_ctl_s {
+ uint64_t reserved_19_63:45;
+ uint64_t reg_nb:1;
+ uint64_t l2c_dc:1;
+ uint64_t l2c_bc:1;
+ uint64_t l2c_0pag:1;
+ uint64_t l2c_stt:1;
+ uint64_t l2c_buff_emod:2;
+ uint64_t l2c_desc_emod:2;
+ uint64_t inv_reg_a2:1;
+ uint64_t reserved_8_8:1;
+ uint64_t l2c_addr_msb:8;
+ } s;
+ struct cvmx_uctlx_ohci_ctl_s cn63xx;
+ struct cvmx_uctlx_ohci_ctl_s cn63xxp1;
+};
+
+union cvmx_uctlx_orto_ctl {
+ uint64_t u64;
+ struct cvmx_uctlx_orto_ctl_s {
+ uint64_t reserved_32_63:32;
+ uint64_t to_val:24;
+ uint64_t reserved_0_7:8;
+ } s;
+ struct cvmx_uctlx_orto_ctl_s cn63xx;
+ struct cvmx_uctlx_orto_ctl_s cn63xxp1;
+};
+
+union cvmx_uctlx_ppaf_wm {
+ uint64_t u64;
+ struct cvmx_uctlx_ppaf_wm_s {
+ uint64_t reserved_5_63:59;
+ uint64_t wm:5;
+ } s;
+ struct cvmx_uctlx_ppaf_wm_s cn63xx;
+ struct cvmx_uctlx_ppaf_wm_s cn63xxp1;
+};
+
+union cvmx_uctlx_uphy_ctl_status {
+ uint64_t u64;
+ struct cvmx_uctlx_uphy_ctl_status_s {
+ uint64_t reserved_10_63:54;
+ uint64_t bist_done:1;
+ uint64_t bist_err:1;
+ uint64_t hsbist:1;
+ uint64_t fsbist:1;
+ uint64_t lsbist:1;
+ uint64_t siddq:1;
+ uint64_t vtest_en:1;
+ uint64_t uphy_bist:1;
+ uint64_t bist_en:1;
+ uint64_t ate_reset:1;
+ } s;
+ struct cvmx_uctlx_uphy_ctl_status_s cn63xx;
+ struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1;
+};
+
+union cvmx_uctlx_uphy_portx_ctl_status {
+ uint64_t u64;
+ struct cvmx_uctlx_uphy_portx_ctl_status_s {
+ uint64_t reserved_43_63:21;
+ uint64_t tdata_out:4;
+ uint64_t txbiststuffenh:1;
+ uint64_t txbiststuffen:1;
+ uint64_t dmpulldown:1;
+ uint64_t dppulldown:1;
+ uint64_t vbusvldext:1;
+ uint64_t portreset:1;
+ uint64_t txhsvxtune:2;
+ uint64_t txvreftune:4;
+ uint64_t txrisetune:1;
+ uint64_t txpreemphasistune:1;
+ uint64_t txfslstune:4;
+ uint64_t sqrxtune:3;
+ uint64_t compdistune:3;
+ uint64_t loop_en:1;
+ uint64_t tclk:1;
+ uint64_t tdata_sel:1;
+ uint64_t taddr_in:4;
+ uint64_t tdata_in:8;
+ } s;
+ struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx;
+ struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1;
+};
+
+#endif
diff --git a/trunk/arch/mips/include/asm/octeon/octeon-model.h b/trunk/arch/mips/include/asm/octeon/octeon-model.h
index cf50336eca2e..700f88e31cad 100644
--- a/trunk/arch/mips/include/asm/octeon/octeon-model.h
+++ b/trunk/arch/mips/include/asm/octeon/octeon-model.h
@@ -35,14 +35,6 @@
#ifndef __OCTEON_MODEL_H__
#define __OCTEON_MODEL_H__
-/* NOTE: These must match what is checked in common-config.mk */
-/* Defines to represent the different versions of Octeon. */
-
-/*
- * IMPORTANT: When the default pass is updated for an Octeon Model,
- * the corresponding change must also be made in the oct-sim script.
- */
-
/*
* The defines below should be used with the OCTEON_IS_MODEL() macro
* to determine what model of chip the software is running on. Models
@@ -71,6 +63,21 @@
#define OM_IGNORE_MINOR_REVISION 0x08000000
#define OM_FLAG_MASK 0xff000000
+#define OM_MATCH_5XXX_FAMILY_MODELS 0x20000000 /* Match all cn5XXX Octeon models. */
+#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000 /* Match all cn6XXX Octeon models. */
+
+/*
+ * CN6XXX models with new revision encoding
+ */
+#define OCTEON_CN63XX_PASS1_0 0x000d9000
+#define OCTEON_CN63XX_PASS1_1 0x000d9001
+#define OCTEON_CN63XX_PASS1_2 0x000d9002
+#define OCTEON_CN63XX_PASS2_0 0x000d9008
+
+#define OCTEON_CN63XX (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN63XX_PASS1_X (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN63XX_PASS2_X (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+
/*
* CN5XXX models with new revision encoding
*/
@@ -189,6 +196,9 @@
| OM_MATCH_PREVIOUS_MODELS \
| OM_IGNORE_REVISION)
+#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
+#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
+
/* The revision byte (low byte) has two different encodings.
* CN3XXX:
*
@@ -222,6 +232,7 @@
| OCTEON_58XX_MODEL_MASK)
#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \
& 0x00fffff8)
+#define OCTEON_5XXX_MODEL_MASK 0x00ff0fc0
#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
@@ -273,6 +284,15 @@ static inline int __OCTEON_IS_MODEL_COMPILE__(uint32_t arg_model,
__OCTEON_MATCH_MASK__((chip_model), (arg_model),
OCTEON_58XX_MODEL_REV_MASK))
return 1;
+
+ if (((arg_model & OM_MATCH_5XXX_FAMILY_MODELS) == OM_MATCH_5XXX_FAMILY_MODELS) &&
+ ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0))
+ return 1;
+
+ if (((arg_model & OM_MATCH_6XXX_FAMILY_MODELS) == OM_MATCH_6XXX_FAMILY_MODELS) &&
+ ((chip_model) >= OCTEON_CN63XX_PASS1_0))
+ return 1;
+
if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
((chip_model & OCTEON_58XX_MODEL_MASK) <
(arg_model & OCTEON_58XX_MODEL_MASK)))
diff --git a/trunk/arch/mips/include/asm/octeon/octeon.h b/trunk/arch/mips/include/asm/octeon/octeon.h
index 917a6c413b1a..6b34afd0d4e7 100644
--- a/trunk/arch/mips/include/asm/octeon/octeon.h
+++ b/trunk/arch/mips/include/asm/octeon/octeon.h
@@ -35,6 +35,7 @@ extern int octeon_is_simulation(void);
extern int octeon_is_pci_host(void);
extern int octeon_usb_is_ref_clk(void);
extern uint64_t octeon_get_clock_rate(void);
+extern u64 octeon_get_io_clock_rate(void);
extern const char *octeon_board_type_string(void);
extern const char *octeon_get_pci_interrupts(void);
extern int octeon_get_southbridge_interrupt(void);
diff --git a/trunk/arch/mips/include/asm/octeon/pci-octeon.h b/trunk/arch/mips/include/asm/octeon/pci-octeon.h
index ece78043acf6..fba2ba200f58 100644
--- a/trunk/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/trunk/arch/mips/include/asm/octeon/pci-octeon.h
@@ -35,6 +35,16 @@
extern int (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
u8 slot, u8 pin);
+/*
+ * For PCI (not PCIe) the BAR2 base address.
+ */
+#define OCTEON_BAR2_PCI_ADDRESS 0x8000000000ull
+
+/*
+ * For PCI (not PCIe) the base of the memory mapped by BAR1
+ */
+extern u64 octeon_bar1_pci_phys;
+
/*
* The following defines are used when octeon_dma_bar_type =
* OCTEON_DMA_BAR_TYPE_BIG
diff --git a/trunk/arch/mips/include/asm/perf_event.h b/trunk/arch/mips/include/asm/perf_event.h
new file mode 100644
index 000000000000..e00007cf8162
--- /dev/null
+++ b/trunk/arch/mips/include/asm/perf_event.h
@@ -0,0 +1,25 @@
+/*
+ * linux/arch/mips/include/asm/perf_event.h
+ *
+ * Copyright (C) 2010 MIPS Technologies, Inc.
+ * Author: Deng-Cheng Zhu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MIPS_PERF_EVENT_H__
+#define __MIPS_PERF_EVENT_H__
+
+/*
+ * MIPS performance counters do not raise NMI upon overflow, a regular
+ * interrupt will be signaled. Hence we can do the pending perf event
+ * work at the tail of the irq handler.
+ */
+static inline void
+set_perf_event_pending(void)
+{
+}
+
+#endif /* __MIPS_PERF_EVENT_H__ */
diff --git a/trunk/arch/mips/include/asm/pgtable-64.h b/trunk/arch/mips/include/asm/pgtable-64.h
index f00896087dda..55908fd56b1f 100644
--- a/trunk/arch/mips/include/asm/pgtable-64.h
+++ b/trunk/arch/mips/include/asm/pgtable-64.h
@@ -113,10 +113,10 @@
#endif
#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
-#if PGDIR_SIZE >= TASK_SIZE
+#if PGDIR_SIZE >= TASK_SIZE64
#define USER_PTRS_PER_PGD (1)
#else
-#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
+#define USER_PTRS_PER_PGD (TASK_SIZE64 / PGDIR_SIZE)
#endif
#define FIRST_USER_ADDRESS 0UL
diff --git a/trunk/arch/mips/include/asm/processor.h b/trunk/arch/mips/include/asm/processor.h
index 0d629bb93cbe..ead6928fa6b8 100644
--- a/trunk/arch/mips/include/asm/processor.h
+++ b/trunk/arch/mips/include/asm/processor.h
@@ -50,13 +50,10 @@ extern unsigned int vced_count, vcei_count;
* so don't change it unless you know what you are doing.
*/
#define TASK_SIZE 0x7fff8000UL
-#define STACK_TOP ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE ((TASK_SIZE / 3) & ~(PAGE_SIZE))
+#ifdef __KERNEL__
+#define STACK_TOP_MAX TASK_SIZE
+#endif
#define TASK_IS_32BIT_ADDR 1
@@ -71,28 +68,29 @@ extern unsigned int vced_count, vcei_count;
* 8192EB ...
*/
#define TASK_SIZE32 0x7fff8000UL
-#define TASK_SIZE 0x10000000000UL
-#define STACK_TOP \
- (((test_thread_flag(TIF_32BIT_ADDR) ? \
- TASK_SIZE32 : TASK_SIZE) & PAGE_MASK) - SPECIAL_PAGES_SIZE)
+#define TASK_SIZE64 0x10000000000UL
+#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
+
+#ifdef __KERNEL__
+#define STACK_TOP_MAX TASK_SIZE64
+#endif
+
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE \
- (test_thread_flag(TIF_32BIT_ADDR) ? \
- PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
#define TASK_SIZE_OF(tsk) \
- (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
+ (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
#endif
-#ifdef __KERNEL__
-#define STACK_TOP_MAX TASK_SIZE
-#endif
+#define STACK_TOP ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
+
#define NUM_FPU_REGS 32
diff --git a/trunk/arch/mips/include/asm/system.h b/trunk/arch/mips/include/asm/system.h
index bb937ccfba1e..6018c80ce37a 100644
--- a/trunk/arch/mips/include/asm/system.h
+++ b/trunk/arch/mips/include/asm/system.h
@@ -115,21 +115,19 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
} else if (kernel_uses_llsc) {
unsigned long dummy;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %0, %3 # xchg_u32 \n"
- " .set mips0 \n"
- " move %2, %z4 \n"
- " .set mips3 \n"
- " sc %2, %1 \n"
- " beqz %2, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (retval), "=m" (*m), "=&r" (dummy)
- : "R" (*m), "Jr" (val)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " ll %0, %3 # xchg_u32 \n"
+ " .set mips0 \n"
+ " move %2, %z4 \n"
+ " .set mips3 \n"
+ " sc %2, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+ : "R" (*m), "Jr" (val)
+ : "memory");
+ } while (unlikely(!dummy));
} else {
unsigned long flags;
@@ -167,19 +165,17 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
} else if (kernel_uses_llsc) {
unsigned long dummy;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %0, %3 # xchg_u64 \n"
- " move %2, %z4 \n"
- " scd %2, %1 \n"
- " beqz %2, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (retval), "=m" (*m), "=&r" (dummy)
- : "R" (*m), "Jr" (val)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " lld %0, %3 # xchg_u64 \n"
+ " move %2, %z4 \n"
+ " scd %2, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+ : "R" (*m), "Jr" (val)
+ : "memory");
+ } while (unlikely(!dummy));
} else {
unsigned long flags;
diff --git a/trunk/arch/mips/include/asm/thread_info.h b/trunk/arch/mips/include/asm/thread_info.h
index 70df9c0d3c5b..d309556cacf8 100644
--- a/trunk/arch/mips/include/asm/thread_info.h
+++ b/trunk/arch/mips/include/asm/thread_info.h
@@ -83,6 +83,8 @@ register struct thread_info *__current_thread_info __asm__("$28");
#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
#define THREAD_MASK (THREAD_SIZE - 1UL)
+#define STACK_WARN (THREAD_SIZE / 8)
+
#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
#ifdef CONFIG_DEBUG_STACK_USAGE
diff --git a/trunk/arch/mips/include/asm/uaccess.h b/trunk/arch/mips/include/asm/uaccess.h
index c2d53c18fd36..653a412c036c 100644
--- a/trunk/arch/mips/include/asm/uaccess.h
+++ b/trunk/arch/mips/include/asm/uaccess.h
@@ -35,7 +35,9 @@
#ifdef CONFIG_64BIT
-#define __UA_LIMIT (- TASK_SIZE)
+extern u64 __ua_limit;
+
+#define __UA_LIMIT __ua_limit
#define __UA_ADDR ".dword"
#define __UA_LA "dla"
diff --git a/trunk/arch/mips/kernel/Makefile b/trunk/arch/mips/kernel/Makefile
index 80884983270d..22b2e0e38617 100644
--- a/trunk/arch/mips/kernel/Makefile
+++ b/trunk/arch/mips/kernel/Makefile
@@ -104,4 +104,6 @@ obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o
obj-$(CONFIG_MIPS_CPUFREQ) += cpufreq/
+obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
+
CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)
diff --git a/trunk/arch/mips/kernel/cpu-probe.c b/trunk/arch/mips/kernel/cpu-probe.c
index b1b304ea2128..71620e19827a 100644
--- a/trunk/arch/mips/kernel/cpu-probe.c
+++ b/trunk/arch/mips/kernel/cpu-probe.c
@@ -25,6 +25,8 @@
#include
#include
#include
+#include
+
/*
* Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
* the implementation of the "wait" feature differs between CPU families. This
@@ -181,12 +183,13 @@ void __init check_wait(void)
case CPU_5KC:
case CPU_25KF:
case CPU_PR4450:
- case CPU_BCM3302:
- case CPU_BCM6338:
- case CPU_BCM6348:
- case CPU_BCM6358:
+ case CPU_BMIPS3300:
+ case CPU_BMIPS4350:
+ case CPU_BMIPS4380:
+ case CPU_BMIPS5000:
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
+ case CPU_CAVIUM_OCTEON2:
case CPU_JZRISC:
cpu_wait = r4k_wait;
break;
@@ -902,33 +905,37 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
{
decode_configs(c);
switch (c->processor_id & 0xff00) {
- case PRID_IMP_BCM3302:
- /* same as PRID_IMP_BCM6338 */
- c->cputype = CPU_BCM3302;
- __cpu_name[cpu] = "Broadcom BCM3302";
- break;
- case PRID_IMP_BCM4710:
- c->cputype = CPU_BCM4710;
- __cpu_name[cpu] = "Broadcom BCM4710";
- break;
- case PRID_IMP_BCM6345:
- c->cputype = CPU_BCM6345;
- __cpu_name[cpu] = "Broadcom BCM6345";
+ case PRID_IMP_BMIPS32:
+ c->cputype = CPU_BMIPS32;
+ __cpu_name[cpu] = "Broadcom BMIPS32";
+ break;
+ case PRID_IMP_BMIPS3300:
+ case PRID_IMP_BMIPS3300_ALT:
+ case PRID_IMP_BMIPS3300_BUG:
+ c->cputype = CPU_BMIPS3300;
+ __cpu_name[cpu] = "Broadcom BMIPS3300";
+ break;
+ case PRID_IMP_BMIPS43XX: {
+ int rev = c->processor_id & 0xff;
+
+ if (rev >= PRID_REV_BMIPS4380_LO &&
+ rev <= PRID_REV_BMIPS4380_HI) {
+ c->cputype = CPU_BMIPS4380;
+ __cpu_name[cpu] = "Broadcom BMIPS4380";
+ } else {
+ c->cputype = CPU_BMIPS4350;
+ __cpu_name[cpu] = "Broadcom BMIPS4350";
+ }
break;
- case PRID_IMP_BCM6348:
- c->cputype = CPU_BCM6348;
- __cpu_name[cpu] = "Broadcom BCM6348";
+ }
+ case PRID_IMP_BMIPS5000:
+ c->cputype = CPU_BMIPS5000;
+ __cpu_name[cpu] = "Broadcom BMIPS5000";
+ c->options |= MIPS_CPU_ULRI;
break;
- case PRID_IMP_BCM4350:
- switch (c->processor_id & 0xf0) {
- case PRID_REV_BCM6358:
- c->cputype = CPU_BCM6358;
- __cpu_name[cpu] = "Broadcom BCM6358";
- break;
- default:
- c->cputype = CPU_UNKNOWN;
- break;
- }
+ case PRID_IMP_BMIPS4KC:
+ c->cputype = CPU_4KC;
+ __cpu_name[cpu] = "MIPS 4Kc";
break;
}
}
@@ -953,6 +960,12 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
if (cpu == 0)
__elf_platform = "octeon";
break;
+ case PRID_IMP_CAVIUM_CN63XX:
+ c->cputype = CPU_CAVIUM_OCTEON2;
+ __cpu_name[cpu] = "Cavium Octeon II";
+ if (cpu == 0)
+ __elf_platform = "octeon2";
+ break;
default:
printk(KERN_INFO "Unknown Octeon chip!\n");
c->cputype = CPU_UNKNOWN;
@@ -976,6 +989,12 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
}
}
+#ifdef CONFIG_64BIT
+/* For use by uaccess.h */
+u64 __ua_limit;
+EXPORT_SYMBOL(__ua_limit);
+#endif
+
const char *__cpu_name[NR_CPUS];
const char *__elf_platform;
@@ -1053,6 +1072,11 @@ __cpuinit void cpu_probe(void)
c->srsets = 1;
cpu_probe_vmbits(c);
+
+#ifdef CONFIG_64BIT
+ if (cpu == 0)
+ __ua_limit = ~((1ull << cpu_vmbits) - 1);
+#endif
}
__cpuinit void cpu_report(void)
diff --git a/trunk/arch/mips/kernel/irq.c b/trunk/arch/mips/kernel/irq.c
index c6345f579a8a..4f93db58a79e 100644
--- a/trunk/arch/mips/kernel/irq.c
+++ b/trunk/arch/mips/kernel/irq.c
@@ -151,6 +151,29 @@ void __init init_IRQ(void)
#endif
}
+#ifdef DEBUG_STACKOVERFLOW
+static inline void check_stack_overflow(void)
+{
+ unsigned long sp;
+
+ __asm__ __volatile__("move %0, $sp" : "=r" (sp));
+ sp &= THREAD_MASK;
+
+ /*
+ * Check for stack overflow: is there less than STACK_WARN free?
+ * STACK_WARN is defined as 1/8 of THREAD_SIZE by default.
+ */
+ if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
+ printk("do_IRQ: stack overflow: %ld\n",
+ sp - sizeof(struct thread_info));
+ dump_stack();
+ }
+}
+#else
+static inline void check_stack_overflow(void) {}
+#endif
+
+
/*
* do_IRQ handles all normal device IRQ's (the special
* SMP cross-CPU interrupts have their own specific
@@ -159,6 +182,7 @@ void __init init_IRQ(void)
void __irq_entry do_IRQ(unsigned int irq)
{
irq_enter();
+ check_stack_overflow();
__DO_IRQ_SMTC_HOOK(irq);
generic_handle_irq(irq);
irq_exit();
diff --git a/trunk/arch/mips/kernel/perf_event.c b/trunk/arch/mips/kernel/perf_event.c
new file mode 100644
index 000000000000..2b7f3f703b83
--- /dev/null
+++ b/trunk/arch/mips/kernel/perf_event.c
@@ -0,0 +1,601 @@
+/*
+ * Linux performance counter support for MIPS.
+ *
+ * Copyright (C) 2010 MIPS Technologies, Inc.
+ * Author: Deng-Cheng Zhu
+ *
+ * This code is based on the implementation for ARM, which is in turn
+ * based on the sparc64 perf event code and the x86 code. Performance
+ * counter access is based on the MIPS Oprofile code. And the callchain
+ * support references the code of MIPS stacktrace.c.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include /* For perf_irq */
+
+/* These are for 32bit counters. For 64bit ones, define them accordingly. */
+#define MAX_PERIOD ((1ULL << 32) - 1)
+#define VALID_COUNT 0x7fffffff
+#define TOTAL_BITS 32
+#define HIGHEST_BIT 31
+
+#define MIPS_MAX_HWEVENTS 4
+
+struct cpu_hw_events {
+ /* Array of events on this cpu. */
+ struct perf_event *events[MIPS_MAX_HWEVENTS];
+
+ /*
+ * Set the bit (indexed by the counter number) when the counter
+ * is used for an event.
+ */
+ unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
+
+ /*
+ * The borrowed MSB for the performance counter. A MIPS performance
+ * counter uses its bit 31 (for 32bit counters) or bit 63 (for 64bit
+ * counters) as a factor of determining whether a counter overflow
+ * should be signaled. So here we use a separate MSB for each
+ * counter to make things easy.
+ */
+ unsigned long msbs[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
+
+ /*
+ * Software copy of the control register for each performance counter.
+ * MIPS CPUs vary in performance counters. They use this differently,
+ * and even may not use it.
+ */
+ unsigned int saved_ctrl[MIPS_MAX_HWEVENTS];
+};
+DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
+ .saved_ctrl = {0},
+};
+
+/* The description of MIPS performance events. */
+struct mips_perf_event {
+ unsigned int event_id;
+ /*
+ * MIPS performance counters are indexed starting from 0.
+ * CNTR_EVEN indicates the indexes of the counters to be used are
+ * even numbers.
+ */
+ unsigned int cntr_mask;
+ #define CNTR_EVEN 0x55555555
+ #define CNTR_ODD 0xaaaaaaaa
+#ifdef CONFIG_MIPS_MT_SMP
+ enum {
+ T = 0,
+ V = 1,
+ P = 2,
+ } range;
+#else
+ #define T
+ #define V
+ #define P
+#endif
+};
+
+static struct mips_perf_event raw_event;
+static DEFINE_MUTEX(raw_event_mutex);
+
+#define UNSUPPORTED_PERF_EVENT_ID 0xffffffff
+#define C(x) PERF_COUNT_HW_CACHE_##x
+
+struct mips_pmu {
+ const char *name;
+ int irq;
+ irqreturn_t (*handle_irq)(int irq, void *dev);
+ int (*handle_shared_irq)(void);
+ void (*start)(void);
+ void (*stop)(void);
+ int (*alloc_counter)(struct cpu_hw_events *cpuc,
+ struct hw_perf_event *hwc);
+ u64 (*read_counter)(unsigned int idx);
+ void (*write_counter)(unsigned int idx, u64 val);
+ void (*enable_event)(struct hw_perf_event *evt, int idx);
+ void (*disable_event)(int idx);
+ const struct mips_perf_event *(*map_raw_event)(u64 config);
+ const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
+ const struct mips_perf_event (*cache_event_map)
+ [PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX];
+ unsigned int num_counters;
+};
+
+static const struct mips_pmu *mipspmu;
+
+static int
+mipspmu_event_set_period(struct perf_event *event,
+ struct hw_perf_event *hwc,
+ int idx)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ s64 left = local64_read(&hwc->period_left);
+ s64 period = hwc->sample_period;
+ int ret = 0;
+ u64 uleft;
+ unsigned long flags;
+
+ if (unlikely(left <= -period)) {
+ left = period;
+ local64_set(&hwc->period_left, left);
+ hwc->last_period = period;
+ ret = 1;
+ }
+
+ if (unlikely(left <= 0)) {
+ left += period;
+ local64_set(&hwc->period_left, left);
+ hwc->last_period = period;
+ ret = 1;
+ }
+
+ if (left > (s64)MAX_PERIOD)
+ left = MAX_PERIOD;
+
+ local64_set(&hwc->prev_count, (u64)-left);
+
+ local_irq_save(flags);
+ uleft = (u64)(-left) & MAX_PERIOD;
+ uleft > VALID_COUNT ?
+ set_bit(idx, cpuc->msbs) : clear_bit(idx, cpuc->msbs);
+ mipspmu->write_counter(idx, (u64)(-left) & VALID_COUNT);
+ local_irq_restore(flags);
+
+ perf_event_update_userpage(event);
+
+ return ret;
+}
+
+static int mipspmu_enable(struct perf_event *event)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ struct hw_perf_event *hwc = &event->hw;
+ int idx;
+ int err = 0;
+
+ /* To look for a free counter for this event. */
+ idx = mipspmu->alloc_counter(cpuc, hwc);
+ if (idx < 0) {
+ err = idx;
+ goto out;
+ }
+
+ /*
+ * If there is an event in the counter we are going to use then
+ * make sure it is disabled.
+ */
+ event->hw.idx = idx;
+ mipspmu->disable_event(idx);
+ cpuc->events[idx] = event;
+
+ /* Set the period for the event. */
+ mipspmu_event_set_period(event, hwc, idx);
+
+ /* Enable the event. */
+ mipspmu->enable_event(hwc, idx);
+
+ /* Propagate our changes to the userspace mapping. */
+ perf_event_update_userpage(event);
+
+out:
+ return err;
+}
+
+static void mipspmu_event_update(struct perf_event *event,
+ struct hw_perf_event *hwc,
+ int idx)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ unsigned long flags;
+ int shift = 64 - TOTAL_BITS;
+ s64 prev_raw_count, new_raw_count;
+ s64 delta;
+
+again:
+ prev_raw_count = local64_read(&hwc->prev_count);
+ local_irq_save(flags);
+ /* Make the counter value be a "real" one. */
+ new_raw_count = mipspmu->read_counter(idx);
+ if (new_raw_count & (test_bit(idx, cpuc->msbs) << HIGHEST_BIT)) {
+ new_raw_count &= VALID_COUNT;
+ clear_bit(idx, cpuc->msbs);
+ } else
+ new_raw_count |= (test_bit(idx, cpuc->msbs) << HIGHEST_BIT);
+ local_irq_restore(flags);
+
+ if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
+ new_raw_count) != prev_raw_count)
+ goto again;
+
+ delta = (new_raw_count << shift) - (prev_raw_count << shift);
+ delta >>= shift;
+
+ local64_add(delta, &event->count);
+ local64_sub(delta, &hwc->period_left);
+
+ return;
+}
+
+static void mipspmu_disable(struct perf_event *event)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ struct hw_perf_event *hwc = &event->hw;
+ int idx = hwc->idx;
+
+
+ WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
+
+ /* We are working on a local event. */
+ mipspmu->disable_event(idx);
+
+ barrier();
+
+ mipspmu_event_update(event, hwc, idx);
+ cpuc->events[idx] = NULL;
+ clear_bit(idx, cpuc->used_mask);
+
+ perf_event_update_userpage(event);
+}
+
+static void mipspmu_unthrottle(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ mipspmu->enable_event(hwc, hwc->idx);
+}
+
+static void mipspmu_read(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ /* Don't read disabled counters! */
+ if (hwc->idx < 0)
+ return;
+
+ mipspmu_event_update(event, hwc, hwc->idx);
+}
+
+static struct pmu pmu = {
+ .enable = mipspmu_enable,
+ .disable = mipspmu_disable,
+ .unthrottle = mipspmu_unthrottle,
+ .read = mipspmu_read,
+};
+
+static atomic_t active_events = ATOMIC_INIT(0);
+static DEFINE_MUTEX(pmu_reserve_mutex);
+static int (*save_perf_irq)(void);
+
+static int mipspmu_get_irq(void)
+{
+ int err;
+
+ if (mipspmu->irq >= 0) {
+ /* Request my own irq handler. */
+ err = request_irq(mipspmu->irq, mipspmu->handle_irq,
+ IRQF_DISABLED | IRQF_NOBALANCING,
+ "mips_perf_pmu", NULL);
+ if (err) {
+ pr_warning("Unable to request IRQ%d for MIPS "
+ "performance counters!\n", mipspmu->irq);
+ }
+ } else if (cp0_perfcount_irq < 0) {
+ /*
+ * We are sharing the irq number with the timer interrupt.
+ */
+ save_perf_irq = perf_irq;
+ perf_irq = mipspmu->handle_shared_irq;
+ err = 0;
+ } else {
+ pr_warning("The platform hasn't properly defined its "
+ "interrupt controller.\n");
+ err = -ENOENT;
+ }
+
+ return err;
+}
+
+static void mipspmu_free_irq(void)
+{
+ if (mipspmu->irq >= 0)
+ free_irq(mipspmu->irq, NULL);
+ else if (cp0_perfcount_irq < 0)
+ perf_irq = save_perf_irq;
+}
+
+static inline unsigned int
+mipspmu_perf_event_encode(const struct mips_perf_event *pev)
+{
+/*
+ * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
+ * event_id.
+ */
+#ifdef CONFIG_MIPS_MT_SMP
+ return ((unsigned int)pev->range << 24) |
+ (pev->cntr_mask & 0xffff00) |
+ (pev->event_id & 0xff);
+#else
+ return (pev->cntr_mask & 0xffff00) |
+ (pev->event_id & 0xff);
+#endif
+}
+
+static const struct mips_perf_event *
+mipspmu_map_general_event(int idx)
+{
+ const struct mips_perf_event *pev;
+
+ pev = ((*mipspmu->general_event_map)[idx].event_id ==
+ UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) :
+ &(*mipspmu->general_event_map)[idx]);
+
+ return pev;
+}
+
+static const struct mips_perf_event *
+mipspmu_map_cache_event(u64 config)
+{
+ unsigned int cache_type, cache_op, cache_result;
+ const struct mips_perf_event *pev;
+
+ cache_type = (config >> 0) & 0xff;
+ if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
+ return ERR_PTR(-EINVAL);
+
+ cache_op = (config >> 8) & 0xff;
+ if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
+ return ERR_PTR(-EINVAL);
+
+ cache_result = (config >> 16) & 0xff;
+ if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
+ return ERR_PTR(-EINVAL);
+
+ pev = &((*mipspmu->cache_event_map)
+ [cache_type]
+ [cache_op]
+ [cache_result]);
+
+ if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID)
+ return ERR_PTR(-EOPNOTSUPP);
+
+ return pev;
+
+}
+
+static int validate_event(struct cpu_hw_events *cpuc,
+ struct perf_event *event)
+{
+ struct hw_perf_event fake_hwc = event->hw;
+
+ if (event->pmu && event->pmu != &pmu)
+ return 0;
+
+ return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0;
+}
+
+static int validate_group(struct perf_event *event)
+{
+ struct perf_event *sibling, *leader = event->group_leader;
+ struct cpu_hw_events fake_cpuc;
+
+ memset(&fake_cpuc, 0, sizeof(fake_cpuc));
+
+ if (!validate_event(&fake_cpuc, leader))
+ return -ENOSPC;
+
+ list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
+ if (!validate_event(&fake_cpuc, sibling))
+ return -ENOSPC;
+ }
+
+ if (!validate_event(&fake_cpuc, event))
+ return -ENOSPC;
+
+ return 0;
+}
+
+/*
+ * mipsxx/rm9000/loongson2 have different performance counters, they have
+ * specific low-level init routines.
+ */
+static void reset_counters(void *arg);
+static int __hw_perf_event_init(struct perf_event *event);
+
+static void hw_perf_event_destroy(struct perf_event *event)
+{
+ if (atomic_dec_and_mutex_lock(&active_events,
+ &pmu_reserve_mutex)) {
+ /*
+ * We must not call the destroy function with interrupts
+ * disabled.
+ */
+ on_each_cpu(reset_counters,
+ (void *)(long)mipspmu->num_counters, 1);
+ mipspmu_free_irq();
+ mutex_unlock(&pmu_reserve_mutex);
+ }
+}
+
+const struct pmu *hw_perf_event_init(struct perf_event *event)
+{
+ int err = 0;
+
+ if (!mipspmu || event->cpu >= nr_cpumask_bits ||
+ (event->cpu >= 0 && !cpu_online(event->cpu)))
+ return ERR_PTR(-ENODEV);
+
+ if (!atomic_inc_not_zero(&active_events)) {
+ if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) {
+ atomic_dec(&active_events);
+ return ERR_PTR(-ENOSPC);
+ }
+
+ mutex_lock(&pmu_reserve_mutex);
+ if (atomic_read(&active_events) == 0)
+ err = mipspmu_get_irq();
+
+ if (!err)
+ atomic_inc(&active_events);
+ mutex_unlock(&pmu_reserve_mutex);
+ }
+
+ if (err)
+ return ERR_PTR(err);
+
+ err = __hw_perf_event_init(event);
+ if (err)
+ hw_perf_event_destroy(event);
+
+ return err ? ERR_PTR(err) : &pmu;
+}
+
+void hw_perf_enable(void)
+{
+ if (mipspmu)
+ mipspmu->start();
+}
+
+void hw_perf_disable(void)
+{
+ if (mipspmu)
+ mipspmu->stop();
+}
+
+/* This is needed by specific irq handlers in perf_event_*.c */
+static void
+handle_associated_event(struct cpu_hw_events *cpuc,
+ int idx, struct perf_sample_data *data, struct pt_regs *regs)
+{
+ struct perf_event *event = cpuc->events[idx];
+ struct hw_perf_event *hwc = &event->hw;
+
+ mipspmu_event_update(event, hwc, idx);
+ data->period = event->hw.last_period;
+ if (!mipspmu_event_set_period(event, hwc, idx))
+ return;
+
+ if (perf_event_overflow(event, 0, data, regs))
+ mipspmu->disable_event(idx);
+}
+
+#include "perf_event_mipsxx.c"
+
+/* Callchain handling code. */
+static inline void
+callchain_store(struct perf_callchain_entry *entry,
+ u64 ip)
+{
+ if (entry->nr < PERF_MAX_STACK_DEPTH)
+ entry->ip[entry->nr++] = ip;
+}
+
+/*
+ * Leave userspace callchain empty for now. When we find a way to trace
+ * the user stack callchains, we add here.
+ */
+static void
+perf_callchain_user(struct pt_regs *regs,
+ struct perf_callchain_entry *entry)
+{
+}
+
+static void save_raw_perf_callchain(struct perf_callchain_entry *entry,
+ unsigned long reg29)
+{
+ unsigned long *sp = (unsigned long *)reg29;
+ unsigned long addr;
+
+ while (!kstack_end(sp)) {
+ addr = *sp++;
+ if (__kernel_text_address(addr)) {
+ callchain_store(entry, addr);
+ if (entry->nr >= PERF_MAX_STACK_DEPTH)
+ break;
+ }
+ }
+}
+
+static void
+perf_callchain_kernel(struct pt_regs *regs,
+ struct perf_callchain_entry *entry)
+{
+ unsigned long sp = regs->regs[29];
+#ifdef CONFIG_KALLSYMS
+ unsigned long ra = regs->regs[31];
+ unsigned long pc = regs->cp0_epc;
+
+ callchain_store(entry, PERF_CONTEXT_KERNEL);
+ if (raw_show_trace || !__kernel_text_address(pc)) {
+ unsigned long stack_page =
+ (unsigned long)task_stack_page(current);
+ if (stack_page && sp >= stack_page &&
+ sp <= stack_page + THREAD_SIZE - 32)
+ save_raw_perf_callchain(entry, sp);
+ return;
+ }
+ do {
+ callchain_store(entry, pc);
+ if (entry->nr >= PERF_MAX_STACK_DEPTH)
+ break;
+ pc = unwind_stack(current, &sp, pc, &ra);
+ } while (pc);
+#else
+ callchain_store(entry, PERF_CONTEXT_KERNEL);
+ save_raw_perf_callchain(entry, sp);
+#endif
+}
+
+static void
+perf_do_callchain(struct pt_regs *regs,
+ struct perf_callchain_entry *entry)
+{
+ int is_user;
+
+ if (!regs)
+ return;
+
+ is_user = user_mode(regs);
+
+ if (!current || !current->pid)
+ return;
+
+ if (is_user && current->state != TASK_RUNNING)
+ return;
+
+ if (!is_user) {
+ perf_callchain_kernel(regs, entry);
+ if (current->mm)
+ regs = task_pt_regs(current);
+ else
+ regs = NULL;
+ }
+ if (regs)
+ perf_callchain_user(regs, entry);
+}
+
+static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
+
+struct perf_callchain_entry *
+perf_callchain(struct pt_regs *regs)
+{
+ struct perf_callchain_entry *entry = &__get_cpu_var(pmc_irq_entry);
+
+ entry->nr = 0;
+ perf_do_callchain(regs, entry);
+ return entry;
+}
diff --git a/trunk/arch/mips/kernel/perf_event_mipsxx.c b/trunk/arch/mips/kernel/perf_event_mipsxx.c
new file mode 100644
index 000000000000..5c7c6fc07565
--- /dev/null
+++ b/trunk/arch/mips/kernel/perf_event_mipsxx.c
@@ -0,0 +1,1052 @@
+#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) || \
+ defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_SB1)
+
+#define M_CONFIG1_PC (1 << 4)
+
+#define M_PERFCTL_EXL (1UL << 0)
+#define M_PERFCTL_KERNEL (1UL << 1)
+#define M_PERFCTL_SUPERVISOR (1UL << 2)
+#define M_PERFCTL_USER (1UL << 3)
+#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
+#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
+#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
+#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
+#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
+#define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
+#define M_TC_EN_TC M_PERFCTL_MT_EN(2)
+#define M_PERFCTL_TCID(tcid) ((tcid) << 22)
+#define M_PERFCTL_WIDE (1UL << 30)
+#define M_PERFCTL_MORE (1UL << 31)
+
+#define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL | \
+ M_PERFCTL_KERNEL | \
+ M_PERFCTL_USER | \
+ M_PERFCTL_SUPERVISOR | \
+ M_PERFCTL_INTERRUPT_ENABLE)
+
+#ifdef CONFIG_MIPS_MT_SMP
+#define M_PERFCTL_CONFIG_MASK 0x3fff801f
+#else
+#define M_PERFCTL_CONFIG_MASK 0x1f
+#endif
+#define M_PERFCTL_EVENT_MASK 0xfe0
+
+#define M_COUNTER_OVERFLOW (1UL << 31)
+
+#ifdef CONFIG_MIPS_MT_SMP
+static int cpu_has_mipsmt_pertccounters;
+
+/*
+ * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because
+ * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs.
+ */
+#if defined(CONFIG_HW_PERF_EVENTS)
+#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
+ 0 : smp_processor_id())
+#else
+#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
+ 0 : cpu_data[smp_processor_id()].vpe_id)
+#endif
+
+/* Copied from op_model_mipsxx.c */
+static inline unsigned int vpe_shift(void)
+{
+ if (num_possible_cpus() > 1)
+ return 1;
+
+ return 0;
+}
+#else /* !CONFIG_MIPS_MT_SMP */
+#define vpe_id() 0
+
+static inline unsigned int vpe_shift(void)
+{
+ return 0;
+}
+#endif /* CONFIG_MIPS_MT_SMP */
+
+static inline unsigned int
+counters_total_to_per_cpu(unsigned int counters)
+{
+ return counters >> vpe_shift();
+}
+
+static inline unsigned int
+counters_per_cpu_to_total(unsigned int counters)
+{
+ return counters << vpe_shift();
+}
+
+#define __define_perf_accessors(r, n, np) \
+ \
+static inline unsigned int r_c0_ ## r ## n(void) \
+{ \
+ unsigned int cpu = vpe_id(); \
+ \
+ switch (cpu) { \
+ case 0: \
+ return read_c0_ ## r ## n(); \
+ case 1: \
+ return read_c0_ ## r ## np(); \
+ default: \
+ BUG(); \
+ } \
+ return 0; \
+} \
+ \
+static inline void w_c0_ ## r ## n(unsigned int value) \
+{ \
+ unsigned int cpu = vpe_id(); \
+ \
+ switch (cpu) { \
+ case 0: \
+ write_c0_ ## r ## n(value); \
+ return; \
+ case 1: \
+ write_c0_ ## r ## np(value); \
+ return; \
+ default: \
+ BUG(); \
+ } \
+ return; \
+} \
+
+__define_perf_accessors(perfcntr, 0, 2)
+__define_perf_accessors(perfcntr, 1, 3)
+__define_perf_accessors(perfcntr, 2, 0)
+__define_perf_accessors(perfcntr, 3, 1)
+
+__define_perf_accessors(perfctrl, 0, 2)
+__define_perf_accessors(perfctrl, 1, 3)
+__define_perf_accessors(perfctrl, 2, 0)
+__define_perf_accessors(perfctrl, 3, 1)
+
+static inline int __n_counters(void)
+{
+ if (!(read_c0_config1() & M_CONFIG1_PC))
+ return 0;
+ if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
+ return 1;
+ if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
+ return 2;
+ if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
+ return 3;
+
+ return 4;
+}
+
+static inline int n_counters(void)
+{
+ int counters;
+
+ switch (current_cpu_type()) {
+ case CPU_R10000:
+ counters = 2;
+ break;
+
+ case CPU_R12000:
+ case CPU_R14000:
+ counters = 4;
+ break;
+
+ default:
+ counters = __n_counters();
+ }
+
+ return counters;
+}
+
+static void reset_counters(void *arg)
+{
+ int counters = (int)(long)arg;
+ switch (counters) {
+ case 4:
+ w_c0_perfctrl3(0);
+ w_c0_perfcntr3(0);
+ case 3:
+ w_c0_perfctrl2(0);
+ w_c0_perfcntr2(0);
+ case 2:
+ w_c0_perfctrl1(0);
+ w_c0_perfcntr1(0);
+ case 1:
+ w_c0_perfctrl0(0);
+ w_c0_perfcntr0(0);
+ }
+}
+
+static inline u64
+mipsxx_pmu_read_counter(unsigned int idx)
+{
+ switch (idx) {
+ case 0:
+ return r_c0_perfcntr0();
+ case 1:
+ return r_c0_perfcntr1();
+ case 2:
+ return r_c0_perfcntr2();
+ case 3:
+ return r_c0_perfcntr3();
+ default:
+ WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
+ return 0;
+ }
+}
+
+static inline void
+mipsxx_pmu_write_counter(unsigned int idx, u64 val)
+{
+ switch (idx) {
+ case 0:
+ w_c0_perfcntr0(val);
+ return;
+ case 1:
+ w_c0_perfcntr1(val);
+ return;
+ case 2:
+ w_c0_perfcntr2(val);
+ return;
+ case 3:
+ w_c0_perfcntr3(val);
+ return;
+ }
+}
+
+static inline unsigned int
+mipsxx_pmu_read_control(unsigned int idx)
+{
+ switch (idx) {
+ case 0:
+ return r_c0_perfctrl0();
+ case 1:
+ return r_c0_perfctrl1();
+ case 2:
+ return r_c0_perfctrl2();
+ case 3:
+ return r_c0_perfctrl3();
+ default:
+ WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
+ return 0;
+ }
+}
+
+static inline void
+mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
+{
+ switch (idx) {
+ case 0:
+ w_c0_perfctrl0(val);
+ return;
+ case 1:
+ w_c0_perfctrl1(val);
+ return;
+ case 2:
+ w_c0_perfctrl2(val);
+ return;
+ case 3:
+ w_c0_perfctrl3(val);
+ return;
+ }
+}
+
+#ifdef CONFIG_MIPS_MT_SMP
+static DEFINE_RWLOCK(pmuint_rwlock);
+#endif
+
+/* 24K/34K/1004K cores can share the same event map. */
+static const struct mips_perf_event mipsxxcore_event_map
+ [PERF_COUNT_HW_MAX] = {
+ [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
+ [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
+ [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
+ [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
+ [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
+ [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
+};
+
+/* 74K core has different branch event code. */
+static const struct mips_perf_event mipsxx74Kcore_event_map
+ [PERF_COUNT_HW_MAX] = {
+ [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
+ [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
+ [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
+ [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
+ [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
+ [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
+};
+
+/* 24K/34K/1004K cores can share the same cache event map. */
+static const struct mips_perf_event mipsxxcore_cache_map
+ [PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+[C(L1D)] = {
+ /*
+ * Like some other architectures (e.g. ARM), the performance
+ * counters don't differentiate between read and write
+ * accesses/misses, so this isn't strictly correct, but it's the
+ * best we can do. Writes and reads get combined.
+ */
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(L1I)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T },
+ /*
+ * Note that MIPS has only "hit" events countable for
+ * the prefetch operation.
+ */
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(LL)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
+ [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
+ [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(DTLB)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(ITLB)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(BPU)] = {
+ /* Using the same code for *HW_BRANCH* */
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+};
+
+/* 74K core has completely different cache event map. */
+static const struct mips_perf_event mipsxx74Kcore_cache_map
+ [PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+[C(L1D)] = {
+ /*
+ * Like some other architectures (e.g. ARM), the performance
+ * counters don't differentiate between read and write
+ * accesses/misses, so this isn't strictly correct, but it's the
+ * best we can do. Writes and reads get combined.
+ */
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
+ [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
+ [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(L1I)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T },
+ /*
+ * Note that MIPS has only "hit" events countable for
+ * the prefetch operation.
+ */
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(LL)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
+ [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
+ [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(DTLB)] = {
+ /* 74K core does not have specific DTLB events. */
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(ITLB)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(BPU)] = {
+ /* Using the same code for *HW_BRANCH* */
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+};
+
+#ifdef CONFIG_MIPS_MT_SMP
+static void
+check_and_calc_range(struct perf_event *event,
+ const struct mips_perf_event *pev)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ if (event->cpu >= 0) {
+ if (pev->range > V) {
+ /*
+ * The user selected an event that is processor
+ * wide, while expecting it to be VPE wide.
+ */
+ hwc->config_base |= M_TC_EN_ALL;
+ } else {
+ /*
+ * FIXME: cpu_data[event->cpu].vpe_id reports 0
+ * for both CPUs.
+ */
+ hwc->config_base |= M_PERFCTL_VPEID(event->cpu);
+ hwc->config_base |= M_TC_EN_VPE;
+ }
+ } else
+ hwc->config_base |= M_TC_EN_ALL;
+}
+#else
+static void
+check_and_calc_range(struct perf_event *event,
+ const struct mips_perf_event *pev)
+{
+}
+#endif
+
+static int __hw_perf_event_init(struct perf_event *event)
+{
+ struct perf_event_attr *attr = &event->attr;
+ struct hw_perf_event *hwc = &event->hw;
+ const struct mips_perf_event *pev;
+ int err;
+
+ /* Returning MIPS event descriptor for generic perf event. */
+ if (PERF_TYPE_HARDWARE == event->attr.type) {
+ if (event->attr.config >= PERF_COUNT_HW_MAX)
+ return -EINVAL;
+ pev = mipspmu_map_general_event(event->attr.config);
+ } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
+ pev = mipspmu_map_cache_event(event->attr.config);
+ } else if (PERF_TYPE_RAW == event->attr.type) {
+ /* We are working on the global raw event. */
+ mutex_lock(&raw_event_mutex);
+ pev = mipspmu->map_raw_event(event->attr.config);
+ } else {
+ /* The event type is not (yet) supported. */
+ return -EOPNOTSUPP;
+ }
+
+ if (IS_ERR(pev)) {
+ if (PERF_TYPE_RAW == event->attr.type)
+ mutex_unlock(&raw_event_mutex);
+ return PTR_ERR(pev);
+ }
+
+ /*
+ * We allow max flexibility on how each individual counter shared
+ * by the single CPU operates (the mode exclusion and the range).
+ */
+ hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE;
+
+ /* Calculate range bits and validate it. */
+ if (num_possible_cpus() > 1)
+ check_and_calc_range(event, pev);
+
+ hwc->event_base = mipspmu_perf_event_encode(pev);
+ if (PERF_TYPE_RAW == event->attr.type)
+ mutex_unlock(&raw_event_mutex);
+
+ if (!attr->exclude_user)
+ hwc->config_base |= M_PERFCTL_USER;
+ if (!attr->exclude_kernel) {
+ hwc->config_base |= M_PERFCTL_KERNEL;
+ /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */
+ hwc->config_base |= M_PERFCTL_EXL;
+ }
+ if (!attr->exclude_hv)
+ hwc->config_base |= M_PERFCTL_SUPERVISOR;
+
+ hwc->config_base &= M_PERFCTL_CONFIG_MASK;
+ /*
+ * The event can belong to another cpu. We do not assign a local
+ * counter for it for now.
+ */
+ hwc->idx = -1;
+ hwc->config = 0;
+
+ if (!hwc->sample_period) {
+ hwc->sample_period = MAX_PERIOD;
+ hwc->last_period = hwc->sample_period;
+ local64_set(&hwc->period_left, hwc->sample_period);
+ }
+
+ err = 0;
+ if (event->group_leader != event) {
+ err = validate_group(event);
+ if (err)
+ return -EINVAL;
+ }
+
+ event->destroy = hw_perf_event_destroy;
+
+ return err;
+}
+
+static void pause_local_counters(void)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ int counters = mipspmu->num_counters;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ switch (counters) {
+ case 4:
+ cpuc->saved_ctrl[3] = r_c0_perfctrl3();
+ w_c0_perfctrl3(cpuc->saved_ctrl[3] &
+ ~M_PERFCTL_COUNT_EVENT_WHENEVER);
+ case 3:
+ cpuc->saved_ctrl[2] = r_c0_perfctrl2();
+ w_c0_perfctrl2(cpuc->saved_ctrl[2] &
+ ~M_PERFCTL_COUNT_EVENT_WHENEVER);
+ case 2:
+ cpuc->saved_ctrl[1] = r_c0_perfctrl1();
+ w_c0_perfctrl1(cpuc->saved_ctrl[1] &
+ ~M_PERFCTL_COUNT_EVENT_WHENEVER);
+ case 1:
+ cpuc->saved_ctrl[0] = r_c0_perfctrl0();
+ w_c0_perfctrl0(cpuc->saved_ctrl[0] &
+ ~M_PERFCTL_COUNT_EVENT_WHENEVER);
+ }
+ local_irq_restore(flags);
+}
+
+static void resume_local_counters(void)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ int counters = mipspmu->num_counters;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ switch (counters) {
+ case 4:
+ w_c0_perfctrl3(cpuc->saved_ctrl[3]);
+ case 3:
+ w_c0_perfctrl2(cpuc->saved_ctrl[2]);
+ case 2:
+ w_c0_perfctrl1(cpuc->saved_ctrl[1]);
+ case 1:
+ w_c0_perfctrl0(cpuc->saved_ctrl[0]);
+ }
+ local_irq_restore(flags);
+}
+
+static int mipsxx_pmu_handle_shared_irq(void)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ struct perf_sample_data data;
+ unsigned int counters = mipspmu->num_counters;
+ unsigned int counter;
+ int handled = IRQ_NONE;
+ struct pt_regs *regs;
+
+ if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
+ return handled;
+
+ /*
+ * First we pause the local counters, so that when we are locked
+ * here, the counters are all paused. When it gets locked due to
+ * perf_disable(), the timer interrupt handler will be delayed.
+ *
+ * See also mipsxx_pmu_start().
+ */
+ pause_local_counters();
+#ifdef CONFIG_MIPS_MT_SMP
+ read_lock(&pmuint_rwlock);
+#endif
+
+ regs = get_irq_regs();
+
+ perf_sample_data_init(&data, 0);
+
+ switch (counters) {
+#define HANDLE_COUNTER(n) \
+ case n + 1: \
+ if (test_bit(n, cpuc->used_mask)) { \
+ counter = r_c0_perfcntr ## n(); \
+ if (counter & M_COUNTER_OVERFLOW) { \
+ w_c0_perfcntr ## n(counter & \
+ VALID_COUNT); \
+ if (test_and_change_bit(n, cpuc->msbs)) \
+ handle_associated_event(cpuc, \
+ n, &data, regs); \
+ handled = IRQ_HANDLED; \
+ } \
+ }
+ HANDLE_COUNTER(3)
+ HANDLE_COUNTER(2)
+ HANDLE_COUNTER(1)
+ HANDLE_COUNTER(0)
+ }
+
+ /*
+ * Do all the work for the pending perf events. We can do this
+ * in here because the performance counter interrupt is a regular
+ * interrupt, not NMI.
+ */
+ if (handled == IRQ_HANDLED)
+ perf_event_do_pending();
+
+#ifdef CONFIG_MIPS_MT_SMP
+ read_unlock(&pmuint_rwlock);
+#endif
+ resume_local_counters();
+ return handled;
+}
+
+static irqreturn_t
+mipsxx_pmu_handle_irq(int irq, void *dev)
+{
+ return mipsxx_pmu_handle_shared_irq();
+}
+
+static void mipsxx_pmu_start(void)
+{
+#ifdef CONFIG_MIPS_MT_SMP
+ write_unlock(&pmuint_rwlock);
+#endif
+ resume_local_counters();
+}
+
+/*
+ * MIPS performance counters can be per-TC. The control registers can
+ * not be directly accessed accross CPUs. Hence if we want to do global
+ * control, we need cross CPU calls. on_each_cpu() can help us, but we
+ * can not make sure this function is called with interrupts enabled. So
+ * here we pause local counters and then grab a rwlock and leave the
+ * counters on other CPUs alone. If any counter interrupt raises while
+ * we own the write lock, simply pause local counters on that CPU and
+ * spin in the handler. Also we know we won't be switched to another
+ * CPU after pausing local counters and before grabbing the lock.
+ */
+static void mipsxx_pmu_stop(void)
+{
+ pause_local_counters();
+#ifdef CONFIG_MIPS_MT_SMP
+ write_lock(&pmuint_rwlock);
+#endif
+}
+
+static int
+mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
+ struct hw_perf_event *hwc)
+{
+ int i;
+
+ /*
+ * We only need to care the counter mask. The range has been
+ * checked definitely.
+ */
+ unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff;
+
+ for (i = mipspmu->num_counters - 1; i >= 0; i--) {
+ /*
+ * Note that some MIPS perf events can be counted by both
+ * even and odd counters, wheresas many other are only by
+ * even _or_ odd counters. This introduces an issue that
+ * when the former kind of event takes the counter the
+ * latter kind of event wants to use, then the "counter
+ * allocation" for the latter event will fail. In fact if
+ * they can be dynamically swapped, they both feel happy.
+ * But here we leave this issue alone for now.
+ */
+ if (test_bit(i, &cntr_mask) &&
+ !test_and_set_bit(i, cpuc->used_mask))
+ return i;
+ }
+
+ return -EAGAIN;
+}
+
+static void
+mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ unsigned long flags;
+
+ WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
+
+ local_irq_save(flags);
+ cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
+ (evt->config_base & M_PERFCTL_CONFIG_MASK) |
+ /* Make sure interrupt enabled. */
+ M_PERFCTL_INTERRUPT_ENABLE;
+ /*
+ * We do not actually let the counter run. Leave it until start().
+ */
+ local_irq_restore(flags);
+}
+
+static void
+mipsxx_pmu_disable_event(int idx)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ unsigned long flags;
+
+ WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
+
+ local_irq_save(flags);
+ cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) &
+ ~M_PERFCTL_COUNT_EVENT_WHENEVER;
+ mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);
+ local_irq_restore(flags);
+}
+
+/* 24K */
+#define IS_UNSUPPORTED_24K_EVENT(r, b) \
+ ((b) == 12 || (r) == 151 || (r) == 152 || (b) == 26 || \
+ (b) == 27 || (r) == 28 || (r) == 158 || (b) == 31 || \
+ (b) == 32 || (b) == 34 || (b) == 36 || (r) == 168 || \
+ (r) == 172 || (b) == 47 || ((b) >= 56 && (b) <= 63) || \
+ ((b) >= 68 && (b) <= 127))
+#define IS_BOTH_COUNTERS_24K_EVENT(b) \
+ ((b) == 0 || (b) == 1 || (b) == 11)
+
+/* 34K */
+#define IS_UNSUPPORTED_34K_EVENT(r, b) \
+ ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 36 || \
+ (b) == 38 || (r) == 175 || ((b) >= 56 && (b) <= 63) || \
+ ((b) >= 68 && (b) <= 127))
+#define IS_BOTH_COUNTERS_34K_EVENT(b) \
+ ((b) == 0 || (b) == 1 || (b) == 11)
+#ifdef CONFIG_MIPS_MT_SMP
+#define IS_RANGE_P_34K_EVENT(r, b) \
+ ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
+ (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 || \
+ (r) == 176 || ((b) >= 50 && (b) <= 55) || \
+ ((b) >= 64 && (b) <= 67))
+#define IS_RANGE_V_34K_EVENT(r) ((r) == 47)
+#endif
+
+/* 74K */
+#define IS_UNSUPPORTED_74K_EVENT(r, b) \
+ ((r) == 5 || ((r) >= 135 && (r) <= 137) || \
+ ((b) >= 10 && (b) <= 12) || (b) == 22 || (b) == 27 || \
+ (b) == 33 || (b) == 34 || ((b) >= 47 && (b) <= 49) || \
+ (r) == 178 || (b) == 55 || (b) == 57 || (b) == 60 || \
+ (b) == 61 || (r) == 62 || (r) == 191 || \
+ ((b) >= 64 && (b) <= 127))
+#define IS_BOTH_COUNTERS_74K_EVENT(b) \
+ ((b) == 0 || (b) == 1)
+
+/* 1004K */
+#define IS_UNSUPPORTED_1004K_EVENT(r, b) \
+ ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 38 || \
+ (r) == 175 || (b) == 63 || ((b) >= 68 && (b) <= 127))
+#define IS_BOTH_COUNTERS_1004K_EVENT(b) \
+ ((b) == 0 || (b) == 1 || (b) == 11)
+#ifdef CONFIG_MIPS_MT_SMP
+#define IS_RANGE_P_1004K_EVENT(r, b) \
+ ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
+ (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 || \
+ (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) || \
+ (r) == 188 || (b) == 61 || (b) == 62 || \
+ ((b) >= 64 && (b) <= 67))
+#define IS_RANGE_V_1004K_EVENT(r) ((r) == 47)
+#endif
+
+/*
+ * User can use 0-255 raw events, where 0-127 for the events of even
+ * counters, and 128-255 for odd counters. Note that bit 7 is used to
+ * indicate the parity. So, for example, when user wants to take the
+ * Event Num of 15 for odd counters (by referring to the user manual),
+ * then 128 needs to be added to 15 as the input for the event config,
+ * i.e., 143 (0x8F) to be used.
+ */
+static const struct mips_perf_event *
+mipsxx_pmu_map_raw_event(u64 config)
+{
+ unsigned int raw_id = config & 0xff;
+ unsigned int base_id = raw_id & 0x7f;
+
+ switch (current_cpu_type()) {
+ case CPU_24K:
+ if (IS_UNSUPPORTED_24K_EVENT(raw_id, base_id))
+ return ERR_PTR(-EOPNOTSUPP);
+ raw_event.event_id = base_id;
+ if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
+ raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+ else
+ raw_event.cntr_mask =
+ raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+ /*
+ * This is actually doing nothing. Non-multithreading
+ * CPUs will not check and calculate the range.
+ */
+ raw_event.range = P;
+#endif
+ break;
+ case CPU_34K:
+ if (IS_UNSUPPORTED_34K_EVENT(raw_id, base_id))
+ return ERR_PTR(-EOPNOTSUPP);
+ raw_event.event_id = base_id;
+ if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
+ raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+ else
+ raw_event.cntr_mask =
+ raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+ if (IS_RANGE_P_34K_EVENT(raw_id, base_id))
+ raw_event.range = P;
+ else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id)))
+ raw_event.range = V;
+ else
+ raw_event.range = T;
+#endif
+ break;
+ case CPU_74K:
+ if (IS_UNSUPPORTED_74K_EVENT(raw_id, base_id))
+ return ERR_PTR(-EOPNOTSUPP);
+ raw_event.event_id = base_id;
+ if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
+ raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+ else
+ raw_event.cntr_mask =
+ raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+ raw_event.range = P;
+#endif
+ break;
+ case CPU_1004K:
+ if (IS_UNSUPPORTED_1004K_EVENT(raw_id, base_id))
+ return ERR_PTR(-EOPNOTSUPP);
+ raw_event.event_id = base_id;
+ if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
+ raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+ else
+ raw_event.cntr_mask =
+ raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+ if (IS_RANGE_P_1004K_EVENT(raw_id, base_id))
+ raw_event.range = P;
+ else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id)))
+ raw_event.range = V;
+ else
+ raw_event.range = T;
+#endif
+ break;
+ }
+
+ return &raw_event;
+}
+
+static struct mips_pmu mipsxxcore_pmu = {
+ .handle_irq = mipsxx_pmu_handle_irq,
+ .handle_shared_irq = mipsxx_pmu_handle_shared_irq,
+ .start = mipsxx_pmu_start,
+ .stop = mipsxx_pmu_stop,
+ .alloc_counter = mipsxx_pmu_alloc_counter,
+ .read_counter = mipsxx_pmu_read_counter,
+ .write_counter = mipsxx_pmu_write_counter,
+ .enable_event = mipsxx_pmu_enable_event,
+ .disable_event = mipsxx_pmu_disable_event,
+ .map_raw_event = mipsxx_pmu_map_raw_event,
+ .general_event_map = &mipsxxcore_event_map,
+ .cache_event_map = &mipsxxcore_cache_map,
+};
+
+static struct mips_pmu mipsxx74Kcore_pmu = {
+ .handle_irq = mipsxx_pmu_handle_irq,
+ .handle_shared_irq = mipsxx_pmu_handle_shared_irq,
+ .start = mipsxx_pmu_start,
+ .stop = mipsxx_pmu_stop,
+ .alloc_counter = mipsxx_pmu_alloc_counter,
+ .read_counter = mipsxx_pmu_read_counter,
+ .write_counter = mipsxx_pmu_write_counter,
+ .enable_event = mipsxx_pmu_enable_event,
+ .disable_event = mipsxx_pmu_disable_event,
+ .map_raw_event = mipsxx_pmu_map_raw_event,
+ .general_event_map = &mipsxx74Kcore_event_map,
+ .cache_event_map = &mipsxx74Kcore_cache_map,
+};
+
+static int __init
+init_hw_perf_events(void)
+{
+ int counters, irq;
+
+ pr_info("Performance counters: ");
+
+ counters = n_counters();
+ if (counters == 0) {
+ pr_cont("No available PMU.\n");
+ return -ENODEV;
+ }
+
+#ifdef CONFIG_MIPS_MT_SMP
+ cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
+ if (!cpu_has_mipsmt_pertccounters)
+ counters = counters_total_to_per_cpu(counters);
+#endif
+
+#ifdef MSC01E_INT_BASE
+ if (cpu_has_veic) {
+ /*
+ * Using platform specific interrupt controller defines.
+ */
+ irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
+ } else {
+#endif
+ if (cp0_perfcount_irq >= 0)
+ irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
+ else
+ irq = -1;
+#ifdef MSC01E_INT_BASE
+ }
+#endif
+
+ on_each_cpu(reset_counters, (void *)(long)counters, 1);
+
+ switch (current_cpu_type()) {
+ case CPU_24K:
+ mipsxxcore_pmu.name = "mips/24K";
+ mipsxxcore_pmu.num_counters = counters;
+ mipsxxcore_pmu.irq = irq;
+ mipspmu = &mipsxxcore_pmu;
+ break;
+ case CPU_34K:
+ mipsxxcore_pmu.name = "mips/34K";
+ mipsxxcore_pmu.num_counters = counters;
+ mipsxxcore_pmu.irq = irq;
+ mipspmu = &mipsxxcore_pmu;
+ break;
+ case CPU_74K:
+ mipsxx74Kcore_pmu.name = "mips/74K";
+ mipsxx74Kcore_pmu.num_counters = counters;
+ mipsxx74Kcore_pmu.irq = irq;
+ mipspmu = &mipsxx74Kcore_pmu;
+ break;
+ case CPU_1004K:
+ mipsxxcore_pmu.name = "mips/1004K";
+ mipsxxcore_pmu.num_counters = counters;
+ mipsxxcore_pmu.irq = irq;
+ mipspmu = &mipsxxcore_pmu;
+ break;
+ default:
+ pr_cont("Either hardware does not support performance "
+ "counters, or not yet implemented.\n");
+ return -ENODEV;
+ }
+
+ if (mipspmu)
+ pr_cont("%s PMU enabled, %d counters available to each "
+ "CPU, irq %d%s\n", mipspmu->name, counters, irq,
+ irq < 0 ? " (share with timer interrupt)" : "");
+
+ return 0;
+}
+arch_initcall(init_hw_perf_events);
+
+#endif /* defined(CONFIG_CPU_MIPS32)... */
diff --git a/trunk/arch/mips/kernel/setup.c b/trunk/arch/mips/kernel/setup.c
index a6b900f2962b..acd3f2c49c06 100644
--- a/trunk/arch/mips/kernel/setup.c
+++ b/trunk/arch/mips/kernel/setup.c
@@ -490,6 +490,7 @@ static void __init arch_mem_init(char **cmdline_p)
bootmem_init();
device_tree_init();
sparse_init();
+ plat_swiotlb_setup();
paging_init();
}
diff --git a/trunk/arch/mips/kernel/traps.c b/trunk/arch/mips/kernel/traps.c
index d053bf4759e4..8e9fbe75894e 100644
--- a/trunk/arch/mips/kernel/traps.c
+++ b/trunk/arch/mips/kernel/traps.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include
#include
@@ -576,10 +577,16 @@ static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
*/
static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
{
- if ((opcode & OPCODE) == LL)
+ if ((opcode & OPCODE) == LL) {
+ perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+ 1, 0, regs, 0);
return simulate_ll(regs, opcode);
- if ((opcode & OPCODE) == SC)
+ }
+ if ((opcode & OPCODE) == SC) {
+ perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+ 1, 0, regs, 0);
return simulate_sc(regs, opcode);
+ }
return -1; /* Must be something else ... */
}
@@ -595,6 +602,8 @@ static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
int rd = (opcode & RD) >> 11;
int rt = (opcode & RT) >> 16;
+ perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+ 1, 0, regs, 0);
switch (rd) {
case 0: /* CPU number */
regs->regs[rt] = smp_processor_id();
@@ -630,8 +639,11 @@ static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
{
- if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC)
+ if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
+ perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+ 1, 0, regs, 0);
return 0;
+ }
return -1; /* Must be something else ... */
}
@@ -1469,6 +1481,7 @@ void __cpuinit per_cpu_trap_init(void)
{
unsigned int cpu = smp_processor_id();
unsigned int status_set = ST0_CU0;
+ unsigned int hwrena = cpu_hwrena_impl_bits;
#ifdef CONFIG_MIPS_MT_SMTC
int secondaryTC = 0;
int bootTC = (cpu == 0);
@@ -1501,14 +1514,14 @@ void __cpuinit per_cpu_trap_init(void)
change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
status_set);
- if (cpu_has_mips_r2) {
- unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits;
+ if (cpu_has_mips_r2)
+ hwrena |= 0x0000000f;
- if (!noulri && cpu_has_userlocal)
- enable |= (1 << 29);
+ if (!noulri && cpu_has_userlocal)
+ hwrena |= (1 << 29);
- write_c0_hwrena(enable);
- }
+ if (hwrena)
+ write_c0_hwrena(hwrena);
#ifdef CONFIG_MIPS_MT_SMTC
if (!secondaryTC) {
diff --git a/trunk/arch/mips/kernel/unaligned.c b/trunk/arch/mips/kernel/unaligned.c
index 33d5a5ce4a29..cfea1adfa153 100644
--- a/trunk/arch/mips/kernel/unaligned.c
+++ b/trunk/arch/mips/kernel/unaligned.c
@@ -78,6 +78,8 @@
#include
#include
#include
+#include
+
#include
#include
#include
@@ -109,6 +111,9 @@ static void emulate_load_store_insn(struct pt_regs *regs,
unsigned long value;
unsigned int res;
+ perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+ 1, 0, regs, 0);
+
/*
* This load never faults.
*/
@@ -511,6 +516,8 @@ asmlinkage void do_ade(struct pt_regs *regs)
unsigned int __user *pc;
mm_segment_t seg;
+ perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
+ 1, 0, regs, regs->cp0_badvaddr);
/*
* Did we catch a fault trying to load an instruction?
* Or are we running in MIPS16 mode?
diff --git a/trunk/arch/mips/loongson/Kconfig b/trunk/arch/mips/loongson/Kconfig
index c97ca69b94e0..6e1b77fec7ea 100644
--- a/trunk/arch/mips/loongson/Kconfig
+++ b/trunk/arch/mips/loongson/Kconfig
@@ -20,7 +20,6 @@ config LEMOTE_FULOONG2E
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_HAS_EARLY_PRINTK
- select GENERIC_HARDIRQS_NO__DO_IRQ
select GENERIC_ISA_DMA_SUPPORT_BROKEN
select CPU_HAS_WB
select LOONGSON_MC146818
@@ -40,7 +39,6 @@ config LEMOTE_MACH2F
select CS5536
select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
select DMA_NONCOHERENT
- select GENERIC_HARDIRQS_NO__DO_IRQ
select GENERIC_ISA_DMA_SUPPORT_BROKEN
select HW_HAS_PCI
select I8259
diff --git a/trunk/arch/mips/math-emu/cp1emu.c b/trunk/arch/mips/math-emu/cp1emu.c
index ec3faa413f3b..b2ad1b0910ff 100644
--- a/trunk/arch/mips/math-emu/cp1emu.c
+++ b/trunk/arch/mips/math-emu/cp1emu.c
@@ -36,6 +36,7 @@
#include
#include
#include
+#include
#include
#include
@@ -258,6 +259,8 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
}
emul:
+ perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+ 1, 0, xcp, 0);
MIPS_FPU_EMU_INC_STATS(emulated);
switch (MIPSInst_OPCODE(ir)) {
case ldc1_op:{
diff --git a/trunk/arch/mips/mm/c-octeon.c b/trunk/arch/mips/mm/c-octeon.c
index 0f9c488044d1..16c4d256b76f 100644
--- a/trunk/arch/mips/mm/c-octeon.c
+++ b/trunk/arch/mips/mm/c-octeon.c
@@ -181,10 +181,10 @@ static void __cpuinit probe_octeon(void)
unsigned int config1;
struct cpuinfo_mips *c = ¤t_cpu_data;
+ config1 = read_c0_config1();
switch (c->cputype) {
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
- config1 = read_c0_config1();
c->icache.linesz = 2 << ((config1 >> 19) & 7);
c->icache.sets = 64 << ((config1 >> 22) & 7);
c->icache.ways = 1 + ((config1 >> 16) & 7);
@@ -204,6 +204,20 @@ static void __cpuinit probe_octeon(void)
c->options |= MIPS_CPU_PREFETCH;
break;
+ case CPU_CAVIUM_OCTEON2:
+ c->icache.linesz = 2 << ((config1 >> 19) & 7);
+ c->icache.sets = 8;
+ c->icache.ways = 37;
+ c->icache.flags |= MIPS_CACHE_VTAG;
+ icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
+
+ c->dcache.linesz = 128;
+ c->dcache.ways = 32;
+ c->dcache.sets = 8;
+ dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
+ c->options |= MIPS_CPU_PREFETCH;
+ break;
+
default:
panic("Unsupported Cavium Networks CPU type\n");
break;
diff --git a/trunk/arch/mips/mm/c-r4k.c b/trunk/arch/mips/mm/c-r4k.c
index 6721ee2b1e8b..b4923a75cb4b 100644
--- a/trunk/arch/mips/mm/c-r4k.c
+++ b/trunk/arch/mips/mm/c-r4k.c
@@ -42,14 +42,14 @@
* o collapses to normal function call on UP kernels
* o collapses to normal function call on systems with a single shared
* primary cache.
+ * o doesn't disable interrupts on the local CPU
*/
-static inline void r4k_on_each_cpu(void (*func) (void *info), void *info,
- int wait)
+static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
{
preempt_disable();
#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
- smp_call_function(func, info, wait);
+ smp_call_function(func, info, 1);
#endif
func(info);
preempt_enable();
@@ -363,7 +363,7 @@ static inline void local_r4k___flush_cache_all(void * args)
static void r4k___flush_cache_all(void)
{
- r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1);
+ r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
}
static inline int has_valid_asid(const struct mm_struct *mm)
@@ -410,7 +410,7 @@ static void r4k_flush_cache_range(struct vm_area_struct *vma,
int exec = vma->vm_flags & VM_EXEC;
if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
- r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1);
+ r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
}
static inline void local_r4k_flush_cache_mm(void * args)
@@ -442,7 +442,7 @@ static void r4k_flush_cache_mm(struct mm_struct *mm)
if (!cpu_has_dc_aliases)
return;
- r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1);
+ r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
}
struct flush_cache_page_args {
@@ -534,7 +534,7 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma,
args.addr = addr;
args.pfn = pfn;
- r4k_on_each_cpu(local_r4k_flush_cache_page, &args, 1);
+ r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
}
static inline void local_r4k_flush_data_cache_page(void * addr)
@@ -547,8 +547,7 @@ static void r4k_flush_data_cache_page(unsigned long addr)
if (in_atomic())
local_r4k_flush_data_cache_page((void *)addr);
else
- r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr,
- 1);
+ r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
}
struct flush_icache_range_args {
@@ -589,7 +588,7 @@ static void r4k_flush_icache_range(unsigned long start, unsigned long end)
args.start = start;
args.end = end;
- r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args, 1);
+ r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
instruction_hazard();
}
@@ -710,7 +709,7 @@ static void local_r4k_flush_cache_sigtramp(void * arg)
static void r4k_flush_cache_sigtramp(unsigned long addr)
{
- r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1);
+ r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
}
static void r4k_flush_icache_all(void)
diff --git a/trunk/arch/mips/mm/dma-default.c b/trunk/arch/mips/mm/dma-default.c
index 469d4019f795..4fc1a0fbe007 100644
--- a/trunk/arch/mips/mm/dma-default.c
+++ b/trunk/arch/mips/mm/dma-default.c
@@ -95,10 +95,9 @@ void *dma_alloc_noncoherent(struct device *dev, size_t size,
return ret;
}
-
EXPORT_SYMBOL(dma_alloc_noncoherent);
-void *dma_alloc_coherent(struct device *dev, size_t size,
+static void *mips_dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t * dma_handle, gfp_t gfp)
{
void *ret;
@@ -123,7 +122,6 @@ void *dma_alloc_coherent(struct device *dev, size_t size,
return ret;
}
-EXPORT_SYMBOL(dma_alloc_coherent);
void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
dma_addr_t dma_handle)
@@ -131,10 +129,9 @@ void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
free_pages((unsigned long) vaddr, get_order(size));
}
-
EXPORT_SYMBOL(dma_free_noncoherent);
-void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
+static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
dma_addr_t dma_handle)
{
unsigned long addr = (unsigned long) vaddr;
@@ -151,8 +148,6 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
free_pages(addr, get_order(size));
}
-EXPORT_SYMBOL(dma_free_coherent);
-
static inline void __dma_sync(unsigned long addr, size_t size,
enum dma_data_direction direction)
{
@@ -174,21 +169,8 @@ static inline void __dma_sync(unsigned long addr, size_t size,
}
}
-dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
- enum dma_data_direction direction)
-{
- unsigned long addr = (unsigned long) ptr;
-
- if (!plat_device_is_coherent(dev))
- __dma_sync(addr, size, direction);
-
- return plat_map_dma_mem(dev, ptr, size);
-}
-
-EXPORT_SYMBOL(dma_map_single);
-
-void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
- enum dma_data_direction direction)
+static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
+ size_t size, enum dma_data_direction direction, struct dma_attrs *attrs)
{
if (cpu_is_noncoherent_r10000(dev))
__dma_sync(dma_addr_to_virt(dev, dma_addr), size,
@@ -197,15 +179,11 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
plat_unmap_dma_mem(dev, dma_addr, size, direction);
}
-EXPORT_SYMBOL(dma_unmap_single);
-
-int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
- enum dma_data_direction direction)
+static int mips_dma_map_sg(struct device *dev, struct scatterlist *sg,
+ int nents, enum dma_data_direction direction, struct dma_attrs *attrs)
{
int i;
- BUG_ON(direction == DMA_NONE);
-
for (i = 0; i < nents; i++, sg++) {
unsigned long addr;
@@ -219,33 +197,27 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
return nents;
}
-EXPORT_SYMBOL(dma_map_sg);
-
-dma_addr_t dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size, enum dma_data_direction direction)
+static dma_addr_t mips_dma_map_page(struct device *dev, struct page *page,
+ unsigned long offset, size_t size, enum dma_data_direction direction,
+ struct dma_attrs *attrs)
{
- BUG_ON(direction == DMA_NONE);
+ unsigned long addr;
- if (!plat_device_is_coherent(dev)) {
- unsigned long addr;
+ addr = (unsigned long) page_address(page) + offset;
- addr = (unsigned long) page_address(page) + offset;
+ if (!plat_device_is_coherent(dev))
__dma_sync(addr, size, direction);
- }
- return plat_map_dma_mem_page(dev, page) + offset;
+ return plat_map_dma_mem(dev, (void *)addr, size);
}
-EXPORT_SYMBOL(dma_map_page);
-
-void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
- enum dma_data_direction direction)
+static void mips_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+ int nhwentries, enum dma_data_direction direction,
+ struct dma_attrs *attrs)
{
unsigned long addr;
int i;
- BUG_ON(direction == DMA_NONE);
-
for (i = 0; i < nhwentries; i++, sg++) {
if (!plat_device_is_coherent(dev) &&
direction != DMA_TO_DEVICE) {
@@ -257,13 +229,9 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
}
}
-EXPORT_SYMBOL(dma_unmap_sg);
-
-void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
- size_t size, enum dma_data_direction direction)
+static void mips_dma_sync_single_for_cpu(struct device *dev,
+ dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
{
- BUG_ON(direction == DMA_NONE);
-
if (cpu_is_noncoherent_r10000(dev)) {
unsigned long addr;
@@ -272,13 +240,9 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
}
}
-EXPORT_SYMBOL(dma_sync_single_for_cpu);
-
-void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
- size_t size, enum dma_data_direction direction)
+static void mips_dma_sync_single_for_device(struct device *dev,
+ dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
{
- BUG_ON(direction == DMA_NONE);
-
plat_extra_sync_for_device(dev);
if (!plat_device_is_coherent(dev)) {
unsigned long addr;
@@ -288,46 +252,11 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
}
}
-EXPORT_SYMBOL(dma_sync_single_for_device);
-
-void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
- unsigned long offset, size_t size, enum dma_data_direction direction)
-{
- BUG_ON(direction == DMA_NONE);
-
- if (cpu_is_noncoherent_r10000(dev)) {
- unsigned long addr;
-
- addr = dma_addr_to_virt(dev, dma_handle);
- __dma_sync(addr + offset, size, direction);
- }
-}
-
-EXPORT_SYMBOL(dma_sync_single_range_for_cpu);
-
-void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
- unsigned long offset, size_t size, enum dma_data_direction direction)
-{
- BUG_ON(direction == DMA_NONE);
-
- plat_extra_sync_for_device(dev);
- if (!plat_device_is_coherent(dev)) {
- unsigned long addr;
-
- addr = dma_addr_to_virt(dev, dma_handle);
- __dma_sync(addr + offset, size, direction);
- }
-}
-
-EXPORT_SYMBOL(dma_sync_single_range_for_device);
-
-void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
- enum dma_data_direction direction)
+static void mips_dma_sync_sg_for_cpu(struct device *dev,
+ struct scatterlist *sg, int nelems, enum dma_data_direction direction)
{
int i;
- BUG_ON(direction == DMA_NONE);
-
/* Make sure that gcc doesn't leave the empty loop body. */
for (i = 0; i < nelems; i++, sg++) {
if (cpu_is_noncoherent_r10000(dev))
@@ -336,15 +265,11 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
}
}
-EXPORT_SYMBOL(dma_sync_sg_for_cpu);
-
-void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
- enum dma_data_direction direction)
+static void mips_dma_sync_sg_for_device(struct device *dev,
+ struct scatterlist *sg, int nelems, enum dma_data_direction direction)
{
int i;
- BUG_ON(direction == DMA_NONE);
-
/* Make sure that gcc doesn't leave the empty loop body. */
for (i = 0; i < nelems; i++, sg++) {
if (!plat_device_is_coherent(dev))
@@ -353,24 +278,18 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nele
}
}
-EXPORT_SYMBOL(dma_sync_sg_for_device);
-
-int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
return plat_dma_mapping_error(dev, dma_addr);
}
-EXPORT_SYMBOL(dma_mapping_error);
-
-int dma_supported(struct device *dev, u64 mask)
+int mips_dma_supported(struct device *dev, u64 mask)
{
return plat_dma_supported(dev, mask);
}
-EXPORT_SYMBOL(dma_supported);
-
-void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
- enum dma_data_direction direction)
+void mips_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
+ enum dma_data_direction direction)
{
BUG_ON(direction == DMA_NONE);
@@ -379,4 +298,30 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
__dma_sync((unsigned long)vaddr, size, direction);
}
-EXPORT_SYMBOL(dma_cache_sync);
+static struct dma_map_ops mips_default_dma_map_ops = {
+ .alloc_coherent = mips_dma_alloc_coherent,
+ .free_coherent = mips_dma_free_coherent,
+ .map_page = mips_dma_map_page,
+ .unmap_page = mips_dma_unmap_page,
+ .map_sg = mips_dma_map_sg,
+ .unmap_sg = mips_dma_unmap_sg,
+ .sync_single_for_cpu = mips_dma_sync_single_for_cpu,
+ .sync_single_for_device = mips_dma_sync_single_for_device,
+ .sync_sg_for_cpu = mips_dma_sync_sg_for_cpu,
+ .sync_sg_for_device = mips_dma_sync_sg_for_device,
+ .mapping_error = mips_dma_mapping_error,
+ .dma_supported = mips_dma_supported
+};
+
+struct dma_map_ops *mips_dma_map_ops = &mips_default_dma_map_ops;
+EXPORT_SYMBOL(mips_dma_map_ops);
+
+#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
+
+static int __init mips_dma_init(void)
+{
+ dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
+
+ return 0;
+}
+fs_initcall(mips_dma_init);
diff --git a/trunk/arch/mips/mm/fault.c b/trunk/arch/mips/mm/fault.c
index 783ad0065fdf..137ee76a0045 100644
--- a/trunk/arch/mips/mm/fault.c
+++ b/trunk/arch/mips/mm/fault.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
@@ -144,6 +145,7 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, unsigned long writ
* the fault.
*/
fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0);
+ perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
if (unlikely(fault & VM_FAULT_ERROR)) {
if (fault & VM_FAULT_OOM)
goto out_of_memory;
@@ -151,10 +153,15 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, unsigned long writ
goto do_sigbus;
BUG();
}
- if (fault & VM_FAULT_MAJOR)
+ if (fault & VM_FAULT_MAJOR) {
+ perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ,
+ 1, 0, regs, address);
tsk->maj_flt++;
- else
+ } else {
+ perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN,
+ 1, 0, regs, address);
tsk->min_flt++;
+ }
up_read(&mm->mmap_sem);
return;
diff --git a/trunk/arch/mips/mm/sc-mips.c b/trunk/arch/mips/mm/sc-mips.c
index 5ab5fa8c1d82..505fecad4684 100644
--- a/trunk/arch/mips/mm/sc-mips.c
+++ b/trunk/arch/mips/mm/sc-mips.c
@@ -57,6 +57,34 @@ static struct bcache_ops mips_sc_ops = {
.bc_inv = mips_sc_inv
};
+/*
+ * Check if the L2 cache controller is activated on a particular platform.
+ * MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
+ * cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
+ * cache being disabled. However there is no guarantee for this to be
+ * true on all platforms. In an act of stupidity the spec defined bits
+ * 12..15 as implementation defined so below function will eventually have
+ * to be replaced by a platform specific probe.
+ */
+static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
+{
+ /* Check the bypass bit (L2B) */
+ switch (c->cputype) {
+ case CPU_34K:
+ case CPU_74K:
+ case CPU_1004K:
+ case CPU_BMIPS5000:
+ if (config2 & (1 << 12))
+ return 0;
+ }
+
+ tmp = (config2 >> 4) & 0x0f;
+ if (0 < tmp && tmp <= 7)
+ c->scache.linesz = 2 << tmp;
+ else
+ return 0;
+}
+
static inline int __init mips_sc_probe(void)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
@@ -79,10 +107,8 @@ static inline int __init mips_sc_probe(void)
return 0;
config2 = read_c0_config2();
- tmp = (config2 >> 4) & 0x0f;
- if (0 < tmp && tmp <= 7)
- c->scache.linesz = 2 << tmp;
- else
+
+ if (!mips_sc_is_activated(c))
return 0;
tmp = (config2 >> 8) & 0x0f;
diff --git a/trunk/arch/mips/mm/tlbex.c b/trunk/arch/mips/mm/tlbex.c
index 4510e61883eb..93816f3bca67 100644
--- a/trunk/arch/mips/mm/tlbex.c
+++ b/trunk/arch/mips/mm/tlbex.c
@@ -338,13 +338,12 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_4KSC:
case CPU_20KC:
case CPU_25KF:
- case CPU_BCM3302:
- case CPU_BCM4710:
+ case CPU_BMIPS32:
+ case CPU_BMIPS3300:
+ case CPU_BMIPS4350:
+ case CPU_BMIPS4380:
+ case CPU_BMIPS5000:
case CPU_LOONGSON2:
- case CPU_BCM6338:
- case CPU_BCM6345:
- case CPU_BCM6348:
- case CPU_BCM6358:
case CPU_R5500:
if (m4kc_tlbp_war())
uasm_i_nop(p);
diff --git a/trunk/arch/mips/mm/uasm.c b/trunk/arch/mips/mm/uasm.c
index d2647a4e012b..23afdebc8e5c 100644
--- a/trunk/arch/mips/mm/uasm.c
+++ b/trunk/arch/mips/mm/uasm.c
@@ -405,7 +405,6 @@ I_u1u2u3(_mfc0)
I_u1u2u3(_mtc0)
I_u2u1u3(_ori)
I_u3u1u2(_or)
-I_u2s3u1(_pref)
I_0(_rfe)
I_u2s3u1(_sc)
I_u2s3u1(_scd)
@@ -427,6 +426,25 @@ I_u1(_syscall);
I_u1u2s3(_bbit0);
I_u1u2s3(_bbit1);
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#include
+void __uasminit uasm_i_pref(u32 **buf, unsigned int a, signed int b,
+ unsigned int c)
+{
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
+ /*
+ * As per erratum Core-14449, replace prefetches 0-4,
+ * 6-24 with 'pref 28'.
+ */
+ build_insn(buf, insn_pref, c, 28, b);
+ else
+ build_insn(buf, insn_pref, c, a, b);
+}
+UASM_EXPORT_SYMBOL(uasm_i_pref);
+#else
+I_u2s3u1(_pref)
+#endif
+
/* Handle labels. */
void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
{
diff --git a/trunk/arch/mips/pci/pci-octeon.c b/trunk/arch/mips/pci/pci-octeon.c
index d248b707eff3..2d74fc9ae3ba 100644
--- a/trunk/arch/mips/pci/pci-octeon.c
+++ b/trunk/arch/mips/pci/pci-octeon.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
@@ -19,6 +20,8 @@
#include
#include
+#include
+
#define USE_OCTEON_INTERNAL_ARBITER
/*
@@ -32,6 +35,8 @@
/* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
#define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull)
+u64 octeon_bar1_pci_phys;
+
/**
* This is the bit decoding used for the Octeon PCI controller addresses
*/
@@ -170,6 +175,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
}
+ dev->dev.archdata.dma_ops = octeon_pci_dma_map_ops;
+
return 0;
}
@@ -618,12 +625,10 @@ static int __init octeon_pci_setup(void)
* before the readl()'s below. We don't want BAR2 overlapping
* with BAR0/BAR1 during these reads.
*/
- octeon_npi_write32(CVMX_NPI_PCI_CFG08, 0);
- octeon_npi_write32(CVMX_NPI_PCI_CFG09, 0x80);
-
- /* Disable the BAR1 movable mappings */
- for (index = 0; index < 32; index++)
- octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
+ octeon_npi_write32(CVMX_NPI_PCI_CFG08,
+ (u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull));
+ octeon_npi_write32(CVMX_NPI_PCI_CFG09,
+ (u32)(OCTEON_BAR2_PCI_ADDRESS >> 32));
if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
/* Remap the Octeon BAR 0 to 0-2GB */
@@ -637,6 +642,25 @@ static int __init octeon_pci_setup(void)
octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
+ /* BAR1 movable mappings set for identity mapping */
+ octeon_bar1_pci_phys = 0x80000000ull;
+ for (index = 0; index < 32; index++) {
+ union cvmx_pci_bar1_indexx bar1_index;
+
+ bar1_index.u32 = 0;
+ /* Address bits[35:22] sent to L2C */
+ bar1_index.s.addr_idx =
+ (octeon_bar1_pci_phys >> 22) + index;
+ /* Don't put PCI accesses in L2. */
+ bar1_index.s.ca = 1;
+ /* Endian Swap Mode */
+ bar1_index.s.end_swp = 1;
+ /* Set '1' when the selected address range is valid. */
+ bar1_index.s.addr_v = 1;
+ octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
+ bar1_index.u32);
+ }
+
/* Devices go after BAR1 */
octeon_pci_mem_resource.start =
OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
@@ -652,6 +676,27 @@ static int __init octeon_pci_setup(void)
octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
+ /* BAR1 movable regions contiguous to cover the swiotlb */
+ octeon_bar1_pci_phys =
+ virt_to_phys(octeon_swiotlb) & ~((1ull << 22) - 1);
+
+ for (index = 0; index < 32; index++) {
+ union cvmx_pci_bar1_indexx bar1_index;
+
+ bar1_index.u32 = 0;
+ /* Address bits[35:22] sent to L2C */
+ bar1_index.s.addr_idx =
+ (octeon_bar1_pci_phys >> 22) + index;
+ /* Don't put PCI accesses in L2. */
+ bar1_index.s.ca = 1;
+ /* Endian Swap Mode */
+ bar1_index.s.end_swp = 1;
+ /* Set '1' when the selected address range is valid. */
+ bar1_index.s.addr_v = 1;
+ octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
+ bar1_index.u32);
+ }
+
/* Devices go after BAR0 */
octeon_pci_mem_resource.start =
OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
@@ -667,6 +712,9 @@ static int __init octeon_pci_setup(void)
* was setup properly.
*/
cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
+
+ octeon_pci_dma_init();
+
return 0;
}
diff --git a/trunk/arch/mips/pci/pcie-octeon.c b/trunk/arch/mips/pci/pcie-octeon.c
index 861361e0c9af..385f035b24e4 100644
--- a/trunk/arch/mips/pci/pcie-octeon.c
+++ b/trunk/arch/mips/pci/pcie-octeon.c
@@ -75,6 +75,8 @@ union cvmx_pcie_address {
} mem;
};
+#include
+
/**
* Return the Core virtual base address for PCIe IO access. IOs are
* read/written as an offset from this address.
@@ -1391,6 +1393,9 @@ static int __init octeon_pcie_setup(void)
cvmx_pcie_get_io_size(1) - 1;
register_pci_controller(&octeon_pcie1_controller);
}
+
+ octeon_pci_dma_init();
+
return 0;
}
diff --git a/trunk/arch/powerpc/include/asm/kgdb.h b/trunk/arch/powerpc/include/asm/kgdb.h
index edd217006d27..9db24e77b9f4 100644
--- a/trunk/arch/powerpc/include/asm/kgdb.h
+++ b/trunk/arch/powerpc/include/asm/kgdb.h
@@ -31,6 +31,7 @@ static inline void arch_kgdb_breakpoint(void)
asm(".long 0x7d821008"); /* twge r2, r2 */
}
#define CACHE_FLUSH_IS_SAFE 1
+#define DBG_MAX_REG_NUM 70
/* The number bytes of registers we have to save depends on a few
* things. For 64bit we default to not including vector registers and
diff --git a/trunk/arch/powerpc/kernel/kgdb.c b/trunk/arch/powerpc/kernel/kgdb.c
index 7f61a3ac787c..7a9db64f3f04 100644
--- a/trunk/arch/powerpc/kernel/kgdb.c
+++ b/trunk/arch/powerpc/kernel/kgdb.c
@@ -194,40 +194,6 @@ static int kgdb_dabr_match(struct pt_regs *regs)
ptr = (unsigned long *)ptr32; \
} while (0)
-
-void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
-{
- unsigned long *ptr = gdb_regs;
- int reg;
-
- memset(gdb_regs, 0, NUMREGBYTES);
-
- for (reg = 0; reg < 32; reg++)
- PACK64(ptr, regs->gpr[reg]);
-
-#ifdef CONFIG_FSL_BOOKE
-#ifdef CONFIG_SPE
- for (reg = 0; reg < 32; reg++)
- PACK64(ptr, current->thread.evr[reg]);
-#else
- ptr += 32;
-#endif
-#else
- /* fp registers not used by kernel, leave zero */
- ptr += 32 * 8 / sizeof(long);
-#endif
-
- PACK64(ptr, regs->nip);
- PACK64(ptr, regs->msr);
- PACK32(ptr, regs->ccr);
- PACK64(ptr, regs->link);
- PACK64(ptr, regs->ctr);
- PACK32(ptr, regs->xer);
-
- BUG_ON((unsigned long)ptr >
- (unsigned long)(((void *)gdb_regs) + NUMREGBYTES));
-}
-
void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
{
struct pt_regs *regs = (struct pt_regs *)(p->thread.ksp +
@@ -271,44 +237,140 @@ void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
(unsigned long)(((void *)gdb_regs) + NUMREGBYTES));
}
-#define UNPACK64(dest, ptr) do { dest = *(ptr++); } while (0)
+#define GDB_SIZEOF_REG sizeof(unsigned long)
+#define GDB_SIZEOF_REG_U32 sizeof(u32)
-#define UNPACK32(dest, ptr) do { \
- u32 *ptr32; \
- ptr32 = (u32 *)ptr; \
- dest = *(ptr32++); \
- ptr = (unsigned long *)ptr32; \
- } while (0)
+#ifdef CONFIG_FSL_BOOKE
+#define GDB_SIZEOF_FLOAT_REG sizeof(unsigned long)
+#else
+#define GDB_SIZEOF_FLOAT_REG sizeof(u64)
+#endif
-void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
+struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] =
{
- unsigned long *ptr = gdb_regs;
- int reg;
-
- for (reg = 0; reg < 32; reg++)
- UNPACK64(regs->gpr[reg], ptr);
+ { "r0", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[0]) },
+ { "r1", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[1]) },
+ { "r2", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[2]) },
+ { "r3", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[3]) },
+ { "r4", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[4]) },
+ { "r5", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[5]) },
+ { "r6", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[6]) },
+ { "r7", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[7]) },
+ { "r8", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[8]) },
+ { "r9", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[9]) },
+ { "r10", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[10]) },
+ { "r11", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[11]) },
+ { "r12", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[12]) },
+ { "r13", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[13]) },
+ { "r14", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[14]) },
+ { "r15", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[15]) },
+ { "r16", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[16]) },
+ { "r17", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[17]) },
+ { "r18", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[18]) },
+ { "r19", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[19]) },
+ { "r20", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[20]) },
+ { "r21", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[21]) },
+ { "r22", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[22]) },
+ { "r23", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[23]) },
+ { "r24", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[24]) },
+ { "r25", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[25]) },
+ { "r26", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[26]) },
+ { "r27", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[27]) },
+ { "r28", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[28]) },
+ { "r29", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[29]) },
+ { "r30", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[30]) },
+ { "r31", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[31]) },
+
+ { "f0", GDB_SIZEOF_FLOAT_REG, 0 },
+ { "f1", GDB_SIZEOF_FLOAT_REG, 1 },
+ { "f2", GDB_SIZEOF_FLOAT_REG, 2 },
+ { "f3", GDB_SIZEOF_FLOAT_REG, 3 },
+ { "f4", GDB_SIZEOF_FLOAT_REG, 4 },
+ { "f5", GDB_SIZEOF_FLOAT_REG, 5 },
+ { "f6", GDB_SIZEOF_FLOAT_REG, 6 },
+ { "f7", GDB_SIZEOF_FLOAT_REG, 7 },
+ { "f8", GDB_SIZEOF_FLOAT_REG, 8 },
+ { "f9", GDB_SIZEOF_FLOAT_REG, 9 },
+ { "f10", GDB_SIZEOF_FLOAT_REG, 10 },
+ { "f11", GDB_SIZEOF_FLOAT_REG, 11 },
+ { "f12", GDB_SIZEOF_FLOAT_REG, 12 },
+ { "f13", GDB_SIZEOF_FLOAT_REG, 13 },
+ { "f14", GDB_SIZEOF_FLOAT_REG, 14 },
+ { "f15", GDB_SIZEOF_FLOAT_REG, 15 },
+ { "f16", GDB_SIZEOF_FLOAT_REG, 16 },
+ { "f17", GDB_SIZEOF_FLOAT_REG, 17 },
+ { "f18", GDB_SIZEOF_FLOAT_REG, 18 },
+ { "f19", GDB_SIZEOF_FLOAT_REG, 19 },
+ { "f20", GDB_SIZEOF_FLOAT_REG, 20 },
+ { "f21", GDB_SIZEOF_FLOAT_REG, 21 },
+ { "f22", GDB_SIZEOF_FLOAT_REG, 22 },
+ { "f23", GDB_SIZEOF_FLOAT_REG, 23 },
+ { "f24", GDB_SIZEOF_FLOAT_REG, 24 },
+ { "f25", GDB_SIZEOF_FLOAT_REG, 25 },
+ { "f26", GDB_SIZEOF_FLOAT_REG, 26 },
+ { "f27", GDB_SIZEOF_FLOAT_REG, 27 },
+ { "f28", GDB_SIZEOF_FLOAT_REG, 28 },
+ { "f29", GDB_SIZEOF_FLOAT_REG, 29 },
+ { "f30", GDB_SIZEOF_FLOAT_REG, 30 },
+ { "f31", GDB_SIZEOF_FLOAT_REG, 31 },
+
+ { "pc", GDB_SIZEOF_REG, offsetof(struct pt_regs, nip) },
+ { "msr", GDB_SIZEOF_REG, offsetof(struct pt_regs, msr) },
+ { "cr", GDB_SIZEOF_REG_U32, offsetof(struct pt_regs, ccr) },
+ { "lr", GDB_SIZEOF_REG, offsetof(struct pt_regs, link) },
+ { "ctr", GDB_SIZEOF_REG_U32, offsetof(struct pt_regs, ctr) },
+ { "xer", GDB_SIZEOF_REG, offsetof(struct pt_regs, xer) },
+};
-#ifdef CONFIG_FSL_BOOKE
-#ifdef CONFIG_SPE
- for (reg = 0; reg < 32; reg++)
- UNPACK64(current->thread.evr[reg], ptr);
+char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs)
+{
+ if (regno >= DBG_MAX_REG_NUM || regno < 0)
+ return NULL;
+
+ if (regno < 32 || regno >= 64)
+ /* First 0 -> 31 gpr registers*/
+ /* pc, msr, ls... registers 64 -> 69 */
+ memcpy(mem, (void *)regs + dbg_reg_def[regno].offset,
+ dbg_reg_def[regno].size);
+
+ if (regno >= 32 && regno < 64) {
+ /* FP registers 32 -> 63 */
+#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_SPE)
+ if (current)
+ memcpy(mem, current->thread.evr[regno-32],
+ dbg_reg_def[regno].size);
#else
- ptr += 32;
+ /* fp registers not used by kernel, leave zero */
+ memset(mem, 0, dbg_reg_def[regno].size);
#endif
+ }
+
+ return dbg_reg_def[regno].name;
+}
+
+int dbg_set_reg(int regno, void *mem, struct pt_regs *regs)
+{
+ if (regno >= DBG_MAX_REG_NUM || regno < 0)
+ return -EINVAL;
+
+ if (regno < 32 || regno >= 64)
+ /* First 0 -> 31 gpr registers*/
+ /* pc, msr, ls... registers 64 -> 69 */
+ memcpy((void *)regs + dbg_reg_def[regno].offset, mem,
+ dbg_reg_def[regno].size);
+
+ if (regno >= 32 && regno < 64) {
+ /* FP registers 32 -> 63 */
+#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_SPE)
+ memcpy(current->thread.evr[regno-32], mem,
+ dbg_reg_def[regno].size);
#else
- /* fp registers not used by kernel, leave zero */
- ptr += 32 * 8 / sizeof(int);
+ /* fp registers not used by kernel, leave zero */
+ return 0;
#endif
+ }
- UNPACK64(regs->nip, ptr);
- UNPACK64(regs->msr, ptr);
- UNPACK32(regs->ccr, ptr);
- UNPACK64(regs->link, ptr);
- UNPACK64(regs->ctr, ptr);
- UNPACK32(regs->xer, ptr);
-
- BUG_ON((unsigned long)ptr >
- (unsigned long)(((void *)gdb_regs) + NUMREGBYTES));
+ return 0;
}
void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long pc)
diff --git a/trunk/arch/powerpc/platforms/cell/spufs/inode.c b/trunk/arch/powerpc/platforms/cell/spufs/inode.c
index 5dec408d6703..3532b92de983 100644
--- a/trunk/arch/powerpc/platforms/cell/spufs/inode.c
+++ b/trunk/arch/powerpc/platforms/cell/spufs/inode.c
@@ -798,17 +798,17 @@ spufs_fill_super(struct super_block *sb, void *data, int silent)
return spufs_create_root(sb, data);
}
-static int
-spufs_get_sb(struct file_system_type *fstype, int flags,
- const char *name, void *data, struct vfsmount *mnt)
+static struct dentry *
+spufs_mount(struct file_system_type *fstype, int flags,
+ const char *name, void *data)
{
- return get_sb_single(fstype, flags, data, spufs_fill_super, mnt);
+ return mount_single(fstype, flags, data, spufs_fill_super);
}
static struct file_system_type spufs_type = {
.owner = THIS_MODULE,
.name = "spufs",
- .get_sb = spufs_get_sb,
+ .mount = spufs_mount,
.kill_sb = kill_litter_super,
};
diff --git a/trunk/arch/s390/Kconfig b/trunk/arch/s390/Kconfig
index fabb40bc4e19..e0b98e71ff47 100644
--- a/trunk/arch/s390/Kconfig
+++ b/trunk/arch/s390/Kconfig
@@ -80,6 +80,7 @@ config S390
select HAVE_FUNCTION_TRACER
select HAVE_FUNCTION_TRACE_MCOUNT_TEST
select HAVE_FTRACE_MCOUNT_RECORD
+ select HAVE_C_RECORDMCOUNT
select HAVE_SYSCALL_TRACEPOINTS
select HAVE_DYNAMIC_FTRACE
select HAVE_FUNCTION_GRAPH_TRACER
@@ -144,7 +145,7 @@ source "kernel/time/Kconfig"
config 64BIT
bool "64 bit kernel"
help
- Select this option if you have a 64 bit IBM zSeries machine
+ Select this option if you have an IBM z/Architecture machine
and want to use the 64 bit addressing mode.
config 32BIT
@@ -196,9 +197,18 @@ config HOTPLUG_CPU
can be controlled through /sys/devices/system/cpu/cpu#.
Say N if you want to disable CPU hotplug.
+config SCHED_MC
+ def_bool y
+ prompt "Multi-core scheduler support"
+ depends on SMP
+ help
+ Multi-core scheduler support improves the CPU scheduler's decision
+ making when dealing with multi-core CPU chips at a cost of slightly
+ increased overhead in some places.
+
config SCHED_BOOK
bool "Book scheduler support"
- depends on SMP
+ depends on SMP && SCHED_MC
help
Book scheduler support improves the CPU scheduler's decision making
when dealing with machines that have several books.
@@ -208,7 +218,7 @@ config MATHEMU
depends on MARCH_G5
help
This option is required for IEEE compliant floating point arithmetic
- on older S/390 machines. Say Y unless you know your machine doesn't
+ on older ESA/390 machines. Say Y unless you know your machine doesn't
need this.
config COMPAT
@@ -237,8 +247,8 @@ config S390_EXEC_PROTECT
space programs and it also selects the addressing mode option above.
The kernel parameter noexec=on will enable this feature and also
switch the addressing modes, default is disabled. Enabling this (via
- kernel parameter) on machines earlier than IBM System z9-109 EC/BC
- will reduce system performance.
+ kernel parameter) on machines earlier than IBM System z9 this will
+ reduce system performance.
comment "Code generation options"
@@ -247,49 +257,46 @@ choice
default MARCH_G5
config MARCH_G5
- bool "S/390 model G5 and G6"
+ bool "System/390 model G5 and G6"
depends on !64BIT
help
Select this to build a 31 bit kernel that works
- on all S/390 and zSeries machines.
+ on all ESA/390 and z/Architecture machines.
config MARCH_Z900
- bool "IBM eServer zSeries model z800 and z900"
+ bool "IBM zSeries model z800 and z900"
help
- Select this to optimize for zSeries machines. This
- will enable some optimizations that are not available
- on older 31 bit only CPUs.
+ Select this to enable optimizations for model z800/z900 (2064 and
+ 2066 series). This will enable some optimizations that are not
+ available on older ESA/390 (31 Bit) only CPUs.
config MARCH_Z990
- bool "IBM eServer zSeries model z890 and z990"
+ bool "IBM zSeries model z890 and z990"
help
- Select this enable optimizations for model z890/z990.
- This will be slightly faster but does not work on
- older machines such as the z900.
+ Select this to enable optimizations for model z890/z990 (2084 and
+ 2086 series). The kernel will be slightly faster but will not work
+ on older machines.
config MARCH_Z9_109
bool "IBM System z9"
help
- Select this to enable optimizations for IBM System z9-109, IBM
- System z9 Enterprise Class (z9 EC), and IBM System z9 Business
- Class (z9 BC). The kernel will be slightly faster but will not
- work on older machines such as the z990, z890, z900, and z800.
+ Select this to enable optimizations for IBM System z9 (2094 and
+ 2096 series). The kernel will be slightly faster but will not work
+ on older machines.
config MARCH_Z10
bool "IBM System z10"
help
- Select this to enable optimizations for IBM System z10. The
- kernel will be slightly faster but will not work on older
- machines such as the z990, z890, z900, z800, z9-109, z9-ec
- and z9-bc.
+ Select this to enable optimizations for IBM System z10 (2097 and
+ 2098 series). The kernel will be slightly faster but will not work
+ on older machines.
config MARCH_Z196
bool "IBM zEnterprise 196"
help
- Select this to enable optimizations for IBM zEnterprise 196.
- The kernel will be slightly faster but will not work on older
- machines such as the z990, z890, z900, z800, z9-109, z9-ec,
- z9-bc, z10-ec and z10-bc.
+ Select this to enable optimizations for IBM zEnterprise 196
+ (2817 series). The kernel will be slightly faster but will not work
+ on older machines.
endchoice
diff --git a/trunk/arch/s390/hypfs/hypfs_diag.c b/trunk/arch/s390/hypfs/hypfs_diag.c
index 020e51c063d2..cd4a81be9cf8 100644
--- a/trunk/arch/s390/hypfs/hypfs_diag.c
+++ b/trunk/arch/s390/hypfs/hypfs_diag.c
@@ -638,18 +638,21 @@ __init int hypfs_diag_init(void)
pr_err("The hardware system does not support hypfs\n");
return -ENODATA;
}
- rc = diag224_get_name_table();
- if (rc) {
- diag204_free_buffer();
- pr_err("The hardware system does not provide all "
- "functions required by hypfs\n");
- }
if (diag204_info_type == INFO_EXT) {
rc = hypfs_dbfs_init();
if (rc)
- diag204_free_buffer();
+ return rc;
}
- return rc;
+ if (MACHINE_IS_LPAR) {
+ rc = diag224_get_name_table();
+ if (rc) {
+ pr_err("The hardware system does not provide all "
+ "functions required by hypfs\n");
+ debugfs_remove(dbfs_d204_file);
+ return rc;
+ }
+ }
+ return 0;
}
void hypfs_diag_exit(void)
diff --git a/trunk/arch/s390/hypfs/inode.c b/trunk/arch/s390/hypfs/inode.c
index 74d98670be27..47cc446dab8f 100644
--- a/trunk/arch/s390/hypfs/inode.c
+++ b/trunk/arch/s390/hypfs/inode.c
@@ -316,10 +316,10 @@ static int hypfs_fill_super(struct super_block *sb, void *data, int silent)
return 0;
}
-static int hypfs_get_super(struct file_system_type *fst, int flags,
- const char *devname, void *data, struct vfsmount *mnt)
+static struct dentry *hypfs_mount(struct file_system_type *fst, int flags,
+ const char *devname, void *data)
{
- return get_sb_single(fst, flags, data, hypfs_fill_super, mnt);
+ return mount_single(fst, flags, data, hypfs_fill_super);
}
static void hypfs_kill_super(struct super_block *sb)
@@ -455,7 +455,7 @@ static const struct file_operations hypfs_file_ops = {
static struct file_system_type hypfs_type = {
.owner = THIS_MODULE,
.name = "s390_hypfs",
- .get_sb = hypfs_get_super,
+ .mount = hypfs_mount,
.kill_sb = hypfs_kill_super
};
diff --git a/trunk/arch/s390/include/asm/dasd.h b/trunk/arch/s390/include/asm/dasd.h
index 218bce81ec70..b604a9186f8e 100644
--- a/trunk/arch/s390/include/asm/dasd.h
+++ b/trunk/arch/s390/include/asm/dasd.h
@@ -217,6 +217,25 @@ typedef struct dasd_symmio_parms {
int rssd_result_len;
} __attribute__ ((packed)) dasd_symmio_parms_t;
+/*
+ * Data returned by Sense Path Group ID (SNID)
+ */
+struct dasd_snid_data {
+ struct {
+ __u8 group:2;
+ __u8 reserve:2;
+ __u8 mode:1;
+ __u8 res:3;
+ } __attribute__ ((packed)) path_state;
+ __u8 pgid[11];
+} __attribute__ ((packed));
+
+struct dasd_snid_ioctl_data {
+ struct dasd_snid_data data;
+ __u8 path_mask;
+} __attribute__ ((packed));
+
+
/********************************************************************************
* SECTION: Definition of IOCTLs
*
@@ -261,25 +280,10 @@ typedef struct dasd_symmio_parms {
/* Set Attributes (cache operations) */
#define BIODASDSATTR _IOW(DASD_IOCTL_LETTER,2,attrib_data_t)
+/* Get Sense Path Group ID (SNID) data */
+#define BIODASDSNID _IOWR(DASD_IOCTL_LETTER, 1, struct dasd_snid_ioctl_data)
+
#define BIODASDSYMMIO _IOWR(DASD_IOCTL_LETTER, 240, dasd_symmio_parms_t)
#endif /* DASD_H */
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only. This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-indent-level: 4
- * c-brace-imaginary-offset: 0
- * c-brace-offset: -4
- * c-argdecl-indent: 4
- * c-label-offset: -4
- * c-continued-statement-offset: 4
- * c-continued-brace-offset: 0
- * indent-tabs-mode: nil
- * tab-width: 8
- * End:
- */
diff --git a/trunk/arch/s390/kernel/asm-offsets.c b/trunk/arch/s390/kernel/asm-offsets.c
index f3c1b823c9a8..33982e7ce04d 100644
--- a/trunk/arch/s390/kernel/asm-offsets.c
+++ b/trunk/arch/s390/kernel/asm-offsets.c
@@ -66,9 +66,9 @@ int main(void)
DEFINE(__VDSO_ECTG_BASE, offsetof(struct vdso_per_cpu_data, ectg_timer_base));
DEFINE(__VDSO_ECTG_USER, offsetof(struct vdso_per_cpu_data, ectg_user_time));
/* constants used by the vdso */
- DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
- DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
- DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
+ DEFINE(__CLOCK_REALTIME, CLOCK_REALTIME);
+ DEFINE(__CLOCK_MONOTONIC, CLOCK_MONOTONIC);
+ DEFINE(__CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
BLANK();
/* constants for SIGP */
DEFINE(__SIGP_STOP, sigp_stop);
diff --git a/trunk/arch/s390/kernel/early.c b/trunk/arch/s390/kernel/early.c
index d149609e46e6..3b7e7dddc324 100644
--- a/trunk/arch/s390/kernel/early.c
+++ b/trunk/arch/s390/kernel/early.c
@@ -282,8 +282,6 @@ static noinline __init void setup_facility_list(void)
static noinline __init void setup_hpage(void)
{
#ifndef CONFIG_DEBUG_PAGEALLOC
- unsigned int facilities;
-
if (!test_facility(2) || !test_facility(8))
return;
S390_lowcore.machine_flags |= MACHINE_FLAG_HPAGE;
diff --git a/trunk/arch/s390/kernel/entry.S b/trunk/arch/s390/kernel/entry.S
index 5efce7202984..1ecc337fb679 100644
--- a/trunk/arch/s390/kernel/entry.S
+++ b/trunk/arch/s390/kernel/entry.S
@@ -557,6 +557,7 @@ pgm_svcper:
# per was called from kernel, must be kprobes
#
kernel_per:
+ REENABLE_IRQS
mvi SP_SVCNR(%r15),0xff # set trap indication to pgm check
mvi SP_SVCNR+1(%r15),0xff
la %r2,SP_PTREGS(%r15) # address of register-save area
diff --git a/trunk/arch/s390/kernel/entry64.S b/trunk/arch/s390/kernel/entry64.S
index a2be23922f43..8f3e802174db 100644
--- a/trunk/arch/s390/kernel/entry64.S
+++ b/trunk/arch/s390/kernel/entry64.S
@@ -568,6 +568,7 @@ pgm_svcper:
# per was called from kernel, must be kprobes
#
kernel_per:
+ REENABLE_IRQS
xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number
la %r2,SP_PTREGS(%r15) # address of register-save area
brasl %r14,do_single_step
diff --git a/trunk/arch/s390/kernel/kprobes.c b/trunk/arch/s390/kernel/kprobes.c
index 2a3d2bf6f083..d60fc4398516 100644
--- a/trunk/arch/s390/kernel/kprobes.c
+++ b/trunk/arch/s390/kernel/kprobes.c
@@ -316,6 +316,8 @@ static int __kprobes kprobe_handler(struct pt_regs *regs)
return 1;
ss_probe:
+ if (regs->psw.mask & (PSW_MASK_PER | PSW_MASK_IO))
+ local_irq_disable();
prepare_singlestep(p, regs);
kcb->kprobe_status = KPROBE_HIT_SS;
return 1;
@@ -463,6 +465,8 @@ static int __kprobes post_kprobe_handler(struct pt_regs *regs)
goto out;
}
reset_current_kprobe();
+ if (regs->psw.mask & (PSW_MASK_PER | PSW_MASK_IO))
+ local_irq_enable();
out:
preempt_enable_no_resched();
@@ -502,8 +506,11 @@ int __kprobes kprobe_fault_handler(struct pt_regs *regs, int trapnr)
regs->psw.mask |= kcb->kprobe_saved_imask;
if (kcb->kprobe_status == KPROBE_REENTER)
restore_previous_kprobe(kcb);
- else
+ else {
reset_current_kprobe();
+ if (regs->psw.mask & (PSW_MASK_PER | PSW_MASK_IO))
+ local_irq_enable();
+ }
preempt_enable_no_resched();
break;
case KPROBE_HIT_ACTIVE:
diff --git a/trunk/arch/s390/kernel/setup.c b/trunk/arch/s390/kernel/setup.c
index e3ceb911dc75..6f6350826c81 100644
--- a/trunk/arch/s390/kernel/setup.c
+++ b/trunk/arch/s390/kernel/setup.c
@@ -761,6 +761,9 @@ static void __init setup_hwcaps(void)
case 0x2098:
strcpy(elf_platform, "z10");
break;
+ case 0x2817:
+ strcpy(elf_platform, "z196");
+ break;
}
}
diff --git a/trunk/arch/s390/kernel/sysinfo.c b/trunk/arch/s390/kernel/sysinfo.c
index f04d93aa48ec..5c9e439bf3f6 100644
--- a/trunk/arch/s390/kernel/sysinfo.c
+++ b/trunk/arch/s390/kernel/sysinfo.c
@@ -106,11 +106,13 @@ static int stsi_15_1_x(struct sysinfo_15_1_x *info, char *page, int len)
for (i = 0; i < TOPOLOGY_NR_MAG; i++)
len += sprintf(page + len, " %d", info->mag[i]);
len += sprintf(page + len, "\n");
+#ifdef CONFIG_SCHED_MC
store_topology(info);
len += sprintf(page + len, "CPU Topology SW: ");
for (i = 0; i < TOPOLOGY_NR_MAG; i++)
len += sprintf(page + len, " %d", info->mag[i]);
len += sprintf(page + len, "\n");
+#endif
return len;
}
diff --git a/trunk/arch/s390/kernel/topology.c b/trunk/arch/s390/kernel/topology.c
index a9dee9048ee5..94b06c31fc8a 100644
--- a/trunk/arch/s390/kernel/topology.c
+++ b/trunk/arch/s390/kernel/topology.c
@@ -53,8 +53,10 @@ static cpumask_t cpu_group_map(struct mask_info *info, unsigned int cpu)
cpumask_t mask;
cpus_clear(mask);
- if (!topology_enabled || !MACHINE_HAS_TOPOLOGY)
- return cpu_possible_map;
+ if (!topology_enabled || !MACHINE_HAS_TOPOLOGY) {
+ cpumask_copy(&mask, cpumask_of(cpu));
+ return mask;
+ }
while (info) {
if (cpu_isset(cpu, info->mask)) {
mask = info->mask;
diff --git a/trunk/arch/s390/kernel/vdso32/clock_getres.S b/trunk/arch/s390/kernel/vdso32/clock_getres.S
index 9532c4e6a9d2..36aaa25d05da 100644
--- a/trunk/arch/s390/kernel/vdso32/clock_getres.S
+++ b/trunk/arch/s390/kernel/vdso32/clock_getres.S
@@ -19,9 +19,9 @@
.type __kernel_clock_getres,@function
__kernel_clock_getres:
.cfi_startproc
- chi %r2,CLOCK_REALTIME
+ chi %r2,__CLOCK_REALTIME
je 0f
- chi %r2,CLOCK_MONOTONIC
+ chi %r2,__CLOCK_MONOTONIC
jne 3f
0: ltr %r3,%r3
jz 2f /* res == NULL */
@@ -34,6 +34,6 @@ __kernel_clock_getres:
3: lhi %r1,__NR_clock_getres /* fallback to svc */
svc 0
br %r14
-4: .long CLOCK_REALTIME_RES
+4: .long __CLOCK_REALTIME_RES
.cfi_endproc
.size __kernel_clock_getres,.-__kernel_clock_getres
diff --git a/trunk/arch/s390/kernel/vdso32/clock_gettime.S b/trunk/arch/s390/kernel/vdso32/clock_gettime.S
index 969643954273..b2224e0b974c 100644
--- a/trunk/arch/s390/kernel/vdso32/clock_gettime.S
+++ b/trunk/arch/s390/kernel/vdso32/clock_gettime.S
@@ -21,9 +21,9 @@ __kernel_clock_gettime:
.cfi_startproc
basr %r5,0
0: al %r5,21f-0b(%r5) /* get &_vdso_data */
- chi %r2,CLOCK_REALTIME
+ chi %r2,__CLOCK_REALTIME
je 10f
- chi %r2,CLOCK_MONOTONIC
+ chi %r2,__CLOCK_MONOTONIC
jne 19f
/* CLOCK_MONOTONIC */
diff --git a/trunk/arch/s390/kernel/vdso64/clock_getres.S b/trunk/arch/s390/kernel/vdso64/clock_getres.S
index 9ce8caafdb4e..176e1f75f9aa 100644
--- a/trunk/arch/s390/kernel/vdso64/clock_getres.S
+++ b/trunk/arch/s390/kernel/vdso64/clock_getres.S
@@ -19,9 +19,9 @@
.type __kernel_clock_getres,@function
__kernel_clock_getres:
.cfi_startproc
- cghi %r2,CLOCK_REALTIME
+ cghi %r2,__CLOCK_REALTIME
je 0f
- cghi %r2,CLOCK_MONOTONIC
+ cghi %r2,__CLOCK_MONOTONIC
je 0f
cghi %r2,-2 /* CLOCK_THREAD_CPUTIME_ID for this thread */
jne 2f
@@ -39,6 +39,6 @@ __kernel_clock_getres:
2: lghi %r1,__NR_clock_getres /* fallback to svc */
svc 0
br %r14
-3: .quad CLOCK_REALTIME_RES
+3: .quad __CLOCK_REALTIME_RES
.cfi_endproc
.size __kernel_clock_getres,.-__kernel_clock_getres
diff --git a/trunk/arch/s390/kernel/vdso64/clock_gettime.S b/trunk/arch/s390/kernel/vdso64/clock_gettime.S
index f40467884a03..d46c95ed5f19 100644
--- a/trunk/arch/s390/kernel/vdso64/clock_gettime.S
+++ b/trunk/arch/s390/kernel/vdso64/clock_gettime.S
@@ -20,11 +20,11 @@
__kernel_clock_gettime:
.cfi_startproc
larl %r5,_vdso_data
- cghi %r2,CLOCK_REALTIME
+ cghi %r2,__CLOCK_REALTIME
je 4f
cghi %r2,-2 /* CLOCK_THREAD_CPUTIME_ID for this thread */
je 9f
- cghi %r2,CLOCK_MONOTONIC
+ cghi %r2,__CLOCK_MONOTONIC
jne 12f
/* CLOCK_MONOTONIC */
diff --git a/trunk/arch/sparc/Kconfig b/trunk/arch/sparc/Kconfig
index a9aaed3c3d97..45d9c87d083a 100644
--- a/trunk/arch/sparc/Kconfig
+++ b/trunk/arch/sparc/Kconfig
@@ -22,8 +22,6 @@ config SPARC
select RTC_CLASS
select RTC_DRV_M48T59
select HAVE_IRQ_WORK
- select HAVE_PERF_EVENTS
- select PERF_USE_VMALLOC
select HAVE_DMA_ATTRS
select HAVE_DMA_API_DEBUG
select HAVE_ARCH_JUMP_LABEL
@@ -50,7 +48,6 @@ config SPARC64
select RTC_DRV_BQ4802
select RTC_DRV_SUN4V
select RTC_DRV_STARFIRE
- select HAVE_IRQ_WORK
select HAVE_PERF_EVENTS
select PERF_USE_VMALLOC
diff --git a/trunk/arch/sparc/include/asm/jump_label.h b/trunk/arch/sparc/include/asm/jump_label.h
index 62e66d7b2fb6..65c0d3029796 100644
--- a/trunk/arch/sparc/include/asm/jump_label.h
+++ b/trunk/arch/sparc/include/asm/jump_label.h
@@ -4,7 +4,6 @@
#ifdef __KERNEL__
#include
-#include
#define JUMP_LABEL_NOP_SIZE 4
diff --git a/trunk/arch/sparc/kernel/irq_32.c b/trunk/arch/sparc/kernel/irq_32.c
index 0116d8d10def..5ad6e5c5dbb3 100644
--- a/trunk/arch/sparc/kernel/irq_32.c
+++ b/trunk/arch/sparc/kernel/irq_32.c
@@ -365,7 +365,7 @@ static int request_fast_irq(unsigned int irq,
unsigned long flags;
unsigned int cpu_irq;
int ret;
-#ifdef CONFIG_SMP
+#if defined CONFIG_SMP && !defined CONFIG_SPARC_LEON
struct tt_entry *trap_table;
extern struct tt_entry trapbase_cpu1, trapbase_cpu2, trapbase_cpu3;
#endif
@@ -425,7 +425,7 @@ static int request_fast_irq(unsigned int irq,
table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_four = SPARC_NOP;
INSTANTIATE(sparc_ttable)
-#ifdef CONFIG_SMP
+#if defined CONFIG_SMP && !defined CONFIG_SPARC_LEON
trap_table = &trapbase_cpu1; INSTANTIATE(trap_table)
trap_table = &trapbase_cpu2; INSTANTIATE(trap_table)
trap_table = &trapbase_cpu3; INSTANTIATE(trap_table)
diff --git a/trunk/arch/sparc/kernel/leon_smp.c b/trunk/arch/sparc/kernel/leon_smp.c
index e1656fc41ccb..7524689b03d2 100644
--- a/trunk/arch/sparc/kernel/leon_smp.c
+++ b/trunk/arch/sparc/kernel/leon_smp.c
@@ -56,8 +56,8 @@ void __init leon_configure_cache_smp(void);
static inline unsigned long do_swap(volatile unsigned long *ptr,
unsigned long val)
{
- __asm__ __volatile__("swapa [%1] %2, %0\n\t" : "=&r"(val)
- : "r"(ptr), "i"(ASI_LEON_DCACHE_MISS)
+ __asm__ __volatile__("swapa [%2] %3, %0\n\t" : "=&r"(val)
+ : "0"(val), "r"(ptr), "i"(ASI_LEON_DCACHE_MISS)
: "memory");
return val;
}
diff --git a/trunk/arch/sparc/kernel/rtrap_32.S b/trunk/arch/sparc/kernel/rtrap_32.S
index 4da2e1f66290..5f5f74c2c2ca 100644
--- a/trunk/arch/sparc/kernel/rtrap_32.S
+++ b/trunk/arch/sparc/kernel/rtrap_32.S
@@ -78,9 +78,9 @@ signal_p:
call do_notify_resume
add %sp, STACKFRAME_SZ, %o0 ! pt_regs ptr
- /* Fall through. */
- ld [%sp + STACKFRAME_SZ + PT_PSR], %t_psr
- clr %l6
+ b signal_p
+ ld [%curptr + TI_FLAGS], %g2
+
ret_trap_continue:
sethi %hi(PSR_SYSCALL), %g1
andn %t_psr, %g1, %t_psr
diff --git a/trunk/arch/sparc/kernel/rtrap_64.S b/trunk/arch/sparc/kernel/rtrap_64.S
index 090b9e9ad5e3..77f1b95e0806 100644
--- a/trunk/arch/sparc/kernel/rtrap_64.S
+++ b/trunk/arch/sparc/kernel/rtrap_64.S
@@ -34,37 +34,9 @@ __handle_preemption:
__handle_user_windows:
call fault_in_user_windows
wrpr %g0, RTRAP_PSTATE, %pstate
- wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
- /* Redo sched+sig checks */
- ldx [%g6 + TI_FLAGS], %l0
- andcc %l0, _TIF_NEED_RESCHED, %g0
-
- be,pt %xcc, 1f
- nop
- call schedule
- wrpr %g0, RTRAP_PSTATE, %pstate
- wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
- ldx [%g6 + TI_FLAGS], %l0
-
-1: andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
- be,pt %xcc, __handle_user_windows_continue
- nop
- mov %l5, %o1
- add %sp, PTREGS_OFF, %o0
- mov %l0, %o2
-
- call do_notify_resume
- wrpr %g0, RTRAP_PSTATE, %pstate
- wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
- /* Signal delivery can modify pt_regs tstate, so we must
- * reload it.
- */
- ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
- sethi %hi(0xf << 20), %l4
- and %l1, %l4, %l4
- ba,pt %xcc, __handle_user_windows_continue
+ ba,pt %xcc, __handle_preemption_continue
+ wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
- andn %l1, %l4, %l1
__handle_userfpu:
rd %fprs, %l5
andcc %l5, FPRS_FEF, %g0
@@ -87,7 +59,7 @@ __handle_signal:
ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
sethi %hi(0xf << 20), %l4
and %l1, %l4, %l4
- ba,pt %xcc, __handle_signal_continue
+ ba,pt %xcc, __handle_preemption_continue
andn %l1, %l4, %l1
/* When returning from a NMI (%pil==15) interrupt we want to
@@ -177,11 +149,9 @@ __handle_preemption_continue:
bne,pn %xcc, __handle_preemption
andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
bne,pn %xcc, __handle_signal
-__handle_signal_continue:
ldub [%g6 + TI_WSAVED], %o2
brnz,pn %o2, __handle_user_windows
nop
-__handle_user_windows_continue:
sethi %hi(TSTATE_PEF), %o0
andcc %l1, %o0, %g0
diff --git a/trunk/arch/sparc/mm/fault_32.c b/trunk/arch/sparc/mm/fault_32.c
index bd8601601afa..5b836f5aea90 100644
--- a/trunk/arch/sparc/mm/fault_32.c
+++ b/trunk/arch/sparc/mm/fault_32.c
@@ -539,6 +539,12 @@ static void force_user_fault(unsigned long address, int write)
__do_fault_siginfo(BUS_ADRERR, SIGBUS, tsk->thread.kregs, address);
}
+static void check_stack_aligned(unsigned long sp)
+{
+ if (sp & 0x7UL)
+ force_sig(SIGILL, current);
+}
+
void window_overflow_fault(void)
{
unsigned long sp;
@@ -547,6 +553,8 @@ void window_overflow_fault(void)
if(((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK))
force_user_fault(sp + 0x38, 1);
force_user_fault(sp, 1);
+
+ check_stack_aligned(sp);
}
void window_underflow_fault(unsigned long sp)
@@ -554,6 +562,8 @@ void window_underflow_fault(unsigned long sp)
if(((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK))
force_user_fault(sp + 0x38, 0);
force_user_fault(sp, 0);
+
+ check_stack_aligned(sp);
}
void window_ret_fault(struct pt_regs *regs)
@@ -564,4 +574,6 @@ void window_ret_fault(struct pt_regs *regs)
if(((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK))
force_user_fault(sp + 0x38, 0);
force_user_fault(sp, 0);
+
+ check_stack_aligned(sp);
}
diff --git a/trunk/arch/x86/kernel/kgdb.c b/trunk/arch/x86/kernel/kgdb.c
index d81cfebb848f..ec592caac4b4 100644
--- a/trunk/arch/x86/kernel/kgdb.c
+++ b/trunk/arch/x86/kernel/kgdb.c
@@ -387,7 +387,7 @@ kgdb_set_hw_break(unsigned long addr, int len, enum kgdb_bptype bptype)
* disable hardware debugging while it is processing gdb packets or
* handling exception.
*/
-void kgdb_disable_hw_debug(struct pt_regs *regs)
+static void kgdb_disable_hw_debug(struct pt_regs *regs)
{
int i;
int cpu = raw_smp_processor_id();
@@ -724,6 +724,7 @@ struct kgdb_arch arch_kgdb_ops = {
.flags = KGDB_HW_BREAKPOINT,
.set_hw_breakpoint = kgdb_set_hw_break,
.remove_hw_breakpoint = kgdb_remove_hw_break,
+ .disable_hw_break = kgdb_disable_hw_debug,
.remove_all_hw_break = kgdb_remove_all_hw_break,
.correct_hw_break = kgdb_correct_hw_break,
};
diff --git a/trunk/drivers/ata/pata_octeon_cf.c b/trunk/drivers/ata/pata_octeon_cf.c
index 06ddd91ffeda..74b829817891 100644
--- a/trunk/drivers/ata/pata_octeon_cf.c
+++ b/trunk/drivers/ata/pata_octeon_cf.c
@@ -60,7 +60,7 @@ static unsigned int ns_to_tim_reg(unsigned int tim_mult, unsigned int nsecs)
* Compute # of eclock periods to get desired duration in
* nanoseconds.
*/
- val = DIV_ROUND_UP(nsecs * (octeon_get_clock_rate() / 1000000),
+ val = DIV_ROUND_UP(nsecs * (octeon_get_io_clock_rate() / 1000000),
1000 * tim_mult);
return val;
diff --git a/trunk/drivers/base/devtmpfs.c b/trunk/drivers/base/devtmpfs.c
index af0600143d1c..82bbb5967aa9 100644
--- a/trunk/drivers/base/devtmpfs.c
+++ b/trunk/drivers/base/devtmpfs.c
@@ -29,33 +29,33 @@
static struct vfsmount *dev_mnt;
#if defined CONFIG_DEVTMPFS_MOUNT
-static int dev_mount = 1;
+static int mount_dev = 1;
#else
-static int dev_mount;
+static int mount_dev;
#endif
static DEFINE_MUTEX(dirlock);
static int __init mount_param(char *str)
{
- dev_mount = simple_strtoul(str, NULL, 0);
+ mount_dev = simple_strtoul(str, NULL, 0);
return 1;
}
__setup("devtmpfs.mount=", mount_param);
-static int dev_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *dev_mount(struct file_system_type *fs_type, int flags,
+ const char *dev_name, void *data)
{
#ifdef CONFIG_TMPFS
- return get_sb_single(fs_type, flags, data, shmem_fill_super, mnt);
+ return mount_single(fs_type, flags, data, shmem_fill_super);
#else
- return get_sb_single(fs_type, flags, data, ramfs_fill_super, mnt);
+ return mount_single(fs_type, flags, data, ramfs_fill_super);
#endif
}
static struct file_system_type dev_fs_type = {
.name = "devtmpfs",
- .get_sb = dev_get_sb,
+ .mount = dev_mount,
.kill_sb = kill_litter_super,
};
@@ -351,7 +351,7 @@ int devtmpfs_mount(const char *mntdir)
{
int err;
- if (!dev_mount)
+ if (!mount_dev)
return 0;
if (!dev_mnt)
diff --git a/trunk/drivers/char/agp/parisc-agp.c b/trunk/drivers/char/agp/parisc-agp.c
index 17e380f5f818..94821ab01c6d 100644
--- a/trunk/drivers/char/agp/parisc-agp.c
+++ b/trunk/drivers/char/agp/parisc-agp.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include
diff --git a/trunk/drivers/dma/Kconfig b/trunk/drivers/dma/Kconfig
index 79d1542f31c0..6ee23592700a 100644
--- a/trunk/drivers/dma/Kconfig
+++ b/trunk/drivers/dma/Kconfig
@@ -200,11 +200,11 @@ config PL330_DMA
platform_data for a dma-pl330 device.
config PCH_DMA
- tristate "Topcliff PCH DMA support"
+ tristate "Topcliff (Intel EG20T) PCH DMA support"
depends on PCI && X86
select DMA_ENGINE
help
- Enable support for the Topcliff PCH DMA engine.
+ Enable support for the Topcliff (Intel EG20T) PCH DMA engine.
config IMX_SDMA
tristate "i.MX SDMA support"
diff --git a/trunk/drivers/ide/hpt366.c b/trunk/drivers/ide/hpt366.c
index 97d98fbf5849..58c51cddc100 100644
--- a/trunk/drivers/ide/hpt366.c
+++ b/trunk/drivers/ide/hpt366.c
@@ -838,7 +838,7 @@ static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
{
- hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x23 : 0x21);
+ hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x21 : 0x23);
}
/**
@@ -1173,8 +1173,9 @@ static u8 hpt3xx_cable_detect(ide_hwif_t *hwif)
u16 mcr;
pci_read_config_word(dev, mcr_addr, &mcr);
- pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
- /* now read cable id register */
+ pci_write_config_word(dev, mcr_addr, mcr | 0x8000);
+ /* Debounce, then read cable ID register */
+ udelay(10);
pci_read_config_byte(dev, 0x5a, &scr1);
pci_write_config_word(dev, mcr_addr, mcr);
} else if (chip_type >= HPT370) {
@@ -1185,10 +1186,11 @@ static u8 hpt3xx_cable_detect(ide_hwif_t *hwif)
u8 scr2 = 0;
pci_read_config_byte(dev, 0x5b, &scr2);
- pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
- /* now read cable id register */
+ pci_write_config_byte(dev, 0x5b, scr2 & ~1);
+ /* Debounce, then read cable ID register */
+ udelay(10);
pci_read_config_byte(dev, 0x5a, &scr1);
- pci_write_config_byte(dev, 0x5b, scr2);
+ pci_write_config_byte(dev, 0x5b, scr2);
} else
pci_read_config_byte(dev, 0x5a, &scr1);
diff --git a/trunk/drivers/ide/ide-dma.c b/trunk/drivers/ide/ide-dma.c
index 06b14bc9a1d4..d4136908f916 100644
--- a/trunk/drivers/ide/ide-dma.c
+++ b/trunk/drivers/ide/ide-dma.c
@@ -449,7 +449,6 @@ ide_startstop_t ide_dma_timeout_retry(ide_drive_t *drive, int error)
ide_hwif_t *hwif = drive->hwif;
const struct ide_dma_ops *dma_ops = hwif->dma_ops;
struct ide_cmd *cmd = &hwif->cmd;
- struct request *rq;
ide_startstop_t ret = ide_stopped;
/*
@@ -487,14 +486,10 @@ ide_startstop_t ide_dma_timeout_retry(ide_drive_t *drive, int error)
ide_dma_off_quietly(drive);
/*
- * un-busy drive etc and make sure request is sane
+ * make sure request is sane
*/
- rq = hwif->rq;
- if (rq) {
- hwif->rq = NULL;
- rq->errors = 0;
- ide_requeue_and_plug(drive, rq);
- }
+ if (hwif->rq)
+ hwif->rq->errors = 0;
return ret;
}
diff --git a/trunk/drivers/infiniband/hw/ipath/ipath_fs.c b/trunk/drivers/infiniband/hw/ipath/ipath_fs.c
index 12d5bf76302c..8c8afc716b98 100644
--- a/trunk/drivers/infiniband/hw/ipath/ipath_fs.c
+++ b/trunk/drivers/infiniband/hw/ipath/ipath_fs.c
@@ -362,13 +362,13 @@ static int ipathfs_fill_super(struct super_block *sb, void *data,
return ret;
}
-static int ipathfs_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *ipathfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- int ret = get_sb_single(fs_type, flags, data,
- ipathfs_fill_super, mnt);
- if (ret >= 0)
- ipath_super = mnt->mnt_sb;
+ struct dentry *ret;
+ ret = mount_single(fs_type, flags, data, ipathfs_fill_super);
+ if (!IS_ERR(ret))
+ ipath_super = ret->d_sb;
return ret;
}
@@ -411,7 +411,7 @@ int ipathfs_remove_device(struct ipath_devdata *dd)
static struct file_system_type ipathfs_fs_type = {
.owner = THIS_MODULE,
.name = "ipathfs",
- .get_sb = ipathfs_get_sb,
+ .mount = ipathfs_mount,
.kill_sb = ipathfs_kill_super,
};
diff --git a/trunk/drivers/infiniband/hw/qib/qib_fs.c b/trunk/drivers/infiniband/hw/qib/qib_fs.c
index 7e433d75c775..f99bddc01716 100644
--- a/trunk/drivers/infiniband/hw/qib/qib_fs.c
+++ b/trunk/drivers/infiniband/hw/qib/qib_fs.c
@@ -555,13 +555,13 @@ static int qibfs_fill_super(struct super_block *sb, void *data, int silent)
return ret;
}
-static int qibfs_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *qibfs_mount(struct file_system_type *fs_type, int flags,
+ const char *dev_name, void *data)
{
- int ret = get_sb_single(fs_type, flags, data,
- qibfs_fill_super, mnt);
- if (ret >= 0)
- qib_super = mnt->mnt_sb;
+ struct dentry *ret;
+ ret = mount_single(fs_type, flags, data, qibfs_fill_super);
+ if (!IS_ERR(ret))
+ qib_super = ret->d_sb;
return ret;
}
@@ -603,7 +603,7 @@ int qibfs_remove(struct qib_devdata *dd)
static struct file_system_type qibfs_fs_type = {
.owner = THIS_MODULE,
.name = "ipathfs",
- .get_sb = qibfs_get_sb,
+ .mount = qibfs_mount,
.kill_sb = qibfs_kill_super,
};
diff --git a/trunk/drivers/isdn/capi/capifs.c b/trunk/drivers/isdn/capi/capifs.c
index 2b83850997c3..b4faed7fe0d3 100644
--- a/trunk/drivers/isdn/capi/capifs.c
+++ b/trunk/drivers/isdn/capi/capifs.c
@@ -125,16 +125,16 @@ capifs_fill_super(struct super_block *s, void *data, int silent)
return -ENOMEM;
}
-static int capifs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *capifs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_single(fs_type, flags, data, capifs_fill_super, mnt);
+ return mount_single(fs_type, flags, data, capifs_fill_super);
}
static struct file_system_type capifs_fs_type = {
.owner = THIS_MODULE,
.name = "capifs",
- .get_sb = capifs_get_sb,
+ .mount = capifs_mount,
.kill_sb = kill_anon_super,
};
diff --git a/trunk/drivers/md/bitmap.c b/trunk/drivers/md/bitmap.c
index e4fb58db5454..5a1ffe3527aa 100644
--- a/trunk/drivers/md/bitmap.c
+++ b/trunk/drivers/md/bitmap.c
@@ -212,7 +212,7 @@ static struct page *read_sb_page(mddev_t *mddev, loff_t offset,
target = rdev->sb_start + offset + index * (PAGE_SIZE/512);
- if (sync_page_io(rdev->bdev, target,
+ if (sync_page_io(rdev, target,
roundup(size, bdev_logical_block_size(rdev->bdev)),
page, READ)) {
page->index = index;
@@ -343,7 +343,7 @@ static void write_page(struct bitmap *bitmap, struct page *page, int wait)
atomic_inc(&bitmap->pending_writes);
set_buffer_locked(bh);
set_buffer_mapped(bh);
- submit_bh(WRITE, bh);
+ submit_bh(WRITE | REQ_UNPLUG | REQ_SYNC, bh);
bh = bh->b_this_page;
}
@@ -1101,7 +1101,7 @@ static void bitmap_count_page(struct bitmap *bitmap, sector_t offset, int inc)
bitmap_checkfree(bitmap, page);
}
static bitmap_counter_t *bitmap_get_counter(struct bitmap *bitmap,
- sector_t offset, int *blocks,
+ sector_t offset, sector_t *blocks,
int create);
/*
@@ -1115,7 +1115,7 @@ void bitmap_daemon_work(mddev_t *mddev)
unsigned long j;
unsigned long flags;
struct page *page = NULL, *lastpage = NULL;
- int blocks;
+ sector_t blocks;
void *paddr;
struct dm_dirty_log *log = mddev->bitmap_info.log;
@@ -1258,7 +1258,7 @@ void bitmap_daemon_work(mddev_t *mddev)
}
static bitmap_counter_t *bitmap_get_counter(struct bitmap *bitmap,
- sector_t offset, int *blocks,
+ sector_t offset, sector_t *blocks,
int create)
__releases(bitmap->lock)
__acquires(bitmap->lock)
@@ -1316,7 +1316,7 @@ int bitmap_startwrite(struct bitmap *bitmap, sector_t offset, unsigned long sect
}
while (sectors) {
- int blocks;
+ sector_t blocks;
bitmap_counter_t *bmc;
spin_lock_irq(&bitmap->lock);
@@ -1381,7 +1381,7 @@ void bitmap_endwrite(struct bitmap *bitmap, sector_t offset, unsigned long secto
success = 0;
while (sectors) {
- int blocks;
+ sector_t blocks;
unsigned long flags;
bitmap_counter_t *bmc;
@@ -1423,7 +1423,7 @@ void bitmap_endwrite(struct bitmap *bitmap, sector_t offset, unsigned long secto
}
EXPORT_SYMBOL(bitmap_endwrite);
-static int __bitmap_start_sync(struct bitmap *bitmap, sector_t offset, int *blocks,
+static int __bitmap_start_sync(struct bitmap *bitmap, sector_t offset, sector_t *blocks,
int degraded)
{
bitmap_counter_t *bmc;
@@ -1452,7 +1452,7 @@ static int __bitmap_start_sync(struct bitmap *bitmap, sector_t offset, int *bloc
return rv;
}
-int bitmap_start_sync(struct bitmap *bitmap, sector_t offset, int *blocks,
+int bitmap_start_sync(struct bitmap *bitmap, sector_t offset, sector_t *blocks,
int degraded)
{
/* bitmap_start_sync must always report on multiples of whole
@@ -1463,7 +1463,7 @@ int bitmap_start_sync(struct bitmap *bitmap, sector_t offset, int *blocks,
* Return the 'or' of the result.
*/
int rv = 0;
- int blocks1;
+ sector_t blocks1;
*blocks = 0;
while (*blocks < (PAGE_SIZE>>9)) {
@@ -1476,7 +1476,7 @@ int bitmap_start_sync(struct bitmap *bitmap, sector_t offset, int *blocks,
}
EXPORT_SYMBOL(bitmap_start_sync);
-void bitmap_end_sync(struct bitmap *bitmap, sector_t offset, int *blocks, int aborted)
+void bitmap_end_sync(struct bitmap *bitmap, sector_t offset, sector_t *blocks, int aborted)
{
bitmap_counter_t *bmc;
unsigned long flags;
@@ -1515,7 +1515,7 @@ void bitmap_close_sync(struct bitmap *bitmap)
* RESYNC bit wherever it is still on
*/
sector_t sector = 0;
- int blocks;
+ sector_t blocks;
if (!bitmap)
return;
while (sector < bitmap->mddev->resync_max_sectors) {
@@ -1528,7 +1528,7 @@ EXPORT_SYMBOL(bitmap_close_sync);
void bitmap_cond_end_sync(struct bitmap *bitmap, sector_t sector)
{
sector_t s = 0;
- int blocks;
+ sector_t blocks;
if (!bitmap)
return;
@@ -1562,7 +1562,7 @@ static void bitmap_set_memory_bits(struct bitmap *bitmap, sector_t offset, int n
* be 0 at this point
*/
- int secs;
+ sector_t secs;
bitmap_counter_t *bmc;
spin_lock_irq(&bitmap->lock);
bmc = bitmap_get_counter(bitmap, offset, &secs, 1);
@@ -1790,7 +1790,7 @@ int bitmap_load(mddev_t *mddev)
* All chunks should be clean, but some might need_sync.
*/
while (sector < mddev->resync_max_sectors) {
- int blocks;
+ sector_t blocks;
bitmap_start_sync(bitmap, sector, &blocks, 0);
sector += blocks;
}
diff --git a/trunk/drivers/md/bitmap.h b/trunk/drivers/md/bitmap.h
index e872a7bad6b8..931a7a7c3796 100644
--- a/trunk/drivers/md/bitmap.h
+++ b/trunk/drivers/md/bitmap.h
@@ -271,8 +271,8 @@ int bitmap_startwrite(struct bitmap *bitmap, sector_t offset,
unsigned long sectors, int behind);
void bitmap_endwrite(struct bitmap *bitmap, sector_t offset,
unsigned long sectors, int success, int behind);
-int bitmap_start_sync(struct bitmap *bitmap, sector_t offset, int *blocks, int degraded);
-void bitmap_end_sync(struct bitmap *bitmap, sector_t offset, int *blocks, int aborted);
+int bitmap_start_sync(struct bitmap *bitmap, sector_t offset, sector_t *blocks, int degraded);
+void bitmap_end_sync(struct bitmap *bitmap, sector_t offset, sector_t *blocks, int aborted);
void bitmap_close_sync(struct bitmap *bitmap);
void bitmap_cond_end_sync(struct bitmap *bitmap, sector_t sector);
diff --git a/trunk/drivers/md/faulty.c b/trunk/drivers/md/faulty.c
index 1a8987884614..339fdc670751 100644
--- a/trunk/drivers/md/faulty.c
+++ b/trunk/drivers/md/faulty.c
@@ -210,7 +210,7 @@ static int make_request(mddev_t *mddev, struct bio *bio)
}
}
if (failit) {
- struct bio *b = bio_clone(bio, GFP_NOIO);
+ struct bio *b = bio_clone_mddev(bio, GFP_NOIO, mddev);
b->bi_bdev = conf->rdev->bdev;
b->bi_private = bio;
b->bi_end_io = faulty_fail;
diff --git a/trunk/drivers/md/md.c b/trunk/drivers/md/md.c
index 225815197a3d..4e957f3140a8 100644
--- a/trunk/drivers/md/md.c
+++ b/trunk/drivers/md/md.c
@@ -57,8 +57,6 @@
#define DEBUG 0
#define dprintk(x...) ((void)(DEBUG && printk(x)))
-static DEFINE_MUTEX(md_mutex);
-
#ifndef MODULE
static void autostart_arrays(int part);
#endif
@@ -69,6 +67,8 @@ static DEFINE_SPINLOCK(pers_lock);
static void md_print_devices(void);
static DECLARE_WAIT_QUEUE_HEAD(resync_wait);
+static struct workqueue_struct *md_wq;
+static struct workqueue_struct *md_misc_wq;
#define MD_BUG(x...) { printk("md: bug in file %s, line %d\n", __FILE__, __LINE__); md_print_devices(); }
@@ -149,6 +149,72 @@ static const struct block_device_operations md_fops;
static int start_readonly;
+/* bio_clone_mddev
+ * like bio_clone, but with a local bio set
+ */
+
+static void mddev_bio_destructor(struct bio *bio)
+{
+ mddev_t *mddev, **mddevp;
+
+ mddevp = (void*)bio;
+ mddev = mddevp[-1];
+
+ bio_free(bio, mddev->bio_set);
+}
+
+struct bio *bio_alloc_mddev(gfp_t gfp_mask, int nr_iovecs,
+ mddev_t *mddev)
+{
+ struct bio *b;
+ mddev_t **mddevp;
+
+ if (!mddev || !mddev->bio_set)
+ return bio_alloc(gfp_mask, nr_iovecs);
+
+ b = bio_alloc_bioset(gfp_mask, nr_iovecs,
+ mddev->bio_set);
+ if (!b)
+ return NULL;
+ mddevp = (void*)b;
+ mddevp[-1] = mddev;
+ b->bi_destructor = mddev_bio_destructor;
+ return b;
+}
+EXPORT_SYMBOL_GPL(bio_alloc_mddev);
+
+struct bio *bio_clone_mddev(struct bio *bio, gfp_t gfp_mask,
+ mddev_t *mddev)
+{
+ struct bio *b;
+ mddev_t **mddevp;
+
+ if (!mddev || !mddev->bio_set)
+ return bio_clone(bio, gfp_mask);
+
+ b = bio_alloc_bioset(gfp_mask, bio->bi_max_vecs,
+ mddev->bio_set);
+ if (!b)
+ return NULL;
+ mddevp = (void*)b;
+ mddevp[-1] = mddev;
+ b->bi_destructor = mddev_bio_destructor;
+ __bio_clone(b, bio);
+ if (bio_integrity(bio)) {
+ int ret;
+
+ ret = bio_integrity_clone(b, bio, gfp_mask, mddev->bio_set);
+
+ if (ret < 0) {
+ bio_put(b);
+ return NULL;
+ }
+ }
+
+ return b;
+}
+EXPORT_SYMBOL_GPL(bio_clone_mddev);
+
/*
* We have a system wide 'event count' that is incremented
* on any 'interesting' event, and readers of /proc/mdstat
@@ -300,7 +366,7 @@ static void md_end_flush(struct bio *bio, int err)
if (atomic_dec_and_test(&mddev->flush_pending)) {
/* The pre-request flush has finished */
- schedule_work(&mddev->flush_work);
+ queue_work(md_wq, &mddev->flush_work);
}
bio_put(bio);
}
@@ -321,7 +387,7 @@ static void submit_flushes(mddev_t *mddev)
atomic_inc(&rdev->nr_pending);
atomic_inc(&rdev->nr_pending);
rcu_read_unlock();
- bi = bio_alloc(GFP_KERNEL, 0);
+ bi = bio_alloc_mddev(GFP_KERNEL, 0, mddev);
bi->bi_end_io = md_end_flush;
bi->bi_private = rdev;
bi->bi_bdev = rdev->bdev;
@@ -369,7 +435,7 @@ void md_flush_request(mddev_t *mddev, struct bio *bio)
submit_flushes(mddev);
if (atomic_dec_and_test(&mddev->flush_pending))
- schedule_work(&mddev->flush_work);
+ queue_work(md_wq, &mddev->flush_work);
}
EXPORT_SYMBOL(md_flush_request);
@@ -428,6 +494,8 @@ static void mddev_delayed_delete(struct work_struct *ws);
static void mddev_put(mddev_t *mddev)
{
+ struct bio_set *bs = NULL;
+
if (!atomic_dec_and_lock(&mddev->active, &all_mddevs_lock))
return;
if (!mddev->raid_disks && list_empty(&mddev->disks) &&
@@ -435,19 +503,22 @@ static void mddev_put(mddev_t *mddev)
/* Array is not configured at all, and not held active,
* so destroy it */
list_del(&mddev->all_mddevs);
+ bs = mddev->bio_set;
+ mddev->bio_set = NULL;
if (mddev->gendisk) {
- /* we did a probe so need to clean up.
- * Call schedule_work inside the spinlock
- * so that flush_scheduled_work() after
- * mddev_find will succeed in waiting for the
- * work to be done.
+ /* We did a probe so need to clean up. Call
+ * queue_work inside the spinlock so that
+ * flush_workqueue() after mddev_find will
+ * succeed in waiting for the work to be done.
*/
INIT_WORK(&mddev->del_work, mddev_delayed_delete);
- schedule_work(&mddev->del_work);
+ queue_work(md_misc_wq, &mddev->del_work);
} else
kfree(mddev);
}
spin_unlock(&all_mddevs_lock);
+ if (bs)
+ bioset_free(bs);
}
void mddev_init(mddev_t *mddev)
@@ -691,7 +762,7 @@ void md_super_write(mddev_t *mddev, mdk_rdev_t *rdev,
* if zero is reached.
* If an error occurred, call md_error
*/
- struct bio *bio = bio_alloc(GFP_NOIO, 1);
+ struct bio *bio = bio_alloc_mddev(GFP_NOIO, 1, mddev);
bio->bi_bdev = rdev->bdev;
bio->bi_sector = sector;
@@ -722,16 +793,16 @@ static void bi_complete(struct bio *bio, int error)
complete((struct completion*)bio->bi_private);
}
-int sync_page_io(struct block_device *bdev, sector_t sector, int size,
- struct page *page, int rw)
+int sync_page_io(mdk_rdev_t *rdev, sector_t sector, int size,
+ struct page *page, int rw)
{
- struct bio *bio = bio_alloc(GFP_NOIO, 1);
+ struct bio *bio = bio_alloc_mddev(GFP_NOIO, 1, rdev->mddev);
struct completion event;
int ret;
rw |= REQ_SYNC | REQ_UNPLUG;
- bio->bi_bdev = bdev;
+ bio->bi_bdev = rdev->bdev;
bio->bi_sector = sector;
bio_add_page(bio, page, size, 0);
init_completion(&event);
@@ -757,7 +828,7 @@ static int read_disk_sb(mdk_rdev_t * rdev, int size)
return 0;
- if (!sync_page_io(rdev->bdev, rdev->sb_start, size, rdev->sb_page, READ))
+ if (!sync_page_io(rdev, rdev->sb_start, size, rdev->sb_page, READ))
goto fail;
rdev->sb_loaded = 1;
return 0;
@@ -1850,7 +1921,7 @@ static void unbind_rdev_from_array(mdk_rdev_t * rdev)
synchronize_rcu();
INIT_WORK(&rdev->del_work, md_delayed_delete);
kobject_get(&rdev->kobj);
- schedule_work(&rdev->del_work);
+ queue_work(md_misc_wq, &rdev->del_work);
}
/*
@@ -2108,6 +2179,8 @@ static void md_update_sb(mddev_t * mddev, int force_change)
if (!mddev->persistent) {
clear_bit(MD_CHANGE_CLEAN, &mddev->flags);
clear_bit(MD_CHANGE_DEVS, &mddev->flags);
+ if (!mddev->external)
+ clear_bit(MD_CHANGE_PENDING, &mddev->flags);
wake_up(&mddev->sb_wait);
return;
}
@@ -4192,10 +4265,10 @@ static int md_alloc(dev_t dev, char *name)
shift = partitioned ? MdpMinorShift : 0;
unit = MINOR(mddev->unit) >> shift;
- /* wait for any previous instance if this device
- * to be completed removed (mddev_delayed_delete).
+ /* wait for any previous instance of this device to be
+ * completely removed (mddev_delayed_delete).
*/
- flush_scheduled_work();
+ flush_workqueue(md_misc_wq);
mutex_lock(&disks_mutex);
error = -EEXIST;
@@ -4378,6 +4451,9 @@ int md_run(mddev_t *mddev)
sysfs_notify_dirent_safe(rdev->sysfs_state);
}
+ if (mddev->bio_set == NULL)
+ mddev->bio_set = bioset_create(BIO_POOL_SIZE, sizeof(mddev));
+
spin_lock(&pers_lock);
pers = find_pers(mddev->level, mddev->clevel);
if (!pers || !try_module_get(pers->owner)) {
@@ -5885,16 +5961,14 @@ static int md_open(struct block_device *bdev, fmode_t mode)
mddev_t *mddev = mddev_find(bdev->bd_dev);
int err;
- mutex_lock(&md_mutex);
if (mddev->gendisk != bdev->bd_disk) {
/* we are racing with mddev_put which is discarding this
* bd_disk.
*/
mddev_put(mddev);
/* Wait until bdev->bd_disk is definitely gone */
- flush_scheduled_work();
+ flush_workqueue(md_misc_wq);
/* Then retry the open from the top */
- mutex_unlock(&md_mutex);
return -ERESTARTSYS;
}
BUG_ON(mddev != bdev->bd_disk->private_data);
@@ -5908,7 +5982,6 @@ static int md_open(struct block_device *bdev, fmode_t mode)
check_disk_size_change(mddev->gendisk, bdev);
out:
- mutex_unlock(&md_mutex);
return err;
}
@@ -5917,10 +5990,8 @@ static int md_release(struct gendisk *disk, fmode_t mode)
mddev_t *mddev = disk->private_data;
BUG_ON(!mddev);
- mutex_lock(&md_mutex);
atomic_dec(&mddev->openers);
mddev_put(mddev);
- mutex_unlock(&md_mutex);
return 0;
}
@@ -6052,7 +6123,7 @@ void md_error(mddev_t *mddev, mdk_rdev_t *rdev)
set_bit(MD_RECOVERY_NEEDED, &mddev->recovery);
md_wakeup_thread(mddev->thread);
if (mddev->event_work.func)
- schedule_work(&mddev->event_work);
+ queue_work(md_misc_wq, &mddev->event_work);
md_new_event_inintr(mddev);
}
@@ -7212,12 +7283,23 @@ static void md_geninit(void)
static int __init md_init(void)
{
- if (register_blkdev(MD_MAJOR, "md"))
- return -1;
- if ((mdp_major=register_blkdev(0, "mdp"))<=0) {
- unregister_blkdev(MD_MAJOR, "md");
- return -1;
- }
+ int ret = -ENOMEM;
+
+ md_wq = alloc_workqueue("md", WQ_RESCUER, 0);
+ if (!md_wq)
+ goto err_wq;
+
+ md_misc_wq = alloc_workqueue("md_misc", 0, 0);
+ if (!md_misc_wq)
+ goto err_misc_wq;
+
+ if ((ret = register_blkdev(MD_MAJOR, "md")) < 0)
+ goto err_md;
+
+ if ((ret = register_blkdev(0, "mdp")) < 0)
+ goto err_mdp;
+ mdp_major = ret;
+
blk_register_region(MKDEV(MD_MAJOR, 0), 1UL<hold_active = 0;
}
+ destroy_workqueue(md_misc_wq);
+ destroy_workqueue(md_wq);
}
subsys_initcall(md_init);
diff --git a/trunk/drivers/md/md.h b/trunk/drivers/md/md.h
index 112a2c32db0c..d05bab55df4e 100644
--- a/trunk/drivers/md/md.h
+++ b/trunk/drivers/md/md.h
@@ -331,6 +331,8 @@ struct mddev_s
struct attribute_group *to_remove;
struct plug_handle *plug; /* if used by personality */
+ struct bio_set *bio_set;
+
/* Generic flush handling.
* The last to finish preflush schedules a worker to submit
* the rest of the request (without the REQ_FLUSH flag).
@@ -495,7 +497,7 @@ extern void md_flush_request(mddev_t *mddev, struct bio *bio);
extern void md_super_write(mddev_t *mddev, mdk_rdev_t *rdev,
sector_t sector, int size, struct page *page);
extern void md_super_wait(mddev_t *mddev);
-extern int sync_page_io(struct block_device *bdev, sector_t sector, int size,
+extern int sync_page_io(mdk_rdev_t *rdev, sector_t sector, int size,
struct page *page, int rw);
extern void md_do_sync(mddev_t *mddev);
extern void md_new_event(mddev_t *mddev);
@@ -517,4 +519,8 @@ extern void md_rdev_init(mdk_rdev_t *rdev);
extern void mddev_suspend(mddev_t *mddev);
extern void mddev_resume(mddev_t *mddev);
+extern struct bio *bio_clone_mddev(struct bio *bio, gfp_t gfp_mask,
+ mddev_t *mddev);
+extern struct bio *bio_alloc_mddev(gfp_t gfp_mask, int nr_iovecs,
+ mddev_t *mddev);
#endif /* _MD_MD_H */
diff --git a/trunk/drivers/md/raid1.c b/trunk/drivers/md/raid1.c
index 378a25894c57..45f8324196ec 100644
--- a/trunk/drivers/md/raid1.c
+++ b/trunk/drivers/md/raid1.c
@@ -100,7 +100,7 @@ static void * r1buf_pool_alloc(gfp_t gfp_flags, void *data)
* Allocate bios : 1 for reading, n-1 for writing
*/
for (j = pi->raid_disks ; j-- ; ) {
- bio = bio_alloc(gfp_flags, RESYNC_PAGES);
+ bio = bio_kmalloc(gfp_flags, RESYNC_PAGES);
if (!bio)
goto out_free_bio;
r1_bio->bios[j] = bio;
@@ -306,6 +306,28 @@ static void raid1_end_read_request(struct bio *bio, int error)
rdev_dec_pending(conf->mirrors[mirror].rdev, conf->mddev);
}
+static void r1_bio_write_done(r1bio_t *r1_bio, int vcnt, struct bio_vec *bv,
+ int behind)
+{
+ if (atomic_dec_and_test(&r1_bio->remaining))
+ {
+ /* it really is the end of this request */
+ if (test_bit(R1BIO_BehindIO, &r1_bio->state)) {
+ /* free extra copy of the data pages */
+ int i = vcnt;
+ while (i--)
+ safe_put_page(bv[i].bv_page);
+ }
+ /* clear the bitmap if all writes complete successfully */
+ bitmap_endwrite(r1_bio->mddev->bitmap, r1_bio->sector,
+ r1_bio->sectors,
+ !test_bit(R1BIO_Degraded, &r1_bio->state),
+ behind);
+ md_write_end(r1_bio->mddev);
+ raid_end_bio_io(r1_bio);
+ }
+}
+
static void raid1_end_write_request(struct bio *bio, int error)
{
int uptodate = test_bit(BIO_UPTODATE, &bio->bi_flags);
@@ -373,21 +395,7 @@ static void raid1_end_write_request(struct bio *bio, int error)
* Let's see if all mirrored write operations have finished
* already.
*/
- if (atomic_dec_and_test(&r1_bio->remaining)) {
- if (test_bit(R1BIO_BehindIO, &r1_bio->state)) {
- /* free extra copy of the data pages */
- int i = bio->bi_vcnt;
- while (i--)
- safe_put_page(bio->bi_io_vec[i].bv_page);
- }
- /* clear the bitmap if all writes complete successfully */
- bitmap_endwrite(r1_bio->mddev->bitmap, r1_bio->sector,
- r1_bio->sectors,
- !test_bit(R1BIO_Degraded, &r1_bio->state),
- behind);
- md_write_end(r1_bio->mddev);
- raid_end_bio_io(r1_bio);
- }
+ r1_bio_write_done(r1_bio, bio->bi_vcnt, bio->bi_io_vec, behind);
if (to_put)
bio_put(to_put);
@@ -411,11 +419,13 @@ static void raid1_end_write_request(struct bio *bio, int error)
static int read_balance(conf_t *conf, r1bio_t *r1_bio)
{
const sector_t this_sector = r1_bio->sector;
- int new_disk = conf->last_used, disk = new_disk;
- int wonly_disk = -1;
const int sectors = r1_bio->sectors;
+ int new_disk = -1;
+ int start_disk;
+ int i;
sector_t new_distance, current_distance;
mdk_rdev_t *rdev;
+ int choose_first;
rcu_read_lock();
/*
@@ -426,54 +436,33 @@ static int read_balance(conf_t *conf, r1bio_t *r1_bio)
retry:
if (conf->mddev->recovery_cp < MaxSector &&
(this_sector + sectors >= conf->next_resync)) {
- /* Choose the first operational device, for consistancy */
- new_disk = 0;
-
- for (rdev = rcu_dereference(conf->mirrors[new_disk].rdev);
- r1_bio->bios[new_disk] == IO_BLOCKED ||
- !rdev || !test_bit(In_sync, &rdev->flags)
- || test_bit(WriteMostly, &rdev->flags);
- rdev = rcu_dereference(conf->mirrors[++new_disk].rdev)) {
-
- if (rdev && test_bit(In_sync, &rdev->flags) &&
- r1_bio->bios[new_disk] != IO_BLOCKED)
- wonly_disk = new_disk;
-
- if (new_disk == conf->raid_disks - 1) {
- new_disk = wonly_disk;
- break;
- }
- }
- goto rb_out;
+ choose_first = 1;
+ start_disk = 0;
+ } else {
+ choose_first = 0;
+ start_disk = conf->last_used;
}
-
/* make sure the disk is operational */
- for (rdev = rcu_dereference(conf->mirrors[new_disk].rdev);
- r1_bio->bios[new_disk] == IO_BLOCKED ||
- !rdev || !test_bit(In_sync, &rdev->flags) ||
- test_bit(WriteMostly, &rdev->flags);
- rdev = rcu_dereference(conf->mirrors[new_disk].rdev)) {
-
- if (rdev && test_bit(In_sync, &rdev->flags) &&
- r1_bio->bios[new_disk] != IO_BLOCKED)
- wonly_disk = new_disk;
-
- if (new_disk <= 0)
- new_disk = conf->raid_disks;
- new_disk--;
- if (new_disk == disk) {
- new_disk = wonly_disk;
+ for (i = 0 ; i < conf->raid_disks ; i++) {
+ int disk = start_disk + i;
+ if (disk >= conf->raid_disks)
+ disk -= conf->raid_disks;
+
+ rdev = rcu_dereference(conf->mirrors[disk].rdev);
+ if (r1_bio->bios[disk] == IO_BLOCKED
+ || rdev == NULL
+ || !test_bit(In_sync, &rdev->flags))
+ continue;
+
+ new_disk = disk;
+ if (!test_bit(WriteMostly, &rdev->flags))
break;
- }
}
- if (new_disk < 0)
+ if (new_disk < 0 || choose_first)
goto rb_out;
- disk = new_disk;
- /* now disk == new_disk == starting point for search */
-
/*
* Don't change to another disk for sequential reads:
*/
@@ -482,20 +471,21 @@ static int read_balance(conf_t *conf, r1bio_t *r1_bio)
if (this_sector == conf->mirrors[new_disk].head_position)
goto rb_out;
- current_distance = abs(this_sector - conf->mirrors[disk].head_position);
-
- /* Find the disk whose head is closest */
+ current_distance = abs(this_sector
+ - conf->mirrors[new_disk].head_position);
- do {
- if (disk <= 0)
- disk = conf->raid_disks;
- disk--;
+ /* look for a better disk - i.e. head is closer */
+ start_disk = new_disk;
+ for (i = 1; i < conf->raid_disks; i++) {
+ int disk = start_disk + 1;
+ if (disk >= conf->raid_disks)
+ disk -= conf->raid_disks;
rdev = rcu_dereference(conf->mirrors[disk].rdev);
-
- if (!rdev || r1_bio->bios[disk] == IO_BLOCKED ||
- !test_bit(In_sync, &rdev->flags) ||
- test_bit(WriteMostly, &rdev->flags))
+ if (r1_bio->bios[disk] == IO_BLOCKED
+ || rdev == NULL
+ || !test_bit(In_sync, &rdev->flags)
+ || test_bit(WriteMostly, &rdev->flags))
continue;
if (!atomic_read(&rdev->nr_pending)) {
@@ -507,11 +497,9 @@ static int read_balance(conf_t *conf, r1bio_t *r1_bio)
current_distance = new_distance;
new_disk = disk;
}
- } while (disk != conf->last_used);
+ }
rb_out:
-
-
if (new_disk >= 0) {
rdev = rcu_dereference(conf->mirrors[new_disk].rdev);
if (!rdev)
@@ -658,7 +646,7 @@ static void raise_barrier(conf_t *conf)
/* block any new IO from starting */
conf->barrier++;
- /* No wait for all pending IO to complete */
+ /* Now wait for all pending IO to complete */
wait_event_lock_irq(conf->wait_barrier,
!conf->nr_pending && conf->barrier < RESYNC_DEPTH,
conf->resync_lock,
@@ -735,23 +723,26 @@ static void unfreeze_array(conf_t *conf)
}
-/* duplicate the data pages for behind I/O */
-static struct page **alloc_behind_pages(struct bio *bio)
+/* duplicate the data pages for behind I/O
+ * We return a list of bio_vec rather than just page pointers
+ * as it makes freeing easier
+ */
+static struct bio_vec *alloc_behind_pages(struct bio *bio)
{
int i;
struct bio_vec *bvec;
- struct page **pages = kzalloc(bio->bi_vcnt * sizeof(struct page *),
+ struct bio_vec *pages = kzalloc(bio->bi_vcnt * sizeof(struct bio_vec),
GFP_NOIO);
if (unlikely(!pages))
goto do_sync_io;
bio_for_each_segment(bvec, bio, i) {
- pages[i] = alloc_page(GFP_NOIO);
- if (unlikely(!pages[i]))
+ pages[i].bv_page = alloc_page(GFP_NOIO);
+ if (unlikely(!pages[i].bv_page))
goto do_sync_io;
- memcpy(kmap(pages[i]) + bvec->bv_offset,
+ memcpy(kmap(pages[i].bv_page) + bvec->bv_offset,
kmap(bvec->bv_page) + bvec->bv_offset, bvec->bv_len);
- kunmap(pages[i]);
+ kunmap(pages[i].bv_page);
kunmap(bvec->bv_page);
}
@@ -759,8 +750,8 @@ static struct page **alloc_behind_pages(struct bio *bio)
do_sync_io:
if (pages)
- for (i = 0; i < bio->bi_vcnt && pages[i]; i++)
- put_page(pages[i]);
+ for (i = 0; i < bio->bi_vcnt && pages[i].bv_page; i++)
+ put_page(pages[i].bv_page);
kfree(pages);
PRINTK("%dB behind alloc failed, doing sync I/O\n", bio->bi_size);
return NULL;
@@ -775,8 +766,7 @@ static int make_request(mddev_t *mddev, struct bio * bio)
int i, targets = 0, disks;
struct bitmap *bitmap;
unsigned long flags;
- struct bio_list bl;
- struct page **behind_pages = NULL;
+ struct bio_vec *behind_pages = NULL;
const int rw = bio_data_dir(bio);
const unsigned long do_sync = (bio->bi_rw & REQ_SYNC);
const unsigned long do_flush_fua = (bio->bi_rw & (REQ_FLUSH | REQ_FUA));
@@ -851,7 +841,7 @@ static int make_request(mddev_t *mddev, struct bio * bio)
}
r1_bio->read_disk = rdisk;
- read_bio = bio_clone(bio, GFP_NOIO);
+ read_bio = bio_clone_mddev(bio, GFP_NOIO, mddev);
r1_bio->bios[rdisk] = read_bio;
@@ -873,13 +863,6 @@ static int make_request(mddev_t *mddev, struct bio * bio)
* bios[x] to bio
*/
disks = conf->raid_disks;
-#if 0
- { static int first=1;
- if (first) printk("First Write sector %llu disks %d\n",
- (unsigned long long)r1_bio->sector, disks);
- first = 0;
- }
-#endif
retry_write:
blocked_rdev = NULL;
rcu_read_lock();
@@ -937,16 +920,17 @@ static int make_request(mddev_t *mddev, struct bio * bio)
(behind_pages = alloc_behind_pages(bio)) != NULL)
set_bit(R1BIO_BehindIO, &r1_bio->state);
- atomic_set(&r1_bio->remaining, 0);
+ atomic_set(&r1_bio->remaining, 1);
atomic_set(&r1_bio->behind_remaining, 0);
- bio_list_init(&bl);
+ bitmap_startwrite(bitmap, bio->bi_sector, r1_bio->sectors,
+ test_bit(R1BIO_BehindIO, &r1_bio->state));
for (i = 0; i < disks; i++) {
struct bio *mbio;
if (!r1_bio->bios[i])
continue;
- mbio = bio_clone(bio, GFP_NOIO);
+ mbio = bio_clone_mddev(bio, GFP_NOIO, mddev);
r1_bio->bios[i] = mbio;
mbio->bi_sector = r1_bio->sector + conf->mirrors[i].rdev->data_offset;
@@ -963,39 +947,29 @@ static int make_request(mddev_t *mddev, struct bio * bio)
* we clear any unused pointer in the io_vec, rather
* than leave them unchanged. This is important
* because when we come to free the pages, we won't
- * know the originial bi_idx, so we just free
+ * know the original bi_idx, so we just free
* them all
*/
__bio_for_each_segment(bvec, mbio, j, 0)
- bvec->bv_page = behind_pages[j];
+ bvec->bv_page = behind_pages[j].bv_page;
if (test_bit(WriteMostly, &conf->mirrors[i].rdev->flags))
atomic_inc(&r1_bio->behind_remaining);
}
atomic_inc(&r1_bio->remaining);
-
- bio_list_add(&bl, mbio);
+ spin_lock_irqsave(&conf->device_lock, flags);
+ bio_list_add(&conf->pending_bio_list, mbio);
+ blk_plug_device(mddev->queue);
+ spin_unlock_irqrestore(&conf->device_lock, flags);
}
+ r1_bio_write_done(r1_bio, bio->bi_vcnt, behind_pages, behind_pages != NULL);
kfree(behind_pages); /* the behind pages are attached to the bios now */
- bitmap_startwrite(bitmap, bio->bi_sector, r1_bio->sectors,
- test_bit(R1BIO_BehindIO, &r1_bio->state));
- spin_lock_irqsave(&conf->device_lock, flags);
- bio_list_merge(&conf->pending_bio_list, &bl);
- bio_list_init(&bl);
-
- blk_plug_device(mddev->queue);
- spin_unlock_irqrestore(&conf->device_lock, flags);
-
- /* In case raid1d snuck into freeze_array */
+ /* In case raid1d snuck in to freeze_array */
wake_up(&conf->wait_barrier);
if (do_sync)
md_wakeup_thread(mddev->thread);
-#if 0
- while ((bio = bio_list_pop(&bl)) != NULL)
- generic_make_request(bio);
-#endif
return 0;
}
@@ -1183,7 +1157,7 @@ static int raid1_remove_disk(mddev_t *mddev, int number)
err = -EBUSY;
goto abort;
}
- /* Only remove non-faulty devices is recovery
+ /* Only remove non-faulty devices if recovery
* is not possible.
*/
if (!test_bit(Faulty, &rdev->flags) &&
@@ -1245,7 +1219,7 @@ static void end_sync_write(struct bio *bio, int error)
break;
}
if (!uptodate) {
- int sync_blocks = 0;
+ sector_t sync_blocks = 0;
sector_t s = r1_bio->sector;
long sectors_to_go = r1_bio->sectors;
/* make sure these bits doesn't get cleared. */
@@ -1388,7 +1362,7 @@ static void sync_request_write(mddev_t *mddev, r1bio_t *r1_bio)
* active, and resync is currently active
*/
rdev = conf->mirrors[d].rdev;
- if (sync_page_io(rdev->bdev,
+ if (sync_page_io(rdev,
sect + rdev->data_offset,
s<<9,
bio->bi_io_vec[idx].bv_page,
@@ -1414,7 +1388,7 @@ static void sync_request_write(mddev_t *mddev, r1bio_t *r1_bio)
continue;
rdev = conf->mirrors[d].rdev;
atomic_add(s, &rdev->corrected_errors);
- if (sync_page_io(rdev->bdev,
+ if (sync_page_io(rdev,
sect + rdev->data_offset,
s<<9,
bio->bi_io_vec[idx].bv_page,
@@ -1429,7 +1403,7 @@ static void sync_request_write(mddev_t *mddev, r1bio_t *r1_bio)
if (r1_bio->bios[d]->bi_end_io != end_sync_read)
continue;
rdev = conf->mirrors[d].rdev;
- if (sync_page_io(rdev->bdev,
+ if (sync_page_io(rdev,
sect + rdev->data_offset,
s<<9,
bio->bi_io_vec[idx].bv_page,
@@ -1513,7 +1487,7 @@ static void fix_read_error(conf_t *conf, int read_disk,
rdev = conf->mirrors[d].rdev;
if (rdev &&
test_bit(In_sync, &rdev->flags) &&
- sync_page_io(rdev->bdev,
+ sync_page_io(rdev,
sect + rdev->data_offset,
s<<9,
conf->tmppage, READ))
@@ -1539,7 +1513,7 @@ static void fix_read_error(conf_t *conf, int read_disk,
rdev = conf->mirrors[d].rdev;
if (rdev &&
test_bit(In_sync, &rdev->flags)) {
- if (sync_page_io(rdev->bdev,
+ if (sync_page_io(rdev,
sect + rdev->data_offset,
s<<9, conf->tmppage, WRITE)
== 0)
@@ -1556,7 +1530,7 @@ static void fix_read_error(conf_t *conf, int read_disk,
rdev = conf->mirrors[d].rdev;
if (rdev &&
test_bit(In_sync, &rdev->flags)) {
- if (sync_page_io(rdev->bdev,
+ if (sync_page_io(rdev,
sect + rdev->data_offset,
s<<9, conf->tmppage, READ)
== 0)
@@ -1646,7 +1620,8 @@ static void raid1d(mddev_t *mddev)
mddev->ro ? IO_BLOCKED : NULL;
r1_bio->read_disk = disk;
bio_put(bio);
- bio = bio_clone(r1_bio->master_bio, GFP_NOIO);
+ bio = bio_clone_mddev(r1_bio->master_bio,
+ GFP_NOIO, mddev);
r1_bio->bios[r1_bio->read_disk] = bio;
rdev = conf->mirrors[disk].rdev;
if (printk_ratelimit())
@@ -1705,7 +1680,7 @@ static sector_t sync_request(mddev_t *mddev, sector_t sector_nr, int *skipped, i
int i;
int wonly = -1;
int write_targets = 0, read_targets = 0;
- int sync_blocks;
+ sector_t sync_blocks;
int still_degraded = 0;
if (!conf->r1buf_pool)
@@ -1755,11 +1730,11 @@ static sector_t sync_request(mddev_t *mddev, sector_t sector_nr, int *skipped, i
msleep_interruptible(1000);
bitmap_cond_end_sync(mddev->bitmap, sector_nr);
+ r1_bio = mempool_alloc(conf->r1buf_pool, GFP_NOIO);
raise_barrier(conf);
conf->next_resync = sector_nr;
- r1_bio = mempool_alloc(conf->r1buf_pool, GFP_NOIO);
rcu_read_lock();
/*
* If we get a correctably read error during resync or recovery,
@@ -1971,7 +1946,6 @@ static conf_t *setup_conf(mddev_t *mddev)
init_waitqueue_head(&conf->wait_barrier);
bio_list_init(&conf->pending_bio_list);
- bio_list_init(&conf->flushing_bio_list);
conf->last_used = -1;
for (i = 0; i < conf->raid_disks; i++) {
diff --git a/trunk/drivers/md/raid1.h b/trunk/drivers/md/raid1.h
index adf8cfd73313..cbfdf1a6acd9 100644
--- a/trunk/drivers/md/raid1.h
+++ b/trunk/drivers/md/raid1.h
@@ -35,8 +35,6 @@ struct r1_private_data_s {
struct list_head retry_list;
/* queue pending writes and submit them on unplug */
struct bio_list pending_bio_list;
- /* queue of writes that have been unplugged */
- struct bio_list flushing_bio_list;
/* for use when syncing mirrors: */
diff --git a/trunk/drivers/md/raid10.c b/trunk/drivers/md/raid10.c
index f0d082f749be..c67aa54694ae 100644
--- a/trunk/drivers/md/raid10.c
+++ b/trunk/drivers/md/raid10.c
@@ -120,7 +120,7 @@ static void * r10buf_pool_alloc(gfp_t gfp_flags, void *data)
* Allocate bios.
*/
for (j = nalloc ; j-- ; ) {
- bio = bio_alloc(gfp_flags, RESYNC_PAGES);
+ bio = bio_kmalloc(gfp_flags, RESYNC_PAGES);
if (!bio)
goto out_free_bio;
r10_bio->devs[j].bio = bio;
@@ -801,7 +801,6 @@ static int make_request(mddev_t *mddev, struct bio * bio)
const int rw = bio_data_dir(bio);
const unsigned long do_sync = (bio->bi_rw & REQ_SYNC);
const unsigned long do_fua = (bio->bi_rw & REQ_FUA);
- struct bio_list bl;
unsigned long flags;
mdk_rdev_t *blocked_rdev;
@@ -890,7 +889,7 @@ static int make_request(mddev_t *mddev, struct bio * bio)
}
mirror = conf->mirrors + disk;
- read_bio = bio_clone(bio, GFP_NOIO);
+ read_bio = bio_clone_mddev(bio, GFP_NOIO, mddev);
r10_bio->devs[slot].bio = read_bio;
@@ -950,16 +949,16 @@ static int make_request(mddev_t *mddev, struct bio * bio)
goto retry_write;
}
- atomic_set(&r10_bio->remaining, 0);
+ atomic_set(&r10_bio->remaining, 1);
+ bitmap_startwrite(mddev->bitmap, bio->bi_sector, r10_bio->sectors, 0);
- bio_list_init(&bl);
for (i = 0; i < conf->copies; i++) {
struct bio *mbio;
int d = r10_bio->devs[i].devnum;
if (!r10_bio->devs[i].bio)
continue;
- mbio = bio_clone(bio, GFP_NOIO);
+ mbio = bio_clone_mddev(bio, GFP_NOIO, mddev);
r10_bio->devs[i].bio = mbio;
mbio->bi_sector = r10_bio->devs[i].addr+
@@ -970,22 +969,22 @@ static int make_request(mddev_t *mddev, struct bio * bio)
mbio->bi_private = r10_bio;
atomic_inc(&r10_bio->remaining);
- bio_list_add(&bl, mbio);
+ spin_lock_irqsave(&conf->device_lock, flags);
+ bio_list_add(&conf->pending_bio_list, mbio);
+ blk_plug_device(mddev->queue);
+ spin_unlock_irqrestore(&conf->device_lock, flags);
}
- if (unlikely(!atomic_read(&r10_bio->remaining))) {
- /* the array is dead */
+ if (atomic_dec_and_test(&r10_bio->remaining)) {
+ /* This matches the end of raid10_end_write_request() */
+ bitmap_endwrite(r10_bio->mddev->bitmap, r10_bio->sector,
+ r10_bio->sectors,
+ !test_bit(R10BIO_Degraded, &r10_bio->state),
+ 0);
md_write_end(mddev);
raid_end_bio_io(r10_bio);
- return 0;
}
- bitmap_startwrite(mddev->bitmap, bio->bi_sector, r10_bio->sectors, 0);
- spin_lock_irqsave(&conf->device_lock, flags);
- bio_list_merge(&conf->pending_bio_list, &bl);
- blk_plug_device(mddev->queue);
- spin_unlock_irqrestore(&conf->device_lock, flags);
-
/* In case raid10d snuck in to freeze_array */
wake_up(&conf->wait_barrier);
@@ -1558,7 +1557,7 @@ static void fix_read_error(conf_t *conf, mddev_t *mddev, r10bio_t *r10_bio)
test_bit(In_sync, &rdev->flags)) {
atomic_inc(&rdev->nr_pending);
rcu_read_unlock();
- success = sync_page_io(rdev->bdev,
+ success = sync_page_io(rdev,
r10_bio->devs[sl].addr +
sect + rdev->data_offset,
s<<9,
@@ -1597,7 +1596,7 @@ static void fix_read_error(conf_t *conf, mddev_t *mddev, r10bio_t *r10_bio)
atomic_inc(&rdev->nr_pending);
rcu_read_unlock();
atomic_add(s, &rdev->corrected_errors);
- if (sync_page_io(rdev->bdev,
+ if (sync_page_io(rdev,
r10_bio->devs[sl].addr +
sect + rdev->data_offset,
s<<9, conf->tmppage, WRITE)
@@ -1634,7 +1633,7 @@ static void fix_read_error(conf_t *conf, mddev_t *mddev, r10bio_t *r10_bio)
char b[BDEVNAME_SIZE];
atomic_inc(&rdev->nr_pending);
rcu_read_unlock();
- if (sync_page_io(rdev->bdev,
+ if (sync_page_io(rdev,
r10_bio->devs[sl].addr +
sect + rdev->data_offset,
s<<9, conf->tmppage,
@@ -1747,7 +1746,8 @@ static void raid10d(mddev_t *mddev)
mdname(mddev),
bdevname(rdev->bdev,b),
(unsigned long long)r10_bio->sector);
- bio = bio_clone(r10_bio->master_bio, GFP_NOIO);
+ bio = bio_clone_mddev(r10_bio->master_bio,
+ GFP_NOIO, mddev);
r10_bio->devs[r10_bio->read_slot].bio = bio;
bio->bi_sector = r10_bio->devs[r10_bio->read_slot].addr
+ rdev->data_offset;
@@ -1820,7 +1820,7 @@ static sector_t sync_request(mddev_t *mddev, sector_t sector_nr, int *skipped, i
int disk;
int i;
int max_sync;
- int sync_blocks;
+ sector_t sync_blocks;
sector_t sectors_skipped = 0;
int chunks_skipped = 0;
diff --git a/trunk/drivers/md/raid5.c b/trunk/drivers/md/raid5.c
index 31140d1259dc..dc574f303f8b 100644
--- a/trunk/drivers/md/raid5.c
+++ b/trunk/drivers/md/raid5.c
@@ -3876,9 +3876,9 @@ static int chunk_aligned_read(mddev_t *mddev, struct bio * raid_bio)
return 0;
}
/*
- * use bio_clone to make a copy of the bio
+ * use bio_clone_mddev to make a copy of the bio
*/
- align_bi = bio_clone(raid_bio, GFP_NOIO);
+ align_bi = bio_clone_mddev(raid_bio, GFP_NOIO, mddev);
if (!align_bi)
return 0;
/*
@@ -4360,7 +4360,7 @@ static inline sector_t sync_request(mddev_t *mddev, sector_t sector_nr, int *ski
raid5_conf_t *conf = mddev->private;
struct stripe_head *sh;
sector_t max_sector = mddev->dev_sectors;
- int sync_blocks;
+ sector_t sync_blocks;
int still_degraded = 0;
int i;
diff --git a/trunk/drivers/misc/ibmasm/ibmasmfs.c b/trunk/drivers/misc/ibmasm/ibmasmfs.c
index 0a53500636c9..d2d5d23416dd 100644
--- a/trunk/drivers/misc/ibmasm/ibmasmfs.c
+++ b/trunk/drivers/misc/ibmasm/ibmasmfs.c
@@ -91,11 +91,10 @@ static void ibmasmfs_create_files (struct super_block *sb, struct dentry *root);
static int ibmasmfs_fill_super (struct super_block *sb, void *data, int silent);
-static int ibmasmfs_get_super(struct file_system_type *fst,
- int flags, const char *name, void *data,
- struct vfsmount *mnt)
+static struct dentry *ibmasmfs_mount(struct file_system_type *fst,
+ int flags, const char *name, void *data)
{
- return get_sb_single(fst, flags, data, ibmasmfs_fill_super, mnt);
+ return mount_single(fst, flags, data, ibmasmfs_fill_super);
}
static const struct super_operations ibmasmfs_s_ops = {
@@ -108,7 +107,7 @@ static const struct file_operations *ibmasmfs_dir_ops = &simple_dir_operations;
static struct file_system_type ibmasmfs_type = {
.owner = THIS_MODULE,
.name = "ibmasmfs",
- .get_sb = ibmasmfs_get_super,
+ .mount = ibmasmfs_mount,
.kill_sb = kill_litter_super,
};
diff --git a/trunk/drivers/misc/kgdbts.c b/trunk/drivers/misc/kgdbts.c
index 72450237a0f4..59c118c19a91 100644
--- a/trunk/drivers/misc/kgdbts.c
+++ b/trunk/drivers/misc/kgdbts.c
@@ -1044,12 +1044,6 @@ static int __init init_kgdbts(void)
return configure_kgdbts();
}
-static void cleanup_kgdbts(void)
-{
- if (configured == 1)
- kgdb_unregister_io_module(&kgdbts_io_ops);
-}
-
static int kgdbts_get_char(void)
{
int val = 0;
@@ -1081,10 +1075,8 @@ static int param_set_kgdbts_var(const char *kmessage, struct kernel_param *kp)
return 0;
}
- if (kgdb_connected) {
- printk(KERN_ERR
- "kgdbts: Cannot reconfigure while KGDB is connected.\n");
-
+ if (configured == 1) {
+ printk(KERN_ERR "kgdbts: ERROR: Already configured and running.\n");
return -EBUSY;
}
@@ -1093,9 +1085,6 @@ static int param_set_kgdbts_var(const char *kmessage, struct kernel_param *kp)
if (config[len - 1] == '\n')
config[len - 1] = '\0';
- if (configured == 1)
- cleanup_kgdbts();
-
/* Go and configure with the new params. */
return configure_kgdbts();
}
@@ -1123,7 +1112,6 @@ static struct kgdb_io kgdbts_io_ops = {
};
module_init(init_kgdbts);
-module_exit(cleanup_kgdbts);
module_param_call(kgdbts, param_set_kgdbts_var, param_get_string, &kps, 0644);
MODULE_PARM_DESC(kgdbts, "[F#|S#][N#]");
MODULE_DESCRIPTION("KGDB Test Suite");
diff --git a/trunk/drivers/mtd/mtdchar.c b/trunk/drivers/mtd/mtdchar.c
index 5ef45487b65f..a34a0fe14884 100644
--- a/trunk/drivers/mtd/mtdchar.c
+++ b/trunk/drivers/mtd/mtdchar.c
@@ -1030,17 +1030,15 @@ static const struct file_operations mtd_fops = {
#endif
};
-static int mtd_inodefs_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data,
- struct vfsmount *mnt)
+static struct dentry *mtd_inodefs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_pseudo(fs_type, "mtd_inode:", NULL, MTD_INODE_FS_MAGIC,
- mnt);
+ return mount_pseudo(fs_type, "mtd_inode:", NULL, MTD_INODE_FS_MAGIC);
}
static struct file_system_type mtd_inodefs_type = {
.name = "mtd_inodefs",
- .get_sb = mtd_inodefs_get_sb,
+ .mount = mtd_inodefs_mount,
.kill_sb = kill_anon_super,
};
diff --git a/trunk/drivers/mtd/mtdsuper.c b/trunk/drivers/mtd/mtdsuper.c
index 38e2ab07e7a3..16b02a1fc100 100644
--- a/trunk/drivers/mtd/mtdsuper.c
+++ b/trunk/drivers/mtd/mtdsuper.c
@@ -54,11 +54,10 @@ static int get_sb_mtd_set(struct super_block *sb, void *_mtd)
/*
* get a superblock on an MTD-backed filesystem
*/
-static int get_sb_mtd_aux(struct file_system_type *fs_type, int flags,
+static struct dentry *mount_mtd_aux(struct file_system_type *fs_type, int flags,
const char *dev_name, void *data,
struct mtd_info *mtd,
- int (*fill_super)(struct super_block *, void *, int),
- struct vfsmount *mnt)
+ int (*fill_super)(struct super_block *, void *, int))
{
struct super_block *sb;
int ret;
@@ -79,57 +78,49 @@ static int get_sb_mtd_aux(struct file_system_type *fs_type, int flags,
ret = fill_super(sb, data, flags & MS_SILENT ? 1 : 0);
if (ret < 0) {
deactivate_locked_super(sb);
- return ret;
+ return ERR_PTR(ret);
}
/* go */
sb->s_flags |= MS_ACTIVE;
- simple_set_mnt(mnt, sb);
-
- return 0;
+ return dget(sb->s_root);
/* new mountpoint for an already mounted superblock */
already_mounted:
DEBUG(1, "MTDSB: Device %d (\"%s\") is already mounted\n",
mtd->index, mtd->name);
- simple_set_mnt(mnt, sb);
- ret = 0;
- goto out_put;
+ put_mtd_device(mtd);
+ return dget(sb->s_root);
out_error:
- ret = PTR_ERR(sb);
-out_put:
put_mtd_device(mtd);
- return ret;
+ return ERR_CAST(sb);
}
/*
* get a superblock on an MTD-backed filesystem by MTD device number
*/
-static int get_sb_mtd_nr(struct file_system_type *fs_type, int flags,
+static struct dentry *mount_mtd_nr(struct file_system_type *fs_type, int flags,
const char *dev_name, void *data, int mtdnr,
- int (*fill_super)(struct super_block *, void *, int),
- struct vfsmount *mnt)
+ int (*fill_super)(struct super_block *, void *, int))
{
struct mtd_info *mtd;
mtd = get_mtd_device(NULL, mtdnr);
if (IS_ERR(mtd)) {
DEBUG(0, "MTDSB: Device #%u doesn't appear to exist\n", mtdnr);
- return PTR_ERR(mtd);
+ return ERR_CAST(mtd);
}
- return get_sb_mtd_aux(fs_type, flags, dev_name, data, mtd, fill_super,
- mnt);
+ return mount_mtd_aux(fs_type, flags, dev_name, data, mtd, fill_super);
}
/*
* set up an MTD-based superblock
*/
-int get_sb_mtd(struct file_system_type *fs_type, int flags,
+struct dentry *mount_mtd(struct file_system_type *fs_type, int flags,
const char *dev_name, void *data,
- int (*fill_super)(struct super_block *, void *, int),
- struct vfsmount *mnt)
+ int (*fill_super)(struct super_block *, void *, int))
{
#ifdef CONFIG_BLOCK
struct block_device *bdev;
@@ -138,7 +129,7 @@ int get_sb_mtd(struct file_system_type *fs_type, int flags,
int mtdnr;
if (!dev_name)
- return -EINVAL;
+ return ERR_PTR(-EINVAL);
DEBUG(2, "MTDSB: dev_name \"%s\"\n", dev_name);
@@ -156,10 +147,10 @@ int get_sb_mtd(struct file_system_type *fs_type, int flags,
mtd = get_mtd_device_nm(dev_name + 4);
if (!IS_ERR(mtd))
- return get_sb_mtd_aux(
+ return mount_mtd_aux(
fs_type, flags,
dev_name, data, mtd,
- fill_super, mnt);
+ fill_super);
printk(KERN_NOTICE "MTD:"
" MTD device with name \"%s\" not found.\n",
@@ -174,9 +165,9 @@ int get_sb_mtd(struct file_system_type *fs_type, int flags,
/* It was a valid number */
DEBUG(1, "MTDSB: mtd%%d, mtdnr %d\n",
mtdnr);
- return get_sb_mtd_nr(fs_type, flags,
+ return mount_mtd_nr(fs_type, flags,
dev_name, data,
- mtdnr, fill_super, mnt);
+ mtdnr, fill_super);
}
}
}
@@ -189,7 +180,7 @@ int get_sb_mtd(struct file_system_type *fs_type, int flags,
if (IS_ERR(bdev)) {
ret = PTR_ERR(bdev);
DEBUG(1, "MTDSB: lookup_bdev() returned %d\n", ret);
- return ret;
+ return ERR_PTR(ret);
}
DEBUG(1, "MTDSB: lookup_bdev() returned 0\n");
@@ -202,8 +193,7 @@ int get_sb_mtd(struct file_system_type *fs_type, int flags,
if (major != MTD_BLOCK_MAJOR)
goto not_an_MTD_device;
- return get_sb_mtd_nr(fs_type, flags, dev_name, data, mtdnr, fill_super,
- mnt);
+ return mount_mtd_nr(fs_type, flags, dev_name, data, mtdnr, fill_super);
not_an_MTD_device:
#endif /* CONFIG_BLOCK */
@@ -212,10 +202,10 @@ int get_sb_mtd(struct file_system_type *fs_type, int flags,
printk(KERN_NOTICE
"MTD: Attempt to mount non-MTD device \"%s\"\n",
dev_name);
- return -EINVAL;
+ return ERR_PTR(-EINVAL);
}
-EXPORT_SYMBOL_GPL(get_sb_mtd);
+EXPORT_SYMBOL_GPL(mount_mtd);
/*
* destroy an MTD-based superblock
diff --git a/trunk/drivers/net/Kconfig b/trunk/drivers/net/Kconfig
index 9334539ebf75..f6668cdaac85 100644
--- a/trunk/drivers/net/Kconfig
+++ b/trunk/drivers/net/Kconfig
@@ -2541,6 +2541,7 @@ source "drivers/net/stmmac/Kconfig"
config PCH_GBE
tristate "PCH Gigabit Ethernet"
depends on PCI
+ select MII
---help---
This is a gigabit ethernet driver for Topcliff PCH.
Topcliff PCH is the platform controller hub that is used in Intel's
diff --git a/trunk/drivers/net/atarilance.c b/trunk/drivers/net/atarilance.c
index 3134e5326231..8cb27cb7bca1 100644
--- a/trunk/drivers/net/atarilance.c
+++ b/trunk/drivers/net/atarilance.c
@@ -407,7 +407,7 @@ static noinline int __init addr_accessible(volatile void *regp, int wordflag,
int writeflag)
{
int ret;
- long flags;
+ unsigned long flags;
long *vbr, save_berr;
local_irq_save(flags);
diff --git a/trunk/drivers/net/cxgb3/cxgb3_main.c b/trunk/drivers/net/cxgb3/cxgb3_main.c
index 4e3c12371aae..407d4e272075 100644
--- a/trunk/drivers/net/cxgb3/cxgb3_main.c
+++ b/trunk/drivers/net/cxgb3/cxgb3_main.c
@@ -3301,7 +3301,6 @@ static int __devinit init_one(struct pci_dev *pdev,
pi->rx_offload = T3_RX_CSUM | T3_LRO;
pi->port_id = i;
netif_carrier_off(netdev);
- netif_tx_stop_all_queues(netdev);
netdev->irq = pdev->irq;
netdev->mem_start = mmio_start;
netdev->mem_end = mmio_start + mmio_len - 1;
@@ -3342,6 +3341,7 @@ static int __devinit init_one(struct pci_dev *pdev,
adapter->name = adapter->port[i]->name;
__set_bit(i, &adapter->registered_device_map);
+ netif_tx_stop_all_queues(adapter->port[i]);
}
}
if (!adapter->registered_device_map) {
diff --git a/trunk/drivers/net/cxgb3/sge.c b/trunk/drivers/net/cxgb3/sge.c
index 5d72bda54389..f9f6645b2e61 100644
--- a/trunk/drivers/net/cxgb3/sge.c
+++ b/trunk/drivers/net/cxgb3/sge.c
@@ -296,8 +296,10 @@ static void free_tx_desc(struct adapter *adapter, struct sge_txq *q,
if (d->skb) { /* an SGL is present */
if (need_unmap)
unmap_skb(d->skb, q, cidx, pdev);
- if (d->eop)
+ if (d->eop) {
kfree_skb(d->skb);
+ d->skb = NULL;
+ }
}
++d;
if (++cidx == q->size) {
diff --git a/trunk/drivers/net/e1000e/82571.c b/trunk/drivers/net/e1000e/82571.c
index ca663f19d7df..7236f1a53ba0 100644
--- a/trunk/drivers/net/e1000e/82571.c
+++ b/trunk/drivers/net/e1000e/82571.c
@@ -52,6 +52,10 @@
(ID_LED_DEF1_DEF2))
#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
+#define E1000_BASE1000T_STATUS 10
+#define E1000_IDLE_ERROR_COUNT_MASK 0xFF
+#define E1000_RECEIVE_ERROR_COUNTER 21
+#define E1000_RECEIVE_ERROR_MAX 0xFFFF
#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
@@ -1242,6 +1246,39 @@ static s32 e1000_led_on_82574(struct e1000_hw *hw)
return 0;
}
+/**
+ * e1000_check_phy_82574 - check 82574 phy hung state
+ * @hw: pointer to the HW structure
+ *
+ * Returns whether phy is hung or not
+ **/
+bool e1000_check_phy_82574(struct e1000_hw *hw)
+{
+ u16 status_1kbt = 0;
+ u16 receive_errors = 0;
+ bool phy_hung = false;
+ s32 ret_val = 0;
+
+ /*
+ * Read PHY Receive Error counter first, if its is max - all F's then
+ * read the Base1000T status register If both are max then PHY is hung.
+ */
+ ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
+
+ if (ret_val)
+ goto out;
+ if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
+ ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
+ if (ret_val)
+ goto out;
+ if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
+ E1000_IDLE_ERROR_COUNT_MASK)
+ phy_hung = true;
+ }
+out:
+ return phy_hung;
+}
+
/**
* e1000_setup_link_82571 - Setup flow control and link settings
* @hw: pointer to the HW structure
@@ -1859,6 +1896,7 @@ struct e1000_info e1000_82574_info = {
| FLAG_HAS_SMART_POWER_DOWN
| FLAG_HAS_AMT
| FLAG_HAS_CTRLEXT_ON_LOAD,
+ .flags2 = FLAG2_CHECK_PHY_HANG,
.pba = 36,
.max_hw_frame_size = DEFAULT_JUMBO,
.get_variants = e1000_get_variants_82571,
diff --git a/trunk/drivers/net/e1000e/e1000.h b/trunk/drivers/net/e1000e/e1000.h
index cee882dd67bf..fdc67fead4ea 100644
--- a/trunk/drivers/net/e1000e/e1000.h
+++ b/trunk/drivers/net/e1000e/e1000.h
@@ -397,6 +397,7 @@ struct e1000_adapter {
struct work_struct print_hang_task;
bool idle_check;
+ int phy_hang_count;
};
struct e1000_info {
@@ -454,6 +455,7 @@ struct e1000_info {
#define FLAG2_HAS_EEE (1 << 5)
#define FLAG2_DMA_BURST (1 << 6)
#define FLAG2_DISABLE_AIM (1 << 8)
+#define FLAG2_CHECK_PHY_HANG (1 << 9)
#define E1000_RX_DESC_PS(R, i) \
(&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
@@ -631,6 +633,7 @@ extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
+extern bool e1000_check_phy_82574(struct e1000_hw *hw);
static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
{
diff --git a/trunk/drivers/net/e1000e/netdev.c b/trunk/drivers/net/e1000e/netdev.c
index ec8cf3f51423..c4ca1629f532 100644
--- a/trunk/drivers/net/e1000e/netdev.c
+++ b/trunk/drivers/net/e1000e/netdev.c
@@ -4098,6 +4098,25 @@ static void e1000e_enable_receives(struct e1000_adapter *adapter)
}
}
+static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
+{
+ struct e1000_hw *hw = &adapter->hw;
+
+ /*
+ * With 82574 controllers, PHY needs to be checked periodically
+ * for hung state and reset, if two calls return true
+ */
+ if (e1000_check_phy_82574(hw))
+ adapter->phy_hang_count++;
+ else
+ adapter->phy_hang_count = 0;
+
+ if (adapter->phy_hang_count > 1) {
+ adapter->phy_hang_count = 0;
+ schedule_work(&adapter->reset_task);
+ }
+}
+
/**
* e1000_watchdog - Timer Call-back
* @data: pointer to adapter cast into an unsigned long
@@ -4333,6 +4352,9 @@ static void e1000_watchdog_task(struct work_struct *work)
if (e1000e_get_laa_state_82571(hw))
e1000e_rar_set(hw, adapter->hw.mac.addr, 0);
+ if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
+ e1000e_check_82574_phy_workaround(adapter);
+
/* Reset the timer */
if (!test_bit(__E1000_DOWN, &adapter->state))
mod_timer(&adapter->watchdog_timer,
@@ -4860,8 +4882,11 @@ static void e1000_reset_task(struct work_struct *work)
struct e1000_adapter *adapter;
adapter = container_of(work, struct e1000_adapter, reset_task);
- e1000e_dump(adapter);
- e_err("Reset adapter\n");
+ if (!((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
+ (adapter->flags & FLAG_RX_RESTART_NOW))) {
+ e1000e_dump(adapter);
+ e_err("Reset adapter\n");
+ }
e1000e_reinit_locked(adapter);
}
diff --git a/trunk/drivers/net/igb/igb_main.c b/trunk/drivers/net/igb/igb_main.c
index 14db09e2fa8b..892d196f17ac 100644
--- a/trunk/drivers/net/igb/igb_main.c
+++ b/trunk/drivers/net/igb/igb_main.c
@@ -4107,7 +4107,6 @@ static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
struct igb_ring *tx_ring)
{
- struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
int tso = 0, count;
u32 tx_flags = 0;
u16 first;
diff --git a/trunk/drivers/net/igbvf/netdev.c b/trunk/drivers/net/igbvf/netdev.c
index ebfaa68ee630..28af019c97bb 100644
--- a/trunk/drivers/net/igbvf/netdev.c
+++ b/trunk/drivers/net/igbvf/netdev.c
@@ -2783,15 +2783,15 @@ static int __devinit igbvf_probe(struct pci_dev *pdev,
/* reset the hardware with the new settings */
igbvf_reset(adapter);
- /* tell the stack to leave us alone until igbvf_open() is called */
- netif_carrier_off(netdev);
- netif_stop_queue(netdev);
-
strcpy(netdev->name, "eth%d");
err = register_netdev(netdev);
if (err)
goto err_hw_init;
+ /* tell the stack to leave us alone until igbvf_open() is called */
+ netif_carrier_off(netdev);
+ netif_stop_queue(netdev);
+
igbvf_print_device_info(adapter);
igbvf_initialize_last_counter_stats(adapter);
diff --git a/trunk/drivers/net/ixgb/ixgb_main.c b/trunk/drivers/net/ixgb/ixgb_main.c
index 666207a9c039..caa8192fff2a 100644
--- a/trunk/drivers/net/ixgb/ixgb_main.c
+++ b/trunk/drivers/net/ixgb/ixgb_main.c
@@ -533,6 +533,7 @@ ixgb_remove(struct pci_dev *pdev)
pci_release_regions(pdev);
free_netdev(netdev);
+ pci_disable_device(pdev);
}
/**
diff --git a/trunk/drivers/net/ixgbe/ixgbe_dcb.c b/trunk/drivers/net/ixgbe/ixgbe_dcb.c
index 8bb9ddb6dffe..0d44c6470ca3 100644
--- a/trunk/drivers/net/ixgbe/ixgbe_dcb.c
+++ b/trunk/drivers/net/ixgbe/ixgbe_dcb.c
@@ -43,9 +43,12 @@
* ixgbe_dcb_check_config().
*/
s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *dcb_config,
- u8 direction)
+ int max_frame, u8 direction)
{
struct tc_bw_alloc *p;
+ int min_credit;
+ int min_multiplier;
+ int min_percent = 100;
s32 ret_val = 0;
/* Initialization values default for Tx settings */
u32 credit_refill = 0;
@@ -59,6 +62,31 @@ s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *dcb_config,
goto out;
}
+ min_credit = ((max_frame / 2) + DCB_CREDIT_QUANTUM - 1) /
+ DCB_CREDIT_QUANTUM;
+
+ /* Find smallest link percentage */
+ for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
+ p = &dcb_config->tc_config[i].path[direction];
+ bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
+ link_percentage = p->bwg_percent;
+
+ link_percentage = (link_percentage * bw_percent) / 100;
+
+ if (link_percentage && link_percentage < min_percent)
+ min_percent = link_percentage;
+ }
+
+ /*
+ * The ratio between traffic classes will control the bandwidth
+ * percentages seen on the wire. To calculate this ratio we use
+ * a multiplier. It is required that the refill credits must be
+ * larger than the max frame size so here we find the smallest
+ * multiplier that will allow all bandwidth percentages to be
+ * greater than the max frame size.
+ */
+ min_multiplier = (min_credit / min_percent) + 1;
+
/* Find out the link percentage for each TC first */
for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
p = &dcb_config->tc_config[i].path[direction];
@@ -73,8 +101,9 @@ s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *dcb_config,
/* Save link_percentage for reference */
p->link_percent = (u8)link_percentage;
- /* Calculate credit refill and save it */
- credit_refill = link_percentage * MINIMUM_CREDIT_REFILL;
+ /* Calculate credit refill ratio using multiplier */
+ credit_refill = min(link_percentage * min_multiplier,
+ MAX_CREDIT_REFILL);
p->data_credits_refill = (u16)credit_refill;
/* Calculate maximum credit for the TC */
@@ -85,8 +114,8 @@ s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *dcb_config,
* of a TC is too small, the maximum credit may not be
* enough to send out a jumbo frame in data plane arbitration.
*/
- if (credit_max && (credit_max < MINIMUM_CREDIT_FOR_JUMBO))
- credit_max = MINIMUM_CREDIT_FOR_JUMBO;
+ if (credit_max && (credit_max < min_credit))
+ credit_max = min_credit;
if (direction == DCB_TX_CONFIG) {
/*
diff --git a/trunk/drivers/net/ixgbe/ixgbe_dcb.h b/trunk/drivers/net/ixgbe/ixgbe_dcb.h
index eb1059f09da0..0208a87b129e 100644
--- a/trunk/drivers/net/ixgbe/ixgbe_dcb.h
+++ b/trunk/drivers/net/ixgbe/ixgbe_dcb.h
@@ -150,15 +150,14 @@ struct ixgbe_dcb_config {
/* DCB driver APIs */
/* DCB credits calculation */
-s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *, u8);
+s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *, int, u8);
/* DCB hw initialization */
s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *);
/* DCB definitions for credit calculation */
+#define DCB_CREDIT_QUANTUM 64 /* DCB Quantum */
#define MAX_CREDIT_REFILL 511 /* 0x1FF * 64B = 32704B */
-#define MINIMUM_CREDIT_REFILL 5 /* 5*64B = 320B */
-#define MINIMUM_CREDIT_FOR_JUMBO 145 /* 145= UpperBound((9*1024+54)/64B) for 9KB jumbo frame */
#define DCB_MAX_TSO_SIZE (32*1024) /* MAX TSO packet size supported in DCB mode */
#define MINIMUM_CREDIT_FOR_TSO (DCB_MAX_TSO_SIZE/64 + 1) /* 513 for 32KB TSO packet */
#define MAX_CREDIT 4095 /* Maximum credit supported: 256KB * 1204 / 64B */
diff --git a/trunk/drivers/net/ixgbe/ixgbe_dcb_82599.c b/trunk/drivers/net/ixgbe/ixgbe_dcb_82599.c
index 67c219f86c3a..05f224715073 100644
--- a/trunk/drivers/net/ixgbe/ixgbe_dcb_82599.c
+++ b/trunk/drivers/net/ixgbe/ixgbe_dcb_82599.c
@@ -397,6 +397,11 @@ static s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw)
reg &= ~IXGBE_RTTDCS_ARBDIS;
IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
+ /* Enable Security TX Buffer IFG for DCB */
+ reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
+ reg |= IXGBE_SECTX_DCB;
+ IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
+
return 0;
}
diff --git a/trunk/drivers/net/ixgbe/ixgbe_dcb_82599.h b/trunk/drivers/net/ixgbe/ixgbe_dcb_82599.h
index 18d7fbf6c292..3841649fb954 100644
--- a/trunk/drivers/net/ixgbe/ixgbe_dcb_82599.h
+++ b/trunk/drivers/net/ixgbe/ixgbe_dcb_82599.h
@@ -95,6 +95,9 @@
#define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */
+/* SECTXMINIFG DCB */
+#define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer IFG */
+
/* DCB hardware-specific driver APIs */
diff --git a/trunk/drivers/net/ixgbe/ixgbe_main.c b/trunk/drivers/net/ixgbe/ixgbe_main.c
index f85631263af8..2bd3eb4ee5a1 100644
--- a/trunk/drivers/net/ixgbe/ixgbe_main.c
+++ b/trunk/drivers/net/ixgbe/ixgbe_main.c
@@ -3347,6 +3347,7 @@ static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
{
struct ixgbe_hw *hw = &adapter->hw;
+ int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
u32 txdctl;
int i, j;
@@ -3359,8 +3360,15 @@ static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
if (hw->mac.type == ixgbe_mac_82598EB)
netif_set_gso_max_size(adapter->netdev, 32768);
- ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
- ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
+#ifdef CONFIG_FCOE
+ if (adapter->netdev->features & NETIF_F_FCOE_MTU)
+ max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
+#endif
+
+ ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, max_frame,
+ DCB_TX_CONFIG);
+ ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, max_frame,
+ DCB_RX_CONFIG);
/* reconfigure the hardware */
ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
diff --git a/trunk/drivers/net/lib8390.c b/trunk/drivers/net/lib8390.c
index 316bb70775b1..e7030ceb178b 100644
--- a/trunk/drivers/net/lib8390.c
+++ b/trunk/drivers/net/lib8390.c
@@ -1077,7 +1077,6 @@ static void __NS8390_init(struct net_device *dev, int startp)
ei_outb_p(ei_local->rx_start_page, e8390_base + EN1_CURPAG);
ei_outb_p(E8390_NODMA+E8390_PAGE0+E8390_STOP, e8390_base+E8390_CMD);
- netif_start_queue(dev);
ei_local->tx1 = ei_local->tx2 = 0;
ei_local->txing = 0;
diff --git a/trunk/drivers/net/netxen/netxen_nic_ctx.c b/trunk/drivers/net/netxen/netxen_nic_ctx.c
index 12612127a087..f7d06cbc70ae 100644
--- a/trunk/drivers/net/netxen/netxen_nic_ctx.c
+++ b/trunk/drivers/net/netxen/netxen_nic_ctx.c
@@ -254,19 +254,6 @@ nx_fw_cmd_create_rx_ctx(struct netxen_adapter *adapter)
return err;
}
-static void
-nx_fw_cmd_reset_ctx(struct netxen_adapter *adapter)
-{
-
- netxen_issue_cmd(adapter, adapter->ahw.pci_func, NXHAL_VERSION,
- adapter->ahw.pci_func, NX_DESTROY_CTX_RESET, 0,
- NX_CDRP_CMD_DESTROY_RX_CTX);
-
- netxen_issue_cmd(adapter, adapter->ahw.pci_func, NXHAL_VERSION,
- adapter->ahw.pci_func, NX_DESTROY_CTX_RESET, 0,
- NX_CDRP_CMD_DESTROY_TX_CTX);
-}
-
static void
nx_fw_cmd_destroy_rx_ctx(struct netxen_adapter *adapter)
{
@@ -698,8 +685,6 @@ int netxen_alloc_hw_resources(struct netxen_adapter *adapter)
if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
if (test_and_set_bit(__NX_FW_ATTACHED, &adapter->state))
goto done;
- if (reset_devices)
- nx_fw_cmd_reset_ctx(adapter);
err = nx_fw_cmd_create_rx_ctx(adapter);
if (err)
goto err_out_free;
diff --git a/trunk/drivers/net/netxen/netxen_nic_main.c b/trunk/drivers/net/netxen/netxen_nic_main.c
index 50820beac3aa..35ae1aa12896 100644
--- a/trunk/drivers/net/netxen/netxen_nic_main.c
+++ b/trunk/drivers/net/netxen/netxen_nic_main.c
@@ -1356,6 +1356,13 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
break;
}
+ if (reset_devices) {
+ if (adapter->portnum == 0) {
+ NXWR32(adapter, NX_CRB_DEV_REF_COUNT, 0);
+ adapter->need_fw_reset = 1;
+ }
+ }
+
err = netxen_start_firmware(adapter);
if (err)
goto err_out_decr_ref;
diff --git a/trunk/drivers/net/stmmac/stmmac_main.c b/trunk/drivers/net/stmmac/stmmac_main.c
index 823b9e6431d5..06bc6034ce81 100644
--- a/trunk/drivers/net/stmmac/stmmac_main.c
+++ b/trunk/drivers/net/stmmac/stmmac_main.c
@@ -337,33 +337,19 @@ static int stmmac_init_phy(struct net_device *dev)
return 0;
}
-static inline void stmmac_mac_enable_rx(void __iomem *ioaddr)
+static inline void stmmac_enable_mac(void __iomem *ioaddr)
{
u32 value = readl(ioaddr + MAC_CTRL_REG);
- value |= MAC_RNABLE_RX;
- /* Set the RE (receive enable bit into the MAC CTRL register). */
- writel(value, ioaddr + MAC_CTRL_REG);
-}
-static inline void stmmac_mac_enable_tx(void __iomem *ioaddr)
-{
- u32 value = readl(ioaddr + MAC_CTRL_REG);
- value |= MAC_ENABLE_TX;
- /* Set the TE (transmit enable bit into the MAC CTRL register). */
+ value |= MAC_RNABLE_RX | MAC_ENABLE_TX;
writel(value, ioaddr + MAC_CTRL_REG);
}
-static inline void stmmac_mac_disable_rx(void __iomem *ioaddr)
+static inline void stmmac_disable_mac(void __iomem *ioaddr)
{
u32 value = readl(ioaddr + MAC_CTRL_REG);
- value &= ~MAC_RNABLE_RX;
- writel(value, ioaddr + MAC_CTRL_REG);
-}
-static inline void stmmac_mac_disable_tx(void __iomem *ioaddr)
-{
- u32 value = readl(ioaddr + MAC_CTRL_REG);
- value &= ~MAC_ENABLE_TX;
+ value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX);
writel(value, ioaddr + MAC_CTRL_REG);
}
@@ -857,8 +843,7 @@ static int stmmac_open(struct net_device *dev)
writel(0xffffffff, priv->ioaddr + MMC_LOW_INTR_MASK);
/* Enable the MAC Rx/Tx */
- stmmac_mac_enable_rx(priv->ioaddr);
- stmmac_mac_enable_tx(priv->ioaddr);
+ stmmac_enable_mac(priv->ioaddr);
/* Set the HW DMA mode and the COE */
stmmac_dma_operation_mode(priv);
@@ -928,9 +913,8 @@ static int stmmac_release(struct net_device *dev)
/* Release and free the Rx/Tx resources */
free_dma_desc_resources(priv);
- /* Disable the MAC core */
- stmmac_mac_disable_tx(priv->ioaddr);
- stmmac_mac_disable_rx(priv->ioaddr);
+ /* Disable the MAC Rx/Tx */
+ stmmac_disable_mac(priv->ioaddr);
netif_carrier_off(dev);
@@ -1787,8 +1771,7 @@ static int stmmac_dvr_remove(struct platform_device *pdev)
priv->hw->dma->stop_rx(priv->ioaddr);
priv->hw->dma->stop_tx(priv->ioaddr);
- stmmac_mac_disable_rx(priv->ioaddr);
- stmmac_mac_disable_tx(priv->ioaddr);
+ stmmac_disable_mac(priv->ioaddr);
netif_carrier_off(ndev);
@@ -1839,13 +1822,11 @@ static int stmmac_suspend(struct platform_device *pdev, pm_message_t state)
dis_ic);
priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
- stmmac_mac_disable_tx(priv->ioaddr);
-
/* Enable Power down mode by programming the PMT regs */
if (device_can_wakeup(priv->device))
priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
else
- stmmac_mac_disable_rx(priv->ioaddr);
+ stmmac_disable_mac(priv->ioaddr);
} else {
priv->shutdown = 1;
/* Although this can appear slightly redundant it actually
@@ -1886,8 +1867,7 @@ static int stmmac_resume(struct platform_device *pdev)
netif_device_attach(dev);
/* Enable the MAC and DMA */
- stmmac_mac_enable_rx(priv->ioaddr);
- stmmac_mac_enable_tx(priv->ioaddr);
+ stmmac_enable_mac(priv->ioaddr);
priv->hw->dma->start_tx(priv->ioaddr);
priv->hw->dma->start_rx(priv->ioaddr);
diff --git a/trunk/drivers/net/wireless/ath/ath5k/attach.c b/trunk/drivers/net/wireless/ath/ath5k/attach.c
index cd0b14a0a93a..fbe8aca975d8 100644
--- a/trunk/drivers/net/wireless/ath/ath5k/attach.c
+++ b/trunk/drivers/net/wireless/ath/ath5k/attach.c
@@ -139,12 +139,12 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
/* Fill the ath5k_hw struct with the needed functions */
ret = ath5k_hw_init_desc_functions(ah);
if (ret)
- goto err_free;
+ goto err;
/* Bring device out of sleep and reset its units */
ret = ath5k_hw_nic_wakeup(ah, 0, true);
if (ret)
- goto err_free;
+ goto err;
/* Get MAC, PHY and RADIO revisions */
ah->ah_mac_srev = srev;
@@ -234,7 +234,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
} else {
ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
ret = -ENODEV;
- goto err_free;
+ goto err;
}
}
@@ -244,7 +244,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
(srev < AR5K_SREV_AR2425)) {
ATH5K_ERR(sc, "Device not yet supported.\n");
ret = -ENODEV;
- goto err_free;
+ goto err;
}
/*
@@ -252,7 +252,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
*/
ret = ath5k_hw_post(ah);
if (ret)
- goto err_free;
+ goto err;
/* Enable pci core retry fix on Hainan (5213A) and later chips */
if (srev >= AR5K_SREV_AR5213A)
@@ -265,7 +265,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
ret = ath5k_eeprom_init(ah);
if (ret) {
ATH5K_ERR(sc, "unable to init EEPROM\n");
- goto err_free;
+ goto err;
}
ee = &ah->ah_capabilities.cap_eeprom;
@@ -307,7 +307,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
if (ret) {
ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
sc->pdev->device);
- goto err_free;
+ goto err;
}
/* Crypto settings */
@@ -341,8 +341,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);
return 0;
-err_free:
- kfree(ah);
+err:
return ret;
}
diff --git a/trunk/drivers/net/wireless/ath/ath9k/ath9k.h b/trunk/drivers/net/wireless/ath/ath9k/ath9k.h
index 973c919fdd27..9b8e7e3fcebd 100644
--- a/trunk/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/trunk/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -310,7 +310,7 @@ struct ath_rx {
u8 rxotherant;
u32 *rxlink;
unsigned int rxfilter;
- spinlock_t rxflushlock;
+ spinlock_t pcu_lock;
spinlock_t rxbuflock;
struct list_head rxbuf;
struct ath_descdma rxdma;
diff --git a/trunk/drivers/net/wireless/ath/ath9k/hif_usb.c b/trunk/drivers/net/wireless/ath/ath9k/hif_usb.c
index 728d904c74d7..6576f683dba0 100644
--- a/trunk/drivers/net/wireless/ath/ath9k/hif_usb.c
+++ b/trunk/drivers/net/wireless/ath/ath9k/hif_usb.c
@@ -801,10 +801,16 @@ static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev)
}
kfree(buf);
- if ((hif_dev->device_id == 0x7010) || (hif_dev->device_id == 0x7015))
+ switch (hif_dev->device_id) {
+ case 0x7010:
+ case 0x7015:
+ case 0x9018:
firm_offset = AR7010_FIRMWARE_TEXT;
- else
+ break;
+ default:
firm_offset = AR9271_FIRMWARE_TEXT;
+ break;
+ }
/*
* Issue FW download complete command to firmware.
diff --git a/trunk/drivers/net/wireless/ath/ath9k/main.c b/trunk/drivers/net/wireless/ath/ath9k/main.c
index c6ec800d7a6b..b52f1cf8a603 100644
--- a/trunk/drivers/net/wireless/ath/ath9k/main.c
+++ b/trunk/drivers/net/wireless/ath/ath9k/main.c
@@ -241,6 +241,9 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
*/
ath9k_hw_set_interrupts(ah, 0);
ath_drain_all_txq(sc, false);
+
+ spin_lock_bh(&sc->rx.pcu_lock);
+
stopped = ath_stoprecv(sc);
/* XXX: do not flush receive queue here. We don't want
@@ -268,6 +271,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
"reset status %d\n",
channel->center_freq, r);
spin_unlock_bh(&sc->sc_resetlock);
+ spin_unlock_bh(&sc->rx.pcu_lock);
goto ps_restore;
}
spin_unlock_bh(&sc->sc_resetlock);
@@ -276,9 +280,12 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
ath_print(common, ATH_DBG_FATAL,
"Unable to restart recv logic\n");
r = -EIO;
+ spin_unlock_bh(&sc->rx.pcu_lock);
goto ps_restore;
}
+ spin_unlock_bh(&sc->rx.pcu_lock);
+
ath_update_txpow(sc);
ath9k_hw_set_interrupts(ah, ah->imask);
@@ -613,7 +620,7 @@ void ath9k_tasklet(unsigned long data)
rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
if (status & rxmask) {
- spin_lock_bh(&sc->rx.rxflushlock);
+ spin_lock_bh(&sc->rx.pcu_lock);
/* Check for high priority Rx first */
if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
@@ -621,7 +628,7 @@ void ath9k_tasklet(unsigned long data)
ath_rx_tasklet(sc, 0, true);
ath_rx_tasklet(sc, 0, false);
- spin_unlock_bh(&sc->rx.rxflushlock);
+ spin_unlock_bh(&sc->rx.pcu_lock);
}
if (status & ATH9K_INT_TX) {
@@ -876,6 +883,7 @@ void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
if (!ah->curchan)
ah->curchan = ath_get_curchannel(sc, sc->hw);
+ spin_lock_bh(&sc->rx.pcu_lock);
spin_lock_bh(&sc->sc_resetlock);
r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
if (r) {
@@ -890,8 +898,10 @@ void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
if (ath_startrecv(sc) != 0) {
ath_print(common, ATH_DBG_FATAL,
"Unable to restart recv logic\n");
+ spin_unlock_bh(&sc->rx.pcu_lock);
return;
}
+ spin_unlock_bh(&sc->rx.pcu_lock);
if (sc->sc_flags & SC_OP_BEACONS)
ath_beacon_config(sc, NULL); /* restart beacons */
@@ -930,6 +940,9 @@ void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
ath9k_hw_set_interrupts(ah, 0);
ath_drain_all_txq(sc, false); /* clear pending tx frames */
+
+ spin_lock_bh(&sc->rx.pcu_lock);
+
ath_stoprecv(sc); /* turn off frame recv */
ath_flushrecv(sc); /* flush recv queue */
@@ -947,6 +960,9 @@ void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
spin_unlock_bh(&sc->sc_resetlock);
ath9k_hw_phy_disable(ah);
+
+ spin_unlock_bh(&sc->rx.pcu_lock);
+
ath9k_hw_configpcipowersave(ah, 1, 1);
ath9k_ps_restore(sc);
ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
@@ -966,6 +982,9 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
ath9k_hw_set_interrupts(ah, 0);
ath_drain_all_txq(sc, retry_tx);
+
+ spin_lock_bh(&sc->rx.pcu_lock);
+
ath_stoprecv(sc);
ath_flushrecv(sc);
@@ -980,6 +999,8 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
ath_print(common, ATH_DBG_FATAL,
"Unable to start recv logic\n");
+ spin_unlock_bh(&sc->rx.pcu_lock);
+
/*
* We may be doing a reset in response to a request
* that changes the channel so update any state that
@@ -1142,6 +1163,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
* be followed by initialization of the appropriate bits
* and then setup of the interrupt mask.
*/
+ spin_lock_bh(&sc->rx.pcu_lock);
spin_lock_bh(&sc->sc_resetlock);
r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
if (r) {
@@ -1150,6 +1172,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
"(freq %u MHz)\n", r,
curchan->center_freq);
spin_unlock_bh(&sc->sc_resetlock);
+ spin_unlock_bh(&sc->rx.pcu_lock);
goto mutex_unlock;
}
spin_unlock_bh(&sc->sc_resetlock);
@@ -1171,8 +1194,10 @@ static int ath9k_start(struct ieee80211_hw *hw)
ath_print(common, ATH_DBG_FATAL,
"Unable to start recv logic\n");
r = -EIO;
+ spin_unlock_bh(&sc->rx.pcu_lock);
goto mutex_unlock;
}
+ spin_unlock_bh(&sc->rx.pcu_lock);
/* Setup our intr mask. */
ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
@@ -1371,12 +1396,14 @@ static void ath9k_stop(struct ieee80211_hw *hw)
* before setting the invalid flag. */
ath9k_hw_set_interrupts(ah, 0);
+ spin_lock_bh(&sc->rx.pcu_lock);
if (!(sc->sc_flags & SC_OP_INVALID)) {
ath_drain_all_txq(sc, false);
ath_stoprecv(sc);
ath9k_hw_phy_disable(ah);
} else
sc->rx.rxlink = NULL;
+ spin_unlock_bh(&sc->rx.pcu_lock);
/* disable HAL and put h/w to sleep */
ath9k_hw_disable(ah);
diff --git a/trunk/drivers/net/wireless/ath/ath9k/rc.c b/trunk/drivers/net/wireless/ath/ath9k/rc.c
index 0cee90cf8dc9..89978d71617f 100644
--- a/trunk/drivers/net/wireless/ath/ath9k/rc.c
+++ b/trunk/drivers/net/wireless/ath/ath9k/rc.c
@@ -527,7 +527,7 @@ static u8 ath_rc_setvalid_rates(struct ath_rate_priv *ath_rc_priv,
for (i = 0; i < rateset->rs_nrates; i++) {
for (j = 0; j < rate_table->rate_cnt; j++) {
u32 phy = rate_table->info[j].phy;
- u16 rate_flags = rate_table->info[i].rate_flags;
+ u16 rate_flags = rate_table->info[j].rate_flags;
u8 rate = rateset->rs_rates[i];
u8 dot11rate = rate_table->info[j].dot11rate;
diff --git a/trunk/drivers/net/wireless/ath/ath9k/recv.c b/trunk/drivers/net/wireless/ath/ath9k/recv.c
index fe73fc50082a..fddb0129bb57 100644
--- a/trunk/drivers/net/wireless/ath/ath9k/recv.c
+++ b/trunk/drivers/net/wireless/ath/ath9k/recv.c
@@ -297,19 +297,17 @@ static void ath_edma_start_recv(struct ath_softc *sc)
ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
- spin_unlock_bh(&sc->rx.rxbuflock);
-
ath_opmode_init(sc);
ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
+
+ spin_unlock_bh(&sc->rx.rxbuflock);
}
static void ath_edma_stop_recv(struct ath_softc *sc)
{
- spin_lock_bh(&sc->rx.rxbuflock);
ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
- spin_unlock_bh(&sc->rx.rxbuflock);
}
int ath_rx_init(struct ath_softc *sc, int nbufs)
@@ -319,7 +317,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
struct ath_buf *bf;
int error = 0;
- spin_lock_init(&sc->rx.rxflushlock);
+ spin_lock_init(&sc->rx.pcu_lock);
sc->sc_flags &= ~SC_OP_RXFLUSH;
spin_lock_init(&sc->rx.rxbuflock);
@@ -506,10 +504,11 @@ int ath_startrecv(struct ath_softc *sc)
ath9k_hw_rxena(ah);
start_recv:
- spin_unlock_bh(&sc->rx.rxbuflock);
ath_opmode_init(sc);
ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
+ spin_unlock_bh(&sc->rx.rxbuflock);
+
return 0;
}
@@ -518,6 +517,7 @@ bool ath_stoprecv(struct ath_softc *sc)
struct ath_hw *ah = sc->sc_ah;
bool stopped;
+ spin_lock_bh(&sc->rx.rxbuflock);
ath9k_hw_stoppcurecv(ah);
ath9k_hw_setrxfilter(ah, 0);
stopped = ath9k_hw_stopdmarecv(ah);
@@ -526,19 +526,18 @@ bool ath_stoprecv(struct ath_softc *sc)
ath_edma_stop_recv(sc);
else
sc->rx.rxlink = NULL;
+ spin_unlock_bh(&sc->rx.rxbuflock);
return stopped;
}
void ath_flushrecv(struct ath_softc *sc)
{
- spin_lock_bh(&sc->rx.rxflushlock);
sc->sc_flags |= SC_OP_RXFLUSH;
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
ath_rx_tasklet(sc, 1, true);
ath_rx_tasklet(sc, 1, false);
sc->sc_flags &= ~SC_OP_RXFLUSH;
- spin_unlock_bh(&sc->rx.rxflushlock);
}
static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
diff --git a/trunk/drivers/net/wireless/ath/ath9k/xmit.c b/trunk/drivers/net/wireless/ath/ath9k/xmit.c
index 30ef2dfc1ed2..f2ade2402ce2 100644
--- a/trunk/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/trunk/drivers/net/wireless/ath/ath9k/xmit.c
@@ -1089,15 +1089,6 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
txq->axq_tx_inprogress = false;
spin_unlock_bh(&txq->axq_lock);
- /* flush any pending frames if aggregation is enabled */
- if (sc->sc_flags & SC_OP_TXAGGR) {
- if (!retry_tx) {
- spin_lock_bh(&txq->axq_lock);
- ath_txq_drain_pending_buffers(sc, txq);
- spin_unlock_bh(&txq->axq_lock);
- }
- }
-
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
spin_lock_bh(&txq->axq_lock);
while (!list_empty(&txq->txq_fifo_pending)) {
@@ -1118,6 +1109,15 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
}
spin_unlock_bh(&txq->axq_lock);
}
+
+ /* flush any pending frames if aggregation is enabled */
+ if (sc->sc_flags & SC_OP_TXAGGR) {
+ if (!retry_tx) {
+ spin_lock_bh(&txq->axq_lock);
+ ath_txq_drain_pending_buffers(sc, txq);
+ spin_unlock_bh(&txq->axq_lock);
+ }
+ }
}
void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
diff --git a/trunk/drivers/net/wireless/b43/sdio.c b/trunk/drivers/net/wireless/b43/sdio.c
index 45933cf8e8c2..9a55338d957f 100644
--- a/trunk/drivers/net/wireless/b43/sdio.c
+++ b/trunk/drivers/net/wireless/b43/sdio.c
@@ -175,7 +175,9 @@ static void b43_sdio_remove(struct sdio_func *func)
struct b43_sdio *sdio = sdio_get_drvdata(func);
ssb_bus_unregister(&sdio->ssb);
+ sdio_claim_host(func);
sdio_disable_func(func);
+ sdio_release_host(func);
kfree(sdio);
sdio_set_drvdata(func, NULL);
}
diff --git a/trunk/drivers/net/wireless/libertas/if_sdio.c b/trunk/drivers/net/wireless/libertas/if_sdio.c
index 296fd00a5129..e5685dc317a8 100644
--- a/trunk/drivers/net/wireless/libertas/if_sdio.c
+++ b/trunk/drivers/net/wireless/libertas/if_sdio.c
@@ -684,18 +684,40 @@ static int if_sdio_prog_firmware(struct if_sdio_card *card)
lbs_deb_enter(LBS_DEB_SDIO);
+ /*
+ * Disable interrupts
+ */
+ sdio_claim_host(card->func);
+ sdio_writeb(card->func, 0x00, IF_SDIO_H_INT_MASK, &ret);
+ sdio_release_host(card->func);
+
sdio_claim_host(card->func);
scratch = if_sdio_read_scratch(card, &ret);
sdio_release_host(card->func);
+ lbs_deb_sdio("firmware status = %#x\n", scratch);
+ lbs_deb_sdio("scratch ret = %d\n", ret);
+
if (ret)
goto out;
- lbs_deb_sdio("firmware status = %#x\n", scratch);
+ /*
+ * The manual clearly describes that FEDC is the right code to use
+ * to detect firmware presence, but for SD8686 it is not that simple.
+ * Scratch is also used to store the RX packet length, so we lose
+ * the FEDC value early on. So we use a non-zero check in order
+ * to validate firmware presence.
+ * Additionally, the SD8686 in the Gumstix always has the high scratch
+ * bit set, even when the firmware is not loaded. So we have to
+ * exclude that from the test.
+ */
if (scratch == IF_SDIO_FIRMWARE_OK) {
lbs_deb_sdio("firmware already loaded\n");
goto success;
+ } else if ((card->model == MODEL_8686) && (scratch & 0x7fff)) {
+ lbs_deb_sdio("firmware may be running\n");
+ goto success;
}
ret = lbs_get_firmware(&card->func->dev, lbs_helper_name, lbs_fw_name,
@@ -709,10 +731,14 @@ static int if_sdio_prog_firmware(struct if_sdio_card *card)
if (ret)
goto out;
+ lbs_deb_sdio("Helper firmware loaded\n");
+
ret = if_sdio_prog_real(card, mainfw);
if (ret)
goto out;
+ lbs_deb_sdio("Firmware loaded\n");
+
success:
sdio_claim_host(card->func);
sdio_set_block_size(card->func, IF_SDIO_BLOCK_SIZE);
@@ -1042,8 +1068,6 @@ static int if_sdio_probe(struct sdio_func *func,
priv->exit_deep_sleep = if_sdio_exit_deep_sleep;
priv->reset_deep_sleep_wakeup = if_sdio_reset_deep_sleep_wakeup;
- priv->fw_ready = 1;
-
sdio_claim_host(func);
/*
@@ -1064,6 +1088,8 @@ static int if_sdio_probe(struct sdio_func *func,
if (ret)
goto reclaim;
+ priv->fw_ready = 1;
+
/*
* FUNC_INIT is required for SD8688 WLAN/BT multiple functions
*/
diff --git a/trunk/drivers/oprofile/oprofilefs.c b/trunk/drivers/oprofile/oprofilefs.c
index 449de59bf35b..e9ff6f7770be 100644
--- a/trunk/drivers/oprofile/oprofilefs.c
+++ b/trunk/drivers/oprofile/oprofilefs.c
@@ -259,17 +259,17 @@ static int oprofilefs_fill_super(struct super_block *sb, void *data, int silent)
}
-static int oprofilefs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *oprofilefs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_single(fs_type, flags, data, oprofilefs_fill_super, mnt);
+ return mount_single(fs_type, flags, data, oprofilefs_fill_super);
}
static struct file_system_type oprofilefs_type = {
.owner = THIS_MODULE,
.name = "oprofilefs",
- .get_sb = oprofilefs_get_sb,
+ .mount = oprofilefs_mount,
.kill_sb = kill_litter_super,
};
diff --git a/trunk/drivers/s390/block/dasd_eckd.c b/trunk/drivers/s390/block/dasd_eckd.c
index 50cf96389d2c..bf61274af3bb 100644
--- a/trunk/drivers/s390/block/dasd_eckd.c
+++ b/trunk/drivers/s390/block/dasd_eckd.c
@@ -2801,6 +2801,73 @@ dasd_eckd_steal_lock(struct dasd_device *device)
return rc;
}
+/*
+ * SNID - Sense Path Group ID
+ * This ioctl may be used in situations where I/O is stalled due to
+ * a reserve, so if the normal dasd_smalloc_request fails, we use the
+ * preallocated dasd_reserve_req.
+ */
+static int dasd_eckd_snid(struct dasd_device *device,
+ void __user *argp)
+{
+ struct dasd_ccw_req *cqr;
+ int rc;
+ struct ccw1 *ccw;
+ int useglobal;
+ struct dasd_snid_ioctl_data usrparm;
+
+ if (!capable(CAP_SYS_ADMIN))
+ return -EACCES;
+
+ if (copy_from_user(&usrparm, argp, sizeof(usrparm)))
+ return -EFAULT;
+
+ useglobal = 0;
+ cqr = dasd_smalloc_request(DASD_ECKD_MAGIC, 1,
+ sizeof(struct dasd_snid_data), device);
+ if (IS_ERR(cqr)) {
+ mutex_lock(&dasd_reserve_mutex);
+ useglobal = 1;
+ cqr = &dasd_reserve_req->cqr;
+ memset(cqr, 0, sizeof(*cqr));
+ memset(&dasd_reserve_req->ccw, 0,
+ sizeof(dasd_reserve_req->ccw));
+ cqr->cpaddr = &dasd_reserve_req->ccw;
+ cqr->data = &dasd_reserve_req->data;
+ cqr->magic = DASD_ECKD_MAGIC;
+ }
+ ccw = cqr->cpaddr;
+ ccw->cmd_code = DASD_ECKD_CCW_SNID;
+ ccw->flags |= CCW_FLAG_SLI;
+ ccw->count = 12;
+ ccw->cda = (__u32)(addr_t) cqr->data;
+ cqr->startdev = device;
+ cqr->memdev = device;
+ clear_bit(DASD_CQR_FLAGS_USE_ERP, &cqr->flags);
+ set_bit(DASD_CQR_FLAGS_FAILFAST, &cqr->flags);
+ cqr->retries = 5;
+ cqr->expires = 10 * HZ;
+ cqr->buildclk = get_clock();
+ cqr->status = DASD_CQR_FILLED;
+ cqr->lpm = usrparm.path_mask;
+
+ rc = dasd_sleep_on_immediatly(cqr);
+ /* verify that I/O processing didn't modify the path mask */
+ if (!rc && usrparm.path_mask && (cqr->lpm != usrparm.path_mask))
+ rc = -EIO;
+ if (!rc) {
+ usrparm.data = *((struct dasd_snid_data *)cqr->data);
+ if (copy_to_user(argp, &usrparm, sizeof(usrparm)))
+ rc = -EFAULT;
+ }
+
+ if (useglobal)
+ mutex_unlock(&dasd_reserve_mutex);
+ else
+ dasd_sfree_request(cqr, cqr->memdev);
+ return rc;
+}
+
/*
* Read performance statistics
*/
@@ -3036,6 +3103,8 @@ dasd_eckd_ioctl(struct dasd_block *block, unsigned int cmd, void __user *argp)
return dasd_eckd_reserve(device);
case BIODASDSLCK:
return dasd_eckd_steal_lock(device);
+ case BIODASDSNID:
+ return dasd_eckd_snid(device, argp);
case BIODASDSYMMIO:
return dasd_symm_io(device, argp);
default:
diff --git a/trunk/drivers/s390/block/dasd_eckd.h b/trunk/drivers/s390/block/dasd_eckd.h
index 0eb49655a6cd..12097c24f2f5 100644
--- a/trunk/drivers/s390/block/dasd_eckd.h
+++ b/trunk/drivers/s390/block/dasd_eckd.h
@@ -27,6 +27,7 @@
#define DASD_ECKD_CCW_WRITE_CKD 0x1d
#define DASD_ECKD_CCW_READ_CKD 0x1e
#define DASD_ECKD_CCW_PSF 0x27
+#define DASD_ECKD_CCW_SNID 0x34
#define DASD_ECKD_CCW_RSSD 0x3e
#define DASD_ECKD_CCW_LOCATE_RECORD 0x47
#define DASD_ECKD_CCW_SNSS 0x54
diff --git a/trunk/drivers/s390/char/tape_core.c b/trunk/drivers/s390/char/tape_core.c
index 29c2d73d719d..6c408670e08d 100644
--- a/trunk/drivers/s390/char/tape_core.c
+++ b/trunk/drivers/s390/char/tape_core.c
@@ -1077,15 +1077,14 @@ __tape_do_irq (struct ccw_device *cdev, unsigned long intparm, struct irb *irb)
/* FIXME: What to do with the request? */
switch (PTR_ERR(irb)) {
case -ETIMEDOUT:
- DBF_LH(1, "(%s): Request timed out\n",
- dev_name(&cdev->dev));
+ DBF_LH(1, "(%08x): Request timed out\n",
+ device->cdev_id);
case -EIO:
__tape_end_request(device, request, -EIO);
break;
default:
- DBF_LH(1, "(%s): Unexpected i/o error %li\n",
- dev_name(&cdev->dev),
- PTR_ERR(irb));
+ DBF_LH(1, "(%08x): Unexpected i/o error %li\n",
+ device->cdev_id, PTR_ERR(irb));
}
return;
}
diff --git a/trunk/drivers/s390/char/tape_std.c b/trunk/drivers/s390/char/tape_std.c
index 03f07e5dd6e9..3c3f342149ec 100644
--- a/trunk/drivers/s390/char/tape_std.c
+++ b/trunk/drivers/s390/char/tape_std.c
@@ -47,8 +47,8 @@ tape_std_assign_timeout(unsigned long data)
device->cdev_id);
rc = tape_cancel_io(device, request);
if(rc)
- DBF_EVENT(3, "(%s): Assign timeout: Cancel failed with rc = %i\n",
- dev_name(&device->cdev->dev), rc);
+ DBF_EVENT(3, "(%08x): Assign timeout: Cancel failed with rc = "
+ "%i\n", device->cdev_id, rc);
}
int
diff --git a/trunk/drivers/staging/Kconfig b/trunk/drivers/staging/Kconfig
index f9c9c8a397db..5eafdf435550 100644
--- a/trunk/drivers/staging/Kconfig
+++ b/trunk/drivers/staging/Kconfig
@@ -87,8 +87,6 @@ source "drivers/staging/rtl8712/Kconfig"
source "drivers/staging/frontier/Kconfig"
-source "drivers/staging/dream/Kconfig"
-
source "drivers/staging/pohmelfs/Kconfig"
source "drivers/staging/autofs/Kconfig"
diff --git a/trunk/drivers/staging/Makefile b/trunk/drivers/staging/Makefile
index a85074f8321b..a97a955c094b 100644
--- a/trunk/drivers/staging/Makefile
+++ b/trunk/drivers/staging/Makefile
@@ -28,7 +28,6 @@ obj-$(CONFIG_RTL8192E) += rtl8192e/
obj-$(CONFIG_R8712U) += rtl8712/
obj-$(CONFIG_SPECTRA) += spectra/
obj-$(CONFIG_TRANZPORT) += frontier/
-obj-$(CONFIG_DREAM) += dream/
obj-$(CONFIG_POHMELFS) += pohmelfs/
obj-$(CONFIG_AUTOFS_FS) += autofs/
obj-$(CONFIG_IDE_PHISON) += phison/
diff --git a/trunk/drivers/staging/autofs/init.c b/trunk/drivers/staging/autofs/init.c
index 765c72f42976..5e4b372ea663 100644
--- a/trunk/drivers/staging/autofs/init.c
+++ b/trunk/drivers/staging/autofs/init.c
@@ -14,16 +14,16 @@
#include
#include "autofs_i.h"
-static int autofs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *autofs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_nodev(fs_type, flags, data, autofs_fill_super, mnt);
+ return mount_nodev(fs_type, flags, data, autofs_fill_super);
}
static struct file_system_type autofs_fs_type = {
.owner = THIS_MODULE,
.name = "autofs",
- .get_sb = autofs_get_sb,
+ .mount = autofs_mount,
.kill_sb = autofs_kill_sb,
};
diff --git a/trunk/drivers/staging/dream/Kconfig b/trunk/drivers/staging/dream/Kconfig
deleted file mode 100644
index 0c30b19a5a7c..000000000000
--- a/trunk/drivers/staging/dream/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-config DREAM
- tristate "HTC Dream support"
- depends on MACH_TROUT
-
-if DREAM
-
-source "drivers/staging/dream/camera/Kconfig"
-
-config INPUT_GPIO
- tristate "GPIO driver support"
- help
- Say Y here if you want to support gpio based keys, wheels etc...
-endif
diff --git a/trunk/drivers/staging/dream/Makefile b/trunk/drivers/staging/dream/Makefile
deleted file mode 100644
index 87de1a57f237..000000000000
--- a/trunk/drivers/staging/dream/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-ccflags-y:=-Idrivers/staging/dream/include
-obj-$(CONFIG_MSM_ADSP) += qdsp5/
-obj-$(CONFIG_MSM_CAMERA) += camera/
-obj-$(CONFIG_INPUT_GPIO) += gpio_axis.o gpio_event.o gpio_input.o gpio_matrix.o gpio_output.o
-
diff --git a/trunk/drivers/staging/dream/TODO b/trunk/drivers/staging/dream/TODO
deleted file mode 100644
index dcd3ba808655..000000000000
--- a/trunk/drivers/staging/dream/TODO
+++ /dev/null
@@ -1,13 +0,0 @@
-
-* camera driver uses old V4L API
-
-* coding style in some places is lacking
-
-* gpio_input.c has some features matrix_keypad lacks. They should be
-merged to gpio_input, with gpio_input.c removed
-
-* pmem provides interface for userspace. Needs to be reviewed at least.
-
-* it is probably possible to simplify touchscreen driver using threaded_irq's.
-
-* touchscreen driver should be switched to oficial multitouch API
diff --git a/trunk/drivers/staging/dream/camera/Kconfig b/trunk/drivers/staging/dream/camera/Kconfig
deleted file mode 100644
index bfb6d241d807..000000000000
--- a/trunk/drivers/staging/dream/camera/Kconfig
+++ /dev/null
@@ -1,46 +0,0 @@
-comment "Qualcomm MSM Camera And Video"
-
-menuconfig MSM_CAMERA
- bool "Qualcomm MSM camera and video capture support"
- depends on ARCH_MSM && VIDEO_V4L2_COMMON
- help
- Say Y here to enable selecting the video adapters for
- Qualcomm msm camera and video encoding
-
-config MSM_CAMERA_DEBUG
- bool "Qualcomm MSM camera debugging with printk"
- depends on MSM_CAMERA
- help
- Enable printk() debug for msm camera
-
-config MSM_CAMERA_FLASH
- bool "Qualcomm MSM camera flash support"
- depends on MSM_CAMERA && BROKEN
- ---help---
- Enable support for LED flash for msm camera
-
-
-comment "Camera Sensor Selection"
-config MT9T013
- bool "Sensor mt9t013 (BAYER 3M)"
- depends on MSM_CAMERA
- ---help---
- MICRON 3M Bayer Sensor with AutoFocus
-
-config MT9D112
- bool "Sensor mt9d112 (YUV 2M)"
- depends on MSM_CAMERA
- ---help---
- MICRON 2M YUV Sensor
-
-config MT9P012
- bool "Sensor mt9p012 (BAYER 5M)"
- depends on MSM_CAMERA
- ---help---
- MICRON 5M Bayer Sensor with Autofocus
-
-config S5K3E2FX
- bool "Sensor s5k3e2fx (Samsung 5M)"
- depends on MSM_CAMERA
- ---help---
- Samsung 5M with Autofocus
diff --git a/trunk/drivers/staging/dream/camera/Makefile b/trunk/drivers/staging/dream/camera/Makefile
deleted file mode 100644
index 03711dc6f482..000000000000
--- a/trunk/drivers/staging/dream/camera/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-ccflags-y:=-Idrivers/staging/dream/include
-obj-$(CONFIG_MT9T013) += mt9t013.o mt9t013_reg.o
-obj-$(CONFIG_MT9D112) += mt9d112.o mt9d112_reg.o
-obj-$(CONFIG_MT9P012) += mt9p012_fox.o mt9p012_reg.o
-obj-$(CONFIG_MSM_CAMERA) += msm_camera.o msm_v4l2.o
-obj-$(CONFIG_S5K3E2FX) += s5k3e2fx.o
-obj-$(CONFIG_ARCH_MSM) += msm_vfe7x.o msm_io7x.o
-obj-$(CONFIG_ARCH_QSD) += msm_vfe8x.o msm_vfe8x_proc.o msm_io8x.o
diff --git a/trunk/drivers/staging/dream/camera/msm_camera.c b/trunk/drivers/staging/dream/camera/msm_camera.c
deleted file mode 100644
index de4ab61efd4b..000000000000
--- a/trunk/drivers/staging/dream/camera/msm_camera.c
+++ /dev/null
@@ -1,2181 +0,0 @@
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-/* FIXME: most allocations need not be GFP_ATOMIC */
-/* FIXME: management of mutexes */
-/* FIXME: msm_pmem_region_lookup return values */
-/* FIXME: way too many copy to/from user */
-/* FIXME: does region->active mean free */
-/* FIXME: check limits on command lenghts passed from userspace */
-/* FIXME: __msm_release: which queues should we flush when opencnt != 0 */
-
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#define MSM_MAX_CAMERA_SENSORS 5
-
-#define ERR_USER_COPY(to) pr_err("%s(%d): copy %s user\n", \
- __func__, __LINE__, ((to) ? "to" : "from"))
-#define ERR_COPY_FROM_USER() ERR_USER_COPY(0)
-#define ERR_COPY_TO_USER() ERR_USER_COPY(1)
-
-static struct class *msm_class;
-static dev_t msm_devno;
-static LIST_HEAD(msm_sensors);
-
-#define __CONTAINS(r, v, l, field) ({ \
- typeof(r) __r = r; \
- typeof(v) __v = v; \
- typeof(v) __e = __v + l; \
- int res = __v >= __r->field && \
- __e <= __r->field + __r->len; \
- res; \
-})
-
-#define CONTAINS(r1, r2, field) ({ \
- typeof(r2) __r2 = r2; \
- __CONTAINS(r1, __r2->field, __r2->len, field); \
-})
-
-#define IN_RANGE(r, v, field) ({ \
- typeof(r) __r = r; \
- typeof(v) __vv = v; \
- int res = ((__vv >= __r->field) && \
- (__vv < (__r->field + __r->len))); \
- res; \
-})
-
-#define OVERLAPS(r1, r2, field) ({ \
- typeof(r1) __r1 = r1; \
- typeof(r2) __r2 = r2; \
- typeof(__r2->field) __v = __r2->field; \
- typeof(__v) __e = __v + __r2->len - 1; \
- int res = (IN_RANGE(__r1, __v, field) || \
- IN_RANGE(__r1, __e, field)); \
- res; \
-})
-
-#define MSM_DRAIN_QUEUE_NOSYNC(sync, name) do { \
- struct msm_queue_cmd *qcmd = NULL; \
- CDBG("%s: draining queue "#name"\n", __func__); \
- while (!list_empty(&(sync)->name)) { \
- qcmd = list_first_entry(&(sync)->name, \
- struct msm_queue_cmd, list); \
- list_del_init(&qcmd->list); \
- kfree(qcmd); \
- }; \
-} while (0)
-
-#define MSM_DRAIN_QUEUE(sync, name) do { \
- unsigned long flags; \
- spin_lock_irqsave(&(sync)->name##_lock, flags); \
- MSM_DRAIN_QUEUE_NOSYNC(sync, name); \
- spin_unlock_irqrestore(&(sync)->name##_lock, flags); \
-} while (0)
-
-static int check_overlap(struct hlist_head *ptype,
- unsigned long paddr,
- unsigned long len)
-{
- struct msm_pmem_region *region;
- struct msm_pmem_region t = { .paddr = paddr, .len = len };
- struct hlist_node *node;
-
- hlist_for_each_entry(region, node, ptype, list) {
- if (CONTAINS(region, &t, paddr) ||
- CONTAINS(&t, region, paddr) ||
- OVERLAPS(region, &t, paddr)) {
- printk(KERN_ERR
- " region (PHYS %p len %ld)"
- " clashes with registered region"
- " (paddr %p len %ld)\n",
- (void *)t.paddr, t.len,
- (void *)region->paddr, region->len);
- return -1;
- }
- }
-
- return 0;
-}
-
-static int msm_pmem_table_add(struct hlist_head *ptype,
- struct msm_pmem_info *info)
-{
- struct file *file;
- unsigned long paddr;
- unsigned long vstart;
- unsigned long len;
- int rc;
- struct msm_pmem_region *region;
-
- rc = get_pmem_file(info->fd, &paddr, &vstart, &len, &file);
- if (rc < 0) {
- pr_err("msm_pmem_table_add: get_pmem_file fd %d error %d\n",
- info->fd, rc);
- return rc;
- }
-
- if (check_overlap(ptype, paddr, len) < 0)
- return -EINVAL;
-
- CDBG("%s: type = %d, paddr = 0x%lx, vaddr = 0x%lx\n",
- __func__,
- info->type, paddr, (unsigned long)info->vaddr);
-
- region = kmalloc(sizeof(*region), GFP_KERNEL);
- if (!region)
- return -ENOMEM;
-
- INIT_HLIST_NODE(®ion->list);
-
- region->type = info->type;
- region->vaddr = info->vaddr;
- region->paddr = paddr;
- region->len = len;
- region->file = file;
- region->y_off = info->y_off;
- region->cbcr_off = info->cbcr_off;
- region->fd = info->fd;
- region->active = info->active;
-
- hlist_add_head(&(region->list), ptype);
-
- return 0;
-}
-
-/* return of 0 means failure */
-static uint8_t msm_pmem_region_lookup(struct hlist_head *ptype,
- int pmem_type, struct msm_pmem_region *reg, uint8_t maxcount)
-{
- struct msm_pmem_region *region;
- struct msm_pmem_region *regptr;
- struct hlist_node *node, *n;
-
- uint8_t rc = 0;
-
- regptr = reg;
-
- hlist_for_each_entry_safe(region, node, n, ptype, list) {
- if (region->type == pmem_type && region->active) {
- *regptr = *region;
- rc += 1;
- if (rc >= maxcount)
- break;
- regptr++;
- }
- }
-
- return rc;
-}
-
-static unsigned long msm_pmem_frame_ptov_lookup(struct msm_sync *sync,
- unsigned long pyaddr,
- unsigned long pcbcraddr,
- uint32_t *yoff, uint32_t *cbcroff, int *fd)
-{
- struct msm_pmem_region *region;
- struct hlist_node *node, *n;
-
- hlist_for_each_entry_safe(region, node, n, &sync->frame, list) {
- if (pyaddr == (region->paddr + region->y_off) &&
- pcbcraddr == (region->paddr +
- region->cbcr_off) &&
- region->active) {
- /* offset since we could pass vaddr inside
- * a registerd pmem buffer
- */
- *yoff = region->y_off;
- *cbcroff = region->cbcr_off;
- *fd = region->fd;
- region->active = 0;
- return (unsigned long)(region->vaddr);
- }
- }
-
- return 0;
-}
-
-static unsigned long msm_pmem_stats_ptov_lookup(struct msm_sync *sync,
- unsigned long addr, int *fd)
-{
- struct msm_pmem_region *region;
- struct hlist_node *node, *n;
-
- hlist_for_each_entry_safe(region, node, n, &sync->stats, list) {
- if (addr == region->paddr && region->active) {
- /* offset since we could pass vaddr inside a
- * registered pmem buffer */
- *fd = region->fd;
- region->active = 0;
- return (unsigned long)(region->vaddr);
- }
- }
-
- return 0;
-}
-
-static unsigned long msm_pmem_frame_vtop_lookup(struct msm_sync *sync,
- unsigned long buffer,
- uint32_t yoff, uint32_t cbcroff, int fd)
-{
- struct msm_pmem_region *region;
- struct hlist_node *node, *n;
-
- hlist_for_each_entry_safe(region,
- node, n, &sync->frame, list) {
- if (((unsigned long)(region->vaddr) == buffer) &&
- (region->y_off == yoff) &&
- (region->cbcr_off == cbcroff) &&
- (region->fd == fd) &&
- (region->active == 0)) {
-
- region->active = 1;
- return region->paddr;
- }
- }
-
- return 0;
-}
-
-static unsigned long msm_pmem_stats_vtop_lookup(
- struct msm_sync *sync,
- unsigned long buffer,
- int fd)
-{
- struct msm_pmem_region *region;
- struct hlist_node *node, *n;
-
- hlist_for_each_entry_safe(region, node, n, &sync->stats, list) {
- if (((unsigned long)(region->vaddr) == buffer) &&
- (region->fd == fd) && region->active == 0) {
- region->active = 1;
- return region->paddr;
- }
- }
-
- return 0;
-}
-
-static int __msm_pmem_table_del(struct msm_sync *sync,
- struct msm_pmem_info *pinfo)
-{
- int rc = 0;
- struct msm_pmem_region *region;
- struct hlist_node *node, *n;
-
- switch (pinfo->type) {
- case MSM_PMEM_OUTPUT1:
- case MSM_PMEM_OUTPUT2:
- case MSM_PMEM_THUMBAIL:
- case MSM_PMEM_MAINIMG:
- case MSM_PMEM_RAW_MAINIMG:
- hlist_for_each_entry_safe(region, node, n,
- &sync->frame, list) {
-
- if (pinfo->type == region->type &&
- pinfo->vaddr == region->vaddr &&
- pinfo->fd == region->fd) {
- hlist_del(node);
- put_pmem_file(region->file);
- kfree(region);
- }
- }
- break;
-
- case MSM_PMEM_AEC_AWB:
- case MSM_PMEM_AF:
- hlist_for_each_entry_safe(region, node, n,
- &sync->stats, list) {
-
- if (pinfo->type == region->type &&
- pinfo->vaddr == region->vaddr &&
- pinfo->fd == region->fd) {
- hlist_del(node);
- put_pmem_file(region->file);
- kfree(region);
- }
- }
- break;
-
- default:
- rc = -EINVAL;
- break;
- }
-
- return rc;
-}
-
-static int msm_pmem_table_del(struct msm_sync *sync, void __user *arg)
-{
- struct msm_pmem_info info;
-
- if (copy_from_user(&info, arg, sizeof(info))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- return __msm_pmem_table_del(sync, &info);
-}
-
-static int __msm_get_frame(struct msm_sync *sync,
- struct msm_frame *frame)
-{
- unsigned long flags;
- int rc = 0;
-
- struct msm_queue_cmd *qcmd = NULL;
- struct msm_vfe_phy_info *pphy;
-
- spin_lock_irqsave(&sync->prev_frame_q_lock, flags);
- if (!list_empty(&sync->prev_frame_q)) {
- qcmd = list_first_entry(&sync->prev_frame_q,
- struct msm_queue_cmd, list);
- list_del_init(&qcmd->list);
- }
- spin_unlock_irqrestore(&sync->prev_frame_q_lock, flags);
-
- if (!qcmd) {
- pr_err("%s: no preview frame.\n", __func__);
- return -EAGAIN;
- }
-
- pphy = (struct msm_vfe_phy_info *)(qcmd->command);
-
- frame->buffer =
- msm_pmem_frame_ptov_lookup(sync,
- pphy->y_phy,
- pphy->cbcr_phy, &(frame->y_off),
- &(frame->cbcr_off), &(frame->fd));
- if (!frame->buffer) {
- pr_err("%s: cannot get frame, invalid lookup address "
- "y=%x cbcr=%x offset=%d\n",
- __func__,
- pphy->y_phy,
- pphy->cbcr_phy,
- frame->y_off);
- rc = -EINVAL;
- }
-
- CDBG("__msm_get_frame: y=0x%x, cbcr=0x%x, qcmd=0x%x, virt_addr=0x%x\n",
- pphy->y_phy, pphy->cbcr_phy, (int) qcmd, (int) frame->buffer);
-
- kfree(qcmd);
- return rc;
-}
-
-static int msm_get_frame(struct msm_sync *sync, void __user *arg)
-{
- int rc = 0;
- struct msm_frame frame;
-
- if (copy_from_user(&frame,
- arg,
- sizeof(struct msm_frame))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- rc = __msm_get_frame(sync, &frame);
- if (rc < 0)
- return rc;
-
- if (sync->croplen) {
- if (frame.croplen > sync->croplen) {
- pr_err("msm_get_frame: invalid frame croplen %d\n",
- frame.croplen);
- return -EINVAL;
- }
-
- if (copy_to_user((void *)frame.cropinfo,
- sync->cropinfo,
- sync->croplen)) {
- ERR_COPY_TO_USER();
- return -EFAULT;
- }
- }
-
- if (copy_to_user((void *)arg,
- &frame, sizeof(struct msm_frame))) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- }
-
- CDBG("Got frame!!!\n");
-
- return rc;
-}
-
-static int msm_enable_vfe(struct msm_sync *sync, void __user *arg)
-{
- int rc = -EIO;
- struct camera_enable_cmd cfg;
-
- if (copy_from_user(&cfg,
- arg,
- sizeof(struct camera_enable_cmd))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- if (sync->vfefn.vfe_enable)
- rc = sync->vfefn.vfe_enable(&cfg);
-
- CDBG("msm_enable_vfe: returned rc = %d\n", rc);
- return rc;
-}
-
-static int msm_disable_vfe(struct msm_sync *sync, void __user *arg)
-{
- int rc = -EIO;
- struct camera_enable_cmd cfg;
-
- if (copy_from_user(&cfg,
- arg,
- sizeof(struct camera_enable_cmd))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- if (sync->vfefn.vfe_disable)
- rc = sync->vfefn.vfe_disable(&cfg, NULL);
-
- CDBG("msm_disable_vfe: returned rc = %d\n", rc);
- return rc;
-}
-
-static struct msm_queue_cmd *__msm_control(struct msm_sync *sync,
- struct msm_control_device_queue *queue,
- struct msm_queue_cmd *qcmd,
- int timeout)
-{
- unsigned long flags;
- int rc;
-
- spin_lock_irqsave(&sync->msg_event_q_lock, flags);
- list_add_tail(&qcmd->list, &sync->msg_event_q);
- /* wake up config thread */
- wake_up(&sync->msg_event_wait);
- spin_unlock_irqrestore(&sync->msg_event_q_lock, flags);
-
- if (!queue)
- return NULL;
-
- /* wait for config status */
- rc = wait_event_interruptible_timeout(
- queue->ctrl_status_wait,
- !list_empty_careful(&queue->ctrl_status_q),
- timeout);
- if (list_empty_careful(&queue->ctrl_status_q)) {
- if (!rc)
- rc = -ETIMEDOUT;
- if (rc < 0) {
- pr_err("msm_control: wait_event error %d\n", rc);
-#if 0
- /* This is a bit scary. If we time out too early, we
- * will free qcmd at the end of this function, and the
- * dsp may do the same when it does respond, so we
- * remove the message from the source queue.
- */
- pr_err("%s: error waiting for ctrl_status_q: %d\n",
- __func__, rc);
- spin_lock_irqsave(&sync->msg_event_q_lock, flags);
- list_del_init(&qcmd->list);
- spin_unlock_irqrestore(&sync->msg_event_q_lock, flags);
-#endif
- return ERR_PTR(rc);
- }
- }
-
- /* control command status is ready */
- spin_lock_irqsave(&queue->ctrl_status_q_lock, flags);
- BUG_ON(list_empty(&queue->ctrl_status_q));
- qcmd = list_first_entry(&queue->ctrl_status_q,
- struct msm_queue_cmd, list);
- list_del_init(&qcmd->list);
- spin_unlock_irqrestore(&queue->ctrl_status_q_lock, flags);
-
- return qcmd;
-}
-
-static int msm_control(struct msm_control_device *ctrl_pmsm,
- int block,
- void __user *arg)
-{
- int rc = 0;
-
- struct msm_sync *sync = ctrl_pmsm->pmsm->sync;
- struct msm_ctrl_cmd udata, *ctrlcmd;
- struct msm_queue_cmd *qcmd = NULL, *qcmd_temp;
-
- if (copy_from_user(&udata, arg, sizeof(struct msm_ctrl_cmd))) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- goto end;
- }
-
- qcmd = kmalloc(sizeof(struct msm_queue_cmd) +
- sizeof(struct msm_ctrl_cmd) + udata.length,
- GFP_KERNEL);
- if (!qcmd) {
- pr_err("msm_control: cannot allocate buffer\n");
- rc = -ENOMEM;
- goto end;
- }
-
- qcmd->type = MSM_CAM_Q_CTRL;
- qcmd->command = ctrlcmd = (struct msm_ctrl_cmd *)(qcmd + 1);
- *ctrlcmd = udata;
- ctrlcmd->value = ctrlcmd + 1;
-
- if (udata.length) {
- if (copy_from_user(ctrlcmd->value,
- udata.value, udata.length)) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- goto end;
- }
- }
-
- if (!block) {
- /* qcmd will be set to NULL */
- qcmd = __msm_control(sync, NULL, qcmd, 0);
- goto end;
- }
-
- qcmd_temp = __msm_control(sync,
- &ctrl_pmsm->ctrl_q,
- qcmd, MAX_SCHEDULE_TIMEOUT);
-
- if (IS_ERR(qcmd_temp)) {
- rc = PTR_ERR(qcmd_temp);
- goto end;
- }
- qcmd = qcmd_temp;
-
- if (qcmd->command) {
- void __user *to = udata.value;
- udata = *(struct msm_ctrl_cmd *)qcmd->command;
- if (udata.length > 0) {
- if (copy_to_user(to,
- udata.value,
- udata.length)) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- goto end;
- }
- }
- udata.value = to;
-
- if (copy_to_user((void *)arg, &udata,
- sizeof(struct msm_ctrl_cmd))) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- goto end;
- }
- }
-
-end:
- /* Note: if we get here as a result of an error, we will free the
- * qcmd that we kmalloc() in this function. When we come here as
- * a result of a successful completion, we are freeing the qcmd that
- * we dequeued from queue->ctrl_status_q.
- */
- kfree(qcmd);
-
- CDBG("msm_control: end rc = %d\n", rc);
- return rc;
-}
-
-static int msm_get_stats(struct msm_sync *sync, void __user *arg)
-{
- unsigned long flags;
- int timeout;
- int rc = 0;
-
- struct msm_stats_event_ctrl se;
-
- struct msm_queue_cmd *qcmd = NULL;
- struct msm_ctrl_cmd *ctrl = NULL;
- struct msm_vfe_resp *data = NULL;
- struct msm_stats_buf stats;
-
- if (copy_from_user(&se, arg,
- sizeof(struct msm_stats_event_ctrl))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- timeout = (int)se.timeout_ms;
-
- CDBG("msm_get_stats timeout %d\n", timeout);
- rc = wait_event_interruptible_timeout(
- sync->msg_event_wait,
- !list_empty_careful(&sync->msg_event_q),
- msecs_to_jiffies(timeout));
- if (list_empty_careful(&sync->msg_event_q)) {
- if (rc == 0)
- rc = -ETIMEDOUT;
- if (rc < 0) {
- pr_err("msm_get_stats error %d\n", rc);
- return rc;
- }
- }
- CDBG("msm_get_stats returned from wait: %d\n", rc);
-
- spin_lock_irqsave(&sync->msg_event_q_lock, flags);
- BUG_ON(list_empty(&sync->msg_event_q));
- qcmd = list_first_entry(&sync->msg_event_q,
- struct msm_queue_cmd, list);
- list_del_init(&qcmd->list);
- spin_unlock_irqrestore(&sync->msg_event_q_lock, flags);
-
- CDBG("=== received from DSP === %d\n", qcmd->type);
-
- switch (qcmd->type) {
- case MSM_CAM_Q_VFE_EVT:
- case MSM_CAM_Q_VFE_MSG:
- data = (struct msm_vfe_resp *)(qcmd->command);
-
- /* adsp event and message */
- se.resptype = MSM_CAM_RESP_STAT_EVT_MSG;
-
- /* 0 - msg from aDSP, 1 - event from mARM */
- se.stats_event.type = data->evt_msg.type;
- se.stats_event.msg_id = data->evt_msg.msg_id;
- se.stats_event.len = data->evt_msg.len;
-
- CDBG("msm_get_stats, qcmd->type = %d\n", qcmd->type);
- CDBG("length = %d\n", se.stats_event.len);
- CDBG("msg_id = %d\n", se.stats_event.msg_id);
-
- if ((data->type == VFE_MSG_STATS_AF) ||
- (data->type == VFE_MSG_STATS_WE)) {
-
- stats.buffer =
- msm_pmem_stats_ptov_lookup(sync,
- data->phy.sbuf_phy,
- &(stats.fd));
- if (!stats.buffer) {
- pr_err("%s: msm_pmem_stats_ptov_lookup error\n",
- __func__);
- rc = -EINVAL;
- goto failure;
- }
-
- if (copy_to_user((void *)(se.stats_event.data),
- &stats,
- sizeof(struct msm_stats_buf))) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- goto failure;
- }
- } else if ((data->evt_msg.len > 0) &&
- (data->type == VFE_MSG_GENERAL)) {
- if (copy_to_user((void *)(se.stats_event.data),
- data->evt_msg.data,
- data->evt_msg.len)) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- }
- } else if (data->type == VFE_MSG_OUTPUT1 ||
- data->type == VFE_MSG_OUTPUT2) {
- if (copy_to_user((void *)(se.stats_event.data),
- data->extdata,
- data->extlen)) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- }
- } else if (data->type == VFE_MSG_SNAPSHOT && sync->pict_pp) {
- struct msm_postproc buf;
- struct msm_pmem_region region;
- buf.fmnum = msm_pmem_region_lookup(&sync->frame,
- MSM_PMEM_MAINIMG,
- ®ion, 1);
- if (buf.fmnum == 1) {
- buf.fmain.buffer = (unsigned long)region.vaddr;
- buf.fmain.y_off = region.y_off;
- buf.fmain.cbcr_off = region.cbcr_off;
- buf.fmain.fd = region.fd;
- } else {
- buf.fmnum = msm_pmem_region_lookup(&sync->frame,
- MSM_PMEM_RAW_MAINIMG,
- ®ion, 1);
- if (buf.fmnum == 1) {
- buf.fmain.path = MSM_FRAME_PREV_2;
- buf.fmain.buffer =
- (unsigned long)region.vaddr;
- buf.fmain.fd = region.fd;
- } else {
- pr_err("%s: pmem lookup failed\n",
- __func__);
- rc = -EINVAL;
- }
- }
-
- if (copy_to_user((void *)(se.stats_event.data), &buf,
- sizeof(buf))) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- goto failure;
- }
- CDBG("snapshot copy_to_user!\n");
- }
- break;
-
- case MSM_CAM_Q_CTRL:
- /* control command from control thread */
- ctrl = (struct msm_ctrl_cmd *)(qcmd->command);
-
- CDBG("msm_get_stats, qcmd->type = %d\n", qcmd->type);
- CDBG("length = %d\n", ctrl->length);
-
- if (ctrl->length > 0) {
- if (copy_to_user((void *)(se.ctrl_cmd.value),
- ctrl->value,
- ctrl->length)) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- goto failure;
- }
- }
-
- se.resptype = MSM_CAM_RESP_CTRL;
-
- /* what to control */
- se.ctrl_cmd.type = ctrl->type;
- se.ctrl_cmd.length = ctrl->length;
- se.ctrl_cmd.resp_fd = ctrl->resp_fd;
- break;
-
- case MSM_CAM_Q_V4L2_REQ:
- /* control command from v4l2 client */
- ctrl = (struct msm_ctrl_cmd *)(qcmd->command);
-
- CDBG("msm_get_stats, qcmd->type = %d\n", qcmd->type);
- CDBG("length = %d\n", ctrl->length);
-
- if (ctrl->length > 0) {
- if (copy_to_user((void *)(se.ctrl_cmd.value),
- ctrl->value, ctrl->length)) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- goto failure;
- }
- }
-
- /* 2 tells config thread this is v4l2 request */
- se.resptype = MSM_CAM_RESP_V4L2;
-
- /* what to control */
- se.ctrl_cmd.type = ctrl->type;
- se.ctrl_cmd.length = ctrl->length;
- break;
-
- default:
- rc = -EFAULT;
- goto failure;
- } /* switch qcmd->type */
-
- if (copy_to_user((void *)arg, &se, sizeof(se))) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- }
-
-failure:
- kfree(qcmd);
-
- CDBG("msm_get_stats: %d\n", rc);
- return rc;
-}
-
-static int msm_ctrl_cmd_done(struct msm_control_device *ctrl_pmsm,
- void __user *arg)
-{
- unsigned long flags;
- int rc = 0;
-
- struct msm_ctrl_cmd udata, *ctrlcmd;
- struct msm_queue_cmd *qcmd = NULL;
-
- if (copy_from_user(&udata, arg, sizeof(struct msm_ctrl_cmd))) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- goto end;
- }
-
- qcmd = kmalloc(sizeof(struct msm_queue_cmd) +
- sizeof(struct msm_ctrl_cmd) + udata.length,
- GFP_KERNEL);
- if (!qcmd) {
- rc = -ENOMEM;
- goto end;
- }
-
- qcmd->command = ctrlcmd = (struct msm_ctrl_cmd *)(qcmd + 1);
- *ctrlcmd = udata;
- if (udata.length > 0) {
- ctrlcmd->value = ctrlcmd + 1;
- if (copy_from_user(ctrlcmd->value,
- (void *)udata.value,
- udata.length)) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- kfree(qcmd);
- goto end;
- }
- } else
- ctrlcmd->value = NULL;
-
-end:
- CDBG("msm_ctrl_cmd_done: end rc = %d\n", rc);
- if (rc == 0) {
- /* wake up control thread */
- spin_lock_irqsave(&ctrl_pmsm->ctrl_q.ctrl_status_q_lock, flags);
- list_add_tail(&qcmd->list, &ctrl_pmsm->ctrl_q.ctrl_status_q);
- wake_up(&ctrl_pmsm->ctrl_q.ctrl_status_wait);
- spin_unlock_irqrestore(&ctrl_pmsm->ctrl_q.ctrl_status_q_lock, flags);
- }
-
- return rc;
-}
-
-static int msm_config_vfe(struct msm_sync *sync, void __user *arg)
-{
- struct msm_vfe_cfg_cmd cfgcmd;
- struct msm_pmem_region region[8];
- struct axidata axi_data;
- void *data = NULL;
- int rc = -EIO;
-
- memset(&axi_data, 0, sizeof(axi_data));
-
- if (copy_from_user(&cfgcmd, arg, sizeof(cfgcmd))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- switch (cfgcmd.cmd_type) {
- case CMD_STATS_ENABLE:
- axi_data.bufnum1 =
- msm_pmem_region_lookup(&sync->stats,
- MSM_PMEM_AEC_AWB, ®ion[0],
- NUM_WB_EXP_STAT_OUTPUT_BUFFERS);
- if (!axi_data.bufnum1) {
- pr_err("%s: pmem region lookup error\n", __func__);
- return -EINVAL;
- }
- axi_data.region = ®ion[0];
- data = &axi_data;
- break;
- case CMD_STATS_AF_ENABLE:
- axi_data.bufnum1 =
- msm_pmem_region_lookup(&sync->stats,
- MSM_PMEM_AF, ®ion[0],
- NUM_AF_STAT_OUTPUT_BUFFERS);
- if (!axi_data.bufnum1) {
- pr_err("%s: pmem region lookup error\n", __func__);
- return -EINVAL;
- }
- axi_data.region = ®ion[0];
- data = &axi_data;
- break;
- case CMD_GENERAL:
- case CMD_STATS_DISABLE:
- break;
- default:
- pr_err("%s: unknown command type %d\n",
- __func__, cfgcmd.cmd_type);
- return -EINVAL;
- }
-
-
- if (sync->vfefn.vfe_config)
- rc = sync->vfefn.vfe_config(&cfgcmd, data);
-
- return rc;
-}
-
-static int msm_frame_axi_cfg(struct msm_sync *sync,
- struct msm_vfe_cfg_cmd *cfgcmd)
-{
- int rc = -EIO;
- struct axidata axi_data;
- void *data = &axi_data;
- struct msm_pmem_region region[8];
- int pmem_type;
-
- memset(&axi_data, 0, sizeof(axi_data));
-
- switch (cfgcmd->cmd_type) {
- case CMD_AXI_CFG_OUT1:
- pmem_type = MSM_PMEM_OUTPUT1;
- axi_data.bufnum1 =
- msm_pmem_region_lookup(&sync->frame, pmem_type,
- ®ion[0], 8);
- if (!axi_data.bufnum1) {
- pr_err("%s: pmem region lookup error\n", __func__);
- return -EINVAL;
- }
- break;
-
- case CMD_AXI_CFG_OUT2:
- pmem_type = MSM_PMEM_OUTPUT2;
- axi_data.bufnum2 =
- msm_pmem_region_lookup(&sync->frame, pmem_type,
- ®ion[0], 8);
- if (!axi_data.bufnum2) {
- pr_err("%s: pmem region lookup error\n", __func__);
- return -EINVAL;
- }
- break;
-
- case CMD_AXI_CFG_SNAP_O1_AND_O2:
- pmem_type = MSM_PMEM_THUMBAIL;
- axi_data.bufnum1 =
- msm_pmem_region_lookup(&sync->frame, pmem_type,
- ®ion[0], 8);
- if (!axi_data.bufnum1) {
- pr_err("%s: pmem region lookup error\n", __func__);
- return -EINVAL;
- }
-
- pmem_type = MSM_PMEM_MAINIMG;
- axi_data.bufnum2 =
- msm_pmem_region_lookup(&sync->frame, pmem_type,
- ®ion[axi_data.bufnum1], 8);
- if (!axi_data.bufnum2) {
- pr_err("%s: pmem region lookup error\n", __func__);
- return -EINVAL;
- }
- break;
-
- case CMD_RAW_PICT_AXI_CFG:
- pmem_type = MSM_PMEM_RAW_MAINIMG;
- axi_data.bufnum2 =
- msm_pmem_region_lookup(&sync->frame, pmem_type,
- ®ion[0], 8);
- if (!axi_data.bufnum2) {
- pr_err("%s: pmem region lookup error\n", __func__);
- return -EINVAL;
- }
- break;
-
- case CMD_GENERAL:
- data = NULL;
- break;
-
- default:
- pr_err("%s: unknown command type %d\n",
- __func__, cfgcmd->cmd_type);
- return -EINVAL;
- }
-
- axi_data.region = ®ion[0];
-
- /* send the AXI configuration command to driver */
- if (sync->vfefn.vfe_config)
- rc = sync->vfefn.vfe_config(cfgcmd, data);
-
- return rc;
-}
-
-static int msm_get_sensor_info(struct msm_sync *sync, void __user *arg)
-{
- int rc = 0;
- struct msm_camsensor_info info;
- struct msm_camera_sensor_info *sdata;
-
- if (copy_from_user(&info,
- arg,
- sizeof(struct msm_camsensor_info))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- sdata = sync->pdev->dev.platform_data;
- CDBG("sensor_name %s\n", sdata->sensor_name);
-
- memcpy(&info.name[0],
- sdata->sensor_name,
- MAX_SENSOR_NAME);
- info.flash_enabled = sdata->flash_type != MSM_CAMERA_FLASH_NONE;
-
- /* copy back to user space */
- if (copy_to_user((void *)arg,
- &info,
- sizeof(struct msm_camsensor_info))) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- }
-
- return rc;
-}
-
-static int __msm_put_frame_buf(struct msm_sync *sync,
- struct msm_frame *pb)
-{
- unsigned long pphy;
- struct msm_vfe_cfg_cmd cfgcmd;
-
- int rc = -EIO;
-
- pphy = msm_pmem_frame_vtop_lookup(sync,
- pb->buffer,
- pb->y_off, pb->cbcr_off, pb->fd);
-
- if (pphy != 0) {
- CDBG("rel: vaddr = 0x%lx, paddr = 0x%lx\n",
- pb->buffer, pphy);
- cfgcmd.cmd_type = CMD_FRAME_BUF_RELEASE;
- cfgcmd.value = (void *)pb;
- if (sync->vfefn.vfe_config)
- rc = sync->vfefn.vfe_config(&cfgcmd, &pphy);
- } else {
- pr_err("%s: msm_pmem_frame_vtop_lookup failed\n",
- __func__);
- rc = -EINVAL;
- }
-
- return rc;
-}
-
-static int msm_put_frame_buffer(struct msm_sync *sync, void __user *arg)
-{
- struct msm_frame buf_t;
-
- if (copy_from_user(&buf_t,
- arg,
- sizeof(struct msm_frame))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- return __msm_put_frame_buf(sync, &buf_t);
-}
-
-static int __msm_register_pmem(struct msm_sync *sync,
- struct msm_pmem_info *pinfo)
-{
- int rc = 0;
-
- switch (pinfo->type) {
- case MSM_PMEM_OUTPUT1:
- case MSM_PMEM_OUTPUT2:
- case MSM_PMEM_THUMBAIL:
- case MSM_PMEM_MAINIMG:
- case MSM_PMEM_RAW_MAINIMG:
- rc = msm_pmem_table_add(&sync->frame, pinfo);
- break;
-
- case MSM_PMEM_AEC_AWB:
- case MSM_PMEM_AF:
- rc = msm_pmem_table_add(&sync->stats, pinfo);
- break;
-
- default:
- rc = -EINVAL;
- break;
- }
-
- return rc;
-}
-
-static int msm_register_pmem(struct msm_sync *sync, void __user *arg)
-{
- struct msm_pmem_info info;
-
- if (copy_from_user(&info, arg, sizeof(info))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- return __msm_register_pmem(sync, &info);
-}
-
-static int msm_stats_axi_cfg(struct msm_sync *sync,
- struct msm_vfe_cfg_cmd *cfgcmd)
-{
- int rc = -EIO;
- struct axidata axi_data;
- void *data = &axi_data;
-
- struct msm_pmem_region region[3];
- int pmem_type = MSM_PMEM_MAX;
-
- memset(&axi_data, 0, sizeof(axi_data));
-
- switch (cfgcmd->cmd_type) {
- case CMD_STATS_AXI_CFG:
- pmem_type = MSM_PMEM_AEC_AWB;
- break;
- case CMD_STATS_AF_AXI_CFG:
- pmem_type = MSM_PMEM_AF;
- break;
- case CMD_GENERAL:
- data = NULL;
- break;
- default:
- pr_err("%s: unknown command type %d\n",
- __func__, cfgcmd->cmd_type);
- return -EINVAL;
- }
-
- if (cfgcmd->cmd_type != CMD_GENERAL) {
- axi_data.bufnum1 =
- msm_pmem_region_lookup(&sync->stats, pmem_type,
- ®ion[0], NUM_WB_EXP_STAT_OUTPUT_BUFFERS);
- if (!axi_data.bufnum1) {
- pr_err("%s: pmem region lookup error\n", __func__);
- return -EINVAL;
- }
- axi_data.region = ®ion[0];
- }
-
- /* send the AEC/AWB STATS configuration command to driver */
- if (sync->vfefn.vfe_config)
- rc = sync->vfefn.vfe_config(cfgcmd, &axi_data);
-
- return rc;
-}
-
-static int msm_put_stats_buffer(struct msm_sync *sync, void __user *arg)
-{
- int rc = -EIO;
-
- struct msm_stats_buf buf;
- unsigned long pphy;
- struct msm_vfe_cfg_cmd cfgcmd;
-
- if (copy_from_user(&buf, arg,
- sizeof(struct msm_stats_buf))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- CDBG("msm_put_stats_buffer\n");
- pphy = msm_pmem_stats_vtop_lookup(sync, buf.buffer, buf.fd);
-
- if (pphy != 0) {
- if (buf.type == STAT_AEAW)
- cfgcmd.cmd_type = CMD_STATS_BUF_RELEASE;
- else if (buf.type == STAT_AF)
- cfgcmd.cmd_type = CMD_STATS_AF_BUF_RELEASE;
- else {
- pr_err("%s: invalid buf type %d\n",
- __func__,
- buf.type);
- rc = -EINVAL;
- goto put_done;
- }
-
- cfgcmd.value = (void *)&buf;
-
- if (sync->vfefn.vfe_config) {
- rc = sync->vfefn.vfe_config(&cfgcmd, &pphy);
- if (rc < 0)
- pr_err("msm_put_stats_buffer: "\
- "vfe_config err %d\n", rc);
- } else
- pr_err("msm_put_stats_buffer: vfe_config is NULL\n");
- } else {
- pr_err("msm_put_stats_buffer: NULL physical address\n");
- rc = -EINVAL;
- }
-
-put_done:
- return rc;
-}
-
-static int msm_axi_config(struct msm_sync *sync, void __user *arg)
-{
- struct msm_vfe_cfg_cmd cfgcmd;
-
- if (copy_from_user(&cfgcmd, arg, sizeof(cfgcmd))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- switch (cfgcmd.cmd_type) {
- case CMD_AXI_CFG_OUT1:
- case CMD_AXI_CFG_OUT2:
- case CMD_AXI_CFG_SNAP_O1_AND_O2:
- case CMD_RAW_PICT_AXI_CFG:
- return msm_frame_axi_cfg(sync, &cfgcmd);
-
- case CMD_STATS_AXI_CFG:
- case CMD_STATS_AF_AXI_CFG:
- return msm_stats_axi_cfg(sync, &cfgcmd);
-
- default:
- pr_err("%s: unknown command type %d\n",
- __func__,
- cfgcmd.cmd_type);
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int __msm_get_pic(struct msm_sync *sync, struct msm_ctrl_cmd *ctrl)
-{
- unsigned long flags;
- int rc = 0;
- int tm;
-
- struct msm_queue_cmd *qcmd = NULL;
-
- tm = (int)ctrl->timeout_ms;
-
- rc = wait_event_interruptible_timeout(
- sync->pict_frame_wait,
- !list_empty_careful(&sync->pict_frame_q),
- msecs_to_jiffies(tm));
- if (list_empty_careful(&sync->pict_frame_q)) {
- if (rc == 0)
- return -ETIMEDOUT;
- if (rc < 0) {
- pr_err("msm_camera_get_picture, rc = %d\n", rc);
- return rc;
- }
- }
-
- spin_lock_irqsave(&sync->pict_frame_q_lock, flags);
- BUG_ON(list_empty(&sync->pict_frame_q));
- qcmd = list_first_entry(&sync->pict_frame_q,
- struct msm_queue_cmd, list);
- list_del_init(&qcmd->list);
- spin_unlock_irqrestore(&sync->pict_frame_q_lock, flags);
-
- if (qcmd->command != NULL) {
- struct msm_ctrl_cmd *q =
- (struct msm_ctrl_cmd *)qcmd->command;
- ctrl->type = q->type;
- ctrl->status = q->status;
- } else {
- ctrl->type = -1;
- ctrl->status = -1;
- }
-
- kfree(qcmd);
- return rc;
-}
-
-static int msm_get_pic(struct msm_sync *sync, void __user *arg)
-{
- struct msm_ctrl_cmd ctrlcmd_t;
- int rc;
-
- if (copy_from_user(&ctrlcmd_t,
- arg,
- sizeof(struct msm_ctrl_cmd))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- rc = __msm_get_pic(sync, &ctrlcmd_t);
- if (rc < 0)
- return rc;
-
- if (sync->croplen) {
- if (ctrlcmd_t.length < sync->croplen) {
- pr_err("msm_get_pic: invalid len %d\n",
- ctrlcmd_t.length);
- return -EINVAL;
- }
- if (copy_to_user(ctrlcmd_t.value,
- sync->cropinfo,
- sync->croplen)) {
- ERR_COPY_TO_USER();
- return -EFAULT;
- }
- }
-
- if (copy_to_user((void *)arg,
- &ctrlcmd_t,
- sizeof(struct msm_ctrl_cmd))) {
- ERR_COPY_TO_USER();
- return -EFAULT;
- }
- return 0;
-}
-
-static int msm_set_crop(struct msm_sync *sync, void __user *arg)
-{
- struct crop_info crop;
-
- if (copy_from_user(&crop,
- arg,
- sizeof(struct crop_info))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- if (!sync->croplen) {
- sync->cropinfo = kmalloc(crop.len, GFP_KERNEL);
- if (!sync->cropinfo)
- return -ENOMEM;
- } else if (sync->croplen < crop.len)
- return -EINVAL;
-
- if (copy_from_user(sync->cropinfo,
- crop.info,
- crop.len)) {
- ERR_COPY_FROM_USER();
- kfree(sync->cropinfo);
- return -EFAULT;
- }
-
- sync->croplen = crop.len;
-
- return 0;
-}
-
-static int msm_pict_pp_done(struct msm_sync *sync, void __user *arg)
-{
- struct msm_ctrl_cmd udata;
- struct msm_ctrl_cmd *ctrlcmd = NULL;
- struct msm_queue_cmd *qcmd = NULL;
- unsigned long flags;
- int rc = 0;
-
- if (!sync->pict_pp)
- return -EINVAL;
-
- if (copy_from_user(&udata, arg, sizeof(struct msm_ctrl_cmd))) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- goto pp_fail;
- }
-
- qcmd = kmalloc(sizeof(struct msm_queue_cmd) +
- sizeof(struct msm_ctrl_cmd),
- GFP_KERNEL);
- if (!qcmd) {
- rc = -ENOMEM;
- goto pp_fail;
- }
-
- qcmd->type = MSM_CAM_Q_VFE_MSG;
- qcmd->command = ctrlcmd = (struct msm_ctrl_cmd *)(qcmd + 1);
- memset(ctrlcmd, 0, sizeof(struct msm_ctrl_cmd));
- ctrlcmd->type = udata.type;
- ctrlcmd->status = udata.status;
-
- spin_lock_irqsave(&sync->pict_frame_q_lock, flags);
- list_add_tail(&qcmd->list, &sync->pict_frame_q);
- spin_unlock_irqrestore(&sync->pict_frame_q_lock, flags);
- wake_up(&sync->pict_frame_wait);
-
-pp_fail:
- return rc;
-}
-
-static long msm_ioctl_common(struct msm_device *pmsm,
- unsigned int cmd,
- void __user *argp)
-{
- CDBG("msm_ioctl_common\n");
- switch (cmd) {
- case MSM_CAM_IOCTL_REGISTER_PMEM:
- return msm_register_pmem(pmsm->sync, argp);
- case MSM_CAM_IOCTL_UNREGISTER_PMEM:
- return msm_pmem_table_del(pmsm->sync, argp);
- default:
- return -EINVAL;
- }
-}
-
-static long msm_ioctl_config(struct file *filep, unsigned int cmd,
- unsigned long arg)
-{
- int rc = -EINVAL;
- void __user *argp = (void __user *)arg;
- struct msm_device *pmsm = filep->private_data;
-
- CDBG("msm_ioctl_config cmd = %d\n", _IOC_NR(cmd));
-
- switch (cmd) {
- case MSM_CAM_IOCTL_GET_SENSOR_INFO:
- rc = msm_get_sensor_info(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_CONFIG_VFE:
- /* Coming from config thread for update */
- rc = msm_config_vfe(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_GET_STATS:
- /* Coming from config thread wait
- * for vfe statistics and control requests */
- rc = msm_get_stats(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_ENABLE_VFE:
- /* This request comes from control thread:
- * enable either QCAMTASK or VFETASK */
- rc = msm_enable_vfe(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_DISABLE_VFE:
- /* This request comes from control thread:
- * disable either QCAMTASK or VFETASK */
- rc = msm_disable_vfe(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_VFE_APPS_RESET:
- msm_camio_vfe_blk_reset();
- rc = 0;
- break;
-
- case MSM_CAM_IOCTL_RELEASE_STATS_BUFFER:
- rc = msm_put_stats_buffer(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_AXI_CONFIG:
- rc = msm_axi_config(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_SET_CROP:
- rc = msm_set_crop(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_PICT_PP: {
- uint8_t enable;
- if (copy_from_user(&enable, argp, sizeof(enable))) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- } else {
- pmsm->sync->pict_pp = enable;
- rc = 0;
- }
- break;
- }
-
- case MSM_CAM_IOCTL_PICT_PP_DONE:
- rc = msm_pict_pp_done(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_SENSOR_IO_CFG:
- rc = pmsm->sync->sctrl.s_config(argp);
- break;
-
- case MSM_CAM_IOCTL_FLASH_LED_CFG: {
- uint32_t led_state;
- if (copy_from_user(&led_state, argp, sizeof(led_state))) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- } else
- rc = msm_camera_flash_set_led_state(led_state);
- break;
- }
-
- default:
- rc = msm_ioctl_common(pmsm, cmd, argp);
- break;
- }
-
- CDBG("msm_ioctl_config cmd = %d DONE\n", _IOC_NR(cmd));
- return rc;
-}
-
-static int msm_unblock_poll_frame(struct msm_sync *);
-
-static long msm_ioctl_frame(struct file *filep, unsigned int cmd,
- unsigned long arg)
-{
- int rc = -EINVAL;
- void __user *argp = (void __user *)arg;
- struct msm_device *pmsm = filep->private_data;
-
-
- switch (cmd) {
- case MSM_CAM_IOCTL_GETFRAME:
- /* Coming from frame thread to get frame
- * after SELECT is done */
- rc = msm_get_frame(pmsm->sync, argp);
- break;
- case MSM_CAM_IOCTL_RELEASE_FRAME_BUFFER:
- rc = msm_put_frame_buffer(pmsm->sync, argp);
- break;
- case MSM_CAM_IOCTL_UNBLOCK_POLL_FRAME:
- rc = msm_unblock_poll_frame(pmsm->sync);
- break;
- default:
- break;
- }
-
- return rc;
-}
-
-
-static long msm_ioctl_control(struct file *filep, unsigned int cmd,
- unsigned long arg)
-{
- int rc = -EINVAL;
- void __user *argp = (void __user *)arg;
- struct msm_control_device *ctrl_pmsm = filep->private_data;
- struct msm_device *pmsm = ctrl_pmsm->pmsm;
-
- switch (cmd) {
- case MSM_CAM_IOCTL_CTRL_COMMAND:
- /* Coming from control thread, may need to wait for
- * command status */
- rc = msm_control(ctrl_pmsm, 1, argp);
- break;
- case MSM_CAM_IOCTL_CTRL_COMMAND_2:
- /* Sends a message, returns immediately */
- rc = msm_control(ctrl_pmsm, 0, argp);
- break;
- case MSM_CAM_IOCTL_CTRL_CMD_DONE:
- /* Config thread calls the control thread to notify it
- * of the result of a MSM_CAM_IOCTL_CTRL_COMMAND.
- */
- rc = msm_ctrl_cmd_done(ctrl_pmsm, argp);
- break;
- case MSM_CAM_IOCTL_GET_PICTURE:
- rc = msm_get_pic(pmsm->sync, argp);
- break;
- default:
- rc = msm_ioctl_common(pmsm, cmd, argp);
- break;
- }
-
- return rc;
-}
-
-static int __msm_release(struct msm_sync *sync)
-{
- struct msm_pmem_region *region;
- struct hlist_node *hnode;
- struct hlist_node *n;
-
- mutex_lock(&sync->lock);
- if (sync->opencnt)
- sync->opencnt--;
-
- if (!sync->opencnt) {
- /* need to clean up system resource */
- if (sync->vfefn.vfe_release)
- sync->vfefn.vfe_release(sync->pdev);
-
- if (sync->cropinfo) {
- kfree(sync->cropinfo);
- sync->cropinfo = NULL;
- sync->croplen = 0;
- }
-
- hlist_for_each_entry_safe(region, hnode, n,
- &sync->frame, list) {
- hlist_del(hnode);
- put_pmem_file(region->file);
- kfree(region);
- }
-
- hlist_for_each_entry_safe(region, hnode, n,
- &sync->stats, list) {
- hlist_del(hnode);
- put_pmem_file(region->file);
- kfree(region);
- }
-
- MSM_DRAIN_QUEUE(sync, msg_event_q);
- MSM_DRAIN_QUEUE(sync, prev_frame_q);
- MSM_DRAIN_QUEUE(sync, pict_frame_q);
-
- sync->sctrl.s_release();
-
- sync->apps_id = NULL;
- CDBG("msm_release completed!\n");
- }
- mutex_unlock(&sync->lock);
-
- return 0;
-}
-
-static int msm_release_config(struct inode *node, struct file *filep)
-{
- int rc;
- struct msm_device *pmsm = filep->private_data;
- printk("msm_camera: RELEASE %s\n", filep->f_path.dentry->d_name.name);
- rc = __msm_release(pmsm->sync);
- atomic_set(&pmsm->opened, 0);
- return rc;
-}
-
-static int msm_release_control(struct inode *node, struct file *filep)
-{
- int rc;
- struct msm_control_device *ctrl_pmsm = filep->private_data;
- struct msm_device *pmsm = ctrl_pmsm->pmsm;
- printk(KERN_INFO "msm_camera: RELEASE %s\n",
- filep->f_path.dentry->d_name.name);
- rc = __msm_release(pmsm->sync);
- if (!rc) {
- MSM_DRAIN_QUEUE(&ctrl_pmsm->ctrl_q, ctrl_status_q);
- MSM_DRAIN_QUEUE(pmsm->sync, pict_frame_q);
- }
- kfree(ctrl_pmsm);
- return rc;
-}
-
-static int msm_release_frame(struct inode *node, struct file *filep)
-{
- int rc;
- struct msm_device *pmsm = filep->private_data;
- printk(KERN_INFO "msm_camera: RELEASE %s\n",
- filep->f_path.dentry->d_name.name);
- rc = __msm_release(pmsm->sync);
- if (!rc) {
- MSM_DRAIN_QUEUE(pmsm->sync, prev_frame_q);
- atomic_set(&pmsm->opened, 0);
- }
- return rc;
-}
-
-static int msm_unblock_poll_frame(struct msm_sync *sync)
-{
- unsigned long flags;
- CDBG("msm_unblock_poll_frame\n");
- spin_lock_irqsave(&sync->prev_frame_q_lock, flags);
- sync->unblock_poll_frame = 1;
- wake_up(&sync->prev_frame_wait);
- spin_unlock_irqrestore(&sync->prev_frame_q_lock, flags);
- return 0;
-}
-
-static unsigned int __msm_poll_frame(struct msm_sync *sync,
- struct file *filep,
- struct poll_table_struct *pll_table)
-{
- int rc = 0;
- unsigned long flags;
-
- poll_wait(filep, &sync->prev_frame_wait, pll_table);
-
- spin_lock_irqsave(&sync->prev_frame_q_lock, flags);
- if (!list_empty_careful(&sync->prev_frame_q))
- /* frame ready */
- rc = POLLIN | POLLRDNORM;
- if (sync->unblock_poll_frame) {
- CDBG("%s: sync->unblock_poll_frame is true\n", __func__);
- rc |= POLLPRI;
- sync->unblock_poll_frame = 0;
- }
- spin_unlock_irqrestore(&sync->prev_frame_q_lock, flags);
-
- return rc;
-}
-
-static unsigned int msm_poll_frame(struct file *filep,
- struct poll_table_struct *pll_table)
-{
- struct msm_device *pmsm = filep->private_data;
- return __msm_poll_frame(pmsm->sync, filep, pll_table);
-}
-
-/*
- * This function executes in interrupt context.
- */
-
-static void *msm_vfe_sync_alloc(int size,
- void *syncdata __attribute__((unused)))
-{
- struct msm_queue_cmd *qcmd =
- kmalloc(sizeof(struct msm_queue_cmd) + size, GFP_ATOMIC);
- return qcmd ? qcmd + 1 : NULL;
-}
-
-/*
- * This function executes in interrupt context.
- */
-
-static void msm_vfe_sync(struct msm_vfe_resp *vdata,
- enum msm_queue qtype, void *syncdata)
-{
- struct msm_queue_cmd *qcmd = NULL;
- struct msm_queue_cmd *qcmd_frame = NULL;
- struct msm_vfe_phy_info *fphy;
-
- unsigned long flags;
- struct msm_sync *sync = (struct msm_sync *)syncdata;
- if (!sync) {
- pr_err("msm_camera: no context in dsp callback.\n");
- return;
- }
-
- qcmd = ((struct msm_queue_cmd *)vdata) - 1;
- qcmd->type = qtype;
-
- if (qtype == MSM_CAM_Q_VFE_MSG) {
- switch (vdata->type) {
- case VFE_MSG_OUTPUT1:
- case VFE_MSG_OUTPUT2:
- qcmd_frame =
- kmalloc(sizeof(struct msm_queue_cmd) +
- sizeof(struct msm_vfe_phy_info),
- GFP_ATOMIC);
- if (!qcmd_frame)
- goto mem_fail;
- fphy = (struct msm_vfe_phy_info *)(qcmd_frame + 1);
- *fphy = vdata->phy;
-
- qcmd_frame->type = MSM_CAM_Q_VFE_MSG;
- qcmd_frame->command = fphy;
-
- CDBG("qcmd_frame= 0x%x phy_y= 0x%x, phy_cbcr= 0x%x\n",
- (int) qcmd_frame, fphy->y_phy, fphy->cbcr_phy);
-
- spin_lock_irqsave(&sync->prev_frame_q_lock, flags);
- list_add_tail(&qcmd_frame->list, &sync->prev_frame_q);
- wake_up(&sync->prev_frame_wait);
- spin_unlock_irqrestore(&sync->prev_frame_q_lock, flags);
- CDBG("woke up frame thread\n");
- break;
- case VFE_MSG_SNAPSHOT:
- if (sync->pict_pp)
- break;
-
- CDBG("snapshot pp = %d\n", sync->pict_pp);
- qcmd_frame =
- kmalloc(sizeof(struct msm_queue_cmd),
- GFP_ATOMIC);
- if (!qcmd_frame)
- goto mem_fail;
- qcmd_frame->type = MSM_CAM_Q_VFE_MSG;
- qcmd_frame->command = NULL;
- spin_lock_irqsave(&sync->pict_frame_q_lock,
- flags);
- list_add_tail(&qcmd_frame->list, &sync->pict_frame_q);
- wake_up(&sync->pict_frame_wait);
- spin_unlock_irqrestore(&sync->pict_frame_q_lock, flags);
- CDBG("woke up picture thread\n");
- break;
- default:
- CDBG("%s: qtype = %d not handled\n",
- __func__, vdata->type);
- break;
- }
- }
-
- qcmd->command = (void *)vdata;
- CDBG("vdata->type = %d\n", vdata->type);
-
- spin_lock_irqsave(&sync->msg_event_q_lock, flags);
- list_add_tail(&qcmd->list, &sync->msg_event_q);
- wake_up(&sync->msg_event_wait);
- spin_unlock_irqrestore(&sync->msg_event_q_lock, flags);
- CDBG("woke up config thread\n");
- return;
-
-mem_fail:
- kfree(qcmd);
-}
-
-static struct msm_vfe_callback msm_vfe_s = {
- .vfe_resp = msm_vfe_sync,
- .vfe_alloc = msm_vfe_sync_alloc,
-};
-
-static int __msm_open(struct msm_sync *sync, const char *const apps_id)
-{
- int rc = 0;
-
- mutex_lock(&sync->lock);
- if (sync->apps_id && strcmp(sync->apps_id, apps_id)) {
- pr_err("msm_camera(%s): sensor %s is already opened for %s\n",
- apps_id,
- sync->sdata->sensor_name,
- sync->apps_id);
- rc = -EBUSY;
- goto msm_open_done;
- }
-
- sync->apps_id = apps_id;
-
- if (!sync->opencnt) {
-
- msm_camvfe_fn_init(&sync->vfefn, sync);
- if (sync->vfefn.vfe_init) {
- rc = sync->vfefn.vfe_init(&msm_vfe_s,
- sync->pdev);
- if (rc < 0) {
- pr_err("vfe_init failed at %d\n", rc);
- goto msm_open_done;
- }
- rc = sync->sctrl.s_init(sync->sdata);
- if (rc < 0) {
- pr_err("sensor init failed: %d\n", rc);
- goto msm_open_done;
- }
- } else {
- pr_err("no sensor init func\n");
- rc = -ENODEV;
- goto msm_open_done;
- }
-
- if (rc >= 0) {
- INIT_HLIST_HEAD(&sync->frame);
- INIT_HLIST_HEAD(&sync->stats);
- sync->unblock_poll_frame = 0;
- }
- }
- sync->opencnt++;
-
-msm_open_done:
- mutex_unlock(&sync->lock);
- return rc;
-}
-
-static int msm_open_common(struct inode *inode, struct file *filep,
- int once)
-{
- int rc;
- struct msm_device *pmsm =
- container_of(inode->i_cdev, struct msm_device, cdev);
-
- CDBG("msm_camera: open %s\n", filep->f_path.dentry->d_name.name);
-
- if (atomic_cmpxchg(&pmsm->opened, 0, 1) && once) {
- pr_err("msm_camera: %s is already opened.\n",
- filep->f_path.dentry->d_name.name);
- return -EBUSY;
- }
-
- rc = nonseekable_open(inode, filep);
- if (rc < 0) {
- pr_err("msm_open: nonseekable_open error %d\n", rc);
- return rc;
- }
-
- rc = __msm_open(pmsm->sync, MSM_APPS_ID_PROP);
- if (rc < 0)
- return rc;
-
- filep->private_data = pmsm;
-
- CDBG("msm_open() open: rc = %d\n", rc);
- return rc;
-}
-
-static int msm_open(struct inode *inode, struct file *filep)
-{
- return msm_open_common(inode, filep, 1);
-}
-
-static int msm_open_control(struct inode *inode, struct file *filep)
-{
- int rc;
-
- struct msm_control_device *ctrl_pmsm =
- kmalloc(sizeof(struct msm_control_device), GFP_KERNEL);
- if (!ctrl_pmsm)
- return -ENOMEM;
-
- rc = msm_open_common(inode, filep, 0);
- if (rc < 0) {
- kfree(ctrl_pmsm);
- return rc;
- }
-
- ctrl_pmsm->pmsm = filep->private_data;
- filep->private_data = ctrl_pmsm;
- spin_lock_init(&ctrl_pmsm->ctrl_q.ctrl_status_q_lock);
- INIT_LIST_HEAD(&ctrl_pmsm->ctrl_q.ctrl_status_q);
- init_waitqueue_head(&ctrl_pmsm->ctrl_q.ctrl_status_wait);
-
- CDBG("msm_open() open: rc = %d\n", rc);
- return rc;
-}
-
-static int __msm_v4l2_control(struct msm_sync *sync,
- struct msm_ctrl_cmd *out)
-{
- int rc = 0;
-
- struct msm_queue_cmd *qcmd = NULL, *rcmd = NULL;
- struct msm_ctrl_cmd *ctrl;
- struct msm_control_device_queue FIXME;
-
- /* wake up config thread, 4 is for V4L2 application */
- qcmd = kmalloc(sizeof(struct msm_queue_cmd), GFP_KERNEL);
- if (!qcmd) {
- pr_err("msm_control: cannot allocate buffer\n");
- rc = -ENOMEM;
- goto end;
- }
- qcmd->type = MSM_CAM_Q_V4L2_REQ;
- qcmd->command = out;
-
- rcmd = __msm_control(sync, &FIXME, qcmd, out->timeout_ms);
- if (IS_ERR(rcmd)) {
- rc = PTR_ERR(rcmd);
- goto end;
- }
-
- ctrl = (struct msm_ctrl_cmd *)(rcmd->command);
- /* FIXME: we should just set out->length = ctrl->length; */
- BUG_ON(out->length < ctrl->length);
- memcpy(out->value, ctrl->value, ctrl->length);
-
-end:
- kfree(rcmd);
- CDBG("__msm_v4l2_control: end rc = %d\n", rc);
- return rc;
-}
-
-static const struct file_operations msm_fops_config = {
- .owner = THIS_MODULE,
- .open = msm_open,
- .unlocked_ioctl = msm_ioctl_config,
- .release = msm_release_config,
- .llseek = no_llseek,
-};
-
-static const struct file_operations msm_fops_control = {
- .owner = THIS_MODULE,
- .open = msm_open_control,
- .unlocked_ioctl = msm_ioctl_control,
- .release = msm_release_control,
- .llseek = no_llseek,
-};
-
-static const struct file_operations msm_fops_frame = {
- .owner = THIS_MODULE,
- .open = msm_open,
- .unlocked_ioctl = msm_ioctl_frame,
- .release = msm_release_frame,
- .poll = msm_poll_frame,
- .llseek = no_llseek,
-};
-
-static int msm_setup_cdev(struct msm_device *msm,
- int node,
- dev_t devno,
- const char *suffix,
- const struct file_operations *fops)
-{
- int rc = -ENODEV;
-
- struct device *device =
- device_create(msm_class, NULL,
- devno, NULL,
- "%s%d", suffix, node);
-
- if (IS_ERR(device)) {
- rc = PTR_ERR(device);
- pr_err("msm_camera: error creating device: %d\n", rc);
- return rc;
- }
-
- cdev_init(&msm->cdev, fops);
- msm->cdev.owner = THIS_MODULE;
-
- rc = cdev_add(&msm->cdev, devno, 1);
- if (rc < 0) {
- pr_err("msm_camera: error adding cdev: %d\n", rc);
- device_destroy(msm_class, devno);
- return rc;
- }
-
- return rc;
-}
-
-static int msm_tear_down_cdev(struct msm_device *msm, dev_t devno)
-{
- cdev_del(&msm->cdev);
- device_destroy(msm_class, devno);
- return 0;
-}
-
-int msm_v4l2_register(struct msm_v4l2_driver *drv)
-{
- /* FIXME: support multiple sensors */
- if (list_empty(&msm_sensors))
- return -ENODEV;
-
- drv->sync = list_first_entry(&msm_sensors, struct msm_sync, list);
- drv->open = __msm_open;
- drv->release = __msm_release;
- drv->ctrl = __msm_v4l2_control;
- drv->reg_pmem = __msm_register_pmem;
- drv->get_frame = __msm_get_frame;
- drv->put_frame = __msm_put_frame_buf;
- drv->get_pict = __msm_get_pic;
- drv->drv_poll = __msm_poll_frame;
-
- return 0;
-}
-EXPORT_SYMBOL(msm_v4l2_register);
-
-int msm_v4l2_unregister(struct msm_v4l2_driver *drv)
-{
- drv->sync = NULL;
- return 0;
-}
-EXPORT_SYMBOL(msm_v4l2_unregister);
-
-static int msm_sync_init(struct msm_sync *sync,
- struct platform_device *pdev,
- int (*sensor_probe)(const struct msm_camera_sensor_info *,
- struct msm_sensor_ctrl *))
-{
- int rc = 0;
- struct msm_sensor_ctrl sctrl;
- sync->sdata = pdev->dev.platform_data;
-
- spin_lock_init(&sync->msg_event_q_lock);
- INIT_LIST_HEAD(&sync->msg_event_q);
- init_waitqueue_head(&sync->msg_event_wait);
-
- spin_lock_init(&sync->prev_frame_q_lock);
- INIT_LIST_HEAD(&sync->prev_frame_q);
- init_waitqueue_head(&sync->prev_frame_wait);
-
- spin_lock_init(&sync->pict_frame_q_lock);
- INIT_LIST_HEAD(&sync->pict_frame_q);
- init_waitqueue_head(&sync->pict_frame_wait);
-
- rc = msm_camio_probe_on(pdev);
- if (rc < 0)
- return rc;
- rc = sensor_probe(sync->sdata, &sctrl);
- if (rc >= 0) {
- sync->pdev = pdev;
- sync->sctrl = sctrl;
- }
- msm_camio_probe_off(pdev);
- if (rc < 0) {
- pr_err("msm_camera: failed to initialize %s\n",
- sync->sdata->sensor_name);
- return rc;
- }
-
- sync->opencnt = 0;
- mutex_init(&sync->lock);
- CDBG("initialized %s\n", sync->sdata->sensor_name);
- return rc;
-}
-
-static int msm_sync_destroy(struct msm_sync *sync)
-{
- return 0;
-}
-
-static int msm_device_init(struct msm_device *pmsm,
- struct msm_sync *sync,
- int node)
-{
- int dev_num = 3 * node;
- int rc = msm_setup_cdev(pmsm, node,
- MKDEV(MAJOR(msm_devno), dev_num),
- "control", &msm_fops_control);
- if (rc < 0) {
- pr_err("error creating control node: %d\n", rc);
- return rc;
- }
-
- rc = msm_setup_cdev(pmsm + 1, node,
- MKDEV(MAJOR(msm_devno), dev_num + 1),
- "config", &msm_fops_config);
- if (rc < 0) {
- pr_err("error creating config node: %d\n", rc);
- msm_tear_down_cdev(pmsm, MKDEV(MAJOR(msm_devno),
- dev_num));
- return rc;
- }
-
- rc = msm_setup_cdev(pmsm + 2, node,
- MKDEV(MAJOR(msm_devno), dev_num + 2),
- "frame", &msm_fops_frame);
- if (rc < 0) {
- pr_err("error creating frame node: %d\n", rc);
- msm_tear_down_cdev(pmsm,
- MKDEV(MAJOR(msm_devno), dev_num));
- msm_tear_down_cdev(pmsm + 1,
- MKDEV(MAJOR(msm_devno), dev_num + 1));
- return rc;
- }
-
- atomic_set(&pmsm[0].opened, 0);
- atomic_set(&pmsm[1].opened, 0);
- atomic_set(&pmsm[2].opened, 0);
-
- pmsm[0].sync = sync;
- pmsm[1].sync = sync;
- pmsm[2].sync = sync;
-
- return rc;
-}
-
-int msm_camera_drv_start(struct platform_device *dev,
- int (*sensor_probe)(const struct msm_camera_sensor_info *,
- struct msm_sensor_ctrl *))
-{
- struct msm_device *pmsm = NULL;
- struct msm_sync *sync;
- int rc = -ENODEV;
- static int camera_node;
-
- if (camera_node >= MSM_MAX_CAMERA_SENSORS) {
- pr_err("msm_camera: too many camera sensors\n");
- return rc;
- }
-
- if (!msm_class) {
- /* There are three device nodes per sensor */
- rc = alloc_chrdev_region(&msm_devno, 0,
- 3 * MSM_MAX_CAMERA_SENSORS,
- "msm_camera");
- if (rc < 0) {
- pr_err("msm_camera: failed to allocate chrdev: %d\n",
- rc);
- return rc;
- }
-
- msm_class = class_create(THIS_MODULE, "msm_camera");
- if (IS_ERR(msm_class)) {
- rc = PTR_ERR(msm_class);
- pr_err("msm_camera: create device class failed: %d\n",
- rc);
- return rc;
- }
- }
-
- pmsm = kzalloc(sizeof(struct msm_device) * 3 +
- sizeof(struct msm_sync), GFP_ATOMIC);
- if (!pmsm)
- return -ENOMEM;
- sync = (struct msm_sync *)(pmsm + 3);
-
- rc = msm_sync_init(sync, dev, sensor_probe);
- if (rc < 0) {
- kfree(pmsm);
- return rc;
- }
-
- CDBG("setting camera node %d\n", camera_node);
- rc = msm_device_init(pmsm, sync, camera_node);
- if (rc < 0) {
- msm_sync_destroy(sync);
- kfree(pmsm);
- return rc;
- }
-
- camera_node++;
- list_add(&sync->list, &msm_sensors);
- return rc;
-}
-EXPORT_SYMBOL(msm_camera_drv_start);
diff --git a/trunk/drivers/staging/dream/camera/msm_io7x.c b/trunk/drivers/staging/dream/camera/msm_io7x.c
deleted file mode 100644
index 55c020bb7afa..000000000000
--- a/trunk/drivers/staging/dream/camera/msm_io7x.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * Copyright (c) 2008-2009 QUALCOMM Incorporated
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-
-#define CAMIF_CFG_RMSK 0x1fffff
-#define CAM_SEL_BMSK 0x2
-#define CAM_PCLK_SRC_SEL_BMSK 0x60000
-#define CAM_PCLK_INVERT_BMSK 0x80000
-#define CAM_PAD_REG_SW_RESET_BMSK 0x100000
-
-#define EXT_CAM_HSYNC_POL_SEL_BMSK 0x10000
-#define EXT_CAM_VSYNC_POL_SEL_BMSK 0x8000
-#define MDDI_CLK_CHICKEN_BIT_BMSK 0x80
-
-#define CAM_SEL_SHFT 0x1
-#define CAM_PCLK_SRC_SEL_SHFT 0x11
-#define CAM_PCLK_INVERT_SHFT 0x13
-#define CAM_PAD_REG_SW_RESET_SHFT 0x14
-
-#define EXT_CAM_HSYNC_POL_SEL_SHFT 0x10
-#define EXT_CAM_VSYNC_POL_SEL_SHFT 0xF
-#define MDDI_CLK_CHICKEN_BIT_SHFT 0x7
-#define APPS_RESET_OFFSET 0x00000210
-
-static struct clk *camio_vfe_mdc_clk;
-static struct clk *camio_mdc_clk;
-static struct clk *camio_vfe_clk;
-
-static struct msm_camera_io_ext camio_ext;
-static struct resource *appio, *mdcio;
-void __iomem *appbase, *mdcbase;
-
-static struct msm_camera_io_ext camio_ext;
-static struct resource *appio, *mdcio;
-void __iomem *appbase, *mdcbase;
-
-extern int clk_set_flags(struct clk *clk, unsigned long flags);
-
-int msm_camio_clk_enable(enum msm_camio_clk_type clktype)
-{
- int rc = -1;
- struct clk *clk = NULL;
-
- switch (clktype) {
- case CAMIO_VFE_MDC_CLK:
- clk = camio_vfe_mdc_clk = clk_get(NULL, "vfe_mdc_clk");
- break;
-
- case CAMIO_MDC_CLK:
- clk = camio_mdc_clk = clk_get(NULL, "mdc_clk");
- break;
-
- case CAMIO_VFE_CLK:
- clk = camio_vfe_clk = clk_get(NULL, "vfe_clk");
- break;
-
- default:
- break;
- }
-
- if (!IS_ERR(clk)) {
- clk_enable(clk);
- rc = 0;
- }
-
- return rc;
-}
-
-int msm_camio_clk_disable(enum msm_camio_clk_type clktype)
-{
- int rc = -1;
- struct clk *clk = NULL;
-
- switch (clktype) {
- case CAMIO_VFE_MDC_CLK:
- clk = camio_vfe_mdc_clk;
- break;
-
- case CAMIO_MDC_CLK:
- clk = camio_mdc_clk;
- break;
-
- case CAMIO_VFE_CLK:
- clk = camio_vfe_clk;
- break;
-
- default:
- break;
- }
-
- if (!IS_ERR(clk)) {
- clk_disable(clk);
- clk_put(clk);
- rc = 0;
- }
-
- return rc;
-}
-
-void msm_camio_clk_rate_set(int rate)
-{
- struct clk *clk = camio_vfe_clk;
-
- if (clk != ERR_PTR(-ENOENT))
- clk_set_rate(clk, rate);
-}
-
-int msm_camio_enable(struct platform_device *pdev)
-{
- int rc = 0;
- struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
- struct msm_camera_device_platform_data *camdev = sinfo->pdata;
-
- camio_ext = camdev->ioext;
-
- appio = request_mem_region(camio_ext.appphy,
- camio_ext.appsz, pdev->name);
- if (!appio) {
- rc = -EBUSY;
- goto enable_fail;
- }
-
- appbase = ioremap(camio_ext.appphy,
- camio_ext.appsz);
- if (!appbase) {
- rc = -ENOMEM;
- goto apps_no_mem;
- }
-
- mdcio = request_mem_region(camio_ext.mdcphy,
- camio_ext.mdcsz, pdev->name);
- if (!mdcio) {
- rc = -EBUSY;
- goto mdc_busy;
- }
-
- mdcbase = ioremap(camio_ext.mdcphy,
- camio_ext.mdcsz);
- if (!mdcbase) {
- rc = -ENOMEM;
- goto mdc_no_mem;
- }
-
- camdev->camera_gpio_on();
-
- msm_camio_clk_enable(CAMIO_VFE_CLK);
- msm_camio_clk_enable(CAMIO_MDC_CLK);
- msm_camio_clk_enable(CAMIO_VFE_MDC_CLK);
- return 0;
-
-mdc_no_mem:
- release_mem_region(camio_ext.mdcphy, camio_ext.mdcsz);
-mdc_busy:
- iounmap(appbase);
-apps_no_mem:
- release_mem_region(camio_ext.appphy, camio_ext.appsz);
-enable_fail:
- return rc;
-}
-
-void msm_camio_disable(struct platform_device *pdev)
-{
- struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
- struct msm_camera_device_platform_data *camdev = sinfo->pdata;
-
- iounmap(mdcbase);
- release_mem_region(camio_ext.mdcphy, camio_ext.mdcsz);
- iounmap(appbase);
- release_mem_region(camio_ext.appphy, camio_ext.appsz);
-
- camdev->camera_gpio_off();
-
- msm_camio_clk_disable(CAMIO_VFE_CLK);
- msm_camio_clk_disable(CAMIO_MDC_CLK);
- msm_camio_clk_disable(CAMIO_VFE_MDC_CLK);
-}
-
-void msm_camio_camif_pad_reg_reset(void)
-{
- uint32_t reg;
- uint32_t mask, value;
-
- /* select CLKRGM_VFE_SRC_CAM_VFE_SRC: internal source */
- msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_INTERNAL);
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
-
- mask = CAM_SEL_BMSK |
- CAM_PCLK_SRC_SEL_BMSK |
- CAM_PCLK_INVERT_BMSK;
-
- value = 1 << CAM_SEL_SHFT |
- 3 << CAM_PCLK_SRC_SEL_SHFT |
- 0 << CAM_PCLK_INVERT_SHFT;
-
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
- mask = CAM_PAD_REG_SW_RESET_BMSK;
- value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
- mask = CAM_PAD_REG_SW_RESET_BMSK;
- value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-
- msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_EXTERNAL);
- mdelay(10);
-}
-
-void msm_camio_vfe_blk_reset(void)
-{
- uint32_t val;
-
- val = readl(appbase + 0x00000210);
- val |= 0x1;
- writel(val, appbase + 0x00000210);
- mdelay(10);
-
- val = readl(appbase + 0x00000210);
- val &= ~0x1;
- writel(val, appbase + 0x00000210);
- mdelay(10);
-}
-
-void msm_camio_camif_pad_reg_reset_2(void)
-{
- uint32_t reg;
- uint32_t mask, value;
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
- mask = CAM_PAD_REG_SW_RESET_BMSK;
- value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
- mask = CAM_PAD_REG_SW_RESET_BMSK;
- value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-}
-
-void msm_camio_clk_sel(enum msm_camio_clk_src_type srctype)
-{
- struct clk *clk = NULL;
-
- clk = camio_vfe_clk;
-
- if (clk != NULL && clk != ERR_PTR(-ENOENT)) {
- switch (srctype) {
- case MSM_CAMIO_CLK_SRC_INTERNAL:
- clk_set_flags(clk, 0x00000100 << 1);
- break;
-
- case MSM_CAMIO_CLK_SRC_EXTERNAL:
- clk_set_flags(clk, 0x00000100);
- break;
-
- default:
- break;
- }
- }
-}
-
-int msm_camio_probe_on(struct platform_device *pdev)
-{
- struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
- struct msm_camera_device_platform_data *camdev = sinfo->pdata;
- camdev->camera_gpio_on();
- return msm_camio_clk_enable(CAMIO_VFE_CLK);
-}
-
-int msm_camio_probe_off(struct platform_device *pdev)
-{
- struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
- struct msm_camera_device_platform_data *camdev = sinfo->pdata;
- camdev->camera_gpio_off();
- return msm_camio_clk_disable(CAMIO_VFE_CLK);
-}
diff --git a/trunk/drivers/staging/dream/camera/msm_io8x.c b/trunk/drivers/staging/dream/camera/msm_io8x.c
deleted file mode 100644
index 895161ae2e14..000000000000
--- a/trunk/drivers/staging/dream/camera/msm_io8x.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * Copyright (c) 2008-2009 QUALCOMM Incorporated
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-
-#define CAMIF_CFG_RMSK 0x1fffff
-#define CAM_SEL_BMSK 0x2
-#define CAM_PCLK_SRC_SEL_BMSK 0x60000
-#define CAM_PCLK_INVERT_BMSK 0x80000
-#define CAM_PAD_REG_SW_RESET_BMSK 0x100000
-
-#define EXT_CAM_HSYNC_POL_SEL_BMSK 0x10000
-#define EXT_CAM_VSYNC_POL_SEL_BMSK 0x8000
-#define MDDI_CLK_CHICKEN_BIT_BMSK 0x80
-
-#define CAM_SEL_SHFT 0x1
-#define CAM_PCLK_SRC_SEL_SHFT 0x11
-#define CAM_PCLK_INVERT_SHFT 0x13
-#define CAM_PAD_REG_SW_RESET_SHFT 0x14
-
-#define EXT_CAM_HSYNC_POL_SEL_SHFT 0x10
-#define EXT_CAM_VSYNC_POL_SEL_SHFT 0xF
-#define MDDI_CLK_CHICKEN_BIT_SHFT 0x7
-#define APPS_RESET_OFFSET 0x00000210
-
-static struct clk *camio_vfe_mdc_clk;
-static struct clk *camio_mdc_clk;
-static struct clk *camio_vfe_clk;
-static struct clk *camio_vfe_axi_clk;
-static struct msm_camera_io_ext camio_ext;
-static struct resource *appio, *mdcio;
-void __iomem *appbase, *mdcbase;
-
-extern int clk_set_flags(struct clk *clk, unsigned long flags);
-
-int msm_camio_clk_enable(enum msm_camio_clk_type clktype)
-{
- int rc = 0;
- struct clk *clk = NULL;
-
- switch (clktype) {
- case CAMIO_VFE_MDC_CLK:
- camio_vfe_mdc_clk =
- clk = clk_get(NULL, "vfe_mdc_clk");
- break;
-
- case CAMIO_MDC_CLK:
- camio_mdc_clk =
- clk = clk_get(NULL, "mdc_clk");
- break;
-
- case CAMIO_VFE_CLK:
- camio_vfe_clk =
- clk = clk_get(NULL, "vfe_clk");
- break;
-
- case CAMIO_VFE_AXI_CLK:
- camio_vfe_axi_clk =
- clk = clk_get(NULL, "vfe_axi_clk");
- break;
-
- default:
- break;
- }
-
- if (!IS_ERR(clk))
- clk_enable(clk);
- else
- rc = -1;
-
- return rc;
-}
-
-int msm_camio_clk_disable(enum msm_camio_clk_type clktype)
-{
- int rc = 0;
- struct clk *clk = NULL;
-
- switch (clktype) {
- case CAMIO_VFE_MDC_CLK:
- clk = camio_vfe_mdc_clk;
- break;
-
- case CAMIO_MDC_CLK:
- clk = camio_mdc_clk;
- break;
-
- case CAMIO_VFE_CLK:
- clk = camio_vfe_clk;
- break;
-
- case CAMIO_VFE_AXI_CLK:
- clk = camio_vfe_axi_clk;
- break;
-
- default:
- break;
- }
-
- if (!IS_ERR(clk)) {
- clk_disable(clk);
- clk_put(clk);
- } else
- rc = -1;
-
- return rc;
-}
-
-void msm_camio_clk_rate_set(int rate)
-{
- struct clk *clk = camio_vfe_mdc_clk;
-
- /* TODO: check return */
- clk_set_rate(clk, rate);
-}
-
-int msm_camio_enable(struct platform_device *pdev)
-{
- int rc = 0;
- struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
- struct msm_camera_device_platform_data *camdev = sinfo->pdata;
-
- camio_ext = camdev->ioext;
-
- appio = request_mem_region(camio_ext.appphy,
- camio_ext.appsz, pdev->name);
- if (!appio) {
- rc = -EBUSY;
- goto enable_fail;
- }
-
- appbase = ioremap(camio_ext.appphy,
- camio_ext.appsz);
- if (!appbase) {
- rc = -ENOMEM;
- goto apps_no_mem;
- }
-
- mdcio = request_mem_region(camio_ext.mdcphy,
- camio_ext.mdcsz, pdev->name);
- if (!mdcio) {
- rc = -EBUSY;
- goto mdc_busy;
- }
-
- mdcbase = ioremap(camio_ext.mdcphy,
- camio_ext.mdcsz);
- if (!mdcbase) {
- rc = -ENOMEM;
- goto mdc_no_mem;
- }
-
- camdev->camera_gpio_on();
-
- msm_camio_clk_enable(CAMIO_VFE_CLK);
- msm_camio_clk_enable(CAMIO_MDC_CLK);
- msm_camio_clk_enable(CAMIO_VFE_MDC_CLK);
- msm_camio_clk_enable(CAMIO_VFE_AXI_CLK);
- return 0;
-
-mdc_no_mem:
- release_mem_region(camio_ext.mdcphy, camio_ext.mdcsz);
-mdc_busy:
- iounmap(appbase);
-apps_no_mem:
- release_mem_region(camio_ext.appphy, camio_ext.appsz);
-enable_fail:
- return rc;
-}
-
-void msm_camio_disable(struct platform_device *pdev)
-{
- struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
- struct msm_camera_device_platform_data *camdev = sinfo->pdata;
-
- iounmap(mdcbase);
- release_mem_region(camio_ext.mdcphy, camio_ext.mdcsz);
- iounmap(appbase);
- release_mem_region(camio_ext.appphy, camio_ext.appsz);
-
- camdev->camera_gpio_off();
-
- msm_camio_clk_disable(CAMIO_VFE_MDC_CLK);
- msm_camio_clk_disable(CAMIO_MDC_CLK);
- msm_camio_clk_disable(CAMIO_VFE_CLK);
- msm_camio_clk_disable(CAMIO_VFE_AXI_CLK);
-}
-
-void msm_camio_camif_pad_reg_reset(void)
-{
- uint32_t reg;
- uint32_t mask, value;
-
- /* select CLKRGM_VFE_SRC_CAM_VFE_SRC: internal source */
- msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_INTERNAL);
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
-
- mask = CAM_SEL_BMSK |
- CAM_PCLK_SRC_SEL_BMSK |
- CAM_PCLK_INVERT_BMSK |
- EXT_CAM_HSYNC_POL_SEL_BMSK |
- EXT_CAM_VSYNC_POL_SEL_BMSK |
- MDDI_CLK_CHICKEN_BIT_BMSK;
-
- value = 1 << CAM_SEL_SHFT |
- 3 << CAM_PCLK_SRC_SEL_SHFT |
- 0 << CAM_PCLK_INVERT_SHFT |
- 0 << EXT_CAM_HSYNC_POL_SEL_SHFT |
- 0 << EXT_CAM_VSYNC_POL_SEL_SHFT |
- 0 << MDDI_CLK_CHICKEN_BIT_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
- mask = CAM_PAD_REG_SW_RESET_BMSK;
- value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
- mask = CAM_PAD_REG_SW_RESET_BMSK;
- value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-
- msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_EXTERNAL);
-
- mdelay(10);
-
- /* todo: check return */
- if (camio_vfe_clk)
- clk_set_rate(camio_vfe_clk, 96000000);
-}
-
-void msm_camio_vfe_blk_reset(void)
-{
- uint32_t val;
-
- val = readl(appbase + 0x00000210);
- val |= 0x1;
- writel(val, appbase + 0x00000210);
- mdelay(10);
-
- val = readl(appbase + 0x00000210);
- val &= ~0x1;
- writel(val, appbase + 0x00000210);
- mdelay(10);
-}
-
-void msm_camio_camif_pad_reg_reset_2(void)
-{
- uint32_t reg;
- uint32_t mask, value;
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
- mask = CAM_PAD_REG_SW_RESET_BMSK;
- value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
- mask = CAM_PAD_REG_SW_RESET_BMSK;
- value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-}
-
-void msm_camio_clk_sel(enum msm_camio_clk_src_type srctype)
-{
- struct clk *clk = NULL;
-
- clk = camio_vfe_clk;
-
- if (clk != NULL) {
- switch (srctype) {
- case MSM_CAMIO_CLK_SRC_INTERNAL:
- clk_set_flags(clk, 0x00000100 << 1);
- break;
-
- case MSM_CAMIO_CLK_SRC_EXTERNAL:
- clk_set_flags(clk, 0x00000100);
- break;
-
- default:
- break;
- }
- }
-}
-
-void msm_camio_clk_axi_rate_set(int rate)
-{
- struct clk *clk = camio_vfe_axi_clk;
- /* todo: check return */
- clk_set_rate(clk, rate);
-}
-
-int msm_camio_probe_on(struct platform_device *pdev)
-{
- struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
- struct msm_camera_device_platform_data *camdev = sinfo->pdata;
-
- camdev->camera_gpio_on();
- return msm_camio_clk_enable(CAMIO_VFE_MDC_CLK);
-}
-
-int msm_camio_probe_off(struct platform_device *pdev)
-{
- struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
- struct msm_camera_device_platform_data *camdev = sinfo->pdata;
-
- camdev->camera_gpio_off();
- return msm_camio_clk_disable(CAMIO_VFE_MDC_CLK);
-}
diff --git a/trunk/drivers/staging/dream/camera/msm_v4l2.c b/trunk/drivers/staging/dream/camera/msm_v4l2.c
deleted file mode 100644
index c276f2f7583a..000000000000
--- a/trunk/drivers/staging/dream/camera/msm_v4l2.c
+++ /dev/null
@@ -1,798 +0,0 @@
-/*
- *
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- *
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-/*#include */
-
-#define MSM_V4L2_START_SNAPSHOT _IOWR('V', BASE_VIDIOC_PRIVATE+1, \
- struct v4l2_buffer)
-
-#define MSM_V4L2_GET_PICTURE _IOWR('V', BASE_VIDIOC_PRIVATE+2, \
- struct v4l2_buffer)
-
-#define MSM_V4L2_DEVICE_NAME "msm_v4l2"
-
-#define MSM_V4L2_PROC_NAME "msm_v4l2"
-
-#define MSM_V4L2_DEVNUM_MPEG2 0
-#define MSM_V4L2_DEVNUM_YUV 20
-
-/* HVGA-P (portrait) and HVGA-L (landscape) */
-#define MSM_V4L2_WIDTH 480
-#define MSM_V4L2_HEIGHT 320
-
-#if 1
-#define D(fmt, args...) printk(KERN_INFO "msm_v4l2: " fmt, ##args)
-#else
-#define D(fmt, args...) do {} while (0)
-#endif
-
-#define PREVIEW_FRAMES_NUM 4
-
-struct msm_v4l2_device {
- struct list_head read_queue;
- struct v4l2_format current_cap_format;
- struct v4l2_format current_pix_format;
- struct video_device *pvdev;
- struct msm_v4l2_driver *drv;
- uint8_t opencnt;
-
- spinlock_t read_queue_lock;
-};
-
-static struct msm_v4l2_device *g_pmsm_v4l2_dev;
-
-
-static DEFINE_MUTEX(msm_v4l2_opencnt_lock);
-
-static int msm_v4l2_open(struct file *f)
-{
- int rc = 0;
- D("%s\n", __func__);
- mutex_lock(&msm_v4l2_opencnt_lock);
- if (!g_pmsm_v4l2_dev->opencnt) {
- rc = g_pmsm_v4l2_dev->drv->open(
- g_pmsm_v4l2_dev->drv->sync,
- MSM_APPS_ID_V4L2);
- }
- g_pmsm_v4l2_dev->opencnt++;
- mutex_unlock(&msm_v4l2_opencnt_lock);
- return rc;
-}
-
-static int msm_v4l2_release(struct file *f)
-{
- int rc = 0;
- D("%s\n", __func__);
- mutex_lock(&msm_v4l2_opencnt_lock);
- if (!g_pmsm_v4l2_dev->opencnt) {
- g_pmsm_v4l2_dev->opencnt--;
- if (!g_pmsm_v4l2_dev->opencnt) {
- rc = g_pmsm_v4l2_dev->drv->release(
- g_pmsm_v4l2_dev->drv->sync);
- }
- }
- mutex_unlock(&msm_v4l2_opencnt_lock);
- return rc;
-}
-
-static unsigned int msm_v4l2_poll(struct file *f, struct poll_table_struct *w)
-{
- return g_pmsm_v4l2_dev->drv->drv_poll(g_pmsm_v4l2_dev->drv->sync, f, w);
-}
-
-static long msm_v4l2_ioctl(struct file *filep,
- unsigned int cmd, unsigned long arg)
-{
- struct msm_ctrl_cmd *ctrlcmd;
-
- D("msm_v4l2_ioctl, cmd = %d, %d\n", cmd, __LINE__);
-
- switch (cmd) {
- case MSM_V4L2_START_SNAPSHOT:
-
- ctrlcmd = kmalloc(sizeof(struct msm_ctrl_cmd), GFP_ATOMIC);
- if (!ctrlcmd) {
- CDBG("msm_v4l2_ioctl: cannot allocate buffer\n");
- return -ENOMEM;
- }
-
- ctrlcmd->length = 0;
- ctrlcmd->value = NULL;
- ctrlcmd->timeout_ms = 10000;
-
- D("msm_v4l2_ioctl, MSM_V4L2_START_SNAPSHOT v4l2 ioctl %d\n",
- cmd);
- ctrlcmd->type = MSM_V4L2_SNAPSHOT;
- return g_pmsm_v4l2_dev->drv->ctrl(g_pmsm_v4l2_dev->drv->sync,
- ctrlcmd);
-
- case MSM_V4L2_GET_PICTURE:
- D("msm_v4l2_ioctl, MSM_V4L2_GET_PICTURE v4l2 ioctl %d\n", cmd);
- ctrlcmd = (struct msm_ctrl_cmd *)arg;
- return g_pmsm_v4l2_dev->drv->get_pict(
- g_pmsm_v4l2_dev->drv->sync, ctrlcmd);
-
- default:
- D("msm_v4l2_ioctl, standard v4l2 ioctl %d\n", cmd);
- return video_ioctl2(filep, cmd, arg);
- }
-}
-
-static void msm_v4l2_release_dev(struct video_device *d)
-{
- D("%s\n", __func__);
-}
-
-static int msm_v4l2_querycap(struct file *f,
- void *pctx, struct v4l2_capability *pcaps)
-{
- D("%s\n", __func__);
- strncpy(pcaps->driver, MSM_APPS_ID_V4L2, sizeof(pcaps->driver));
- strncpy(pcaps->card,
- MSM_V4L2_DEVICE_NAME, sizeof(pcaps->card));
- pcaps->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
- return 0;
-}
-
-static int msm_v4l2_s_std(struct file *f, void *pctx, v4l2_std_id *pnorm)
-{
- D("%s\n", __func__);
- return 0;
-}
-
-static int msm_v4l2_queryctrl(struct file *f,
- void *pctx, struct v4l2_queryctrl *pqctrl)
-{
- int rc = 0;
- struct msm_ctrl_cmd *ctrlcmd;
-
- D("%s\n", __func__);
-
- ctrlcmd = kmalloc(sizeof(struct msm_ctrl_cmd), GFP_ATOMIC);
- if (!ctrlcmd) {
- CDBG("msm_v4l2_queryctrl: cannot allocate buffer\n");
- return -ENOMEM;
- }
-
- ctrlcmd->type = MSM_V4L2_QUERY_CTRL;
- ctrlcmd->length = sizeof(struct v4l2_queryctrl);
- ctrlcmd->value = pqctrl;
- ctrlcmd->timeout_ms = 10000;
-
- rc = g_pmsm_v4l2_dev->drv->ctrl(g_pmsm_v4l2_dev->drv->sync, ctrlcmd);
- if (rc < 0)
- return -1;
-
- return ctrlcmd->status;
-}
-
-static int msm_v4l2_g_ctrl(struct file *f, void *pctx, struct v4l2_control *c)
-{
- int rc = 0;
- struct msm_ctrl_cmd *ctrlcmd;
-
- D("%s\n", __func__);
-
- ctrlcmd = kmalloc(sizeof(struct msm_ctrl_cmd), GFP_ATOMIC);
- if (!ctrlcmd) {
- CDBG("msm_v4l2_g_ctrl: cannot allocate buffer\n");
- return -ENOMEM;
- }
-
- ctrlcmd->type = MSM_V4L2_GET_CTRL;
- ctrlcmd->length = sizeof(struct v4l2_control);
- ctrlcmd->value = c;
- ctrlcmd->timeout_ms = 10000;
-
- rc = g_pmsm_v4l2_dev->drv->ctrl(g_pmsm_v4l2_dev->drv->sync, ctrlcmd);
- if (rc < 0)
- return -1;
-
- return ctrlcmd->status;
-}
-
-static int msm_v4l2_s_ctrl(struct file *f, void *pctx, struct v4l2_control *c)
-{
- int rc = 0;
- struct msm_ctrl_cmd *ctrlcmd;
-
- ctrlcmd = kmalloc(sizeof(struct msm_ctrl_cmd), GFP_ATOMIC);
- if (!ctrlcmd) {
- CDBG("msm_v4l2_s_ctrl: cannot allocate buffer\n");
- return -ENOMEM;
- }
-
- ctrlcmd->type = MSM_V4L2_SET_CTRL;
- ctrlcmd->length = sizeof(struct v4l2_control);
- ctrlcmd->value = c;
- ctrlcmd->timeout_ms = 10000;
-
- D("%s\n", __func__);
-
- rc = g_pmsm_v4l2_dev->drv->ctrl(g_pmsm_v4l2_dev->drv->sync, ctrlcmd);
- if (rc < 0)
- return -1;
-
- return ctrlcmd->status;
-}
-
-static int msm_v4l2_reqbufs(struct file *f,
- void *pctx, struct v4l2_requestbuffers *b)
-{
- D("%s\n", __func__);
- return 0;
-}
-
-static int msm_v4l2_querybuf(struct file *f, void *pctx, struct v4l2_buffer *pb)
-{
- struct msm_pmem_info pmem_buf;
-#if 0
- __u32 width = 0;
- __u32 height = 0;
- __u32 y_size = 0;
- __u32 y_pad = 0;
-
- /* FIXME: g_pmsm_v4l2_dev->current_pix_format.fmt.pix.width; */
- width = 640;
- /* FIXME: g_pmsm_v4l2_dev->current_pix_format.fmt.pix.height; */
- height = 480;
-
- D("%s: width = %d, height = %d\n", __func__, width, height);
-
- y_size = width * height;
- y_pad = y_size % 4;
-#endif
-
- __u32 y_pad = pb->bytesused % 4;
-
- /* V4L2 videodev will do the copy_from_user. */
-
- memset(&pmem_buf, 0, sizeof(struct msm_pmem_info));
- pmem_buf.type = MSM_PMEM_OUTPUT2;
- pmem_buf.vaddr = (void *)pb->m.userptr;
- pmem_buf.y_off = 0;
- pmem_buf.fd = (int)pb->reserved;
- /* pmem_buf.cbcr_off = (y_size + y_pad); */
- pmem_buf.cbcr_off = (pb->bytesused + y_pad);
-
- g_pmsm_v4l2_dev->drv->reg_pmem(g_pmsm_v4l2_dev->drv->sync, &pmem_buf);
-
- return 0;
-}
-
-static int msm_v4l2_qbuf(struct file *f, void *pctx, struct v4l2_buffer *pb)
-{
- /*
- __u32 y_size = 0;
- __u32 y_pad = 0;
- __u32 width = 0;
- __u32 height = 0;
- */
-
- __u32 y_pad = 0;
-
- struct msm_pmem_info meminfo;
- struct msm_frame frame;
- static int cnt;
-
- if ((pb->flags >> 16) & 0x0001) {
- /* this is for previwe */
-#if 0
- width = 640;
- height = 480;
-
- /* V4L2 videodev will do the copy_from_user. */
- D("%s: width = %d, height = %d\n", __func__, width, height);
- y_size = width * height;
- y_pad = y_size % 4;
-#endif
-
- y_pad = pb->bytesused % 4;
-
- if (pb->type == V4L2_BUF_TYPE_PRIVATE) {
- /* this qbuf is actually for releasing */
-
- frame.buffer = pb->m.userptr;
- frame.y_off = 0;
- /* frame.cbcr_off = (y_size + y_pad); */
- frame.cbcr_off = (pb->bytesused + y_pad);
- frame.fd = pb->reserved;
-
- D("V4L2_BUF_TYPE_PRIVATE: pb->bytesused = %d \n",
- pb->bytesused);
-
- g_pmsm_v4l2_dev->drv->put_frame(
- g_pmsm_v4l2_dev->drv->sync,
- &frame);
-
- return 0;
- }
-
- D("V4L2_BUF_TYPE_VIDEO_CAPTURE: pb->bytesused = %d \n",
- pb->bytesused);
-
- meminfo.type = MSM_PMEM_OUTPUT2;
- meminfo.fd = (int)pb->reserved;
- meminfo.vaddr = (void *)pb->m.userptr;
- meminfo.y_off = 0;
- /* meminfo.cbcr_off = (y_size + y_pad); */
- meminfo.cbcr_off = (pb->bytesused + y_pad);
- if (cnt == PREVIEW_FRAMES_NUM - 1)
- meminfo.active = 0;
- else
- meminfo.active = 1;
- cnt++;
- g_pmsm_v4l2_dev->drv->reg_pmem(g_pmsm_v4l2_dev->drv->sync,
- &meminfo);
- } else if ((pb->flags) & 0x0001) {
- /* this is for snapshot */
-
- __u32 y_size = 0;
-
- if ((pb->flags >> 8) & 0x01) {
-
- y_size = pb->bytesused;
-
- meminfo.type = MSM_PMEM_THUMBAIL;
- } else if ((pb->flags >> 9) & 0x01) {
-
- y_size = pb->bytesused;
-
- meminfo.type = MSM_PMEM_MAINIMG;
- }
-
- y_pad = y_size % 4;
-
- meminfo.fd = (int)pb->reserved;
- meminfo.vaddr = (void *)pb->m.userptr;
- meminfo.y_off = 0;
- /* meminfo.cbcr_off = (y_size + y_pad); */
- meminfo.cbcr_off = (y_size + y_pad);
- meminfo.active = 1;
- g_pmsm_v4l2_dev->drv->reg_pmem(g_pmsm_v4l2_dev->drv->sync,
- &meminfo);
- }
-
- return 0;
-}
-
-static int msm_v4l2_dqbuf(struct file *f, void *pctx, struct v4l2_buffer *pb)
-{
- struct msm_frame frame;
- D("%s\n", __func__);
-
- /* V4L2 videodev will do the copy_to_user. */
- if (pb->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
-
- D("%s, %d\n", __func__, __LINE__);
-
- g_pmsm_v4l2_dev->drv->get_frame(
- g_pmsm_v4l2_dev->drv->sync,
- &frame);
-
- pb->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
- pb->m.userptr = (unsigned long)frame.buffer; /* FIXME */
- pb->reserved = (int)frame.fd;
- /* pb->length = (int)frame.cbcr_off; */
-
- pb->bytesused = frame.cbcr_off;
-
- } else if (pb->type == V4L2_BUF_TYPE_PRIVATE) {
- __u32 y_pad = pb->bytesused % 4;
-
- frame.buffer = pb->m.userptr;
- frame.y_off = 0;
- /* frame.cbcr_off = (y_size + y_pad); */
- frame.cbcr_off = (pb->bytesused + y_pad);
- frame.fd = pb->reserved;
-
- g_pmsm_v4l2_dev->drv->put_frame(
- g_pmsm_v4l2_dev->drv->sync,
- &frame);
- }
-
- return 0;
-}
-
-static int msm_v4l2_streamon(struct file *f, void *pctx, enum v4l2_buf_type i)
-{
- struct msm_ctrl_cmd *ctrlcmd;
-
- ctrlcmd = kmalloc(sizeof(struct msm_ctrl_cmd), GFP_ATOMIC);
- if (!ctrlcmd) {
- CDBG("msm_v4l2_s_fmt_cap: cannot allocate buffer\n");
- return -ENOMEM;
- }
-
- ctrlcmd->type = MSM_V4L2_STREAM_ON;
- ctrlcmd->timeout_ms = 10000;
- ctrlcmd->length = 0;
- ctrlcmd->value = NULL;
-
- D("%s\n", __func__);
-
- g_pmsm_v4l2_dev->drv->ctrl(
- g_pmsm_v4l2_dev->drv->sync,
- ctrlcmd);
-
- D("%s after drv->ctrl \n", __func__);
-
- return 0;
-}
-
-static int msm_v4l2_streamoff(struct file *f, void *pctx, enum v4l2_buf_type i)
-{
- struct msm_ctrl_cmd *ctrlcmd;
-
- ctrlcmd = kmalloc(sizeof(struct msm_ctrl_cmd), GFP_ATOMIC);
- if (!ctrlcmd) {
- CDBG("msm_v4l2_s_fmt_cap: cannot allocate buffer\n");
- return -ENOMEM;
- }
-
- ctrlcmd->type = MSM_V4L2_STREAM_OFF;
- ctrlcmd->timeout_ms = 10000;
- ctrlcmd->length = 0;
- ctrlcmd->value = NULL;
-
-
- D("%s\n", __func__);
-
- g_pmsm_v4l2_dev->drv->ctrl(
- g_pmsm_v4l2_dev->drv->sync,
- ctrlcmd);
-
- return 0;
-}
-
-static int msm_v4l2_enum_fmt_overlay(struct file *f,
- void *pctx, struct v4l2_fmtdesc *pfmtdesc)
-{
- D("%s\n", __func__);
- return 0;
-}
-
-static int msm_v4l2_enum_fmt_cap(struct file *f,
- void *pctx, struct v4l2_fmtdesc *pfmtdesc)
-{
- D("%s\n", __func__);
-
- switch (pfmtdesc->index) {
- case 0:
- pfmtdesc->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
- pfmtdesc->flags = 0;
- strncpy(pfmtdesc->description, "YUV 4:2:0",
- sizeof(pfmtdesc->description));
- pfmtdesc->pixelformat = V4L2_PIX_FMT_YVU420;
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int msm_v4l2_g_fmt_cap(struct file *f,
- void *pctx, struct v4l2_format *pfmt)
-{
- D("%s\n", __func__);
- pfmt->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
- pfmt->fmt.pix.width = MSM_V4L2_WIDTH;
- pfmt->fmt.pix.height = MSM_V4L2_HEIGHT;
- pfmt->fmt.pix.pixelformat = V4L2_PIX_FMT_YVU420;
- pfmt->fmt.pix.field = V4L2_FIELD_ANY;
- pfmt->fmt.pix.bytesperline = 0;
- pfmt->fmt.pix.sizeimage = 0;
- pfmt->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG;
- pfmt->fmt.pix.priv = 0;
- return 0;
-}
-
-static int msm_v4l2_s_fmt_cap(struct file *f,
- void *pctx, struct v4l2_format *pfmt)
-{
- struct msm_ctrl_cmd *ctrlcmd;
-
- D("%s\n", __func__);
-
- ctrlcmd = kmalloc(sizeof(struct msm_ctrl_cmd), GFP_ATOMIC);
- if (!ctrlcmd) {
- CDBG("msm_v4l2_s_fmt_cap: cannot allocate buffer\n");
- return -ENOMEM;
- }
-
- ctrlcmd->type = MSM_V4L2_VID_CAP_TYPE;
- ctrlcmd->length = sizeof(struct v4l2_format);
- ctrlcmd->value = pfmt;
- ctrlcmd->timeout_ms = 10000;
-
- if (pfmt->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
- kfree(ctrlcmd);
- return -1;
- }
-
-#if 0
- /* FIXEME */
- if (pfmt->fmt.pix.pixelformat != V4L2_PIX_FMT_YVU420) {
- kfree(ctrlcmd);
- return -EINVAL;
- }
-#endif
-
- /* Ok, but check other params, too. */
-
-#if 0
- memcpy(&g_pmsm_v4l2_dev->current_pix_format.fmt.pix, pfmt,
- sizeof(struct v4l2_format));
-#endif
-
- g_pmsm_v4l2_dev->drv->ctrl(g_pmsm_v4l2_dev->drv->sync, ctrlcmd);
-
- return 0;
-}
-
-static int msm_v4l2_g_fmt_overlay(struct file *f,
- void *pctx, struct v4l2_format *pfmt)
-{
- D("%s\n", __func__);
- pfmt->type = V4L2_BUF_TYPE_VIDEO_OVERLAY;
- pfmt->fmt.pix.width = MSM_V4L2_WIDTH;
- pfmt->fmt.pix.height = MSM_V4L2_HEIGHT;
- pfmt->fmt.pix.pixelformat = V4L2_PIX_FMT_YVU420;
- pfmt->fmt.pix.field = V4L2_FIELD_ANY;
- pfmt->fmt.pix.bytesperline = 0;
- pfmt->fmt.pix.sizeimage = 0;
- pfmt->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG;
- pfmt->fmt.pix.priv = 0;
- return 0;
-}
-
-static int msm_v4l2_s_fmt_overlay(struct file *f,
- void *pctx, struct v4l2_format *pfmt)
-{
- D("%s\n", __func__);
- return 0;
-}
-
-static int msm_v4l2_overlay(struct file *f, void *pctx, unsigned int i)
-{
- D("%s\n", __func__);
- return 0;
-}
-
-static int msm_v4l2_g_jpegcomp(struct file *f,
- void *pctx, struct v4l2_jpegcompression *pcomp)
-{
- D("%s\n", __func__);
- return 0;
-}
-
-static int msm_v4l2_s_jpegcomp(struct file *f,
- void *pctx, struct v4l2_jpegcompression *pcomp)
-{
- D("%s\n", __func__);
- return 0;
-}
-
-#ifdef CONFIG_PROC_FS
-int msm_v4l2_read_proc(char *pbuf, char **start, off_t offset,
- int count, int *eof, void *data)
-{
- int len = 0;
- len += snprintf(pbuf, strlen("stats\n") + 1, "stats\n");
-
- if (g_pmsm_v4l2_dev) {
- len += snprintf(pbuf, strlen("mode: ") + 1, "mode: ");
-
- if (g_pmsm_v4l2_dev->current_cap_format.type
- == V4L2_BUF_TYPE_VIDEO_CAPTURE)
- len += snprintf(pbuf, strlen("capture\n") + 1,
- "capture\n");
- else
- len += snprintf(pbuf, strlen("unknown\n") + 1,
- "unknown\n");
-
- len += snprintf(pbuf, 21, "resolution: %dx%d\n",
- g_pmsm_v4l2_dev->current_cap_format.fmt.pix.
- width,
- g_pmsm_v4l2_dev->current_cap_format.fmt.pix.
- height);
-
- len += snprintf(pbuf,
- strlen("pixel format: ") + 1, "pixel format: ");
- if (g_pmsm_v4l2_dev->current_cap_format.fmt.pix.pixelformat
- == V4L2_PIX_FMT_YVU420)
- len += snprintf(pbuf, strlen("yvu420\n") + 1,
- "yvu420\n");
- else
- len += snprintf(pbuf, strlen("unknown\n") + 1,
- "unknown\n");
-
- len += snprintf(pbuf, strlen("colorspace: ") + 1,
- "colorspace: ");
- if (g_pmsm_v4l2_dev->current_cap_format.fmt.pix.colorspace
- == V4L2_COLORSPACE_JPEG)
- len += snprintf(pbuf, strlen("jpeg\n") + 1, "jpeg\n");
- else
- len += snprintf(pbuf, strlen("unknown\n") + 1,
- "unknown\n");
- }
-
- *eof = 1;
- return len;
-}
-#endif
-
-static const struct v4l2_file_operations msm_v4l2_fops = {
- .owner = THIS_MODULE,
- .open = msm_v4l2_open,
- .poll = msm_v4l2_poll,
- .release = msm_v4l2_release,
- .ioctl = msm_v4l2_ioctl,
-};
-
-static void msm_v4l2_dev_init(struct msm_v4l2_device *pmsm_v4l2_dev)
-{
- pmsm_v4l2_dev->read_queue_lock =
- __SPIN_LOCK_UNLOCKED(pmsm_v4l2_dev->read_queue_lock);
- INIT_LIST_HEAD(&pmsm_v4l2_dev->read_queue);
-}
-
-static int msm_v4l2_try_fmt_cap(struct file *file,
- void *fh, struct v4l2_format *f)
-{
- /* FIXME */
- return 0;
-}
-
-static int mm_v4l2_try_fmt_type_private(struct file *file,
- void *fh, struct v4l2_format *f)
-{
- /* FIXME */
- return 0;
-}
-
-/*
- * should the following structure be used instead of the code in the function?
- * static const struct v4l2_ioctl_ops msm_v4l2_ioctl_ops = {
- * .vidioc_querycap = ....
- * }
- */
-static const struct v4l2_ioctl_ops msm_ioctl_ops = {
- .vidioc_querycap = msm_v4l2_querycap,
- .vidioc_s_std = msm_v4l2_s_std,
-
- .vidioc_queryctrl = msm_v4l2_queryctrl,
- .vidioc_g_ctrl = msm_v4l2_g_ctrl,
- .vidioc_s_ctrl = msm_v4l2_s_ctrl,
-
- .vidioc_reqbufs = msm_v4l2_reqbufs,
- .vidioc_querybuf = msm_v4l2_querybuf,
- .vidioc_qbuf = msm_v4l2_qbuf,
- .vidioc_dqbuf = msm_v4l2_dqbuf,
-
- .vidioc_streamon = msm_v4l2_streamon,
- .vidioc_streamoff = msm_v4l2_streamoff,
-
- .vidioc_enum_fmt_vid_overlay = msm_v4l2_enum_fmt_overlay,
- .vidioc_enum_fmt_vid_cap = msm_v4l2_enum_fmt_cap,
-
- .vidioc_try_fmt_vid_cap = msm_v4l2_try_fmt_cap,
- .vidioc_try_fmt_type_private = mm_v4l2_try_fmt_type_private,
-
- .vidioc_g_fmt_vid_cap = msm_v4l2_g_fmt_cap,
- .vidioc_s_fmt_vid_cap = msm_v4l2_s_fmt_cap,
- .vidioc_g_fmt_vid_overlay = msm_v4l2_g_fmt_overlay,
- .vidioc_s_fmt_vid_overlay = msm_v4l2_s_fmt_overlay,
- .vidioc_overlay = msm_v4l2_overlay,
-
- .vidioc_g_jpegcomp = msm_v4l2_g_jpegcomp,
- .vidioc_s_jpegcomp = msm_v4l2_s_jpegcomp,
-};
-
-static int msm_v4l2_video_dev_init(struct video_device *pvd)
-{
- strncpy(pvd->name, MSM_APPS_ID_V4L2, sizeof(pvd->name));
- pvd->vfl_type = 1;
- pvd->fops = &msm_v4l2_fops;
- pvd->release = msm_v4l2_release_dev;
- pvd->minor = -1;
- pvd->ioctl_ops = &msm_ioctl_ops;
- return msm_v4l2_register(g_pmsm_v4l2_dev->drv);
-}
-
-static int __init msm_v4l2_init(void)
-{
- int rc = -ENOMEM;
- struct video_device *pvdev = NULL;
- struct msm_v4l2_device *pmsm_v4l2_dev = NULL;
- D("%s\n", __func__);
-
- pvdev = video_device_alloc();
- if (pvdev == NULL)
- return rc;
-
- pmsm_v4l2_dev =
- kzalloc(sizeof(struct msm_v4l2_device), GFP_KERNEL);
- if (pmsm_v4l2_dev == NULL) {
- video_device_release(pvdev);
- return rc;
- }
-
- msm_v4l2_dev_init(pmsm_v4l2_dev);
-
- g_pmsm_v4l2_dev = pmsm_v4l2_dev;
- g_pmsm_v4l2_dev->pvdev = pvdev;
-
- g_pmsm_v4l2_dev->drv =
- kzalloc(sizeof(struct msm_v4l2_driver), GFP_KERNEL);
- if (!g_pmsm_v4l2_dev->drv) {
- video_device_release(pvdev);
- kfree(pmsm_v4l2_dev);
- return rc;
- }
-
- rc = msm_v4l2_video_dev_init(pvdev);
- if (rc < 0) {
- video_device_release(pvdev);
- kfree(g_pmsm_v4l2_dev->drv);
- kfree(pmsm_v4l2_dev);
- return rc;
- }
-
- if (video_register_device(pvdev, VFL_TYPE_GRABBER,
- MSM_V4L2_DEVNUM_YUV)) {
- D("failed to register device\n");
- video_device_release(pvdev);
- kfree(g_pmsm_v4l2_dev);
- g_pmsm_v4l2_dev = NULL;
- return -ENOENT;
- }
-#ifdef CONFIG_PROC_FS
- create_proc_read_entry(MSM_V4L2_PROC_NAME,
- 0, NULL, msm_v4l2_read_proc, NULL);
-#endif
-
- return 0;
-}
-
-static void __exit msm_v4l2_exit(void)
-{
- struct video_device *pvdev = g_pmsm_v4l2_dev->pvdev;
- D("%s\n", __func__);
-#ifdef CONFIG_PROC_FS
- remove_proc_entry(MSM_V4L2_PROC_NAME, NULL);
-#endif
- video_unregister_device(pvdev);
- video_device_release(pvdev);
-
- msm_v4l2_unregister(g_pmsm_v4l2_dev->drv);
-
- kfree(g_pmsm_v4l2_dev->drv);
- g_pmsm_v4l2_dev->drv = NULL;
-
- kfree(g_pmsm_v4l2_dev);
- g_pmsm_v4l2_dev = NULL;
-}
-
-module_init(msm_v4l2_init);
-module_exit(msm_v4l2_exit);
-
-MODULE_DESCRIPTION("MSM V4L2 driver");
-MODULE_LICENSE("GPL v2");
diff --git a/trunk/drivers/staging/dream/camera/msm_vfe7x.c b/trunk/drivers/staging/dream/camera/msm_vfe7x.c
deleted file mode 100644
index 198656ac3de5..000000000000
--- a/trunk/drivers/staging/dream/camera/msm_vfe7x.c
+++ /dev/null
@@ -1,702 +0,0 @@
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include "msm_vfe7x.h"
-
-#define QDSP_CMDQUEUE QDSP_vfeCommandQueue
-
-#define VFE_RESET_CMD 0
-#define VFE_START_CMD 1
-#define VFE_STOP_CMD 2
-#define VFE_FRAME_ACK 20
-#define STATS_AF_ACK 21
-#define STATS_WE_ACK 22
-
-#define MSG_STOP_ACK 1
-#define MSG_SNAPSHOT 2
-#define MSG_OUTPUT1 6
-#define MSG_OUTPUT2 7
-#define MSG_STATS_AF 8
-#define MSG_STATS_WE 9
-
-static struct msm_adsp_module *qcam_mod;
-static struct msm_adsp_module *vfe_mod;
-static struct msm_vfe_callback *resp;
-static void *extdata;
-static uint32_t extlen;
-
-struct mutex vfe_lock;
-static void *vfe_syncdata;
-static uint8_t vfestopped;
-
-static struct stop_event stopevent;
-
-static void vfe_7x_convert(struct msm_vfe_phy_info *pinfo,
- enum vfe_resp_msg type,
- void *data, void **ext, int32_t *elen)
-{
- switch (type) {
- case VFE_MSG_OUTPUT1:
- case VFE_MSG_OUTPUT2: {
- pinfo->y_phy = ((struct vfe_endframe *)data)->y_address;
- pinfo->cbcr_phy =
- ((struct vfe_endframe *)data)->cbcr_address;
-
- CDBG("vfe_7x_convert, y_phy = 0x%x, cbcr_phy = 0x%x\n",
- pinfo->y_phy, pinfo->cbcr_phy);
-
- ((struct vfe_frame_extra *)extdata)->bl_evencol =
- ((struct vfe_endframe *)data)->blacklevelevencolumn;
-
- ((struct vfe_frame_extra *)extdata)->bl_oddcol =
- ((struct vfe_endframe *)data)->blackleveloddcolumn;
-
- ((struct vfe_frame_extra *)extdata)->g_def_p_cnt =
- ((struct vfe_endframe *)data)->greendefectpixelcount;
-
- ((struct vfe_frame_extra *)extdata)->r_b_def_p_cnt =
- ((struct vfe_endframe *)data)->redbluedefectpixelcount;
-
- *ext = extdata;
- *elen = extlen;
- }
- break;
-
- case VFE_MSG_STATS_AF:
- case VFE_MSG_STATS_WE:
- pinfo->sbuf_phy = *(uint32_t *)data;
- break;
-
- default:
- break;
- } /* switch */
-}
-
-static void vfe_7x_ops(void *driver_data, unsigned id, size_t len,
- void (*getevent)(void *ptr, size_t len))
-{
- uint32_t evt_buf[3];
- struct msm_vfe_resp *rp;
- void *data;
-
- len = (id == (uint16_t)-1) ? 0 : len;
- data = resp->vfe_alloc(sizeof(struct msm_vfe_resp) + len, vfe_syncdata);
-
- if (!data) {
- pr_err("rp: cannot allocate buffer\n");
- return;
- }
- rp = (struct msm_vfe_resp *)data;
- rp->evt_msg.len = len;
-
- if (id == ((uint16_t)-1)) {
- /* event */
- rp->type = VFE_EVENT;
- rp->evt_msg.type = MSM_CAMERA_EVT;
- getevent(evt_buf, sizeof(evt_buf));
- rp->evt_msg.msg_id = evt_buf[0];
- resp->vfe_resp(rp, MSM_CAM_Q_VFE_EVT, vfe_syncdata);
- } else {
- /* messages */
- rp->evt_msg.type = MSM_CAMERA_MSG;
- rp->evt_msg.msg_id = id;
- rp->evt_msg.data = rp + 1;
- getevent(rp->evt_msg.data, len);
-
- switch (rp->evt_msg.msg_id) {
- case MSG_SNAPSHOT:
- rp->type = VFE_MSG_SNAPSHOT;
- break;
-
- case MSG_OUTPUT1:
- rp->type = VFE_MSG_OUTPUT1;
- vfe_7x_convert(&(rp->phy), VFE_MSG_OUTPUT1,
- rp->evt_msg.data, &(rp->extdata),
- &(rp->extlen));
- break;
-
- case MSG_OUTPUT2:
- rp->type = VFE_MSG_OUTPUT2;
- vfe_7x_convert(&(rp->phy), VFE_MSG_OUTPUT2,
- rp->evt_msg.data, &(rp->extdata),
- &(rp->extlen));
- break;
-
- case MSG_STATS_AF:
- rp->type = VFE_MSG_STATS_AF;
- vfe_7x_convert(&(rp->phy), VFE_MSG_STATS_AF,
- rp->evt_msg.data, NULL, NULL);
- break;
-
- case MSG_STATS_WE:
- rp->type = VFE_MSG_STATS_WE;
- vfe_7x_convert(&(rp->phy), VFE_MSG_STATS_WE,
- rp->evt_msg.data, NULL, NULL);
-
- CDBG("MSG_STATS_WE: phy = 0x%x\n", rp->phy.sbuf_phy);
- break;
-
- case MSG_STOP_ACK:
- rp->type = VFE_MSG_GENERAL;
- stopevent.state = 1;
- wake_up(&stopevent.wait);
- break;
-
-
- default:
- rp->type = VFE_MSG_GENERAL;
- break;
- }
- resp->vfe_resp(rp, MSM_CAM_Q_VFE_MSG, vfe_syncdata);
- }
-}
-
-static struct msm_adsp_ops vfe_7x_sync = {
- .event = vfe_7x_ops,
-};
-
-static int vfe_7x_enable(struct camera_enable_cmd *enable)
-{
- int rc = -EFAULT;
-
- if (!strcmp(enable->name, "QCAMTASK"))
- rc = msm_adsp_enable(qcam_mod);
- else if (!strcmp(enable->name, "VFETASK"))
- rc = msm_adsp_enable(vfe_mod);
-
- return rc;
-}
-
-static int vfe_7x_disable(struct camera_enable_cmd *enable,
- struct platform_device *dev __attribute__((unused)))
-{
- int rc = -EFAULT;
-
- if (!strcmp(enable->name, "QCAMTASK"))
- rc = msm_adsp_disable(qcam_mod);
- else if (!strcmp(enable->name, "VFETASK"))
- rc = msm_adsp_disable(vfe_mod);
-
- return rc;
-}
-
-static int vfe_7x_stop(void)
-{
- int rc = 0;
- uint32_t stopcmd = VFE_STOP_CMD;
- rc = msm_adsp_write(vfe_mod, QDSP_CMDQUEUE,
- &stopcmd, sizeof(uint32_t));
- if (rc < 0) {
- CDBG("%s:%d: failed rc = %d \n", __func__, __LINE__, rc);
- return rc;
- }
-
- stopevent.state = 0;
- rc = wait_event_timeout(stopevent.wait,
- stopevent.state != 0,
- msecs_to_jiffies(stopevent.timeout));
-
- return rc;
-}
-
-static void vfe_7x_release(struct platform_device *pdev)
-{
- mutex_lock(&vfe_lock);
- vfe_syncdata = NULL;
- mutex_unlock(&vfe_lock);
-
- if (!vfestopped) {
- CDBG("%s:%d:Calling vfe_7x_stop()\n", __func__, __LINE__);
- vfe_7x_stop();
- } else
- vfestopped = 0;
-
- msm_adsp_disable(qcam_mod);
- msm_adsp_disable(vfe_mod);
-
- msm_adsp_put(qcam_mod);
- msm_adsp_put(vfe_mod);
-
- msm_camio_disable(pdev);
-
- kfree(extdata);
- extlen = 0;
-}
-
-static int vfe_7x_init(struct msm_vfe_callback *presp,
- struct platform_device *dev)
-{
- int rc = 0;
-
- init_waitqueue_head(&stopevent.wait);
- stopevent.timeout = 200;
- stopevent.state = 0;
-
- if (presp && presp->vfe_resp)
- resp = presp;
- else
- return -EFAULT;
-
- /* Bring up all the required GPIOs and Clocks */
- rc = msm_camio_enable(dev);
- if (rc < 0)
- return rc;
-
- msm_camio_camif_pad_reg_reset();
-
- extlen = sizeof(struct vfe_frame_extra);
-
- extdata = kmalloc(extlen, GFP_ATOMIC);
- if (!extdata) {
- rc = -ENOMEM;
- goto init_fail;
- }
-
- rc = msm_adsp_get("QCAMTASK", &qcam_mod, &vfe_7x_sync, NULL);
- if (rc) {
- rc = -EBUSY;
- goto get_qcam_fail;
- }
-
- rc = msm_adsp_get("VFETASK", &vfe_mod, &vfe_7x_sync, NULL);
- if (rc) {
- rc = -EBUSY;
- goto get_vfe_fail;
- }
-
- return 0;
-
-get_vfe_fail:
- msm_adsp_put(qcam_mod);
-get_qcam_fail:
- kfree(extdata);
-init_fail:
- extlen = 0;
- return rc;
-}
-
-static int vfe_7x_config_axi(int mode,
- struct axidata *ad, struct axiout *ao)
-{
- struct msm_pmem_region *regptr;
- unsigned long *bptr;
- int cnt;
-
- int rc = 0;
-
- if (mode == OUTPUT_1 || mode == OUTPUT_1_AND_2) {
- regptr = ad->region;
-
- CDBG("bufnum1 = %d\n", ad->bufnum1);
- CDBG("config_axi1: O1, phy = 0x%lx, y_off = %d, cbcr_off =%d\n",
- regptr->paddr, regptr->y_off, regptr->cbcr_off);
-
- bptr = &ao->output1buffer1_y_phy;
- for (cnt = 0; cnt < ad->bufnum1; cnt++) {
- *bptr = regptr->paddr + regptr->y_off;
- bptr++;
- *bptr = regptr->paddr + regptr->cbcr_off;
-
- bptr++;
- regptr++;
- }
-
- regptr--;
- for (cnt = 0; cnt < (8 - ad->bufnum1); cnt++) {
- *bptr = regptr->paddr + regptr->y_off;
- bptr++;
- *bptr = regptr->paddr + regptr->cbcr_off;
- bptr++;
- }
- } /* if OUTPUT1 or Both */
-
- if (mode == OUTPUT_2 || mode == OUTPUT_1_AND_2) {
- regptr = &(ad->region[ad->bufnum1]);
-
- CDBG("bufnum2 = %d\n", ad->bufnum2);
- CDBG("config_axi2: O2, phy = 0x%lx, y_off = %d, cbcr_off =%d\n",
- regptr->paddr, regptr->y_off, regptr->cbcr_off);
-
- bptr = &ao->output2buffer1_y_phy;
- for (cnt = 0; cnt < ad->bufnum2; cnt++) {
- *bptr = regptr->paddr + regptr->y_off;
- bptr++;
- *bptr = regptr->paddr + regptr->cbcr_off;
-
- bptr++;
- regptr++;
- }
-
- regptr--;
- for (cnt = 0; cnt < (8 - ad->bufnum2); cnt++) {
- *bptr = regptr->paddr + regptr->y_off;
- bptr++;
- *bptr = regptr->paddr + regptr->cbcr_off;
- bptr++;
- }
- }
-
- return rc;
-}
-
-static int vfe_7x_config(struct msm_vfe_cfg_cmd *cmd, void *data)
-{
- struct msm_pmem_region *regptr;
- unsigned char buf[256];
-
- struct vfe_stats_ack sack;
- struct axidata *axid;
- uint32_t i;
-
- struct vfe_stats_we_cfg *scfg = NULL;
- struct vfe_stats_af_cfg *sfcfg = NULL;
-
- struct axiout *axio = NULL;
- void *cmd_data = NULL;
- void *cmd_data_alloc = NULL;
- long rc = 0;
- struct msm_vfe_command_7k *vfecmd;
-
- vfecmd =
- kmalloc(sizeof(struct msm_vfe_command_7k),
- GFP_ATOMIC);
- if (!vfecmd) {
- pr_err("vfecmd alloc failed!\n");
- return -ENOMEM;
- }
-
- if (cmd->cmd_type != CMD_FRAME_BUF_RELEASE &&
- cmd->cmd_type != CMD_STATS_BUF_RELEASE &&
- cmd->cmd_type != CMD_STATS_AF_BUF_RELEASE) {
- if (copy_from_user(vfecmd,
- (void __user *)(cmd->value),
- sizeof(struct msm_vfe_command_7k))) {
- rc = -EFAULT;
- goto config_failure;
- }
- }
-
- switch (cmd->cmd_type) {
- case CMD_STATS_ENABLE:
- case CMD_STATS_AXI_CFG: {
- axid = data;
- if (!axid) {
- rc = -EFAULT;
- goto config_failure;
- }
-
- scfg =
- kmalloc(sizeof(struct vfe_stats_we_cfg),
- GFP_ATOMIC);
- if (!scfg) {
- rc = -ENOMEM;
- goto config_failure;
- }
-
- if (copy_from_user(scfg,
- (void __user *)(vfecmd->value),
- vfecmd->length)) {
-
- rc = -EFAULT;
- goto config_done;
- }
-
- CDBG("STATS_ENABLE: bufnum = %d, enabling = %d\n",
- axid->bufnum1, scfg->wb_expstatsenable);
-
- if (axid->bufnum1 > 0) {
- regptr = axid->region;
-
- for (i = 0; i < axid->bufnum1; i++) {
-
- CDBG("STATS_ENABLE, phy = 0x%lx\n",
- regptr->paddr);
-
- scfg->wb_expstatoutputbuffer[i] =
- (void *)regptr->paddr;
- regptr++;
- }
-
- cmd_data = scfg;
-
- } else {
- rc = -EINVAL;
- goto config_done;
- }
- }
- break;
-
- case CMD_STATS_AF_ENABLE:
- case CMD_STATS_AF_AXI_CFG: {
- axid = data;
- if (!axid) {
- rc = -EFAULT;
- goto config_failure;
- }
-
- sfcfg =
- kmalloc(sizeof(struct vfe_stats_af_cfg),
- GFP_ATOMIC);
-
- if (!sfcfg) {
- rc = -ENOMEM;
- goto config_failure;
- }
-
- if (copy_from_user(sfcfg,
- (void __user *)(vfecmd->value),
- vfecmd->length)) {
-
- rc = -EFAULT;
- goto config_done;
- }
-
- CDBG("AF_ENABLE: bufnum = %d, enabling = %d\n",
- axid->bufnum1, sfcfg->af_enable);
-
- if (axid->bufnum1 > 0) {
- regptr = axid->region;
-
- for (i = 0; i < axid->bufnum1; i++) {
-
- CDBG("STATS_ENABLE, phy = 0x%lx\n",
- regptr->paddr);
-
- sfcfg->af_outbuf[i] =
- (void *)regptr->paddr;
-
- regptr++;
- }
-
- cmd_data = sfcfg;
-
- } else {
- rc = -EINVAL;
- goto config_done;
- }
- }
- break;
-
- case CMD_FRAME_BUF_RELEASE: {
- struct msm_frame *b;
- unsigned long p;
- struct vfe_outputack fack;
- if (!data) {
- rc = -EFAULT;
- goto config_failure;
- }
-
- b = (struct msm_frame *)(cmd->value);
- p = *(unsigned long *)data;
-
- fack.header = VFE_FRAME_ACK;
-
- fack.output2newybufferaddress =
- (void *)(p + b->y_off);
-
- fack.output2newcbcrbufferaddress =
- (void *)(p + b->cbcr_off);
-
- vfecmd->queue = QDSP_CMDQUEUE;
- vfecmd->length = sizeof(struct vfe_outputack);
- cmd_data = &fack;
- }
- break;
-
- case CMD_SNAP_BUF_RELEASE:
- break;
-
- case CMD_STATS_BUF_RELEASE: {
- CDBG("vfe_7x_config: CMD_STATS_BUF_RELEASE\n");
- if (!data) {
- rc = -EFAULT;
- goto config_failure;
- }
-
- sack.header = STATS_WE_ACK;
- sack.bufaddr = (void *)*(uint32_t *)data;
-
- vfecmd->queue = QDSP_CMDQUEUE;
- vfecmd->length = sizeof(struct vfe_stats_ack);
- cmd_data = &sack;
- }
- break;
-
- case CMD_STATS_AF_BUF_RELEASE: {
- CDBG("vfe_7x_config: CMD_STATS_AF_BUF_RELEASE\n");
- if (!data) {
- rc = -EFAULT;
- goto config_failure;
- }
-
- sack.header = STATS_AF_ACK;
- sack.bufaddr = (void *)*(uint32_t *)data;
-
- vfecmd->queue = QDSP_CMDQUEUE;
- vfecmd->length = sizeof(struct vfe_stats_ack);
- cmd_data = &sack;
- }
- break;
-
- case CMD_GENERAL:
- case CMD_STATS_DISABLE: {
- if (vfecmd->length > 256) {
- cmd_data_alloc =
- cmd_data = kmalloc(vfecmd->length, GFP_ATOMIC);
- if (!cmd_data) {
- rc = -ENOMEM;
- goto config_failure;
- }
- } else
- cmd_data = buf;
-
- if (copy_from_user(cmd_data,
- (void __user *)(vfecmd->value),
- vfecmd->length)) {
-
- rc = -EFAULT;
- goto config_done;
- }
-
- if (vfecmd->queue == QDSP_CMDQUEUE) {
- switch (*(uint32_t *)cmd_data) {
- case VFE_RESET_CMD:
- msm_camio_vfe_blk_reset();
- msm_camio_camif_pad_reg_reset_2();
- vfestopped = 0;
- break;
-
- case VFE_START_CMD:
- msm_camio_camif_pad_reg_reset_2();
- vfestopped = 0;
- break;
-
- case VFE_STOP_CMD:
- vfestopped = 1;
- goto config_send;
-
- default:
- break;
- }
- } /* QDSP_CMDQUEUE */
- }
- break;
-
- case CMD_AXI_CFG_OUT1: {
- axid = data;
- if (!axid) {
- rc = -EFAULT;
- goto config_failure;
- }
-
- axio = kmalloc(sizeof(struct axiout), GFP_ATOMIC);
- if (!axio) {
- rc = -ENOMEM;
- goto config_failure;
- }
-
- if (copy_from_user(axio, (void *)(vfecmd->value),
- sizeof(struct axiout))) {
- rc = -EFAULT;
- goto config_done;
- }
-
- vfe_7x_config_axi(OUTPUT_1, axid, axio);
-
- cmd_data = axio;
- }
- break;
-
- case CMD_AXI_CFG_OUT2:
- case CMD_RAW_PICT_AXI_CFG: {
- axid = data;
- if (!axid) {
- rc = -EFAULT;
- goto config_failure;
- }
-
- axio = kmalloc(sizeof(struct axiout), GFP_ATOMIC);
- if (!axio) {
- rc = -ENOMEM;
- goto config_failure;
- }
-
- if (copy_from_user(axio, (void __user *)(vfecmd->value),
- sizeof(struct axiout))) {
- rc = -EFAULT;
- goto config_done;
- }
-
- vfe_7x_config_axi(OUTPUT_2, axid, axio);
- cmd_data = axio;
- }
- break;
-
- case CMD_AXI_CFG_SNAP_O1_AND_O2: {
- axid = data;
- if (!axid) {
- rc = -EFAULT;
- goto config_failure;
- }
-
- axio = kmalloc(sizeof(struct axiout), GFP_ATOMIC);
- if (!axio) {
- rc = -ENOMEM;
- goto config_failure;
- }
-
- if (copy_from_user(axio, (void __user *)(vfecmd->value),
- sizeof(struct axiout))) {
- rc = -EFAULT;
- goto config_done;
- }
-
- vfe_7x_config_axi(OUTPUT_1_AND_2, axid, axio);
-
- cmd_data = axio;
- }
- break;
-
- default:
- break;
- } /* switch */
-
- if (vfestopped)
- goto config_done;
-
-config_send:
- CDBG("send adsp command = %d\n", *(uint32_t *)cmd_data);
- rc = msm_adsp_write(vfe_mod, vfecmd->queue,
- cmd_data, vfecmd->length);
-
-config_done:
- if (cmd_data_alloc != NULL)
- kfree(cmd_data_alloc);
-
-config_failure:
- kfree(scfg);
- kfree(axio);
- kfree(vfecmd);
- return rc;
-}
-
-void msm_camvfe_fn_init(struct msm_camvfe_fn *fptr, void *data)
-{
- mutex_init(&vfe_lock);
- fptr->vfe_init = vfe_7x_init;
- fptr->vfe_enable = vfe_7x_enable;
- fptr->vfe_config = vfe_7x_config;
- fptr->vfe_disable = vfe_7x_disable;
- fptr->vfe_release = vfe_7x_release;
- vfe_syncdata = data;
-}
diff --git a/trunk/drivers/staging/dream/camera/msm_vfe7x.h b/trunk/drivers/staging/dream/camera/msm_vfe7x.h
deleted file mode 100644
index be3e9ad8f524..000000000000
--- a/trunk/drivers/staging/dream/camera/msm_vfe7x.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-#ifndef __MSM_VFE7X_H__
-#define __MSM_VFE7X_H__
-#include
-#include
-
-struct vfe_frame_extra {
- uint32_t bl_evencol;
- uint32_t bl_oddcol;
- uint16_t g_def_p_cnt;
- uint16_t r_b_def_p_cnt;
-};
-
-struct vfe_endframe {
- uint32_t y_address;
- uint32_t cbcr_address;
-
- unsigned int blacklevelevencolumn:23;
- uint16_t reserved1:9;
- unsigned int blackleveloddcolumn:23;
- uint16_t reserved2:9;
-
- uint16_t greendefectpixelcount:8;
- uint16_t reserved3:8;
- uint16_t redbluedefectpixelcount:8;
- uint16_t reserved4:8;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_outputack {
- uint32_t header;
- void *output2newybufferaddress;
- void *output2newcbcrbufferaddress;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_stats_ack {
- uint32_t header;
- /* MUST BE 64 bit ALIGNED */
- void *bufaddr;
-} __attribute__((packed, aligned(4)));
-
-/* AXI Output Config Command sent to DSP */
-struct axiout {
- uint32_t cmdheader:32;
- int outputmode:3;
- uint8_t format:2;
- uint32_t /* reserved */ : 27;
-
- /* AXI Output 1 Y Configuration, Part 1 */
- uint32_t out1yimageheight:12;
- uint32_t /* reserved */ : 4;
- uint32_t out1yimagewidthin64bitwords:10;
- uint32_t /* reserved */ : 6;
-
- /* AXI Output 1 Y Configuration, Part 2 */
- uint8_t out1yburstlen:2;
- uint32_t out1ynumrows:12;
- uint32_t out1yrowincin64bitincs:12;
- uint32_t /* reserved */ : 6;
-
- /* AXI Output 1 CbCr Configuration, Part 1 */
- uint32_t out1cbcrimageheight:12;
- uint32_t /* reserved */ : 4;
- uint32_t out1cbcrimagewidthin64bitwords:10;
- uint32_t /* reserved */ : 6;
-
- /* AXI Output 1 CbCr Configuration, Part 2 */
- uint8_t out1cbcrburstlen:2;
- uint32_t out1cbcrnumrows:12;
- uint32_t out1cbcrrowincin64bitincs:12;
- uint32_t /* reserved */ : 6;
-
- /* AXI Output 2 Y Configuration, Part 1 */
- uint32_t out2yimageheight:12;
- uint32_t /* reserved */ : 4;
- uint32_t out2yimagewidthin64bitwords:10;
- uint32_t /* reserved */ : 6;
-
- /* AXI Output 2 Y Configuration, Part 2 */
- uint8_t out2yburstlen:2;
- uint32_t out2ynumrows:12;
- uint32_t out2yrowincin64bitincs:12;
- uint32_t /* reserved */ : 6;
-
- /* AXI Output 2 CbCr Configuration, Part 1 */
- uint32_t out2cbcrimageheight:12;
- uint32_t /* reserved */ : 4;
- uint32_t out2cbcrimagewidtein64bitwords:10;
- uint32_t /* reserved */ : 6;
-
- /* AXI Output 2 CbCr Configuration, Part 2 */
- uint8_t out2cbcrburstlen:2;
- uint32_t out2cbcrnumrows:12;
- uint32_t out2cbcrrowincin64bitincs:12;
- uint32_t /* reserved */ : 6;
-
- /* Address configuration:
- * output1 phisycal address */
- unsigned long output1buffer1_y_phy;
- unsigned long output1buffer1_cbcr_phy;
- unsigned long output1buffer2_y_phy;
- unsigned long output1buffer2_cbcr_phy;
- unsigned long output1buffer3_y_phy;
- unsigned long output1buffer3_cbcr_phy;
- unsigned long output1buffer4_y_phy;
- unsigned long output1buffer4_cbcr_phy;
- unsigned long output1buffer5_y_phy;
- unsigned long output1buffer5_cbcr_phy;
- unsigned long output1buffer6_y_phy;
- unsigned long output1buffer6_cbcr_phy;
- unsigned long output1buffer7_y_phy;
- unsigned long output1buffer7_cbcr_phy;
- unsigned long output1buffer8_y_phy;
- unsigned long output1buffer8_cbcr_phy;
-
- /* output2 phisycal address */
- unsigned long output2buffer1_y_phy;
- unsigned long output2buffer1_cbcr_phy;
- unsigned long output2buffer2_y_phy;
- unsigned long output2buffer2_cbcr_phy;
- unsigned long output2buffer3_y_phy;
- unsigned long output2buffer3_cbcr_phy;
- unsigned long output2buffer4_y_phy;
- unsigned long output2buffer4_cbcr_phy;
- unsigned long output2buffer5_y_phy;
- unsigned long output2buffer5_cbcr_phy;
- unsigned long output2buffer6_y_phy;
- unsigned long output2buffer6_cbcr_phy;
- unsigned long output2buffer7_y_phy;
- unsigned long output2buffer7_cbcr_phy;
- unsigned long output2buffer8_y_phy;
- unsigned long output2buffer8_cbcr_phy;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_stats_we_cfg {
- uint32_t header;
-
- /* White Balance/Exposure Statistic Selection */
- uint8_t wb_expstatsenable:1;
- uint8_t wb_expstatbuspriorityselection:1;
- unsigned int wb_expstatbuspriorityvalue:4;
- unsigned int /* reserved */ : 26;
-
- /* White Balance/Exposure Statistic Configuration, Part 1 */
- uint8_t exposurestatregions:1;
- uint8_t exposurestatsubregions:1;
- unsigned int /* reserved */ : 14;
-
- unsigned int whitebalanceminimumy:8;
- unsigned int whitebalancemaximumy:8;
-
- /* White Balance/Exposure Statistic Configuration, Part 2 */
- uint8_t wb_expstatslopeofneutralregionline[
- NUM_WB_EXP_NEUTRAL_REGION_LINES];
-
- /* White Balance/Exposure Statistic Configuration, Part 3 */
- unsigned int wb_expstatcrinterceptofneutralregionline2:12;
- unsigned int /* reserved */ : 4;
- unsigned int wb_expstatcbinterceptofneutralreginnline1:12;
- unsigned int /* reserved */ : 4;
-
- /* White Balance/Exposure Statistic Configuration, Part 4 */
- unsigned int wb_expstatcrinterceptofneutralregionline4:12;
- unsigned int /* reserved */ : 4;
- unsigned int wb_expstatcbinterceptofneutralregionline3:12;
- unsigned int /* reserved */ : 4;
-
- /* White Balance/Exposure Statistic Output Buffer Header */
- unsigned int wb_expmetricheaderpattern:8;
- unsigned int /* reserved */ : 24;
-
- /* White Balance/Exposure Statistic Output Buffers-MUST
- * BE 64 bit ALIGNED */
- void *wb_expstatoutputbuffer[NUM_WB_EXP_STAT_OUTPUT_BUFFERS];
-} __attribute__((packed, aligned(4)));
-
-struct vfe_stats_af_cfg {
- uint32_t header;
-
- /* Autofocus Statistic Selection */
- uint8_t af_enable:1;
- uint8_t af_busprioritysel:1;
- unsigned int af_buspriorityval:4;
- unsigned int /* reserved */ : 26;
-
- /* Autofocus Statistic Configuration, Part 1 */
- unsigned int af_singlewinvoffset:12;
- unsigned int /* reserved */ : 4;
- unsigned int af_singlewinhoffset:12;
- unsigned int /* reserved */ : 3;
- uint8_t af_winmode:1;
-
- /* Autofocus Statistic Configuration, Part 2 */
- unsigned int af_singglewinvh:11;
- unsigned int /* reserved */ : 5;
- unsigned int af_singlewinhw:11;
- unsigned int /* reserved */ : 5;
-
- /* Autofocus Statistic Configuration, Parts 3-6 */
- uint8_t af_multiwingrid[NUM_AUTOFOCUS_MULTI_WINDOW_GRIDS];
-
- /* Autofocus Statistic Configuration, Part 7 */
- signed int af_metrichpfcoefa00:5;
- signed int af_metrichpfcoefa04:5;
- unsigned int af_metricmaxval:11;
- uint8_t af_metricsel:1;
- unsigned int /* reserved */ : 10;
-
- /* Autofocus Statistic Configuration, Part 8 */
- signed int af_metrichpfcoefa20:5;
- signed int af_metrichpfcoefa21:5;
- signed int af_metrichpfcoefa22:5;
- signed int af_metrichpfcoefa23:5;
- signed int af_metrichpfcoefa24:5;
- unsigned int /* reserved */ : 7;
-
- /* Autofocus Statistic Output Buffer Header */
- unsigned int af_metrichp:8;
- unsigned int /* reserved */ : 24;
-
- /* Autofocus Statistic Output Buffers - MUST BE 64 bit ALIGNED!!! */
- void *af_outbuf[NUM_AF_STAT_OUTPUT_BUFFERS];
-} __attribute__((packed, aligned(4))); /* VFE_StatsAutofocusConfigCmdType */
-
-struct msm_camera_frame_msg {
- unsigned long output_y_address;
- unsigned long output_cbcr_address;
-
- unsigned int blacklevelevenColumn:23;
- uint16_t reserved1:9;
- unsigned int blackleveloddColumn:23;
- uint16_t reserved2:9;
-
- uint16_t greendefectpixelcount:8;
- uint16_t reserved3:8;
- uint16_t redbluedefectpixelcount:8;
- uint16_t reserved4:8;
-} __attribute__((packed, aligned(4)));
-
-/* New one for 7k */
-struct msm_vfe_command_7k {
- uint16_t queue;
- uint16_t length;
- void *value;
-};
-
-struct stop_event {
- wait_queue_head_t wait;
- int state;
- int timeout;
-};
-
-
-#endif /* __MSM_VFE7X_H__ */
diff --git a/trunk/drivers/staging/dream/camera/msm_vfe8x.c b/trunk/drivers/staging/dream/camera/msm_vfe8x.c
deleted file mode 100644
index d87d56f914de..000000000000
--- a/trunk/drivers/staging/dream/camera/msm_vfe8x.c
+++ /dev/null
@@ -1,736 +0,0 @@
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-#include
-#include
-#include
-#include
-#include "msm_vfe8x_proc.h"
-
-#define ON 1
-#define OFF 0
-
-struct mutex vfe_lock;
-static void *vfe_syncdata;
-
-static int vfe_enable(struct camera_enable_cmd *enable)
-{
- int rc = 0;
- return rc;
-}
-
-static int vfe_disable(struct camera_enable_cmd *enable,
- struct platform_device *dev)
-{
- int rc = 0;
-
- vfe_stop();
-
- msm_camio_disable(dev);
- return rc;
-}
-
-static void vfe_release(struct platform_device *dev)
-{
- msm_camio_disable(dev);
- vfe_cmd_release(dev);
-
- mutex_lock(&vfe_lock);
- vfe_syncdata = NULL;
- mutex_unlock(&vfe_lock);
-}
-
-static void vfe_config_axi(int mode,
- struct axidata *ad, struct vfe_cmd_axi_output_config *ao)
-{
- struct msm_pmem_region *regptr;
- int i, j;
- uint32_t *p1, *p2;
-
- if (mode == OUTPUT_1 || mode == OUTPUT_1_AND_2) {
- regptr = ad->region;
- for (i = 0;
- i < ad->bufnum1; i++) {
-
- p1 = &(ao->output1.outputY.outFragments[i][0]);
- p2 = &(ao->output1.outputCbcr.outFragments[i][0]);
-
- for (j = 0;
- j < ao->output1.fragmentCount; j++) {
-
- *p1 = regptr->paddr + regptr->y_off;
- p1++;
-
- *p2 = regptr->paddr + regptr->cbcr_off;
- p2++;
- }
- regptr++;
- }
- } /* if OUTPUT1 or Both */
-
- if (mode == OUTPUT_2 || mode == OUTPUT_1_AND_2) {
-
- regptr = &(ad->region[ad->bufnum1]);
- CDBG("bufnum2 = %d\n", ad->bufnum2);
-
- for (i = 0;
- i < ad->bufnum2; i++) {
-
- p1 = &(ao->output2.outputY.outFragments[i][0]);
- p2 = &(ao->output2.outputCbcr.outFragments[i][0]);
-
- CDBG("config_axi: O2, phy = 0x%lx, y_off = %d, cbcr_off = %d\n",
- regptr->paddr, regptr->y_off, regptr->cbcr_off);
-
- for (j = 0;
- j < ao->output2.fragmentCount; j++) {
-
- *p1 = regptr->paddr + regptr->y_off;
- CDBG("vfe_config_axi: p1 = 0x%x\n", *p1);
- p1++;
-
- *p2 = regptr->paddr + regptr->cbcr_off;
- CDBG("vfe_config_axi: p2 = 0x%x\n", *p2);
- p2++;
- }
- regptr++;
- }
- }
-}
-
-static int vfe_proc_general(struct msm_vfe_command_8k *cmd)
-{
- int rc = 0;
-
- CDBG("vfe_proc_general: cmdID = %d\n", cmd->id);
-
- switch (cmd->id) {
- case VFE_CMD_ID_RESET:
- msm_camio_vfe_blk_reset();
- msm_camio_camif_pad_reg_reset_2();
- vfe_reset();
- break;
-
- case VFE_CMD_ID_START: {
- struct vfe_cmd_start start;
- if (copy_from_user(&start,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- /* msm_camio_camif_pad_reg_reset_2(); */
- msm_camio_camif_pad_reg_reset();
- vfe_start(&start);
- }
- break;
-
- case VFE_CMD_ID_CAMIF_CONFIG: {
- struct vfe_cmd_camif_config camif;
- if (copy_from_user(&camif,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_camif_config(&camif);
- }
- break;
-
- case VFE_CMD_ID_BLACK_LEVEL_CONFIG: {
- struct vfe_cmd_black_level_config bl;
- if (copy_from_user(&bl,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_black_level_config(&bl);
- }
- break;
-
- case VFE_CMD_ID_ROLL_OFF_CONFIG: {
- struct vfe_cmd_roll_off_config rolloff;
- if (copy_from_user(&rolloff,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_roll_off_config(&rolloff);
- }
- break;
-
- case VFE_CMD_ID_DEMUX_CHANNEL_GAIN_CONFIG: {
- struct vfe_cmd_demux_channel_gain_config demuxc;
- if (copy_from_user(&demuxc,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- /* demux is always enabled. */
- vfe_demux_channel_gain_config(&demuxc);
- }
- break;
-
- case VFE_CMD_ID_DEMOSAIC_CONFIG: {
- struct vfe_cmd_demosaic_config demosaic;
- if (copy_from_user(&demosaic,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_demosaic_config(&demosaic);
- }
- break;
-
- case VFE_CMD_ID_FOV_CROP_CONFIG:
- case VFE_CMD_ID_FOV_CROP_UPDATE: {
- struct vfe_cmd_fov_crop_config fov;
- if (copy_from_user(&fov,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_fov_crop_config(&fov);
- }
- break;
-
- case VFE_CMD_ID_MAIN_SCALER_CONFIG:
- case VFE_CMD_ID_MAIN_SCALER_UPDATE: {
- struct vfe_cmd_main_scaler_config mainds;
- if (copy_from_user(&mainds,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_main_scaler_config(&mainds);
- }
- break;
-
- case VFE_CMD_ID_WHITE_BALANCE_CONFIG:
- case VFE_CMD_ID_WHITE_BALANCE_UPDATE: {
- struct vfe_cmd_white_balance_config wb;
- if (copy_from_user(&wb,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_white_balance_config(&wb);
- }
- break;
-
- case VFE_CMD_ID_COLOR_CORRECTION_CONFIG:
- case VFE_CMD_ID_COLOR_CORRECTION_UPDATE: {
- struct vfe_cmd_color_correction_config cc;
- if (copy_from_user(&cc,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_color_correction_config(&cc);
- }
- break;
-
- case VFE_CMD_ID_LA_CONFIG: {
- struct vfe_cmd_la_config la;
- if (copy_from_user(&la,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_la_config(&la);
- }
- break;
-
- case VFE_CMD_ID_RGB_GAMMA_CONFIG: {
- struct vfe_cmd_rgb_gamma_config rgb;
- if (copy_from_user(&rgb,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- rc = vfe_rgb_gamma_config(&rgb);
- }
- break;
-
- case VFE_CMD_ID_CHROMA_ENHAN_CONFIG:
- case VFE_CMD_ID_CHROMA_ENHAN_UPDATE: {
- struct vfe_cmd_chroma_enhan_config chrom;
- if (copy_from_user(&chrom,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_chroma_enhan_config(&chrom);
- }
- break;
-
- case VFE_CMD_ID_CHROMA_SUPPRESSION_CONFIG:
- case VFE_CMD_ID_CHROMA_SUPPRESSION_UPDATE: {
- struct vfe_cmd_chroma_suppression_config chromsup;
- if (copy_from_user(&chromsup,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_chroma_sup_config(&chromsup);
- }
- break;
-
- case VFE_CMD_ID_ASF_CONFIG: {
- struct vfe_cmd_asf_config asf;
- if (copy_from_user(&asf,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_asf_config(&asf);
- }
- break;
-
- case VFE_CMD_ID_SCALER2Y_CONFIG:
- case VFE_CMD_ID_SCALER2Y_UPDATE: {
- struct vfe_cmd_scaler2_config ds2y;
- if (copy_from_user(&ds2y,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_scaler2y_config(&ds2y);
- }
- break;
-
- case VFE_CMD_ID_SCALER2CbCr_CONFIG:
- case VFE_CMD_ID_SCALER2CbCr_UPDATE: {
- struct vfe_cmd_scaler2_config ds2cbcr;
- if (copy_from_user(&ds2cbcr,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_scaler2cbcr_config(&ds2cbcr);
- }
- break;
-
- case VFE_CMD_ID_CHROMA_SUBSAMPLE_CONFIG: {
- struct vfe_cmd_chroma_subsample_config sub;
- if (copy_from_user(&sub,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_chroma_subsample_config(&sub);
- }
- break;
-
- case VFE_CMD_ID_FRAME_SKIP_CONFIG: {
- struct vfe_cmd_frame_skip_config fskip;
- if (copy_from_user(&fskip,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_frame_skip_config(&fskip);
- }
- break;
-
- case VFE_CMD_ID_OUTPUT_CLAMP_CONFIG: {
- struct vfe_cmd_output_clamp_config clamp;
- if (copy_from_user(&clamp,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_output_clamp_config(&clamp);
- }
- break;
-
- /* module update commands */
- case VFE_CMD_ID_BLACK_LEVEL_UPDATE: {
- struct vfe_cmd_black_level_config blk;
- if (copy_from_user(&blk,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_black_level_update(&blk);
- }
- break;
-
- case VFE_CMD_ID_DEMUX_CHANNEL_GAIN_UPDATE: {
- struct vfe_cmd_demux_channel_gain_config dmu;
- if (copy_from_user(&dmu,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_demux_channel_gain_update(&dmu);
- }
- break;
-
- case VFE_CMD_ID_DEMOSAIC_BPC_UPDATE: {
- struct vfe_cmd_demosaic_bpc_update demo_bpc;
- if (copy_from_user(&demo_bpc,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_demosaic_bpc_update(&demo_bpc);
- }
- break;
-
- case VFE_CMD_ID_DEMOSAIC_ABF_UPDATE: {
- struct vfe_cmd_demosaic_abf_update demo_abf;
- if (copy_from_user(&demo_abf,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_demosaic_abf_update(&demo_abf);
- }
- break;
-
- case VFE_CMD_ID_LA_UPDATE: {
- struct vfe_cmd_la_config la;
- if (copy_from_user(&la,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_la_update(&la);
- }
- break;
-
- case VFE_CMD_ID_RGB_GAMMA_UPDATE: {
- struct vfe_cmd_rgb_gamma_config rgb;
- if (copy_from_user(&rgb,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- rc = vfe_rgb_gamma_update(&rgb);
- }
- break;
-
- case VFE_CMD_ID_ASF_UPDATE: {
- struct vfe_cmd_asf_update asf;
- if (copy_from_user(&asf,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_asf_update(&asf);
- }
- break;
-
- case VFE_CMD_ID_FRAME_SKIP_UPDATE: {
- struct vfe_cmd_frame_skip_update fskip;
- if (copy_from_user(&fskip,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_frame_skip_update(&fskip);
- }
- break;
-
- case VFE_CMD_ID_CAMIF_FRAME_UPDATE: {
- struct vfe_cmds_camif_frame fup;
- if (copy_from_user(&fup,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_camif_frame_update(&fup);
- }
- break;
-
- /* stats update commands */
- case VFE_CMD_ID_STATS_AUTOFOCUS_UPDATE: {
- struct vfe_cmd_stats_af_update afup;
- if (copy_from_user(&afup,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_stats_update_af(&afup);
- }
- break;
-
- case VFE_CMD_ID_STATS_WB_EXP_UPDATE: {
- struct vfe_cmd_stats_wb_exp_update wbexp;
- if (copy_from_user(&wbexp,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_stats_update_wb_exp(&wbexp);
- }
- break;
-
- /* control of start, stop, update, etc... */
- case VFE_CMD_ID_STOP:
- vfe_stop();
- break;
-
- case VFE_CMD_ID_GET_HW_VERSION:
- break;
-
- /* stats */
- case VFE_CMD_ID_STATS_SETTING: {
- struct vfe_cmd_stats_setting stats;
- if (copy_from_user(&stats,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_stats_setting(&stats);
- }
- break;
-
- case VFE_CMD_ID_STATS_AUTOFOCUS_START: {
- struct vfe_cmd_stats_af_start af;
- if (copy_from_user(&af,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_stats_start_af(&af);
- }
- break;
-
- case VFE_CMD_ID_STATS_AUTOFOCUS_STOP:
- vfe_stats_af_stop();
- break;
-
- case VFE_CMD_ID_STATS_WB_EXP_START: {
- struct vfe_cmd_stats_wb_exp_start awexp;
- if (copy_from_user(&awexp,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_stats_start_wb_exp(&awexp);
- }
- break;
-
- case VFE_CMD_ID_STATS_WB_EXP_STOP:
- vfe_stats_wb_exp_stop();
- break;
-
- case VFE_CMD_ID_ASYNC_TIMER_SETTING:
- break;
-
- case VFE_CMD_ID_UPDATE:
- vfe_update();
- break;
-
- /* test gen */
- case VFE_CMD_ID_TEST_GEN_START:
- break;
-
-/*
- acknowledge from upper layer
- these are not in general command.
-
- case VFE_CMD_ID_OUTPUT1_ACK:
- break;
- case VFE_CMD_ID_OUTPUT2_ACK:
- break;
- case VFE_CMD_ID_EPOCH1_ACK:
- break;
- case VFE_CMD_ID_EPOCH2_ACK:
- break;
- case VFE_CMD_ID_STATS_AUTOFOCUS_ACK:
- break;
- case VFE_CMD_ID_STATS_WB_EXP_ACK:
- break;
-*/
-
- default:
- break;
- } /* switch */
-
- return rc;
-}
-
-static int vfe_config(struct msm_vfe_cfg_cmd *cmd, void *data)
-{
- struct msm_pmem_region *regptr;
- struct msm_vfe_command_8k vfecmd;
-
- uint32_t i;
-
- void *cmd_data = NULL;
- long rc = 0;
-
- struct vfe_cmd_axi_output_config *axio = NULL;
- struct vfe_cmd_stats_setting *scfg = NULL;
-
- if (cmd->cmd_type != CMD_FRAME_BUF_RELEASE &&
- cmd->cmd_type != CMD_STATS_BUF_RELEASE) {
-
- if (copy_from_user(&vfecmd,
- (void __user *)(cmd->value),
- sizeof(struct msm_vfe_command_8k)))
- return -EFAULT;
- }
-
- CDBG("vfe_config: cmdType = %d\n", cmd->cmd_type);
-
- switch (cmd->cmd_type) {
- case CMD_GENERAL:
- rc = vfe_proc_general(&vfecmd);
- break;
-
- case CMD_STATS_ENABLE:
- case CMD_STATS_AXI_CFG: {
- struct axidata *axid;
-
- axid = data;
- if (!axid)
- return -EFAULT;
-
- scfg =
- kmalloc(sizeof(struct vfe_cmd_stats_setting),
- GFP_ATOMIC);
- if (!scfg)
- return -ENOMEM;
-
- if (copy_from_user(scfg,
- (void __user *)(vfecmd.value),
- vfecmd.length)) {
-
- kfree(scfg);
- return -EFAULT;
- }
-
- regptr = axid->region;
- if (axid->bufnum1 > 0) {
- for (i = 0; i < axid->bufnum1; i++) {
- scfg->awbBuffer[i] =
- (uint32_t)(regptr->paddr);
- regptr++;
- }
- }
-
- if (axid->bufnum2 > 0) {
- for (i = 0; i < axid->bufnum2; i++) {
- scfg->afBuffer[i] =
- (uint32_t)(regptr->paddr);
- regptr++;
- }
- }
-
- vfe_stats_config(scfg);
- }
- break;
-
- case CMD_STATS_AF_AXI_CFG: {
- }
- break;
-
- case CMD_FRAME_BUF_RELEASE: {
- /* preview buffer release */
- struct msm_frame *b;
- unsigned long p;
- struct vfe_cmd_output_ack fack;
-
- if (!data)
- return -EFAULT;
-
- b = (struct msm_frame *)(cmd->value);
- p = *(unsigned long *)data;
-
- b->path = MSM_FRAME_ENC;
-
- fack.ybufaddr[0] =
- (uint32_t)(p + b->y_off);
-
- fack.chromabufaddr[0] =
- (uint32_t)(p + b->cbcr_off);
-
- if (b->path == MSM_FRAME_PREV_1)
- vfe_output1_ack(&fack);
-
- if (b->path == MSM_FRAME_ENC ||
- b->path == MSM_FRAME_PREV_2)
- vfe_output2_ack(&fack);
- }
- break;
-
- case CMD_SNAP_BUF_RELEASE: {
- }
- break;
-
- case CMD_STATS_BUF_RELEASE: {
- struct vfe_cmd_stats_wb_exp_ack sack;
-
- if (!data)
- return -EFAULT;
-
- sack.nextWbExpOutputBufferAddr = *(uint32_t *)data;
- vfe_stats_wb_exp_ack(&sack);
- }
- break;
-
- case CMD_AXI_CFG_OUT1: {
- struct axidata *axid;
-
- axid = data;
- if (!axid)
- return -EFAULT;
-
- axio = memdup_user((void __user *)(vfecmd.value),
- sizeof(struct vfe_cmd_axi_output_config));
- if (IS_ERR(axio))
- return PTR_ERR(axio);
-
- vfe_config_axi(OUTPUT_1, axid, axio);
- vfe_axi_output_config(axio);
- }
- break;
-
- case CMD_AXI_CFG_OUT2:
- case CMD_RAW_PICT_AXI_CFG: {
- struct axidata *axid;
-
- axid = data;
- if (!axid)
- return -EFAULT;
-
- axio = memdup_user((void __user *)(vfecmd.value),
- sizeof(struct vfe_cmd_axi_output_config));
- if (IS_ERR(axio))
- return PTR_ERR(axio);
-
- vfe_config_axi(OUTPUT_2, axid, axio);
-
- axio->outputDataSize = 0;
- vfe_axi_output_config(axio);
- }
- break;
-
- case CMD_AXI_CFG_SNAP_O1_AND_O2: {
- struct axidata *axid;
- axid = data;
- if (!axid)
- return -EFAULT;
-
- axio = memdup_user((void __user *)(vfecmd.value),
- sizeof(struct vfe_cmd_axi_output_config));
- if (IS_ERR(axio))
- return PTR_ERR(axio);
-
- vfe_config_axi(OUTPUT_1_AND_2,
- axid, axio);
- vfe_axi_output_config(axio);
- cmd_data = axio;
- }
- break;
-
- default:
- break;
- } /* switch */
-
- kfree(scfg);
-
- kfree(axio);
-
-/*
- if (cmd->length > 256 &&
- cmd_data &&
- (cmd->cmd_type == CMD_GENERAL ||
- cmd->cmd_type == CMD_STATS_DISABLE)) {
- kfree(cmd_data);
- }
-*/
- return rc;
-}
-
-static int vfe_init(struct msm_vfe_callback *presp,
- struct platform_device *dev)
-{
- int rc = 0;
-
- rc = vfe_cmd_init(presp, dev, vfe_syncdata);
- if (rc < 0)
- return rc;
-
- /* Bring up all the required GPIOs and Clocks */
- return msm_camio_enable(dev);
-}
-
-void msm_camvfe_fn_init(struct msm_camvfe_fn *fptr, void *data)
-{
- mutex_init(&vfe_lock);
- fptr->vfe_init = vfe_init;
- fptr->vfe_enable = vfe_enable;
- fptr->vfe_config = vfe_config;
- fptr->vfe_disable = vfe_disable;
- fptr->vfe_release = vfe_release;
- vfe_syncdata = data;
-}
diff --git a/trunk/drivers/staging/dream/camera/msm_vfe8x.h b/trunk/drivers/staging/dream/camera/msm_vfe8x.h
deleted file mode 100644
index 28a70a9e5ed7..000000000000
--- a/trunk/drivers/staging/dream/camera/msm_vfe8x.h
+++ /dev/null
@@ -1,895 +0,0 @@
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-#ifndef __MSM_VFE8X_H__
-#define __MSM_VFE8X_H__
-
-#define TRUE 1
-#define FALSE 0
-#define boolean uint8_t
-
-enum VFE_STATE {
- VFE_STATE_IDLE,
- VFE_STATE_ACTIVE
-};
-
-enum vfe_cmd_id {
- /*
- *Important! Command_ID are arranged in order.
- *Don't change!*/
- VFE_CMD_ID_START,
- VFE_CMD_ID_RESET,
-
- /* bus and camif config */
- VFE_CMD_ID_AXI_INPUT_CONFIG,
- VFE_CMD_ID_CAMIF_CONFIG,
- VFE_CMD_ID_AXI_OUTPUT_CONFIG,
-
- /* module config */
- VFE_CMD_ID_BLACK_LEVEL_CONFIG,
- VFE_CMD_ID_ROLL_OFF_CONFIG,
- VFE_CMD_ID_DEMUX_CHANNEL_GAIN_CONFIG,
- VFE_CMD_ID_DEMOSAIC_CONFIG,
- VFE_CMD_ID_FOV_CROP_CONFIG,
- VFE_CMD_ID_MAIN_SCALER_CONFIG,
- VFE_CMD_ID_WHITE_BALANCE_CONFIG,
- VFE_CMD_ID_COLOR_CORRECTION_CONFIG,
- VFE_CMD_ID_LA_CONFIG,
- VFE_CMD_ID_RGB_GAMMA_CONFIG,
- VFE_CMD_ID_CHROMA_ENHAN_CONFIG,
- VFE_CMD_ID_CHROMA_SUPPRESSION_CONFIG,
- VFE_CMD_ID_ASF_CONFIG,
- VFE_CMD_ID_SCALER2Y_CONFIG,
- VFE_CMD_ID_SCALER2CbCr_CONFIG,
- VFE_CMD_ID_CHROMA_SUBSAMPLE_CONFIG,
- VFE_CMD_ID_FRAME_SKIP_CONFIG,
- VFE_CMD_ID_OUTPUT_CLAMP_CONFIG,
-
- /* test gen */
- VFE_CMD_ID_TEST_GEN_START,
-
- VFE_CMD_ID_UPDATE,
-
- /* ackownledge from upper layer */
- VFE_CMD_ID_OUTPUT1_ACK,
- VFE_CMD_ID_OUTPUT2_ACK,
- VFE_CMD_ID_EPOCH1_ACK,
- VFE_CMD_ID_EPOCH2_ACK,
- VFE_CMD_ID_STATS_AUTOFOCUS_ACK,
- VFE_CMD_ID_STATS_WB_EXP_ACK,
-
- /* module update commands */
- VFE_CMD_ID_BLACK_LEVEL_UPDATE,
- VFE_CMD_ID_DEMUX_CHANNEL_GAIN_UPDATE,
- VFE_CMD_ID_DEMOSAIC_BPC_UPDATE,
- VFE_CMD_ID_DEMOSAIC_ABF_UPDATE,
- VFE_CMD_ID_FOV_CROP_UPDATE,
- VFE_CMD_ID_WHITE_BALANCE_UPDATE,
- VFE_CMD_ID_COLOR_CORRECTION_UPDATE,
- VFE_CMD_ID_LA_UPDATE,
- VFE_CMD_ID_RGB_GAMMA_UPDATE,
- VFE_CMD_ID_CHROMA_ENHAN_UPDATE,
- VFE_CMD_ID_CHROMA_SUPPRESSION_UPDATE,
- VFE_CMD_ID_MAIN_SCALER_UPDATE,
- VFE_CMD_ID_SCALER2CbCr_UPDATE,
- VFE_CMD_ID_SCALER2Y_UPDATE,
- VFE_CMD_ID_ASF_UPDATE,
- VFE_CMD_ID_FRAME_SKIP_UPDATE,
- VFE_CMD_ID_CAMIF_FRAME_UPDATE,
-
- /* stats update commands */
- VFE_CMD_ID_STATS_AUTOFOCUS_UPDATE,
- VFE_CMD_ID_STATS_WB_EXP_UPDATE,
-
- /* control of start, stop, update, etc... */
- VFE_CMD_ID_STOP,
- VFE_CMD_ID_GET_HW_VERSION,
-
- /* stats */
- VFE_CMD_ID_STATS_SETTING,
- VFE_CMD_ID_STATS_AUTOFOCUS_START,
- VFE_CMD_ID_STATS_AUTOFOCUS_STOP,
- VFE_CMD_ID_STATS_WB_EXP_START,
- VFE_CMD_ID_STATS_WB_EXP_STOP,
-
- VFE_CMD_ID_ASYNC_TIMER_SETTING,
-
- /* max id */
- VFE_CMD_ID_MAX
-};
-
-struct vfe_cmd_hw_version {
- uint32_t minorVersion;
- uint32_t majorVersion;
- uint32_t coreVersion;
-};
-
-enum VFE_CAMIF_SYNC_EDGE {
- VFE_CAMIF_SYNC_EDGE_ActiveHigh,
- VFE_CAMIF_SYNC_EDGE_ActiveLow
-};
-
-enum VFE_CAMIF_SYNC_MODE {
- VFE_CAMIF_SYNC_MODE_APS,
- VFE_CAMIF_SYNC_MODE_EFS,
- VFE_CAMIF_SYNC_MODE_ELS,
- VFE_CAMIF_SYNC_MODE_ILLEGAL
-};
-
-struct vfe_cmds_camif_efs {
- uint8_t efsendofline;
- uint8_t efsstartofline;
- uint8_t efsendofframe;
- uint8_t efsstartofframe;
-};
-
-struct vfe_cmds_camif_frame {
- uint16_t pixelsPerLine;
- uint16_t linesPerFrame;
-};
-
-struct vfe_cmds_camif_window {
- uint16_t firstpixel;
- uint16_t lastpixel;
- uint16_t firstline;
- uint16_t lastline;
-};
-
-enum CAMIF_SUBSAMPLE_FRAME_SKIP {
- CAMIF_SUBSAMPLE_FRAME_SKIP_0,
- CAMIF_SUBSAMPLE_FRAME_SKIP_AllFrames,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_2Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_3Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_4Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_5Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_6Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_7Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_8Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_9Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_10Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_11Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_12Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_13Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_14Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_15Frame
-};
-
-struct vfe_cmds_camif_subsample {
- uint16_t pixelskipmask;
- uint16_t lineskipmask;
- enum CAMIF_SUBSAMPLE_FRAME_SKIP frameskip;
- uint8_t frameskipmode;
- uint8_t pixelskipwrap;
-};
-
-struct vfe_cmds_camif_epoch {
- uint8_t enable;
- uint16_t lineindex;
-};
-
-struct vfe_cmds_camif_cfg {
- enum VFE_CAMIF_SYNC_EDGE vSyncEdge;
- enum VFE_CAMIF_SYNC_EDGE hSyncEdge;
- enum VFE_CAMIF_SYNC_MODE syncMode;
- uint8_t vfeSubSampleEnable;
- uint8_t busSubSampleEnable;
- uint8_t irqSubSampleEnable;
- uint8_t binningEnable;
- uint8_t misrEnable;
-};
-
-struct vfe_cmd_camif_config {
- struct vfe_cmds_camif_cfg camifConfig;
- struct vfe_cmds_camif_efs EFS;
- struct vfe_cmds_camif_frame frame;
- struct vfe_cmds_camif_window window;
- struct vfe_cmds_camif_subsample subsample;
- struct vfe_cmds_camif_epoch epoch1;
- struct vfe_cmds_camif_epoch epoch2;
-};
-
-enum VFE_AXI_OUTPUT_MODE {
- VFE_AXI_OUTPUT_MODE_Output1,
- VFE_AXI_OUTPUT_MODE_Output2,
- VFE_AXI_OUTPUT_MODE_Output1AndOutput2,
- VFE_AXI_OUTPUT_MODE_CAMIFToAXIViaOutput2,
- VFE_AXI_OUTPUT_MODE_Output2AndCAMIFToAXIViaOutput1,
- VFE_AXI_OUTPUT_MODE_Output1AndCAMIFToAXIViaOutput2,
- VFE_AXI_LAST_OUTPUT_MODE_ENUM
-};
-
-enum VFE_RAW_WR_PATH_SEL {
- VFE_RAW_OUTPUT_DISABLED,
- VFE_RAW_OUTPUT_ENC_CBCR_PATH,
- VFE_RAW_OUTPUT_VIEW_CBCR_PATH,
- VFE_RAW_OUTPUT_PATH_INVALID
-};
-
-enum VFE_RAW_PIXEL_DATA_SIZE {
- VFE_RAW_PIXEL_DATA_SIZE_8BIT,
- VFE_RAW_PIXEL_DATA_SIZE_10BIT,
- VFE_RAW_PIXEL_DATA_SIZE_12BIT,
-};
-
-#define VFE_AXI_OUTPUT_BURST_LENGTH 4
-#define VFE_MAX_NUM_FRAGMENTS_PER_FRAME 4
-#define VFE_AXI_OUTPUT_CFG_FRAME_COUNT 3
-
-struct vfe_cmds_axi_out_per_component {
- uint16_t imageWidth;
- uint16_t imageHeight;
- uint16_t outRowCount;
- uint16_t outRowIncrement;
- uint32_t outFragments[VFE_AXI_OUTPUT_CFG_FRAME_COUNT]
- [VFE_MAX_NUM_FRAGMENTS_PER_FRAME];
-};
-
-struct vfe_cmds_axi_per_output_path {
- uint8_t fragmentCount;
- struct vfe_cmds_axi_out_per_component outputY;
- struct vfe_cmds_axi_out_per_component outputCbcr;
-};
-
-enum VFE_AXI_BURST_LENGTH {
- VFE_AXI_BURST_LENGTH_IS_2 = 2,
- VFE_AXI_BURST_LENGTH_IS_4 = 4,
- VFE_AXI_BURST_LENGTH_IS_8 = 8,
- VFE_AXI_BURST_LENGTH_IS_16 = 16
-};
-
-struct vfe_cmd_axi_output_config {
- enum VFE_AXI_BURST_LENGTH burstLength;
- enum VFE_AXI_OUTPUT_MODE outputMode;
- enum VFE_RAW_PIXEL_DATA_SIZE outputDataSize;
- struct vfe_cmds_axi_per_output_path output1;
- struct vfe_cmds_axi_per_output_path output2;
-};
-
-struct vfe_cmd_fov_crop_config {
- uint8_t enable;
- uint16_t firstPixel;
- uint16_t lastPixel;
- uint16_t firstLine;
- uint16_t lastLine;
-};
-
-struct vfe_cmds_main_scaler_stripe_init {
- uint16_t MNCounterInit;
- uint16_t phaseInit;
-};
-
-struct vfe_cmds_scaler_one_dimension {
- uint8_t enable;
- uint16_t inputSize;
- uint16_t outputSize;
- uint32_t phaseMultiplicationFactor;
- uint8_t interpolationResolution;
-};
-
-struct vfe_cmd_main_scaler_config {
- uint8_t enable;
- struct vfe_cmds_scaler_one_dimension hconfig;
- struct vfe_cmds_scaler_one_dimension vconfig;
- struct vfe_cmds_main_scaler_stripe_init MNInitH;
- struct vfe_cmds_main_scaler_stripe_init MNInitV;
-};
-
-struct vfe_cmd_scaler2_config {
- uint8_t enable;
- struct vfe_cmds_scaler_one_dimension hconfig;
- struct vfe_cmds_scaler_one_dimension vconfig;
-};
-
-struct vfe_cmd_frame_skip_config {
- uint8_t output1Period;
- uint32_t output1Pattern;
- uint8_t output2Period;
- uint32_t output2Pattern;
-};
-
-struct vfe_cmd_frame_skip_update {
- uint32_t output1Pattern;
- uint32_t output2Pattern;
-};
-
-struct vfe_cmd_output_clamp_config {
- uint8_t minCh0;
- uint8_t minCh1;
- uint8_t minCh2;
- uint8_t maxCh0;
- uint8_t maxCh1;
- uint8_t maxCh2;
-};
-
-struct vfe_cmd_chroma_subsample_config {
- uint8_t enable;
- uint8_t cropEnable;
- uint8_t vsubSampleEnable;
- uint8_t hsubSampleEnable;
- uint8_t vCosited;
- uint8_t hCosited;
- uint8_t vCositedPhase;
- uint8_t hCositedPhase;
- uint16_t cropWidthFirstPixel;
- uint16_t cropWidthLastPixel;
- uint16_t cropHeightFirstLine;
- uint16_t cropHeightLastLine;
-};
-
-enum VFE_START_INPUT_SOURCE {
- VFE_START_INPUT_SOURCE_CAMIF,
- VFE_START_INPUT_SOURCE_TESTGEN,
- VFE_START_INPUT_SOURCE_AXI,
- VFE_START_INPUT_SOURCE_INVALID
-};
-
-enum VFE_START_OPERATION_MODE {
- VFE_START_OPERATION_MODE_CONTINUOUS,
- VFE_START_OPERATION_MODE_SNAPSHOT
-};
-
-enum VFE_START_PIXEL_PATTERN {
- VFE_BAYER_RGRGRG,
- VFE_BAYER_GRGRGR,
- VFE_BAYER_BGBGBG,
- VFE_BAYER_GBGBGB,
- VFE_YUV_YCbYCr,
- VFE_YUV_YCrYCb,
- VFE_YUV_CbYCrY,
- VFE_YUV_CrYCbY
-};
-
-enum VFE_BUS_RD_INPUT_PIXEL_PATTERN {
- VFE_BAYER_RAW,
- VFE_YUV_INTERLEAVED,
- VFE_YUV_PSEUDO_PLANAR_Y,
- VFE_YUV_PSEUDO_PLANAR_CBCR
-};
-
-enum VFE_YUV_INPUT_COSITING_MODE {
- VFE_YUV_COSITED,
- VFE_YUV_INTERPOLATED
-};
-
-struct vfe_cmd_start {
- enum VFE_START_INPUT_SOURCE inputSource;
- enum VFE_START_OPERATION_MODE operationMode;
- uint8_t snapshotCount;
- enum VFE_START_PIXEL_PATTERN pixel;
- enum VFE_YUV_INPUT_COSITING_MODE yuvInputCositingMode;
-};
-
-struct vfe_cmd_output_ack {
- uint32_t ybufaddr[VFE_MAX_NUM_FRAGMENTS_PER_FRAME];
- uint32_t chromabufaddr[VFE_MAX_NUM_FRAGMENTS_PER_FRAME];
-};
-
-#define VFE_STATS_BUFFER_COUNT 3
-
-struct vfe_cmd_stats_setting {
- uint16_t frameHDimension;
- uint16_t frameVDimension;
- uint8_t afBusPrioritySelection;
- uint8_t afBusPriority;
- uint8_t awbBusPrioritySelection;
- uint8_t awbBusPriority;
- uint8_t histBusPrioritySelection;
- uint8_t histBusPriority;
- uint32_t afBuffer[VFE_STATS_BUFFER_COUNT];
- uint32_t awbBuffer[VFE_STATS_BUFFER_COUNT];
- uint32_t histBuffer[VFE_STATS_BUFFER_COUNT];
-};
-
-struct vfe_cmd_stats_af_start {
- uint8_t enable;
- uint8_t windowMode;
- uint16_t windowHOffset;
- uint16_t windowVOffset;
- uint16_t windowWidth;
- uint16_t windowHeight;
- uint8_t gridForMultiWindows[16];
- uint8_t metricSelection;
- int16_t metricMax;
- int8_t highPassCoef[7];
- int8_t bufferHeader;
-};
-
-struct vfe_cmd_stats_af_update {
- uint8_t windowMode;
- uint16_t windowHOffset;
- uint16_t windowVOffset;
- uint16_t windowWidth;
- uint16_t windowHeight;
-};
-
-struct vfe_cmd_stats_wb_exp_start {
- uint8_t enable;
- uint8_t wbExpRegions;
- uint8_t wbExpSubRegion;
- uint8_t awbYMin;
- uint8_t awbYMax;
- int8_t awbMCFG[4];
- int16_t awbCCFG[4];
- int8_t axwHeader;
-};
-
-struct vfe_cmd_stats_wb_exp_update {
- uint8_t wbExpRegions;
- uint8_t wbExpSubRegion;
- int8_t awbYMin;
- int8_t awbYMax;
- int8_t awbMCFG[4];
- int16_t awbCCFG[4];
-};
-
-struct vfe_cmd_stats_af_ack {
- uint32_t nextAFOutputBufferAddr;
-};
-
-struct vfe_cmd_stats_wb_exp_ack {
- uint32_t nextWbExpOutputBufferAddr;
-};
-
-struct vfe_cmd_black_level_config {
- uint8_t enable;
- uint16_t evenEvenAdjustment;
- uint16_t evenOddAdjustment;
- uint16_t oddEvenAdjustment;
- uint16_t oddOddAdjustment;
-};
-
-/* 13*1 */
-#define VFE_ROLL_OFF_INIT_TABLE_SIZE 13
-/* 13*16 */
-#define VFE_ROLL_OFF_DELTA_TABLE_SIZE 208
-
-struct vfe_cmd_roll_off_config {
- uint8_t enable;
- uint16_t gridWidth;
- uint16_t gridHeight;
- uint16_t yDelta;
- uint8_t gridXIndex;
- uint8_t gridYIndex;
- uint16_t gridPixelXIndex;
- uint16_t gridPixelYIndex;
- uint16_t yDeltaAccum;
- uint16_t initTableR[VFE_ROLL_OFF_INIT_TABLE_SIZE];
- uint16_t initTableGr[VFE_ROLL_OFF_INIT_TABLE_SIZE];
- uint16_t initTableB[VFE_ROLL_OFF_INIT_TABLE_SIZE];
- uint16_t initTableGb[VFE_ROLL_OFF_INIT_TABLE_SIZE];
- int16_t deltaTableR[VFE_ROLL_OFF_DELTA_TABLE_SIZE];
- int16_t deltaTableGr[VFE_ROLL_OFF_DELTA_TABLE_SIZE];
- int16_t deltaTableB[VFE_ROLL_OFF_DELTA_TABLE_SIZE];
- int16_t deltaTableGb[VFE_ROLL_OFF_DELTA_TABLE_SIZE];
-};
-
-struct vfe_cmd_demux_channel_gain_config {
- uint16_t ch0EvenGain;
- uint16_t ch0OddGain;
- uint16_t ch1Gain;
- uint16_t ch2Gain;
-};
-
-struct vfe_cmds_demosaic_abf {
- uint8_t enable;
- uint8_t forceOn;
- uint8_t shift;
- uint16_t lpThreshold;
- uint16_t max;
- uint16_t min;
- uint8_t ratio;
-};
-
-struct vfe_cmds_demosaic_bpc {
- uint8_t enable;
- uint16_t fmaxThreshold;
- uint16_t fminThreshold;
- uint16_t redDiffThreshold;
- uint16_t blueDiffThreshold;
- uint16_t greenDiffThreshold;
-};
-
-struct vfe_cmd_demosaic_config {
- uint8_t enable;
- uint8_t slopeShift;
- struct vfe_cmds_demosaic_abf abfConfig;
- struct vfe_cmds_demosaic_bpc bpcConfig;
-};
-
-struct vfe_cmd_demosaic_bpc_update {
- struct vfe_cmds_demosaic_bpc bpcUpdate;
-};
-
-struct vfe_cmd_demosaic_abf_update {
- struct vfe_cmds_demosaic_abf abfUpdate;
-};
-
-struct vfe_cmd_white_balance_config {
- uint8_t enable;
- uint16_t ch2Gain;
- uint16_t ch1Gain;
- uint16_t ch0Gain;
-};
-
-enum VFE_COLOR_CORRECTION_COEF_QFACTOR {
- COEF_IS_Q7_SIGNED,
- COEF_IS_Q8_SIGNED,
- COEF_IS_Q9_SIGNED,
- COEF_IS_Q10_SIGNED
-};
-
-struct vfe_cmd_color_correction_config {
- uint8_t enable;
- enum VFE_COLOR_CORRECTION_COEF_QFACTOR coefQFactor;
- int16_t C0;
- int16_t C1;
- int16_t C2;
- int16_t C3;
- int16_t C4;
- int16_t C5;
- int16_t C6;
- int16_t C7;
- int16_t C8;
- int16_t K0;
- int16_t K1;
- int16_t K2;
-};
-
-#define VFE_LA_TABLE_LENGTH 256
-struct vfe_cmd_la_config {
- uint8_t enable;
- int16_t table[VFE_LA_TABLE_LENGTH];
-};
-
-#define VFE_GAMMA_TABLE_LENGTH 256
-enum VFE_RGB_GAMMA_TABLE_SELECT {
- RGB_GAMMA_CH0_SELECTED,
- RGB_GAMMA_CH1_SELECTED,
- RGB_GAMMA_CH2_SELECTED,
- RGB_GAMMA_CH0_CH1_SELECTED,
- RGB_GAMMA_CH0_CH2_SELECTED,
- RGB_GAMMA_CH1_CH2_SELECTED,
- RGB_GAMMA_CH0_CH1_CH2_SELECTED
-};
-
-struct vfe_cmd_rgb_gamma_config {
- uint8_t enable;
- enum VFE_RGB_GAMMA_TABLE_SELECT channelSelect;
- int16_t table[VFE_GAMMA_TABLE_LENGTH];
-};
-
-struct vfe_cmd_chroma_enhan_config {
- uint8_t enable;
- int16_t am;
- int16_t ap;
- int16_t bm;
- int16_t bp;
- int16_t cm;
- int16_t cp;
- int16_t dm;
- int16_t dp;
- int16_t kcr;
- int16_t kcb;
- int16_t RGBtoYConversionV0;
- int16_t RGBtoYConversionV1;
- int16_t RGBtoYConversionV2;
- uint8_t RGBtoYConversionOffset;
-};
-
-struct vfe_cmd_chroma_suppression_config {
- uint8_t enable;
- uint8_t m1;
- uint8_t m3;
- uint8_t n1;
- uint8_t n3;
- uint8_t nn1;
- uint8_t mm1;
-};
-
-struct vfe_cmd_asf_config {
- uint8_t enable;
- uint8_t smoothFilterEnabled;
- uint8_t sharpMode;
- uint8_t smoothCoefCenter;
- uint8_t smoothCoefSurr;
- uint8_t normalizeFactor;
- uint8_t sharpK1;
- uint8_t sharpK2;
- uint8_t sharpThreshE1;
- int8_t sharpThreshE2;
- int8_t sharpThreshE3;
- int8_t sharpThreshE4;
- int8_t sharpThreshE5;
- int8_t filter1Coefficients[9];
- int8_t filter2Coefficients[9];
- uint8_t cropEnable;
- uint16_t cropFirstPixel;
- uint16_t cropLastPixel;
- uint16_t cropFirstLine;
- uint16_t cropLastLine;
-};
-
-struct vfe_cmd_asf_update {
- uint8_t enable;
- uint8_t smoothFilterEnabled;
- uint8_t sharpMode;
- uint8_t smoothCoefCenter;
- uint8_t smoothCoefSurr;
- uint8_t normalizeFactor;
- uint8_t sharpK1;
- uint8_t sharpK2;
- uint8_t sharpThreshE1;
- int8_t sharpThreshE2;
- int8_t sharpThreshE3;
- int8_t sharpThreshE4;
- int8_t sharpThreshE5;
- int8_t filter1Coefficients[9];
- int8_t filter2Coefficients[9];
- uint8_t cropEnable;
-};
-
-enum VFE_TEST_GEN_SYNC_EDGE {
- VFE_TEST_GEN_SYNC_EDGE_ActiveHigh,
- VFE_TEST_GEN_SYNC_EDGE_ActiveLow
-};
-
-struct vfe_cmd_test_gen_start {
- uint8_t pixelDataSelect;
- uint8_t systematicDataSelect;
- enum VFE_TEST_GEN_SYNC_EDGE hsyncEdge;
- enum VFE_TEST_GEN_SYNC_EDGE vsyncEdge;
- uint16_t numFrame;
- enum VFE_RAW_PIXEL_DATA_SIZE pixelDataSize;
- uint16_t imageWidth;
- uint16_t imageHeight;
- uint32_t startOfFrameOffset;
- uint32_t endOfFrameNOffset;
- uint16_t startOfLineOffset;
- uint16_t endOfLineNOffset;
- uint16_t hbi;
- uint8_t vblEnable;
- uint16_t vbl;
- uint8_t startOfFrameDummyLine;
- uint8_t endOfFrameDummyLine;
- uint8_t unicolorBarEnable;
- uint8_t colorBarsSplitEnable;
- uint8_t unicolorBarSelect;
- enum VFE_START_PIXEL_PATTERN colorBarsPixelPattern;
- uint8_t colorBarsRotatePeriod;
- uint16_t testGenRandomSeed;
-};
-
-struct vfe_cmd_bus_pm_start {
- uint8_t output2YWrPmEnable;
- uint8_t output2CbcrWrPmEnable;
- uint8_t output1YWrPmEnable;
- uint8_t output1CbcrWrPmEnable;
-};
-
-struct vfe_cmd_camif_frame_update {
- struct vfe_cmds_camif_frame camifFrame;
-};
-
-struct vfe_cmd_sync_timer_setting {
- uint8_t whichSyncTimer;
- uint8_t operation;
- uint8_t polarity;
- uint16_t repeatCount;
- uint16_t hsyncCount;
- uint32_t pclkCount;
- uint32_t outputDuration;
-};
-
-struct vfe_cmd_async_timer_setting {
- uint8_t whichAsyncTimer;
- uint8_t operation;
- uint8_t polarity;
- uint16_t repeatCount;
- uint16_t inactiveCount;
- uint32_t activeCount;
-};
-
-struct vfe_frame_skip_counts {
- uint32_t totalFrameCount;
- uint32_t output1Count;
- uint32_t output2Count;
-};
-
-enum VFE_AXI_RD_UNPACK_HBI_SEL {
- VFE_AXI_RD_HBI_32_CLOCK_CYCLES,
- VFE_AXI_RD_HBI_64_CLOCK_CYCLES,
- VFE_AXI_RD_HBI_128_CLOCK_CYCLES,
- VFE_AXI_RD_HBI_256_CLOCK_CYCLES,
- VFE_AXI_RD_HBI_512_CLOCK_CYCLES,
- VFE_AXI_RD_HBI_1024_CLOCK_CYCLES,
- VFE_AXI_RD_HBI_2048_CLOCK_CYCLES,
- VFE_AXI_RD_HBI_4096_CLOCK_CYCLES
-};
-
-struct vfe_cmd_axi_input_config {
- uint32_t fragAddr[4];
- uint8_t totalFragmentCount;
- uint16_t ySize;
- uint16_t xOffset;
- uint16_t xSize;
- uint16_t rowIncrement;
- uint16_t numOfRows;
- enum VFE_AXI_BURST_LENGTH burstLength;
- uint8_t unpackPhase;
- enum VFE_AXI_RD_UNPACK_HBI_SEL unpackHbi;
- enum VFE_RAW_PIXEL_DATA_SIZE pixelSize;
- uint8_t padRepeatCountLeft;
- uint8_t padRepeatCountRight;
- uint8_t padRepeatCountTop;
- uint8_t padRepeatCountBottom;
- uint8_t padLeftComponentSelectCycle0;
- uint8_t padLeftComponentSelectCycle1;
- uint8_t padLeftComponentSelectCycle2;
- uint8_t padLeftComponentSelectCycle3;
- uint8_t padLeftStopCycle0;
- uint8_t padLeftStopCycle1;
- uint8_t padLeftStopCycle2;
- uint8_t padLeftStopCycle3;
- uint8_t padRightComponentSelectCycle0;
- uint8_t padRightComponentSelectCycle1;
- uint8_t padRightComponentSelectCycle2;
- uint8_t padRightComponentSelectCycle3;
- uint8_t padRightStopCycle0;
- uint8_t padRightStopCycle1;
- uint8_t padRightStopCycle2;
- uint8_t padRightStopCycle3;
- uint8_t padTopLineCount;
- uint8_t padBottomLineCount;
-};
-
-struct vfe_interrupt_status {
- uint8_t camifErrorIrq;
- uint8_t camifSofIrq;
- uint8_t camifEolIrq;
- uint8_t camifEofIrq;
- uint8_t camifEpoch1Irq;
- uint8_t camifEpoch2Irq;
- uint8_t camifOverflowIrq;
- uint8_t ceIrq;
- uint8_t regUpdateIrq;
- uint8_t resetAckIrq;
- uint8_t encYPingpongIrq;
- uint8_t encCbcrPingpongIrq;
- uint8_t viewYPingpongIrq;
- uint8_t viewCbcrPingpongIrq;
- uint8_t rdPingpongIrq;
- uint8_t afPingpongIrq;
- uint8_t awbPingpongIrq;
- uint8_t histPingpongIrq;
- uint8_t encIrq;
- uint8_t viewIrq;
- uint8_t busOverflowIrq;
- uint8_t afOverflowIrq;
- uint8_t awbOverflowIrq;
- uint8_t syncTimer0Irq;
- uint8_t syncTimer1Irq;
- uint8_t syncTimer2Irq;
- uint8_t asyncTimer0Irq;
- uint8_t asyncTimer1Irq;
- uint8_t asyncTimer2Irq;
- uint8_t asyncTimer3Irq;
- uint8_t axiErrorIrq;
- uint8_t violationIrq;
- uint8_t anyErrorIrqs;
- uint8_t anyOutput1PathIrqs;
- uint8_t anyOutput2PathIrqs;
- uint8_t anyOutputPathIrqs;
- uint8_t anyAsyncTimerIrqs;
- uint8_t anySyncTimerIrqs;
- uint8_t anyIrqForActiveStatesOnly;
-};
-
-enum VFE_MESSAGE_ID {
- VFE_MSG_ID_RESET_ACK,
- VFE_MSG_ID_START_ACK,
- VFE_MSG_ID_STOP_ACK,
- VFE_MSG_ID_UPDATE_ACK,
- VFE_MSG_ID_OUTPUT1,
- VFE_MSG_ID_OUTPUT2,
- VFE_MSG_ID_SNAPSHOT_DONE,
- VFE_MSG_ID_STATS_AUTOFOCUS,
- VFE_MSG_ID_STATS_WB_EXP,
- VFE_MSG_ID_EPOCH1,
- VFE_MSG_ID_EPOCH2,
- VFE_MSG_ID_SYNC_TIMER0_DONE,
- VFE_MSG_ID_SYNC_TIMER1_DONE,
- VFE_MSG_ID_SYNC_TIMER2_DONE,
- VFE_MSG_ID_ASYNC_TIMER0_DONE,
- VFE_MSG_ID_ASYNC_TIMER1_DONE,
- VFE_MSG_ID_ASYNC_TIMER2_DONE,
- VFE_MSG_ID_ASYNC_TIMER3_DONE,
- VFE_MSG_ID_AF_OVERFLOW,
- VFE_MSG_ID_AWB_OVERFLOW,
- VFE_MSG_ID_AXI_ERROR,
- VFE_MSG_ID_CAMIF_OVERFLOW,
- VFE_MSG_ID_VIOLATION,
- VFE_MSG_ID_CAMIF_ERROR,
- VFE_MSG_ID_BUS_OVERFLOW,
-};
-
-struct vfe_msg_stats_autofocus {
- uint32_t afBuffer;
- uint32_t frameCounter;
-};
-
-struct vfe_msg_stats_wb_exp {
- uint32_t awbBuffer;
- uint32_t frameCounter;
-};
-
-struct vfe_frame_bpc_info {
- uint32_t greenDefectPixelCount;
- uint32_t redBlueDefectPixelCount;
-};
-
-struct vfe_frame_asf_info {
- uint32_t asfMaxEdge;
- uint32_t asfHbiCount;
-};
-
-struct vfe_msg_camif_status {
- uint8_t camifState;
- uint32_t pixelCount;
- uint32_t lineCount;
-};
-
-struct vfe_bus_pm_per_path {
- uint32_t yWrPmStats0;
- uint32_t yWrPmStats1;
- uint32_t cbcrWrPmStats0;
- uint32_t cbcrWrPmStats1;
-};
-
-struct vfe_bus_performance_monitor {
- struct vfe_bus_pm_per_path encPathPmInfo;
- struct vfe_bus_pm_per_path viewPathPmInfo;
-};
-
-struct vfe_irq_thread_msg {
- uint32_t vfeIrqStatus;
- uint32_t camifStatus;
- uint32_t demosaicStatus;
- uint32_t asfMaxEdge;
- struct vfe_bus_performance_monitor pmInfo;
-};
-
-struct vfe_msg_output {
- uint32_t yBuffer;
- uint32_t cbcrBuffer;
- struct vfe_frame_bpc_info bpcInfo;
- struct vfe_frame_asf_info asfInfo;
- uint32_t frameCounter;
- struct vfe_bus_pm_per_path pmData;
-};
-
-struct vfe_message {
- enum VFE_MESSAGE_ID _d;
- union {
- struct vfe_msg_output msgOutput1;
- struct vfe_msg_output msgOutput2;
- struct vfe_msg_stats_autofocus msgStatsAf;
- struct vfe_msg_stats_wb_exp msgStatsWbExp;
- struct vfe_msg_camif_status msgCamifError;
- struct vfe_bus_performance_monitor msgBusOverflow;
- } _u;
-};
-
-/* New one for 8k */
-struct msm_vfe_command_8k {
- int32_t id;
- uint16_t length;
- void *value;
-};
-
-struct vfe_frame_extra {
- struct vfe_frame_bpc_info bpcInfo;
- struct vfe_frame_asf_info asfInfo;
- uint32_t frameCounter;
- struct vfe_bus_pm_per_path pmData;
-};
-#endif /* __MSM_VFE8X_H__ */
diff --git a/trunk/drivers/staging/dream/camera/msm_vfe8x_proc.c b/trunk/drivers/staging/dream/camera/msm_vfe8x_proc.c
deleted file mode 100644
index f80ef967ba87..000000000000
--- a/trunk/drivers/staging/dream/camera/msm_vfe8x_proc.c
+++ /dev/null
@@ -1,4003 +0,0 @@
-/*
-* Copyright (C) 2008-2009 QUALCOMM Incorporated.
-*/
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include "msm_vfe8x_proc.h"
-#include
-
-struct msm_vfe8x_ctrl {
- /* bit 1:0 ENC_IRQ_MASK = 0x11:
- * generate IRQ when both y and cbcr frame is ready. */
-
- /* bit 1:0 VIEW_IRQ_MASK= 0x11:
- * generate IRQ when both y and cbcr frame is ready. */
- struct vfe_irq_composite_mask_config vfeIrqCompositeMaskLocal;
- struct vfe_module_enable vfeModuleEnableLocal;
- struct vfe_camif_cfg_data vfeCamifConfigLocal;
- struct vfe_interrupt_mask vfeImaskLocal;
- struct vfe_stats_cmd_data vfeStatsCmdLocal;
- struct vfe_bus_cfg_data vfeBusConfigLocal;
- struct vfe_cmd_bus_pm_start vfeBusPmConfigLocal;
- struct vfe_bus_cmd_data vfeBusCmdLocal;
- enum vfe_interrupt_name vfeInterruptNameLocal;
- uint32_t vfeLaBankSel;
- struct vfe_gamma_lut_sel vfeGammaLutSel;
-
- boolean vfeStartAckPendingFlag;
- boolean vfeStopAckPending;
- boolean vfeResetAckPending;
- boolean vfeUpdateAckPending;
-
- enum VFE_AXI_OUTPUT_MODE axiOutputMode;
- enum VFE_START_OPERATION_MODE vfeOperationMode;
-
- uint32_t vfeSnapShotCount;
- uint32_t vfeRequestedSnapShotCount;
- boolean vfeStatsPingPongReloadFlag;
- uint32_t vfeFrameId;
-
- struct vfe_cmd_frame_skip_config vfeFrameSkip;
- uint32_t vfeFrameSkipPattern;
- uint8_t vfeFrameSkipCount;
- uint8_t vfeFrameSkipPeriod;
-
- boolean vfeTestGenStartFlag;
- uint32_t vfeImaskPacked;
- uint32_t vfeImaskCompositePacked;
- enum VFE_RAW_PIXEL_DATA_SIZE axiInputDataSize;
- struct vfe_irq_thread_msg vfeIrqThreadMsgLocal;
-
- struct vfe_output_path_combo viewPath;
- struct vfe_output_path_combo encPath;
- struct vfe_frame_skip_counts vfeDroppedFrameCounts;
- struct vfe_stats_control afStatsControl;
- struct vfe_stats_control awbStatsControl;
-
- enum VFE_STATE vstate;
-
- spinlock_t ack_lock;
- spinlock_t state_lock;
- spinlock_t io_lock;
-
- struct msm_vfe_callback *resp;
- uint32_t extlen;
- void *extdata;
-
- spinlock_t tasklet_lock;
- struct list_head tasklet_q;
-
- int vfeirq;
- void __iomem *vfebase;
-
- void *syncdata;
-};
-static struct msm_vfe8x_ctrl *ctrl;
-static irqreturn_t vfe_parse_irq(int irq_num, void *data);
-
-struct isr_queue_cmd {
- struct list_head list;
- struct vfe_interrupt_status vfeInterruptStatus;
- struct vfe_frame_asf_info vfeAsfFrameInfo;
- struct vfe_frame_bpc_info vfeBpcFrameInfo;
- struct vfe_msg_camif_status vfeCamifStatusLocal;
- struct vfe_bus_performance_monitor vfePmData;
-};
-
-static void vfe_prog_hw(uint8_t *hwreg,
- uint32_t *inptr, uint32_t regcnt)
-{
- /* unsigned long flags; */
- uint32_t i;
- uint32_t *p;
-
- /* @todo This is causing issues, need further investigate */
- /* spin_lock_irqsave(&ctrl->io_lock, flags); */
-
- p = (uint32_t *)(hwreg);
- for (i = 0; i < (regcnt >> 2); i++)
- writel(*inptr++, p++);
- /* *p++ = *inptr++; */
-
- /* spin_unlock_irqrestore(&ctrl->io_lock, flags); */
-}
-
-static void vfe_read_reg_values(uint8_t *hwreg,
- uint32_t *dest, uint32_t count)
-{
- /* unsigned long flags; */
- uint32_t *temp;
- uint32_t i;
-
- /* @todo This is causing issues, need further investigate */
- /* spin_lock_irqsave(&ctrl->io_lock, flags); */
-
- temp = (uint32_t *)(hwreg);
- for (i = 0; i < count; i++)
- *dest++ = *temp++;
-
- /* spin_unlock_irqrestore(&ctrl->io_lock, flags); */
-}
-
-static struct vfe_irqenable vfe_read_irq_mask(void)
-{
- /* unsigned long flags; */
- uint32_t *temp;
- struct vfe_irqenable rc;
-
- memset(&rc, 0, sizeof(rc));
-
- /* @todo This is causing issues, need further investigate */
- /* spin_lock_irqsave(&ctrl->io_lock, flags); */
- temp = (uint32_t *)(ctrl->vfebase + VFE_IRQ_MASK);
-
- rc = *((struct vfe_irqenable *)temp);
- /* spin_unlock_irqrestore(&ctrl->io_lock, flags); */
-
- return rc;
-}
-
-static void
-vfe_set_bus_pipo_addr(struct vfe_output_path_combo *vpath,
- struct vfe_output_path_combo *epath)
-{
- vpath->yPath.hwRegPingAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_VIEW_Y_WR_PING_ADDR);
- vpath->yPath.hwRegPongAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_VIEW_Y_WR_PONG_ADDR);
- vpath->cbcrPath.hwRegPingAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_VIEW_CBCR_WR_PING_ADDR);
- vpath->cbcrPath.hwRegPongAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_VIEW_CBCR_WR_PONG_ADDR);
-
- epath->yPath.hwRegPingAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_ENC_Y_WR_PING_ADDR);
- epath->yPath.hwRegPongAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_ENC_Y_WR_PONG_ADDR);
- epath->cbcrPath.hwRegPingAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_ENC_CBCR_WR_PING_ADDR);
- epath->cbcrPath.hwRegPongAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_ENC_CBCR_WR_PONG_ADDR);
-}
-
-static void vfe_axi_output(struct vfe_cmd_axi_output_config *in,
- struct vfe_output_path_combo *out1,
- struct vfe_output_path_combo *out2, uint16_t out)
-{
- struct vfe_axi_out_cfg cmd;
-
- uint16_t temp;
- uint32_t burstLength;
-
- /* force it to burst length 4, hardware does not support it. */
- burstLength = 1;
-
- /* AXI Output 2 Y Configuration*/
- /* VFE_BUS_ENC_Y_WR_PING_ADDR */
- cmd.out2YPingAddr = out2->yPath.addressBuffer[0];
-
- /* VFE_BUS_ENC_Y_WR_PONG_ADDR */
- cmd.out2YPongAddr = out2->yPath.addressBuffer[1];
-
- /* VFE_BUS_ENC_Y_WR_IMAGE_SIZE */
- cmd.out2YImageHeight = in->output2.outputY.imageHeight;
- /* convert the image width and row increment to be in
- * unit of 64bit (8 bytes) */
- temp = (in->output2.outputY.imageWidth + (out - 1)) /
- out;
- cmd.out2YImageWidthin64bit = temp;
-
- /* VFE_BUS_ENC_Y_WR_BUFFER_CFG */
- cmd.out2YBurstLength = burstLength;
- cmd.out2YNumRows = in->output2.outputY.outRowCount;
- temp = (in->output2.outputY.outRowIncrement + (out - 1)) /
- out;
- cmd.out2YRowIncrementIn64bit = temp;
-
- /* AXI Output 2 Cbcr Configuration*/
- /* VFE_BUS_ENC_Cbcr_WR_PING_ADDR */
- cmd.out2CbcrPingAddr = out2->cbcrPath.addressBuffer[0];
-
- /* VFE_BUS_ENC_Cbcr_WR_PONG_ADDR */
- cmd.out2CbcrPongAddr = out2->cbcrPath.addressBuffer[1];
-
- /* VFE_BUS_ENC_Cbcr_WR_IMAGE_SIZE */
- cmd.out2CbcrImageHeight = in->output2.outputCbcr.imageHeight;
- temp = (in->output2.outputCbcr.imageWidth + (out - 1)) /
- out;
- cmd.out2CbcrImageWidthIn64bit = temp;
-
- /* VFE_BUS_ENC_Cbcr_WR_BUFFER_CFG */
- cmd.out2CbcrBurstLength = burstLength;
- cmd.out2CbcrNumRows = in->output2.outputCbcr.outRowCount;
- temp = (in->output2.outputCbcr.outRowIncrement + (out - 1)) /
- out;
- cmd.out2CbcrRowIncrementIn64bit = temp;
-
- /* AXI Output 1 Y Configuration */
- /* VFE_BUS_VIEW_Y_WR_PING_ADDR */
- cmd.out1YPingAddr = out1->yPath.addressBuffer[0];
-
- /* VFE_BUS_VIEW_Y_WR_PONG_ADDR */
- cmd.out1YPongAddr = out1->yPath.addressBuffer[1];
-
- /* VFE_BUS_VIEW_Y_WR_IMAGE_SIZE */
- cmd.out1YImageHeight = in->output1.outputY.imageHeight;
- temp = (in->output1.outputY.imageWidth + (out - 1)) /
- out;
- cmd.out1YImageWidthin64bit = temp;
-
- /* VFE_BUS_VIEW_Y_WR_BUFFER_CFG */
- cmd.out1YBurstLength = burstLength;
- cmd.out1YNumRows = in->output1.outputY.outRowCount;
-
- temp =
- (in->output1.outputY.outRowIncrement +
- (out - 1)) / out;
- cmd.out1YRowIncrementIn64bit = temp;
-
- /* AXI Output 1 Cbcr Configuration*/
- cmd.out1CbcrPingAddr = out1->cbcrPath.addressBuffer[0];
-
- /* VFE_BUS_VIEW_Cbcr_WR_PONG_ADDR */
- cmd.out1CbcrPongAddr =
- out1->cbcrPath.addressBuffer[1];
-
- /* VFE_BUS_VIEW_Cbcr_WR_IMAGE_SIZE */
- cmd.out1CbcrImageHeight = in->output1.outputCbcr.imageHeight;
- temp = (in->output1.outputCbcr.imageWidth +
- (out - 1)) / out;
- cmd.out1CbcrImageWidthIn64bit = temp;
-
- cmd.out1CbcrBurstLength = burstLength;
- cmd.out1CbcrNumRows = in->output1.outputCbcr.outRowCount;
- temp =
- (in->output1.outputCbcr.outRowIncrement +
- (out - 1)) / out;
-
- cmd.out1CbcrRowIncrementIn64bit = temp;
-
- vfe_prog_hw(ctrl->vfebase + VFE_BUS_ENC_Y_WR_PING_ADDR,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-static void vfe_reg_bus_cfg(struct vfe_bus_cfg_data *in)
-{
- struct vfe_axi_bus_cfg cmd;
-
- cmd.stripeRdPathEn = in->stripeRdPathEn;
- cmd.encYWrPathEn = in->encYWrPathEn;
- cmd.encCbcrWrPathEn = in->encCbcrWrPathEn;
- cmd.viewYWrPathEn = in->viewYWrPathEn;
- cmd.viewCbcrWrPathEn = in->viewCbcrWrPathEn;
- cmd.rawPixelDataSize = (uint32_t)in->rawPixelDataSize;
- cmd.rawWritePathSelect = (uint32_t)in->rawWritePathSelect;
-
- /* program vfe_bus_cfg */
- writel(*((uint32_t *)&cmd), ctrl->vfebase + VFE_BUS_CFG);
-}
-
-static void vfe_reg_camif_config(struct vfe_camif_cfg_data *in)
-{
- struct VFE_CAMIFConfigType cfg;
-
- memset(&cfg, 0, sizeof(cfg));
-
- cfg.VSyncEdge =
- in->camifCfgFromCmd.vSyncEdge;
-
- cfg.HSyncEdge =
- in->camifCfgFromCmd.hSyncEdge;
-
- cfg.syncMode =
- in->camifCfgFromCmd.syncMode;
-
- cfg.vfeSubsampleEnable =
- in->camifCfgFromCmd.vfeSubSampleEnable;
-
- cfg.busSubsampleEnable =
- in->camifCfgFromCmd.busSubSampleEnable;
-
- cfg.camif2vfeEnable =
- in->camif2OutputEnable;
-
- cfg.camif2busEnable =
- in->camif2BusEnable;
-
- cfg.irqSubsampleEnable =
- in->camifCfgFromCmd.irqSubSampleEnable;
-
- cfg.binningEnable =
- in->camifCfgFromCmd.binningEnable;
-
- cfg.misrEnable =
- in->camifCfgFromCmd.misrEnable;
-
- /* program camif_config */
- writel(*((uint32_t *)&cfg), ctrl->vfebase + CAMIF_CONFIG);
-}
-
-static void vfe_reg_bus_cmd(struct vfe_bus_cmd_data *in)
-{
- struct vfe_buscmd cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- cmd.stripeReload = in->stripeReload;
- cmd.busPingpongReload = in->busPingpongReload;
- cmd.statsPingpongReload = in->statsPingpongReload;
-
- writel(*((uint32_t *)&cmd), ctrl->vfebase + VFE_BUS_CMD);
-
- CDBG("bus command = 0x%x\n", (*((uint32_t *)&cmd)));
-
- /* this is needed, as the control bits are pulse based.
- * Don't want to reload bus pingpong again. */
- in->busPingpongReload = 0;
- in->statsPingpongReload = 0;
- in->stripeReload = 0;
-}
-
-static void vfe_reg_module_cfg(struct vfe_module_enable *in)
-{
- struct vfe_mod_enable ena;
-
- memset(&ena, 0, sizeof(ena));
-
- ena.blackLevelCorrectionEnable = in->blackLevelCorrectionEnable;
- ena.lensRollOffEnable = in->lensRollOffEnable;
- ena.demuxEnable = in->demuxEnable;
- ena.chromaUpsampleEnable = in->chromaUpsampleEnable;
- ena.demosaicEnable = in->demosaicEnable;
- ena.statsEnable = in->statsEnable;
- ena.cropEnable = in->cropEnable;
- ena.mainScalerEnable = in->mainScalerEnable;
- ena.whiteBalanceEnable = in->whiteBalanceEnable;
- ena.colorCorrectionEnable = in->colorCorrectionEnable;
- ena.yHistEnable = in->yHistEnable;
- ena.skinToneEnable = in->skinToneEnable;
- ena.lumaAdaptationEnable = in->lumaAdaptationEnable;
- ena.rgbLUTEnable = in->rgbLUTEnable;
- ena.chromaEnhanEnable = in->chromaEnhanEnable;
- ena.asfEnable = in->asfEnable;
- ena.chromaSuppressionEnable = in->chromaSuppressionEnable;
- ena.chromaSubsampleEnable = in->chromaSubsampleEnable;
- ena.scaler2YEnable = in->scaler2YEnable;
- ena.scaler2CbcrEnable = in->scaler2CbcrEnable;
-
- writel(*((uint32_t *)&ena), ctrl->vfebase + VFE_MODULE_CFG);
-}
-
-static void vfe_program_dmi_cfg(enum VFE_DMI_RAM_SEL bankSel)
-{
- /* set bit 8 for auto increment. */
- uint32_t value = (uint32_t) ctrl->vfebase + VFE_DMI_CFG_DEFAULT;
-
- value += (uint32_t)bankSel;
- /* CDBG("dmi cfg input bank is 0x%x\n", bankSel); */
-
- writel(value, ctrl->vfebase + VFE_DMI_CFG);
- writel(0, ctrl->vfebase + VFE_DMI_ADDR);
-}
-
-static void vfe_write_lens_roll_off_table(
- struct vfe_cmd_roll_off_config *in)
-{
- uint16_t i;
- uint32_t data;
-
- uint16_t *initGr = in->initTableGr;
- uint16_t *initGb = in->initTableGb;
- uint16_t *initB = in->initTableB;
- uint16_t *initR = in->initTableR;
-
- int16_t *pDeltaGr = in->deltaTableGr;
- int16_t *pDeltaGb = in->deltaTableGb;
- int16_t *pDeltaB = in->deltaTableB;
- int16_t *pDeltaR = in->deltaTableR;
-
- vfe_program_dmi_cfg(ROLLOFF_RAM);
-
- /* first pack and write init table */
- for (i = 0; i < VFE_ROLL_OFF_INIT_TABLE_SIZE; i++) {
- data = (((uint32_t)(*initR)) & 0x0000FFFF) |
- (((uint32_t)(*initGr)) << 16);
- initR++;
- initGr++;
-
- writel(data, ctrl->vfebase + VFE_DMI_DATA_LO);
-
- data = (((uint32_t)(*initB)) & 0x0000FFFF) |
- (((uint32_t)(*initGr))<<16);
- initB++;
- initGb++;
-
- writel(data, ctrl->vfebase + VFE_DMI_DATA_LO);
- }
-
- /* there are gaps between the init table and delta table,
- * set the offset for delta table. */
- writel(LENS_ROLL_OFF_DELTA_TABLE_OFFSET,
- ctrl->vfebase + VFE_DMI_ADDR);
-
- /* pack and write delta table */
- for (i = 0; i < VFE_ROLL_OFF_DELTA_TABLE_SIZE; i++) {
- data = (((int32_t)(*pDeltaR)) & 0x0000FFFF) |
- (((int32_t)(*pDeltaGr))<<16);
- pDeltaR++;
- pDeltaGr++;
-
- writel(data, ctrl->vfebase + VFE_DMI_DATA_LO);
-
- data = (((int32_t)(*pDeltaB)) & 0x0000FFFF) |
- (((int32_t)(*pDeltaGb))<<16);
- pDeltaB++;
- pDeltaGb++;
-
- writel(data, ctrl->vfebase + VFE_DMI_DATA_LO);
- }
-
- /* After DMI transfer, to make it safe, need to set the
- * DMI_CFG to unselect any SRAM
- */
- /* unselect the SRAM Bank. */
- writel(VFE_DMI_CFG_DEFAULT, ctrl->vfebase + VFE_DMI_CFG);
-}
-
-static void vfe_set_default_reg_values(void)
-{
- writel(0x800080, ctrl->vfebase + VFE_DEMUX_GAIN_0);
- writel(0x800080, ctrl->vfebase + VFE_DEMUX_GAIN_1);
- writel(0xFFFFF, ctrl->vfebase + VFE_CGC_OVERRIDE);
-
- /* default frame drop period and pattern */
- writel(0x1f, ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG);
- writel(0x1f, ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_CFG);
- writel(0xFFFFFFFF, ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN);
- writel(0xFFFFFFFF, ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_PATTERN);
- writel(0x1f, ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y_CFG);
- writel(0x1f, ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR_CFG);
- writel(0xFFFFFFFF, ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y_PATTERN);
- writel(0xFFFFFFFF, ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR_PATTERN);
- writel(0, ctrl->vfebase + VFE_CLAMP_MIN_CFG);
- writel(0xFFFFFF, ctrl->vfebase + VFE_CLAMP_MAX_CFG);
-}
-
-static void vfe_config_demux(uint32_t period, uint32_t even, uint32_t odd)
-{
- writel(period, ctrl->vfebase + VFE_DEMUX_CFG);
- writel(even, ctrl->vfebase + VFE_DEMUX_EVEN_CFG);
- writel(odd, ctrl->vfebase + VFE_DEMUX_ODD_CFG);
-}
-
-static void vfe_pm_stop(void)
-{
- writel(VFE_PERFORMANCE_MONITOR_STOP, ctrl->vfebase + VFE_BUS_PM_CMD);
-}
-
-static void vfe_program_bus_rd_irq_en(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_BUS_PINGPONG_IRQ_EN);
-}
-
-static void vfe_camif_go(void)
-{
- writel(CAMIF_COMMAND_START, ctrl->vfebase + CAMIF_COMMAND);
-}
-
-static void vfe_camif_stop_immediately(void)
-{
- writel(CAMIF_COMMAND_STOP_IMMEDIATELY, ctrl->vfebase + CAMIF_COMMAND);
- writel(0, ctrl->vfebase + VFE_CGC_OVERRIDE);
-}
-
-static void vfe_program_reg_update_cmd(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_REG_UPDATE_CMD);
-}
-
-static void vfe_program_bus_cmd(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_BUS_CMD);
-}
-
-static void vfe_program_global_reset_cmd(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_GLOBAL_RESET_CMD);
-}
-
-static void vfe_program_axi_cmd(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_AXI_CMD);
-}
-
-static void vfe_program_irq_composite_mask(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_IRQ_COMPOSITE_MASK);
-}
-
-static inline void vfe_program_irq_mask(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_IRQ_MASK);
-}
-
-static void vfe_program_chroma_upsample_cfg(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_CHROMA_UPSAMPLE_CFG);
-}
-
-static uint32_t vfe_read_axi_status(void)
-{
- return readl(ctrl->vfebase + VFE_AXI_STATUS);
-}
-
-static uint32_t vfe_read_pm_status_in_raw_capture(void)
-{
- return readl(ctrl->vfebase + VFE_BUS_ENC_CBCR_WR_PM_STATS_1);
-}
-
-static void
-vfe_set_stats_pingpong_address(struct vfe_stats_control *afControl,
- struct vfe_stats_control *awbControl)
-{
- afControl->hwRegPingAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
- afControl->hwRegPongAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
-
- awbControl->hwRegPingAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
- awbControl->hwRegPongAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
-}
-
-static uint32_t vfe_read_camif_status(void)
-{
- return readl(ctrl->vfebase + CAMIF_STATUS);
-}
-
-static void vfe_program_lut_bank_sel(struct vfe_gamma_lut_sel *in)
-{
- struct VFE_GammaLutSelect_ConfigCmdType cmd;
-
- memset(&cmd, 0, sizeof(cmd));
-
- cmd.ch0BankSelect = in->ch0BankSelect;
- cmd.ch1BankSelect = in->ch1BankSelect;
- cmd.ch2BankSelect = in->ch2BankSelect;
- CDBG("VFE gamma lut bank selection is 0x%x\n", *((uint32_t *)&cmd));
- vfe_prog_hw(ctrl->vfebase + VFE_LUT_BANK_SEL,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-static void vfe_program_stats_cmd(struct vfe_stats_cmd_data *in)
-{
- struct VFE_StatsCmdType stats;
- memset(&stats, 0, sizeof(stats));
-
- stats.autoFocusEnable = in->autoFocusEnable;
- stats.axwEnable = in->axwEnable;
- stats.histEnable = in->histEnable;
- stats.clearHistEnable = in->clearHistEnable;
- stats.histAutoClearEnable = in->histAutoClearEnable;
- stats.colorConversionEnable = in->colorConversionEnable;
-
- writel(*((uint32_t *)&stats), ctrl->vfebase + VFE_STATS_CMD);
-}
-
-static void vfe_pm_start(struct vfe_cmd_bus_pm_start *in)
-{
- struct VFE_Bus_Pm_ConfigCmdType cmd;
- memset(&cmd, 0, sizeof(struct VFE_Bus_Pm_ConfigCmdType));
-
- cmd.output2YWrPmEnable = in->output2YWrPmEnable;
- cmd.output2CbcrWrPmEnable = in->output2CbcrWrPmEnable;
- cmd.output1YWrPmEnable = in->output1YWrPmEnable;
- cmd.output1CbcrWrPmEnable = in->output1CbcrWrPmEnable;
-
- vfe_prog_hw(ctrl->vfebase + VFE_BUS_PM_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-static void vfe_8k_pm_start(struct vfe_cmd_bus_pm_start *in)
-{
- in->output1CbcrWrPmEnable = ctrl->vfeBusConfigLocal.viewCbcrWrPathEn;
- in->output1YWrPmEnable = ctrl->vfeBusConfigLocal.viewYWrPathEn;
- in->output2CbcrWrPmEnable = ctrl->vfeBusConfigLocal.encCbcrWrPathEn;
- in->output2YWrPmEnable = ctrl->vfeBusConfigLocal.encYWrPathEn;
-
- if (in->output1CbcrWrPmEnable || in->output1YWrPmEnable)
- ctrl->viewPath.pmEnabled = TRUE;
-
- if (in->output2CbcrWrPmEnable || in->output2YWrPmEnable)
- ctrl->encPath.pmEnabled = TRUE;
-
- vfe_pm_start(in);
-
- writel(VFE_PERFORMANCE_MONITOR_GO, ctrl->vfebase + VFE_BUS_PM_CMD);
-}
-
-static uint32_t vfe_irq_pack(struct vfe_interrupt_mask data)
-{
- struct vfe_irqenable packedData;
-
- memset(&packedData, 0, sizeof(packedData));
-
- packedData.camifErrorIrq = data.camifErrorIrq;
- packedData.camifSofIrq = data.camifSofIrq;
- packedData.camifEolIrq = data.camifEolIrq;
- packedData.camifEofIrq = data.camifEofIrq;
- packedData.camifEpoch1Irq = data.camifEpoch1Irq;
- packedData.camifEpoch2Irq = data.camifEpoch2Irq;
- packedData.camifOverflowIrq = data.camifOverflowIrq;
- packedData.ceIrq = data.ceIrq;
- packedData.regUpdateIrq = data.regUpdateIrq;
- packedData.resetAckIrq = data.resetAckIrq;
- packedData.encYPingpongIrq = data.encYPingpongIrq;
- packedData.encCbcrPingpongIrq = data.encCbcrPingpongIrq;
- packedData.viewYPingpongIrq = data.viewYPingpongIrq;
- packedData.viewCbcrPingpongIrq = data.viewCbcrPingpongIrq;
- packedData.rdPingpongIrq = data.rdPingpongIrq;
- packedData.afPingpongIrq = data.afPingpongIrq;
- packedData.awbPingpongIrq = data.awbPingpongIrq;
- packedData.histPingpongIrq = data.histPingpongIrq;
- packedData.encIrq = data.encIrq;
- packedData.viewIrq = data.viewIrq;
- packedData.busOverflowIrq = data.busOverflowIrq;
- packedData.afOverflowIrq = data.afOverflowIrq;
- packedData.awbOverflowIrq = data.awbOverflowIrq;
- packedData.syncTimer0Irq = data.syncTimer0Irq;
- packedData.syncTimer1Irq = data.syncTimer1Irq;
- packedData.syncTimer2Irq = data.syncTimer2Irq;
- packedData.asyncTimer0Irq = data.asyncTimer0Irq;
- packedData.asyncTimer1Irq = data.asyncTimer1Irq;
- packedData.asyncTimer2Irq = data.asyncTimer2Irq;
- packedData.asyncTimer3Irq = data.asyncTimer3Irq;
- packedData.axiErrorIrq = data.axiErrorIrq;
- packedData.violationIrq = data.violationIrq;
-
- return *((uint32_t *)&packedData);
-}
-
-static uint32_t
-vfe_irq_composite_pack(struct vfe_irq_composite_mask_config data)
-{
- struct VFE_Irq_Composite_MaskType packedData;
-
- memset(&packedData, 0, sizeof(packedData));
-
- packedData.encIrqComMaskBits = data.encIrqComMask;
- packedData.viewIrqComMaskBits = data.viewIrqComMask;
- packedData.ceDoneSelBits = data.ceDoneSel;
-
- return *((uint32_t *)&packedData);
-}
-
-static void vfe_addr_convert(struct msm_vfe_phy_info *pinfo,
- enum vfe_resp_msg type, void *data, void **ext, int32_t *elen)
-{
- switch (type) {
- case VFE_MSG_OUTPUT1: {
- pinfo->y_phy =
- ((struct vfe_message *)data)->_u.msgOutput1.yBuffer;
- pinfo->cbcr_phy =
- ((struct vfe_message *)data)->_u.msgOutput1.cbcrBuffer;
-
- ((struct vfe_frame_extra *)ctrl->extdata)->bpcInfo =
- ((struct vfe_message *)data)->_u.msgOutput1.bpcInfo;
-
- ((struct vfe_frame_extra *)ctrl->extdata)->asfInfo =
- ((struct vfe_message *)data)->_u.msgOutput1.asfInfo;
-
- ((struct vfe_frame_extra *)ctrl->extdata)->frameCounter =
- ((struct vfe_message *)data)->_u.msgOutput1.frameCounter;
-
- ((struct vfe_frame_extra *)ctrl->extdata)->pmData =
- ((struct vfe_message *)data)->_u.msgOutput1.pmData;
-
- *ext = ctrl->extdata;
- *elen = ctrl->extlen;
- }
- break;
-
- case VFE_MSG_OUTPUT2: {
- pinfo->y_phy =
- ((struct vfe_message *)data)->_u.msgOutput2.yBuffer;
- pinfo->cbcr_phy =
- ((struct vfe_message *)data)->_u.msgOutput2.cbcrBuffer;
-
- CDBG("vfe_addr_convert, pinfo->y_phy = 0x%x\n", pinfo->y_phy);
- CDBG("vfe_addr_convert, pinfo->cbcr_phy = 0x%x\n",
- pinfo->cbcr_phy);
-
- ((struct vfe_frame_extra *)ctrl->extdata)->bpcInfo =
- ((struct vfe_message *)data)->_u.msgOutput2.bpcInfo;
-
- ((struct vfe_frame_extra *)ctrl->extdata)->asfInfo =
- ((struct vfe_message *)data)->_u.msgOutput2.asfInfo;
-
- ((struct vfe_frame_extra *)ctrl->extdata)->frameCounter =
- ((struct vfe_message *)data)->_u.msgOutput2.frameCounter;
-
- ((struct vfe_frame_extra *)ctrl->extdata)->pmData =
- ((struct vfe_message *)data)->_u.msgOutput2.pmData;
-
- *ext = ctrl->extdata;
- *elen = ctrl->extlen;
- }
- break;
-
- case VFE_MSG_STATS_AF:
- pinfo->sbuf_phy =
- ((struct vfe_message *)data)->_u.msgStatsAf.afBuffer;
- break;
-
- case VFE_MSG_STATS_WE:
- pinfo->sbuf_phy =
- ((struct vfe_message *)data)->_u.msgStatsWbExp.awbBuffer;
- break;
-
- default:
- break;
- } /* switch */
-}
-
-static void
-vfe_proc_ops(enum VFE_MESSAGE_ID id, void *msg, size_t len)
-{
- struct msm_vfe_resp *rp;
-
- /* In 8k, OUTPUT1 & OUTPUT2 messages arrive before
- * SNAPSHOT_DONE. We don't send such messages to user */
-
- CDBG("ctrl->vfeOperationMode = %d, msgId = %d\n",
- ctrl->vfeOperationMode, id);
-
- if ((ctrl->vfeOperationMode == VFE_START_OPERATION_MODE_SNAPSHOT) &&
- (id == VFE_MSG_ID_OUTPUT1 || id == VFE_MSG_ID_OUTPUT2)) {
- return;
- }
-
- rp = ctrl->resp->vfe_alloc(sizeof(struct msm_vfe_resp), ctrl->syncdata);
- if (!rp) {
- CDBG("rp: cannot allocate buffer\n");
- return;
- }
-
- CDBG("vfe_proc_ops, msgId = %d\n", id);
-
- rp->evt_msg.type = MSM_CAMERA_MSG;
- rp->evt_msg.msg_id = id;
- rp->evt_msg.len = len;
- rp->evt_msg.data = msg;
-
- switch (rp->evt_msg.msg_id) {
- case VFE_MSG_ID_SNAPSHOT_DONE:
- rp->type = VFE_MSG_SNAPSHOT;
- break;
-
- case VFE_MSG_ID_OUTPUT1:
- rp->type = VFE_MSG_OUTPUT1;
- vfe_addr_convert(&(rp->phy), VFE_MSG_OUTPUT1,
- rp->evt_msg.data, &(rp->extdata),
- &(rp->extlen));
- break;
-
- case VFE_MSG_ID_OUTPUT2:
- rp->type = VFE_MSG_OUTPUT2;
- vfe_addr_convert(&(rp->phy), VFE_MSG_OUTPUT2,
- rp->evt_msg.data, &(rp->extdata),
- &(rp->extlen));
- break;
-
- case VFE_MSG_ID_STATS_AUTOFOCUS:
- rp->type = VFE_MSG_STATS_AF;
- vfe_addr_convert(&(rp->phy), VFE_MSG_STATS_AF,
- rp->evt_msg.data, NULL, NULL);
- break;
-
- case VFE_MSG_ID_STATS_WB_EXP:
- rp->type = VFE_MSG_STATS_WE;
- vfe_addr_convert(&(rp->phy), VFE_MSG_STATS_WE,
- rp->evt_msg.data, NULL, NULL);
- break;
-
- default:
- rp->type = VFE_MSG_GENERAL;
- break;
- }
-
- ctrl->resp->vfe_resp(rp, MSM_CAM_Q_VFE_MSG, ctrl->syncdata);
-}
-
-static void vfe_send_msg_no_payload(enum VFE_MESSAGE_ID id)
-{
- struct vfe_message *msg;
-
- msg = kzalloc(sizeof(*msg), GFP_ATOMIC);
- if (!msg)
- return;
-
- msg->_d = id;
- vfe_proc_ops(id, msg, 0);
-}
-
-static void vfe_send_bus_overflow_msg(void)
-{
- struct vfe_message *msg;
- msg =
- kzalloc(sizeof(struct vfe_message), GFP_ATOMIC);
- if (!msg)
- return;
-
- msg->_d = VFE_MSG_ID_BUS_OVERFLOW;
-#if 0
- memcpy(&(msg->_u.msgBusOverflow),
- &ctrl->vfePmData, sizeof(ctrl->vfePmData));
-#endif
-
- vfe_proc_ops(VFE_MSG_ID_BUS_OVERFLOW,
- msg, sizeof(struct vfe_message));
-}
-
-static void vfe_send_camif_error_msg(void)
-{
-#if 0
- struct vfe_message *msg;
- msg =
- kzalloc(sizeof(struct vfe_message), GFP_ATOMIC);
- if (!msg)
- return;
-
- msg->_d = VFE_MSG_ID_CAMIF_ERROR;
- memcpy(&(msg->_u.msgCamifError),
- &ctrl->vfeCamifStatusLocal, sizeof(ctrl->vfeCamifStatusLocal));
-
- vfe_proc_ops(VFE_MSG_ID_CAMIF_ERROR,
- msg, sizeof(struct vfe_message));
-#endif
-}
-
-static void vfe_process_error_irq(
- struct vfe_interrupt_status *irqstatus)
-{
- /* all possible error irq. Note error irqs are not enabled, it is
- * checked only when other interrupts are present. */
- if (irqstatus->afOverflowIrq)
- vfe_send_msg_no_payload(VFE_MSG_ID_AF_OVERFLOW);
-
- if (irqstatus->awbOverflowIrq)
- vfe_send_msg_no_payload(VFE_MSG_ID_AWB_OVERFLOW);
-
- if (irqstatus->axiErrorIrq)
- vfe_send_msg_no_payload(VFE_MSG_ID_AXI_ERROR);
-
- if (irqstatus->busOverflowIrq)
- vfe_send_bus_overflow_msg();
-
- if (irqstatus->camifErrorIrq)
- vfe_send_camif_error_msg();
-
- if (irqstatus->camifOverflowIrq)
- vfe_send_msg_no_payload(VFE_MSG_ID_CAMIF_OVERFLOW);
-
- if (irqstatus->violationIrq)
- ;
-}
-
-static void vfe_process_camif_sof_irq(void)
-{
- /* increment the frame id number. */
- ctrl->vfeFrameId++;
-
- CDBG("camif_sof_irq, frameId = %d\n",
- ctrl->vfeFrameId);
-
- /* In snapshot mode, if frame skip is programmed,
- * need to check it accordingly to stop camif at
- * correct frame boundary. For the dropped frames,
- * there won't be any output path irqs, but there is
- * still SOF irq, which can help us determine when
- * to stop the camif.
- */
- if (ctrl->vfeOperationMode) {
- if ((1 << ctrl->vfeFrameSkipCount) &
- ctrl->vfeFrameSkipPattern) {
-
- ctrl->vfeSnapShotCount--;
- if (ctrl->vfeSnapShotCount == 0)
- /* terminate vfe pipeline at frame boundary. */
- writel(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
- ctrl->vfebase + CAMIF_COMMAND);
- }
-
- /* update frame skip counter for bit checking. */
- ctrl->vfeFrameSkipCount++;
- if (ctrl->vfeFrameSkipCount ==
- (ctrl->vfeFrameSkipPeriod + 1))
- ctrl->vfeFrameSkipCount = 0;
- }
-}
-
-static int vfe_get_af_pingpong_status(void)
-{
- uint32_t busPingPongStatus;
- int rc = 0;
-
- busPingPongStatus =
- readl(ctrl->vfebase + VFE_BUS_PINGPONG_STATUS);
-
- if ((busPingPongStatus & VFE_AF_PINGPONG_STATUS_BIT) == 0)
- return -EFAULT;
-
- return rc;
-}
-
-static uint32_t vfe_read_af_buf_addr(boolean pipo)
-{
- if (pipo == FALSE)
- return readl(ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
- else
- return readl(ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
-}
-
-static void
-vfe_update_af_buf_addr(boolean pipo, uint32_t addr)
-{
- if (pipo == FALSE)
- writel(addr, ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
- else
- writel(addr, ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
-}
-
-static void
-vfe_send_af_stats_msg(uint32_t afBufAddress)
-{
- /* unsigned long flags; */
- struct vfe_message *msg;
- msg =
- kzalloc(sizeof(struct vfe_message), GFP_ATOMIC);
- if (!msg)
- return;
-
- /* fill message with right content. */
- /* @todo This is causing issues, need further investigate */
- /* spin_lock_irqsave(&ctrl->state_lock, flags); */
- if (ctrl->vstate != VFE_STATE_ACTIVE) {
- kfree(msg);
- goto af_stats_done;
- }
-
- msg->_d = VFE_MSG_ID_STATS_AUTOFOCUS;
- msg->_u.msgStatsAf.afBuffer = afBufAddress;
- msg->_u.msgStatsAf.frameCounter = ctrl->vfeFrameId;
-
- vfe_proc_ops(VFE_MSG_ID_STATS_AUTOFOCUS,
- msg, sizeof(struct vfe_message));
-
- ctrl->afStatsControl.ackPending = TRUE;
-
-af_stats_done:
- /* spin_unlock_irqrestore(&ctrl->state_lock, flags); */
- return;
-}
-
-static void vfe_process_stats_af_irq(void)
-{
- boolean bufferAvailable;
-
- if (!(ctrl->afStatsControl.ackPending)) {
-
- /* read hardware status. */
- ctrl->afStatsControl.pingPongStatus =
- vfe_get_af_pingpong_status();
-
- bufferAvailable =
- (ctrl->afStatsControl.pingPongStatus) ^ 1;
-
- ctrl->afStatsControl.bufToRender =
- vfe_read_af_buf_addr(bufferAvailable);
-
- /* update the same buffer address (ping or pong) */
- vfe_update_af_buf_addr(bufferAvailable,
- ctrl->afStatsControl.nextFrameAddrBuf);
-
- vfe_send_af_stats_msg(ctrl->afStatsControl.bufToRender);
- } else
- ctrl->afStatsControl.droppedStatsFrameCount++;
-}
-
-static boolean vfe_get_awb_pingpong_status(void)
-{
- uint32_t busPingPongStatus;
-
- busPingPongStatus =
- readl(ctrl->vfebase + VFE_BUS_PINGPONG_STATUS);
-
- if ((busPingPongStatus & VFE_AWB_PINGPONG_STATUS_BIT) == 0)
- return FALSE;
-
- return TRUE;
-}
-
-static uint32_t
-vfe_read_awb_buf_addr(boolean pingpong)
-{
- if (pingpong == FALSE)
- return readl(ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
- else
- return readl(ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
-}
-
-static void vfe_update_awb_buf_addr(
- boolean pingpong, uint32_t addr)
-{
- if (pingpong == FALSE)
- writel(addr, ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
- else
- writel(addr, ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
-}
-
-static void vfe_send_awb_stats_msg(uint32_t awbBufAddress)
-{
- /* unsigned long flags; */
- struct vfe_message *msg;
-
- msg =
- kzalloc(sizeof(struct vfe_message), GFP_ATOMIC);
- if (!msg)
- return;
-
- /* fill message with right content. */
- /* @todo This is causing issues, need further investigate */
- /* spin_lock_irqsave(&ctrl->state_lock, flags); */
- if (ctrl->vstate != VFE_STATE_ACTIVE) {
- kfree(msg);
- goto awb_stats_done;
- }
-
- msg->_d = VFE_MSG_ID_STATS_WB_EXP;
- msg->_u.msgStatsWbExp.awbBuffer = awbBufAddress;
- msg->_u.msgStatsWbExp.frameCounter = ctrl->vfeFrameId;
-
- vfe_proc_ops(VFE_MSG_ID_STATS_WB_EXP,
- msg, sizeof(struct vfe_message));
-
- ctrl->awbStatsControl.ackPending = TRUE;
-
-awb_stats_done:
- /* spin_unlock_irqrestore(&ctrl->state_lock, flags); */
- return;
-}
-
-static void vfe_process_stats_awb_irq(void)
-{
- boolean bufferAvailable;
-
- if (!(ctrl->awbStatsControl.ackPending)) {
-
- ctrl->awbStatsControl.pingPongStatus =
- vfe_get_awb_pingpong_status();
-
- bufferAvailable = (ctrl->awbStatsControl.pingPongStatus) ^ 1;
-
- ctrl->awbStatsControl.bufToRender =
- vfe_read_awb_buf_addr(bufferAvailable);
-
- vfe_update_awb_buf_addr(bufferAvailable,
- ctrl->awbStatsControl.nextFrameAddrBuf);
-
- vfe_send_awb_stats_msg(ctrl->awbStatsControl.bufToRender);
-
- } else
- ctrl->awbStatsControl.droppedStatsFrameCount++;
-}
-
-static void vfe_process_sync_timer_irq(
- struct vfe_interrupt_status *irqstatus)
-{
- if (irqstatus->syncTimer0Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_SYNC_TIMER0_DONE);
-
- if (irqstatus->syncTimer1Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_SYNC_TIMER1_DONE);
-
- if (irqstatus->syncTimer2Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_SYNC_TIMER2_DONE);
-}
-
-static void vfe_process_async_timer_irq(
- struct vfe_interrupt_status *irqstatus)
-{
-
- if (irqstatus->asyncTimer0Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_ASYNC_TIMER0_DONE);
-
- if (irqstatus->asyncTimer1Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_ASYNC_TIMER1_DONE);
-
- if (irqstatus->asyncTimer2Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_ASYNC_TIMER2_DONE);
-
- if (irqstatus->asyncTimer3Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_ASYNC_TIMER3_DONE);
-}
-
-static void vfe_send_violation_msg(void)
-{
- vfe_send_msg_no_payload(VFE_MSG_ID_VIOLATION);
-}
-
-static void vfe_send_async_timer_msg(void)
-{
- vfe_send_msg_no_payload(VFE_MSG_ID_ASYNC_TIMER0_DONE);
-}
-
-static void vfe_write_gamma_table(uint8_t channel,
- boolean bank, int16_t *pTable)
-{
- uint16_t i;
-
- enum VFE_DMI_RAM_SEL dmiRamSel = NO_MEM_SELECTED;
-
- switch (channel) {
- case 0:
- if (bank == 0)
- dmiRamSel = RGBLUT_RAM_CH0_BANK0;
- else
- dmiRamSel = RGBLUT_RAM_CH0_BANK1;
- break;
-
- case 1:
- if (bank == 0)
- dmiRamSel = RGBLUT_RAM_CH1_BANK0;
- else
- dmiRamSel = RGBLUT_RAM_CH1_BANK1;
- break;
-
- case 2:
- if (bank == 0)
- dmiRamSel = RGBLUT_RAM_CH2_BANK0;
- else
- dmiRamSel = RGBLUT_RAM_CH2_BANK1;
- break;
-
- default:
- break;
- }
-
- vfe_program_dmi_cfg(dmiRamSel);
-
- for (i = 0; i < VFE_GAMMA_TABLE_LENGTH; i++) {
- writel((uint32_t)(*pTable), ctrl->vfebase + VFE_DMI_DATA_LO);
- pTable++;
- }
-
- /* After DMI transfer, need to set the DMI_CFG to unselect any SRAM
- unselect the SRAM Bank. */
- writel(VFE_DMI_CFG_DEFAULT, ctrl->vfebase + VFE_DMI_CFG);
-}
-
-static void vfe_prog_hw_testgen_cmd(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_HW_TESTGEN_CMD);
-}
-
-static inline void vfe_read_irq_status(struct vfe_irq_thread_msg *out)
-{
- uint32_t *temp;
-
- memset(out, 0, sizeof(struct vfe_irq_thread_msg));
-
- temp = (uint32_t *)(ctrl->vfebase + VFE_IRQ_STATUS);
- out->vfeIrqStatus = readl(temp);
-
- temp = (uint32_t *)(ctrl->vfebase + CAMIF_STATUS);
- out->camifStatus = readl(temp);
- writel(0x7, ctrl->vfebase + CAMIF_COMMAND);
- writel(0x3, ctrl->vfebase + CAMIF_COMMAND);
- CDBG("camifStatus = 0x%x\n", out->camifStatus);
-
-/*
- temp = (uint32_t *)(ctrl->vfebase + VFE_DEMOSAIC_STATUS);
- out->demosaicStatus = readl(temp);
-
- temp = (uint32_t *)(ctrl->vfebase + VFE_ASF_MAX_EDGE);
- out->asfMaxEdge = readl(temp);
-
- temp = (uint32_t *)(ctrl->vfebase + VFE_BUS_ENC_Y_WR_PM_STATS_0);
-*/
-
-#if 0
- out->pmInfo.encPathPmInfo.yWrPmStats0 = readl(temp++);
- out->pmInfo.encPathPmInfo.yWrPmStats1 = readl(temp++);
- out->pmInfo.encPathPmInfo.cbcrWrPmStats0 = readl(temp++);
- out->pmInfo.encPathPmInfo.cbcrWrPmStats1 = readl(temp++);
- out->pmInfo.viewPathPmInfo.yWrPmStats0 = readl(temp++);
- out->pmInfo.viewPathPmInfo.yWrPmStats1 = readl(temp++);
- out->pmInfo.viewPathPmInfo.cbcrWrPmStats0 = readl(temp++);
- out->pmInfo.viewPathPmInfo.cbcrWrPmStats1 = readl(temp);
-#endif /* if 0 Jeff */
-}
-
-static struct vfe_interrupt_status
-vfe_parse_interrupt_status(uint32_t irqStatusIn)
-{
- struct vfe_irqenable hwstat;
- struct vfe_interrupt_status ret;
- boolean temp;
-
- memset(&hwstat, 0, sizeof(hwstat));
- memset(&ret, 0, sizeof(ret));
-
- hwstat = *((struct vfe_irqenable *)(&irqStatusIn));
-
- ret.camifErrorIrq = hwstat.camifErrorIrq;
- ret.camifSofIrq = hwstat.camifSofIrq;
- ret.camifEolIrq = hwstat.camifEolIrq;
- ret.camifEofIrq = hwstat.camifEofIrq;
- ret.camifEpoch1Irq = hwstat.camifEpoch1Irq;
- ret.camifEpoch2Irq = hwstat.camifEpoch2Irq;
- ret.camifOverflowIrq = hwstat.camifOverflowIrq;
- ret.ceIrq = hwstat.ceIrq;
- ret.regUpdateIrq = hwstat.regUpdateIrq;
- ret.resetAckIrq = hwstat.resetAckIrq;
- ret.encYPingpongIrq = hwstat.encYPingpongIrq;
- ret.encCbcrPingpongIrq = hwstat.encCbcrPingpongIrq;
- ret.viewYPingpongIrq = hwstat.viewYPingpongIrq;
- ret.viewCbcrPingpongIrq = hwstat.viewCbcrPingpongIrq;
- ret.rdPingpongIrq = hwstat.rdPingpongIrq;
- ret.afPingpongIrq = hwstat.afPingpongIrq;
- ret.awbPingpongIrq = hwstat.awbPingpongIrq;
- ret.histPingpongIrq = hwstat.histPingpongIrq;
- ret.encIrq = hwstat.encIrq;
- ret.viewIrq = hwstat.viewIrq;
- ret.busOverflowIrq = hwstat.busOverflowIrq;
- ret.afOverflowIrq = hwstat.afOverflowIrq;
- ret.awbOverflowIrq = hwstat.awbOverflowIrq;
- ret.syncTimer0Irq = hwstat.syncTimer0Irq;
- ret.syncTimer1Irq = hwstat.syncTimer1Irq;
- ret.syncTimer2Irq = hwstat.syncTimer2Irq;
- ret.asyncTimer0Irq = hwstat.asyncTimer0Irq;
- ret.asyncTimer1Irq = hwstat.asyncTimer1Irq;
- ret.asyncTimer2Irq = hwstat.asyncTimer2Irq;
- ret.asyncTimer3Irq = hwstat.asyncTimer3Irq;
- ret.axiErrorIrq = hwstat.axiErrorIrq;
- ret.violationIrq = hwstat.violationIrq;
-
- /* logic OR of any error bits
- * although each irq corresponds to a bit, the data type here is a
- * boolean already. hence use logic operation.
- */
- temp =
- ret.camifErrorIrq ||
- ret.camifOverflowIrq ||
- ret.afOverflowIrq ||
- ret.awbPingpongIrq ||
- ret.busOverflowIrq ||
- ret.axiErrorIrq ||
- ret.violationIrq;
-
- ret.anyErrorIrqs = temp;
-
- /* logic OR of any output path bits*/
- temp =
- ret.encYPingpongIrq ||
- ret.encCbcrPingpongIrq ||
- ret.encIrq;
-
- ret.anyOutput2PathIrqs = temp;
-
- temp =
- ret.viewYPingpongIrq ||
- ret.viewCbcrPingpongIrq ||
- ret.viewIrq;
-
- ret.anyOutput1PathIrqs = temp;
-
- ret.anyOutputPathIrqs =
- ret.anyOutput1PathIrqs ||
- ret.anyOutput2PathIrqs;
-
- /* logic OR of any sync timer bits*/
- temp =
- ret.syncTimer0Irq ||
- ret.syncTimer1Irq ||
- ret.syncTimer2Irq;
-
- ret.anySyncTimerIrqs = temp;
-
- /* logic OR of any async timer bits*/
- temp =
- ret.asyncTimer0Irq ||
- ret.asyncTimer1Irq ||
- ret.asyncTimer2Irq ||
- ret.asyncTimer3Irq;
-
- ret.anyAsyncTimerIrqs = temp;
-
- /* bool for all interrupts that are not allowed in idle state */
- temp =
- ret.anyErrorIrqs ||
- ret.anyOutputPathIrqs ||
- ret.anySyncTimerIrqs ||
- ret.regUpdateIrq ||
- ret.awbPingpongIrq ||
- ret.afPingpongIrq ||
- ret.camifSofIrq ||
- ret.camifEpoch2Irq ||
- ret.camifEpoch1Irq;
-
- ret.anyIrqForActiveStatesOnly =
- temp;
-
- return ret;
-}
-
-static struct vfe_frame_asf_info
-vfe_get_asf_frame_info(struct vfe_irq_thread_msg *in)
-{
- struct vfe_asf_info asfInfoTemp;
- struct vfe_frame_asf_info rc;
-
- memset(&rc, 0, sizeof(rc));
- memset(&asfInfoTemp, 0, sizeof(asfInfoTemp));
-
- asfInfoTemp =
- *((struct vfe_asf_info *)(&(in->asfMaxEdge)));
-
- rc.asfHbiCount = asfInfoTemp.HBICount;
- rc.asfMaxEdge = asfInfoTemp.maxEdge;
-
- return rc;
-}
-
-static struct vfe_frame_bpc_info
-vfe_get_demosaic_frame_info(struct vfe_irq_thread_msg *in)
-{
- struct vfe_bps_info bpcInfoTemp;
- struct vfe_frame_bpc_info rc;
-
- memset(&rc, 0, sizeof(rc));
- memset(&bpcInfoTemp, 0, sizeof(bpcInfoTemp));
-
- bpcInfoTemp =
- *((struct vfe_bps_info *)(&(in->demosaicStatus)));
-
- rc.greenDefectPixelCount =
- bpcInfoTemp.greenBadPixelCount;
-
- rc.redBlueDefectPixelCount =
- bpcInfoTemp.RedBlueBadPixelCount;
-
- return rc;
-}
-
-static struct vfe_msg_camif_status
-vfe_get_camif_status(struct vfe_irq_thread_msg *in)
-{
- struct vfe_camif_stats camifStatusTemp;
- struct vfe_msg_camif_status rc;
-
- memset(&rc, 0, sizeof(rc));
- memset(&camifStatusTemp, 0, sizeof(camifStatusTemp));
-
- camifStatusTemp =
- *((struct vfe_camif_stats *)(&(in->camifStatus)));
-
- rc.camifState = (boolean)camifStatusTemp.camifHalt;
- rc.lineCount = camifStatusTemp.lineCount;
- rc.pixelCount = camifStatusTemp.pixelCount;
-
- return rc;
-}
-
-static struct vfe_bus_performance_monitor
-vfe_get_performance_monitor_data(struct vfe_irq_thread_msg *in)
-{
- struct vfe_bus_performance_monitor rc;
- memset(&rc, 0, sizeof(rc));
-
- rc.encPathPmInfo.yWrPmStats0 =
- in->pmInfo.encPathPmInfo.yWrPmStats0;
- rc.encPathPmInfo.yWrPmStats1 =
- in->pmInfo.encPathPmInfo.yWrPmStats1;
- rc.encPathPmInfo.cbcrWrPmStats0 =
- in->pmInfo.encPathPmInfo.cbcrWrPmStats0;
- rc.encPathPmInfo.cbcrWrPmStats1 =
- in->pmInfo.encPathPmInfo.cbcrWrPmStats1;
- rc.viewPathPmInfo.yWrPmStats0 =
- in->pmInfo.viewPathPmInfo.yWrPmStats0;
- rc.viewPathPmInfo.yWrPmStats1 =
- in->pmInfo.viewPathPmInfo.yWrPmStats1;
- rc.viewPathPmInfo.cbcrWrPmStats0 =
- in->pmInfo.viewPathPmInfo.cbcrWrPmStats0;
- rc.viewPathPmInfo.cbcrWrPmStats1 =
- in->pmInfo.viewPathPmInfo.cbcrWrPmStats1;
-
- return rc;
-}
-
-static void vfe_process_reg_update_irq(void)
-{
- CDBG("vfe_process_reg_update_irq: ackPendingFlag is %d\n",
- ctrl->vfeStartAckPendingFlag);
- if (ctrl->vfeStartAckPendingFlag == TRUE) {
- vfe_send_msg_no_payload(VFE_MSG_ID_START_ACK);
- ctrl->vfeStartAckPendingFlag = FALSE;
- } else
- vfe_send_msg_no_payload(VFE_MSG_ID_UPDATE_ACK);
-}
-
-static void vfe_process_reset_irq(void)
-{
- /* unsigned long flags; */
-
- /* @todo This is causing issues, need further investigate */
- /* spin_lock_irqsave(&ctrl->state_lock, flags); */
- ctrl->vstate = VFE_STATE_IDLE;
- /* spin_unlock_irqrestore(&ctrl->state_lock, flags); */
-
- if (ctrl->vfeStopAckPending == TRUE) {
- ctrl->vfeStopAckPending = FALSE;
- vfe_send_msg_no_payload(VFE_MSG_ID_STOP_ACK);
- } else {
- vfe_set_default_reg_values();
- vfe_send_msg_no_payload(VFE_MSG_ID_RESET_ACK);
- }
-}
-
-static void vfe_process_pingpong_irq(struct vfe_output_path *in,
- uint8_t fragmentCount)
-{
- uint16_t circularIndex;
- uint32_t nextFragmentAddr;
-
- /* get next fragment address from circular buffer */
- circularIndex = (in->fragIndex) % (2 * fragmentCount);
- nextFragmentAddr = in->addressBuffer[circularIndex];
-
- in->fragIndex = circularIndex + 1;
-
- /* use next fragment to program hardware ping/pong address. */
- if (in->hwCurrentFlag == ping) {
- writel(nextFragmentAddr, in->hwRegPingAddress);
- in->hwCurrentFlag = pong;
-
- } else {
- writel(nextFragmentAddr, in->hwRegPongAddress);
- in->hwCurrentFlag = ping;
- }
-}
-
-static void vfe_send_output2_msg(
- struct vfe_msg_output *pPayload)
-{
- /* unsigned long flags; */
- struct vfe_message *msg;
-
- msg = kzalloc(sizeof(struct vfe_message), GFP_ATOMIC);
- if (!msg)
- return;
-
- /* fill message with right content. */
- /* @todo This is causing issues, need further investigate */
- /* spin_lock_irqsave(&ctrl->state_lock, flags); */
- if (ctrl->vstate != VFE_STATE_ACTIVE) {
- kfree(msg);
- goto output2_msg_done;
- }
-
- msg->_d = VFE_MSG_ID_OUTPUT2;
-
- memcpy(&(msg->_u.msgOutput2),
- (void *)pPayload, sizeof(struct vfe_msg_output));
-
- vfe_proc_ops(VFE_MSG_ID_OUTPUT2,
- msg, sizeof(struct vfe_message));
-
- ctrl->encPath.ackPending = TRUE;
-
- if (!(ctrl->vfeRequestedSnapShotCount <= 3) &&
- (ctrl->vfeOperationMode ==
- VFE_START_OPERATION_MODE_SNAPSHOT))
- ctrl->encPath.ackPending = TRUE;
-
-output2_msg_done:
- /* spin_unlock_irqrestore(&ctrl->state_lock, flags); */
- return;
-}
-
-static void vfe_send_output1_msg(
- struct vfe_msg_output *pPayload)
-{
- /* unsigned long flags; */
- struct vfe_message *msg;
-
- msg = kzalloc(sizeof(struct vfe_message), GFP_ATOMIC);
- if (!msg)
- return;
-
- /* @todo This is causing issues, need further investigate */
- /* spin_lock_irqsave(&ctrl->state_lock, flags); */
- if (ctrl->vstate != VFE_STATE_ACTIVE) {
- kfree(msg);
- goto output1_msg_done;
- }
-
- msg->_d = VFE_MSG_ID_OUTPUT1;
- memmove(&(msg->_u),
- (void *)pPayload, sizeof(struct vfe_msg_output));
-
- vfe_proc_ops(VFE_MSG_ID_OUTPUT1,
- msg, sizeof(struct vfe_message));
-
- ctrl->viewPath.ackPending = TRUE;
-
- if (!(ctrl->vfeRequestedSnapShotCount <= 3) &&
- (ctrl->vfeOperationMode ==
- VFE_START_OPERATION_MODE_SNAPSHOT))
- ctrl->viewPath.ackPending = TRUE;
-
-output1_msg_done:
- /* spin_unlock_irqrestore(&ctrl->state_lock, flags); */
- return;
-}
-
-static void vfe_send_output_msg(boolean whichOutputPath,
- uint32_t yPathAddr, uint32_t cbcrPathAddr)
-{
- struct vfe_msg_output msgPayload;
-
- msgPayload.yBuffer = yPathAddr;
- msgPayload.cbcrBuffer = cbcrPathAddr;
-
- /* asf info is common for both output1 and output2 */
-#if 0
- msgPayload.asfInfo.asfHbiCount = ctrl->vfeAsfFrameInfo.asfHbiCount;
- msgPayload.asfInfo.asfMaxEdge = ctrl->vfeAsfFrameInfo.asfMaxEdge;
-
- /* demosaic info is common for both output1 and output2 */
- msgPayload.bpcInfo.greenDefectPixelCount =
- ctrl->vfeBpcFrameInfo.greenDefectPixelCount;
- msgPayload.bpcInfo.redBlueDefectPixelCount =
- ctrl->vfeBpcFrameInfo.redBlueDefectPixelCount;
-#endif /* if 0 */
-
- /* frame ID is common for both paths. */
- msgPayload.frameCounter = ctrl->vfeFrameId;
-
- if (whichOutputPath) {
- /* msgPayload.pmData = ctrl->vfePmData.encPathPmInfo; */
- vfe_send_output2_msg(&msgPayload);
- } else {
- /* msgPayload.pmData = ctrl->vfePmData.viewPathPmInfo; */
- vfe_send_output1_msg(&msgPayload);
- }
-}
-
-static void vfe_process_frame_done_irq_multi_frag(
- struct vfe_output_path_combo *in)
-{
- uint32_t yAddress, cbcrAddress;
- uint16_t idx;
- uint32_t *ptrY;
- uint32_t *ptrCbcr;
- const uint32_t *ptrSrc;
- uint8_t i;
-
- if (!in->ackPending) {
-
- idx = (in->currentFrame) * (in->fragCount);
-
- /* Send output message. */
- yAddress = in->yPath.addressBuffer[idx];
- cbcrAddress = in->cbcrPath.addressBuffer[idx];
-
- /* copy next frame to current frame. */
- ptrSrc = in->nextFrameAddrBuf;
- ptrY = (uint32_t *)&(in->yPath.addressBuffer[idx]);
- ptrCbcr = (uint32_t *)&(in->cbcrPath.addressBuffer[idx]);
-
- /* Copy Y address */
- for (i = 0; i < in->fragCount; i++)
- *ptrY++ = *ptrSrc++;
-
- /* Copy Cbcr address */
- for (i = 0; i < in->fragCount; i++)
- *ptrCbcr++ = *ptrSrc++;
-
- vfe_send_output_msg(in->whichOutputPath, yAddress, cbcrAddress);
-
- } else {
- if (in->whichOutputPath == 0)
- ctrl->vfeDroppedFrameCounts.output1Count++;
-
- if (in->whichOutputPath == 1)
- ctrl->vfeDroppedFrameCounts.output2Count++;
- }
-
- /* toggle current frame. */
- in->currentFrame = in->currentFrame^1;
-
- if (ctrl->vfeOperationMode)
- in->snapshotPendingCount--;
-}
-
-static void vfe_process_frame_done_irq_no_frag_io(
- struct vfe_output_path_combo *in, uint32_t *pNextAddr,
- uint32_t *pdestRenderAddr)
-{
- uint32_t busPingPongStatus;
- uint32_t tempAddress;
-
- /* 1. read hw status register. */
- busPingPongStatus =
- readl(ctrl->vfebase + VFE_BUS_PINGPONG_STATUS);
-
- CDBG("hardware status is 0x%x\n", busPingPongStatus);
-
- /* 2. determine ping or pong */
- /* use cbcr status */
- busPingPongStatus = busPingPongStatus & (1<<(in->cbcrStatusBit));
-
- /* 3. read out address and update address */
- if (busPingPongStatus == 0) {
- /* hw is working on ping, render pong buffer */
- /* a. read out pong address */
- /* read out y address. */
- tempAddress = readl(in->yPath.hwRegPongAddress);
-
- CDBG("pong 1 addr = 0x%x\n", tempAddress);
- *pdestRenderAddr++ = tempAddress;
- /* read out cbcr address. */
- tempAddress = readl(in->cbcrPath.hwRegPongAddress);
-
- CDBG("pong 2 addr = 0x%x\n", tempAddress);
- *pdestRenderAddr = tempAddress;
-
- /* b. update pong address */
- writel(*pNextAddr++, in->yPath.hwRegPongAddress);
- writel(*pNextAddr, in->cbcrPath.hwRegPongAddress);
- } else {
- /* hw is working on pong, render ping buffer */
-
- /* a. read out ping address */
- tempAddress = readl(in->yPath.hwRegPingAddress);
- CDBG("ping 1 addr = 0x%x\n", tempAddress);
- *pdestRenderAddr++ = tempAddress;
- tempAddress = readl(in->cbcrPath.hwRegPingAddress);
-
- CDBG("ping 2 addr = 0x%x\n", tempAddress);
- *pdestRenderAddr = tempAddress;
-
- /* b. update ping address */
- writel(*pNextAddr++, in->yPath.hwRegPingAddress);
- CDBG("NextAddress = 0x%x\n", *pNextAddr);
- writel(*pNextAddr, in->cbcrPath.hwRegPingAddress);
- }
-}
-
-static void vfe_process_frame_done_irq_no_frag(
- struct vfe_output_path_combo *in)
-{
- uint32_t addressToRender[2];
- static uint32_t fcnt;
-
- if (fcnt++ < 3)
- return;
-
- if (!in->ackPending) {
- vfe_process_frame_done_irq_no_frag_io(in,
- in->nextFrameAddrBuf, addressToRender);
-
- /* use addressToRender to send out message. */
- vfe_send_output_msg(in->whichOutputPath,
- addressToRender[0], addressToRender[1]);
-
- } else {
- /* ackPending is still there, accumulate dropped frame count.
- * These count can be read through ioctrl command. */
- CDBG("waiting frame ACK\n");
-
- if (in->whichOutputPath == 0)
- ctrl->vfeDroppedFrameCounts.output1Count++;
-
- if (in->whichOutputPath == 1)
- ctrl->vfeDroppedFrameCounts.output2Count++;
- }
-
- /* in case of multishot when upper layer did not ack, there will still
- * be a snapshot done msg sent out, even though the number of frames
- * sent out may be less than the desired number of frames. snapshot
- * done msg would be helpful to indicate that vfe pipeline has stop,
- * and in good known state.
- */
- if (ctrl->vfeOperationMode)
- in->snapshotPendingCount--;
-}
-
-static void vfe_process_output_path_irq(
- struct vfe_interrupt_status *irqstatus)
-{
- /* unsigned long flags; */
-
- /* process the view path interrupts */
- if (irqstatus->anyOutput1PathIrqs) {
- if (ctrl->viewPath.multiFrag) {
-
- if (irqstatus->viewCbcrPingpongIrq)
- vfe_process_pingpong_irq(
- &(ctrl->viewPath.cbcrPath),
- ctrl->viewPath.fragCount);
-
- if (irqstatus->viewYPingpongIrq)
- vfe_process_pingpong_irq(
- &(ctrl->viewPath.yPath),
- ctrl->viewPath.fragCount);
-
- if (irqstatus->viewIrq)
- vfe_process_frame_done_irq_multi_frag(
- &ctrl->viewPath);
-
- } else {
- /* typical case for no fragment,
- only frame done irq is enabled. */
- if (irqstatus->viewIrq)
- vfe_process_frame_done_irq_no_frag(
- &ctrl->viewPath);
- }
- }
-
- /* process the encoder path interrupts */
- if (irqstatus->anyOutput2PathIrqs) {
- if (ctrl->encPath.multiFrag) {
- if (irqstatus->encCbcrPingpongIrq)
- vfe_process_pingpong_irq(
- &(ctrl->encPath.cbcrPath),
- ctrl->encPath.fragCount);
-
- if (irqstatus->encYPingpongIrq)
- vfe_process_pingpong_irq(&(ctrl->encPath.yPath),
- ctrl->encPath.fragCount);
-
- if (irqstatus->encIrq)
- vfe_process_frame_done_irq_multi_frag(
- &ctrl->encPath);
-
- } else {
- if (irqstatus->encIrq)
- vfe_process_frame_done_irq_no_frag(
- &ctrl->encPath);
- }
- }
-
- if (ctrl->vfeOperationMode) {
- if ((ctrl->encPath.snapshotPendingCount == 0) &&
- (ctrl->viewPath.snapshotPendingCount == 0)) {
-
- /* @todo This is causing issues, further investigate */
- /* spin_lock_irqsave(&ctrl->state_lock, flags); */
- ctrl->vstate = VFE_STATE_IDLE;
- /* spin_unlock_irqrestore(&ctrl->state_lock, flags); */
-
- vfe_send_msg_no_payload(VFE_MSG_ID_SNAPSHOT_DONE);
- vfe_prog_hw_testgen_cmd(VFE_TEST_GEN_STOP);
- vfe_pm_stop();
- }
- }
-}
-
-static void vfe_do_tasklet(unsigned long data)
-{
- unsigned long flags;
-
- struct isr_queue_cmd *qcmd = NULL;
-
- CDBG("=== vfe_do_tasklet start === \n");
-
- spin_lock_irqsave(&ctrl->tasklet_lock, flags);
- qcmd = list_first_entry(&ctrl->tasklet_q,
- struct isr_queue_cmd, list);
-
- if (!qcmd) {
- spin_unlock_irqrestore(&ctrl->tasklet_lock, flags);
- return;
- }
-
- list_del(&qcmd->list);
- spin_unlock_irqrestore(&ctrl->tasklet_lock, flags);
-
- if (qcmd->vfeInterruptStatus.regUpdateIrq) {
- CDBG("irq regUpdateIrq\n");
- vfe_process_reg_update_irq();
- }
-
- if (qcmd->vfeInterruptStatus.resetAckIrq) {
- CDBG("irq resetAckIrq\n");
- vfe_process_reset_irq();
- }
-
- spin_lock_irqsave(&ctrl->state_lock, flags);
- if (ctrl->vstate != VFE_STATE_ACTIVE) {
- spin_unlock_irqrestore(&ctrl->state_lock, flags);
- return;
- }
- spin_unlock_irqrestore(&ctrl->state_lock, flags);
-
-#if 0
- if (qcmd->vfeInterruptStatus.camifEpoch1Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_EPOCH1);
-
- if (qcmd->vfeInterruptStatus.camifEpoch2Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_EPOCH2);
-#endif /* Jeff */
-
- /* next, check output path related interrupts. */
- if (qcmd->vfeInterruptStatus.anyOutputPathIrqs) {
- CDBG("irq anyOutputPathIrqs\n");
- vfe_process_output_path_irq(&qcmd->vfeInterruptStatus);
- }
-
- if (qcmd->vfeInterruptStatus.afPingpongIrq)
- vfe_process_stats_af_irq();
-
- if (qcmd->vfeInterruptStatus.awbPingpongIrq)
- vfe_process_stats_awb_irq();
-
- /* any error irqs*/
- if (qcmd->vfeInterruptStatus.anyErrorIrqs)
- vfe_process_error_irq(&qcmd->vfeInterruptStatus);
-
-#if 0
- if (qcmd->vfeInterruptStatus.anySyncTimerIrqs)
- vfe_process_sync_timer_irq();
-
- if (qcmd->vfeInterruptStatus.anyAsyncTimerIrqs)
- vfe_process_async_timer_irq();
-#endif /* Jeff */
-
- if (qcmd->vfeInterruptStatus.camifSofIrq) {
- CDBG("irq camifSofIrq\n");
- vfe_process_camif_sof_irq();
- }
-
- kfree(qcmd);
- CDBG("=== vfe_do_tasklet end === \n");
-}
-
-DECLARE_TASKLET(vfe_tasklet, vfe_do_tasklet, 0);
-
-static irqreturn_t vfe_parse_irq(int irq_num, void *data)
-{
- unsigned long flags;
- uint32_t irqStatusLocal;
- struct vfe_irq_thread_msg irq;
- struct isr_queue_cmd *qcmd;
-
- CDBG("vfe_parse_irq\n");
-
- vfe_read_irq_status(&irq);
-
- if (irq.vfeIrqStatus == 0) {
- CDBG("vfe_parse_irq: irq.vfeIrqStatus is 0\n");
- return IRQ_HANDLED;
- }
-
- qcmd = kzalloc(sizeof(struct isr_queue_cmd),
- GFP_ATOMIC);
- if (!qcmd) {
- CDBG("vfe_parse_irq: qcmd malloc failed!\n");
- return IRQ_HANDLED;
- }
-
- spin_lock_irqsave(&ctrl->ack_lock, flags);
-
- if (ctrl->vfeStopAckPending)
- irqStatusLocal =
- (VFE_IMASK_WHILE_STOPPING & irq.vfeIrqStatus);
- else
- irqStatusLocal =
- ((ctrl->vfeImaskPacked | VFE_IMASK_ERROR_ONLY) &
- irq.vfeIrqStatus);
-
- spin_unlock_irqrestore(&ctrl->ack_lock, flags);
-
- /* first parse the interrupt status to local data structures. */
- qcmd->vfeInterruptStatus = vfe_parse_interrupt_status(irqStatusLocal);
- qcmd->vfeAsfFrameInfo = vfe_get_asf_frame_info(&irq);
- qcmd->vfeBpcFrameInfo = vfe_get_demosaic_frame_info(&irq);
- qcmd->vfeCamifStatusLocal = vfe_get_camif_status(&irq);
- qcmd->vfePmData = vfe_get_performance_monitor_data(&irq);
-
- spin_lock_irqsave(&ctrl->tasklet_lock, flags);
- list_add_tail(&qcmd->list, &ctrl->tasklet_q);
- spin_unlock_irqrestore(&ctrl->tasklet_lock, flags);
- tasklet_schedule(&vfe_tasklet);
-
- /* clear the pending interrupt of the same kind.*/
- writel(irq.vfeIrqStatus, ctrl->vfebase + VFE_IRQ_CLEAR);
-
- return IRQ_HANDLED;
-}
-
-int vfe_cmd_init(struct msm_vfe_callback *presp,
- struct platform_device *pdev, void *sdata)
-{
- struct resource *vfemem, *vfeirq, *vfeio;
- int rc;
-
- vfemem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!vfemem) {
- CDBG("no mem resource?\n");
- return -ENODEV;
- }
-
- vfeirq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (!vfeirq) {
- CDBG("no irq resource?\n");
- return -ENODEV;
- }
-
- vfeio = request_mem_region(vfemem->start,
- resource_size(vfemem), pdev->name);
- if (!vfeio) {
- CDBG("VFE region already claimed\n");
- return -EBUSY;
- }
-
- ctrl =
- kzalloc(sizeof(struct msm_vfe8x_ctrl), GFP_KERNEL);
- if (!ctrl) {
- rc = -ENOMEM;
- goto cmd_init_failed1;
- }
-
- ctrl->vfeirq = vfeirq->start;
-
- ctrl->vfebase =
- ioremap(vfemem->start, (vfemem->end - vfemem->start) + 1);
- if (!ctrl->vfebase) {
- rc = -ENOMEM;
- goto cmd_init_failed2;
- }
-
- rc = request_irq(ctrl->vfeirq, vfe_parse_irq,
- IRQF_TRIGGER_RISING, "vfe", 0);
- if (rc < 0)
- goto cmd_init_failed2;
-
- if (presp && presp->vfe_resp)
- ctrl->resp = presp;
- else {
- rc = -EINVAL;
- goto cmd_init_failed3;
- }
-
- ctrl->extdata =
- kmalloc(sizeof(struct vfe_frame_extra), GFP_KERNEL);
- if (!ctrl->extdata) {
- rc = -ENOMEM;
- goto cmd_init_failed3;
- }
-
- spin_lock_init(&ctrl->ack_lock);
- spin_lock_init(&ctrl->state_lock);
- spin_lock_init(&ctrl->io_lock);
-
- ctrl->extlen = sizeof(struct vfe_frame_extra);
-
- spin_lock_init(&ctrl->tasklet_lock);
- INIT_LIST_HEAD(&ctrl->tasklet_q);
-
- ctrl->syncdata = sdata;
- return 0;
-
-cmd_init_failed3:
- disable_irq(ctrl->vfeirq);
- free_irq(ctrl->vfeirq, 0);
- iounmap(ctrl->vfebase);
-cmd_init_failed2:
- kfree(ctrl);
-cmd_init_failed1:
- release_mem_region(vfemem->start, (vfemem->end - vfemem->start) + 1);
- return rc;
-}
-
-void vfe_cmd_release(struct platform_device *dev)
-{
- struct resource *mem;
-
- disable_irq(ctrl->vfeirq);
- free_irq(ctrl->vfeirq, 0);
-
- iounmap(ctrl->vfebase);
- mem = platform_get_resource(dev, IORESOURCE_MEM, 0);
- release_mem_region(mem->start, (mem->end - mem->start) + 1);
-
- ctrl->extlen = 0;
-
- kfree(ctrl->extdata);
- kfree(ctrl);
-}
-
-void vfe_stats_af_stop(void)
-{
- ctrl->vfeStatsCmdLocal.autoFocusEnable = FALSE;
- ctrl->vfeImaskLocal.afPingpongIrq = FALSE;
-}
-
-void vfe_stop(void)
-{
- boolean vfeAxiBusy;
- uint32_t vfeAxiStauts;
-
- /* for reset hw modules, and send msg when reset_irq comes.*/
- ctrl->vfeStopAckPending = TRUE;
-
- ctrl->vfeStatsPingPongReloadFlag = FALSE;
- vfe_pm_stop();
-
- /* disable all interrupts. */
- vfe_program_irq_mask(VFE_DISABLE_ALL_IRQS);
-
- /* in either continuous or snapshot mode, stop command can be issued
- * at any time.
- */
- vfe_camif_stop_immediately();
- vfe_program_axi_cmd(AXI_HALT);
- vfe_prog_hw_testgen_cmd(VFE_TEST_GEN_STOP);
-
- vfeAxiBusy = TRUE;
-
- while (vfeAxiBusy) {
- vfeAxiStauts = vfe_read_axi_status();
- if ((vfeAxiStauts & AXI_STATUS_BUSY_MASK) != 0)
- vfeAxiBusy = FALSE;
- }
-
- vfe_program_axi_cmd(AXI_HALT_CLEAR);
-
- /* clear all pending interrupts */
- writel(VFE_CLEAR_ALL_IRQS, ctrl->vfebase + VFE_IRQ_CLEAR);
-
- /* enable reset_ack and async timer interrupt only while stopping
- * the pipeline.
- */
- vfe_program_irq_mask(VFE_IMASK_WHILE_STOPPING);
-
- vfe_program_global_reset_cmd(VFE_RESET_UPON_STOP_CMD);
-}
-
-void vfe_update(void)
-{
- ctrl->vfeModuleEnableLocal.statsEnable =
- ctrl->vfeStatsCmdLocal.autoFocusEnable |
- ctrl->vfeStatsCmdLocal.axwEnable;
-
- vfe_reg_module_cfg(&ctrl->vfeModuleEnableLocal);
-
- vfe_program_stats_cmd(&ctrl->vfeStatsCmdLocal);
-
- ctrl->vfeImaskPacked = vfe_irq_pack(ctrl->vfeImaskLocal);
- vfe_program_irq_mask(ctrl->vfeImaskPacked);
-
- if ((ctrl->vfeModuleEnableLocal.statsEnable == TRUE) &&
- (ctrl->vfeStatsPingPongReloadFlag == FALSE)) {
- ctrl->vfeStatsPingPongReloadFlag = TRUE;
-
- ctrl->vfeBusCmdLocal.statsPingpongReload = TRUE;
- vfe_reg_bus_cmd(&ctrl->vfeBusCmdLocal);
- }
-
- vfe_program_reg_update_cmd(VFE_REG_UPDATE_TRIGGER);
-}
-
-int vfe_rgb_gamma_update(struct vfe_cmd_rgb_gamma_config *in)
-{
- int rc = 0;
-
- ctrl->vfeModuleEnableLocal.rgbLUTEnable = in->enable;
-
- switch (in->channelSelect) {
- case RGB_GAMMA_CH0_SELECTED:
- ctrl->vfeGammaLutSel.ch0BankSelect ^= 1;
- vfe_write_gamma_table(0,
- ctrl->vfeGammaLutSel.ch0BankSelect, in->table);
- break;
-
- case RGB_GAMMA_CH1_SELECTED:
- ctrl->vfeGammaLutSel.ch1BankSelect ^= 1;
- vfe_write_gamma_table(1,
- ctrl->vfeGammaLutSel.ch1BankSelect, in->table);
- break;
-
- case RGB_GAMMA_CH2_SELECTED:
- ctrl->vfeGammaLutSel.ch2BankSelect ^= 1;
- vfe_write_gamma_table(2,
- ctrl->vfeGammaLutSel.ch2BankSelect, in->table);
- break;
-
- case RGB_GAMMA_CH0_CH1_SELECTED:
- ctrl->vfeGammaLutSel.ch0BankSelect ^= 1;
- ctrl->vfeGammaLutSel.ch1BankSelect ^= 1;
- vfe_write_gamma_table(0, ctrl->vfeGammaLutSel.ch0BankSelect,
- in->table);
- vfe_write_gamma_table(1, ctrl->vfeGammaLutSel.ch1BankSelect,
- in->table);
- break;
-
- case RGB_GAMMA_CH0_CH2_SELECTED:
- ctrl->vfeGammaLutSel.ch0BankSelect ^= 1;
- ctrl->vfeGammaLutSel.ch2BankSelect ^= 1;
- vfe_write_gamma_table(0, ctrl->vfeGammaLutSel.ch0BankSelect,
- in->table);
- vfe_write_gamma_table(2, ctrl->vfeGammaLutSel.ch2BankSelect,
- in->table);
- break;
-
- case RGB_GAMMA_CH1_CH2_SELECTED:
- ctrl->vfeGammaLutSel.ch1BankSelect ^= 1;
- ctrl->vfeGammaLutSel.ch2BankSelect ^= 1;
- vfe_write_gamma_table(1, ctrl->vfeGammaLutSel.ch1BankSelect,
- in->table);
- vfe_write_gamma_table(2, ctrl->vfeGammaLutSel.ch2BankSelect,
- in->table);
- break;
-
- case RGB_GAMMA_CH0_CH1_CH2_SELECTED:
- ctrl->vfeGammaLutSel.ch0BankSelect ^= 1;
- ctrl->vfeGammaLutSel.ch1BankSelect ^= 1;
- ctrl->vfeGammaLutSel.ch2BankSelect ^= 1;
- vfe_write_gamma_table(0, ctrl->vfeGammaLutSel.ch0BankSelect,
- in->table);
- vfe_write_gamma_table(1, ctrl->vfeGammaLutSel.ch1BankSelect,
- in->table);
- vfe_write_gamma_table(2, ctrl->vfeGammaLutSel.ch2BankSelect,
- in->table);
- break;
-
- default:
- return -EINVAL;
- } /* switch */
-
- /* update the gammaLutSel register. */
- vfe_program_lut_bank_sel(&ctrl->vfeGammaLutSel);
-
- return rc;
-}
-
-int vfe_rgb_gamma_config(struct vfe_cmd_rgb_gamma_config *in)
-{
- int rc = 0;
-
- ctrl->vfeModuleEnableLocal.rgbLUTEnable = in->enable;
-
- switch (in->channelSelect) {
- case RGB_GAMMA_CH0_SELECTED:
-vfe_write_gamma_table(0, 0, in->table);
-break;
-
- case RGB_GAMMA_CH1_SELECTED:
- vfe_write_gamma_table(1, 0, in->table);
- break;
-
- case RGB_GAMMA_CH2_SELECTED:
- vfe_write_gamma_table(2, 0, in->table);
- break;
-
- case RGB_GAMMA_CH0_CH1_SELECTED:
- vfe_write_gamma_table(0, 0, in->table);
- vfe_write_gamma_table(1, 0, in->table);
- break;
-
- case RGB_GAMMA_CH0_CH2_SELECTED:
- vfe_write_gamma_table(0, 0, in->table);
- vfe_write_gamma_table(2, 0, in->table);
- break;
-
- case RGB_GAMMA_CH1_CH2_SELECTED:
- vfe_write_gamma_table(1, 0, in->table);
- vfe_write_gamma_table(2, 0, in->table);
- break;
-
- case RGB_GAMMA_CH0_CH1_CH2_SELECTED:
- vfe_write_gamma_table(0, 0, in->table);
- vfe_write_gamma_table(1, 0, in->table);
- vfe_write_gamma_table(2, 0, in->table);
- break;
-
- default:
- rc = -EINVAL;
- break;
- } /* switch */
-
- return rc;
-}
-
-void vfe_stats_af_ack(struct vfe_cmd_stats_af_ack *in)
-{
- ctrl->afStatsControl.nextFrameAddrBuf = in->nextAFOutputBufferAddr;
- ctrl->afStatsControl.ackPending = FALSE;
-}
-
-void vfe_stats_wb_exp_ack(struct vfe_cmd_stats_wb_exp_ack *in)
-{
- ctrl->awbStatsControl.nextFrameAddrBuf = in->nextWbExpOutputBufferAddr;
- ctrl->awbStatsControl.ackPending = FALSE;
-}
-
-void vfe_output2_ack(struct vfe_cmd_output_ack *in)
-{
- const uint32_t *psrc;
- uint32_t *pdest;
- uint8_t i;
-
- pdest = ctrl->encPath.nextFrameAddrBuf;
-
- CDBG("output2_ack: ack addr = 0x%x\n", in->ybufaddr[0]);
-
- psrc = in->ybufaddr;
- for (i = 0; i < ctrl->encPath.fragCount; i++)
- *pdest++ = *psrc++;
-
- psrc = in->chromabufaddr;
- for (i = 0; i < ctrl->encPath.fragCount; i++)
- *pdest++ = *psrc++;
-
- ctrl->encPath.ackPending = FALSE;
-}
-
-void vfe_output1_ack(struct vfe_cmd_output_ack *in)
-{
- const uint32_t *psrc;
- uint32_t *pdest;
- uint8_t i;
-
- pdest = ctrl->viewPath.nextFrameAddrBuf;
-
- psrc = in->ybufaddr;
- for (i = 0; i < ctrl->viewPath.fragCount; i++)
- *pdest++ = *psrc++;
-
- psrc = in->chromabufaddr;
- for (i = 0; i < ctrl->viewPath.fragCount; i++)
- *pdest++ = *psrc++;
-
- ctrl->viewPath.ackPending = FALSE;
-}
-
-void vfe_start(struct vfe_cmd_start *in)
-{
- unsigned long flags;
- uint32_t pmstatus = 0;
- boolean rawmode;
- uint32_t demperiod = 0;
- uint32_t demeven = 0;
- uint32_t demodd = 0;
-
- /* derived from other commands. (camif config, axi output config,
- * etc)
- */
- struct vfe_cfg hwcfg;
- struct vfe_upsample_cfg chromupcfg;
-
- CDBG("vfe_start operationMode = %d\n", in->operationMode);
-
- memset(&hwcfg, 0, sizeof(hwcfg));
- memset(&chromupcfg, 0, sizeof(chromupcfg));
-
- switch (in->pixel) {
- case VFE_BAYER_RGRGRG:
- demperiod = 1;
- demeven = 0xC9;
- demodd = 0xAC;
- break;
-
- case VFE_BAYER_GRGRGR:
- demperiod = 1;
- demeven = 0x9C;
- demodd = 0xCA;
- break;
-
- case VFE_BAYER_BGBGBG:
- demperiod = 1;
- demeven = 0xCA;
- demodd = 0x9C;
- break;
-
- case VFE_BAYER_GBGBGB:
- demperiod = 1;
- demeven = 0xAC;
- demodd = 0xC9;
- break;
-
- case VFE_YUV_YCbYCr:
- demperiod = 3;
- demeven = 0x9CAC;
- demodd = 0x9CAC;
- break;
-
- case VFE_YUV_YCrYCb:
- demperiod = 3;
- demeven = 0xAC9C;
- demodd = 0xAC9C;
- break;
-
- case VFE_YUV_CbYCrY:
- demperiod = 3;
- demeven = 0xC9CA;
- demodd = 0xC9CA;
- break;
-
- case VFE_YUV_CrYCbY:
- demperiod = 3;
- demeven = 0xCAC9;
- demodd = 0xCAC9;
- break;
-
- default:
- return;
- }
-
- vfe_config_demux(demperiod, demeven, demodd);
-
- vfe_program_lut_bank_sel(&ctrl->vfeGammaLutSel);
-
- /* save variables to local. */
- ctrl->vfeOperationMode = in->operationMode;
- if (ctrl->vfeOperationMode ==
- VFE_START_OPERATION_MODE_SNAPSHOT) {
- /* in snapshot mode, initialize snapshot count*/
- ctrl->vfeSnapShotCount = in->snapshotCount;
-
- /* save the requested count, this is temporarily done, to
- help with HJR / multishot. */
- ctrl->vfeRequestedSnapShotCount = ctrl->vfeSnapShotCount;
-
- CDBG("requested snapshot count = %d\n", ctrl->vfeSnapShotCount);
-
- /* Assumption is to have the same pattern and period for both
- paths, if both paths are used. */
- if (ctrl->viewPath.pathEnabled) {
- ctrl->viewPath.snapshotPendingCount =
- in->snapshotCount;
-
- ctrl->vfeFrameSkipPattern =
- ctrl->vfeFrameSkip.output1Pattern;
- ctrl->vfeFrameSkipPeriod =
- ctrl->vfeFrameSkip.output1Period;
- }
-
- if (ctrl->encPath.pathEnabled) {
- ctrl->encPath.snapshotPendingCount =
- in->snapshotCount;
-
- ctrl->vfeFrameSkipPattern =
- ctrl->vfeFrameSkip.output2Pattern;
- ctrl->vfeFrameSkipPeriod =
- ctrl->vfeFrameSkip.output2Period;
- }
- }
-
- /* enable color conversion for bayer sensor
- if stats enabled, need to do color conversion. */
- if (in->pixel <= VFE_BAYER_GBGBGB)
- ctrl->vfeStatsCmdLocal.colorConversionEnable = TRUE;
-
- vfe_program_stats_cmd(&ctrl->vfeStatsCmdLocal);
-
- if (in->pixel >= VFE_YUV_YCbYCr)
- ctrl->vfeModuleEnableLocal.chromaUpsampleEnable = TRUE;
-
- ctrl->vfeModuleEnableLocal.demuxEnable = TRUE;
-
- /* if any stats module is enabled, the main bit is enabled. */
- ctrl->vfeModuleEnableLocal.statsEnable =
- ctrl->vfeStatsCmdLocal.autoFocusEnable |
- ctrl->vfeStatsCmdLocal.axwEnable;
-
- vfe_reg_module_cfg(&ctrl->vfeModuleEnableLocal);
-
- /* in case of offline processing, do not need to config camif. Having
- * bus output enabled in camif_config register might confuse the
- * hardware?
- */
- if (in->inputSource != VFE_START_INPUT_SOURCE_AXI) {
- vfe_reg_camif_config(&ctrl->vfeCamifConfigLocal);
- } else {
- /* offline processing, enable axi read */
- ctrl->vfeBusConfigLocal.stripeRdPathEn = TRUE;
- ctrl->vfeBusCmdLocal.stripeReload = TRUE;
- ctrl->vfeBusConfigLocal.rawPixelDataSize =
- ctrl->axiInputDataSize;
- }
-
- vfe_reg_bus_cfg(&ctrl->vfeBusConfigLocal);
-
- /* directly from start command */
- hwcfg.pixelPattern = in->pixel;
- hwcfg.inputSource = in->inputSource;
- writel(*(uint32_t *)&hwcfg, ctrl->vfebase + VFE_CFG);
-
- /* regardless module enabled or not, it does not hurt
- * to program the cositing mode. */
- chromupcfg.chromaCositingForYCbCrInputs =
- in->yuvInputCositingMode;
-
- writel(*(uint32_t *)&(chromupcfg),
- ctrl->vfebase + VFE_CHROMA_UPSAMPLE_CFG);
-
- /* MISR to monitor the axi read. */
- writel(0xd8, ctrl->vfebase + VFE_BUS_MISR_MAST_CFG_0);
-
- /* clear all pending interrupts. */
- writel(VFE_CLEAR_ALL_IRQS, ctrl->vfebase + VFE_IRQ_CLEAR);
-
- /* define how composite interrupt work. */
- ctrl->vfeImaskCompositePacked =
- vfe_irq_composite_pack(ctrl->vfeIrqCompositeMaskLocal);
-
- vfe_program_irq_composite_mask(ctrl->vfeImaskCompositePacked);
-
- /* enable all necessary interrupts. */
- ctrl->vfeImaskLocal.camifSofIrq = TRUE;
- ctrl->vfeImaskLocal.regUpdateIrq = TRUE;
- ctrl->vfeImaskLocal.resetAckIrq = TRUE;
-
- ctrl->vfeImaskPacked = vfe_irq_pack(ctrl->vfeImaskLocal);
- vfe_program_irq_mask(ctrl->vfeImaskPacked);
-
- /* enable bus performance monitor */
- vfe_8k_pm_start(&ctrl->vfeBusPmConfigLocal);
-
- /* trigger vfe reg update */
- ctrl->vfeStartAckPendingFlag = TRUE;
-
- /* write bus command to trigger reload of ping pong buffer. */
- ctrl->vfeBusCmdLocal.busPingpongReload = TRUE;
-
- if (ctrl->vfeModuleEnableLocal.statsEnable == TRUE) {
- ctrl->vfeBusCmdLocal.statsPingpongReload = TRUE;
- ctrl->vfeStatsPingPongReloadFlag = TRUE;
- }
-
- writel(VFE_REG_UPDATE_TRIGGER,
- ctrl->vfebase + VFE_REG_UPDATE_CMD);
-
- /* program later than the reg update. */
- vfe_reg_bus_cmd(&ctrl->vfeBusCmdLocal);
-
- if ((in->inputSource ==
- VFE_START_INPUT_SOURCE_CAMIF) ||
- (in->inputSource ==
- VFE_START_INPUT_SOURCE_TESTGEN))
- writel(CAMIF_COMMAND_START, ctrl->vfebase + CAMIF_COMMAND);
-
- /* start test gen if it is enabled */
- if (ctrl->vfeTestGenStartFlag == TRUE) {
- ctrl->vfeTestGenStartFlag = FALSE;
- vfe_prog_hw_testgen_cmd(VFE_TEST_GEN_GO);
- }
-
- CDBG("ctrl->axiOutputMode = %d\n", ctrl->axiOutputMode);
- if (ctrl->axiOutputMode == VFE_AXI_OUTPUT_MODE_CAMIFToAXIViaOutput2) {
- /* raw dump mode */
- rawmode = TRUE;
-
- while (rawmode) {
- pmstatus =
- readl(ctrl->vfebase +
- VFE_BUS_ENC_CBCR_WR_PM_STATS_1);
-
- if ((pmstatus & VFE_PM_BUF_MAX_CNT_MASK) != 0)
- rawmode = FALSE;
- }
-
- vfe_send_msg_no_payload(VFE_MSG_ID_START_ACK);
- ctrl->vfeStartAckPendingFlag = FALSE;
- }
-
- spin_lock_irqsave(&ctrl->state_lock, flags);
- ctrl->vstate = VFE_STATE_ACTIVE;
- spin_unlock_irqrestore(&ctrl->state_lock, flags);
-}
-
-void vfe_la_update(struct vfe_cmd_la_config *in)
-{
- int16_t *pTable;
- enum VFE_DMI_RAM_SEL dmiRamSel;
- int i;
-
- pTable = in->table;
- ctrl->vfeModuleEnableLocal.lumaAdaptationEnable = in->enable;
-
- /* toggle the bank to be used. */
- ctrl->vfeLaBankSel ^= 1;
-
- if (ctrl->vfeLaBankSel == 0)
- dmiRamSel = LUMA_ADAPT_LUT_RAM_BANK0;
- else
- dmiRamSel = LUMA_ADAPT_LUT_RAM_BANK1;
-
- /* configure the DMI_CFG to select right sram */
- vfe_program_dmi_cfg(dmiRamSel);
-
- for (i = 0; i < VFE_LA_TABLE_LENGTH; i++) {
- writel((uint32_t)(*pTable), ctrl->vfebase + VFE_DMI_DATA_LO);
- pTable++;
- }
-
- /* After DMI transfer, to make it safe, need to set
- * the DMI_CFG to unselect any SRAM */
- writel(VFE_DMI_CFG_DEFAULT, ctrl->vfebase + VFE_DMI_CFG);
- writel(ctrl->vfeLaBankSel, ctrl->vfebase + VFE_LA_CFG);
-}
-
-void vfe_la_config(struct vfe_cmd_la_config *in)
-{
- uint16_t i;
- int16_t *pTable;
- enum VFE_DMI_RAM_SEL dmiRamSel;
-
- pTable = in->table;
- ctrl->vfeModuleEnableLocal.lumaAdaptationEnable = in->enable;
-
- if (ctrl->vfeLaBankSel == 0)
- dmiRamSel = LUMA_ADAPT_LUT_RAM_BANK0;
- else
- dmiRamSel = LUMA_ADAPT_LUT_RAM_BANK1;
-
- /* configure the DMI_CFG to select right sram */
- vfe_program_dmi_cfg(dmiRamSel);
-
- for (i = 0; i < VFE_LA_TABLE_LENGTH; i++) {
- writel((uint32_t)(*pTable), ctrl->vfebase + VFE_DMI_DATA_LO);
- pTable++;
- }
-
- /* After DMI transfer, to make it safe, need to set the
- * DMI_CFG to unselect any SRAM */
- writel(VFE_DMI_CFG_DEFAULT, ctrl->vfebase + VFE_DMI_CFG);
-
- /* can only be bank 0 or bank 1 for now. */
- writel(ctrl->vfeLaBankSel, ctrl->vfebase + VFE_LA_CFG);
- CDBG("VFE Luma adaptation bank selection is 0x%x\n",
- *(uint32_t *)&ctrl->vfeLaBankSel);
-}
-
-void vfe_test_gen_start(struct vfe_cmd_test_gen_start *in)
-{
- struct VFE_TestGen_ConfigCmdType cmd;
-
- memset(&cmd, 0, sizeof(cmd));
-
- cmd.numFrame = in->numFrame;
- cmd.pixelDataSelect = in->pixelDataSelect;
- cmd.systematicDataSelect = in->systematicDataSelect;
- cmd.pixelDataSize = (uint32_t)in->pixelDataSize;
- cmd.hsyncEdge = (uint32_t)in->hsyncEdge;
- cmd.vsyncEdge = (uint32_t)in->vsyncEdge;
- cmd.imageWidth = in->imageWidth;
- cmd.imageHeight = in->imageHeight;
- cmd.sofOffset = in->startOfFrameOffset;
- cmd.eofNOffset = in->endOfFrameNOffset;
- cmd.solOffset = in->startOfLineOffset;
- cmd.eolNOffset = in->endOfLineNOffset;
- cmd.hBlankInterval = in->hbi;
- cmd.vBlankInterval = in->vbl;
- cmd.vBlankIntervalEnable = in->vblEnable;
- cmd.sofDummy = in->startOfFrameDummyLine;
- cmd.eofDummy = in->endOfFrameDummyLine;
- cmd.unicolorBarSelect = in->unicolorBarSelect;
- cmd.unicolorBarEnable = in->unicolorBarEnable;
- cmd.splitEnable = in->colorBarsSplitEnable;
- cmd.pixelPattern = (uint32_t)in->colorBarsPixelPattern;
- cmd.rotatePeriod = in->colorBarsRotatePeriod;
- cmd.randomSeed = in->testGenRandomSeed;
-
- vfe_prog_hw(ctrl->vfebase + VFE_HW_TESTGEN_CFG,
- (uint32_t *) &cmd, sizeof(cmd));
-}
-
-void vfe_frame_skip_update(struct vfe_cmd_frame_skip_update *in)
-{
- struct VFE_FRAME_SKIP_UpdateCmdType cmd;
-
- cmd.yPattern = in->output1Pattern;
- cmd.cbcrPattern = in->output1Pattern;
- vfe_prog_hw(ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y_PATTERN,
- (uint32_t *)&cmd, sizeof(cmd));
-
- cmd.yPattern = in->output2Pattern;
- cmd.cbcrPattern = in->output2Pattern;
- vfe_prog_hw(ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_frame_skip_config(struct vfe_cmd_frame_skip_config *in)
-{
- struct vfe_frame_skip_cfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeFrameSkip = *in;
-
- cmd.output2YPeriod = in->output2Period;
- cmd.output2CbCrPeriod = in->output2Period;
- cmd.output2YPattern = in->output2Pattern;
- cmd.output2CbCrPattern = in->output2Pattern;
- cmd.output1YPeriod = in->output1Period;
- cmd.output1CbCrPeriod = in->output1Period;
- cmd.output1YPattern = in->output1Pattern;
- cmd.output1CbCrPattern = in->output1Pattern;
-
- vfe_prog_hw(ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_output_clamp_config(struct vfe_cmd_output_clamp_config *in)
-{
- struct vfe_output_clamp_cfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- cmd.yChanMax = in->maxCh0;
- cmd.cbChanMax = in->maxCh1;
- cmd.crChanMax = in->maxCh2;
-
- cmd.yChanMin = in->minCh0;
- cmd.cbChanMin = in->minCh1;
- cmd.crChanMin = in->minCh2;
-
- vfe_prog_hw(ctrl->vfebase + VFE_CLAMP_MAX_CFG, (uint32_t *)&cmd,
- sizeof(cmd));
-}
-
-void vfe_camif_frame_update(struct vfe_cmds_camif_frame *in)
-{
- struct vfe_camifframe_update cmd;
-
- memset(&cmd, 0, sizeof(cmd));
-
- cmd.pixelsPerLine = in->pixelsPerLine;
- cmd.linesPerFrame = in->linesPerFrame;
-
- vfe_prog_hw(ctrl->vfebase + CAMIF_FRAME_CONFIG, (uint32_t *)&cmd,
- sizeof(cmd));
-}
-
-void vfe_color_correction_config(
- struct vfe_cmd_color_correction_config *in)
-{
- struct vfe_color_correction_cfg cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- ctrl->vfeModuleEnableLocal.colorCorrectionEnable = in->enable;
-
- cmd.c0 = in->C0;
- cmd.c1 = in->C1;
- cmd.c2 = in->C2;
- cmd.c3 = in->C3;
- cmd.c4 = in->C4;
- cmd.c5 = in->C5;
- cmd.c6 = in->C6;
- cmd.c7 = in->C7;
- cmd.c8 = in->C8;
-
- cmd.k0 = in->K0;
- cmd.k1 = in->K1;
- cmd.k2 = in->K2;
-
- cmd.coefQFactor = in->coefQFactor;
-
- vfe_prog_hw(ctrl->vfebase + VFE_COLOR_CORRECT_COEFF_0,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_demosaic_abf_update(struct vfe_cmd_demosaic_abf_update *in)
-{
-struct vfe_demosaic_cfg cmd;
- struct vfe_demosaic_abf_cfg cmdabf;
- uint32_t temp;
-
- memset(&cmd, 0, sizeof(cmd));
- temp = readl(ctrl->vfebase + VFE_DEMOSAIC_CFG);
-
- cmd = *((struct vfe_demosaic_cfg *)(&temp));
- cmd.abfEnable = in->abfUpdate.enable;
- cmd.forceAbfOn = in->abfUpdate.forceOn;
- cmd.abfShift = in->abfUpdate.shift;
- vfe_prog_hw(ctrl->vfebase + VFE_DEMOSAIC_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-
- cmdabf.lpThreshold = in->abfUpdate.lpThreshold;
- cmdabf.ratio = in->abfUpdate.ratio;
- cmdabf.minValue = in->abfUpdate.min;
- cmdabf.maxValue = in->abfUpdate.max;
- vfe_prog_hw(ctrl->vfebase + VFE_DEMOSAIC_ABF_CFG_0,
- (uint32_t *)&cmdabf, sizeof(cmdabf));
-}
-
-void vfe_demosaic_bpc_update(struct vfe_cmd_demosaic_bpc_update *in)
-{
- struct vfe_demosaic_cfg cmd;
- struct vfe_demosaic_bpc_cfg cmdbpc;
- uint32_t temp;
-
- memset(&cmd, 0, sizeof(cmd));
-
- temp = readl(ctrl->vfebase + VFE_DEMOSAIC_CFG);
-
- cmd = *((struct vfe_demosaic_cfg *)(&temp));
- cmd.badPixelCorrEnable = in->bpcUpdate.enable;
- cmd.fminThreshold = in->bpcUpdate.fminThreshold;
- cmd.fmaxThreshold = in->bpcUpdate.fmaxThreshold;
-
- vfe_prog_hw(ctrl->vfebase + VFE_DEMOSAIC_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-
- cmdbpc.blueDiffThreshold = in->bpcUpdate.blueDiffThreshold;
- cmdbpc.redDiffThreshold = in->bpcUpdate.redDiffThreshold;
- cmdbpc.greenDiffThreshold = in->bpcUpdate.greenDiffThreshold;
-
- vfe_prog_hw(ctrl->vfebase + VFE_DEMOSAIC_BPC_CFG_0,
- (uint32_t *)&cmdbpc, sizeof(cmdbpc));
-}
-
-void vfe_demosaic_config(struct vfe_cmd_demosaic_config *in)
-{
- struct vfe_demosaic_cfg cmd;
- struct vfe_demosaic_bpc_cfg cmd_bpc;
- struct vfe_demosaic_abf_cfg cmd_abf;
-
- memset(&cmd, 0, sizeof(cmd));
- memset(&cmd_bpc, 0, sizeof(cmd_bpc));
- memset(&cmd_abf, 0, sizeof(cmd_abf));
-
- ctrl->vfeModuleEnableLocal.demosaicEnable = in->enable;
-
- cmd.abfEnable = in->abfConfig.enable;
- cmd.badPixelCorrEnable = in->bpcConfig.enable;
- cmd.forceAbfOn = in->abfConfig.forceOn;
- cmd.abfShift = in->abfConfig.shift;
- cmd.fminThreshold = in->bpcConfig.fminThreshold;
- cmd.fmaxThreshold = in->bpcConfig.fmaxThreshold;
- cmd.slopeShift = in->slopeShift;
-
- vfe_prog_hw(ctrl->vfebase + VFE_DEMOSAIC_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-
- cmd_abf.lpThreshold = in->abfConfig.lpThreshold;
- cmd_abf.ratio = in->abfConfig.ratio;
- cmd_abf.minValue = in->abfConfig.min;
- cmd_abf.maxValue = in->abfConfig.max;
-
- vfe_prog_hw(ctrl->vfebase + VFE_DEMOSAIC_ABF_CFG_0,
- (uint32_t *)&cmd_abf, sizeof(cmd_abf));
-
- cmd_bpc.blueDiffThreshold = in->bpcConfig.blueDiffThreshold;
- cmd_bpc.redDiffThreshold = in->bpcConfig.redDiffThreshold;
- cmd_bpc.greenDiffThreshold = in->bpcConfig.greenDiffThreshold;
-
- vfe_prog_hw(ctrl->vfebase + VFE_DEMOSAIC_BPC_CFG_0,
- (uint32_t *)&cmd_bpc, sizeof(cmd_bpc));
-}
-
-void vfe_demux_channel_gain_update(
- struct vfe_cmd_demux_channel_gain_config *in)
-{
- struct vfe_demux_cfg cmd;
-
- memset(&cmd, 0, sizeof(cmd));
-
- cmd.ch0EvenGain = in->ch0EvenGain;
- cmd.ch0OddGain = in->ch0OddGain;
- cmd.ch1Gain = in->ch1Gain;
- cmd.ch2Gain = in->ch2Gain;
-
- vfe_prog_hw(ctrl->vfebase + VFE_DEMUX_GAIN_0,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_demux_channel_gain_config(
- struct vfe_cmd_demux_channel_gain_config *in)
-{
- struct vfe_demux_cfg cmd;
-
- memset(&cmd, 0, sizeof(cmd));
-
- cmd.ch0EvenGain = in->ch0EvenGain;
- cmd.ch0OddGain = in->ch0OddGain;
- cmd.ch1Gain = in->ch1Gain;
- cmd.ch2Gain = in->ch2Gain;
-
- vfe_prog_hw(ctrl->vfebase + VFE_DEMUX_GAIN_0,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_black_level_update(struct vfe_cmd_black_level_config *in)
-{
- struct vfe_blacklevel_cfg cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- ctrl->vfeModuleEnableLocal.blackLevelCorrectionEnable = in->enable;
-
- cmd.evenEvenAdjustment = in->evenEvenAdjustment;
- cmd.evenOddAdjustment = in->evenOddAdjustment;
- cmd.oddEvenAdjustment = in->oddEvenAdjustment;
- cmd.oddOddAdjustment = in->oddOddAdjustment;
-
- vfe_prog_hw(ctrl->vfebase + VFE_BLACK_EVEN_EVEN_VALUE,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_black_level_config(struct vfe_cmd_black_level_config *in)
-{
- struct vfe_blacklevel_cfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.blackLevelCorrectionEnable = in->enable;
-
- cmd.evenEvenAdjustment = in->evenEvenAdjustment;
- cmd.evenOddAdjustment = in->evenOddAdjustment;
- cmd.oddEvenAdjustment = in->oddEvenAdjustment;
- cmd.oddOddAdjustment = in->oddOddAdjustment;
-
- vfe_prog_hw(ctrl->vfebase + VFE_BLACK_EVEN_EVEN_VALUE,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_asf_update(struct vfe_cmd_asf_update *in)
-{
- struct vfe_asf_update cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.asfEnable = in->enable;
-
- cmd.smoothEnable = in->smoothFilterEnabled;
- cmd.sharpMode = in->sharpMode;
- cmd.smoothCoeff1 = in->smoothCoefCenter;
- cmd.smoothCoeff0 = in->smoothCoefSurr;
- cmd.cropEnable = in->cropEnable;
- cmd.sharpThresholdE1 = in->sharpThreshE1;
- cmd.sharpDegreeK1 = in->sharpK1;
- cmd.sharpDegreeK2 = in->sharpK2;
- cmd.normalizeFactor = in->normalizeFactor;
- cmd.sharpThresholdE2 = in->sharpThreshE2;
- cmd.sharpThresholdE3 = in->sharpThreshE3;
- cmd.sharpThresholdE4 = in->sharpThreshE4;
- cmd.sharpThresholdE5 = in->sharpThreshE5;
- cmd.F1Coeff0 = in->filter1Coefficients[0];
- cmd.F1Coeff1 = in->filter1Coefficients[1];
- cmd.F1Coeff2 = in->filter1Coefficients[2];
- cmd.F1Coeff3 = in->filter1Coefficients[3];
- cmd.F1Coeff4 = in->filter1Coefficients[4];
- cmd.F1Coeff5 = in->filter1Coefficients[5];
- cmd.F1Coeff6 = in->filter1Coefficients[6];
- cmd.F1Coeff7 = in->filter1Coefficients[7];
- cmd.F1Coeff8 = in->filter1Coefficients[8];
- cmd.F2Coeff0 = in->filter2Coefficients[0];
- cmd.F2Coeff1 = in->filter2Coefficients[1];
- cmd.F2Coeff2 = in->filter2Coefficients[2];
- cmd.F2Coeff3 = in->filter2Coefficients[3];
- cmd.F2Coeff4 = in->filter2Coefficients[4];
- cmd.F2Coeff5 = in->filter2Coefficients[5];
- cmd.F2Coeff6 = in->filter2Coefficients[6];
- cmd.F2Coeff7 = in->filter2Coefficients[7];
- cmd.F2Coeff8 = in->filter2Coefficients[8];
-
- vfe_prog_hw(ctrl->vfebase + VFE_ASF_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_asf_config(struct vfe_cmd_asf_config *in)
-{
- struct vfe_asf_update cmd;
- struct vfe_asfcrop_cfg cmd2;
-
- memset(&cmd, 0, sizeof(cmd));
- memset(&cmd2, 0, sizeof(cmd2));
-
- ctrl->vfeModuleEnableLocal.asfEnable = in->enable;
-
- cmd.smoothEnable = in->smoothFilterEnabled;
- cmd.sharpMode = in->sharpMode;
- cmd.smoothCoeff0 = in->smoothCoefCenter;
- cmd.smoothCoeff1 = in->smoothCoefSurr;
- cmd.cropEnable = in->cropEnable;
- cmd.sharpThresholdE1 = in->sharpThreshE1;
- cmd.sharpDegreeK1 = in->sharpK1;
- cmd.sharpDegreeK2 = in->sharpK2;
- cmd.normalizeFactor = in->normalizeFactor;
- cmd.sharpThresholdE2 = in->sharpThreshE2;
- cmd.sharpThresholdE3 = in->sharpThreshE3;
- cmd.sharpThresholdE4 = in->sharpThreshE4;
- cmd.sharpThresholdE5 = in->sharpThreshE5;
- cmd.F1Coeff0 = in->filter1Coefficients[0];
- cmd.F1Coeff1 = in->filter1Coefficients[1];
- cmd.F1Coeff2 = in->filter1Coefficients[2];
- cmd.F1Coeff3 = in->filter1Coefficients[3];
- cmd.F1Coeff4 = in->filter1Coefficients[4];
- cmd.F1Coeff5 = in->filter1Coefficients[5];
- cmd.F1Coeff6 = in->filter1Coefficients[6];
- cmd.F1Coeff7 = in->filter1Coefficients[7];
- cmd.F1Coeff8 = in->filter1Coefficients[8];
- cmd.F2Coeff0 = in->filter2Coefficients[0];
- cmd.F2Coeff1 = in->filter2Coefficients[1];
- cmd.F2Coeff2 = in->filter2Coefficients[2];
- cmd.F2Coeff3 = in->filter2Coefficients[3];
- cmd.F2Coeff4 = in->filter2Coefficients[4];
- cmd.F2Coeff5 = in->filter2Coefficients[5];
- cmd.F2Coeff6 = in->filter2Coefficients[6];
- cmd.F2Coeff7 = in->filter2Coefficients[7];
- cmd.F2Coeff8 = in->filter2Coefficients[8];
-
- vfe_prog_hw(ctrl->vfebase + VFE_ASF_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-
- cmd2.firstLine = in->cropFirstLine;
- cmd2.lastLine = in->cropLastLine;
- cmd2.firstPixel = in->cropFirstPixel;
- cmd2.lastPixel = in->cropLastPixel;
-
- vfe_prog_hw(ctrl->vfebase + VFE_ASF_CROP_WIDTH_CFG,
- (uint32_t *)&cmd2, sizeof(cmd2));
-}
-
-void vfe_white_balance_config(struct vfe_cmd_white_balance_config *in)
-{
- struct vfe_wb_cfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.whiteBalanceEnable =
- in->enable;
-
- cmd.ch0Gain = in->ch0Gain;
- cmd.ch1Gain = in->ch1Gain;
- cmd.ch2Gain = in->ch2Gain;
-
- vfe_prog_hw(ctrl->vfebase + VFE_WB_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_chroma_sup_config(struct vfe_cmd_chroma_suppression_config *in)
-{
- struct vfe_chroma_suppress_cfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.chromaSuppressionEnable = in->enable;
-
- cmd.m1 = in->m1;
- cmd.m3 = in->m3;
- cmd.n1 = in->n1;
- cmd.n3 = in->n3;
- cmd.mm1 = in->mm1;
- cmd.nn1 = in->nn1;
-
- vfe_prog_hw(ctrl->vfebase + VFE_CHROMA_SUPPRESS_CFG_0,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_roll_off_config(struct vfe_cmd_roll_off_config *in)
-{
- struct vfe_rolloff_cfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.lensRollOffEnable = in->enable;
-
- cmd.gridWidth = in->gridWidth;
- cmd.gridHeight = in->gridHeight;
- cmd.yDelta = in->yDelta;
- cmd.gridX = in->gridXIndex;
- cmd.gridY = in->gridYIndex;
- cmd.pixelX = in->gridPixelXIndex;
- cmd.pixelY = in->gridPixelYIndex;
- cmd.yDeltaAccum = in->yDeltaAccum;
-
- vfe_prog_hw(ctrl->vfebase + VFE_ROLLOFF_CFG_0,
- (uint32_t *)&cmd, sizeof(cmd));
-
- vfe_write_lens_roll_off_table(in);
-}
-
-void vfe_chroma_subsample_config(
- struct vfe_cmd_chroma_subsample_config *in)
-{
- struct vfe_chromasubsample_cfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.chromaSubsampleEnable = in->enable;
-
- cmd.hCositedPhase = in->hCositedPhase;
- cmd.vCositedPhase = in->vCositedPhase;
- cmd.hCosited = in->hCosited;
- cmd.vCosited = in->vCosited;
- cmd.hsubSampleEnable = in->hsubSampleEnable;
- cmd.vsubSampleEnable = in->vsubSampleEnable;
- cmd.cropEnable = in->cropEnable;
- cmd.cropWidthLastPixel = in->cropWidthLastPixel;
- cmd.cropWidthFirstPixel = in->cropWidthFirstPixel;
- cmd.cropHeightLastLine = in->cropHeightLastLine;
- cmd.cropHeightFirstLine = in->cropHeightFirstLine;
-
- vfe_prog_hw(ctrl->vfebase + VFE_CHROMA_SUBSAMPLE_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_chroma_enhan_config(struct vfe_cmd_chroma_enhan_config *in)
-{
- struct vfe_chroma_enhance_cfg cmd;
- struct vfe_color_convert_cfg cmd2;
-
- memset(&cmd, 0, sizeof(cmd));
- memset(&cmd2, 0, sizeof(cmd2));
-
- ctrl->vfeModuleEnableLocal.chromaEnhanEnable = in->enable;
-
- cmd.ap = in->ap;
- cmd.am = in->am;
- cmd.bp = in->bp;
- cmd.bm = in->bm;
- cmd.cp = in->cp;
- cmd.cm = in->cm;
- cmd.dp = in->dp;
- cmd.dm = in->dm;
- cmd.kcb = in->kcb;
- cmd.kcr = in->kcr;
-
- cmd2.v0 = in->RGBtoYConversionV0;
- cmd2.v1 = in->RGBtoYConversionV1;
- cmd2.v2 = in->RGBtoYConversionV2;
- cmd2.ConvertOffset = in->RGBtoYConversionOffset;
-
- vfe_prog_hw(ctrl->vfebase + VFE_CHROMA_ENHAN_A,
- (uint32_t *)&cmd, sizeof(cmd));
-
- vfe_prog_hw(ctrl->vfebase + VFE_COLOR_CONVERT_COEFF_0,
- (uint32_t *)&cmd2, sizeof(cmd2));
-}
-
-void vfe_scaler2cbcr_config(struct vfe_cmd_scaler2_config *in)
-{
- struct vfe_scaler2_cfg cmd;
-
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.scaler2CbcrEnable = in->enable;
-
- cmd.hEnable = in->hconfig.enable;
- cmd.vEnable = in->vconfig.enable;
- cmd.inWidth = in->hconfig.inputSize;
- cmd.outWidth = in->hconfig.outputSize;
- cmd.horizPhaseMult = in->hconfig.phaseMultiplicationFactor;
- cmd.horizInterResolution = in->hconfig.interpolationResolution;
- cmd.inHeight = in->vconfig.inputSize;
- cmd.outHeight = in->vconfig.outputSize;
- cmd.vertPhaseMult = in->vconfig.phaseMultiplicationFactor;
- cmd.vertInterResolution = in->vconfig.interpolationResolution;
-
- vfe_prog_hw(ctrl->vfebase + VFE_SCALE_CBCR_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_scaler2y_config(struct vfe_cmd_scaler2_config *in)
-{
- struct vfe_scaler2_cfg cmd;
-
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.scaler2YEnable = in->enable;
-
- cmd.hEnable = in->hconfig.enable;
- cmd.vEnable = in->vconfig.enable;
- cmd.inWidth = in->hconfig.inputSize;
- cmd.outWidth = in->hconfig.outputSize;
- cmd.horizPhaseMult = in->hconfig.phaseMultiplicationFactor;
- cmd.horizInterResolution = in->hconfig.interpolationResolution;
- cmd.inHeight = in->vconfig.inputSize;
- cmd.outHeight = in->vconfig.outputSize;
- cmd.vertPhaseMult = in->vconfig.phaseMultiplicationFactor;
- cmd.vertInterResolution = in->vconfig.interpolationResolution;
-
- vfe_prog_hw(ctrl->vfebase + VFE_SCALE_Y_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_main_scaler_config(struct vfe_cmd_main_scaler_config *in)
-{
- struct vfe_main_scaler_cfg cmd;
-
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.mainScalerEnable = in->enable;
-
- cmd.hEnable = in->hconfig.enable;
- cmd.vEnable = in->vconfig.enable;
- cmd.inWidth = in->hconfig.inputSize;
- cmd.outWidth = in->hconfig.outputSize;
- cmd.horizPhaseMult = in->hconfig.phaseMultiplicationFactor;
- cmd.horizInterResolution = in->hconfig.interpolationResolution;
- cmd.horizMNInit = in->MNInitH.MNCounterInit;
- cmd.horizPhaseInit = in->MNInitH.phaseInit;
- cmd.inHeight = in->vconfig.inputSize;
- cmd.outHeight = in->vconfig.outputSize;
- cmd.vertPhaseMult = in->vconfig.phaseMultiplicationFactor;
- cmd.vertInterResolution = in->vconfig.interpolationResolution;
- cmd.vertMNInit = in->MNInitV.MNCounterInit;
- cmd.vertPhaseInit = in->MNInitV.phaseInit;
-
- vfe_prog_hw(ctrl->vfebase + VFE_SCALE_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_stats_wb_exp_stop(void)
-{
- ctrl->vfeStatsCmdLocal.axwEnable = FALSE;
- ctrl->vfeImaskLocal.awbPingpongIrq = FALSE;
-}
-
-void vfe_stats_update_wb_exp(struct vfe_cmd_stats_wb_exp_update *in)
-{
- struct vfe_statsawb_update cmd;
- struct vfe_statsawbae_update cmd2;
-
- memset(&cmd, 0, sizeof(cmd));
- memset(&cmd2, 0, sizeof(cmd2));
-
- cmd.m1 = in->awbMCFG[0];
- cmd.m2 = in->awbMCFG[1];
- cmd.m3 = in->awbMCFG[2];
- cmd.m4 = in->awbMCFG[3];
- cmd.c1 = in->awbCCFG[0];
- cmd.c2 = in->awbCCFG[1];
- cmd.c3 = in->awbCCFG[2];
- cmd.c4 = in->awbCCFG[3];
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_AWB_MCFG,
- (uint32_t *)&cmd, sizeof(cmd));
-
- cmd2.aeRegionCfg = in->wbExpRegions;
- cmd2.aeSubregionCfg = in->wbExpSubRegion;
- cmd2.awbYMin = in->awbYMin;
- cmd2.awbYMax = in->awbYMax;
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_AWBAE_CFG,
- (uint32_t *)&cmd2, sizeof(cmd2));
-}
-
-void vfe_stats_update_af(struct vfe_cmd_stats_af_update *in)
-{
- struct vfe_statsaf_update cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- cmd.windowVOffset = in->windowVOffset;
- cmd.windowHOffset = in->windowHOffset;
- cmd.windowMode = in->windowMode;
- cmd.windowHeight = in->windowHeight;
- cmd.windowWidth = in->windowWidth;
-
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_AF_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_stats_start_wb_exp(struct vfe_cmd_stats_wb_exp_start *in)
-{
- struct vfe_statsawb_update cmd;
- struct vfe_statsawbae_update cmd2;
- struct vfe_statsaxw_hdr_cfg cmd3;
-
- ctrl->vfeStatsCmdLocal.axwEnable = in->enable;
- ctrl->vfeImaskLocal.awbPingpongIrq = TRUE;
-
- memset(&cmd, 0, sizeof(cmd));
- memset(&cmd2, 0, sizeof(cmd2));
- memset(&cmd3, 0, sizeof(cmd3));
-
- cmd.m1 = in->awbMCFG[0];
- cmd.m2 = in->awbMCFG[1];
- cmd.m3 = in->awbMCFG[2];
- cmd.m4 = in->awbMCFG[3];
- cmd.c1 = in->awbCCFG[0];
- cmd.c2 = in->awbCCFG[1];
- cmd.c3 = in->awbCCFG[2];
- cmd.c4 = in->awbCCFG[3];
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_AWB_MCFG,
- (uint32_t *)&cmd, sizeof(cmd));
-
- cmd2.aeRegionCfg = in->wbExpRegions;
- cmd2.aeSubregionCfg = in->wbExpSubRegion;
- cmd2.awbYMin = in->awbYMin;
- cmd2.awbYMax = in->awbYMax;
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_AWBAE_CFG,
- (uint32_t *)&cmd2, sizeof(cmd2));
-
- cmd3.axwHeader = in->axwHeader;
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_AXW_HEADER,
- (uint32_t *)&cmd3, sizeof(cmd3));
-}
-
-void vfe_stats_start_af(struct vfe_cmd_stats_af_start *in)
-{
- struct vfe_statsaf_update cmd;
- struct vfe_statsaf_cfg cmd2;
-
- memset(&cmd, 0, sizeof(cmd));
- memset(&cmd2, 0, sizeof(cmd2));
-
-ctrl->vfeStatsCmdLocal.autoFocusEnable = in->enable;
-ctrl->vfeImaskLocal.afPingpongIrq = TRUE;
-
- cmd.windowVOffset = in->windowVOffset;
- cmd.windowHOffset = in->windowHOffset;
- cmd.windowMode = in->windowMode;
- cmd.windowHeight = in->windowHeight;
- cmd.windowWidth = in->windowWidth;
-
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_AF_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-
- cmd2.a00 = in->highPassCoef[0];
- cmd2.a04 = in->highPassCoef[1];
- cmd2.a20 = in->highPassCoef[2];
- cmd2.a21 = in->highPassCoef[3];
- cmd2.a22 = in->highPassCoef[4];
- cmd2.a23 = in->highPassCoef[5];
- cmd2.a24 = in->highPassCoef[6];
- cmd2.fvMax = in->metricMax;
- cmd2.fvMetric = in->metricSelection;
- cmd2.afHeader = in->bufferHeader;
- cmd2.entry00 = in->gridForMultiWindows[0];
- cmd2.entry01 = in->gridForMultiWindows[1];
- cmd2.entry02 = in->gridForMultiWindows[2];
- cmd2.entry03 = in->gridForMultiWindows[3];
- cmd2.entry10 = in->gridForMultiWindows[4];
- cmd2.entry11 = in->gridForMultiWindows[5];
- cmd2.entry12 = in->gridForMultiWindows[6];
- cmd2.entry13 = in->gridForMultiWindows[7];
- cmd2.entry20 = in->gridForMultiWindows[8];
- cmd2.entry21 = in->gridForMultiWindows[9];
- cmd2.entry22 = in->gridForMultiWindows[10];
- cmd2.entry23 = in->gridForMultiWindows[11];
- cmd2.entry30 = in->gridForMultiWindows[12];
- cmd2.entry31 = in->gridForMultiWindows[13];
- cmd2.entry32 = in->gridForMultiWindows[14];
- cmd2.entry33 = in->gridForMultiWindows[15];
-
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_AF_GRID_0,
- (uint32_t *)&cmd2, sizeof(cmd2));
-}
-
-void vfe_stats_setting(struct vfe_cmd_stats_setting *in)
-{
- struct vfe_statsframe cmd1;
- struct vfe_busstats_wrprio cmd2;
-
- memset(&cmd1, 0, sizeof(cmd1));
- memset(&cmd2, 0, sizeof(cmd2));
-
- ctrl->afStatsControl.addressBuffer[0] = in->afBuffer[0];
- ctrl->afStatsControl.addressBuffer[1] = in->afBuffer[1];
- ctrl->afStatsControl.nextFrameAddrBuf = in->afBuffer[2];
-
- ctrl->awbStatsControl.addressBuffer[0] = in->awbBuffer[0];
- ctrl->awbStatsControl.addressBuffer[1] = in->awbBuffer[1];
- ctrl->awbStatsControl.nextFrameAddrBuf = in->awbBuffer[2];
-
- cmd1.lastPixel = in->frameHDimension;
- cmd1.lastLine = in->frameVDimension;
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_FRAME_SIZE,
- (uint32_t *)&cmd1, sizeof(cmd1));
-
- cmd2.afBusPriority = in->afBusPriority;
- cmd2.awbBusPriority = in->awbBusPriority;
- cmd2.histBusPriority = in->histBusPriority;
- cmd2.afBusPriorityEn = in->afBusPrioritySelection;
- cmd2.awbBusPriorityEn = in->awbBusPrioritySelection;
- cmd2.histBusPriorityEn = in->histBusPrioritySelection;
-
- vfe_prog_hw(ctrl->vfebase + VFE_BUS_STATS_WR_PRIORITY,
- (uint32_t *)&cmd2, sizeof(cmd2));
-
- /* Program the bus ping pong address for statistics modules. */
- writel(in->afBuffer[0], ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
- writel(in->afBuffer[1], ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
- writel(in->awbBuffer[0],
- ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
- writel(in->awbBuffer[1],
- ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
- writel(in->histBuffer[0],
- ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PING_ADDR);
- writel(in->histBuffer[1],
- ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PONG_ADDR);
-}
-
-void vfe_axi_input_config(struct vfe_cmd_axi_input_config *in)
-{
- struct VFE_AxiInputCmdType cmd;
- uint32_t xSizeWord, axiRdUnpackPattern;
- uint8_t axiInputPpw;
- uint32_t busPingpongRdIrqEnable;
-
- ctrl->vfeImaskLocal.rdPingpongIrq = TRUE;
-
- switch (in->pixelSize) {
- case VFE_RAW_PIXEL_DATA_SIZE_10BIT:
- ctrl->axiInputDataSize = VFE_RAW_PIXEL_DATA_SIZE_10BIT;
- break;
-
- case VFE_RAW_PIXEL_DATA_SIZE_12BIT:
- ctrl->axiInputDataSize = VFE_RAW_PIXEL_DATA_SIZE_12BIT;
- break;
-
- case VFE_RAW_PIXEL_DATA_SIZE_8BIT:
- default:
- ctrl->axiInputDataSize = VFE_RAW_PIXEL_DATA_SIZE_8BIT;
- break;
- }
-
- memset(&cmd, 0, sizeof(cmd));
-
- switch (in->pixelSize) {
- case VFE_RAW_PIXEL_DATA_SIZE_10BIT:
- axiInputPpw = 6;
- axiRdUnpackPattern = 0xD43210;
- break;
-
- case VFE_RAW_PIXEL_DATA_SIZE_12BIT:
- axiInputPpw = 5;
- axiRdUnpackPattern = 0xC3210;
- break;
-
- case VFE_RAW_PIXEL_DATA_SIZE_8BIT:
- default:
- axiInputPpw = 8;
- axiRdUnpackPattern = 0xF6543210;
- break;
- }
-
- xSizeWord =
- ((((in->xOffset % axiInputPpw) + in->xSize) +
- (axiInputPpw-1)) / axiInputPpw) - 1;
-
- cmd.stripeStartAddr0 = in->fragAddr[0];
- cmd.stripeStartAddr1 = in->fragAddr[1];
- cmd.stripeStartAddr2 = in->fragAddr[2];
- cmd.stripeStartAddr3 = in->fragAddr[3];
- cmd.ySize = in->ySize;
- cmd.yOffsetDelta = 0;
- cmd.xSizeWord = xSizeWord;
- cmd.burstLength = 1;
- cmd.NumOfRows = in->numOfRows;
- cmd.RowIncrement =
- (in->rowIncrement + (axiInputPpw-1))/axiInputPpw;
- cmd.mainUnpackHeight = in->ySize;
- cmd.mainUnpackWidth = in->xSize - 1;
- cmd.mainUnpackHbiSel = (uint32_t)in->unpackHbi;
- cmd.mainUnpackPhase = in->unpackPhase;
- cmd.unpackPattern = axiRdUnpackPattern;
- cmd.padLeft = in->padRepeatCountLeft;
- cmd.padRight = in->padRepeatCountRight;
- cmd.padTop = in->padRepeatCountTop;
- cmd.padBottom = in->padRepeatCountBottom;
- cmd.leftUnpackPattern0 = in->padLeftComponentSelectCycle0;
- cmd.leftUnpackPattern1 = in->padLeftComponentSelectCycle1;
- cmd.leftUnpackPattern2 = in->padLeftComponentSelectCycle2;
- cmd.leftUnpackPattern3 = in->padLeftComponentSelectCycle3;
- cmd.leftUnpackStop0 = in->padLeftStopCycle0;
- cmd.leftUnpackStop1 = in->padLeftStopCycle1;
- cmd.leftUnpackStop2 = in->padLeftStopCycle2;
- cmd.leftUnpackStop3 = in->padLeftStopCycle3;
- cmd.rightUnpackPattern0 = in->padRightComponentSelectCycle0;
- cmd.rightUnpackPattern1 = in->padRightComponentSelectCycle1;
- cmd.rightUnpackPattern2 = in->padRightComponentSelectCycle2;
- cmd.rightUnpackPattern3 = in->padRightComponentSelectCycle3;
- cmd.rightUnpackStop0 = in->padRightStopCycle0;
- cmd.rightUnpackStop1 = in->padRightStopCycle1;
- cmd.rightUnpackStop2 = in->padRightStopCycle2;
- cmd.rightUnpackStop3 = in->padRightStopCycle3;
- cmd.topUnapckPattern = in->padTopLineCount;
- cmd.bottomUnapckPattern = in->padBottomLineCount;
-
- /* program vfe_bus_cfg */
- vfe_prog_hw(ctrl->vfebase + VFE_BUS_STRIPE_RD_ADDR_0,
- (uint32_t *)&cmd, sizeof(cmd));
-
- /* hacking code, put it to default value */
- busPingpongRdIrqEnable = 0xf;
-
- writel(busPingpongRdIrqEnable,
- ctrl->vfebase + VFE_BUS_PINGPONG_IRQ_EN);
-}
-
-void vfe_stats_config(struct vfe_cmd_stats_setting *in)
-{
- ctrl->afStatsControl.addressBuffer[0] = in->afBuffer[0];
- ctrl->afStatsControl.addressBuffer[1] = in->afBuffer[1];
- ctrl->afStatsControl.nextFrameAddrBuf = in->afBuffer[2];
-
- ctrl->awbStatsControl.addressBuffer[0] = in->awbBuffer[0];
- ctrl->awbStatsControl.addressBuffer[1] = in->awbBuffer[1];
- ctrl->awbStatsControl.nextFrameAddrBuf = in->awbBuffer[2];
-
- vfe_stats_setting(in);
-}
-
-void vfe_axi_output_config(
- struct vfe_cmd_axi_output_config *in)
-{
- /* local variable */
- uint32_t *pcircle;
- uint32_t *pdest;
- uint32_t *psrc;
- uint8_t i;
- uint8_t fcnt;
- uint16_t axioutpw = 8;
-
- /* parameters check, condition and usage mode check */
- ctrl->encPath.fragCount = in->output2.fragmentCount;
- if (ctrl->encPath.fragCount > 1)
- ctrl->encPath.multiFrag = TRUE;
-
- ctrl->viewPath.fragCount = in->output1.fragmentCount;
- if (ctrl->viewPath.fragCount > 1)
- ctrl->viewPath.multiFrag = TRUE;
-
- /* VFE_BUS_CFG. raw data size */
- ctrl->vfeBusConfigLocal.rawPixelDataSize = in->outputDataSize;
-
- switch (in->outputDataSize) {
- case VFE_RAW_PIXEL_DATA_SIZE_8BIT:
- axioutpw = 8;
- break;
-
- case VFE_RAW_PIXEL_DATA_SIZE_10BIT:
- axioutpw = 6;
- break;
-
- case VFE_RAW_PIXEL_DATA_SIZE_12BIT:
- axioutpw = 5;
- break;
- }
-
- ctrl->axiOutputMode = in->outputMode;
-
- CDBG("axiOutputMode = %d\n", ctrl->axiOutputMode);
-
- switch (ctrl->axiOutputMode) {
- case VFE_AXI_OUTPUT_MODE_Output1: {
- ctrl->vfeCamifConfigLocal.camif2BusEnable = FALSE;
- ctrl->vfeCamifConfigLocal.camif2OutputEnable = TRUE;
- ctrl->vfeBusConfigLocal.rawWritePathSelect =
- VFE_RAW_OUTPUT_DISABLED;
-
- ctrl->encPath.pathEnabled = FALSE;
- ctrl->vfeImaskLocal.encIrq = FALSE;
- ctrl->vfeIrqCompositeMaskLocal.encIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.encYWrPathEn = FALSE;
- ctrl->vfeBusConfigLocal.encCbcrWrPathEn = FALSE;
- ctrl->viewPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.viewIrq = TRUE;
- ctrl->vfeIrqCompositeMaskLocal.viewIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.viewYWrPathEn = TRUE;
- ctrl->vfeBusConfigLocal.viewCbcrWrPathEn = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encYWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encCbcrWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encCbcrPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewYWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewCbcrWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewCbcrPingpongIrq = TRUE;
- } /* VFE_AXI_OUTPUT_MODE_Output1 */
- break;
-
- case VFE_AXI_OUTPUT_MODE_Output2: {
- ctrl->vfeCamifConfigLocal.camif2BusEnable = FALSE;
- ctrl->vfeCamifConfigLocal.camif2OutputEnable = TRUE;
- ctrl->vfeBusConfigLocal.rawWritePathSelect =
- VFE_RAW_OUTPUT_DISABLED;
-
- ctrl->encPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.encIrq = TRUE;
- ctrl->vfeIrqCompositeMaskLocal.encIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.encYWrPathEn = TRUE;
- ctrl->vfeBusConfigLocal.encCbcrWrPathEn = TRUE;
-
- ctrl->viewPath.pathEnabled = FALSE;
- ctrl->vfeImaskLocal.viewIrq = FALSE;
- ctrl->vfeIrqCompositeMaskLocal.viewIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.viewYWrPathEn = FALSE;
- ctrl->vfeBusConfigLocal.viewCbcrWrPathEn = FALSE;
-
- if (ctrl->vfeBusConfigLocal.encYWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encCbcrWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encCbcrPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewYWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewCbcrWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewCbcrPingpongIrq = TRUE;
- } /* VFE_AXI_OUTPUT_MODE_Output2 */
- break;
-
- case VFE_AXI_OUTPUT_MODE_Output1AndOutput2: {
- ctrl->vfeCamifConfigLocal.camif2BusEnable = FALSE;
- ctrl->vfeCamifConfigLocal.camif2OutputEnable = TRUE;
- ctrl->vfeBusConfigLocal.rawWritePathSelect =
- VFE_RAW_OUTPUT_DISABLED;
-
- ctrl->encPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.encIrq = TRUE;
- ctrl->vfeIrqCompositeMaskLocal.encIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.encYWrPathEn = TRUE;
- ctrl->vfeBusConfigLocal.encCbcrWrPathEn = TRUE;
- ctrl->viewPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.viewIrq = TRUE;
- ctrl->vfeIrqCompositeMaskLocal.viewIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.viewYWrPathEn = TRUE;
- ctrl->vfeBusConfigLocal.viewCbcrWrPathEn = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encYWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encCbcrWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encCbcrPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewYWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewCbcrWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewCbcrPingpongIrq = TRUE;
- } /* VFE_AXI_OUTPUT_MODE_Output1AndOutput2 */
- break;
-
- case VFE_AXI_OUTPUT_MODE_CAMIFToAXIViaOutput2: {
- /* For raw snapshot, we need both ping and pong buffer
- * initialized to the same address. Otherwise, if we
- * leave the pong buffer to NULL, there will be axi_error.
- * Note that ideally we should deal with this at upper layer,
- * which is in msm_vfe8x.c */
- if (!in->output2.outputCbcr.outFragments[1][0]) {
- in->output2.outputCbcr.outFragments[1][0] =
- in->output2.outputCbcr.outFragments[0][0];
- }
-
- ctrl->vfeCamifConfigLocal.camif2BusEnable = TRUE;
- ctrl->vfeCamifConfigLocal.camif2OutputEnable = FALSE;
- ctrl->vfeBusConfigLocal.rawWritePathSelect =
- VFE_RAW_OUTPUT_ENC_CBCR_PATH;
-
- ctrl->encPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.encIrq = TRUE;
- ctrl->vfeIrqCompositeMaskLocal.encIrqComMask =
- VFE_COMP_IRQ_CBCR_ONLY;
-
- ctrl->vfeBusConfigLocal.encYWrPathEn = FALSE;
- ctrl->vfeBusConfigLocal.encCbcrWrPathEn = TRUE;
-
- ctrl->viewPath.pathEnabled = FALSE;
- ctrl->vfeImaskLocal.viewIrq = FALSE;
- ctrl->vfeIrqCompositeMaskLocal.viewIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.viewYWrPathEn = FALSE;
- ctrl->vfeBusConfigLocal.viewCbcrWrPathEn = FALSE;
-
- if (ctrl->vfeBusConfigLocal.encYWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encCbcrWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encCbcrPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewYWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewCbcrWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewCbcrPingpongIrq = TRUE;
- } /* VFE_AXI_OUTPUT_MODE_CAMIFToAXIViaOutput2 */
- break;
-
- case VFE_AXI_OUTPUT_MODE_Output2AndCAMIFToAXIViaOutput1: {
- ctrl->vfeCamifConfigLocal.camif2BusEnable = TRUE;
- ctrl->vfeCamifConfigLocal.camif2OutputEnable = TRUE;
- ctrl->vfeBusConfigLocal.rawWritePathSelect =
- VFE_RAW_OUTPUT_VIEW_CBCR_PATH;
-
- ctrl->encPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.encIrq = TRUE;
- ctrl->vfeIrqCompositeMaskLocal.encIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.encYWrPathEn = TRUE;
- ctrl->vfeBusConfigLocal.encCbcrWrPathEn = TRUE;
-
- ctrl->viewPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.viewIrq = TRUE;
- ctrl->vfeIrqCompositeMaskLocal.viewIrqComMask =
- VFE_COMP_IRQ_CBCR_ONLY;
-
- ctrl->vfeBusConfigLocal.viewYWrPathEn = FALSE;
- ctrl->vfeBusConfigLocal.viewCbcrWrPathEn = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encYWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encCbcrWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encCbcrPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewYWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewCbcrWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewCbcrPingpongIrq = TRUE;
- } /* VFE_AXI_OUTPUT_MODE_Output2AndCAMIFToAXIViaOutput1 */
- break;
-
- case VFE_AXI_OUTPUT_MODE_Output1AndCAMIFToAXIViaOutput2: {
- ctrl->vfeCamifConfigLocal.camif2BusEnable = TRUE;
- ctrl->vfeCamifConfigLocal.camif2OutputEnable = TRUE;
- ctrl->vfeBusConfigLocal.rawWritePathSelect =
- VFE_RAW_OUTPUT_ENC_CBCR_PATH;
-
- ctrl->encPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.encIrq = TRUE;
- ctrl->vfeIrqCompositeMaskLocal.encIrqComMask =
- VFE_COMP_IRQ_CBCR_ONLY;
-
- ctrl->vfeBusConfigLocal.encYWrPathEn = FALSE;
- ctrl->vfeBusConfigLocal.encCbcrWrPathEn = TRUE;
-
- ctrl->viewPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.viewIrq = TRUE;
-
- ctrl->vfeIrqCompositeMaskLocal.viewIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.viewYWrPathEn = TRUE;
- ctrl->vfeBusConfigLocal.viewCbcrWrPathEn = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encYWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encCbcrWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encCbcrPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewYWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewCbcrWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewCbcrPingpongIrq = TRUE;
- } /* VFE_AXI_OUTPUT_MODE_Output1AndCAMIFToAXIViaOutput2 */
- break;
-
- case VFE_AXI_LAST_OUTPUT_MODE_ENUM:
- break;
- } /* switch */
-
- /* Save the addresses for each path. */
- /* output2 path */
- fcnt = ctrl->encPath.fragCount;
-
- pcircle = ctrl->encPath.yPath.addressBuffer;
- pdest = ctrl->encPath.nextFrameAddrBuf;
-
- psrc = &(in->output2.outputY.outFragments[0][0]);
- for (i = 0; i < fcnt; i++)
- *pcircle++ = *psrc++;
-
- psrc = &(in->output2.outputY.outFragments[1][0]);
- for (i = 0; i < fcnt; i++)
- *pcircle++ = *psrc++;
-
- psrc = &(in->output2.outputY.outFragments[2][0]);
- for (i = 0; i < fcnt; i++)
- *pdest++ = *psrc++;
-
- pcircle = ctrl->encPath.cbcrPath.addressBuffer;
-
- psrc = &(in->output2.outputCbcr.outFragments[0][0]);
- for (i = 0; i < fcnt; i++)
- *pcircle++ = *psrc++;
-
- psrc = &(in->output2.outputCbcr.outFragments[1][0]);
- for (i = 0; i < fcnt; i++)
- *pcircle++ = *psrc++;
-
- psrc = &(in->output2.outputCbcr.outFragments[2][0]);
- for (i = 0; i < fcnt; i++)
- *pdest++ = *psrc++;
-
- vfe_set_bus_pipo_addr(&ctrl->viewPath, &ctrl->encPath);
-
- ctrl->encPath.ackPending = FALSE;
- ctrl->encPath.currentFrame = ping;
- ctrl->encPath.whichOutputPath = 1;
- ctrl->encPath.yPath.fragIndex = 2;
- ctrl->encPath.cbcrPath.fragIndex = 2;
- ctrl->encPath.yPath.hwCurrentFlag = ping;
- ctrl->encPath.cbcrPath.hwCurrentFlag = ping;
-
- /* output1 path */
- pcircle = ctrl->viewPath.yPath.addressBuffer;
- pdest = ctrl->viewPath.nextFrameAddrBuf;
- fcnt = ctrl->viewPath.fragCount;
-
- psrc = &(in->output1.outputY.outFragments[0][0]);
- for (i = 0; i < fcnt; i++)
- *pcircle++ = *psrc++;
-
- psrc = &(in->output1.outputY.outFragments[1][0]);
- for (i = 0; i < fcnt; i++)
- *pcircle++ = *psrc++;
-
- psrc = &(in->output1.outputY.outFragments[2][0]);
- for (i = 0; i < fcnt; i++)
- *pdest++ = *psrc++;
-
- pcircle = ctrl->viewPath.cbcrPath.addressBuffer;
-
- psrc = &(in->output1.outputCbcr.outFragments[0][0]);
- for (i = 0; i < fcnt; i++)
- *pcircle++ = *psrc++;
-
- psrc = &(in->output1.outputCbcr.outFragments[1][0]);
- for (i = 0; i < fcnt; i++)
- *pcircle++ = *psrc++;
-
- psrc = &(in->output1.outputCbcr.outFragments[2][0]);
- for (i = 0; i < fcnt; i++)
- *pdest++ = *psrc++;
-
- ctrl->viewPath.ackPending = FALSE;
- ctrl->viewPath.currentFrame = ping;
- ctrl->viewPath.whichOutputPath = 0;
- ctrl->viewPath.yPath.fragIndex = 2;
- ctrl->viewPath.cbcrPath.fragIndex = 2;
- ctrl->viewPath.yPath.hwCurrentFlag = ping;
- ctrl->viewPath.cbcrPath.hwCurrentFlag = ping;
-
- /* call to program the registers. */
- vfe_axi_output(in, &ctrl->viewPath, &ctrl->encPath, axioutpw);
-}
-
-void vfe_camif_config(struct vfe_cmd_camif_config *in)
-{
- struct vfe_camifcfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- CDBG("camif.frame pixelsPerLine = %d\n", in->frame.pixelsPerLine);
- CDBG("camif.frame linesPerFrame = %d\n", in->frame.linesPerFrame);
- CDBG("camif.window firstpixel = %d\n", in->window.firstpixel);
- CDBG("camif.window lastpixel = %d\n", in->window.lastpixel);
- CDBG("camif.window firstline = %d\n", in->window.firstline);
- CDBG("camif.window lastline = %d\n", in->window.lastline);
-
- /* determine if epoch interrupt needs to be enabled. */
- if ((in->epoch1.enable == TRUE) &&
- (in->epoch1.lineindex <=
- in->frame.linesPerFrame))
- ctrl->vfeImaskLocal.camifEpoch1Irq = 1;
-
- if ((in->epoch2.enable == TRUE) &&
- (in->epoch2.lineindex <=
- in->frame.linesPerFrame)) {
- ctrl->vfeImaskLocal.camifEpoch2Irq = 1;
- }
-
- /* save the content to program CAMIF_CONFIG separately. */
- ctrl->vfeCamifConfigLocal.camifCfgFromCmd = in->camifConfig;
-
- /* EFS_Config */
- cmd.efsEndOfLine = in->EFS.efsendofline;
- cmd.efsStartOfLine = in->EFS.efsstartofline;
- cmd.efsEndOfFrame = in->EFS.efsendofframe;
- cmd.efsStartOfFrame = in->EFS.efsstartofframe;
-
- /* Frame Config */
- cmd.frameConfigPixelsPerLine = in->frame.pixelsPerLine;
- cmd.frameConfigLinesPerFrame = in->frame.linesPerFrame;
-
- /* Window Width Config */
- cmd.windowWidthCfgLastPixel = in->window.lastpixel;
- cmd.windowWidthCfgFirstPixel = in->window.firstpixel;
-
- /* Window Height Config */
- cmd.windowHeightCfglastLine = in->window.lastline;
- cmd.windowHeightCfgfirstLine = in->window.firstline;
-
- /* Subsample 1 Config */
- cmd.subsample1CfgPixelSkip = in->subsample.pixelskipmask;
- cmd.subsample1CfgLineSkip = in->subsample.lineskipmask;
-
- /* Subsample 2 Config */
- cmd.subsample2CfgFrameSkip = in->subsample.frameskip;
- cmd.subsample2CfgFrameSkipMode = in->subsample.frameskipmode;
- cmd.subsample2CfgPixelSkipWrap = in->subsample.pixelskipwrap;
-
- /* Epoch Interrupt */
- cmd.epoch1Line = in->epoch1.lineindex;
- cmd.epoch2Line = in->epoch2.lineindex;
-
- vfe_prog_hw(ctrl->vfebase + CAMIF_EFS_CONFIG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_fov_crop_config(struct vfe_cmd_fov_crop_config *in)
-{
- struct vfe_fov_crop_cfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.cropEnable = in->enable;
-
- /* FOV Corp, Part 1 */
- cmd.lastPixel = in->lastPixel;
- cmd.firstPixel = in->firstPixel;
-
- /* FOV Corp, Part 2 */
- cmd.lastLine = in->lastLine;
- cmd.firstLine = in->firstLine;
-
- vfe_prog_hw(ctrl->vfebase + VFE_CROP_WIDTH_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_get_hw_version(struct vfe_cmd_hw_version *out)
-{
- uint32_t vfeHwVersionPacked;
- struct vfe_hw_ver ver;
-
- vfeHwVersionPacked = readl(ctrl->vfebase + VFE_HW_VERSION);
-
- ver = *((struct vfe_hw_ver *)&vfeHwVersionPacked);
-
- out->coreVersion = ver.coreVersion;
- out->minorVersion = ver.minorVersion;
- out->majorVersion = ver.majorVersion;
-}
-
-static void vfe_reset_internal_variables(void)
-{
- unsigned long flags;
-
- /* local variables to program the hardware. */
- ctrl->vfeImaskPacked = 0;
- ctrl->vfeImaskCompositePacked = 0;
-
- /* FALSE = disable, 1 = enable. */
- memset(&ctrl->vfeModuleEnableLocal, 0,
- sizeof(ctrl->vfeModuleEnableLocal));
-
- /* 0 = disable, 1 = enable */
- memset(&ctrl->vfeCamifConfigLocal, 0,
- sizeof(ctrl->vfeCamifConfigLocal));
- /* 0 = disable, 1 = enable */
- memset(&ctrl->vfeImaskLocal, 0, sizeof(ctrl->vfeImaskLocal));
- memset(&ctrl->vfeStatsCmdLocal, 0, sizeof(ctrl->vfeStatsCmdLocal));
- memset(&ctrl->vfeBusConfigLocal, 0, sizeof(ctrl->vfeBusConfigLocal));
- memset(&ctrl->vfeBusPmConfigLocal, 0,
- sizeof(ctrl->vfeBusPmConfigLocal));
- memset(&ctrl->vfeBusCmdLocal, 0, sizeof(ctrl->vfeBusCmdLocal));
- memset(&ctrl->vfeInterruptNameLocal, 0,
- sizeof(ctrl->vfeInterruptNameLocal));
- memset(&ctrl->vfeDroppedFrameCounts, 0,
- sizeof(ctrl->vfeDroppedFrameCounts));
- memset(&ctrl->vfeIrqThreadMsgLocal, 0,
- sizeof(ctrl->vfeIrqThreadMsgLocal));
-
- /* state control variables */
- ctrl->vfeStartAckPendingFlag = FALSE;
- ctrl->vfeStopAckPending = FALSE;
- ctrl->vfeIrqCompositeMaskLocal.ceDoneSel = 0;
- ctrl->vfeIrqCompositeMaskLocal.encIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
- ctrl->vfeIrqCompositeMaskLocal.viewIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- spin_lock_irqsave(&ctrl->state_lock, flags);
- ctrl->vstate = VFE_STATE_IDLE;
- spin_unlock_irqrestore(&ctrl->state_lock, flags);
-
- ctrl->axiOutputMode = VFE_AXI_LAST_OUTPUT_MODE_ENUM;
- /* 0 for continuous mode, 1 for snapshot mode */
- ctrl->vfeOperationMode = VFE_START_OPERATION_MODE_CONTINUOUS;
- ctrl->vfeSnapShotCount = 0;
- ctrl->vfeStatsPingPongReloadFlag = FALSE;
- /* this is unsigned 32 bit integer. */
- ctrl->vfeFrameId = 0;
- ctrl->vfeFrameSkip.output1Pattern = 0xffffffff;
- ctrl->vfeFrameSkip.output1Period = 31;
- ctrl->vfeFrameSkip.output2Pattern = 0xffffffff;
- ctrl->vfeFrameSkip.output2Period = 31;
- ctrl->vfeFrameSkipPattern = 0xffffffff;
- ctrl->vfeFrameSkipCount = 0;
- ctrl->vfeFrameSkipPeriod = 31;
-
- memset((void *)&ctrl->encPath, 0, sizeof(ctrl->encPath));
- memset((void *)&ctrl->viewPath, 0, sizeof(ctrl->viewPath));
-
- ctrl->encPath.whichOutputPath = 1;
- ctrl->encPath.cbcrStatusBit = 5;
- ctrl->viewPath.whichOutputPath = 0;
- ctrl->viewPath.cbcrStatusBit = 7;
-
- ctrl->vfeTestGenStartFlag = FALSE;
-
- /* default to bank 0. */
- ctrl->vfeLaBankSel = 0;
-
- /* default to bank 0 for all channels. */
- memset(&ctrl->vfeGammaLutSel, 0, sizeof(ctrl->vfeGammaLutSel));
-
- /* Stats control variables. */
- memset(&ctrl->afStatsControl, 0, sizeof(ctrl->afStatsControl));
- memset(&ctrl->awbStatsControl, 0, sizeof(ctrl->awbStatsControl));
- vfe_set_stats_pingpong_address(&ctrl->afStatsControl,
- &ctrl->awbStatsControl);
-}
-
-void vfe_reset(void)
-{
- vfe_reset_internal_variables();
-
- ctrl->vfeImaskLocal.resetAckIrq = TRUE;
- ctrl->vfeImaskPacked = vfe_irq_pack(ctrl->vfeImaskLocal);
-
- /* disable all interrupts. */
- writel(VFE_DISABLE_ALL_IRQS,
- ctrl->vfebase + VFE_IRQ_COMPOSITE_MASK);
-
- /* clear all pending interrupts*/
- writel(VFE_CLEAR_ALL_IRQS,
- ctrl->vfebase + VFE_IRQ_CLEAR);
-
- /* enable reset_ack interrupt. */
- writel(ctrl->vfeImaskPacked,
- ctrl->vfebase + VFE_IRQ_MASK);
-
- writel(VFE_RESET_UPON_RESET_CMD,
- ctrl->vfebase + VFE_GLOBAL_RESET_CMD);
-}
diff --git a/trunk/drivers/staging/dream/camera/msm_vfe8x_proc.h b/trunk/drivers/staging/dream/camera/msm_vfe8x_proc.h
deleted file mode 100644
index 91828569a4d7..000000000000
--- a/trunk/drivers/staging/dream/camera/msm_vfe8x_proc.h
+++ /dev/null
@@ -1,1549 +0,0 @@
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#ifndef __MSM_VFE8X_REG_H__
-#define __MSM_VFE8X_REG_H__
-
-#include
-#include
-#include "msm_vfe8x.h"
-
-/* at start of camif, bit 1:0 = 0x01:enable
- * image data capture at frame boundary. */
-#define CAMIF_COMMAND_START 0x00000005
-
-/* bit 2= 0x1:clear the CAMIF_STATUS register
- * value. */
-#define CAMIF_COMMAND_CLEAR 0x00000004
-
-/* at stop of vfe pipeline, for now it is assumed
- * that camif will stop at any time. Bit 1:0 = 0x10:
- * disable image data capture immediately. */
-#define CAMIF_COMMAND_STOP_IMMEDIATELY 0x00000002
-
-/* at stop of vfe pipeline, for now it is assumed
- * that camif will stop at any time. Bit 1:0 = 0x00:
- * disable image data capture at frame boundary */
-#define CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY 0x00000000
-
-/* to halt axi bridge */
-#define AXI_HALT 0x00000001
-
-/* clear the halt bit. */
-#define AXI_HALT_CLEAR 0x00000000
-
-/* reset the pipeline when stop command is issued.
- * (without reset the register.) bit 26-31 = 0,
- * domain reset, bit 0-9 = 1 for module reset, except
- * register module. */
-#define VFE_RESET_UPON_STOP_CMD 0x000003ef
-
-/* reset the pipeline when reset command.
- * bit 26-31 = 0, domain reset, bit 0-9 = 1 for module reset. */
-#define VFE_RESET_UPON_RESET_CMD 0x000003ff
-
-/* bit 5 is for axi status idle or busy.
- * 1 = halted, 0 = busy */
-#define AXI_STATUS_BUSY_MASK 0x00000020
-
-/* bit 0 & bit 1 = 1, both y and cbcr irqs need to be present
- * for frame done interrupt */
-#define VFE_COMP_IRQ_BOTH_Y_CBCR 3
-
-/* bit 1 = 1, only cbcr irq triggers frame done interrupt */
-#define VFE_COMP_IRQ_CBCR_ONLY 2
-
-/* bit 0 = 1, only y irq triggers frame done interrupt */
-#define VFE_COMP_IRQ_Y_ONLY 1
-
-/* bit 0 = 1, PM go; bit1 = 1, PM stop */
-#define VFE_PERFORMANCE_MONITOR_GO 0x00000001
-#define VFE_PERFORMANCE_MONITOR_STOP 0x00000002
-
-/* bit 0 = 1, test gen go; bit1 = 1, test gen stop */
-#define VFE_TEST_GEN_GO 0x00000001
-#define VFE_TEST_GEN_STOP 0x00000002
-
-/* the chroma is assumed to be interpolated between
- * the luma samples. JPEG 4:2:2 */
-#define VFE_CHROMA_UPSAMPLE_INTERPOLATED 0
-
-/* constants for irq registers */
-#define VFE_DISABLE_ALL_IRQS 0
-/* bit =1 is to clear the corresponding bit in VFE_IRQ_STATUS. */
-#define VFE_CLEAR_ALL_IRQS 0xffffffff
-/* imask for while waiting for stop ack, driver has already
- * requested stop, waiting for reset irq,
- * bit 29,28,27,26 for async timer, bit 9 for reset */
-#define VFE_IMASK_WHILE_STOPPING 0x3c000200
-
-/* when normal case, don't want to block error status.
- * bit 0,6,20,21,22,30,31 */
-#define VFE_IMASK_ERROR_ONLY 0xC0700041
-#define VFE_REG_UPDATE_TRIGGER 1
-#define VFE_PM_BUF_MAX_CNT_MASK 0xFF
-#define VFE_DMI_CFG_DEFAULT 0x00000100
-#define LENS_ROLL_OFF_DELTA_TABLE_OFFSET 32
-#define VFE_AF_PINGPONG_STATUS_BIT 0x100
-#define VFE_AWB_PINGPONG_STATUS_BIT 0x200
-
-/* VFE I/O registers */
-enum {
- VFE_HW_VERSION = 0x00000000,
- VFE_GLOBAL_RESET_CMD = 0x00000004,
- VFE_MODULE_RESET = 0x00000008,
- VFE_CGC_OVERRIDE = 0x0000000C,
- VFE_MODULE_CFG = 0x00000010,
- VFE_CFG = 0x00000014,
- VFE_IRQ_MASK = 0x00000018,
- VFE_IRQ_CLEAR = 0x0000001C,
-VFE_IRQ_STATUS = 0x00000020,
-VFE_IRQ_COMPOSITE_MASK = 0x00000024,
-VFE_BUS_CMD = 0x00000028,
-VFE_BUS_CFG = 0x0000002C,
-VFE_BUS_ENC_Y_WR_PING_ADDR = 0x00000030,
-VFE_BUS_ENC_Y_WR_PONG_ADDR = 0x00000034,
-VFE_BUS_ENC_Y_WR_IMAGE_SIZE = 0x00000038,
-VFE_BUS_ENC_Y_WR_BUFFER_CFG = 0x0000003C,
-VFE_BUS_ENC_CBCR_WR_PING_ADDR = 0x00000040,
-VFE_BUS_ENC_CBCR_WR_PONG_ADDR = 0x00000044,
-VFE_BUS_ENC_CBCR_WR_IMAGE_SIZE = 0x00000048,
-VFE_BUS_ENC_CBCR_WR_BUFFER_CFG = 0x0000004C,
-VFE_BUS_VIEW_Y_WR_PING_ADDR = 0x00000050,
-VFE_BUS_VIEW_Y_WR_PONG_ADDR = 0x00000054,
-VFE_BUS_VIEW_Y_WR_IMAGE_SIZE = 0x00000058,
-VFE_BUS_VIEW_Y_WR_BUFFER_CFG = 0x0000005C,
-VFE_BUS_VIEW_CBCR_WR_PING_ADDR = 0x00000060,
-VFE_BUS_VIEW_CBCR_WR_PONG_ADDR = 0x00000064,
-VFE_BUS_VIEW_CBCR_WR_IMAGE_SIZE = 0x00000068,
-VFE_BUS_VIEW_CBCR_WR_BUFFER_CFG = 0x0000006C,
-VFE_BUS_STATS_AF_WR_PING_ADDR = 0x00000070,
-VFE_BUS_STATS_AF_WR_PONG_ADDR = 0x00000074,
-VFE_BUS_STATS_AWB_WR_PING_ADDR = 0x00000078,
-VFE_BUS_STATS_AWB_WR_PONG_ADDR = 0x0000007C,
-VFE_BUS_STATS_HIST_WR_PING_ADDR = 0x00000080,
-VFE_BUS_STATS_HIST_WR_PONG_ADDR = 0x00000084,
-VFE_BUS_STATS_WR_PRIORITY = 0x00000088,
-VFE_BUS_STRIPE_RD_ADDR_0 = 0x0000008C,
-VFE_BUS_STRIPE_RD_ADDR_1 = 0x00000090,
-VFE_BUS_STRIPE_RD_ADDR_2 = 0x00000094,
-VFE_BUS_STRIPE_RD_ADDR_3 = 0x00000098,
-VFE_BUS_STRIPE_RD_VSIZE = 0x0000009C,
-VFE_BUS_STRIPE_RD_HSIZE = 0x000000A0,
-VFE_BUS_STRIPE_RD_BUFFER_CFG = 0x000000A4,
-VFE_BUS_STRIPE_RD_UNPACK_CFG = 0x000000A8,
-VFE_BUS_STRIPE_RD_UNPACK = 0x000000AC,
-VFE_BUS_STRIPE_RD_PAD_SIZE = 0x000000B0,
-VFE_BUS_STRIPE_RD_PAD_L_UNPACK = 0x000000B4,
-VFE_BUS_STRIPE_RD_PAD_R_UNPACK = 0x000000B8,
-VFE_BUS_STRIPE_RD_PAD_TB_UNPACK = 0x000000BC,
-VFE_BUS_PINGPONG_IRQ_EN = 0x000000C0,
-VFE_BUS_PINGPONG_STATUS = 0x000000C4,
-VFE_BUS_PM_CMD = 0x000000C8,
-VFE_BUS_PM_CFG = 0x000000CC,
-VFE_BUS_ENC_Y_WR_PM_STATS_0 = 0x000000D0,
-VFE_BUS_ENC_Y_WR_PM_STATS_1 = 0x000000D4,
-VFE_BUS_ENC_CBCR_WR_PM_STATS_0 = 0x000000D8,
-VFE_BUS_ENC_CBCR_WR_PM_STATS_1 = 0x000000DC,
-VFE_BUS_VIEW_Y_WR_PM_STATS_0 = 0x000000E0,
-VFE_BUS_VIEW_Y_WR_PM_STATS_1 = 0x000000E4,
-VFE_BUS_VIEW_CBCR_WR_PM_STATS_0 = 0x000000E8,
-VFE_BUS_VIEW_CBCR_WR_PM_STATS_1 = 0x000000EC,
-VFE_BUS_MISR_CFG = 0x000000F4,
-VFE_BUS_MISR_MAST_CFG_0 = 0x000000F8,
-VFE_BUS_MISR_MAST_CFG_1 = 0x000000FC,
-VFE_BUS_MISR_RD_VAL = 0x00000100,
-VFE_AXI_CMD = 0x00000104,
-VFE_AXI_CFG = 0x00000108,
-VFE_AXI_STATUS = 0x0000010C,
-CAMIF_COMMAND = 0x00000110,
-CAMIF_CONFIG = 0x00000114,
-CAMIF_EFS_CONFIG = 0x00000118,
-CAMIF_FRAME_CONFIG = 0x0000011C,
-CAMIF_WINDOW_WIDTH_CONFIG = 0x00000120,
-CAMIF_WINDOW_HEIGHT_CONFIG = 0x00000124,
-CAMIF_SUBSAMPLE1_CONFIG = 0x00000128,
-CAMIF_SUBSAMPLE2_CONFIG = 0x0000012C,
-CAMIF_EPOCH_IRQ = 0x00000130,
-CAMIF_STATUS = 0x00000134,
-CAMIF_MISR = 0x00000138,
-VFE_SYNC_TIMER_CMD = 0x0000013C,
-VFE_SYNC_TIMER0_LINE_START = 0x00000140,
-VFE_SYNC_TIMER0_PIXEL_START = 0x00000144,
-VFE_SYNC_TIMER0_PIXEL_DURATION = 0x00000148,
-VFE_SYNC_TIMER1_LINE_START = 0x0000014C,
-VFE_SYNC_TIMER1_PIXEL_START = 0x00000150,
-VFE_SYNC_TIMER1_PIXEL_DURATION = 0x00000154,
-VFE_SYNC_TIMER2_LINE_START = 0x00000158,
-VFE_SYNC_TIMER2_PIXEL_START = 0x0000015C,
-VFE_SYNC_TIMER2_PIXEL_DURATION = 0x00000160,
-VFE_SYNC_TIMER_POLARITY = 0x00000164,
-VFE_ASYNC_TIMER_CMD = 0x00000168,
-VFE_ASYNC_TIMER0_CFG_0 = 0x0000016C,
-VFE_ASYNC_TIMER0_CFG_1 = 0x00000170,
-VFE_ASYNC_TIMER1_CFG_0 = 0x00000174,
-VFE_ASYNC_TIMER1_CFG_1 = 0x00000178,
-VFE_ASYNC_TIMER2_CFG_0 = 0x0000017C,
-VFE_ASYNC_TIMER2_CFG_1 = 0x00000180,
-VFE_ASYNC_TIMER3_CFG_0 = 0x00000184,
-VFE_ASYNC_TIMER3_CFG_1 = 0x00000188,
-VFE_TIMER_SEL = 0x0000018C,
-VFE_REG_UPDATE_CMD = 0x00000190,
-VFE_BLACK_EVEN_EVEN_VALUE = 0x00000194,
-VFE_BLACK_EVEN_ODD_VALUE = 0x00000198,
-VFE_BLACK_ODD_EVEN_VALUE = 0x0000019C,
-VFE_BLACK_ODD_ODD_VALUE = 0x000001A0,
-VFE_ROLLOFF_CFG_0 = 0x000001A4,
-VFE_ROLLOFF_CFG_1 = 0x000001A8,
-VFE_ROLLOFF_CFG_2 = 0x000001AC,
-VFE_DEMUX_CFG = 0x000001B0,
-VFE_DEMUX_GAIN_0 = 0x000001B4,
-VFE_DEMUX_GAIN_1 = 0x000001B8,
-VFE_DEMUX_EVEN_CFG = 0x000001BC,
-VFE_DEMUX_ODD_CFG = 0x000001C0,
-VFE_DEMOSAIC_CFG = 0x000001C4,
-VFE_DEMOSAIC_ABF_CFG_0 = 0x000001C8,
-VFE_DEMOSAIC_ABF_CFG_1 = 0x000001CC,
-VFE_DEMOSAIC_BPC_CFG_0 = 0x000001D0,
-VFE_DEMOSAIC_BPC_CFG_1 = 0x000001D4,
-VFE_DEMOSAIC_STATUS = 0x000001D8,
-VFE_CHROMA_UPSAMPLE_CFG = 0x000001DC,
-VFE_CROP_WIDTH_CFG = 0x000001E0,
-VFE_CROP_HEIGHT_CFG = 0x000001E4,
-VFE_COLOR_CORRECT_COEFF_0 = 0x000001E8,
-VFE_COLOR_CORRECT_COEFF_1 = 0x000001EC,
-VFE_COLOR_CORRECT_COEFF_2 = 0x000001F0,
-VFE_COLOR_CORRECT_COEFF_3 = 0x000001F4,
-VFE_COLOR_CORRECT_COEFF_4 = 0x000001F8,
-VFE_COLOR_CORRECT_COEFF_5 = 0x000001FC,
-VFE_COLOR_CORRECT_COEFF_6 = 0x00000200,
-VFE_COLOR_CORRECT_COEFF_7 = 0x00000204,
-VFE_COLOR_CORRECT_COEFF_8 = 0x00000208,
-VFE_COLOR_CORRECT_OFFSET_0 = 0x0000020C,
-VFE_COLOR_CORRECT_OFFSET_1 = 0x00000210,
-VFE_COLOR_CORRECT_OFFSET_2 = 0x00000214,
-VFE_COLOR_CORRECT_COEFF_Q = 0x00000218,
-VFE_LA_CFG = 0x0000021C,
-VFE_LUT_BANK_SEL = 0x00000220,
-VFE_CHROMA_ENHAN_A = 0x00000224,
-VFE_CHROMA_ENHAN_B = 0x00000228,
-VFE_CHROMA_ENHAN_C = 0x0000022C,
-VFE_CHROMA_ENHAN_D = 0x00000230,
-VFE_CHROMA_ENHAN_K = 0x00000234,
-VFE_COLOR_CONVERT_COEFF_0 = 0x00000238,
-VFE_COLOR_CONVERT_COEFF_1 = 0x0000023C,
-VFE_COLOR_CONVERT_COEFF_2 = 0x00000240,
-VFE_COLOR_CONVERT_OFFSET = 0x00000244,
-VFE_ASF_CFG = 0x00000248,
-VFE_ASF_SHARP_CFG_0 = 0x0000024C,
-VFE_ASF_SHARP_CFG_1 = 0x00000250,
-VFE_ASF_SHARP_COEFF_0 = 0x00000254,
-VFE_ASF_SHARP_COEFF_1 = 0x00000258,
-VFE_ASF_SHARP_COEFF_2 = 0x0000025C,
-VFE_ASF_SHARP_COEFF_3 = 0x00000260,
-VFE_ASF_MAX_EDGE = 0x00000264,
-VFE_ASF_CROP_WIDTH_CFG = 0x00000268,
-VFE_ASF_CROP_HEIGHT_CFG = 0x0000026C,
-VFE_SCALE_CFG = 0x00000270,
-VFE_SCALE_H_IMAGE_SIZE_CFG = 0x00000274,
-VFE_SCALE_H_PHASE_CFG = 0x00000278,
-VFE_SCALE_H_STRIPE_CFG = 0x0000027C,
-VFE_SCALE_V_IMAGE_SIZE_CFG = 0x00000280,
-VFE_SCALE_V_PHASE_CFG = 0x00000284,
-VFE_SCALE_V_STRIPE_CFG = 0x00000288,
-VFE_SCALE_Y_CFG = 0x0000028C,
-VFE_SCALE_Y_H_IMAGE_SIZE_CFG = 0x00000290,
-VFE_SCALE_Y_H_PHASE_CFG = 0x00000294,
-VFE_SCALE_Y_V_IMAGE_SIZE_CFG = 0x00000298,
-VFE_SCALE_Y_V_PHASE_CFG = 0x0000029C,
-VFE_SCALE_CBCR_CFG = 0x000002A0,
-VFE_SCALE_CBCR_H_IMAGE_SIZE_CFG = 0x000002A4,
-VFE_SCALE_CBCR_H_PHASE_CFG = 0x000002A8,
-VFE_SCALE_CBCR_V_IMAGE_SIZE_CFG = 0x000002AC,
-VFE_SCALE_CBCR_V_PHASE_CFG = 0x000002B0,
-VFE_WB_CFG = 0x000002B4,
-VFE_CHROMA_SUPPRESS_CFG_0 = 0x000002B8,
-VFE_CHROMA_SUPPRESS_CFG_1 = 0x000002BC,
-VFE_CHROMA_SUBSAMPLE_CFG = 0x000002C0,
-VFE_CHROMA_SUB_CROP_WIDTH_CFG = 0x000002C4,
-VFE_CHROMA_SUB_CROP_HEIGHT_CFG = 0x000002C8,
-VFE_FRAMEDROP_ENC_Y_CFG = 0x000002CC,
-VFE_FRAMEDROP_ENC_CBCR_CFG = 0x000002D0,
-VFE_FRAMEDROP_ENC_Y_PATTERN = 0x000002D4,
-VFE_FRAMEDROP_ENC_CBCR_PATTERN = 0x000002D8,
-VFE_FRAMEDROP_VIEW_Y_CFG = 0x000002DC,
-VFE_FRAMEDROP_VIEW_CBCR_CFG = 0x000002E0,
-VFE_FRAMEDROP_VIEW_Y_PATTERN = 0x000002E4,
-VFE_FRAMEDROP_VIEW_CBCR_PATTERN = 0x000002E8,
-VFE_CLAMP_MAX_CFG = 0x000002EC,
-VFE_CLAMP_MIN_CFG = 0x000002F0,
-VFE_STATS_CMD = 0x000002F4,
-VFE_STATS_AF_CFG = 0x000002F8,
-VFE_STATS_AF_DIM = 0x000002FC,
-VFE_STATS_AF_GRID_0 = 0x00000300,
-VFE_STATS_AF_GRID_1 = 0x00000304,
-VFE_STATS_AF_GRID_2 = 0x00000308,
-VFE_STATS_AF_GRID_3 = 0x0000030C,
-VFE_STATS_AF_HEADER = 0x00000310,
-VFE_STATS_AF_COEF0 = 0x00000314,
-VFE_STATS_AF_COEF1 = 0x00000318,
-VFE_STATS_AWBAE_CFG = 0x0000031C,
-VFE_STATS_AXW_HEADER = 0x00000320,
-VFE_STATS_AWB_MCFG = 0x00000324,
-VFE_STATS_AWB_CCFG1 = 0x00000328,
-VFE_STATS_AWB_CCFG2 = 0x0000032C,
-VFE_STATS_HIST_HEADER = 0x00000330,
-VFE_STATS_HIST_INNER_OFFSET = 0x00000334,
-VFE_STATS_HIST_INNER_DIM = 0x00000338,
-VFE_STATS_FRAME_SIZE = 0x0000033C,
-VFE_DMI_CFG = 0x00000340,
-VFE_DMI_ADDR = 0x00000344,
-VFE_DMI_DATA_HI = 0x00000348,
-VFE_DMI_DATA_LO = 0x0000034C,
-VFE_DMI_RAM_AUTO_LOAD_CMD = 0x00000350,
-VFE_DMI_RAM_AUTO_LOAD_STATUS = 0x00000354,
-VFE_DMI_RAM_AUTO_LOAD_CFG = 0x00000358,
-VFE_DMI_RAM_AUTO_LOAD_SEED = 0x0000035C,
-VFE_TESTBUS_SEL = 0x00000360,
-VFE_TESTGEN_CFG = 0x00000364,
-VFE_SW_TESTGEN_CMD = 0x00000368,
-VFE_HW_TESTGEN_CMD = 0x0000036C,
-VFE_HW_TESTGEN_CFG = 0x00000370,
-VFE_HW_TESTGEN_IMAGE_CFG = 0x00000374,
-VFE_HW_TESTGEN_SOF_OFFSET_CFG = 0x00000378,
-VFE_HW_TESTGEN_EOF_NOFFSET_CFG = 0x0000037C,
-VFE_HW_TESTGEN_SOL_OFFSET_CFG = 0x00000380,
-VFE_HW_TESTGEN_EOL_NOFFSET_CFG = 0x00000384,
-VFE_HW_TESTGEN_HBI_CFG = 0x00000388,
-VFE_HW_TESTGEN_VBL_CFG = 0x0000038C,
-VFE_HW_TESTGEN_SOF_DUMMY_LINE_CFG2 = 0x00000390,
-VFE_HW_TESTGEN_EOF_DUMMY_LINE_CFG2 = 0x00000394,
-VFE_HW_TESTGEN_COLOR_BARS_CFG = 0x00000398,
-VFE_HW_TESTGEN_RANDOM_CFG = 0x0000039C,
-VFE_SPARE = 0x000003A0,
-};
-
-#define ping 0x0
-#define pong 0x1
-
-struct vfe_bus_cfg_data {
- boolean stripeRdPathEn;
- boolean encYWrPathEn;
- boolean encCbcrWrPathEn;
- boolean viewYWrPathEn;
- boolean viewCbcrWrPathEn;
- enum VFE_RAW_PIXEL_DATA_SIZE rawPixelDataSize;
- enum VFE_RAW_WR_PATH_SEL rawWritePathSelect;
-};
-
-struct vfe_camif_cfg_data {
- boolean camif2OutputEnable;
- boolean camif2BusEnable;
- struct vfe_cmds_camif_cfg camifCfgFromCmd;
-};
-
-struct vfe_irq_composite_mask_config {
- uint8_t encIrqComMask;
- uint8_t viewIrqComMask;
- uint8_t ceDoneSel;
-};
-
-/* define a structure for each output path.*/
-struct vfe_output_path {
- uint32_t addressBuffer[8];
- uint16_t fragIndex;
- boolean hwCurrentFlag;
- uint8_t *hwRegPingAddress;
- uint8_t *hwRegPongAddress;
-};
-
-struct vfe_output_path_combo {
- boolean whichOutputPath;
- boolean pathEnabled;
- boolean multiFrag;
- uint8_t fragCount;
- boolean ackPending;
- uint8_t currentFrame;
- uint32_t nextFrameAddrBuf[8];
- struct vfe_output_path yPath;
- struct vfe_output_path cbcrPath;
- uint8_t snapshotPendingCount;
- boolean pmEnabled;
- uint8_t cbcrStatusBit;
-};
-
-struct vfe_stats_control {
- boolean ackPending;
- uint32_t addressBuffer[2];
- uint32_t nextFrameAddrBuf;
- boolean pingPongStatus;
- uint8_t *hwRegPingAddress;
- uint8_t *hwRegPongAddress;
- uint32_t droppedStatsFrameCount;
- uint32_t bufToRender;
-};
-
-struct vfe_gamma_lut_sel {
- boolean ch0BankSelect;
- boolean ch1BankSelect;
- boolean ch2BankSelect;
-};
-
-struct vfe_interrupt_mask {
- boolean camifErrorIrq;
- boolean camifSofIrq;
- boolean camifEolIrq;
- boolean camifEofIrq;
- boolean camifEpoch1Irq;
- boolean camifEpoch2Irq;
- boolean camifOverflowIrq;
- boolean ceIrq;
- boolean regUpdateIrq;
- boolean resetAckIrq;
- boolean encYPingpongIrq;
- boolean encCbcrPingpongIrq;
- boolean viewYPingpongIrq;
- boolean viewCbcrPingpongIrq;
- boolean rdPingpongIrq;
- boolean afPingpongIrq;
- boolean awbPingpongIrq;
- boolean histPingpongIrq;
- boolean encIrq;
- boolean viewIrq;
- boolean busOverflowIrq;
- boolean afOverflowIrq;
- boolean awbOverflowIrq;
- boolean syncTimer0Irq;
- boolean syncTimer1Irq;
- boolean syncTimer2Irq;
- boolean asyncTimer0Irq;
- boolean asyncTimer1Irq;
- boolean asyncTimer2Irq;
- boolean asyncTimer3Irq;
- boolean axiErrorIrq;
- boolean violationIrq;
-};
-
-enum vfe_interrupt_name {
- CAMIF_ERROR_IRQ,
- CAMIF_SOF_IRQ,
- CAMIF_EOL_IRQ,
- CAMIF_EOF_IRQ,
- CAMIF_EPOCH1_IRQ,
- CAMIF_EPOCH2_IRQ,
- CAMIF_OVERFLOW_IRQ,
- CE_IRQ,
- REG_UPDATE_IRQ,
- RESET_ACK_IRQ,
- ENC_Y_PINGPONG_IRQ,
- ENC_CBCR_PINGPONG_IRQ,
- VIEW_Y_PINGPONG_IRQ,
- VIEW_CBCR_PINGPONG_IRQ,
- RD_PINGPONG_IRQ,
- AF_PINGPONG_IRQ,
- AWB_PINGPONG_IRQ,
- HIST_PINGPONG_IRQ,
- ENC_IRQ,
- VIEW_IRQ,
- BUS_OVERFLOW_IRQ,
- AF_OVERFLOW_IRQ,
- AWB_OVERFLOW_IRQ,
- SYNC_TIMER0_IRQ,
- SYNC_TIMER1_IRQ,
- SYNC_TIMER2_IRQ,
- ASYNC_TIMER0_IRQ,
- ASYNC_TIMER1_IRQ,
- ASYNC_TIMER2_IRQ,
- ASYNC_TIMER3_IRQ,
- AXI_ERROR_IRQ,
- VIOLATION_IRQ
-};
-
-enum VFE_DMI_RAM_SEL {
- NO_MEM_SELECTED = 0,
- ROLLOFF_RAM = 0x1,
- RGBLUT_RAM_CH0_BANK0 = 0x2,
- RGBLUT_RAM_CH0_BANK1 = 0x3,
- RGBLUT_RAM_CH1_BANK0 = 0x4,
- RGBLUT_RAM_CH1_BANK1 = 0x5,
- RGBLUT_RAM_CH2_BANK0 = 0x6,
- RGBLUT_RAM_CH2_BANK1 = 0x7,
- STATS_HIST_CB_EVEN_RAM = 0x8,
- STATS_HIST_CB_ODD_RAM = 0x9,
- STATS_HIST_CR_EVEN_RAM = 0xa,
- STATS_HIST_CR_ODD_RAM = 0xb,
- RGBLUT_CHX_BANK0 = 0xc,
- RGBLUT_CHX_BANK1 = 0xd,
- LUMA_ADAPT_LUT_RAM_BANK0 = 0xe,
- LUMA_ADAPT_LUT_RAM_BANK1 = 0xf
-};
-
-struct vfe_module_enable {
- boolean blackLevelCorrectionEnable;
- boolean lensRollOffEnable;
- boolean demuxEnable;
- boolean chromaUpsampleEnable;
- boolean demosaicEnable;
- boolean statsEnable;
- boolean cropEnable;
- boolean mainScalerEnable;
- boolean whiteBalanceEnable;
- boolean colorCorrectionEnable;
- boolean yHistEnable;
- boolean skinToneEnable;
- boolean lumaAdaptationEnable;
- boolean rgbLUTEnable;
- boolean chromaEnhanEnable;
- boolean asfEnable;
- boolean chromaSuppressionEnable;
- boolean chromaSubsampleEnable;
- boolean scaler2YEnable;
- boolean scaler2CbcrEnable;
-};
-
-struct vfe_bus_cmd_data {
- boolean stripeReload;
- boolean busPingpongReload;
- boolean statsPingpongReload;
-};
-
-struct vfe_stats_cmd_data {
- boolean autoFocusEnable;
- boolean axwEnable;
- boolean histEnable;
- boolean clearHistEnable;
- boolean histAutoClearEnable;
- boolean colorConversionEnable;
-};
-
-struct vfe_hw_ver {
- uint32_t minorVersion:8;
- uint32_t majorVersion:8;
- uint32_t coreVersion:4;
- uint32_t /* reserved */ : 12;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_cfg {
- uint32_t pixelPattern:3;
- uint32_t /* reserved */ : 13;
- uint32_t inputSource:2;
- uint32_t /* reserved */ : 14;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_buscmd {
- uint32_t stripeReload:1;
- uint32_t /* reserved */ : 3;
- uint32_t busPingpongReload:1;
- uint32_t statsPingpongReload:1;
- uint32_t /* reserved */ : 26;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_Irq_Composite_MaskType {
- uint32_t encIrqComMaskBits:2;
- uint32_t viewIrqComMaskBits:2;
- uint32_t ceDoneSelBits:5;
- uint32_t /* reserved */ : 23;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_mod_enable {
- uint32_t blackLevelCorrectionEnable:1;
- uint32_t lensRollOffEnable:1;
- uint32_t demuxEnable:1;
- uint32_t chromaUpsampleEnable:1;
- uint32_t demosaicEnable:1;
- uint32_t statsEnable:1;
- uint32_t cropEnable:1;
- uint32_t mainScalerEnable:1;
- uint32_t whiteBalanceEnable:1;
- uint32_t colorCorrectionEnable:1;
- uint32_t yHistEnable:1;
- uint32_t skinToneEnable:1;
- uint32_t lumaAdaptationEnable:1;
- uint32_t rgbLUTEnable:1;
- uint32_t chromaEnhanEnable:1;
- uint32_t asfEnable:1;
- uint32_t chromaSuppressionEnable:1;
- uint32_t chromaSubsampleEnable:1;
- uint32_t scaler2YEnable:1;
- uint32_t scaler2CbcrEnable:1;
- uint32_t /* reserved */ : 14;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_irqenable {
- uint32_t camifErrorIrq:1;
- uint32_t camifSofIrq:1;
- uint32_t camifEolIrq:1;
- uint32_t camifEofIrq:1;
- uint32_t camifEpoch1Irq:1;
- uint32_t camifEpoch2Irq:1;
- uint32_t camifOverflowIrq:1;
- uint32_t ceIrq:1;
- uint32_t regUpdateIrq:1;
- uint32_t resetAckIrq:1;
- uint32_t encYPingpongIrq:1;
- uint32_t encCbcrPingpongIrq:1;
- uint32_t viewYPingpongIrq:1;
- uint32_t viewCbcrPingpongIrq:1;
- uint32_t rdPingpongIrq:1;
- uint32_t afPingpongIrq:1;
- uint32_t awbPingpongIrq:1;
- uint32_t histPingpongIrq:1;
- uint32_t encIrq:1;
- uint32_t viewIrq:1;
- uint32_t busOverflowIrq:1;
- uint32_t afOverflowIrq:1;
- uint32_t awbOverflowIrq:1;
- uint32_t syncTimer0Irq:1;
- uint32_t syncTimer1Irq:1;
- uint32_t syncTimer2Irq:1;
- uint32_t asyncTimer0Irq:1;
- uint32_t asyncTimer1Irq:1;
- uint32_t asyncTimer2Irq:1;
- uint32_t asyncTimer3Irq:1;
- uint32_t axiErrorIrq:1;
- uint32_t violationIrq:1;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_upsample_cfg {
- uint32_t chromaCositingForYCbCrInputs:1;
- uint32_t /* reserved */ : 31;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_CAMIFConfigType {
- /* CAMIF Config */
- uint32_t /* reserved */ : 1;
- uint32_t VSyncEdge:1;
- uint32_t HSyncEdge:1;
- uint32_t syncMode:2;
- uint32_t vfeSubsampleEnable:1;
- uint32_t /* reserved */ : 1;
- uint32_t busSubsampleEnable:1;
- uint32_t camif2vfeEnable:1;
- uint32_t /* reserved */ : 1;
- uint32_t camif2busEnable:1;
- uint32_t irqSubsampleEnable:1;
- uint32_t binningEnable:1;
- uint32_t /* reserved */ : 18;
- uint32_t misrEnable:1;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_camifcfg {
- /* EFS_Config */
- uint32_t efsEndOfLine:8;
- uint32_t efsStartOfLine:8;
- uint32_t efsEndOfFrame:8;
- uint32_t efsStartOfFrame:8;
- /* Frame Config */
- uint32_t frameConfigPixelsPerLine:14;
- uint32_t /* reserved */ : 2;
- uint32_t frameConfigLinesPerFrame:14;
- uint32_t /* reserved */ : 2;
- /* Window Width Config */
- uint32_t windowWidthCfgLastPixel:14;
- uint32_t /* reserved */ : 2;
- uint32_t windowWidthCfgFirstPixel:14;
- uint32_t /* reserved */ : 2;
- /* Window Height Config */
- uint32_t windowHeightCfglastLine:14;
- uint32_t /* reserved */ : 2;
- uint32_t windowHeightCfgfirstLine:14;
- uint32_t /* reserved */ : 2;
- /* Subsample 1 Config */
- uint32_t subsample1CfgPixelSkip:16;
- uint32_t subsample1CfgLineSkip:16;
- /* Subsample 2 Config */
- uint32_t subsample2CfgFrameSkip:4;
- uint32_t subsample2CfgFrameSkipMode:1;
- uint32_t subsample2CfgPixelSkipWrap:1;
- uint32_t /* reserved */ : 26;
- /* Epoch Interrupt */
- uint32_t epoch1Line:14;
- uint32_t /* reserved */ : 2;
- uint32_t epoch2Line:14;
- uint32_t /* reserved */ : 2;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_camifframe_update {
- uint32_t pixelsPerLine:14;
- uint32_t /* reserved */ : 2;
- uint32_t linesPerFrame:14;
- uint32_t /* reserved */ : 2;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_axi_bus_cfg {
- uint32_t stripeRdPathEn:1;
- uint32_t /* reserved */ : 3;
- uint32_t encYWrPathEn:1;
- uint32_t encCbcrWrPathEn:1;
- uint32_t viewYWrPathEn:1;
- uint32_t viewCbcrWrPathEn:1;
- uint32_t rawPixelDataSize:2;
- uint32_t rawWritePathSelect:2;
- uint32_t /* reserved */ : 20;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_axi_out_cfg {
- uint32_t out2YPingAddr:32;
- uint32_t out2YPongAddr:32;
- uint32_t out2YImageHeight:12;
- uint32_t /* reserved */ : 4;
- uint32_t out2YImageWidthin64bit:10;
- uint32_t /* reserved */ : 6;
- uint32_t out2YBurstLength:2;
- uint32_t /* reserved */ : 2;
- uint32_t out2YNumRows:12;
- uint32_t out2YRowIncrementIn64bit:12;
- uint32_t /* reserved */ : 4;
- uint32_t out2CbcrPingAddr:32;
- uint32_t out2CbcrPongAddr:32;
- uint32_t out2CbcrImageHeight:12;
- uint32_t /* reserved */ : 4;
- uint32_t out2CbcrImageWidthIn64bit:10;
- uint32_t /* reserved */ : 6;
- uint32_t out2CbcrBurstLength:2;
- uint32_t /* reserved */ : 2;
- uint32_t out2CbcrNumRows:12;
- uint32_t out2CbcrRowIncrementIn64bit:12;
- uint32_t /* reserved */ : 4;
- uint32_t out1YPingAddr:32;
- uint32_t out1YPongAddr:32;
- uint32_t out1YImageHeight:12;
- uint32_t /* reserved */ : 4;
- uint32_t out1YImageWidthin64bit:10;
- uint32_t /* reserved */ : 6;
- uint32_t out1YBurstLength:2;
- uint32_t /* reserved */ : 2;
- uint32_t out1YNumRows:12;
- uint32_t out1YRowIncrementIn64bit:12;
- uint32_t /* reserved */ : 4;
- uint32_t out1CbcrPingAddr:32;
- uint32_t out1CbcrPongAddr:32;
- uint32_t out1CbcrImageHeight:12;
- uint32_t /* reserved */ : 4;
- uint32_t out1CbcrImageWidthIn64bit:10;
- uint32_t /* reserved */ : 6;
- uint32_t out1CbcrBurstLength:2;
- uint32_t /* reserved */ : 2;
- uint32_t out1CbcrNumRows:12;
- uint32_t out1CbcrRowIncrementIn64bit:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_output_clamp_cfg {
- /* Output Clamp Maximums */
- uint32_t yChanMax:8;
- uint32_t cbChanMax:8;
- uint32_t crChanMax:8;
- uint32_t /* reserved */ : 8;
- /* Output Clamp Minimums */
- uint32_t yChanMin:8;
- uint32_t cbChanMin:8;
- uint32_t crChanMin:8;
- uint32_t /* reserved */ : 8;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_fov_crop_cfg {
- uint32_t lastPixel:12;
- uint32_t /* reserved */ : 4;
- uint32_t firstPixel:12;
- uint32_t /* reserved */ : 4;
-
- /* FOV Corp, Part 2 */
- uint32_t lastLine:12;
- uint32_t /* reserved */ : 4;
- uint32_t firstLine:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_FRAME_SKIP_UpdateCmdType {
- uint32_t yPattern:32;
- uint32_t cbcrPattern:32;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_frame_skip_cfg {
- /* Frame Drop Enc (output2) */
- uint32_t output2YPeriod:5;
- uint32_t /* reserved */ : 27;
- uint32_t output2CbCrPeriod:5;
- uint32_t /* reserved */ : 27;
- uint32_t output2YPattern:32;
- uint32_t output2CbCrPattern:32;
- /* Frame Drop View (output1) */
- uint32_t output1YPeriod:5;
- uint32_t /* reserved */ : 27;
- uint32_t output1CbCrPeriod:5;
- uint32_t /* reserved */ : 27;
- uint32_t output1YPattern:32;
- uint32_t output1CbCrPattern:32;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_main_scaler_cfg {
- /* Scaler Enable Config */
- uint32_t hEnable:1;
- uint32_t vEnable:1;
- uint32_t /* reserved */ : 30;
- /* Scale H Image Size Config */
- uint32_t inWidth:12;
- uint32_t /* reserved */ : 4;
- uint32_t outWidth:12;
- uint32_t /* reserved */ : 4;
- /* Scale H Phase Config */
- uint32_t horizPhaseMult:18;
- uint32_t /* reserved */ : 2;
- uint32_t horizInterResolution:2;
- uint32_t /* reserved */ : 10;
- /* Scale H Stripe Config */
- uint32_t horizMNInit:12;
- uint32_t /* reserved */ : 4;
- uint32_t horizPhaseInit:15;
- uint32_t /* reserved */ : 1;
- /* Scale V Image Size Config */
- uint32_t inHeight:12;
- uint32_t /* reserved */ : 4;
- uint32_t outHeight:12;
- uint32_t /* reserved */ : 4;
- /* Scale V Phase Config */
- uint32_t vertPhaseMult:18;
- uint32_t /* reserved */ : 2;
- uint32_t vertInterResolution:2;
- uint32_t /* reserved */ : 10;
- /* Scale V Stripe Config */
- uint32_t vertMNInit:12;
- uint32_t /* reserved */ : 4;
- uint32_t vertPhaseInit:15;
- uint32_t /* reserved */ : 1;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_scaler2_cfg {
- /* Scaler Enable Config */
- uint32_t hEnable:1;
- uint32_t vEnable:1;
- uint32_t /* reserved */ : 30;
- /* Scaler H Image Size Config */
- uint32_t inWidth:12;
- uint32_t /* reserved */ : 4;
- uint32_t outWidth:12;
- uint32_t /* reserved */ : 4;
- /* Scaler H Phase Config */
- uint32_t horizPhaseMult:18;
- uint32_t /* reserved */ : 2;
- uint32_t horizInterResolution:2;
- uint32_t /* reserved */ : 10;
- /* Scaler V Image Size Config */
- uint32_t inHeight:12;
- uint32_t /* reserved */ : 4;
- uint32_t outHeight:12;
- uint32_t /* reserved */ : 4;
- /* Scaler V Phase Config */
- uint32_t vertPhaseMult:18;
- uint32_t /* reserved */ : 2;
- uint32_t vertInterResolution:2;
- uint32_t /* reserved */ : 10;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_rolloff_cfg {
- /* Rolloff 0 Config */
- uint32_t gridWidth:9;
- uint32_t gridHeight:9;
- uint32_t yDelta:9;
- uint32_t /* reserved */ : 5;
- /* Rolloff 1 Config*/
- uint32_t gridX:4;
- uint32_t gridY:4;
- uint32_t pixelX:9;
- uint32_t /* reserved */ : 3;
- uint32_t pixelY:9;
- uint32_t /* reserved */ : 3;
- /* Rolloff 2 Config */
- uint32_t yDeltaAccum:12;
- uint32_t /* reserved */ : 20;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_asf_update {
- /* ASF Config Command */
- uint32_t smoothEnable:1;
- uint32_t sharpMode:2;
- uint32_t /* reserved */ : 1;
- uint32_t smoothCoeff1:4;
- uint32_t smoothCoeff0:8;
- uint32_t pipeFlushCount:12;
- uint32_t pipeFlushOvd:1;
- uint32_t flushHaltOvd:1;
- uint32_t cropEnable:1;
- uint32_t /* reserved */ : 1;
- /* Sharpening Config 0 */
- uint32_t sharpThresholdE1:7;
- uint32_t /* reserved */ : 1;
- uint32_t sharpDegreeK1:5;
- uint32_t /* reserved */ : 3;
- uint32_t sharpDegreeK2:5;
- uint32_t /* reserved */ : 3;
- uint32_t normalizeFactor:7;
- uint32_t /* reserved */ : 1;
- /* Sharpening Config 1 */
- uint32_t sharpThresholdE2:8;
- uint32_t sharpThresholdE3:8;
- uint32_t sharpThresholdE4:8;
- uint32_t sharpThresholdE5:8;
- /* Sharpening Coefficients 0 */
- uint32_t F1Coeff0:6;
- uint32_t F1Coeff1:6;
- uint32_t F1Coeff2:6;
- uint32_t F1Coeff3:6;
- uint32_t F1Coeff4:6;
- uint32_t /* reserved */ : 2;
- /* Sharpening Coefficients 1 */
- uint32_t F1Coeff5:6;
- uint32_t F1Coeff6:6;
- uint32_t F1Coeff7:6;
- uint32_t F1Coeff8:7;
- uint32_t /* reserved */ : 7;
- /* Sharpening Coefficients 2 */
- uint32_t F2Coeff0:6;
- uint32_t F2Coeff1:6;
- uint32_t F2Coeff2:6;
- uint32_t F2Coeff3:6;
- uint32_t F2Coeff4:6;
- uint32_t /* reserved */ : 2;
- /* Sharpening Coefficients 3 */
- uint32_t F2Coeff5:6;
- uint32_t F2Coeff6:6;
- uint32_t F2Coeff7:6;
- uint32_t F2Coeff8:7;
- uint32_t /* reserved */ : 7;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_asfcrop_cfg {
- /* ASF Crop Width Config */
- uint32_t lastPixel:12;
- uint32_t /* reserved */ : 4;
- uint32_t firstPixel:12;
- uint32_t /* reserved */ : 4;
- /* ASP Crop Height Config */
- uint32_t lastLine:12;
- uint32_t /* reserved */ : 4;
- uint32_t firstLine:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_chroma_suppress_cfg {
- /* Chroma Suppress 0 Config */
- uint32_t m1:8;
- uint32_t m3:8;
- uint32_t n1:3;
- uint32_t /* reserved */ : 1;
- uint32_t n3:3;
- uint32_t /* reserved */ : 9;
- /* Chroma Suppress 1 Config */
- uint32_t mm1:8;
- uint32_t nn1:3;
- uint32_t /* reserved */ : 21;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_chromasubsample_cfg {
- /* Chroma Subsample Selection */
- uint32_t hCositedPhase:1;
- uint32_t vCositedPhase:1;
- uint32_t hCosited:1;
- uint32_t vCosited:1;
- uint32_t hsubSampleEnable:1;
- uint32_t vsubSampleEnable:1;
- uint32_t cropEnable:1;
- uint32_t /* reserved */ : 25;
- uint32_t cropWidthLastPixel:12;
- uint32_t /* reserved */ : 4;
- uint32_t cropWidthFirstPixel:12;
- uint32_t /* reserved */ : 4;
- uint32_t cropHeightLastLine:12;
- uint32_t /* reserved */ : 4;
- uint32_t cropHeightFirstLine:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_blacklevel_cfg {
- /* Black Even-Even Value Config */
- uint32_t evenEvenAdjustment:9;
- uint32_t /* reserved */ : 23;
- /* Black Even-Odd Value Config */
- uint32_t evenOddAdjustment:9;
- uint32_t /* reserved */ : 23;
- /* Black Odd-Even Value Config */
- uint32_t oddEvenAdjustment:9;
- uint32_t /* reserved */ : 23;
- /* Black Odd-Odd Value Config */
- uint32_t oddOddAdjustment:9;
- uint32_t /* reserved */ : 23;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_demux_cfg {
- /* Demux Gain 0 Config */
- uint32_t ch0EvenGain:10;
- uint32_t /* reserved */ : 6;
- uint32_t ch0OddGain:10;
- uint32_t /* reserved */ : 6;
- /* Demux Gain 1 Config */
- uint32_t ch1Gain:10;
- uint32_t /* reserved */ : 6;
- uint32_t ch2Gain:10;
- uint32_t /* reserved */ : 6;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_bps_info {
- uint32_t greenBadPixelCount:8;
- uint32_t /* reserved */ : 8;
- uint32_t RedBlueBadPixelCount:8;
- uint32_t /* reserved */ : 8;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_demosaic_cfg {
- /* Demosaic Config */
- uint32_t abfEnable:1;
- uint32_t badPixelCorrEnable:1;
- uint32_t forceAbfOn:1;
- uint32_t /* reserved */ : 1;
- uint32_t abfShift:4;
- uint32_t fminThreshold:7;
- uint32_t /* reserved */ : 1;
- uint32_t fmaxThreshold:7;
- uint32_t /* reserved */ : 5;
- uint32_t slopeShift:3;
- uint32_t /* reserved */ : 1;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_demosaic_bpc_cfg {
- /* Demosaic BPC Config 0 */
- uint32_t blueDiffThreshold:12;
- uint32_t redDiffThreshold:12;
- uint32_t /* reserved */ : 8;
- /* Demosaic BPC Config 1 */
- uint32_t greenDiffThreshold:12;
- uint32_t /* reserved */ : 20;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_demosaic_abf_cfg {
- /* Demosaic ABF Config 0 */
- uint32_t lpThreshold:10;
- uint32_t /* reserved */ : 22;
- /* Demosaic ABF Config 1 */
- uint32_t ratio:4;
- uint32_t minValue:10;
- uint32_t /* reserved */ : 2;
- uint32_t maxValue:10;
- uint32_t /* reserved */ : 6;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_color_correction_cfg {
- /* Color Corr. Coefficient 0 Config */
- uint32_t c0:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Coefficient 1 Config */
- uint32_t c1:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Coefficient 2 Config */
- uint32_t c2:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Coefficient 3 Config */
- uint32_t c3:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Coefficient 4 Config */
- uint32_t c4:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Coefficient 5 Config */
- uint32_t c5:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Coefficient 6 Config */
- uint32_t c6:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Coefficient 7 Config */
- uint32_t c7:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Coefficient 8 Config */
- uint32_t c8:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Offset 0 Config */
- uint32_t k0:11;
- uint32_t /* reserved */ : 21;
- /* Color Corr. Offset 1 Config */
- uint32_t k1:11;
- uint32_t /* reserved */ : 21;
- /* Color Corr. Offset 2 Config */
- uint32_t k2:11;
- uint32_t /* reserved */ : 21;
- /* Color Corr. Coefficient Q Config */
- uint32_t coefQFactor:2;
- uint32_t /* reserved */ : 30;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_LumaAdaptation_ConfigCmdType {
- /* LA Config */
- uint32_t lutBankSelect:1;
- uint32_t /* reserved */ : 31;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_wb_cfg {
- /* WB Config */
- uint32_t ch0Gain:9;
- uint32_t ch1Gain:9;
- uint32_t ch2Gain:9;
- uint32_t /* reserved */ : 5;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_GammaLutSelect_ConfigCmdType {
- /* LUT Bank Select Config */
- uint32_t ch0BankSelect:1;
- uint32_t ch1BankSelect:1;
- uint32_t ch2BankSelect:1;
- uint32_t /* reserved */ : 29;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_chroma_enhance_cfg {
- /* Chroma Enhance A Config */
- uint32_t ap:11;
- uint32_t /* reserved */ : 5;
- uint32_t am:11;
- uint32_t /* reserved */ : 5;
- /* Chroma Enhance B Config */
- uint32_t bp:11;
- uint32_t /* reserved */ : 5;
- uint32_t bm:11;
- uint32_t /* reserved */ : 5;
- /* Chroma Enhance C Config */
- uint32_t cp:11;
- uint32_t /* reserved */ : 5;
- uint32_t cm:11;
- uint32_t /* reserved */ : 5;
- /* Chroma Enhance D Config */
- uint32_t dp:11;
- uint32_t /* reserved */ : 5;
- uint32_t dm:11;
- uint32_t /* reserved */ : 5;
- /* Chroma Enhance K Config */
- uint32_t kcb:11;
- uint32_t /* reserved */ : 5;
- uint32_t kcr:11;
- uint32_t /* reserved */ : 5;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_color_convert_cfg {
- /* Conversion Coefficient 0 */
- uint32_t v0:12;
- uint32_t /* reserved */ : 20;
- /* Conversion Coefficient 1 */
- uint32_t v1:12;
- uint32_t /* reserved */ : 20;
- /* Conversion Coefficient 2 */
- uint32_t v2:12;
- uint32_t /* reserved */ : 20;
- /* Conversion Offset */
- uint32_t ConvertOffset:8;
- uint32_t /* reserved */ : 24;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_SyncTimer_ConfigCmdType {
- /* Timer Line Start Config */
- uint32_t timerLineStart:12;
- uint32_t /* reserved */ : 20;
- /* Timer Pixel Start Config */
- uint32_t timerPixelStart:18;
- uint32_t /* reserved */ : 14;
- /* Timer Pixel Duration Config */
- uint32_t timerPixelDuration:28;
- uint32_t /* reserved */ : 4;
- /* Sync Timer Polarity Config */
- uint32_t timer0Polarity:1;
- uint32_t timer1Polarity:1;
- uint32_t timer2Polarity:1;
- uint32_t /* reserved */ : 29;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_AsyncTimer_ConfigCmdType {
- /* Async Timer Config 0 */
- uint32_t inactiveLength:20;
- uint32_t numRepetition:10;
- uint32_t /* reserved */ : 1;
- uint32_t polarity:1;
- /* Async Timer Config 1 */
- uint32_t activeLength:20;
- uint32_t /* reserved */ : 12;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_AWBAEStatistics_ConfigCmdType {
- /* AWB autoexposure Config */
- uint32_t aeRegionConfig:1;
- uint32_t aeSubregionConfig:1;
- uint32_t /* reserved */ : 14;
- uint32_t awbYMin:8;
- uint32_t awbYMax:8;
- /* AXW Header */
- uint32_t axwHeader:8;
- uint32_t /* reserved */ : 24;
- /* AWB Mconfig */
- uint32_t m4:8;
- uint32_t m3:8;
- uint32_t m2:8;
- uint32_t m1:8;
- /* AWB Cconfig */
- uint32_t c2:12;
- uint32_t /* reserved */ : 4;
- uint32_t c1:12;
- uint32_t /* reserved */ : 4;
- /* AWB Cconfig 2 */
- uint32_t c4:12;
- uint32_t /* reserved */ : 4;
- uint32_t c3:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_TestGen_ConfigCmdType {
- /* HW Test Gen Config */
- uint32_t numFrame:10;
- uint32_t /* reserved */ : 2;
- uint32_t pixelDataSelect:1;
- uint32_t systematicDataSelect:1;
- uint32_t /* reserved */ : 2;
- uint32_t pixelDataSize:2;
- uint32_t hsyncEdge:1;
- uint32_t vsyncEdge:1;
- uint32_t /* reserved */ : 12;
- /* HW Test Gen Image Config */
- uint32_t imageWidth:14;
- uint32_t /* reserved */ : 2;
- uint32_t imageHeight:14;
- uint32_t /* reserved */ : 2;
- /* SOF Offset Config */
- uint32_t sofOffset:24;
- uint32_t /* reserved */ : 8;
- /* EOF NOffset Config */
- uint32_t eofNOffset:24;
- uint32_t /* reserved */ : 8;
- /* SOL Offset Config */
- uint32_t solOffset:9;
- uint32_t /* reserved */ : 23;
- /* EOL NOffset Config */
- uint32_t eolNOffset:9;
- uint32_t /* reserved */ : 23;
- /* HBI Config */
- uint32_t hBlankInterval:14;
- uint32_t /* reserved */ : 18;
- /* VBL Config */
- uint32_t vBlankInterval:14;
- uint32_t /* reserved */ : 2;
- uint32_t vBlankIntervalEnable:1;
- uint32_t /* reserved */ : 15;
- /* SOF Dummy Line Config */
- uint32_t sofDummy:8;
- uint32_t /* reserved */ : 24;
- /* EOF Dummy Line Config */
- uint32_t eofDummy:8;
- uint32_t /* reserved */ : 24;
- /* Color Bars Config */
- uint32_t unicolorBarSelect:3;
- uint32_t /* reserved */ : 1;
- uint32_t unicolorBarEnable:1;
- uint32_t splitEnable:1;
- uint32_t pixelPattern:2;
- uint32_t rotatePeriod:6;
- uint32_t /* reserved */ : 18;
- /* Random Config */
- uint32_t randomSeed:16;
- uint32_t /* reserved */ : 16;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_Bus_Pm_ConfigCmdType {
- /* VFE Bus Performance Monitor Config */
- uint32_t output2YWrPmEnable:1;
- uint32_t output2CbcrWrPmEnable:1;
- uint32_t output1YWrPmEnable:1;
- uint32_t output1CbcrWrPmEnable:1;
- uint32_t /* reserved */ : 28;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_asf_info {
- /* asf max edge */
- uint32_t maxEdge:13;
- uint32_t /* reserved */ : 3;
- /* HBi count */
- uint32_t HBICount:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_camif_stats {
- uint32_t pixelCount:14;
- uint32_t /* reserved */ : 2;
- uint32_t lineCount:14;
- uint32_t /* reserved */ : 1;
- uint32_t camifHalt:1;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_StatsCmdType {
- uint32_t autoFocusEnable:1;
- uint32_t axwEnable:1;
- uint32_t histEnable:1;
- uint32_t clearHistEnable:1;
- uint32_t histAutoClearEnable:1;
- uint32_t colorConversionEnable:1;
- uint32_t /* reserved */ : 26;
-} __attribute__((packed, aligned(4)));
-
-
-struct vfe_statsframe {
- uint32_t lastPixel:12;
- uint32_t /* reserved */ : 4;
- uint32_t lastLine:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_busstats_wrprio {
- uint32_t afBusPriority:4;
- uint32_t awbBusPriority:4;
- uint32_t histBusPriority:4;
- uint32_t afBusPriorityEn:1;
- uint32_t awbBusPriorityEn:1;
- uint32_t histBusPriorityEn:1;
- uint32_t /* reserved */ : 17;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_statsaf_update {
- /* VFE_STATS_AF_CFG */
- uint32_t windowVOffset:12;
- uint32_t /* reserved */ : 4;
- uint32_t windowHOffset:12;
- uint32_t /* reserved */ : 3;
- uint32_t windowMode:1;
-
- /* VFE_STATS_AF_DIM */
- uint32_t windowHeight:12;
- uint32_t /* reserved */ : 4;
- uint32_t windowWidth:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_statsaf_cfg {
- /* VFE_STATS_AF_GRID_0 */
- uint32_t entry00:8;
- uint32_t entry01:8;
- uint32_t entry02:8;
- uint32_t entry03:8;
-
- /* VFE_STATS_AF_GRID_1 */
- uint32_t entry10:8;
- uint32_t entry11:8;
- uint32_t entry12:8;
- uint32_t entry13:8;
-
- /* VFE_STATS_AF_GRID_2 */
- uint32_t entry20:8;
- uint32_t entry21:8;
- uint32_t entry22:8;
- uint32_t entry23:8;
-
- /* VFE_STATS_AF_GRID_3 */
- uint32_t entry30:8;
- uint32_t entry31:8;
- uint32_t entry32:8;
- uint32_t entry33:8;
-
- /* VFE_STATS_AF_HEADER */
- uint32_t afHeader:8;
- uint32_t /* reserved */ : 24;
- /* VFE_STATS_AF_COEF0 */
- uint32_t a00:5;
- uint32_t a04:5;
- uint32_t fvMax:11;
- uint32_t fvMetric:1;
- uint32_t /* reserved */ : 10;
-
- /* VFE_STATS_AF_COEF1 */
- uint32_t a20:5;
- uint32_t a21:5;
- uint32_t a22:5;
- uint32_t a23:5;
- uint32_t a24:5;
- uint32_t /* reserved */ : 7;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_statsawbae_update {
- uint32_t aeRegionCfg:1;
- uint32_t aeSubregionCfg:1;
- uint32_t /* reserved */ : 14;
- uint32_t awbYMin:8;
- uint32_t awbYMax:8;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_statsaxw_hdr_cfg {
- /* Stats AXW Header Config */
- uint32_t axwHeader:8;
- uint32_t /* reserved */ : 24;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_statsawb_update {
- /* AWB MConfig */
- uint32_t m4:8;
- uint32_t m3:8;
- uint32_t m2:8;
- uint32_t m1:8;
-
- /* AWB CConfig1 */
- uint32_t c2:12;
- uint32_t /* reserved */ : 4;
- uint32_t c1:12;
- uint32_t /* reserved */ : 4;
-
- /* AWB CConfig2 */
- uint32_t c4:12;
- uint32_t /* reserved */ : 4;
- uint32_t c3:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_SyncTimerCmdType {
- uint32_t hsyncCount:12;
- uint32_t /* reserved */ : 20;
- uint32_t pclkCount:18;
- uint32_t /* reserved */ : 14;
- uint32_t outputDuration:28;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_AsyncTimerCmdType {
- /* config 0 */
- uint32_t inactiveCount:20;
- uint32_t repeatCount:10;
- uint32_t /* reserved */ : 1;
- uint32_t polarity:1;
- /* config 1 */
- uint32_t activeCount:20;
- uint32_t /* reserved */ : 12;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_AxiInputCmdType {
- uint32_t stripeStartAddr0:32;
- uint32_t stripeStartAddr1:32;
- uint32_t stripeStartAddr2:32;
- uint32_t stripeStartAddr3:32;
-
- uint32_t ySize:12;
- uint32_t yOffsetDelta:12;
- uint32_t /* reserved */ : 8;
-
- /* bus_stripe_rd_hSize */
- uint32_t /* reserved */ : 16;
- uint32_t xSizeWord:10;
- uint32_t /* reserved */ : 6;
-
- /* bus_stripe_rd_buffer_cfg */
- uint32_t burstLength:2;
- uint32_t /* reserved */ : 2;
- uint32_t NumOfRows:12;
- uint32_t RowIncrement:12;
- uint32_t /* reserved */ : 4;
-
- /* bus_stripe_rd_unpack_cfg */
- uint32_t mainUnpackHeight:12;
- uint32_t mainUnpackWidth:13;
- uint32_t mainUnpackHbiSel:3;
- uint32_t mainUnpackPhase:3;
- uint32_t /* reserved */ : 1;
-
- /* bus_stripe_rd_unpack */
- uint32_t unpackPattern:32;
-
- /* bus_stripe_rd_pad_size */
- uint32_t padLeft:7;
- uint32_t /* reserved */ : 1;
- uint32_t padRight:7;
- uint32_t /* reserved */ : 1;
- uint32_t padTop:7;
- uint32_t /* reserved */ : 1;
- uint32_t padBottom:7;
- uint32_t /* reserved */ : 1;
-
- /* bus_stripe_rd_pad_L_unpack */
- uint32_t leftUnpackPattern0:4;
- uint32_t leftUnpackPattern1:4;
- uint32_t leftUnpackPattern2:4;
- uint32_t leftUnpackPattern3:4;
- uint32_t leftUnpackStop0:1;
- uint32_t leftUnpackStop1:1;
- uint32_t leftUnpackStop2:1;
- uint32_t leftUnpackStop3:1;
- uint32_t /* reserved */ : 12;
-
- /* bus_stripe_rd_pad_R_unpack */
- uint32_t rightUnpackPattern0:4;
- uint32_t rightUnpackPattern1:4;
- uint32_t rightUnpackPattern2:4;
- uint32_t rightUnpackPattern3:4;
- uint32_t rightUnpackStop0:1;
- uint32_t rightUnpackStop1:1;
- uint32_t rightUnpackStop2:1;
- uint32_t rightUnpackStop3:1;
- uint32_t /* reserved */ : 12;
-
- /* bus_stripe_rd_pad_tb_unpack */
- uint32_t topUnapckPattern:4;
- uint32_t /* reserved */ : 12;
- uint32_t bottomUnapckPattern:4;
- uint32_t /* reserved */ : 12;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_AxiRdFragIrqEnable {
- uint32_t stripeRdFragirq0Enable:1;
- uint32_t stripeRdFragirq1Enable:1;
- uint32_t stripeRdFragirq2Enable:1;
- uint32_t stripeRdFragirq3Enable:1;
- uint32_t /* reserved */ : 28;
-} __attribute__((packed, aligned(4)));
-
-int vfe_cmd_init(struct msm_vfe_callback *, struct platform_device *, void *);
-void vfe_stats_af_stop(void);
-void vfe_stop(void);
-void vfe_update(void);
-int vfe_rgb_gamma_update(struct vfe_cmd_rgb_gamma_config *);
-int vfe_rgb_gamma_config(struct vfe_cmd_rgb_gamma_config *);
-void vfe_stats_wb_exp_ack(struct vfe_cmd_stats_wb_exp_ack *);
-void vfe_stats_af_ack(struct vfe_cmd_stats_af_ack *);
-void vfe_start(struct vfe_cmd_start *);
-void vfe_la_update(struct vfe_cmd_la_config *);
-void vfe_la_config(struct vfe_cmd_la_config *);
-void vfe_test_gen_start(struct vfe_cmd_test_gen_start *);
-void vfe_frame_skip_update(struct vfe_cmd_frame_skip_update *);
-void vfe_frame_skip_config(struct vfe_cmd_frame_skip_config *);
-void vfe_output_clamp_config(struct vfe_cmd_output_clamp_config *);
-void vfe_camif_frame_update(struct vfe_cmds_camif_frame *);
-void vfe_color_correction_config(struct vfe_cmd_color_correction_config *);
-void vfe_demosaic_abf_update(struct vfe_cmd_demosaic_abf_update *);
-void vfe_demosaic_bpc_update(struct vfe_cmd_demosaic_bpc_update *);
-void vfe_demosaic_config(struct vfe_cmd_demosaic_config *);
-void vfe_demux_channel_gain_update(struct vfe_cmd_demux_channel_gain_config *);
-void vfe_demux_channel_gain_config(struct vfe_cmd_demux_channel_gain_config *);
-void vfe_black_level_update(struct vfe_cmd_black_level_config *);
-void vfe_black_level_config(struct vfe_cmd_black_level_config *);
-void vfe_asf_update(struct vfe_cmd_asf_update *);
-void vfe_asf_config(struct vfe_cmd_asf_config *);
-void vfe_white_balance_config(struct vfe_cmd_white_balance_config *);
-void vfe_chroma_sup_config(struct vfe_cmd_chroma_suppression_config *);
-void vfe_roll_off_config(struct vfe_cmd_roll_off_config *);
-void vfe_chroma_subsample_config(struct vfe_cmd_chroma_subsample_config *);
-void vfe_chroma_enhan_config(struct vfe_cmd_chroma_enhan_config *);
-void vfe_scaler2cbcr_config(struct vfe_cmd_scaler2_config *);
-void vfe_scaler2y_config(struct vfe_cmd_scaler2_config *);
-void vfe_main_scaler_config(struct vfe_cmd_main_scaler_config *);
-void vfe_stats_wb_exp_stop(void);
-void vfe_stats_update_wb_exp(struct vfe_cmd_stats_wb_exp_update *);
-void vfe_stats_update_af(struct vfe_cmd_stats_af_update *);
-void vfe_stats_start_wb_exp(struct vfe_cmd_stats_wb_exp_start *);
-void vfe_stats_start_af(struct vfe_cmd_stats_af_start *);
-void vfe_stats_setting(struct vfe_cmd_stats_setting *);
-void vfe_axi_input_config(struct vfe_cmd_axi_input_config *);
-void vfe_stats_config(struct vfe_cmd_stats_setting *);
-void vfe_axi_output_config(struct vfe_cmd_axi_output_config *);
-void vfe_camif_config(struct vfe_cmd_camif_config *);
-void vfe_fov_crop_config(struct vfe_cmd_fov_crop_config *);
-void vfe_get_hw_version(struct vfe_cmd_hw_version *);
-void vfe_reset(void);
-void vfe_cmd_release(struct platform_device *);
-void vfe_output1_ack(struct vfe_cmd_output_ack *);
-void vfe_output2_ack(struct vfe_cmd_output_ack *);
-#endif /* __MSM_VFE8X_REG_H__ */
diff --git a/trunk/drivers/staging/dream/camera/mt9d112.c b/trunk/drivers/staging/dream/camera/mt9d112.c
deleted file mode 100644
index e6f2d5124611..000000000000
--- a/trunk/drivers/staging/dream/camera/mt9d112.c
+++ /dev/null
@@ -1,762 +0,0 @@
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include "mt9d112.h"
-
-/* Micron MT9D112 Registers and their values */
-/* Sensor Core Registers */
-#define REG_MT9D112_MODEL_ID 0x3000
-#define MT9D112_MODEL_ID 0x1580
-
-/* SOC Registers Page 1 */
-#define REG_MT9D112_SENSOR_RESET 0x301A
-#define REG_MT9D112_STANDBY_CONTROL 0x3202
-#define REG_MT9D112_MCU_BOOT 0x3386
-
-struct mt9d112_work {
- struct work_struct work;
-};
-
-static struct mt9d112_work *mt9d112_sensorw;
-static struct i2c_client *mt9d112_client;
-
-struct mt9d112_ctrl {
- const struct msm_camera_sensor_info *sensordata;
-};
-
-
-static struct mt9d112_ctrl *mt9d112_ctrl;
-
-static DECLARE_WAIT_QUEUE_HEAD(mt9d112_wait_queue);
-DECLARE_MUTEX(mt9d112_sem);
-
-
-/*=============================================================
- EXTERNAL DECLARATIONS
-==============================================================*/
-extern struct mt9d112_reg mt9d112_regs;
-
-
-/*=============================================================*/
-
-static int mt9d112_reset(const struct msm_camera_sensor_info *dev)
-{
- int rc = 0;
-
- rc = gpio_request(dev->sensor_reset, "mt9d112");
-
- if (!rc) {
- rc = gpio_direction_output(dev->sensor_reset, 0);
- mdelay(20);
- rc = gpio_direction_output(dev->sensor_reset, 1);
- }
-
- gpio_free(dev->sensor_reset);
- return rc;
-}
-
-static int32_t mt9d112_i2c_txdata(unsigned short saddr,
- unsigned char *txdata, int length)
-{
- struct i2c_msg msg[] = {
- {
- .addr = saddr,
- .flags = 0,
- .len = length,
- .buf = txdata,
- },
- };
-
- if (i2c_transfer(mt9d112_client->adapter, msg, 1) < 0) {
- CDBG("mt9d112_i2c_txdata failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int32_t mt9d112_i2c_write(unsigned short saddr,
- unsigned short waddr, unsigned short wdata, enum mt9d112_width width)
-{
- int32_t rc = -EIO;
- unsigned char buf[4];
-
- memset(buf, 0, sizeof(buf));
- switch (width) {
- case WORD_LEN: {
- buf[0] = (waddr & 0xFF00)>>8;
- buf[1] = (waddr & 0x00FF);
- buf[2] = (wdata & 0xFF00)>>8;
- buf[3] = (wdata & 0x00FF);
-
- rc = mt9d112_i2c_txdata(saddr, buf, 4);
- }
- break;
-
- case BYTE_LEN: {
- buf[0] = waddr;
- buf[1] = wdata;
- rc = mt9d112_i2c_txdata(saddr, buf, 2);
- }
- break;
-
- default:
- break;
- }
-
- if (rc < 0)
- CDBG(
- "i2c_write failed, addr = 0x%x, val = 0x%x!\n",
- waddr, wdata);
-
- return rc;
-}
-
-static int32_t mt9d112_i2c_write_table(
- struct mt9d112_i2c_reg_conf const *reg_conf_tbl,
- int num_of_items_in_table)
-{
- int i;
- int32_t rc = -EIO;
-
- for (i = 0; i < num_of_items_in_table; i++) {
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- reg_conf_tbl->waddr, reg_conf_tbl->wdata,
- reg_conf_tbl->width);
- if (rc < 0)
- break;
- if (reg_conf_tbl->mdelay_time != 0)
- mdelay(reg_conf_tbl->mdelay_time);
- reg_conf_tbl++;
- }
-
- return rc;
-}
-
-static int mt9d112_i2c_rxdata(unsigned short saddr,
- unsigned char *rxdata, int length)
-{
- struct i2c_msg msgs[] = {
- {
- .addr = saddr,
- .flags = 0,
- .len = 2,
- .buf = rxdata,
- },
- {
- .addr = saddr,
- .flags = I2C_M_RD,
- .len = length,
- .buf = rxdata,
- },
- };
-
- if (i2c_transfer(mt9d112_client->adapter, msgs, 2) < 0) {
- CDBG("mt9d112_i2c_rxdata failed!\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int32_t mt9d112_i2c_read(unsigned short saddr,
- unsigned short raddr, unsigned short *rdata, enum mt9d112_width width)
-{
- int32_t rc = 0;
- unsigned char buf[4];
-
- if (!rdata)
- return -EIO;
-
- memset(buf, 0, sizeof(buf));
-
- switch (width) {
- case WORD_LEN: {
- buf[0] = (raddr & 0xFF00)>>8;
- buf[1] = (raddr & 0x00FF);
-
- rc = mt9d112_i2c_rxdata(saddr, buf, 2);
- if (rc < 0)
- return rc;
-
- *rdata = buf[0] << 8 | buf[1];
- }
- break;
-
- default:
- break;
- }
-
- if (rc < 0)
- CDBG("mt9d112_i2c_read failed!\n");
-
- return rc;
-}
-
-static int32_t mt9d112_set_lens_roll_off(void)
-{
- int32_t rc = 0;
- rc = mt9d112_i2c_write_table(&mt9d112_regs.rftbl[0],
- mt9d112_regs.rftbl_size);
- return rc;
-}
-
-static long mt9d112_reg_init(void)
-{
- int32_t array_length;
- int32_t i;
- long rc;
-
- /* PLL Setup Start */
- rc = mt9d112_i2c_write_table(&mt9d112_regs.plltbl[0],
- mt9d112_regs.plltbl_size);
-
- if (rc < 0)
- return rc;
- /* PLL Setup End */
-
- array_length = mt9d112_regs.prev_snap_reg_settings_size;
-
- /* Configure sensor for Preview mode and Snapshot mode */
- for (i = 0; i < array_length; i++) {
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- mt9d112_regs.prev_snap_reg_settings[i].register_address,
- mt9d112_regs.prev_snap_reg_settings[i].register_value,
- WORD_LEN);
-
- if (rc < 0)
- return rc;
- }
-
- /* Configure for Noise Reduction, Saturation and Aperture Correction */
- array_length = mt9d112_regs.noise_reduction_reg_settings_size;
-
- for (i = 0; i < array_length; i++) {
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- mt9d112_regs.noise_reduction_reg_settings[i].register_address,
- mt9d112_regs.noise_reduction_reg_settings[i].register_value,
- WORD_LEN);
-
- if (rc < 0)
- return rc;
- }
-
- /* Set Color Kill Saturation point to optimum value */
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x35A4,
- 0x0593,
- WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_i2c_write_table(&mt9d112_regs.stbl[0],
- mt9d112_regs.stbl_size);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_set_lens_roll_off();
- if (rc < 0)
- return rc;
-
- return 0;
-}
-
-static long mt9d112_set_sensor_mode(int mode)
-{
- uint16_t clock;
- long rc = 0;
-
- switch (mode) {
- case SENSOR_PREVIEW_MODE:
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, 0xA20C, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, 0x0004, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, 0xA215, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, 0x0004, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, 0xA20B, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, 0x0000, WORD_LEN);
- if (rc < 0)
- return rc;
-
- clock = 0x0250;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x341C, clock, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, 0xA103, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, 0x0001, WORD_LEN);
- if (rc < 0)
- return rc;
-
- mdelay(5);
- break;
-
- case SENSOR_SNAPSHOT_MODE:
- /* Switch to lower fps for Snapshot */
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x341C, 0x0120, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, 0xA120, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, 0x0002, WORD_LEN);
- if (rc < 0)
- return rc;
-
- mdelay(5);
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, 0xA103, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, 0x0002, WORD_LEN);
- if (rc < 0)
- return rc;
- break;
-
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static long mt9d112_set_effect(int mode, int effect)
-{
- uint16_t reg_addr;
- uint16_t reg_val;
- long rc = 0;
-
- switch (mode) {
- case SENSOR_PREVIEW_MODE:
- /* Context A Special Effects */
- reg_addr = 0x2799;
- break;
-
- case SENSOR_SNAPSHOT_MODE:
- /* Context B Special Effects */
- reg_addr = 0x279B;
- break;
-
- default:
- reg_addr = 0x2799;
- break;
- }
-
- switch (effect) {
- case CAMERA_EFFECT_OFF: {
- reg_val = 0x6440;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, reg_addr, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, reg_val, WORD_LEN);
- if (rc < 0)
- return rc;
- }
- break;
-
- case CAMERA_EFFECT_MONO: {
- reg_val = 0x6441;
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, reg_addr, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, reg_val, WORD_LEN);
- if (rc < 0)
- return rc;
- }
- break;
-
- case CAMERA_EFFECT_NEGATIVE: {
- reg_val = 0x6443;
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, reg_addr, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, reg_val, WORD_LEN);
- if (rc < 0)
- return rc;
- }
- break;
-
- case CAMERA_EFFECT_SOLARIZE: {
- reg_val = 0x6445;
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, reg_addr, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, reg_val, WORD_LEN);
- if (rc < 0)
- return rc;
- }
- break;
-
- case CAMERA_EFFECT_SEPIA: {
- reg_val = 0x6442;
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, reg_addr, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, reg_val, WORD_LEN);
- if (rc < 0)
- return rc;
- }
- break;
-
- case CAMERA_EFFECT_PASTEL:
- case CAMERA_EFFECT_MOSAIC:
- case CAMERA_EFFECT_RESIZE:
- return -EINVAL;
-
- default: {
- reg_val = 0x6440;
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, reg_addr, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, reg_val, WORD_LEN);
- if (rc < 0)
- return rc;
-
- return -EINVAL;
- }
- }
-
- /* Refresh Sequencer */
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, 0xA103, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, 0x0005, WORD_LEN);
-
- return rc;
-}
-
-static int mt9d112_sensor_init_probe(const struct msm_camera_sensor_info *data)
-{
- uint16_t model_id = 0;
- int rc = 0;
-
- CDBG("init entry \n");
- rc = mt9d112_reset(data);
- if (rc < 0) {
- CDBG("reset failed!\n");
- goto init_probe_fail;
- }
-
- mdelay(5);
-
- /* Micron suggested Power up block Start:
- * Put MCU into Reset - Stop MCU */
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- REG_MT9D112_MCU_BOOT, 0x0501, WORD_LEN);
- if (rc < 0)
- goto init_probe_fail;
-
- /* Pull MCU from Reset - Start MCU */
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- REG_MT9D112_MCU_BOOT, 0x0500, WORD_LEN);
- if (rc < 0)
- goto init_probe_fail;
-
- mdelay(5);
-
- /* Micron Suggested - Power up block */
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- REG_MT9D112_SENSOR_RESET, 0x0ACC, WORD_LEN);
- if (rc < 0)
- goto init_probe_fail;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- REG_MT9D112_STANDBY_CONTROL, 0x0008, WORD_LEN);
- if (rc < 0)
- goto init_probe_fail;
-
- /* FUSED_DEFECT_CORRECTION */
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x33F4, 0x031D, WORD_LEN);
- if (rc < 0)
- goto init_probe_fail;
-
- mdelay(5);
-
- /* Micron suggested Power up block End */
- /* Read the Model ID of the sensor */
- rc = mt9d112_i2c_read(mt9d112_client->addr,
- REG_MT9D112_MODEL_ID, &model_id, WORD_LEN);
- if (rc < 0)
- goto init_probe_fail;
-
- CDBG("mt9d112 model_id = 0x%x\n", model_id);
-
- /* Check if it matches it with the value in Datasheet */
- if (model_id != MT9D112_MODEL_ID) {
- rc = -EINVAL;
- goto init_probe_fail;
- }
-
- rc = mt9d112_reg_init();
- if (rc < 0)
- goto init_probe_fail;
-
- return rc;
-
-init_probe_fail:
- return rc;
-}
-
-int mt9d112_sensor_init(const struct msm_camera_sensor_info *data)
-{
- int rc = 0;
-
- mt9d112_ctrl = kzalloc(sizeof(struct mt9d112_ctrl), GFP_KERNEL);
- if (!mt9d112_ctrl) {
- CDBG("mt9d112_init failed!\n");
- rc = -ENOMEM;
- goto init_done;
- }
-
- if (data)
- mt9d112_ctrl->sensordata = data;
-
- /* Input MCLK = 24MHz */
- msm_camio_clk_rate_set(24000000);
- mdelay(5);
-
- msm_camio_camif_pad_reg_reset();
-
- rc = mt9d112_sensor_init_probe(data);
- if (rc < 0) {
- CDBG("mt9d112_sensor_init failed!\n");
- goto init_fail;
- }
-
-init_done:
- return rc;
-
-init_fail:
- kfree(mt9d112_ctrl);
- return rc;
-}
-
-static int mt9d112_init_client(struct i2c_client *client)
-{
- /* Initialize the MSM_CAMI2C Chip */
- init_waitqueue_head(&mt9d112_wait_queue);
- return 0;
-}
-
-int mt9d112_sensor_config(void __user *argp)
-{
- struct sensor_cfg_data cfg_data;
- long rc = 0;
-
- if (copy_from_user(&cfg_data,
- (void *)argp,
- sizeof(struct sensor_cfg_data)))
- return -EFAULT;
-
- /* down(&mt9d112_sem); */
-
- CDBG("mt9d112_ioctl, cfgtype = %d, mode = %d\n",
- cfg_data.cfgtype, cfg_data.mode);
-
- switch (cfg_data.cfgtype) {
- case CFG_SET_MODE:
- rc = mt9d112_set_sensor_mode(
- cfg_data.mode);
- break;
-
- case CFG_SET_EFFECT:
- rc = mt9d112_set_effect(cfg_data.mode,
- cfg_data.cfg.effect);
- break;
-
- case CFG_GET_AF_MAX_STEPS:
- default:
- rc = -EINVAL;
- break;
- }
-
- /* up(&mt9d112_sem); */
-
- return rc;
-}
-
-int mt9d112_sensor_release(void)
-{
- int rc = 0;
-
- /* down(&mt9d112_sem); */
-
- kfree(mt9d112_ctrl);
- /* up(&mt9d112_sem); */
-
- return rc;
-}
-
-static int mt9d112_i2c_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
-{
- int rc = 0;
- if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
- rc = -ENOTSUPP;
- goto probe_failure;
- }
-
- mt9d112_sensorw =
- kzalloc(sizeof(struct mt9d112_work), GFP_KERNEL);
-
- if (!mt9d112_sensorw) {
- rc = -ENOMEM;
- goto probe_failure;
- }
-
- i2c_set_clientdata(client, mt9d112_sensorw);
- mt9d112_init_client(client);
- mt9d112_client = client;
-
- CDBG("mt9d112_probe succeeded!\n");
-
- return 0;
-
-probe_failure:
- kfree(mt9d112_sensorw);
- mt9d112_sensorw = NULL;
- CDBG("mt9d112_probe failed!\n");
- return rc;
-}
-
-static const struct i2c_device_id mt9d112_i2c_id[] = {
- { "mt9d112", 0},
- { },
-};
-
-static struct i2c_driver mt9d112_i2c_driver = {
- .id_table = mt9d112_i2c_id,
- .probe = mt9d112_i2c_probe,
- .remove = __exit_p(mt9d112_i2c_remove),
- .driver = {
- .name = "mt9d112",
- },
-};
-
-static int mt9d112_sensor_probe(const struct msm_camera_sensor_info *info,
- struct msm_sensor_ctrl *s)
-{
- int rc = i2c_add_driver(&mt9d112_i2c_driver);
- if (rc < 0 || mt9d112_client == NULL) {
- rc = -ENOTSUPP;
- goto probe_done;
- }
-
- /* Input MCLK = 24MHz */
- msm_camio_clk_rate_set(24000000);
- mdelay(5);
-
- rc = mt9d112_sensor_init_probe(info);
- if (rc < 0)
- goto probe_done;
-
- s->s_init = mt9d112_sensor_init;
- s->s_release = mt9d112_sensor_release;
- s->s_config = mt9d112_sensor_config;
-
-probe_done:
- CDBG("%s %s:%d\n", __FILE__, __func__, __LINE__);
- return rc;
-}
-
-static int __mt9d112_probe(struct platform_device *pdev)
-{
- return msm_camera_drv_start(pdev, mt9d112_sensor_probe);
-}
-
-static struct platform_driver msm_camera_driver = {
- .probe = __mt9d112_probe,
- .driver = {
- .name = "msm_camera_mt9d112",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init mt9d112_init(void)
-{
- return platform_driver_register(&msm_camera_driver);
-}
-
-module_init(mt9d112_init);
diff --git a/trunk/drivers/staging/dream/camera/mt9d112.h b/trunk/drivers/staging/dream/camera/mt9d112.h
deleted file mode 100644
index c678996f9e2b..000000000000
--- a/trunk/drivers/staging/dream/camera/mt9d112.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#ifndef MT9D112_H
-#define MT9D112_H
-
-#include
-#include
-
-enum mt9d112_width {
- WORD_LEN,
- BYTE_LEN
-};
-
-struct mt9d112_i2c_reg_conf {
- unsigned short waddr;
- unsigned short wdata;
- enum mt9d112_width width;
- unsigned short mdelay_time;
-};
-
-struct mt9d112_reg {
- const struct register_address_value_pair *prev_snap_reg_settings;
- uint16_t prev_snap_reg_settings_size;
- const struct register_address_value_pair *noise_reduction_reg_settings;
- uint16_t noise_reduction_reg_settings_size;
- const struct mt9d112_i2c_reg_conf *plltbl;
- uint16_t plltbl_size;
- const struct mt9d112_i2c_reg_conf *stbl;
- uint16_t stbl_size;
- const struct mt9d112_i2c_reg_conf *rftbl;
- uint16_t rftbl_size;
-};
-
-#endif /* MT9D112_H */
diff --git a/trunk/drivers/staging/dream/camera/mt9d112_reg.c b/trunk/drivers/staging/dream/camera/mt9d112_reg.c
deleted file mode 100644
index c52e96f47141..000000000000
--- a/trunk/drivers/staging/dream/camera/mt9d112_reg.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#include "mt9d112.h"
-
-struct register_address_value_pair
-preview_snapshot_mode_reg_settings_array[] = {
- {0x338C, 0x2703},
- {0x3390, 800}, /* Output Width (P) = 640 */
- {0x338C, 0x2705},
- {0x3390, 600}, /* Output Height (P) = 480 */
- {0x338C, 0x2707},
- {0x3390, 0x0640}, /* Output Width (S) = 1600 */
- {0x338C, 0x2709},
- {0x3390, 0x04B0}, /* Output Height (S) = 1200 */
- {0x338C, 0x270D},
- {0x3390, 0x0000}, /* Row Start (P) = 0 */
- {0x338C, 0x270F},
- {0x3390, 0x0000}, /* Column Start (P) = 0 */
- {0x338C, 0x2711},
- {0x3390, 0x04BD}, /* Row End (P) = 1213 */
- {0x338C, 0x2713},
- {0x3390, 0x064D}, /* Column End (P) = 1613 */
- {0x338C, 0x2715},
- {0x3390, 0x0000}, /* Extra Delay (P) = 0 */
- {0x338C, 0x2717},
- {0x3390, 0x2111}, /* Row Speed (P) = 8465 */
- {0x338C, 0x2719},
- {0x3390, 0x046C}, /* Read Mode (P) = 1132 */
- {0x338C, 0x271B},
- {0x3390, 0x024F}, /* Sensor_Sample_Time_pck(P) = 591 */
- {0x338C, 0x271D},
- {0x3390, 0x0102}, /* Sensor_Fine_Correction(P) = 258 */
- {0x338C, 0x271F},
- {0x3390, 0x0279}, /* Sensor_Fine_IT_min(P) = 633 */
- {0x338C, 0x2721},
- {0x3390, 0x0155}, /* Sensor_Fine_IT_max_margin(P) = 341 */
- {0x338C, 0x2723},
- {0x3390, 659}, /* Frame Lines (P) = 679 */
- {0x338C, 0x2725},
- {0x3390, 0x0824}, /* Line Length (P) = 2084 */
- {0x338C, 0x2727},
- {0x3390, 0x2020},
- {0x338C, 0x2729},
- {0x3390, 0x2020},
- {0x338C, 0x272B},
- {0x3390, 0x1020},
- {0x338C, 0x272D},
- {0x3390, 0x2007},
- {0x338C, 0x272F},
- {0x3390, 0x0004}, /* Row Start(S) = 4 */
- {0x338C, 0x2731},
- {0x3390, 0x0004}, /* Column Start(S) = 4 */
- {0x338C, 0x2733},
- {0x3390, 0x04BB}, /* Row End(S) = 1211 */
- {0x338C, 0x2735},
- {0x3390, 0x064B}, /* Column End(S) = 1611 */
- {0x338C, 0x2737},
- {0x3390, 0x04CE}, /* Extra Delay(S) = 1230 */
- {0x338C, 0x2739},
- {0x3390, 0x2111}, /* Row Speed(S) = 8465 */
- {0x338C, 0x273B},
- {0x3390, 0x0024}, /* Read Mode(S) = 36 */
- {0x338C, 0x273D},
- {0x3390, 0x0120}, /* Sensor sample time pck(S) = 288 */
- {0x338C, 0x2741},
- {0x3390, 0x0169}, /* Sensor_Fine_IT_min(P) = 361 */
- {0x338C, 0x2745},
- {0x3390, 0x04FF}, /* Frame Lines(S) = 1279 */
- {0x338C, 0x2747},
- {0x3390, 0x0824}, /* Line Length(S) = 2084 */
- {0x338C, 0x2751},
- {0x3390, 0x0000}, /* Crop_X0(P) = 0 */
- {0x338C, 0x2753},
- {0x3390, 0x0320}, /* Crop_X1(P) = 800 */
- {0x338C, 0x2755},
- {0x3390, 0x0000}, /* Crop_Y0(P) = 0 */
- {0x338C, 0x2757},
- {0x3390, 0x0258}, /* Crop_Y1(P) = 600 */
- {0x338C, 0x275F},
- {0x3390, 0x0000}, /* Crop_X0(S) = 0 */
- {0x338C, 0x2761},
- {0x3390, 0x0640}, /* Crop_X1(S) = 1600 */
- {0x338C, 0x2763},
- {0x3390, 0x0000}, /* Crop_Y0(S) = 0 */
- {0x338C, 0x2765},
- {0x3390, 0x04B0}, /* Crop_Y1(S) = 1200 */
- {0x338C, 0x222E},
- {0x3390, 0x00A0}, /* R9 Step = 160 */
- {0x338C, 0xA408},
- {0x3390, 0x001F},
- {0x338C, 0xA409},
- {0x3390, 0x0021},
- {0x338C, 0xA40A},
- {0x3390, 0x0025},
- {0x338C, 0xA40B},
- {0x3390, 0x0027},
- {0x338C, 0x2411},
- {0x3390, 0x00A0},
- {0x338C, 0x2413},
- {0x3390, 0x00C0},
- {0x338C, 0x2415},
- {0x3390, 0x00A0},
- {0x338C, 0x2417},
- {0x3390, 0x00C0},
- {0x338C, 0x2799},
- {0x3390, 0x6408}, /* MODE_SPEC_EFFECTS(P) */
- {0x338C, 0x279B},
- {0x3390, 0x6408}, /* MODE_SPEC_EFFECTS(S) */
-};
-
-static struct register_address_value_pair
-noise_reduction_reg_settings_array[] = {
- {0x338C, 0xA76D},
- {0x3390, 0x0003},
- {0x338C, 0xA76E},
- {0x3390, 0x0003},
- {0x338C, 0xA76F},
- {0x3390, 0},
- {0x338C, 0xA770},
- {0x3390, 21},
- {0x338C, 0xA771},
- {0x3390, 37},
- {0x338C, 0xA772},
- {0x3390, 63},
- {0x338C, 0xA773},
- {0x3390, 100},
- {0x338C, 0xA774},
- {0x3390, 128},
- {0x338C, 0xA775},
- {0x3390, 151},
- {0x338C, 0xA776},
- {0x3390, 169},
- {0x338C, 0xA777},
- {0x3390, 186},
- {0x338C, 0xA778},
- {0x3390, 199},
- {0x338C, 0xA779},
- {0x3390, 210},
- {0x338C, 0xA77A},
- {0x3390, 220},
- {0x338C, 0xA77B},
- {0x3390, 228},
- {0x338C, 0xA77C},
- {0x3390, 234},
- {0x338C, 0xA77D},
- {0x3390, 240},
- {0x338C, 0xA77E},
- {0x3390, 244},
- {0x338C, 0xA77F},
- {0x3390, 248},
- {0x338C, 0xA780},
- {0x3390, 252},
- {0x338C, 0xA781},
- {0x3390, 255},
- {0x338C, 0xA782},
- {0x3390, 0},
- {0x338C, 0xA783},
- {0x3390, 21},
- {0x338C, 0xA784},
- {0x3390, 37},
- {0x338C, 0xA785},
- {0x3390, 63},
- {0x338C, 0xA786},
- {0x3390, 100},
- {0x338C, 0xA787},
- {0x3390, 128},
- {0x338C, 0xA788},
- {0x3390, 151},
- {0x338C, 0xA789},
- {0x3390, 169},
- {0x338C, 0xA78A},
- {0x3390, 186},
- {0x338C, 0xA78B},
- {0x3390, 199},
- {0x338C, 0xA78C},
- {0x3390, 210},
- {0x338C, 0xA78D},
- {0x3390, 220},
- {0x338C, 0xA78E},
- {0x3390, 228},
- {0x338C, 0xA78F},
- {0x3390, 234},
- {0x338C, 0xA790},
- {0x3390, 240},
- {0x338C, 0xA791},
- {0x3390, 244},
- {0x338C, 0xA793},
- {0x3390, 252},
- {0x338C, 0xA794},
- {0x3390, 255},
- {0x338C, 0xA103},
- {0x3390, 6},
-};
-
-static const struct mt9d112_i2c_reg_conf const lens_roll_off_tbl[] = {
- { 0x34CE, 0x81A0, WORD_LEN, 0 },
- { 0x34D0, 0x6331, WORD_LEN, 0 },
- { 0x34D2, 0x3394, WORD_LEN, 0 },
- { 0x34D4, 0x9966, WORD_LEN, 0 },
- { 0x34D6, 0x4B25, WORD_LEN, 0 },
- { 0x34D8, 0x2670, WORD_LEN, 0 },
- { 0x34DA, 0x724C, WORD_LEN, 0 },
- { 0x34DC, 0xFFFD, WORD_LEN, 0 },
- { 0x34DE, 0x00CA, WORD_LEN, 0 },
- { 0x34E6, 0x00AC, WORD_LEN, 0 },
- { 0x34EE, 0x0EE1, WORD_LEN, 0 },
- { 0x34F6, 0x0D87, WORD_LEN, 0 },
- { 0x3500, 0xE1F7, WORD_LEN, 0 },
- { 0x3508, 0x1CF4, WORD_LEN, 0 },
- { 0x3510, 0x1D28, WORD_LEN, 0 },
- { 0x3518, 0x1F26, WORD_LEN, 0 },
- { 0x3520, 0x2220, WORD_LEN, 0 },
- { 0x3528, 0x333D, WORD_LEN, 0 },
- { 0x3530, 0x15D9, WORD_LEN, 0 },
- { 0x3538, 0xCFB8, WORD_LEN, 0 },
- { 0x354C, 0x05FE, WORD_LEN, 0 },
- { 0x3544, 0x05F8, WORD_LEN, 0 },
- { 0x355C, 0x0596, WORD_LEN, 0 },
- { 0x3554, 0x0611, WORD_LEN, 0 },
- { 0x34E0, 0x00F2, WORD_LEN, 0 },
- { 0x34E8, 0x00A8, WORD_LEN, 0 },
- { 0x34F0, 0x0F7B, WORD_LEN, 0 },
- { 0x34F8, 0x0CD7, WORD_LEN, 0 },
- { 0x3502, 0xFEDB, WORD_LEN, 0 },
- { 0x350A, 0x13E4, WORD_LEN, 0 },
- { 0x3512, 0x1F2C, WORD_LEN, 0 },
- { 0x351A, 0x1D20, WORD_LEN, 0 },
- { 0x3522, 0x2422, WORD_LEN, 0 },
- { 0x352A, 0x2925, WORD_LEN, 0 },
- { 0x3532, 0x1D04, WORD_LEN, 0 },
- { 0x353A, 0xFBF2, WORD_LEN, 0 },
- { 0x354E, 0x0616, WORD_LEN, 0 },
- { 0x3546, 0x0597, WORD_LEN, 0 },
- { 0x355E, 0x05CD, WORD_LEN, 0 },
- { 0x3556, 0x0529, WORD_LEN, 0 },
- { 0x34E4, 0x00B2, WORD_LEN, 0 },
- { 0x34EC, 0x005E, WORD_LEN, 0 },
- { 0x34F4, 0x0F43, WORD_LEN, 0 },
- { 0x34FC, 0x0E2F, WORD_LEN, 0 },
- { 0x3506, 0xF9FC, WORD_LEN, 0 },
- { 0x350E, 0x0CE4, WORD_LEN, 0 },
- { 0x3516, 0x1E1E, WORD_LEN, 0 },
- { 0x351E, 0x1B19, WORD_LEN, 0 },
- { 0x3526, 0x151B, WORD_LEN, 0 },
- { 0x352E, 0x1416, WORD_LEN, 0 },
- { 0x3536, 0x10FC, WORD_LEN, 0 },
- { 0x353E, 0xC018, WORD_LEN, 0 },
- { 0x3552, 0x06B4, WORD_LEN, 0 },
- { 0x354A, 0x0506, WORD_LEN, 0 },
- { 0x3562, 0x06AB, WORD_LEN, 0 },
- { 0x355A, 0x063A, WORD_LEN, 0 },
- { 0x34E2, 0x00E5, WORD_LEN, 0 },
- { 0x34EA, 0x008B, WORD_LEN, 0 },
- { 0x34F2, 0x0E4C, WORD_LEN, 0 },
- { 0x34FA, 0x0CA3, WORD_LEN, 0 },
- { 0x3504, 0x0907, WORD_LEN, 0 },
- { 0x350C, 0x1DFD, WORD_LEN, 0 },
- { 0x3514, 0x1E24, WORD_LEN, 0 },
- { 0x351C, 0x2529, WORD_LEN, 0 },
- { 0x3524, 0x1D20, WORD_LEN, 0 },
- { 0x352C, 0x2332, WORD_LEN, 0 },
- { 0x3534, 0x10E9, WORD_LEN, 0 },
- { 0x353C, 0x0BCB, WORD_LEN, 0 },
- { 0x3550, 0x04EF, WORD_LEN, 0 },
- { 0x3548, 0x0609, WORD_LEN, 0 },
- { 0x3560, 0x0580, WORD_LEN, 0 },
- { 0x3558, 0x05DD, WORD_LEN, 0 },
- { 0x3540, 0x0000, WORD_LEN, 0 },
- { 0x3542, 0x0000, WORD_LEN, 0 }
-};
-
-static const struct mt9d112_i2c_reg_conf const pll_setup_tbl[] = {
- { 0x341E, 0x8F09, WORD_LEN, 0 },
- { 0x341C, 0x0250, WORD_LEN, 0 },
- { 0x341E, 0x8F09, WORD_LEN, 5 },
- { 0x341E, 0x8F08, WORD_LEN, 0 }
-};
-
-/* Refresh Sequencer */
-static const struct mt9d112_i2c_reg_conf const sequencer_tbl[] = {
- { 0x338C, 0x2799, WORD_LEN, 0},
- { 0x3390, 0x6440, WORD_LEN, 5},
- { 0x338C, 0x279B, WORD_LEN, 0},
- { 0x3390, 0x6440, WORD_LEN, 5},
- { 0x338C, 0xA103, WORD_LEN, 0},
- { 0x3390, 0x0005, WORD_LEN, 5},
- { 0x338C, 0xA103, WORD_LEN, 0},
- { 0x3390, 0x0006, WORD_LEN, 5}
-};
-
-struct mt9d112_reg mt9d112_regs = {
- .prev_snap_reg_settings = &preview_snapshot_mode_reg_settings_array[0],
- .prev_snap_reg_settings_size = ARRAY_SIZE(preview_snapshot_mode_reg_settings_array),
- .noise_reduction_reg_settings = &noise_reduction_reg_settings_array[0],
- .noise_reduction_reg_settings_size = ARRAY_SIZE(noise_reduction_reg_settings_array),
- .plltbl = pll_setup_tbl,
- .plltbl_size = ARRAY_SIZE(pll_setup_tbl),
- .stbl = sequencer_tbl,
- .stbl_size = ARRAY_SIZE(sequencer_tbl),
- .rftbl = lens_roll_off_tbl,
- .rftbl_size = ARRAY_SIZE(lens_roll_off_tbl)
-};
-
-
-
diff --git a/trunk/drivers/staging/dream/camera/mt9p012.h b/trunk/drivers/staging/dream/camera/mt9p012.h
deleted file mode 100644
index 678a0027d42e..000000000000
--- a/trunk/drivers/staging/dream/camera/mt9p012.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-
-#ifndef MT9T012_H
-#define MT9T012_H
-
-#include
-
-struct reg_struct {
- uint16_t vt_pix_clk_div; /* 0x0300 */
- uint16_t vt_sys_clk_div; /* 0x0302 */
- uint16_t pre_pll_clk_div; /* 0x0304 */
- uint16_t pll_multiplier; /* 0x0306 */
- uint16_t op_pix_clk_div; /* 0x0308 */
- uint16_t op_sys_clk_div; /* 0x030A */
- uint16_t scale_m; /* 0x0404 */
- uint16_t row_speed; /* 0x3016 */
- uint16_t x_addr_start; /* 0x3004 */
- uint16_t x_addr_end; /* 0x3008 */
- uint16_t y_addr_start; /* 0x3002 */
- uint16_t y_addr_end; /* 0x3006 */
- uint16_t read_mode; /* 0x3040 */
- uint16_t x_output_size ; /* 0x034C */
- uint16_t y_output_size; /* 0x034E */
- uint16_t line_length_pck; /* 0x300C */
- uint16_t frame_length_lines; /* 0x300A */
- uint16_t coarse_int_time; /* 0x3012 */
- uint16_t fine_int_time; /* 0x3014 */
-};
-
-
-struct mt9p012_i2c_reg_conf {
- unsigned short waddr;
- unsigned short wdata;
-};
-
-
-struct mt9p012_reg {
- struct reg_struct *reg_pat;
- uint16_t reg_pat_size;
- struct mt9p012_i2c_reg_conf *ttbl;
- uint16_t ttbl_size;
- struct mt9p012_i2c_reg_conf *lctbl;
- uint16_t lctbl_size;
- struct mt9p012_i2c_reg_conf *rftbl;
- uint16_t rftbl_size;
-};
-
-#endif /* MT9T012_H */
diff --git a/trunk/drivers/staging/dream/camera/mt9p012_fox.c b/trunk/drivers/staging/dream/camera/mt9p012_fox.c
deleted file mode 100644
index 791bd6c40615..000000000000
--- a/trunk/drivers/staging/dream/camera/mt9p012_fox.c
+++ /dev/null
@@ -1,1306 +0,0 @@
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include "mt9p012.h"
-
-/*=============================================================
- SENSOR REGISTER DEFINES
-==============================================================*/
-#define MT9P012_REG_MODEL_ID 0x0000
-#define MT9P012_MODEL_ID 0x2801
-#define REG_GROUPED_PARAMETER_HOLD 0x0104
-#define GROUPED_PARAMETER_HOLD 0x0100
-#define GROUPED_PARAMETER_UPDATE 0x0000
-#define REG_COARSE_INT_TIME 0x3012
-#define REG_VT_PIX_CLK_DIV 0x0300
-#define REG_VT_SYS_CLK_DIV 0x0302
-#define REG_PRE_PLL_CLK_DIV 0x0304
-#define REG_PLL_MULTIPLIER 0x0306
-#define REG_OP_PIX_CLK_DIV 0x0308
-#define REG_OP_SYS_CLK_DIV 0x030A
-#define REG_SCALE_M 0x0404
-#define REG_FRAME_LENGTH_LINES 0x300A
-#define REG_LINE_LENGTH_PCK 0x300C
-#define REG_X_ADDR_START 0x3004
-#define REG_Y_ADDR_START 0x3002
-#define REG_X_ADDR_END 0x3008
-#define REG_Y_ADDR_END 0x3006
-#define REG_X_OUTPUT_SIZE 0x034C
-#define REG_Y_OUTPUT_SIZE 0x034E
-#define REG_FINE_INTEGRATION_TIME 0x3014
-#define REG_ROW_SPEED 0x3016
-#define MT9P012_REG_RESET_REGISTER 0x301A
-#define MT9P012_RESET_REGISTER_PWON 0x10CC
-#define MT9P012_RESET_REGISTER_PWOFF 0x10C8
-#define REG_READ_MODE 0x3040
-#define REG_GLOBAL_GAIN 0x305E
-#define REG_TEST_PATTERN_MODE 0x3070
-
-#define MT9P012_REV_7
-
-
-enum mt9p012_test_mode {
- TEST_OFF,
- TEST_1,
- TEST_2,
- TEST_3
-};
-
-enum mt9p012_resolution {
- QTR_SIZE,
- FULL_SIZE,
- INVALID_SIZE
-};
-
-enum mt9p012_reg_update {
- /* Sensor egisters that need to be updated during initialization */
- REG_INIT,
- /* Sensor egisters that needs periodic I2C writes */
- UPDATE_PERIODIC,
- /* All the sensor Registers will be updated */
- UPDATE_ALL,
- /* Not valid update */
- UPDATE_INVALID
-};
-
-enum mt9p012_setting {
- RES_PREVIEW,
- RES_CAPTURE
-};
-
-/* actuator's Slave Address */
-#define MT9P012_AF_I2C_ADDR 0x18
-
-/* AF Total steps parameters */
-#define MT9P012_STEPS_NEAR_TO_CLOSEST_INF 32
-#define MT9P012_TOTAL_STEPS_NEAR_TO_FAR 32
-
-#define MT9P012_MU5M0_PREVIEW_DUMMY_PIXELS 0
-#define MT9P012_MU5M0_PREVIEW_DUMMY_LINES 0
-
-/* Time in milisecs for waiting for the sensor to reset.*/
-#define MT9P012_RESET_DELAY_MSECS 66
-
-/* for 20 fps preview */
-#define MT9P012_DEFAULT_CLOCK_RATE 24000000
-#define MT9P012_DEFAULT_MAX_FPS 26 /* ???? */
-
-struct mt9p012_work {
- struct work_struct work;
-};
-static struct mt9p012_work *mt9p012_sensorw;
-static struct i2c_client *mt9p012_client;
-
-struct mt9p012_ctrl {
- const struct msm_camera_sensor_info *sensordata;
-
- int sensormode;
- uint32_t fps_divider; /* init to 1 * 0x00000400 */
- uint32_t pict_fps_divider; /* init to 1 * 0x00000400 */
-
- uint16_t curr_lens_pos;
- uint16_t init_curr_lens_pos;
- uint16_t my_reg_gain;
- uint32_t my_reg_line_count;
-
- enum mt9p012_resolution prev_res;
- enum mt9p012_resolution pict_res;
- enum mt9p012_resolution curr_res;
- enum mt9p012_test_mode set_test;
-};
-
-
-static struct mt9p012_ctrl *mt9p012_ctrl;
-static DECLARE_WAIT_QUEUE_HEAD(mt9p012_wait_queue);
-DECLARE_MUTEX(mt9p012_sem);
-
-/*=============================================================
- EXTERNAL DECLARATIONS
-==============================================================*/
-extern struct mt9p012_reg mt9p012_regs; /* from mt9p012_reg.c */
-
-
-
-/*=============================================================*/
-
-static int mt9p012_i2c_rxdata(unsigned short saddr, unsigned char *rxdata,
- int length)
-{
- struct i2c_msg msgs[] = {
- {
- .addr = saddr,
- .flags = 0,
- .len = 2,
- .buf = rxdata,
- },
- {
- .addr = saddr,
- .flags = I2C_M_RD,
- .len = length,
- .buf = rxdata,
- },
- };
-
- if (i2c_transfer(mt9p012_client->adapter, msgs, 2) < 0) {
- CDBG("mt9p012_i2c_rxdata failed!\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int32_t mt9p012_i2c_read_w(unsigned short saddr, unsigned short raddr,
- unsigned short *rdata)
-{
- int32_t rc = 0;
- unsigned char buf[4];
-
- if (!rdata)
- return -EIO;
-
- memset(buf, 0, sizeof(buf));
-
- buf[0] = (raddr & 0xFF00)>>8;
- buf[1] = (raddr & 0x00FF);
-
- rc = mt9p012_i2c_rxdata(saddr, buf, 2);
- if (rc < 0)
- return rc;
-
- *rdata = buf[0] << 8 | buf[1];
-
- if (rc < 0)
- CDBG("mt9p012_i2c_read failed!\n");
-
- return rc;
-}
-
-static int32_t mt9p012_i2c_txdata(unsigned short saddr, unsigned char *txdata,
- int length)
-{
- struct i2c_msg msg[] = {
- {
- .addr = saddr,
- .flags = 0,
- .len = length,
- .buf = txdata,
- },
- };
-
- if (i2c_transfer(mt9p012_client->adapter, msg, 1) < 0) {
- CDBG("mt9p012_i2c_txdata failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int32_t mt9p012_i2c_write_b(unsigned short saddr, unsigned short baddr,
- unsigned short bdata)
-{
- int32_t rc = -EIO;
- unsigned char buf[2];
-
- memset(buf, 0, sizeof(buf));
- buf[0] = baddr;
- buf[1] = bdata;
- rc = mt9p012_i2c_txdata(saddr, buf, 2);
-
- if (rc < 0)
- CDBG("i2c_write failed, saddr = 0x%x addr = 0x%x, val =0x%x!\n",
- saddr, baddr, bdata);
-
- return rc;
-}
-
-static int32_t mt9p012_i2c_write_w(unsigned short saddr, unsigned short waddr,
- unsigned short wdata)
-{
- int32_t rc = -EIO;
- unsigned char buf[4];
-
- memset(buf, 0, sizeof(buf));
- buf[0] = (waddr & 0xFF00)>>8;
- buf[1] = (waddr & 0x00FF);
- buf[2] = (wdata & 0xFF00)>>8;
- buf[3] = (wdata & 0x00FF);
-
- rc = mt9p012_i2c_txdata(saddr, buf, 4);
-
- if (rc < 0)
- CDBG("i2c_write_w failed, addr = 0x%x, val = 0x%x!\n",
- waddr, wdata);
-
- return rc;
-}
-
-static int32_t mt9p012_i2c_write_w_table(
- struct mt9p012_i2c_reg_conf *reg_conf_tbl, int num)
-{
- int i;
- int32_t rc = -EIO;
-
- for (i = 0; i < num; i++) {
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- reg_conf_tbl->waddr, reg_conf_tbl->wdata);
- if (rc < 0)
- break;
- reg_conf_tbl++;
- }
-
- return rc;
-}
-
-static int32_t mt9p012_test(enum mt9p012_test_mode mo)
-{
- int32_t rc = 0;
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return rc;
-
- if (mo == TEST_OFF)
- return 0;
- else {
- rc = mt9p012_i2c_write_w_table(mt9p012_regs.ttbl, mt9p012_regs.ttbl_size);
- if (rc < 0)
- return rc;
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_TEST_PATTERN_MODE, (uint16_t)mo);
- if (rc < 0)
- return rc;
- }
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
- if (rc < 0)
- return rc;
-
- return rc;
-}
-
-static int32_t mt9p012_lens_shading_enable(uint8_t is_enable)
-{
- int32_t rc = 0;
-
- CDBG("%s: entered. enable = %d\n", __func__, is_enable);
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD, GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return rc;
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr, 0x3780,
- ((uint16_t) is_enable) << 15);
- if (rc < 0)
- return rc;
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD, GROUPED_PARAMETER_UPDATE);
-
- CDBG("%s: exiting. rc = %d\n", __func__, rc);
- return rc;
-}
-
-static int32_t mt9p012_set_lc(void)
-{
- int32_t rc;
-
- rc = mt9p012_i2c_write_w_table(mt9p012_regs.lctbl, mt9p012_regs.lctbl_size);
- if (rc < 0)
- return rc;
-
- rc = mt9p012_i2c_write_w_table(mt9p012_regs.rftbl, mt9p012_regs.rftbl_size);
-
- return rc;
-}
-
-static void mt9p012_get_pict_fps(uint16_t fps, uint16_t *pfps)
-{
- /* input fps is preview fps in Q8 format */
- uint32_t divider; /*Q10 */
- uint32_t pclk_mult; /*Q10 */
-
- if (mt9p012_ctrl->prev_res == QTR_SIZE) {
- divider = (uint32_t)
- (((mt9p012_regs.reg_pat[RES_PREVIEW].frame_length_lines *
- mt9p012_regs.reg_pat[RES_PREVIEW].line_length_pck) * 0x00000400) /
- (mt9p012_regs.reg_pat[RES_CAPTURE].frame_length_lines *
- mt9p012_regs.reg_pat[RES_CAPTURE].line_length_pck));
-
- pclk_mult =
- (uint32_t) ((mt9p012_regs.reg_pat[RES_CAPTURE].pll_multiplier *
- 0x00000400) / (mt9p012_regs.reg_pat[RES_PREVIEW].pll_multiplier));
- } else {
- /* full size resolution used for preview. */
- divider = 0x00000400; /*1.0 */
- pclk_mult = 0x00000400; /*1.0 */
- }
-
- /* Verify PCLK settings and frame sizes. */
- *pfps = (uint16_t) (fps * divider * pclk_mult / 0x00000400 /
- 0x00000400);
-}
-
-static uint16_t mt9p012_get_prev_lines_pf(void)
-{
- if (mt9p012_ctrl->prev_res == QTR_SIZE)
- return mt9p012_regs.reg_pat[RES_PREVIEW].frame_length_lines;
- else
- return mt9p012_regs.reg_pat[RES_CAPTURE].frame_length_lines;
-}
-
-static uint16_t mt9p012_get_prev_pixels_pl(void)
-{
- if (mt9p012_ctrl->prev_res == QTR_SIZE)
- return mt9p012_regs.reg_pat[RES_PREVIEW].line_length_pck;
- else
- return mt9p012_regs.reg_pat[RES_CAPTURE].line_length_pck;
-}
-
-static uint16_t mt9p012_get_pict_lines_pf(void)
-{
- return mt9p012_regs.reg_pat[RES_CAPTURE].frame_length_lines;
-}
-
-static uint16_t mt9p012_get_pict_pixels_pl(void)
-{
- return mt9p012_regs.reg_pat[RES_CAPTURE].line_length_pck;
-}
-
-static uint32_t mt9p012_get_pict_max_exp_lc(void)
-{
- uint16_t snapshot_lines_per_frame;
-
- if (mt9p012_ctrl->pict_res == QTR_SIZE)
- snapshot_lines_per_frame =
- mt9p012_regs.reg_pat[RES_PREVIEW].frame_length_lines - 1;
- else
- snapshot_lines_per_frame =
- mt9p012_regs.reg_pat[RES_CAPTURE].frame_length_lines - 1;
-
- return snapshot_lines_per_frame * 24;
-}
-
-static int32_t mt9p012_set_fps(struct fps_cfg *fps)
-{
- /* input is new fps in Q10 format */
- int32_t rc = 0;
-
- mt9p012_ctrl->fps_divider = fps->fps_div;
- mt9p012_ctrl->pict_fps_divider = fps->pict_fps_div;
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return -EBUSY;
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_LINE_LENGTH_PCK,
- (mt9p012_regs.reg_pat[RES_PREVIEW].line_length_pck *
- fps->f_mult / 0x00000400));
- if (rc < 0)
- return rc;
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
-
- return rc;
-}
-
-static int32_t mt9p012_write_exp_gain(uint16_t gain, uint32_t line)
-{
- uint16_t max_legal_gain = 0x01FF;
- uint32_t line_length_ratio = 0x00000400;
- enum mt9p012_setting setting;
- int32_t rc = 0;
-
- CDBG("Line:%d mt9p012_write_exp_gain \n", __LINE__);
-
- if (mt9p012_ctrl->sensormode == SENSOR_PREVIEW_MODE) {
- mt9p012_ctrl->my_reg_gain = gain;
- mt9p012_ctrl->my_reg_line_count = (uint16_t)line;
- }
-
- if (gain > max_legal_gain) {
- CDBG("Max legal gain Line:%d \n", __LINE__);
- gain = max_legal_gain;
- }
-
- /* Verify no overflow */
- if (mt9p012_ctrl->sensormode != SENSOR_SNAPSHOT_MODE) {
- line = (uint32_t)(line * mt9p012_ctrl->fps_divider /
- 0x00000400);
- setting = RES_PREVIEW;
- } else {
- line = (uint32_t)(line * mt9p012_ctrl->pict_fps_divider /
- 0x00000400);
- setting = RES_CAPTURE;
- }
-
- /* Set digital gain to 1 */
-#ifdef MT9P012_REV_7
- gain |= 0x1000;
-#else
- gain |= 0x0200;
-#endif
-
- if ((mt9p012_regs.reg_pat[setting].frame_length_lines - 1) < line) {
- line_length_ratio = (uint32_t) (line * 0x00000400) /
- (mt9p012_regs.reg_pat[setting].frame_length_lines - 1);
- } else
- line_length_ratio = 0x00000400;
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0) {
- CDBG("mt9p012_i2c_write_w failed... Line:%d \n", __LINE__);
- return rc;
- }
-
- rc =
- mt9p012_i2c_write_w(
- mt9p012_client->addr,
- REG_GLOBAL_GAIN, gain);
- if (rc < 0) {
- CDBG("mt9p012_i2c_write_w failed... Line:%d \n", __LINE__);
- return rc;
- }
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_COARSE_INT_TIME,
- line);
- if (rc < 0) {
- CDBG("mt9p012_i2c_write_w failed... Line:%d \n", __LINE__);
- return rc;
- }
-
- CDBG("mt9p012_write_exp_gain: gain = %d, line = %d\n", gain, line);
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
- if (rc < 0)
- CDBG("mt9p012_i2c_write_w failed... Line:%d \n", __LINE__);
-
- return rc;
-}
-
-static int32_t mt9p012_set_pict_exp_gain(uint16_t gain, uint32_t line)
-{
- int32_t rc = 0;
-
- CDBG("Line:%d mt9p012_set_pict_exp_gain \n", __LINE__);
-
- rc =
- mt9p012_write_exp_gain(gain, line);
- if (rc < 0) {
- CDBG("Line:%d mt9p012_set_pict_exp_gain failed... \n",
- __LINE__);
- return rc;
- }
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- MT9P012_REG_RESET_REGISTER,
- 0x10CC | 0x0002);
- if (rc < 0) {
- CDBG("mt9p012_i2c_write_w failed... Line:%d \n", __LINE__);
- return rc;
- }
-
- mdelay(5);
-
- /* camera_timed_wait(snapshot_wait*exposure_ratio); */
- return rc;
-}
-
-static int32_t mt9p012_setting(enum mt9p012_reg_update rupdate,
- enum mt9p012_setting rt)
-{
- int32_t rc = 0;
-
- switch (rupdate) {
- case UPDATE_PERIODIC:
- if (rt == RES_PREVIEW || rt == RES_CAPTURE) {
-
- struct mt9p012_i2c_reg_conf ppc_tbl[] = {
- {REG_GROUPED_PARAMETER_HOLD, GROUPED_PARAMETER_HOLD},
- {REG_ROW_SPEED, mt9p012_regs.reg_pat[rt].row_speed},
- {REG_X_ADDR_START, mt9p012_regs.reg_pat[rt].x_addr_start},
- {REG_X_ADDR_END, mt9p012_regs.reg_pat[rt].x_addr_end},
- {REG_Y_ADDR_START, mt9p012_regs.reg_pat[rt].y_addr_start},
- {REG_Y_ADDR_END, mt9p012_regs.reg_pat[rt].y_addr_end},
- {REG_READ_MODE, mt9p012_regs.reg_pat[rt].read_mode},
- {REG_SCALE_M, mt9p012_regs.reg_pat[rt].scale_m},
- {REG_X_OUTPUT_SIZE, mt9p012_regs.reg_pat[rt].x_output_size},
- {REG_Y_OUTPUT_SIZE, mt9p012_regs.reg_pat[rt].y_output_size},
-
- {REG_LINE_LENGTH_PCK, mt9p012_regs.reg_pat[rt].line_length_pck},
- {REG_FRAME_LENGTH_LINES,
- (mt9p012_regs.reg_pat[rt].frame_length_lines *
- mt9p012_ctrl->fps_divider / 0x00000400)},
- {REG_COARSE_INT_TIME, mt9p012_regs.reg_pat[rt].coarse_int_time},
- {REG_FINE_INTEGRATION_TIME, mt9p012_regs.reg_pat[rt].fine_int_time},
- {REG_GROUPED_PARAMETER_HOLD, GROUPED_PARAMETER_UPDATE},
- };
-
- rc = mt9p012_i2c_write_w_table(&ppc_tbl[0],
- ARRAY_SIZE(ppc_tbl));
- if (rc < 0)
- return rc;
-
- rc = mt9p012_test(mt9p012_ctrl->set_test);
- if (rc < 0)
- return rc;
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- MT9P012_REG_RESET_REGISTER,
- MT9P012_RESET_REGISTER_PWON | 0x0002);
- if (rc < 0)
- return rc;
-
- mdelay(5); /* 15? wait for sensor to transition*/
-
- return rc;
- }
- break; /* UPDATE_PERIODIC */
-
- case REG_INIT:
- if (rt == RES_PREVIEW || rt == RES_CAPTURE) {
- struct mt9p012_i2c_reg_conf ipc_tbl1[] = {
- {MT9P012_REG_RESET_REGISTER, MT9P012_RESET_REGISTER_PWOFF},
- {REG_VT_PIX_CLK_DIV, mt9p012_regs.reg_pat[rt].vt_pix_clk_div},
- {REG_VT_SYS_CLK_DIV, mt9p012_regs.reg_pat[rt].vt_sys_clk_div},
- {REG_PRE_PLL_CLK_DIV, mt9p012_regs.reg_pat[rt].pre_pll_clk_div},
- {REG_PLL_MULTIPLIER, mt9p012_regs.reg_pat[rt].pll_multiplier},
- {REG_OP_PIX_CLK_DIV, mt9p012_regs.reg_pat[rt].op_pix_clk_div},
- {REG_OP_SYS_CLK_DIV, mt9p012_regs.reg_pat[rt].op_sys_clk_div},
-#ifdef MT9P012_REV_7
- {0x30B0, 0x0001},
- {0x308E, 0xE060},
- {0x3092, 0x0A52},
- {0x3094, 0x4656},
- {0x3096, 0x5652},
- {0x30CA, 0x8006},
- {0x312A, 0xDD02},
- {0x312C, 0x00E4},
- {0x3170, 0x299A},
-#endif
- /* optimized settings for noise */
- {0x3088, 0x6FF6},
- {0x3154, 0x0282},
- {0x3156, 0x0381},
- {0x3162, 0x04CE},
- {0x0204, 0x0010},
- {0x0206, 0x0010},
- {0x0208, 0x0010},
- {0x020A, 0x0010},
- {0x020C, 0x0010},
- {MT9P012_REG_RESET_REGISTER, MT9P012_RESET_REGISTER_PWON},
- };
-
- struct mt9p012_i2c_reg_conf ipc_tbl2[] = {
- {MT9P012_REG_RESET_REGISTER, MT9P012_RESET_REGISTER_PWOFF},
- {REG_VT_PIX_CLK_DIV, mt9p012_regs.reg_pat[rt].vt_pix_clk_div},
- {REG_VT_SYS_CLK_DIV, mt9p012_regs.reg_pat[rt].vt_sys_clk_div},
- {REG_PRE_PLL_CLK_DIV, mt9p012_regs.reg_pat[rt].pre_pll_clk_div},
- {REG_PLL_MULTIPLIER, mt9p012_regs.reg_pat[rt].pll_multiplier},
- {REG_OP_PIX_CLK_DIV, mt9p012_regs.reg_pat[rt].op_pix_clk_div},
- {REG_OP_SYS_CLK_DIV, mt9p012_regs.reg_pat[rt].op_sys_clk_div},
-#ifdef MT9P012_REV_7
- {0x30B0, 0x0001},
- {0x308E, 0xE060},
- {0x3092, 0x0A52},
- {0x3094, 0x4656},
- {0x3096, 0x5652},
- {0x30CA, 0x8006},
- {0x312A, 0xDD02},
- {0x312C, 0x00E4},
- {0x3170, 0x299A},
-#endif
- /* optimized settings for noise */
- {0x3088, 0x6FF6},
- {0x3154, 0x0282},
- {0x3156, 0x0381},
- {0x3162, 0x04CE},
- {0x0204, 0x0010},
- {0x0206, 0x0010},
- {0x0208, 0x0010},
- {0x020A, 0x0010},
- {0x020C, 0x0010},
- {MT9P012_REG_RESET_REGISTER, MT9P012_RESET_REGISTER_PWON},
- };
-
- struct mt9p012_i2c_reg_conf ipc_tbl3[] = {
- {REG_GROUPED_PARAMETER_HOLD, GROUPED_PARAMETER_HOLD},
- /* Set preview or snapshot mode */
- {REG_ROW_SPEED, mt9p012_regs.reg_pat[rt].row_speed},
- {REG_X_ADDR_START, mt9p012_regs.reg_pat[rt].x_addr_start},
- {REG_X_ADDR_END, mt9p012_regs.reg_pat[rt].x_addr_end},
- {REG_Y_ADDR_START, mt9p012_regs.reg_pat[rt].y_addr_start},
- {REG_Y_ADDR_END, mt9p012_regs.reg_pat[rt].y_addr_end},
- {REG_READ_MODE, mt9p012_regs.reg_pat[rt].read_mode},
- {REG_SCALE_M, mt9p012_regs.reg_pat[rt].scale_m},
- {REG_X_OUTPUT_SIZE, mt9p012_regs.reg_pat[rt].x_output_size},
- {REG_Y_OUTPUT_SIZE, mt9p012_regs.reg_pat[rt].y_output_size},
- {REG_LINE_LENGTH_PCK, mt9p012_regs.reg_pat[rt].line_length_pck},
- {REG_FRAME_LENGTH_LINES,
- mt9p012_regs.reg_pat[rt].frame_length_lines},
- {REG_COARSE_INT_TIME, mt9p012_regs.reg_pat[rt].coarse_int_time},
- {REG_FINE_INTEGRATION_TIME, mt9p012_regs.reg_pat[rt].fine_int_time},
- {REG_GROUPED_PARAMETER_HOLD, GROUPED_PARAMETER_UPDATE},
- };
-
- /* reset fps_divider */
- mt9p012_ctrl->fps_divider = 1 * 0x0400;
-
- rc = mt9p012_i2c_write_w_table(&ipc_tbl1[0],
- ARRAY_SIZE(ipc_tbl1));
- if (rc < 0)
- return rc;
-
- rc = mt9p012_i2c_write_w_table(&ipc_tbl2[0],
- ARRAY_SIZE(ipc_tbl2));
- if (rc < 0)
- return rc;
-
- mdelay(5);
-
- rc = mt9p012_i2c_write_w_table(&ipc_tbl3[0],
- ARRAY_SIZE(ipc_tbl3));
- if (rc < 0)
- return rc;
-
- /* load lens shading */
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD, GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return rc;
-
- rc = mt9p012_set_lc();
- if (rc < 0)
- return rc;
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD, GROUPED_PARAMETER_UPDATE);
-
- if (rc < 0)
- return rc;
- }
- break; /* case REG_INIT: */
-
- default:
- rc = -EINVAL;
- break;
- } /* switch (rupdate) */
-
- return rc;
-}
-
-static int32_t mt9p012_video_config(int mode, int res)
-{
- int32_t rc;
-
- switch (res) {
- case QTR_SIZE:
- rc = mt9p012_setting(UPDATE_PERIODIC, RES_PREVIEW);
- if (rc < 0)
- return rc;
-
- CDBG("mt9p012 sensor configuration done!\n");
- break;
-
- case FULL_SIZE:
- rc =
- mt9p012_setting(UPDATE_PERIODIC, RES_CAPTURE);
- if (rc < 0)
- return rc;
-
- break;
-
- default:
- return 0;
- } /* switch */
-
- mt9p012_ctrl->prev_res = res;
- mt9p012_ctrl->curr_res = res;
- mt9p012_ctrl->sensormode = mode;
-
- rc =
- mt9p012_write_exp_gain(mt9p012_ctrl->my_reg_gain,
- mt9p012_ctrl->my_reg_line_count);
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- MT9P012_REG_RESET_REGISTER,
- 0x10cc|0x0002);
-
- return rc;
-}
-
-static int32_t mt9p012_snapshot_config(int mode)
-{
- int32_t rc = 0;
-
- rc = mt9p012_setting(UPDATE_PERIODIC, RES_CAPTURE);
- if (rc < 0)
- return rc;
-
- mt9p012_ctrl->curr_res = mt9p012_ctrl->pict_res;
-
- mt9p012_ctrl->sensormode = mode;
-
- return rc;
-}
-
-static int32_t mt9p012_raw_snapshot_config(int mode)
-{
- int32_t rc = 0;
-
- rc = mt9p012_setting(UPDATE_PERIODIC, RES_CAPTURE);
- if (rc < 0)
- return rc;
-
- mt9p012_ctrl->curr_res = mt9p012_ctrl->pict_res;
-
- mt9p012_ctrl->sensormode = mode;
-
- return rc;
-}
-
-static int32_t mt9p012_power_down(void)
-{
- int32_t rc = 0;
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- MT9P012_REG_RESET_REGISTER,
- MT9P012_RESET_REGISTER_PWOFF);
-
- mdelay(5);
- return rc;
-}
-
-static int32_t mt9p012_move_focus(int direction, int32_t num_steps)
-{
- int16_t step_direction;
- int16_t actual_step;
- int16_t next_position;
- uint8_t code_val_msb, code_val_lsb;
-
- if (num_steps > MT9P012_TOTAL_STEPS_NEAR_TO_FAR)
- num_steps = MT9P012_TOTAL_STEPS_NEAR_TO_FAR;
- else if (num_steps == 0) {
- CDBG("mt9p012_move_focus failed at line %d ...\n", __LINE__);
- return -EINVAL;
- }
-
- if (direction == MOVE_NEAR)
- step_direction = 16; /* 10bit */
- else if (direction == MOVE_FAR)
- step_direction = -16; /* 10 bit */
- else {
- CDBG("mt9p012_move_focus failed at line %d ...\n", __LINE__);
- return -EINVAL;
- }
-
- if (mt9p012_ctrl->curr_lens_pos < mt9p012_ctrl->init_curr_lens_pos)
- mt9p012_ctrl->curr_lens_pos =
- mt9p012_ctrl->init_curr_lens_pos;
-
- actual_step = (int16_t)(step_direction * (int16_t)num_steps);
- next_position = (int16_t)(mt9p012_ctrl->curr_lens_pos + actual_step);
-
- if (next_position > 1023)
- next_position = 1023;
- else if (next_position < 0)
- next_position = 0;
-
- code_val_msb = next_position >> 4;
- code_val_lsb = (next_position & 0x000F) << 4;
- /* code_val_lsb |= mode_mask; */
-
- /* Writing the digital code for current to the actuator */
- if (mt9p012_i2c_write_b(MT9P012_AF_I2C_ADDR >> 1,
- code_val_msb, code_val_lsb) < 0) {
- CDBG("mt9p012_move_focus failed at line %d ...\n", __LINE__);
- return -EBUSY;
- }
-
- /* Storing the current lens Position */
- mt9p012_ctrl->curr_lens_pos = next_position;
-
- return 0;
-}
-
-static int32_t mt9p012_set_default_focus(void)
-{
- int32_t rc = 0;
- uint8_t code_val_msb, code_val_lsb;
-
- code_val_msb = 0x00;
- code_val_lsb = 0x00;
-
- /* Write the digital code for current to the actuator */
- rc = mt9p012_i2c_write_b(MT9P012_AF_I2C_ADDR >> 1,
- code_val_msb, code_val_lsb);
-
- mt9p012_ctrl->curr_lens_pos = 0;
- mt9p012_ctrl->init_curr_lens_pos = 0;
-
- return rc;
-}
-
-static int mt9p012_probe_init_done(const struct msm_camera_sensor_info *data)
-{
- gpio_direction_output(data->sensor_reset, 0);
- gpio_free(data->sensor_reset);
- return 0;
-}
-
-static int mt9p012_probe_init_sensor(const struct msm_camera_sensor_info *data)
-{
- int32_t rc;
- uint16_t chipid;
-
- rc = gpio_request(data->sensor_reset, "mt9p012");
- if (!rc)
- gpio_direction_output(data->sensor_reset, 1);
- else
- goto init_probe_done;
-
- mdelay(20);
-
- /* RESET the sensor image part via I2C command */
- CDBG("mt9p012_sensor_init(): reseting sensor.\n");
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- MT9P012_REG_RESET_REGISTER, 0x10CC|0x0001);
- if (rc < 0) {
- CDBG("sensor reset failed. rc = %d\n", rc);
- goto init_probe_fail;
- }
-
- mdelay(MT9P012_RESET_DELAY_MSECS);
-
- /* 3. Read sensor Model ID: */
- rc = mt9p012_i2c_read_w(mt9p012_client->addr,
- MT9P012_REG_MODEL_ID, &chipid);
- if (rc < 0)
- goto init_probe_fail;
-
- /* 4. Compare sensor ID to MT9T012VC ID: */
- if (chipid != MT9P012_MODEL_ID) {
- CDBG("mt9p012 wrong model_id = 0x%x\n", chipid);
- rc = -ENODEV;
- goto init_probe_fail;
- }
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr, 0x306E, 0x9000);
- if (rc < 0) {
- CDBG("REV_7 write failed. rc = %d\n", rc);
- goto init_probe_fail;
- }
-
- /* RESET_REGISTER, enable parallel interface and disable serialiser */
- CDBG("mt9p012_sensor_init(): enabling parallel interface.\n");
- rc = mt9p012_i2c_write_w(mt9p012_client->addr, 0x301A, 0x10CC);
- if (rc < 0) {
- CDBG("enable parallel interface failed. rc = %d\n", rc);
- goto init_probe_fail;
- }
-
- /* To disable the 2 extra lines */
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- 0x3064, 0x0805);
-
- if (rc < 0) {
- CDBG("disable the 2 extra lines failed. rc = %d\n", rc);
- goto init_probe_fail;
- }
-
- mdelay(MT9P012_RESET_DELAY_MSECS);
- goto init_probe_done;
-
-init_probe_fail:
- mt9p012_probe_init_done(data);
-init_probe_done:
- return rc;
-}
-
-static int mt9p012_sensor_open_init(const struct msm_camera_sensor_info *data)
-{
- int32_t rc;
-
- mt9p012_ctrl = kzalloc(sizeof(struct mt9p012_ctrl), GFP_KERNEL);
- if (!mt9p012_ctrl) {
- CDBG("mt9p012_init failed!\n");
- rc = -ENOMEM;
- goto init_done;
- }
-
- mt9p012_ctrl->fps_divider = 1 * 0x00000400;
- mt9p012_ctrl->pict_fps_divider = 1 * 0x00000400;
- mt9p012_ctrl->set_test = TEST_OFF;
- mt9p012_ctrl->prev_res = QTR_SIZE;
- mt9p012_ctrl->pict_res = FULL_SIZE;
-
- if (data)
- mt9p012_ctrl->sensordata = data;
-
- /* enable mclk first */
- msm_camio_clk_rate_set(MT9P012_DEFAULT_CLOCK_RATE);
- mdelay(20);
-
- msm_camio_camif_pad_reg_reset();
- mdelay(20);
-
- rc = mt9p012_probe_init_sensor(data);
- if (rc < 0)
- goto init_fail1;
-
- if (mt9p012_ctrl->prev_res == QTR_SIZE)
- rc = mt9p012_setting(REG_INIT, RES_PREVIEW);
- else
- rc = mt9p012_setting(REG_INIT, RES_CAPTURE);
-
- if (rc < 0) {
- CDBG("mt9p012_setting failed. rc = %d\n", rc);
- goto init_fail1;
- }
-
- /* sensor : output enable */
- CDBG("mt9p012_sensor_open_init(): enabling output.\n");
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- MT9P012_REG_RESET_REGISTER, MT9P012_RESET_REGISTER_PWON);
- if (rc < 0) {
- CDBG("sensor output enable failed. rc = %d\n", rc);
- goto init_fail1;
- }
-
- /* TODO: enable AF actuator */
-#if 0
- CDBG("enable AF actuator, gpio = %d\n",
- mt9p012_ctrl->sensordata->vcm_pwd);
- rc = gpio_request(mt9p012_ctrl->sensordata->vcm_pwd, "mt9p012");
- if (!rc)
- gpio_direction_output(mt9p012_ctrl->sensordata->vcm_pwd, 1);
- else {
- CDBG("mt9p012_ctrl gpio request failed!\n");
- goto init_fail1;
- }
- mdelay(20);
-
- rc = mt9p012_set_default_focus();
-#endif
- if (rc >= 0)
- goto init_done;
-
- /* TODO:
- * gpio_direction_output(mt9p012_ctrl->sensordata->vcm_pwd, 0);
- * gpio_free(mt9p012_ctrl->sensordata->vcm_pwd); */
-init_fail1:
- mt9p012_probe_init_done(data);
- kfree(mt9p012_ctrl);
-init_done:
- return rc;
-}
-
-static int mt9p012_init_client(struct i2c_client *client)
-{
- /* Initialize the MSM_CAMI2C Chip */
- init_waitqueue_head(&mt9p012_wait_queue);
- return 0;
-}
-
-static int32_t mt9p012_set_sensor_mode(int mode, int res)
-{
- int32_t rc = 0;
-
- switch (mode) {
- case SENSOR_PREVIEW_MODE:
- rc = mt9p012_video_config(mode, res);
- break;
-
- case SENSOR_SNAPSHOT_MODE:
- rc = mt9p012_snapshot_config(mode);
- break;
-
- case SENSOR_RAW_SNAPSHOT_MODE:
- rc = mt9p012_raw_snapshot_config(mode);
- break;
-
- default:
- rc = -EINVAL;
- break;
- }
-
- return rc;
-}
-
-int mt9p012_sensor_config(void __user *argp)
-{
- struct sensor_cfg_data cdata;
- int rc = 0;
-
- if (copy_from_user(&cdata,
- (void *)argp,
- sizeof(struct sensor_cfg_data)))
- return -EFAULT;
-
- down(&mt9p012_sem);
-
- CDBG("%s: cfgtype = %d\n", __func__, cdata.cfgtype);
- switch (cdata.cfgtype) {
- case CFG_GET_PICT_FPS:
- mt9p012_get_pict_fps(cdata.cfg.gfps.prevfps,
- &(cdata.cfg.gfps.pictfps));
-
- if (copy_to_user((void *)argp, &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PREV_L_PF:
- cdata.cfg.prevl_pf = mt9p012_get_prev_lines_pf();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PREV_P_PL:
- cdata.cfg.prevp_pl = mt9p012_get_prev_pixels_pl();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_L_PF:
- cdata.cfg.pictl_pf = mt9p012_get_pict_lines_pf();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_P_PL:
- cdata.cfg.pictp_pl = mt9p012_get_pict_pixels_pl();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_MAX_EXP_LC:
- cdata.cfg.pict_max_exp_lc =
- mt9p012_get_pict_max_exp_lc();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_SET_FPS:
- case CFG_SET_PICT_FPS:
- rc = mt9p012_set_fps(&(cdata.cfg.fps));
- break;
-
- case CFG_SET_EXP_GAIN:
- rc = mt9p012_write_exp_gain(cdata.cfg.exp_gain.gain,
- cdata.cfg.exp_gain.line);
- break;
-
- case CFG_SET_PICT_EXP_GAIN:
- CDBG("Line:%d CFG_SET_PICT_EXP_GAIN \n", __LINE__);
- rc = mt9p012_set_pict_exp_gain(cdata.cfg.exp_gain.gain,
- cdata.cfg.exp_gain.line);
- break;
-
- case CFG_SET_MODE:
- rc = mt9p012_set_sensor_mode(cdata.mode, cdata.rs);
- break;
-
- case CFG_PWR_DOWN:
- rc = mt9p012_power_down();
- break;
-
- case CFG_MOVE_FOCUS:
- CDBG("mt9p012_ioctl: CFG_MOVE_FOCUS: cdata.cfg.focus.dir=%d cdata.cfg.focus.steps=%d\n",
- cdata.cfg.focus.dir, cdata.cfg.focus.steps);
- rc = mt9p012_move_focus(cdata.cfg.focus.dir,
- cdata.cfg.focus.steps);
- break;
-
- case CFG_SET_DEFAULT_FOCUS:
- rc = mt9p012_set_default_focus();
- break;
-
- case CFG_SET_LENS_SHADING:
- CDBG("%s: CFG_SET_LENS_SHADING\n", __func__);
- rc = mt9p012_lens_shading_enable(cdata.cfg.lens_shading);
- break;
-
- case CFG_GET_AF_MAX_STEPS:
- cdata.max_steps = MT9P012_STEPS_NEAR_TO_CLOSEST_INF;
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_SET_EFFECT:
- default:
- rc = -EINVAL;
- break;
- }
-
- up(&mt9p012_sem);
- return rc;
-}
-
-int mt9p012_sensor_release(void)
-{
- int rc = -EBADF;
-
- down(&mt9p012_sem);
-
- mt9p012_power_down();
-
- gpio_direction_output(mt9p012_ctrl->sensordata->sensor_reset,
- 0);
- gpio_free(mt9p012_ctrl->sensordata->sensor_reset);
-
- gpio_direction_output(mt9p012_ctrl->sensordata->vcm_pwd, 0);
- gpio_free(mt9p012_ctrl->sensordata->vcm_pwd);
-
- kfree(mt9p012_ctrl);
- mt9p012_ctrl = NULL;
-
- CDBG("mt9p012_release completed\n");
-
- up(&mt9p012_sem);
- return rc;
-}
-
-static int mt9p012_i2c_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
-{
- int rc = 0;
- CDBG("mt9p012_probe called!\n");
-
- if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
- CDBG("i2c_check_functionality failed\n");
- goto probe_failure;
- }
-
- mt9p012_sensorw = kzalloc(sizeof(struct mt9p012_work), GFP_KERNEL);
- if (!mt9p012_sensorw) {
- CDBG("kzalloc failed.\n");
- rc = -ENOMEM;
- goto probe_failure;
- }
-
- i2c_set_clientdata(client, mt9p012_sensorw);
- mt9p012_init_client(client);
- mt9p012_client = client;
-
- mdelay(50);
-
- CDBG("mt9p012_probe successed! rc = %d\n", rc);
- return 0;
-
-probe_failure:
- CDBG("mt9p012_probe failed! rc = %d\n", rc);
- return rc;
-}
-
-static const struct i2c_device_id mt9p012_i2c_id[] = {
- { "mt9p012", 0},
- { }
-};
-
-static struct i2c_driver mt9p012_i2c_driver = {
- .id_table = mt9p012_i2c_id,
- .probe = mt9p012_i2c_probe,
- .remove = __exit_p(mt9p012_i2c_remove),
- .driver = {
- .name = "mt9p012",
- },
-};
-
-static int mt9p012_sensor_probe(const struct msm_camera_sensor_info *info,
- struct msm_sensor_ctrl *s)
-{
- int rc = i2c_add_driver(&mt9p012_i2c_driver);
- if (rc < 0 || mt9p012_client == NULL) {
- rc = -ENOTSUPP;
- goto probe_done;
- }
-
- msm_camio_clk_rate_set(MT9P012_DEFAULT_CLOCK_RATE);
- mdelay(20);
-
- rc = mt9p012_probe_init_sensor(info);
- if (rc < 0)
- goto probe_done;
-
- s->s_init = mt9p012_sensor_open_init;
- s->s_release = mt9p012_sensor_release;
- s->s_config = mt9p012_sensor_config;
- mt9p012_probe_init_done(info);
-
-probe_done:
- CDBG("%s %s:%d\n", __FILE__, __func__, __LINE__);
- return rc;
-}
-
-static int __mt9p012_probe(struct platform_device *pdev)
-{
- return msm_camera_drv_start(pdev, mt9p012_sensor_probe);
-}
-
-static struct platform_driver msm_camera_driver = {
- .probe = __mt9p012_probe,
- .driver = {
- .name = "msm_camera_mt9p012",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init mt9p012_init(void)
-{
- return platform_driver_register(&msm_camera_driver);
-}
-
-module_init(mt9p012_init);
diff --git a/trunk/drivers/staging/dream/camera/mt9p012_reg.c b/trunk/drivers/staging/dream/camera/mt9p012_reg.c
deleted file mode 100644
index e5223d693b2c..000000000000
--- a/trunk/drivers/staging/dream/camera/mt9p012_reg.c
+++ /dev/null
@@ -1,573 +0,0 @@
-/*
- * Copyright (C) 2009 QUALCOMM Incorporated.
- */
-
-#include "mt9p012.h"
-#include
-
-/*Micron settings from Applications for lower power consumption.*/
-struct reg_struct mt9p012_reg_pat[2] = {
- { /* Preview */
- /* vt_pix_clk_div REG=0x0300 */
- 6, /* 5 */
-
- /* vt_sys_clk_div REG=0x0302 */
- 1,
-
- /* pre_pll_clk_div REG=0x0304 */
- 2,
-
- /* pll_multiplier REG=0x0306 */
- 60,
-
- /* op_pix_clk_div REG=0x0308 */
- 8, /* 10 */
-
- /* op_sys_clk_div REG=0x030A */
- 1,
-
- /* scale_m REG=0x0404 */
- 16,
-
- /* row_speed REG=0x3016 */
- 0x0111,
-
- /* x_addr_start REG=0x3004 */
- 8,
-
- /* x_addr_end REG=0x3008 */
- 2597,
-
- /* y_addr_start REG=0x3002 */
- 8,
-
- /* y_addr_end REG=0x3006 */
- 1949,
-
- /* read_mode REG=0x3040
- * Preview 2x2 skipping */
- 0x00C3,
-
- /* x_output_size REG=0x034C */
- 1296,
-
- /* y_output_size REG=0x034E */
- 972,
-
- /* line_length_pck REG=0x300C */
- 3784,
-
- /* frame_length_lines REG=0x300A */
- 1057,
-
- /* coarse_integration_time REG=0x3012 */
- 16,
-
- /* fine_integration_time REG=0x3014 */
- 1764
- },
- { /*Snapshot*/
- /* vt_pix_clk_div REG=0x0300 */
- 6,
-
- /* vt_sys_clk_div REG=0x0302 */
- 1,
-
- /* pre_pll_clk_div REG=0x0304 */
- 2,
-
- /* pll_multiplier REG=0x0306
- * 60 for 10fps snapshot */
- 60,
-
- /* op_pix_clk_div REG=0x0308 */
- 8,
-
- /* op_sys_clk_div REG=0x030A */
- 1,
-
- /* scale_m REG=0x0404 */
- 16,
-
- /* row_speed REG=0x3016 */
- 0x0111,
-
- /* x_addr_start REG=0x3004 */
- 8,
-
- /* x_addr_end REG=0x3008 */
- 2615,
-
- /* y_addr_start REG=0x3002 */
- 8,
-
- /* y_addr_end REG=0x3006 */
- 1967,
-
- /* read_mode REG=0x3040 */
- 0x0041,
-
- /* x_output_size REG=0x034C */
- 2608,
-
- /* y_output_size REG=0x034E */
- 1960,
-
- /* line_length_pck REG=0x300C */
- 3911,
-
- /* frame_length_lines REG=0x300A //10 fps snapshot */
- 2045,
-
- /* coarse_integration_time REG=0x3012 */
- 16,
-
- /* fine_integration_time REG=0x3014 */
- 882
- }
-};
-
-
-struct mt9p012_i2c_reg_conf mt9p012_test_tbl[] = {
- {0x3044, 0x0544 & 0xFBFF},
- {0x30CA, 0x0004 | 0x0001},
- {0x30D4, 0x9020 & 0x7FFF},
- {0x31E0, 0x0003 & 0xFFFE},
- {0x3180, 0x91FF & 0x7FFF},
- {0x301A, (0x10CC | 0x8000) & 0xFFF7},
- {0x301E, 0x0000},
- {0x3780, 0x0000},
-};
-
-
-struct mt9p012_i2c_reg_conf mt9p012_lc_tbl[] = {
- /* [Lens shading 85 Percent TL84] */
- /* P_RD_P0Q0 */
- {0x360A, 0x7FEF},
- /* P_RD_P0Q1 */
- {0x360C, 0x232C},
- /* P_RD_P0Q2 */
- {0x360E, 0x7050},
- /* P_RD_P0Q3 */
- {0x3610, 0xF3CC},
- /* P_RD_P0Q4 */
- {0x3612, 0x89D1},
- /* P_RD_P1Q0 */
- {0x364A, 0xBE0D},
- /* P_RD_P1Q1 */
- {0x364C, 0x9ACB},
- /* P_RD_P1Q2 */
- {0x364E, 0x2150},
- /* P_RD_P1Q3 */
- {0x3650, 0xB26B},
- /* P_RD_P1Q4 */
- {0x3652, 0x9511},
- /* P_RD_P2Q0 */
- {0x368A, 0x2151},
- /* P_RD_P2Q1 */
- {0x368C, 0x00AD},
- /* P_RD_P2Q2 */
- {0x368E, 0x8334},
- /* P_RD_P2Q3 */
- {0x3690, 0x478E},
- /* P_RD_P2Q4 */
- {0x3692, 0x0515},
- /* P_RD_P3Q0 */
- {0x36CA, 0x0710},
- /* P_RD_P3Q1 */
- {0x36CC, 0x452D},
- /* P_RD_P3Q2 */
- {0x36CE, 0xF352},
- /* P_RD_P3Q3 */
- {0x36D0, 0x190F},
- /* P_RD_P3Q4 */
- {0x36D2, 0x4413},
- /* P_RD_P4Q0 */
- {0x370A, 0xD112},
- /* P_RD_P4Q1 */
- {0x370C, 0xF50F},
- /* P_RD_P4Q2 */
- {0x370C, 0xF50F},
- /* P_RD_P4Q3 */
- {0x3710, 0xDC11},
- /* P_RD_P4Q4 */
- {0x3712, 0xD776},
- /* P_GR_P0Q0 */
- {0x3600, 0x1750},
- /* P_GR_P0Q1 */
- {0x3602, 0xF0AC},
- /* P_GR_P0Q2 */
- {0x3604, 0x4711},
- /* P_GR_P0Q3 */
- {0x3606, 0x07CE},
- /* P_GR_P0Q4 */
- {0x3608, 0x96B2},
- /* P_GR_P1Q0 */
- {0x3640, 0xA9AE},
- /* P_GR_P1Q1 */
- {0x3642, 0xF9AC},
- /* P_GR_P1Q2 */
- {0x3644, 0x39F1},
- /* P_GR_P1Q3 */
- {0x3646, 0x016F},
- /* P_GR_P1Q4 */
- {0x3648, 0x8AB2},
- /* P_GR_P2Q0 */
- {0x3680, 0x1752},
- /* P_GR_P2Q1 */
- {0x3682, 0x70F0},
- /* P_GR_P2Q2 */
- {0x3684, 0x83F5},
- /* P_GR_P2Q3 */
- {0x3686, 0x8392},
- /* P_GR_P2Q4 */
- {0x3688, 0x1FD6},
- /* P_GR_P3Q0 */
- {0x36C0, 0x1131},
- /* P_GR_P3Q1 */
- {0x36C2, 0x3DAF},
- /* P_GR_P3Q2 */
- {0x36C4, 0x89B4},
- /* P_GR_P3Q3 */
- {0x36C6, 0xA391},
- /* P_GR_P3Q4 */
- {0x36C8, 0x1334},
- /* P_GR_P4Q0 */
- {0x3700, 0xDC13},
- /* P_GR_P4Q1 */
- {0x3702, 0xD052},
- /* P_GR_P4Q2 */
- {0x3704, 0x5156},
- /* P_GR_P4Q3 */
- {0x3706, 0x1F13},
- /* P_GR_P4Q4 */
- {0x3708, 0x8C38},
- /* P_BL_P0Q0 */
- {0x3614, 0x0050},
- /* P_BL_P0Q1 */
- {0x3616, 0xBD4C},
- /* P_BL_P0Q2 */
- {0x3618, 0x41B0},
- /* P_BL_P0Q3 */
- {0x361A, 0x660D},
- /* P_BL_P0Q4 */
- {0x361C, 0xC590},
- /* P_BL_P1Q0 */
- {0x3654, 0x87EC},
- /* P_BL_P1Q1 */
- {0x3656, 0xE44C},
- /* P_BL_P1Q2 */
- {0x3658, 0x302E},
- /* P_BL_P1Q3 */
- {0x365A, 0x106E},
- /* P_BL_P1Q4 */
- {0x365C, 0xB58E},
- /* P_BL_P2Q0 */
- {0x3694, 0x0DD1},
- /* P_BL_P2Q1 */
- {0x3696, 0x2A50},
- /* P_BL_P2Q2 */
- {0x3698, 0xC793},
- /* P_BL_P2Q3 */
- {0x369A, 0xE8F1},
- /* P_BL_P2Q4 */
- {0x369C, 0x4174},
- /* P_BL_P3Q0 */
- {0x36D4, 0x01EF},
- /* P_BL_P3Q1 */
- {0x36D6, 0x06CF},
- /* P_BL_P3Q2 */
- {0x36D8, 0x8D91},
- /* P_BL_P3Q3 */
- {0x36DA, 0x91F0},
- /* P_BL_P3Q4 */
- {0x36DC, 0x52EF},
- /* P_BL_P4Q0 */
- {0x3714, 0xA6D2},
- /* P_BL_P4Q1 */
- {0x3716, 0xA312},
- /* P_BL_P4Q2 */
- {0x3718, 0x2695},
- /* P_BL_P4Q3 */
- {0x371A, 0x3953},
- /* P_BL_P4Q4 */
- {0x371C, 0x9356},
- /* P_GB_P0Q0 */
- {0x361E, 0x7EAF},
- /* P_GB_P0Q1 */
- {0x3620, 0x2A4C},
- /* P_GB_P0Q2 */
- {0x3622, 0x49F0},
- {0x3624, 0xF1EC},
- /* P_GB_P0Q4 */
- {0x3626, 0xC670},
- /* P_GB_P1Q0 */
- {0x365E, 0x8E0C},
- /* P_GB_P1Q1 */
- {0x3660, 0xC2A9},
- /* P_GB_P1Q2 */
- {0x3662, 0x274F},
- /* P_GB_P1Q3 */
- {0x3664, 0xADAB},
- /* P_GB_P1Q4 */
- {0x3666, 0x8EF0},
- /* P_GB_P2Q0 */
- {0x369E, 0x09B1},
- /* P_GB_P2Q1 */
- {0x36A0, 0xAA2E},
- /* P_GB_P2Q2 */
- {0x36A2, 0xC3D3},
- /* P_GB_P2Q3 */
- {0x36A4, 0x7FAF},
- /* P_GB_P2Q4 */
- {0x36A6, 0x3F34},
- /* P_GB_P3Q0 */
- {0x36DE, 0x4C8F},
- /* P_GB_P3Q1 */
- {0x36E0, 0x886E},
- /* P_GB_P3Q2 */
- {0x36E2, 0xE831},
- /* P_GB_P3Q3 */
- {0x36E4, 0x1FD0},
- /* P_GB_P3Q4 */
- {0x36E6, 0x1192},
- /* P_GB_P4Q0 */
- {0x371E, 0xB952},
- /* P_GB_P4Q1 */
- {0x3720, 0x6DCF},
- /* P_GB_P4Q2 */
- {0x3722, 0x1B55},
- /* P_GB_P4Q3 */
- {0x3724, 0xA112},
- /* P_GB_P4Q4 */
- {0x3726, 0x82F6},
- /* POLY_ORIGIN_C */
- {0x3782, 0x0510},
- /* POLY_ORIGIN_R */
- {0x3784, 0x0390},
- /* POLY_SC_ENABLE */
- {0x3780, 0x8000},
-};
-
-/* rolloff table for illuminant A */
-struct mt9p012_i2c_reg_conf mt9p012_rolloff_tbl[] = {
- /* P_RD_P0Q0 */
- {0x360A, 0x7FEF},
- /* P_RD_P0Q1 */
- {0x360C, 0x232C},
- /* P_RD_P0Q2 */
- {0x360E, 0x7050},
- /* P_RD_P0Q3 */
- {0x3610, 0xF3CC},
- /* P_RD_P0Q4 */
- {0x3612, 0x89D1},
- /* P_RD_P1Q0 */
- {0x364A, 0xBE0D},
- /* P_RD_P1Q1 */
- {0x364C, 0x9ACB},
- /* P_RD_P1Q2 */
- {0x364E, 0x2150},
- /* P_RD_P1Q3 */
- {0x3650, 0xB26B},
- /* P_RD_P1Q4 */
- {0x3652, 0x9511},
- /* P_RD_P2Q0 */
- {0x368A, 0x2151},
- /* P_RD_P2Q1 */
- {0x368C, 0x00AD},
- /* P_RD_P2Q2 */
- {0x368E, 0x8334},
- /* P_RD_P2Q3 */
- {0x3690, 0x478E},
- /* P_RD_P2Q4 */
- {0x3692, 0x0515},
- /* P_RD_P3Q0 */
- {0x36CA, 0x0710},
- /* P_RD_P3Q1 */
- {0x36CC, 0x452D},
- /* P_RD_P3Q2 */
- {0x36CE, 0xF352},
- /* P_RD_P3Q3 */
- {0x36D0, 0x190F},
- /* P_RD_P3Q4 */
- {0x36D2, 0x4413},
- /* P_RD_P4Q0 */
- {0x370A, 0xD112},
- /* P_RD_P4Q1 */
- {0x370C, 0xF50F},
- /* P_RD_P4Q2 */
- {0x370E, 0x6375},
- /* P_RD_P4Q3 */
- {0x3710, 0xDC11},
- /* P_RD_P4Q4 */
- {0x3712, 0xD776},
- /* P_GR_P0Q0 */
- {0x3600, 0x1750},
- /* P_GR_P0Q1 */
- {0x3602, 0xF0AC},
- /* P_GR_P0Q2 */
- {0x3604, 0x4711},
- /* P_GR_P0Q3 */
- {0x3606, 0x07CE},
- /* P_GR_P0Q4 */
- {0x3608, 0x96B2},
- /* P_GR_P1Q0 */
- {0x3640, 0xA9AE},
- /* P_GR_P1Q1 */
- {0x3642, 0xF9AC},
- /* P_GR_P1Q2 */
- {0x3644, 0x39F1},
- /* P_GR_P1Q3 */
- {0x3646, 0x016F},
- /* P_GR_P1Q4 */
- {0x3648, 0x8AB2},
- /* P_GR_P2Q0 */
- {0x3680, 0x1752},
- /* P_GR_P2Q1 */
- {0x3682, 0x70F0},
- /* P_GR_P2Q2 */
- {0x3684, 0x83F5},
- /* P_GR_P2Q3 */
- {0x3686, 0x8392},
- /* P_GR_P2Q4 */
- {0x3688, 0x1FD6},
- /* P_GR_P3Q0 */
- {0x36C0, 0x1131},
- /* P_GR_P3Q1 */
- {0x36C2, 0x3DAF},
- /* P_GR_P3Q2 */
- {0x36C4, 0x89B4},
- /* P_GR_P3Q3 */
- {0x36C6, 0xA391},
- /* P_GR_P3Q4 */
- {0x36C8, 0x1334},
- /* P_GR_P4Q0 */
- {0x3700, 0xDC13},
- /* P_GR_P4Q1 */
- {0x3702, 0xD052},
- /* P_GR_P4Q2 */
- {0x3704, 0x5156},
- /* P_GR_P4Q3 */
- {0x3706, 0x1F13},
- /* P_GR_P4Q4 */
- {0x3708, 0x8C38},
- /* P_BL_P0Q0 */
- {0x3614, 0x0050},
- /* P_BL_P0Q1 */
- {0x3616, 0xBD4C},
- /* P_BL_P0Q2 */
- {0x3618, 0x41B0},
- /* P_BL_P0Q3 */
- {0x361A, 0x660D},
- /* P_BL_P0Q4 */
- {0x361C, 0xC590},
- /* P_BL_P1Q0 */
- {0x3654, 0x87EC},
- /* P_BL_P1Q1 */
- {0x3656, 0xE44C},
- /* P_BL_P1Q2 */
- {0x3658, 0x302E},
- /* P_BL_P1Q3 */
- {0x365A, 0x106E},
- /* P_BL_P1Q4 */
- {0x365C, 0xB58E},
- /* P_BL_P2Q0 */
- {0x3694, 0x0DD1},
- /* P_BL_P2Q1 */
- {0x3696, 0x2A50},
- /* P_BL_P2Q2 */
- {0x3698, 0xC793},
- /* P_BL_P2Q3 */
- {0x369A, 0xE8F1},
- /* P_BL_P2Q4 */
- {0x369C, 0x4174},
- /* P_BL_P3Q0 */
- {0x36D4, 0x01EF},
- /* P_BL_P3Q1 */
- {0x36D6, 0x06CF},
- /* P_BL_P3Q2 */
- {0x36D8, 0x8D91},
- /* P_BL_P3Q3 */
- {0x36DA, 0x91F0},
- /* P_BL_P3Q4 */
- {0x36DC, 0x52EF},
- /* P_BL_P4Q0 */
- {0x3714, 0xA6D2},
- /* P_BL_P4Q1 */
- {0x3716, 0xA312},
- /* P_BL_P4Q2 */
- {0x3718, 0x2695},
- /* P_BL_P4Q3 */
- {0x371A, 0x3953},
- /* P_BL_P4Q4 */
- {0x371C, 0x9356},
- /* P_GB_P0Q0 */
- {0x361E, 0x7EAF},
- /* P_GB_P0Q1 */
- {0x3620, 0x2A4C},
- /* P_GB_P0Q2 */
- {0x3622, 0x49F0},
- {0x3624, 0xF1EC},
- /* P_GB_P0Q4 */
- {0x3626, 0xC670},
- /* P_GB_P1Q0 */
- {0x365E, 0x8E0C},
- /* P_GB_P1Q1 */
- {0x3660, 0xC2A9},
- /* P_GB_P1Q2 */
- {0x3662, 0x274F},
- /* P_GB_P1Q3 */
- {0x3664, 0xADAB},
- /* P_GB_P1Q4 */
- {0x3666, 0x8EF0},
- /* P_GB_P2Q0 */
- {0x369E, 0x09B1},
- /* P_GB_P2Q1 */
- {0x36A0, 0xAA2E},
- /* P_GB_P2Q2 */
- {0x36A2, 0xC3D3},
- /* P_GB_P2Q3 */
- {0x36A4, 0x7FAF},
- /* P_GB_P2Q4 */
- {0x36A6, 0x3F34},
- /* P_GB_P3Q0 */
- {0x36DE, 0x4C8F},
- /* P_GB_P3Q1 */
- {0x36E0, 0x886E},
- /* P_GB_P3Q2 */
- {0x36E2, 0xE831},
- /* P_GB_P3Q3 */
- {0x36E4, 0x1FD0},
- /* P_GB_P3Q4 */
- {0x36E6, 0x1192},
- /* P_GB_P4Q0 */
- {0x371E, 0xB952},
- /* P_GB_P4Q1 */
- {0x3720, 0x6DCF},
- /* P_GB_P4Q2 */
- {0x3722, 0x1B55},
- /* P_GB_P4Q3 */
- {0x3724, 0xA112},
- /* P_GB_P4Q4 */
- {0x3726, 0x82F6},
- /* POLY_ORIGIN_C */
- {0x3782, 0x0510},
- /* POLY_ORIGIN_R */
- {0x3784, 0x0390},
- /* POLY_SC_ENABLE */
- {0x3780, 0x8000},
-};
-
-
-struct mt9p012_reg mt9p012_regs = {
- .reg_pat = &mt9p012_reg_pat[0],
- .reg_pat_size = ARRAY_SIZE(mt9p012_reg_pat),
- .ttbl = &mt9p012_test_tbl[0],
- .ttbl_size = ARRAY_SIZE(mt9p012_test_tbl),
- .lctbl = &mt9p012_lc_tbl[0],
- .lctbl_size = ARRAY_SIZE(mt9p012_lc_tbl),
- .rftbl = &mt9p012_rolloff_tbl[0],
- .rftbl_size = ARRAY_SIZE(mt9p012_rolloff_tbl)
-};
-
-
diff --git a/trunk/drivers/staging/dream/camera/mt9t013.c b/trunk/drivers/staging/dream/camera/mt9t013.c
deleted file mode 100644
index 8fd7727ba234..000000000000
--- a/trunk/drivers/staging/dream/camera/mt9t013.c
+++ /dev/null
@@ -1,1497 +0,0 @@
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include "mt9t013.h"
-
-/*=============================================================
- SENSOR REGISTER DEFINES
-==============================================================*/
-#define MT9T013_REG_MODEL_ID 0x0000
-#define MT9T013_MODEL_ID 0x2600
-#define REG_GROUPED_PARAMETER_HOLD 0x0104
-#define GROUPED_PARAMETER_HOLD 0x0100
-#define GROUPED_PARAMETER_UPDATE 0x0000
-#define REG_COARSE_INT_TIME 0x3012
-#define REG_VT_PIX_CLK_DIV 0x0300
-#define REG_VT_SYS_CLK_DIV 0x0302
-#define REG_PRE_PLL_CLK_DIV 0x0304
-#define REG_PLL_MULTIPLIER 0x0306
-#define REG_OP_PIX_CLK_DIV 0x0308
-#define REG_OP_SYS_CLK_DIV 0x030A
-#define REG_SCALE_M 0x0404
-#define REG_FRAME_LENGTH_LINES 0x300A
-#define REG_LINE_LENGTH_PCK 0x300C
-#define REG_X_ADDR_START 0x3004
-#define REG_Y_ADDR_START 0x3002
-#define REG_X_ADDR_END 0x3008
-#define REG_Y_ADDR_END 0x3006
-#define REG_X_OUTPUT_SIZE 0x034C
-#define REG_Y_OUTPUT_SIZE 0x034E
-#define REG_FINE_INT_TIME 0x3014
-#define REG_ROW_SPEED 0x3016
-#define MT9T013_REG_RESET_REGISTER 0x301A
-#define MT9T013_RESET_REGISTER_PWON 0x10CC
-#define MT9T013_RESET_REGISTER_PWOFF 0x1008 /* 0x10C8 stop streaming*/
-#define REG_READ_MODE 0x3040
-#define REG_GLOBAL_GAIN 0x305E
-#define REG_TEST_PATTERN_MODE 0x3070
-
-
-enum mt9t013_test_mode {
- TEST_OFF,
- TEST_1,
- TEST_2,
- TEST_3
-};
-
-enum mt9t013_resolution {
- QTR_SIZE,
- FULL_SIZE,
- INVALID_SIZE
-};
-
-enum mt9t013_reg_update {
- REG_INIT, /* registers that need to be updated during initialization */
- UPDATE_PERIODIC, /* registers that needs periodic I2C writes */
- UPDATE_ALL, /* all registers will be updated */
- UPDATE_INVALID
-};
-
-enum mt9t013_setting {
- RES_PREVIEW,
- RES_CAPTURE
-};
-
-/* actuator's Slave Address */
-#define MT9T013_AF_I2C_ADDR 0x18
-
-/*
-* AF Total steps parameters
-*/
-#define MT9T013_TOTAL_STEPS_NEAR_TO_FAR 30
-
-/*
- * Time in milisecs for waiting for the sensor to reset.
- */
-#define MT9T013_RESET_DELAY_MSECS 66
-
-/* for 30 fps preview */
-#define MT9T013_DEFAULT_CLOCK_RATE 24000000
-#define MT9T013_DEFAULT_MAX_FPS 26
-
-
-/* FIXME: Changes from here */
-struct mt9t013_work {
- struct work_struct work;
-};
-
-static struct mt9t013_work *mt9t013_sensorw;
-static struct i2c_client *mt9t013_client;
-
-struct mt9t013_ctrl {
- const struct msm_camera_sensor_info *sensordata;
-
- int sensormode;
- uint32_t fps_divider; /* init to 1 * 0x00000400 */
- uint32_t pict_fps_divider; /* init to 1 * 0x00000400 */
-
- uint16_t curr_lens_pos;
- uint16_t init_curr_lens_pos;
- uint16_t my_reg_gain;
- uint32_t my_reg_line_count;
-
- enum mt9t013_resolution prev_res;
- enum mt9t013_resolution pict_res;
- enum mt9t013_resolution curr_res;
- enum mt9t013_test_mode set_test;
-
- unsigned short imgaddr;
-};
-
-
-static struct mt9t013_ctrl *mt9t013_ctrl;
-static DECLARE_WAIT_QUEUE_HEAD(mt9t013_wait_queue);
-DECLARE_MUTEX(mt9t013_sem);
-
-extern struct mt9t013_reg mt9t013_regs; /* from mt9t013_reg.c */
-
-static int mt9t013_i2c_rxdata(unsigned short saddr,
- unsigned char *rxdata, int length)
-{
- struct i2c_msg msgs[] = {
- {
- .addr = saddr,
- .flags = 0,
- .len = 2,
- .buf = rxdata,
- },
- {
- .addr = saddr,
- .flags = I2C_M_RD,
- .len = length,
- .buf = rxdata,
- },
- };
-
- if (i2c_transfer(mt9t013_client->adapter, msgs, 2) < 0) {
- pr_err("mt9t013_i2c_rxdata failed!\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int32_t mt9t013_i2c_read_w(unsigned short saddr,
- unsigned short raddr, unsigned short *rdata)
-{
- int32_t rc = 0;
- unsigned char buf[4];
-
- if (!rdata)
- return -EIO;
-
- memset(buf, 0, sizeof(buf));
-
- buf[0] = (raddr & 0xFF00)>>8;
- buf[1] = (raddr & 0x00FF);
-
- rc = mt9t013_i2c_rxdata(saddr, buf, 2);
- if (rc < 0)
- return rc;
-
- *rdata = buf[0] << 8 | buf[1];
-
- if (rc < 0)
- pr_err("mt9t013_i2c_read failed!\n");
-
- return rc;
-}
-
-static int32_t mt9t013_i2c_txdata(unsigned short saddr,
- unsigned char *txdata, int length)
-{
- struct i2c_msg msg[] = {
- {
- .addr = saddr,
- .flags = 0,
- .len = length,
- .buf = txdata,
- },
- };
-
- if (i2c_transfer(mt9t013_client->adapter, msg, 1) < 0) {
- pr_err("mt9t013_i2c_txdata failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int32_t mt9t013_i2c_write_b(unsigned short saddr,
- unsigned short waddr, unsigned short wdata)
-{
- int32_t rc = -EIO;
- unsigned char buf[2];
-
- memset(buf, 0, sizeof(buf));
- buf[0] = waddr;
- buf[1] = wdata;
- rc = mt9t013_i2c_txdata(saddr, buf, 2);
-
- if (rc < 0)
- pr_err("i2c_write failed, addr = 0x%x, val = 0x%x!\n",
- waddr, wdata);
-
- return rc;
-}
-
-static int32_t mt9t013_i2c_write_w(unsigned short saddr,
- unsigned short waddr, unsigned short wdata)
-{
- int32_t rc = -EIO;
- unsigned char buf[4];
-
- memset(buf, 0, sizeof(buf));
- buf[0] = (waddr & 0xFF00)>>8;
- buf[1] = (waddr & 0x00FF);
- buf[2] = (wdata & 0xFF00)>>8;
- buf[3] = (wdata & 0x00FF);
-
- rc = mt9t013_i2c_txdata(saddr, buf, 4);
-
- if (rc < 0)
- pr_err("i2c_write_w failed, addr = 0x%x, val = 0x%x!\n",
- waddr, wdata);
-
- return rc;
-}
-
-static int32_t mt9t013_i2c_write_w_table(
- struct mt9t013_i2c_reg_conf *reg_conf_tbl, int num_of_items_in_table)
-{
- int i;
- int32_t rc = -EIO;
-
- for (i = 0; i < num_of_items_in_table; i++) {
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- reg_conf_tbl->waddr, reg_conf_tbl->wdata);
- if (rc < 0)
- break;
- reg_conf_tbl++;
- }
-
- return rc;
-}
-
-static int32_t mt9t013_test(enum mt9t013_test_mode mo)
-{
- int32_t rc = 0;
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return rc;
-
- if (mo == TEST_OFF)
- return 0;
- else {
- rc = mt9t013_i2c_write_w_table(mt9t013_regs.ttbl,
- mt9t013_regs.ttbl_size);
- if (rc < 0)
- return rc;
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_TEST_PATTERN_MODE, (uint16_t)mo);
- if (rc < 0)
- return rc;
- }
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
- if (rc < 0)
- return rc;
-
- return rc;
-}
-
-static int32_t mt9t013_set_lc(void)
-{
- int32_t rc;
-
- rc = mt9t013_i2c_write_w_table(mt9t013_regs.lctbl, mt9t013_regs.lctbl_size);
- if (rc < 0)
- return rc;
-
- return rc;
-}
-
-static int32_t mt9t013_set_default_focus(uint8_t af_step)
-{
- int32_t rc = 0;
- uint8_t code_val_msb, code_val_lsb;
- code_val_msb = 0x01;
- code_val_lsb = af_step;
-
- /* Write the digital code for current to the actuator */
- rc = mt9t013_i2c_write_b(MT9T013_AF_I2C_ADDR>>1,
- code_val_msb, code_val_lsb);
-
- mt9t013_ctrl->curr_lens_pos = 0;
- mt9t013_ctrl->init_curr_lens_pos = 0;
- return rc;
-}
-
-static void mt9t013_get_pict_fps(uint16_t fps, uint16_t *pfps)
-{
- /* input fps is preview fps in Q8 format */
- uint32_t divider; /*Q10 */
- uint32_t pclk_mult; /*Q10 */
-
- if (mt9t013_ctrl->prev_res == QTR_SIZE) {
- divider =
- (uint32_t)(
- ((mt9t013_regs.reg_pat[RES_PREVIEW].frame_length_lines *
- mt9t013_regs.reg_pat[RES_PREVIEW].line_length_pck) *
- 0x00000400) /
- (mt9t013_regs.reg_pat[RES_CAPTURE].frame_length_lines *
- mt9t013_regs.reg_pat[RES_CAPTURE].line_length_pck));
-
- pclk_mult =
- (uint32_t) ((mt9t013_regs.reg_pat[RES_CAPTURE].pll_multiplier *
- 0x00000400) /
- (mt9t013_regs.reg_pat[RES_PREVIEW].pll_multiplier));
-
- } else {
- /* full size resolution used for preview. */
- divider = 0x00000400; /*1.0 */
- pclk_mult = 0x00000400; /*1.0 */
- }
-
- /* Verify PCLK settings and frame sizes. */
- *pfps =
- (uint16_t) (fps * divider * pclk_mult /
- 0x00000400 / 0x00000400);
-}
-
-static uint16_t mt9t013_get_prev_lines_pf(void)
-{
- if (mt9t013_ctrl->prev_res == QTR_SIZE)
- return mt9t013_regs.reg_pat[RES_PREVIEW].frame_length_lines;
- else
- return mt9t013_regs.reg_pat[RES_CAPTURE].frame_length_lines;
-}
-
-static uint16_t mt9t013_get_prev_pixels_pl(void)
-{
- if (mt9t013_ctrl->prev_res == QTR_SIZE)
- return mt9t013_regs.reg_pat[RES_PREVIEW].line_length_pck;
- else
- return mt9t013_regs.reg_pat[RES_CAPTURE].line_length_pck;
-}
-
-static uint16_t mt9t013_get_pict_lines_pf(void)
-{
- return mt9t013_regs.reg_pat[RES_CAPTURE].frame_length_lines;
-}
-
-static uint16_t mt9t013_get_pict_pixels_pl(void)
-{
- return mt9t013_regs.reg_pat[RES_CAPTURE].line_length_pck;
-}
-
-static uint32_t mt9t013_get_pict_max_exp_lc(void)
-{
- uint16_t snapshot_lines_per_frame;
-
- if (mt9t013_ctrl->pict_res == QTR_SIZE) {
- snapshot_lines_per_frame =
- mt9t013_regs.reg_pat[RES_PREVIEW].frame_length_lines - 1;
- } else {
- snapshot_lines_per_frame =
- mt9t013_regs.reg_pat[RES_CAPTURE].frame_length_lines - 1;
- }
-
- return snapshot_lines_per_frame * 24;
-}
-
-static int32_t mt9t013_set_fps(struct fps_cfg *fps)
-{
- /* input is new fps in Q8 format */
- int32_t rc = 0;
-
- mt9t013_ctrl->fps_divider = fps->fps_div;
- mt9t013_ctrl->pict_fps_divider = fps->pict_fps_div;
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return -EBUSY;
-
- CDBG("mt9t013_set_fps: fps_div is %d, frame_rate is %d\n",
- fps->fps_div,
- (uint16_t) (mt9t013_regs.reg_pat[RES_PREVIEW].
- frame_length_lines *
- fps->fps_div/0x00000400));
-
- CDBG("mt9t013_set_fps: fps_mult is %d, frame_rate is %d\n",
- fps->f_mult,
- (uint16_t)(mt9t013_regs.reg_pat[RES_PREVIEW].
- line_length_pck *
- fps->f_mult / 0x00000400));
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_LINE_LENGTH_PCK,
- (uint16_t) (
- mt9t013_regs.reg_pat[RES_PREVIEW].line_length_pck *
- fps->f_mult / 0x00000400));
- if (rc < 0)
- return rc;
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
- if (rc < 0)
- return rc;
-
- return rc;
-}
-
-static int32_t mt9t013_write_exp_gain(uint16_t gain, uint32_t line)
-{
- const uint16_t max_legal_gain = 0x01FF;
- uint32_t line_length_ratio = 0x00000400;
- enum mt9t013_setting setting;
- int32_t rc = 0;
-
- if (mt9t013_ctrl->sensormode == SENSOR_PREVIEW_MODE) {
- mt9t013_ctrl->my_reg_gain = gain;
- mt9t013_ctrl->my_reg_line_count = (uint16_t) line;
- }
-
- if (gain > max_legal_gain)
- gain = max_legal_gain;
-
- /* Verify no overflow */
- if (mt9t013_ctrl->sensormode != SENSOR_SNAPSHOT_MODE) {
- line = (uint32_t) (line * mt9t013_ctrl->fps_divider /
- 0x00000400);
-
- setting = RES_PREVIEW;
-
- } else {
- line = (uint32_t) (line * mt9t013_ctrl->pict_fps_divider /
- 0x00000400);
-
- setting = RES_CAPTURE;
- }
-
- /*Set digital gain to 1 */
- gain |= 0x0200;
-
- if ((mt9t013_regs.reg_pat[setting].frame_length_lines - 1) < line) {
-
- line_length_ratio =
- (uint32_t) (line * 0x00000400) /
- (mt9t013_regs.reg_pat[setting].frame_length_lines - 1);
- } else
- line_length_ratio = 0x00000400;
-
- /* There used to be PARAMETER_HOLD register write before and
- * after REG_GLOBAL_GAIN & REG_COARSE_INIT_TIME. This causes
- * aec oscillation. Hence removed. */
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr, REG_GLOBAL_GAIN, gain);
- if (rc < 0)
- return rc;
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_COARSE_INT_TIME,
- (uint16_t)((uint32_t) line * 0x00000400 /
- line_length_ratio));
- if (rc < 0)
- return rc;
-
- return rc;
-}
-
-static int32_t mt9t013_set_pict_exp_gain(uint16_t gain, uint32_t line)
-{
- int32_t rc = 0;
-
- rc = mt9t013_write_exp_gain(gain, line);
- if (rc < 0)
- return rc;
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- MT9T013_REG_RESET_REGISTER,
- 0x10CC | 0x0002);
-
- mdelay(5);
-
- /* camera_timed_wait(snapshot_wait*exposure_ratio); */
- return rc;
-}
-
-static int32_t mt9t013_setting(enum mt9t013_reg_update rupdate,
- enum mt9t013_setting rt)
-{
- int32_t rc = 0;
-
- switch (rupdate) {
- case UPDATE_PERIODIC: {
-
- if (rt == RES_PREVIEW || rt == RES_CAPTURE) {
-#if 0
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- MT9T013_REG_RESET_REGISTER,
- MT9T013_RESET_REGISTER_PWOFF);
- if (rc < 0)
- return rc;
-#endif
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_VT_PIX_CLK_DIV,
- mt9t013_regs.reg_pat[rt].vt_pix_clk_div);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_VT_SYS_CLK_DIV,
- mt9t013_regs.reg_pat[rt].vt_sys_clk_div);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_PRE_PLL_CLK_DIV,
- mt9t013_regs.reg_pat[rt].pre_pll_clk_div);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_PLL_MULTIPLIER,
- mt9t013_regs.reg_pat[rt].pll_multiplier);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_OP_PIX_CLK_DIV,
- mt9t013_regs.reg_pat[rt].op_pix_clk_div);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_OP_SYS_CLK_DIV,
- mt9t013_regs.reg_pat[rt].op_sys_clk_div);
- if (rc < 0)
- return rc;
-
- mdelay(5);
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_ROW_SPEED,
- mt9t013_regs.reg_pat[rt].row_speed);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_X_ADDR_START,
- mt9t013_regs.reg_pat[rt].x_addr_start);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_X_ADDR_END,
- mt9t013_regs.reg_pat[rt].x_addr_end);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_Y_ADDR_START,
- mt9t013_regs.reg_pat[rt].y_addr_start);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_Y_ADDR_END,
- mt9t013_regs.reg_pat[rt].y_addr_end);
- if (rc < 0)
- return rc;
-
- if (machine_is_sapphire()) {
- if (rt == 0)
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_READ_MODE,
- 0x046F);
- else
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_READ_MODE,
- 0x0027);
- } else
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_READ_MODE,
- mt9t013_regs.reg_pat[rt].read_mode);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_SCALE_M,
- mt9t013_regs.reg_pat[rt].scale_m);
- if (rc < 0)
- return rc;
-
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_X_OUTPUT_SIZE,
- mt9t013_regs.reg_pat[rt].x_output_size);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_Y_OUTPUT_SIZE,
- mt9t013_regs.reg_pat[rt].y_output_size);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_LINE_LENGTH_PCK,
- mt9t013_regs.reg_pat[rt].line_length_pck);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_FRAME_LENGTH_LINES,
- (mt9t013_regs.reg_pat[rt].frame_length_lines *
- mt9t013_ctrl->fps_divider / 0x00000400));
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_COARSE_INT_TIME,
- mt9t013_regs.reg_pat[rt].coarse_int_time);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_FINE_INT_TIME,
- mt9t013_regs.reg_pat[rt].fine_int_time);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
- if (rc < 0)
- return rc;
-
- rc = mt9t013_test(mt9t013_ctrl->set_test);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- MT9T013_REG_RESET_REGISTER,
- MT9T013_RESET_REGISTER_PWON);
- if (rc < 0)
- return rc;
-
- mdelay(5);
-
- return rc;
- }
- }
- break;
-
- /*CAMSENSOR_REG_UPDATE_PERIODIC */
- case REG_INIT: {
- if (rt == RES_PREVIEW || rt == RES_CAPTURE) {
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- MT9T013_REG_RESET_REGISTER,
- MT9T013_RESET_REGISTER_PWOFF);
- if (rc < 0)
- /* MODE_SELECT, stop streaming */
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_VT_PIX_CLK_DIV,
- mt9t013_regs.reg_pat[rt].vt_pix_clk_div);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_VT_SYS_CLK_DIV,
- mt9t013_regs.reg_pat[rt].vt_sys_clk_div);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_PRE_PLL_CLK_DIV,
- mt9t013_regs.reg_pat[rt].pre_pll_clk_div);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_PLL_MULTIPLIER,
- mt9t013_regs.reg_pat[rt].pll_multiplier);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_OP_PIX_CLK_DIV,
- mt9t013_regs.reg_pat[rt].op_pix_clk_div);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_OP_SYS_CLK_DIV,
- mt9t013_regs.reg_pat[rt].op_sys_clk_div);
- if (rc < 0)
- return rc;
-
- mdelay(5);
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return rc;
-
- /* additional power saving mode ok around 38.2MHz */
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- 0x3084, 0x2409);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- 0x3092, 0x0A49);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- 0x3094, 0x4949);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- 0x3096, 0x4949);
- if (rc < 0)
- return rc;
-
- /* Set preview or snapshot mode */
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_ROW_SPEED,
- mt9t013_regs.reg_pat[rt].row_speed);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_X_ADDR_START,
- mt9t013_regs.reg_pat[rt].x_addr_start);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_X_ADDR_END,
- mt9t013_regs.reg_pat[rt].x_addr_end);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_Y_ADDR_START,
- mt9t013_regs.reg_pat[rt].y_addr_start);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_Y_ADDR_END,
- mt9t013_regs.reg_pat[rt].y_addr_end);
- if (rc < 0)
- return rc;
-
- if (machine_is_sapphire()) {
- if (rt == 0)
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_READ_MODE,
- 0x046F);
- else
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_READ_MODE,
- 0x0027);
- } else
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_READ_MODE,
- mt9t013_regs.reg_pat[rt].read_mode);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_SCALE_M,
- mt9t013_regs.reg_pat[rt].scale_m);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_X_OUTPUT_SIZE,
- mt9t013_regs.reg_pat[rt].x_output_size);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_Y_OUTPUT_SIZE,
- mt9t013_regs.reg_pat[rt].y_output_size);
- if (rc < 0)
- return 0;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_LINE_LENGTH_PCK,
- mt9t013_regs.reg_pat[rt].line_length_pck);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_FRAME_LENGTH_LINES,
- mt9t013_regs.reg_pat[rt].frame_length_lines);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_COARSE_INT_TIME,
- mt9t013_regs.reg_pat[rt].coarse_int_time);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_FINE_INT_TIME,
- mt9t013_regs.reg_pat[rt].fine_int_time);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
- if (rc < 0)
- return rc;
-
- /* load lens shading */
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return rc;
-
- /* most likely needs to be written only once. */
- rc = mt9t013_set_lc();
- if (rc < 0)
- return -EBUSY;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
- if (rc < 0)
- return rc;
-
- rc = mt9t013_test(mt9t013_ctrl->set_test);
- if (rc < 0)
- return rc;
-
- mdelay(5);
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- MT9T013_REG_RESET_REGISTER,
- MT9T013_RESET_REGISTER_PWON);
- if (rc < 0)
- /* MODE_SELECT, stop streaming */
- return rc;
-
- CDBG("!!! mt9t013 !!! PowerOn is done!\n");
- mdelay(5);
- return rc;
- }
- } /* case CAMSENSOR_REG_INIT: */
- break;
-
- /*CAMSENSOR_REG_INIT */
- default:
- rc = -EINVAL;
- break;
- } /* switch (rupdate) */
-
- return rc;
-}
-
-static int32_t mt9t013_video_config(int mode, int res)
-{
- int32_t rc;
-
- switch (res) {
- case QTR_SIZE:
- rc = mt9t013_setting(UPDATE_PERIODIC, RES_PREVIEW);
- if (rc < 0)
- return rc;
- CDBG("sensor configuration done!\n");
- break;
-
- case FULL_SIZE:
- rc = mt9t013_setting(UPDATE_PERIODIC, RES_CAPTURE);
- if (rc < 0)
- return rc;
- break;
-
- default:
- return -EINVAL;
- } /* switch */
-
- mt9t013_ctrl->prev_res = res;
- mt9t013_ctrl->curr_res = res;
- mt9t013_ctrl->sensormode = mode;
-
- return mt9t013_write_exp_gain(mt9t013_ctrl->my_reg_gain,
- mt9t013_ctrl->my_reg_line_count);
-}
-
-static int32_t mt9t013_snapshot_config(int mode)
-{
- int32_t rc = 0;
-
- rc = mt9t013_setting(UPDATE_PERIODIC, RES_CAPTURE);
- if (rc < 0)
- return rc;
-
- mt9t013_ctrl->curr_res = mt9t013_ctrl->pict_res;
- mt9t013_ctrl->sensormode = mode;
- return rc;
-}
-
-static int32_t mt9t013_raw_snapshot_config(int mode)
-{
- int32_t rc = 0;
-
- rc = mt9t013_setting(UPDATE_PERIODIC, RES_CAPTURE);
- if (rc < 0)
- return rc;
-
- mt9t013_ctrl->curr_res = mt9t013_ctrl->pict_res;
- mt9t013_ctrl->sensormode = mode;
- return rc;
-}
-
-static int32_t mt9t013_power_down(void)
-{
- int32_t rc = 0;
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- MT9T013_REG_RESET_REGISTER,
- MT9T013_RESET_REGISTER_PWOFF);
- if (rc >= 0)
- mdelay(5);
- return rc;
-}
-
-static int32_t mt9t013_move_focus(int direction, int32_t num_steps)
-{
- int16_t step_direction;
- int16_t actual_step;
- int16_t next_position;
- int16_t break_steps[4];
- uint8_t code_val_msb, code_val_lsb;
- int16_t i;
-
- if (num_steps > MT9T013_TOTAL_STEPS_NEAR_TO_FAR)
- num_steps = MT9T013_TOTAL_STEPS_NEAR_TO_FAR;
- else if (num_steps == 0)
- return -EINVAL;
-
- if (direction == MOVE_NEAR)
- step_direction = 4;
- else if (direction == MOVE_FAR)
- step_direction = -4;
- else
- return -EINVAL;
-
- if (mt9t013_ctrl->curr_lens_pos < mt9t013_ctrl->init_curr_lens_pos)
- mt9t013_ctrl->curr_lens_pos = mt9t013_ctrl->init_curr_lens_pos;
-
- actual_step =
- (int16_t) (step_direction *
- (int16_t) num_steps);
-
- for (i = 0; i < 4; i++)
- break_steps[i] =
- actual_step / 4 * (i + 1) - actual_step / 4 * i;
-
- for (i = 0; i < 4; i++) {
- next_position =
- (int16_t)
- (mt9t013_ctrl->curr_lens_pos + break_steps[i]);
-
- if (next_position > 255)
- next_position = 255;
- else if (next_position < 0)
- next_position = 0;
-
- code_val_msb =
- ((next_position >> 4) << 2) |
- ((next_position << 4) >> 6);
-
- code_val_lsb =
- ((next_position & 0x03) << 6);
-
- /* Writing the digital code for current to the actuator */
- if (mt9t013_i2c_write_b(MT9T013_AF_I2C_ADDR>>1,
- code_val_msb, code_val_lsb) < 0)
- return -EBUSY;
-
- /* Storing the current lens Position */
- mt9t013_ctrl->curr_lens_pos = next_position;
-
- if (i < 3)
- mdelay(1);
- } /* for */
-
- return 0;
-}
-
-static int mt9t013_sensor_init_done(const struct msm_camera_sensor_info *data)
-{
- gpio_direction_output(data->sensor_reset, 0);
- gpio_free(data->sensor_reset);
- return 0;
-}
-
-static int mt9t013_probe_init_sensor(const struct msm_camera_sensor_info *data)
-{
- int rc;
- uint16_t chipid;
-
- rc = gpio_request(data->sensor_reset, "mt9t013");
- if (!rc)
- gpio_direction_output(data->sensor_reset, 1);
- else
- goto init_probe_done;
-
- mdelay(20);
-
- /* RESET the sensor image part via I2C command */
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- MT9T013_REG_RESET_REGISTER, 0x1009);
- if (rc < 0)
- goto init_probe_fail;
-
- /* 3. Read sensor Model ID: */
- rc = mt9t013_i2c_read_w(mt9t013_client->addr,
- MT9T013_REG_MODEL_ID, &chipid);
-
- if (rc < 0)
- goto init_probe_fail;
-
- CDBG("mt9t013 model_id = 0x%x\n", chipid);
-
- /* 4. Compare sensor ID to MT9T012VC ID: */
- if (chipid != MT9T013_MODEL_ID) {
- rc = -ENODEV;
- goto init_probe_fail;
- }
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- 0x3064, 0x0805);
- if (rc < 0)
- goto init_probe_fail;
-
- mdelay(MT9T013_RESET_DELAY_MSECS);
-
- goto init_probe_done;
-
- /* sensor: output enable */
-#if 0
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- MT9T013_REG_RESET_REGISTER,
- MT9T013_RESET_REGISTER_PWON);
-
- /* if this fails, the sensor is not the MT9T013 */
- rc = mt9t013_set_default_focus(0);
-#endif
-
-init_probe_fail:
- gpio_direction_output(data->sensor_reset, 0);
- gpio_free(data->sensor_reset);
-init_probe_done:
- return rc;
-}
-
-static int32_t mt9t013_poweron_af(void)
-{
- int32_t rc = 0;
-
- /* enable AF actuator */
- CDBG("enable AF actuator, gpio = %d\n",
- mt9t013_ctrl->sensordata->vcm_pwd);
- rc = gpio_request(mt9t013_ctrl->sensordata->vcm_pwd, "mt9t013");
- if (!rc) {
- gpio_direction_output(mt9t013_ctrl->sensordata->vcm_pwd, 0);
- mdelay(20);
- rc = mt9t013_set_default_focus(0);
- } else
- pr_err("%s, gpio_request failed (%d)!\n", __func__, rc);
- return rc;
-}
-
-static void mt9t013_poweroff_af(void)
-{
- gpio_direction_output(mt9t013_ctrl->sensordata->vcm_pwd, 1);
- gpio_free(mt9t013_ctrl->sensordata->vcm_pwd);
-}
-
-int mt9t013_sensor_open_init(const struct msm_camera_sensor_info *data)
-{
- int32_t rc;
-
- mt9t013_ctrl = kzalloc(sizeof(struct mt9t013_ctrl), GFP_KERNEL);
- if (!mt9t013_ctrl) {
- pr_err("mt9t013_init failed!\n");
- rc = -ENOMEM;
- goto init_done;
- }
-
- mt9t013_ctrl->fps_divider = 1 * 0x00000400;
- mt9t013_ctrl->pict_fps_divider = 1 * 0x00000400;
- mt9t013_ctrl->set_test = TEST_OFF;
- mt9t013_ctrl->prev_res = QTR_SIZE;
- mt9t013_ctrl->pict_res = FULL_SIZE;
-
- if (data)
- mt9t013_ctrl->sensordata = data;
-
- /* enable mclk first */
- msm_camio_clk_rate_set(MT9T013_DEFAULT_CLOCK_RATE);
- mdelay(20);
-
- msm_camio_camif_pad_reg_reset();
- mdelay(20);
-
- rc = mt9t013_probe_init_sensor(data);
- if (rc < 0)
- goto init_fail;
-
- if (mt9t013_ctrl->prev_res == QTR_SIZE)
- rc = mt9t013_setting(REG_INIT, RES_PREVIEW);
- else
- rc = mt9t013_setting(REG_INIT, RES_CAPTURE);
-
- if (rc >= 0)
- rc = mt9t013_poweron_af();
-
- if (rc < 0)
- goto init_fail;
- else
- goto init_done;
-
-init_fail:
- kfree(mt9t013_ctrl);
-init_done:
- return rc;
-}
-
-static int mt9t013_init_client(struct i2c_client *client)
-{
- /* Initialize the MSM_CAMI2C Chip */
- init_waitqueue_head(&mt9t013_wait_queue);
- return 0;
-}
-
-
-static int32_t mt9t013_set_sensor_mode(int mode, int res)
-{
- int32_t rc = 0;
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return rc;
-
- switch (mode) {
- case SENSOR_PREVIEW_MODE:
- rc = mt9t013_video_config(mode, res);
- break;
-
- case SENSOR_SNAPSHOT_MODE:
- rc = mt9t013_snapshot_config(mode);
- break;
-
- case SENSOR_RAW_SNAPSHOT_MODE:
- rc = mt9t013_raw_snapshot_config(mode);
- break;
-
- default:
- return -EINVAL;
- }
-
- /* FIXME: what should we do if rc < 0? */
- if (rc >= 0)
- return mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
- return rc;
-}
-
-int mt9t013_sensor_config(void __user *argp)
-{
- struct sensor_cfg_data cdata;
- long rc = 0;
-
- if (copy_from_user(&cdata, (void *)argp,
- sizeof(struct sensor_cfg_data)))
- return -EFAULT;
-
- down(&mt9t013_sem);
-
- CDBG("mt9t013_sensor_config: cfgtype = %d\n", cdata.cfgtype);
- switch (cdata.cfgtype) {
- case CFG_GET_PICT_FPS:
- mt9t013_get_pict_fps(cdata.cfg.gfps.prevfps,
- &(cdata.cfg.gfps.pictfps));
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PREV_L_PF:
- cdata.cfg.prevl_pf = mt9t013_get_prev_lines_pf();
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PREV_P_PL:
- cdata.cfg.prevp_pl = mt9t013_get_prev_pixels_pl();
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_L_PF:
- cdata.cfg.pictl_pf = mt9t013_get_pict_lines_pf();
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_P_PL:
- cdata.cfg.pictp_pl =
- mt9t013_get_pict_pixels_pl();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_MAX_EXP_LC:
- cdata.cfg.pict_max_exp_lc =
- mt9t013_get_pict_max_exp_lc();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_SET_FPS:
- case CFG_SET_PICT_FPS:
- rc = mt9t013_set_fps(&(cdata.cfg.fps));
- break;
-
- case CFG_SET_EXP_GAIN:
- rc = mt9t013_write_exp_gain(cdata.cfg.exp_gain.gain,
- cdata.cfg.exp_gain.line);
- break;
-
- case CFG_SET_PICT_EXP_GAIN:
- rc = mt9t013_set_pict_exp_gain(cdata.cfg.exp_gain.gain,
- cdata.cfg.exp_gain.line);
- break;
-
- case CFG_SET_MODE:
- rc = mt9t013_set_sensor_mode(cdata.mode, cdata.rs);
- break;
-
- case CFG_PWR_DOWN:
- rc = mt9t013_power_down();
- break;
-
- case CFG_MOVE_FOCUS:
- rc = mt9t013_move_focus(cdata.cfg.focus.dir,
- cdata.cfg.focus.steps);
- break;
-
- case CFG_SET_DEFAULT_FOCUS:
- rc = mt9t013_set_default_focus(cdata.cfg.focus.steps);
- break;
-
- case CFG_GET_AF_MAX_STEPS:
- cdata.max_steps = MT9T013_TOTAL_STEPS_NEAR_TO_FAR;
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_SET_EFFECT:
- default:
- rc = -EINVAL;
- break;
- }
-
- up(&mt9t013_sem);
- return rc;
-}
-
-int mt9t013_sensor_release(void)
-{
- int rc = -EBADF;
-
- down(&mt9t013_sem);
-
- mt9t013_poweroff_af();
- mt9t013_power_down();
-
- gpio_direction_output(mt9t013_ctrl->sensordata->sensor_reset,
- 0);
- gpio_free(mt9t013_ctrl->sensordata->sensor_reset);
-
- kfree(mt9t013_ctrl);
-
- up(&mt9t013_sem);
- CDBG("mt9t013_release completed!\n");
- return rc;
-}
-
-static int mt9t013_i2c_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
-{
- int rc = 0;
- if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
- rc = -ENOTSUPP;
- goto probe_failure;
- }
-
- mt9t013_sensorw =
- kzalloc(sizeof(struct mt9t013_work), GFP_KERNEL);
-
- if (!mt9t013_sensorw) {
- rc = -ENOMEM;
- goto probe_failure;
- }
-
- i2c_set_clientdata(client, mt9t013_sensorw);
- mt9t013_init_client(client);
- mt9t013_client = client;
- mt9t013_client->addr = mt9t013_client->addr >> 1;
- mdelay(50);
-
- CDBG("i2c probe ok\n");
- return 0;
-
-probe_failure:
- kfree(mt9t013_sensorw);
- mt9t013_sensorw = NULL;
- pr_err("i2c probe failure %d\n", rc);
- return rc;
-}
-
-static const struct i2c_device_id mt9t013_i2c_id[] = {
- { "mt9t013", 0},
- { }
-};
-
-static struct i2c_driver mt9t013_i2c_driver = {
- .id_table = mt9t013_i2c_id,
- .probe = mt9t013_i2c_probe,
- .remove = __exit_p(mt9t013_i2c_remove),
- .driver = {
- .name = "mt9t013",
- },
-};
-
-static int mt9t013_sensor_probe(
- const struct msm_camera_sensor_info *info,
- struct msm_sensor_ctrl *s)
-{
- /* We expect this driver to match with the i2c device registered
- * in the board file immediately. */
- int rc = i2c_add_driver(&mt9t013_i2c_driver);
- if (rc < 0 || mt9t013_client == NULL) {
- rc = -ENOTSUPP;
- goto probe_done;
- }
-
- /* enable mclk first */
- msm_camio_clk_rate_set(MT9T013_DEFAULT_CLOCK_RATE);
- mdelay(20);
-
- rc = mt9t013_probe_init_sensor(info);
- if (rc < 0) {
- i2c_del_driver(&mt9t013_i2c_driver);
- goto probe_done;
- }
-
- s->s_init = mt9t013_sensor_open_init;
- s->s_release = mt9t013_sensor_release;
- s->s_config = mt9t013_sensor_config;
- mt9t013_sensor_init_done(info);
-
-probe_done:
- return rc;
-}
-
-static int __mt9t013_probe(struct platform_device *pdev)
-{
- return msm_camera_drv_start(pdev, mt9t013_sensor_probe);
-}
-
-static struct platform_driver msm_camera_driver = {
- .probe = __mt9t013_probe,
- .driver = {
- .name = "msm_camera_mt9t013",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init mt9t013_init(void)
-{
- return platform_driver_register(&msm_camera_driver);
-}
-
-module_init(mt9t013_init);
diff --git a/trunk/drivers/staging/dream/camera/mt9t013.h b/trunk/drivers/staging/dream/camera/mt9t013.h
deleted file mode 100644
index 9bce2036e3b6..000000000000
--- a/trunk/drivers/staging/dream/camera/mt9t013.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#ifndef MT9T013_H
-#define MT9T013_H
-
-#include
-
-struct reg_struct {
- uint16_t vt_pix_clk_div; /* 0x0300 */
- uint16_t vt_sys_clk_div; /* 0x0302 */
- uint16_t pre_pll_clk_div; /* 0x0304 */
- uint16_t pll_multiplier; /* 0x0306 */
- uint16_t op_pix_clk_div; /* 0x0308 */
- uint16_t op_sys_clk_div; /* 0x030A */
- uint16_t scale_m; /* 0x0404 */
- uint16_t row_speed; /* 0x3016 */
- uint16_t x_addr_start; /* 0x3004 */
- uint16_t x_addr_end; /* 0x3008 */
- uint16_t y_addr_start; /* 0x3002 */
- uint16_t y_addr_end; /* 0x3006 */
- uint16_t read_mode; /* 0x3040 */
- uint16_t x_output_size; /* 0x034C */
- uint16_t y_output_size; /* 0x034E */
- uint16_t line_length_pck; /* 0x300C */
- uint16_t frame_length_lines; /* 0x300A */
- uint16_t coarse_int_time; /* 0x3012 */
- uint16_t fine_int_time; /* 0x3014 */
-};
-
-struct mt9t013_i2c_reg_conf {
- unsigned short waddr;
- unsigned short wdata;
-};
-
-struct mt9t013_reg {
- struct reg_struct *reg_pat;
- uint16_t reg_pat_size;
- struct mt9t013_i2c_reg_conf *ttbl;
- uint16_t ttbl_size;
- struct mt9t013_i2c_reg_conf *lctbl;
- uint16_t lctbl_size;
- struct mt9t013_i2c_reg_conf *rftbl;
- uint16_t rftbl_size;
-};
-
-#endif /* #define MT9T013_H */
diff --git a/trunk/drivers/staging/dream/camera/mt9t013_reg.c b/trunk/drivers/staging/dream/camera/mt9t013_reg.c
deleted file mode 100644
index ba0a1d4b4d5f..000000000000
--- a/trunk/drivers/staging/dream/camera/mt9t013_reg.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * Copyright (C) 2009 QUALCOMM Incorporated.
- */
-
-#include "mt9t013.h"
-#include
-
-struct reg_struct const mt9t013_reg_pat[2] = {
- { /* Preview 2x2 binning 20fps, pclk MHz, MCLK 24MHz */
- /* vt_pix_clk_div:REG=0x0300 update get_snapshot_fps
- * if this change */
- 8,
-
- /* vt_sys_clk_div: REG=0x0302 update get_snapshot_fps
- * if this change */
- 1,
-
- /* pre_pll_clk_div REG=0x0304 update get_snapshot_fps
- * if this change */
- 2,
-
- /* pll_multiplier REG=0x0306 60 for 30fps preview, 40
- * for 20fps preview
- * 46 for 30fps preview, try 47/48 to increase further */
- 46,
-
- /* op_pix_clk_div REG=0x0308 */
- 8,
-
- /* op_sys_clk_div REG=0x030A */
- 1,
-
- /* scale_m REG=0x0404 */
- 16,
-
- /* row_speed REG=0x3016 */
- 0x0111,
-
- /* x_addr_start REG=0x3004 */
- 8,
-
- /* x_addr_end REG=0x3008 */
- 2053,
-
- /* y_addr_start REG=0x3002 */
- 8,
-
- /* y_addr_end REG=0x3006 */
- 1541,
-
- /* read_mode REG=0x3040 */
- 0x046C,
-
- /* x_output_size REG=0x034C */
- 1024,
-
- /* y_output_size REG=0x034E */
- 768,
-
- /* line_length_pck REG=0x300C */
- 2616,
-
- /* frame_length_lines REG=0x300A */
- 916,
-
- /* coarse_int_time REG=0x3012 */
- 16,
-
- /* fine_int_time REG=0x3014 */
- 1461
- },
- { /*Snapshot */
- /* vt_pix_clk_div REG=0x0300 update get_snapshot_fps
- * if this change */
- 8,
-
- /* vt_sys_clk_div REG=0x0302 update get_snapshot_fps
- * if this change */
- 1,
-
- /* pre_pll_clk_div REG=0x0304 update get_snapshot_fps
- * if this change */
- 2,
-
- /* pll_multiplier REG=0x0306 50 for 15fps snapshot,
- * 40 for 10fps snapshot
- * 46 for 30fps snapshot, try 47/48 to increase further */
- 46,
-
- /* op_pix_clk_div REG=0x0308 */
- 8,
-
- /* op_sys_clk_div REG=0x030A */
- 1,
-
- /* scale_m REG=0x0404 */
- 16,
-
- /* row_speed REG=0x3016 */
- 0x0111,
-
- /* x_addr_start REG=0x3004 */
- 8,
-
- /* x_addr_end REG=0x3008 */
- 2071,
-
- /* y_addr_start REG=0x3002 */
- 8,
-
- /* y_addr_end REG=0x3006 */
- 1551,
-
- /* read_mode REG=0x3040 */
- 0x0024,
-
- /* x_output_size REG=0x034C */
- 2064,
-
- /* y_output_size REG=0x034E */
- 1544,
-
- /* line_length_pck REG=0x300C */
- 2952,
-
- /* frame_length_lines REG=0x300A */
- 1629,
-
- /* coarse_int_time REG=0x3012 */
- 16,
-
- /* fine_int_time REG=0x3014 */
- 733
- }
-};
-
-struct mt9t013_i2c_reg_conf mt9t013_test_tbl[] = {
- { 0x3044, 0x0544 & 0xFBFF },
- { 0x30CA, 0x0004 | 0x0001 },
- { 0x30D4, 0x9020 & 0x7FFF },
- { 0x31E0, 0x0003 & 0xFFFE },
- { 0x3180, 0x91FF & 0x7FFF },
- { 0x301A, (0x10CC | 0x8000) & 0xFFF7 },
- { 0x301E, 0x0000 },
- { 0x3780, 0x0000 },
-};
-
-/* [Lens shading 85 Percent TL84] */
-struct mt9t013_i2c_reg_conf mt9t013_lc_tbl[] = {
- { 0x360A, 0x0290 }, /* P_RD_P0Q0 */
- { 0x360C, 0xC92D }, /* P_RD_P0Q1 */
- { 0x360E, 0x0771 }, /* P_RD_P0Q2 */
- { 0x3610, 0xE38C }, /* P_RD_P0Q3 */
- { 0x3612, 0xD74F }, /* P_RD_P0Q4 */
- { 0x364A, 0x168C }, /* P_RD_P1Q0 */
- { 0x364C, 0xCACB }, /* P_RD_P1Q1 */
- { 0x364E, 0x8C4C }, /* P_RD_P1Q2 */
- { 0x3650, 0x0BEA }, /* P_RD_P1Q3 */
- { 0x3652, 0xDC0F }, /* P_RD_P1Q4 */
- { 0x368A, 0x70B0 }, /* P_RD_P2Q0 */
- { 0x368C, 0x200B }, /* P_RD_P2Q1 */
- { 0x368E, 0x30B2 }, /* P_RD_P2Q2 */
- { 0x3690, 0xD04F }, /* P_RD_P2Q3 */
- { 0x3692, 0xACF5 }, /* P_RD_P2Q4 */
- { 0x36CA, 0xF7C9 }, /* P_RD_P3Q0 */
- { 0x36CC, 0x2AED }, /* P_RD_P3Q1 */
- { 0x36CE, 0xA652 }, /* P_RD_P3Q2 */
- { 0x36D0, 0x8192 }, /* P_RD_P3Q3 */
- { 0x36D2, 0x3A15 }, /* P_RD_P3Q4 */
- { 0x370A, 0xDA30 }, /* P_RD_P4Q0 */
- { 0x370C, 0x2E2F }, /* P_RD_P4Q1 */
- { 0x370E, 0xBB56 }, /* P_RD_P4Q2 */
- { 0x3710, 0x8195 }, /* P_RD_P4Q3 */
- { 0x3712, 0x02F9 }, /* P_RD_P4Q4 */
- { 0x3600, 0x0230 }, /* P_GR_P0Q0 */
- { 0x3602, 0x58AD }, /* P_GR_P0Q1 */
- { 0x3604, 0x18D1 }, /* P_GR_P0Q2 */
- { 0x3606, 0x260D }, /* P_GR_P0Q3 */
- { 0x3608, 0xF530 }, /* P_GR_P0Q4 */
- { 0x3640, 0x17EB }, /* P_GR_P1Q0 */
- { 0x3642, 0x3CAB }, /* P_GR_P1Q1 */
- { 0x3644, 0x87CE }, /* P_GR_P1Q2 */
- { 0x3646, 0xC02E }, /* P_GR_P1Q3 */
- { 0x3648, 0xF48F }, /* P_GR_P1Q4 */
- { 0x3680, 0x5350 }, /* P_GR_P2Q0 */
- { 0x3682, 0x7EAF }, /* P_GR_P2Q1 */
- { 0x3684, 0x4312 }, /* P_GR_P2Q2 */
- { 0x3686, 0xC652 }, /* P_GR_P2Q3 */
- { 0x3688, 0xBC15 }, /* P_GR_P2Q4 */
- { 0x36C0, 0xB8AD }, /* P_GR_P3Q0 */
- { 0x36C2, 0xBDCD }, /* P_GR_P3Q1 */
- { 0x36C4, 0xE4B2 }, /* P_GR_P3Q2 */
- { 0x36C6, 0xB50F }, /* P_GR_P3Q3 */
- { 0x36C8, 0x5B95 }, /* P_GR_P3Q4 */
- { 0x3700, 0xFC90 }, /* P_GR_P4Q0 */
- { 0x3702, 0x8C51 }, /* P_GR_P4Q1 */
- { 0x3704, 0xCED6 }, /* P_GR_P4Q2 */
- { 0x3706, 0xB594 }, /* P_GR_P4Q3 */
- { 0x3708, 0x0A39 }, /* P_GR_P4Q4 */
- { 0x3614, 0x0230 }, /* P_BL_P0Q0 */
- { 0x3616, 0x160D }, /* P_BL_P0Q1 */
- { 0x3618, 0x08D1 }, /* P_BL_P0Q2 */
- { 0x361A, 0x98AB }, /* P_BL_P0Q3 */
- { 0x361C, 0xEA50 }, /* P_BL_P0Q4 */
- { 0x3654, 0xB4EA }, /* P_BL_P1Q0 */
- { 0x3656, 0xEA6C }, /* P_BL_P1Q1 */
- { 0x3658, 0xFE08 }, /* P_BL_P1Q2 */
- { 0x365A, 0x2C6E }, /* P_BL_P1Q3 */
- { 0x365C, 0xEB0E }, /* P_BL_P1Q4 */
- { 0x3694, 0x6DF0 }, /* P_BL_P2Q0 */
- { 0x3696, 0x3ACF }, /* P_BL_P2Q1 */
- { 0x3698, 0x3E0F }, /* P_BL_P2Q2 */
- { 0x369A, 0xB2B1 }, /* P_BL_P2Q3 */
- { 0x369C, 0xC374 }, /* P_BL_P2Q4 */
- { 0x36D4, 0xF2AA }, /* P_BL_P3Q0 */
- { 0x36D6, 0x8CCC }, /* P_BL_P3Q1 */
- { 0x36D8, 0xDEF2 }, /* P_BL_P3Q2 */
- { 0x36DA, 0xFA11 }, /* P_BL_P3Q3 */
- { 0x36DC, 0x42F5 }, /* P_BL_P3Q4 */
- { 0x3714, 0xF4F1 }, /* P_BL_P4Q0 */
- { 0x3716, 0xF6F0 }, /* P_BL_P4Q1 */
- { 0x3718, 0x8FD6 }, /* P_BL_P4Q2 */
- { 0x371A, 0xEA14 }, /* P_BL_P4Q3 */
- { 0x371C, 0x6338 }, /* P_BL_P4Q4 */
- { 0x361E, 0x0350 }, /* P_GB_P0Q0 */
- { 0x3620, 0x91AE }, /* P_GB_P0Q1 */
- { 0x3622, 0x0571 }, /* P_GB_P0Q2 */
- { 0x3624, 0x100D }, /* P_GB_P0Q3 */
- { 0x3626, 0xCA70 }, /* P_GB_P0Q4 */
- { 0x365E, 0xE6CB }, /* P_GB_P1Q0 */
- { 0x3660, 0x50ED }, /* P_GB_P1Q1 */
- { 0x3662, 0x3DAE }, /* P_GB_P1Q2 */
- { 0x3664, 0xAA4F }, /* P_GB_P1Q3 */
- { 0x3666, 0xDC50 }, /* P_GB_P1Q4 */
- { 0x369E, 0x5470 }, /* P_GB_P2Q0 */
- { 0x36A0, 0x1F6E }, /* P_GB_P2Q1 */
- { 0x36A2, 0x6671 }, /* P_GB_P2Q2 */
- { 0x36A4, 0xC010 }, /* P_GB_P2Q3 */
- { 0x36A6, 0x8DF5 }, /* P_GB_P2Q4 */
- { 0x36DE, 0x0B0C }, /* P_GB_P3Q0 */
- { 0x36E0, 0x84CE }, /* P_GB_P3Q1 */
- { 0x36E2, 0x8493 }, /* P_GB_P3Q2 */
- { 0x36E4, 0xA610 }, /* P_GB_P3Q3 */
- { 0x36E6, 0x50B5 }, /* P_GB_P3Q4 */
- { 0x371E, 0x9651 }, /* P_GB_P4Q0 */
- { 0x3720, 0x1EAB }, /* P_GB_P4Q1 */
- { 0x3722, 0xAF76 }, /* P_GB_P4Q2 */
- { 0x3724, 0xE4F4 }, /* P_GB_P4Q3 */
- { 0x3726, 0x79F8 }, /* P_GB_P4Q4 */
- { 0x3782, 0x0410 }, /* POLY_ORIGIN_C */
- { 0x3784, 0x0320 }, /* POLY_ORIGIN_R */
- { 0x3780, 0x8000 } /* POLY_SC_ENABLE */
-};
-
-struct mt9t013_reg mt9t013_regs = {
- .reg_pat = &mt9t013_reg_pat[0],
- .reg_pat_size = ARRAY_SIZE(mt9t013_reg_pat),
- .ttbl = &mt9t013_test_tbl[0],
- .ttbl_size = ARRAY_SIZE(mt9t013_test_tbl),
- .lctbl = &mt9t013_lc_tbl[0],
- .lctbl_size = ARRAY_SIZE(mt9t013_lc_tbl),
- .rftbl = &mt9t013_lc_tbl[0], /* &mt9t013_rolloff_tbl[0], */
- .rftbl_size = ARRAY_SIZE(mt9t013_lc_tbl)
-};
-
-
diff --git a/trunk/drivers/staging/dream/camera/s5k3e2fx.c b/trunk/drivers/staging/dream/camera/s5k3e2fx.c
deleted file mode 100644
index 1459903a339d..000000000000
--- a/trunk/drivers/staging/dream/camera/s5k3e2fx.c
+++ /dev/null
@@ -1,1307 +0,0 @@
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include "s5k3e2fx.h"
-
-#define S5K3E2FX_REG_MODEL_ID 0x0000
-#define S5K3E2FX_MODEL_ID 0x3E2F
-
-/* PLL Registers */
-#define REG_PRE_PLL_CLK_DIV 0x0305
-#define REG_PLL_MULTIPLIER_MSB 0x0306
-#define REG_PLL_MULTIPLIER_LSB 0x0307
-#define REG_VT_PIX_CLK_DIV 0x0301
-#define REG_VT_SYS_CLK_DIV 0x0303
-#define REG_OP_PIX_CLK_DIV 0x0309
-#define REG_OP_SYS_CLK_DIV 0x030B
-
-/* Data Format Registers */
-#define REG_CCP_DATA_FORMAT_MSB 0x0112
-#define REG_CCP_DATA_FORMAT_LSB 0x0113
-
-/* Output Size */
-#define REG_X_OUTPUT_SIZE_MSB 0x034C
-#define REG_X_OUTPUT_SIZE_LSB 0x034D
-#define REG_Y_OUTPUT_SIZE_MSB 0x034E
-#define REG_Y_OUTPUT_SIZE_LSB 0x034F
-
-/* Binning */
-#define REG_X_EVEN_INC 0x0381
-#define REG_X_ODD_INC 0x0383
-#define REG_Y_EVEN_INC 0x0385
-#define REG_Y_ODD_INC 0x0387
-/*Reserved register */
-#define REG_BINNING_ENABLE 0x3014
-
-/* Frame Fotmat */
-#define REG_FRAME_LENGTH_LINES_MSB 0x0340
-#define REG_FRAME_LENGTH_LINES_LSB 0x0341
-#define REG_LINE_LENGTH_PCK_MSB 0x0342
-#define REG_LINE_LENGTH_PCK_LSB 0x0343
-
-/* MSR setting */
-/* Reserved registers */
-#define REG_SHADE_CLK_ENABLE 0x30AC
-#define REG_SEL_CCP 0x30C4
-#define REG_VPIX 0x3024
-#define REG_CLAMP_ON 0x3015
-#define REG_OFFSET 0x307E
-
-/* CDS timing settings */
-/* Reserved registers */
-#define REG_LD_START 0x3000
-#define REG_LD_END 0x3001
-#define REG_SL_START 0x3002
-#define REG_SL_END 0x3003
-#define REG_RX_START 0x3004
-#define REG_S1_START 0x3005
-#define REG_S1_END 0x3006
-#define REG_S1S_START 0x3007
-#define REG_S1S_END 0x3008
-#define REG_S3_START 0x3009
-#define REG_S3_END 0x300A
-#define REG_CMP_EN_START 0x300B
-#define REG_CLP_SL_START 0x300C
-#define REG_CLP_SL_END 0x300D
-#define REG_OFF_START 0x300E
-#define REG_RMP_EN_START 0x300F
-#define REG_TX_START 0x3010
-#define REG_TX_END 0x3011
-#define REG_STX_WIDTH 0x3012
-#define REG_TYPE1_AF_ENABLE 0x3130
-#define DRIVER_ENABLED 0x0001
-#define AUTO_START_ENABLED 0x0010
-#define REG_NEW_POSITION 0x3131
-#define REG_3152_RESERVED 0x3152
-#define REG_315A_RESERVED 0x315A
-#define REG_ANALOGUE_GAIN_CODE_GLOBAL_MSB 0x0204
-#define REG_ANALOGUE_GAIN_CODE_GLOBAL_LSB 0x0205
-#define REG_FINE_INTEGRATION_TIME 0x0200
-#define REG_COARSE_INTEGRATION_TIME 0x0202
-#define REG_COARSE_INTEGRATION_TIME_LSB 0x0203
-
-/* Mode select register */
-#define S5K3E2FX_REG_MODE_SELECT 0x0100
-#define S5K3E2FX_MODE_SELECT_STREAM 0x01 /* start streaming */
-#define S5K3E2FX_MODE_SELECT_SW_STANDBY 0x00 /* software standby */
-#define S5K3E2FX_REG_SOFTWARE_RESET 0x0103
-#define S5K3E2FX_SOFTWARE_RESET 0x01
-#define REG_TEST_PATTERN_MODE 0x0601
-
-struct reg_struct {
- uint8_t pre_pll_clk_div; /* 0x0305 */
- uint8_t pll_multiplier_msb; /* 0x0306 */
- uint8_t pll_multiplier_lsb; /* 0x0307 */
- uint8_t vt_pix_clk_div; /* 0x0301 */
- uint8_t vt_sys_clk_div; /* 0x0303 */
- uint8_t op_pix_clk_div; /* 0x0309 */
- uint8_t op_sys_clk_div; /* 0x030B */
- uint8_t ccp_data_format_msb; /* 0x0112 */
- uint8_t ccp_data_format_lsb; /* 0x0113 */
- uint8_t x_output_size_msb; /* 0x034C */
- uint8_t x_output_size_lsb; /* 0x034D */
- uint8_t y_output_size_msb; /* 0x034E */
- uint8_t y_output_size_lsb; /* 0x034F */
- uint8_t x_even_inc; /* 0x0381 */
- uint8_t x_odd_inc; /* 0x0383 */
- uint8_t y_even_inc; /* 0x0385 */
- uint8_t y_odd_inc; /* 0x0387 */
- uint8_t binning_enable; /* 0x3014 */
- uint8_t frame_length_lines_msb; /* 0x0340 */
- uint8_t frame_length_lines_lsb; /* 0x0341 */
- uint8_t line_length_pck_msb; /* 0x0342 */
- uint8_t line_length_pck_lsb; /* 0x0343 */
- uint8_t shade_clk_enable ; /* 0x30AC */
- uint8_t sel_ccp; /* 0x30C4 */
- uint8_t vpix; /* 0x3024 */
- uint8_t clamp_on; /* 0x3015 */
- uint8_t offset; /* 0x307E */
- uint8_t ld_start; /* 0x3000 */
- uint8_t ld_end; /* 0x3001 */
- uint8_t sl_start; /* 0x3002 */
- uint8_t sl_end; /* 0x3003 */
- uint8_t rx_start; /* 0x3004 */
- uint8_t s1_start; /* 0x3005 */
- uint8_t s1_end; /* 0x3006 */
- uint8_t s1s_start; /* 0x3007 */
- uint8_t s1s_end; /* 0x3008 */
- uint8_t s3_start; /* 0x3009 */
- uint8_t s3_end; /* 0x300A */
- uint8_t cmp_en_start; /* 0x300B */
- uint8_t clp_sl_start; /* 0x300C */
- uint8_t clp_sl_end; /* 0x300D */
- uint8_t off_start; /* 0x300E */
- uint8_t rmp_en_start; /* 0x300F */
- uint8_t tx_start; /* 0x3010 */
- uint8_t tx_end; /* 0x3011 */
- uint8_t stx_width; /* 0x3012 */
- uint8_t reg_3152_reserved; /* 0x3152 */
- uint8_t reg_315A_reserved; /* 0x315A */
- uint8_t analogue_gain_code_global_msb; /* 0x0204 */
- uint8_t analogue_gain_code_global_lsb; /* 0x0205 */
- uint8_t fine_integration_time; /* 0x0200 */
- uint8_t coarse_integration_time; /* 0x0202 */
- uint32_t size_h;
- uint32_t blk_l;
- uint32_t size_w;
- uint32_t blk_p;
-};
-
-struct reg_struct s5k3e2fx_reg_pat[2] = {
- { /* Preview */
- 0x06, /* pre_pll_clk_div REG=0x0305 */
- 0x00, /* pll_multiplier_msb REG=0x0306 */
- 0x88, /* pll_multiplier_lsb REG=0x0307 */
- 0x0a, /* vt_pix_clk_div REG=0x0301 */
- 0x01, /* vt_sys_clk_div REG=0x0303 */
- 0x0a, /* op_pix_clk_div REG=0x0309 */
- 0x01, /* op_sys_clk_div REG=0x030B */
- 0x0a, /* ccp_data_format_msb REG=0x0112 */
- 0x0a, /* ccp_data_format_lsb REG=0x0113 */
- 0x05, /* x_output_size_msb REG=0x034C */
- 0x10, /* x_output_size_lsb REG=0x034D */
- 0x03, /* y_output_size_msb REG=0x034E */
- 0xcc, /* y_output_size_lsb REG=0x034F */
-
- /* enable binning for preview */
- 0x01, /* x_even_inc REG=0x0381 */
- 0x01, /* x_odd_inc REG=0x0383 */
- 0x01, /* y_even_inc REG=0x0385 */
- 0x03, /* y_odd_inc REG=0x0387 */
- 0x06, /* binning_enable REG=0x3014 */
-
- 0x03, /* frame_length_lines_msb REG=0x0340 */
- 0xde, /* frame_length_lines_lsb REG=0x0341 */
- 0x0a, /* line_length_pck_msb REG=0x0342 */
- 0xac, /* line_length_pck_lsb REG=0x0343 */
- 0x81, /* shade_clk_enable REG=0x30AC */
- 0x01, /* sel_ccp REG=0x30C4 */
- 0x04, /* vpix REG=0x3024 */
- 0x00, /* clamp_on REG=0x3015 */
- 0x02, /* offset REG=0x307E */
- 0x03, /* ld_start REG=0x3000 */
- 0x9c, /* ld_end REG=0x3001 */
- 0x02, /* sl_start REG=0x3002 */
- 0x9e, /* sl_end REG=0x3003 */
- 0x05, /* rx_start REG=0x3004 */
- 0x0f, /* s1_start REG=0x3005 */
- 0x24, /* s1_end REG=0x3006 */
- 0x7c, /* s1s_start REG=0x3007 */
- 0x9a, /* s1s_end REG=0x3008 */
- 0x10, /* s3_start REG=0x3009 */
- 0x14, /* s3_end REG=0x300A */
- 0x10, /* cmp_en_start REG=0x300B */
- 0x04, /* clp_sl_start REG=0x300C */
- 0x26, /* clp_sl_end REG=0x300D */
- 0x02, /* off_start REG=0x300E */
- 0x0e, /* rmp_en_start REG=0x300F */
- 0x30, /* tx_start REG=0x3010 */
- 0x4e, /* tx_end REG=0x3011 */
- 0x1E, /* stx_width REG=0x3012 */
- 0x08, /* reg_3152_reserved REG=0x3152 */
- 0x10, /* reg_315A_reserved REG=0x315A */
- 0x00, /* analogue_gain_code_global_msb REG=0x0204 */
- 0x80, /* analogue_gain_code_global_lsb REG=0x0205 */
- 0x02, /* fine_integration_time REG=0x0200 */
- 0x03, /* coarse_integration_time REG=0x0202 */
- 972,
- 18,
- 1296,
- 1436
- },
- { /* Snapshot */
- 0x06, /* pre_pll_clk_div REG=0x0305 */
- 0x00, /* pll_multiplier_msb REG=0x0306 */
- 0x88, /* pll_multiplier_lsb REG=0x0307 */
- 0x0a, /* vt_pix_clk_div REG=0x0301 */
- 0x01, /* vt_sys_clk_div REG=0x0303 */
- 0x0a, /* op_pix_clk_div REG=0x0309 */
- 0x01, /* op_sys_clk_div REG=0x030B */
- 0x0a, /* ccp_data_format_msb REG=0x0112 */
- 0x0a, /* ccp_data_format_lsb REG=0x0113 */
- 0x0a, /* x_output_size_msb REG=0x034C */
- 0x30, /* x_output_size_lsb REG=0x034D */
- 0x07, /* y_output_size_msb REG=0x034E */
- 0xa8, /* y_output_size_lsb REG=0x034F */
-
- /* disable binning for snapshot */
- 0x01, /* x_even_inc REG=0x0381 */
- 0x01, /* x_odd_inc REG=0x0383 */
- 0x01, /* y_even_inc REG=0x0385 */
- 0x01, /* y_odd_inc REG=0x0387 */
- 0x00, /* binning_enable REG=0x3014 */
-
- 0x07, /* frame_length_lines_msb REG=0x0340 */
- 0xb6, /* frame_length_lines_lsb REG=0x0341 */
- 0x0a, /* line_length_pck_msb REG=0x0342 */
- 0xac, /* line_length_pck_lsb REG=0x0343 */
- 0x81, /* shade_clk_enable REG=0x30AC */
- 0x01, /* sel_ccp REG=0x30C4 */
- 0x04, /* vpix REG=0x3024 */
- 0x00, /* clamp_on REG=0x3015 */
- 0x02, /* offset REG=0x307E */
- 0x03, /* ld_start REG=0x3000 */
- 0x9c, /* ld_end REG=0x3001 */
- 0x02, /* sl_start REG=0x3002 */
- 0x9e, /* sl_end REG=0x3003 */
- 0x05, /* rx_start REG=0x3004 */
- 0x0f, /* s1_start REG=0x3005 */
- 0x24, /* s1_end REG=0x3006 */
- 0x7c, /* s1s_start REG=0x3007 */
- 0x9a, /* s1s_end REG=0x3008 */
- 0x10, /* s3_start REG=0x3009 */
- 0x14, /* s3_end REG=0x300A */
- 0x10, /* cmp_en_start REG=0x300B */
- 0x04, /* clp_sl_start REG=0x300C */
- 0x26, /* clp_sl_end REG=0x300D */
- 0x02, /* off_start REG=0x300E */
- 0x0e, /* rmp_en_start REG=0x300F */
- 0x30, /* tx_start REG=0x3010 */
- 0x4e, /* tx_end REG=0x3011 */
- 0x1E, /* stx_width REG=0x3012 */
- 0x08, /* reg_3152_reserved REG=0x3152 */
- 0x10, /* reg_315A_reserved REG=0x315A */
- 0x00, /* analogue_gain_code_global_msb REG=0x0204 */
- 0x80, /* analogue_gain_code_global_lsb REG=0x0205 */
- 0x02, /* fine_integration_time REG=0x0200 */
- 0x03, /* coarse_integration_time REG=0x0202 */
- 1960,
- 14,
- 2608,
- 124
- }
-};
-
-struct s5k3e2fx_work {
- struct work_struct work;
-};
-static struct s5k3e2fx_work *s5k3e2fx_sensorw;
-static struct i2c_client *s5k3e2fx_client;
-
-struct s5k3e2fx_ctrl {
- const struct msm_camera_sensor_info *sensordata;
-
- int sensormode;
- uint32_t fps_divider; /* init to 1 * 0x00000400 */
- uint32_t pict_fps_divider; /* init to 1 * 0x00000400 */
-
- uint16_t curr_lens_pos;
- uint16_t init_curr_lens_pos;
- uint16_t my_reg_gain;
- uint32_t my_reg_line_count;
-
- enum msm_s_resolution prev_res;
- enum msm_s_resolution pict_res;
- enum msm_s_resolution curr_res;
- enum msm_s_test_mode set_test;
-};
-
-struct s5k3e2fx_i2c_reg_conf {
- unsigned short waddr;
- unsigned char bdata;
-};
-
-static struct s5k3e2fx_ctrl *s5k3e2fx_ctrl;
-static DECLARE_WAIT_QUEUE_HEAD(s5k3e2fx_wait_queue);
-DECLARE_MUTEX(s5k3e2fx_sem);
-
-static int s5k3e2fx_i2c_rxdata(unsigned short saddr, unsigned char *rxdata,
- int length)
-{
- struct i2c_msg msgs[] = {
- {
- .addr = saddr,
- .flags = 0,
- .len = 2,
- .buf = rxdata,
- },
- {
- .addr = saddr,
- .flags = I2C_M_RD,
- .len = length,
- .buf = rxdata,
- },
- };
-
- if (i2c_transfer(s5k3e2fx_client->adapter, msgs, 2) < 0) {
- CDBG("s5k3e2fx_i2c_rxdata failed!\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int32_t s5k3e2fx_i2c_txdata(unsigned short saddr,
- unsigned char *txdata, int length)
-{
- struct i2c_msg msg[] = {
- {
- .addr = saddr,
- .flags = 0,
- .len = length,
- .buf = txdata,
- },
- };
-
- if (i2c_transfer(s5k3e2fx_client->adapter, msg, 1) < 0) {
- CDBG("s5k3e2fx_i2c_txdata failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int32_t s5k3e2fx_i2c_write_b(unsigned short saddr, unsigned short waddr,
- unsigned char bdata)
-{
- int32_t rc = -EIO;
- unsigned char buf[4];
-
- memset(buf, 0, sizeof(buf));
- buf[0] = (waddr & 0xFF00)>>8;
- buf[1] = (waddr & 0x00FF);
- buf[2] = bdata;
-
- rc = s5k3e2fx_i2c_txdata(saddr, buf, 3);
-
- if (rc < 0)
- CDBG("i2c_write_w failed, addr = 0x%x, val = 0x%x!\n",
- waddr, bdata);
-
- return rc;
-}
-
-static int32_t s5k3e2fx_i2c_write_table(
- struct s5k3e2fx_i2c_reg_conf *reg_cfg_tbl, int num)
-{
- int i;
- int32_t rc = -EIO;
- for (i = 0; i < num; i++) {
- if (rc < 0)
- break;
- reg_cfg_tbl++;
- }
-
- return rc;
-}
-
-static int32_t s5k3e2fx_i2c_read_w(unsigned short saddr, unsigned short raddr,
- unsigned short *rdata)
-{
- int32_t rc = 0;
- unsigned char buf[4];
-
- if (!rdata)
- return -EIO;
-
- memset(buf, 0, sizeof(buf));
-
- buf[0] = (raddr & 0xFF00)>>8;
- buf[1] = (raddr & 0x00FF);
-
- rc = s5k3e2fx_i2c_rxdata(saddr, buf, 2);
- if (rc < 0)
- return rc;
-
- *rdata = buf[0] << 8 | buf[1];
-
- if (rc < 0)
- CDBG("s5k3e2fx_i2c_read failed!\n");
-
- return rc;
-}
-
-static int s5k3e2fx_probe_init_done(const struct msm_camera_sensor_info *data)
-{
- gpio_direction_output(data->sensor_reset, 0);
- gpio_free(data->sensor_reset);
- return 0;
-}
-
-static int s5k3e2fx_probe_init_sensor(const struct msm_camera_sensor_info *data)
-{
- int32_t rc;
- uint16_t chipid = 0;
-
- rc = gpio_request(data->sensor_reset, "s5k3e2fx");
- if (!rc)
- gpio_direction_output(data->sensor_reset, 1);
- else
- goto init_probe_done;
-
- mdelay(20);
-
- CDBG("s5k3e2fx_sensor_init(): reseting sensor.\n");
-
- rc = s5k3e2fx_i2c_read_w(s5k3e2fx_client->addr,
- S5K3E2FX_REG_MODEL_ID, &chipid);
- if (rc < 0)
- goto init_probe_fail;
-
- if (chipid != S5K3E2FX_MODEL_ID) {
- CDBG("S5K3E2FX wrong model_id = 0x%x\n", chipid);
- rc = -ENODEV;
- goto init_probe_fail;
- }
-
- goto init_probe_done;
-
-init_probe_fail:
- s5k3e2fx_probe_init_done(data);
-init_probe_done:
- return rc;
-}
-
-static int s5k3e2fx_init_client(struct i2c_client *client)
-{
- /* Initialize the MSM_CAMI2C Chip */
- init_waitqueue_head(&s5k3e2fx_wait_queue);
- return 0;
-}
-
-static const struct i2c_device_id s5k3e2fx_i2c_id[] = {
- { "s5k3e2fx", 0},
- { }
-};
-
-static int s5k3e2fx_i2c_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
-{
- int rc = 0;
- CDBG("s5k3e2fx_probe called!\n");
-
- if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
- CDBG("i2c_check_functionality failed\n");
- goto probe_failure;
- }
-
- s5k3e2fx_sensorw = kzalloc(sizeof(struct s5k3e2fx_work), GFP_KERNEL);
- if (!s5k3e2fx_sensorw) {
- CDBG("kzalloc failed.\n");
- rc = -ENOMEM;
- goto probe_failure;
- }
-
- i2c_set_clientdata(client, s5k3e2fx_sensorw);
- s5k3e2fx_init_client(client);
- s5k3e2fx_client = client;
-
- mdelay(50);
-
- CDBG("s5k3e2fx_probe successed! rc = %d\n", rc);
- return 0;
-
-probe_failure:
- CDBG("s5k3e2fx_probe failed! rc = %d\n", rc);
- return rc;
-}
-
-static struct i2c_driver s5k3e2fx_i2c_driver = {
- .id_table = s5k3e2fx_i2c_id,
- .probe = s5k3e2fx_i2c_probe,
- .remove = __exit_p(s5k3e2fx_i2c_remove),
- .driver = {
- .name = "s5k3e2fx",
- },
-};
-
-static int32_t s5k3e2fx_test(enum msm_s_test_mode mo)
-{
- int32_t rc = 0;
-
- if (mo == S_TEST_OFF)
- rc = 0;
- else
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr,
- REG_TEST_PATTERN_MODE, (uint16_t)mo);
-
- return rc;
-}
-
-static int32_t s5k3e2fx_setting(enum msm_s_reg_update rupdate,
- enum msm_s_setting rt)
-{
- int32_t rc = 0;
- uint16_t num_lperf;
-
- switch (rupdate) {
- case S_UPDATE_PERIODIC:
- if (rt == S_RES_PREVIEW || rt == S_RES_CAPTURE) {
-
- struct s5k3e2fx_i2c_reg_conf tbl_1[] = {
- {REG_CCP_DATA_FORMAT_MSB, s5k3e2fx_reg_pat[rt].ccp_data_format_msb},
- {REG_CCP_DATA_FORMAT_LSB, s5k3e2fx_reg_pat[rt].ccp_data_format_lsb},
- {REG_X_OUTPUT_SIZE_MSB, s5k3e2fx_reg_pat[rt].x_output_size_msb},
- {REG_X_OUTPUT_SIZE_LSB, s5k3e2fx_reg_pat[rt].x_output_size_lsb},
- {REG_Y_OUTPUT_SIZE_MSB, s5k3e2fx_reg_pat[rt].y_output_size_msb},
- {REG_Y_OUTPUT_SIZE_LSB, s5k3e2fx_reg_pat[rt].y_output_size_lsb},
- {REG_X_EVEN_INC, s5k3e2fx_reg_pat[rt].x_even_inc},
- {REG_X_ODD_INC, s5k3e2fx_reg_pat[rt].x_odd_inc},
- {REG_Y_EVEN_INC, s5k3e2fx_reg_pat[rt].y_even_inc},
- {REG_Y_ODD_INC, s5k3e2fx_reg_pat[rt].y_odd_inc},
- {REG_BINNING_ENABLE, s5k3e2fx_reg_pat[rt].binning_enable},
- };
-
- struct s5k3e2fx_i2c_reg_conf tbl_2[] = {
- {REG_FRAME_LENGTH_LINES_MSB, 0},
- {REG_FRAME_LENGTH_LINES_LSB, 0},
- {REG_LINE_LENGTH_PCK_MSB, s5k3e2fx_reg_pat[rt].line_length_pck_msb},
- {REG_LINE_LENGTH_PCK_LSB, s5k3e2fx_reg_pat[rt].line_length_pck_lsb},
- {REG_SHADE_CLK_ENABLE, s5k3e2fx_reg_pat[rt].shade_clk_enable},
- {REG_SEL_CCP, s5k3e2fx_reg_pat[rt].sel_ccp},
- {REG_VPIX, s5k3e2fx_reg_pat[rt].vpix},
- {REG_CLAMP_ON, s5k3e2fx_reg_pat[rt].clamp_on},
- {REG_OFFSET, s5k3e2fx_reg_pat[rt].offset},
- {REG_LD_START, s5k3e2fx_reg_pat[rt].ld_start},
- {REG_LD_END, s5k3e2fx_reg_pat[rt].ld_end},
- {REG_SL_START, s5k3e2fx_reg_pat[rt].sl_start},
- {REG_SL_END, s5k3e2fx_reg_pat[rt].sl_end},
- {REG_RX_START, s5k3e2fx_reg_pat[rt].rx_start},
- {REG_S1_START, s5k3e2fx_reg_pat[rt].s1_start},
- {REG_S1_END, s5k3e2fx_reg_pat[rt].s1_end},
- {REG_S1S_START, s5k3e2fx_reg_pat[rt].s1s_start},
- {REG_S1S_END, s5k3e2fx_reg_pat[rt].s1s_end},
- {REG_S3_START, s5k3e2fx_reg_pat[rt].s3_start},
- {REG_S3_END, s5k3e2fx_reg_pat[rt].s3_end},
- {REG_CMP_EN_START, s5k3e2fx_reg_pat[rt].cmp_en_start},
- {REG_CLP_SL_START, s5k3e2fx_reg_pat[rt].clp_sl_start},
- {REG_CLP_SL_END, s5k3e2fx_reg_pat[rt].clp_sl_end},
- {REG_OFF_START, s5k3e2fx_reg_pat[rt].off_start},
- {REG_RMP_EN_START, s5k3e2fx_reg_pat[rt].rmp_en_start},
- {REG_TX_START, s5k3e2fx_reg_pat[rt].tx_start},
- {REG_TX_END, s5k3e2fx_reg_pat[rt].tx_end},
- {REG_STX_WIDTH, s5k3e2fx_reg_pat[rt].stx_width},
- {REG_3152_RESERVED, s5k3e2fx_reg_pat[rt].reg_3152_reserved},
- {REG_315A_RESERVED, s5k3e2fx_reg_pat[rt].reg_315A_reserved},
- {REG_ANALOGUE_GAIN_CODE_GLOBAL_MSB, s5k3e2fx_reg_pat[rt].analogue_gain_code_global_msb},
- {REG_ANALOGUE_GAIN_CODE_GLOBAL_LSB, s5k3e2fx_reg_pat[rt].analogue_gain_code_global_lsb},
- {REG_FINE_INTEGRATION_TIME, s5k3e2fx_reg_pat[rt].fine_integration_time},
- {REG_COARSE_INTEGRATION_TIME, s5k3e2fx_reg_pat[rt].coarse_integration_time},
- {S5K3E2FX_REG_MODE_SELECT, S5K3E2FX_MODE_SELECT_STREAM},
- };
-
- rc = s5k3e2fx_i2c_write_table(&tbl_1[0],
- ARRAY_SIZE(tbl_1));
- if (rc < 0)
- return rc;
-
- num_lperf =
- (uint16_t)((s5k3e2fx_reg_pat[rt].frame_length_lines_msb << 8) & 0xFF00) +
- s5k3e2fx_reg_pat[rt].frame_length_lines_lsb;
-
- num_lperf = num_lperf * s5k3e2fx_ctrl->fps_divider / 0x0400;
-
- tbl_2[0] = (struct s5k3e2fx_i2c_reg_conf) {REG_FRAME_LENGTH_LINES_MSB, (num_lperf & 0xFF00) >> 8};
- tbl_2[1] = (struct s5k3e2fx_i2c_reg_conf) {REG_FRAME_LENGTH_LINES_LSB, (num_lperf & 0x00FF)};
-
- rc = s5k3e2fx_i2c_write_table(&tbl_2[0],
- ARRAY_SIZE(tbl_2));
- if (rc < 0)
- return rc;
-
- mdelay(5);
-
- rc = s5k3e2fx_test(s5k3e2fx_ctrl->set_test);
- if (rc < 0)
- return rc;
- }
- break; /* UPDATE_PERIODIC */
-
- case S_REG_INIT:
- if (rt == S_RES_PREVIEW || rt == S_RES_CAPTURE) {
-
- struct s5k3e2fx_i2c_reg_conf tbl_3[] = {
- {S5K3E2FX_REG_SOFTWARE_RESET, S5K3E2FX_SOFTWARE_RESET},
- {S5K3E2FX_REG_MODE_SELECT, S5K3E2FX_MODE_SELECT_SW_STANDBY},
- /* PLL setting */
- {REG_PRE_PLL_CLK_DIV, s5k3e2fx_reg_pat[rt].pre_pll_clk_div},
- {REG_PLL_MULTIPLIER_MSB, s5k3e2fx_reg_pat[rt].pll_multiplier_msb},
- {REG_PLL_MULTIPLIER_LSB, s5k3e2fx_reg_pat[rt].pll_multiplier_lsb},
- {REG_VT_PIX_CLK_DIV, s5k3e2fx_reg_pat[rt].vt_pix_clk_div},
- {REG_VT_SYS_CLK_DIV, s5k3e2fx_reg_pat[rt].vt_sys_clk_div},
- {REG_OP_PIX_CLK_DIV, s5k3e2fx_reg_pat[rt].op_pix_clk_div},
- {REG_OP_SYS_CLK_DIV, s5k3e2fx_reg_pat[rt].op_sys_clk_div},
- /*Data Format */
- {REG_CCP_DATA_FORMAT_MSB, s5k3e2fx_reg_pat[rt].ccp_data_format_msb},
- {REG_CCP_DATA_FORMAT_LSB, s5k3e2fx_reg_pat[rt].ccp_data_format_lsb},
- /*Output Size */
- {REG_X_OUTPUT_SIZE_MSB, s5k3e2fx_reg_pat[rt].x_output_size_msb},
- {REG_X_OUTPUT_SIZE_LSB, s5k3e2fx_reg_pat[rt].x_output_size_lsb},
- {REG_Y_OUTPUT_SIZE_MSB, s5k3e2fx_reg_pat[rt].y_output_size_msb},
- {REG_Y_OUTPUT_SIZE_LSB, s5k3e2fx_reg_pat[rt].y_output_size_lsb},
- /* Binning */
- {REG_X_EVEN_INC, s5k3e2fx_reg_pat[rt].x_even_inc},
- {REG_X_ODD_INC, s5k3e2fx_reg_pat[rt].x_odd_inc },
- {REG_Y_EVEN_INC, s5k3e2fx_reg_pat[rt].y_even_inc},
- {REG_Y_ODD_INC, s5k3e2fx_reg_pat[rt].y_odd_inc},
- {REG_BINNING_ENABLE, s5k3e2fx_reg_pat[rt].binning_enable},
- /* Frame format */
- {REG_FRAME_LENGTH_LINES_MSB, s5k3e2fx_reg_pat[rt].frame_length_lines_msb},
- {REG_FRAME_LENGTH_LINES_LSB, s5k3e2fx_reg_pat[rt].frame_length_lines_lsb},
- {REG_LINE_LENGTH_PCK_MSB, s5k3e2fx_reg_pat[rt].line_length_pck_msb},
- {REG_LINE_LENGTH_PCK_LSB, s5k3e2fx_reg_pat[rt].line_length_pck_lsb},
- /* MSR setting */
- {REG_SHADE_CLK_ENABLE, s5k3e2fx_reg_pat[rt].shade_clk_enable},
- {REG_SEL_CCP, s5k3e2fx_reg_pat[rt].sel_ccp},
- {REG_VPIX, s5k3e2fx_reg_pat[rt].vpix},
- {REG_CLAMP_ON, s5k3e2fx_reg_pat[rt].clamp_on},
- {REG_OFFSET, s5k3e2fx_reg_pat[rt].offset},
- /* CDS timing setting */
- {REG_LD_START, s5k3e2fx_reg_pat[rt].ld_start},
- {REG_LD_END, s5k3e2fx_reg_pat[rt].ld_end},
- {REG_SL_START, s5k3e2fx_reg_pat[rt].sl_start},
- {REG_SL_END, s5k3e2fx_reg_pat[rt].sl_end},
- {REG_RX_START, s5k3e2fx_reg_pat[rt].rx_start},
- {REG_S1_START, s5k3e2fx_reg_pat[rt].s1_start},
- {REG_S1_END, s5k3e2fx_reg_pat[rt].s1_end},
- {REG_S1S_START, s5k3e2fx_reg_pat[rt].s1s_start},
- {REG_S1S_END, s5k3e2fx_reg_pat[rt].s1s_end},
- {REG_S3_START, s5k3e2fx_reg_pat[rt].s3_start},
- {REG_S3_END, s5k3e2fx_reg_pat[rt].s3_end},
- {REG_CMP_EN_START, s5k3e2fx_reg_pat[rt].cmp_en_start},
- {REG_CLP_SL_START, s5k3e2fx_reg_pat[rt].clp_sl_start},
- {REG_CLP_SL_END, s5k3e2fx_reg_pat[rt].clp_sl_end},
- {REG_OFF_START, s5k3e2fx_reg_pat[rt].off_start},
- {REG_RMP_EN_START, s5k3e2fx_reg_pat[rt].rmp_en_start},
- {REG_TX_START, s5k3e2fx_reg_pat[rt].tx_start},
- {REG_TX_END, s5k3e2fx_reg_pat[rt].tx_end},
- {REG_STX_WIDTH, s5k3e2fx_reg_pat[rt].stx_width},
- {REG_3152_RESERVED, s5k3e2fx_reg_pat[rt].reg_3152_reserved},
- {REG_315A_RESERVED, s5k3e2fx_reg_pat[rt].reg_315A_reserved},
- {REG_ANALOGUE_GAIN_CODE_GLOBAL_MSB, s5k3e2fx_reg_pat[rt].analogue_gain_code_global_msb},
- {REG_ANALOGUE_GAIN_CODE_GLOBAL_LSB, s5k3e2fx_reg_pat[rt].analogue_gain_code_global_lsb},
- {REG_FINE_INTEGRATION_TIME, s5k3e2fx_reg_pat[rt].fine_integration_time},
- {REG_COARSE_INTEGRATION_TIME, s5k3e2fx_reg_pat[rt].coarse_integration_time},
- {S5K3E2FX_REG_MODE_SELECT, S5K3E2FX_MODE_SELECT_STREAM},
- };
-
- /* reset fps_divider */
- s5k3e2fx_ctrl->fps_divider = 1 * 0x0400;
- rc = s5k3e2fx_i2c_write_table(&tbl_3[0],
- ARRAY_SIZE(tbl_3));
- if (rc < 0)
- return rc;
- }
- break; /* case REG_INIT: */
-
- default:
- rc = -EINVAL;
- break;
- } /* switch (rupdate) */
-
- return rc;
-}
-
-static int s5k3e2fx_sensor_open_init(const struct msm_camera_sensor_info *data)
-{
- int32_t rc;
-
- s5k3e2fx_ctrl = kzalloc(sizeof(struct s5k3e2fx_ctrl), GFP_KERNEL);
- if (!s5k3e2fx_ctrl) {
- CDBG("s5k3e2fx_init failed!\n");
- rc = -ENOMEM;
- goto init_done;
- }
-
- s5k3e2fx_ctrl->fps_divider = 1 * 0x00000400;
- s5k3e2fx_ctrl->pict_fps_divider = 1 * 0x00000400;
- s5k3e2fx_ctrl->set_test = S_TEST_OFF;
- s5k3e2fx_ctrl->prev_res = S_QTR_SIZE;
- s5k3e2fx_ctrl->pict_res = S_FULL_SIZE;
-
- if (data)
- s5k3e2fx_ctrl->sensordata = data;
-
- /* enable mclk first */
- msm_camio_clk_rate_set(24000000);
- mdelay(20);
-
- msm_camio_camif_pad_reg_reset();
- mdelay(20);
-
- rc = s5k3e2fx_probe_init_sensor(data);
- if (rc < 0)
- goto init_fail1;
-
- if (s5k3e2fx_ctrl->prev_res == S_QTR_SIZE)
- rc = s5k3e2fx_setting(S_REG_INIT, S_RES_PREVIEW);
- else
- rc = s5k3e2fx_setting(S_REG_INIT, S_RES_CAPTURE);
-
- if (rc < 0) {
- CDBG("s5k3e2fx_setting failed. rc = %d\n", rc);
- goto init_fail1;
- }
-
- /* initialize AF */
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr, 0x3146, 0x3A);
- if (rc < 0)
- goto init_fail1;
-
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr, 0x3130, 0x03);
- if (rc < 0)
- goto init_fail1;
-
- goto init_done;
-
-init_fail1:
- s5k3e2fx_probe_init_done(data);
- kfree(s5k3e2fx_ctrl);
-init_done:
- return rc;
-}
-
-static int32_t s5k3e2fx_power_down(void)
-{
- int32_t rc = 0;
- return rc;
-}
-
-static int s5k3e2fx_sensor_release(void)
-{
- int rc = -EBADF;
-
- down(&s5k3e2fx_sem);
-
- s5k3e2fx_power_down();
-
- gpio_direction_output(s5k3e2fx_ctrl->sensordata->sensor_reset,
- 0);
- gpio_free(s5k3e2fx_ctrl->sensordata->sensor_reset);
-
- kfree(s5k3e2fx_ctrl);
- s5k3e2fx_ctrl = NULL;
-
- CDBG("s5k3e2fx_release completed\n");
-
- up(&s5k3e2fx_sem);
- return rc;
-}
-
-static void s5k3e2fx_get_pict_fps(uint16_t fps, uint16_t *pfps)
-{
- /* input fps is preview fps in Q8 format */
- uint32_t divider; /* Q10 */
-
- divider = (uint32_t)
- ((s5k3e2fx_reg_pat[S_RES_PREVIEW].size_h +
- s5k3e2fx_reg_pat[S_RES_PREVIEW].blk_l) *
- (s5k3e2fx_reg_pat[S_RES_PREVIEW].size_w +
- s5k3e2fx_reg_pat[S_RES_PREVIEW].blk_p)) * 0x00000400 /
- ((s5k3e2fx_reg_pat[S_RES_CAPTURE].size_h +
- s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_l) *
- (s5k3e2fx_reg_pat[S_RES_CAPTURE].size_w +
- s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_p));
-
- /* Verify PCLK settings and frame sizes. */
- *pfps = (uint16_t)(fps * divider / 0x00000400);
-}
-
-static uint16_t s5k3e2fx_get_prev_lines_pf(void)
-{
- return (s5k3e2fx_reg_pat[S_RES_PREVIEW].size_h +
- s5k3e2fx_reg_pat[S_RES_PREVIEW].blk_l);
-}
-
-static uint16_t s5k3e2fx_get_prev_pixels_pl(void)
-{
- return s5k3e2fx_reg_pat[S_RES_PREVIEW].size_w +
- s5k3e2fx_reg_pat[S_RES_PREVIEW].blk_p;
-}
-
-static uint16_t s5k3e2fx_get_pict_lines_pf(void)
-{
- return s5k3e2fx_reg_pat[S_RES_CAPTURE].size_h +
- s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_l;
-}
-
-static uint16_t s5k3e2fx_get_pict_pixels_pl(void)
-{
- return s5k3e2fx_reg_pat[S_RES_CAPTURE].size_w +
- s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_p;
-}
-
-static uint32_t s5k3e2fx_get_pict_max_exp_lc(void)
-{
- uint32_t snapshot_lines_per_frame;
-
- if (s5k3e2fx_ctrl->pict_res == S_QTR_SIZE)
- snapshot_lines_per_frame =
- s5k3e2fx_reg_pat[S_RES_PREVIEW].size_h +
- s5k3e2fx_reg_pat[S_RES_PREVIEW].blk_l;
- else
- snapshot_lines_per_frame = 3961 * 3;
-
- return snapshot_lines_per_frame;
-}
-
-static int32_t s5k3e2fx_set_fps(struct fps_cfg *fps)
-{
- /* input is new fps in Q10 format */
- int32_t rc = 0;
-
- s5k3e2fx_ctrl->fps_divider = fps->fps_div;
-
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr,
- REG_FRAME_LENGTH_LINES_MSB,
- (((s5k3e2fx_reg_pat[S_RES_PREVIEW].size_h +
- s5k3e2fx_reg_pat[S_RES_PREVIEW].blk_l) *
- s5k3e2fx_ctrl->fps_divider / 0x400) & 0xFF00) >> 8);
- if (rc < 0)
- goto set_fps_done;
-
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr,
- REG_FRAME_LENGTH_LINES_LSB,
- (((s5k3e2fx_reg_pat[S_RES_PREVIEW].size_h +
- s5k3e2fx_reg_pat[S_RES_PREVIEW].blk_l) *
- s5k3e2fx_ctrl->fps_divider / 0x400) & 0xFF00));
-
-set_fps_done:
- return rc;
-}
-
-static int32_t s5k3e2fx_write_exp_gain(uint16_t gain, uint32_t line)
-{
- int32_t rc = 0;
-
- uint16_t max_legal_gain = 0x0200;
- uint32_t ll_ratio; /* Q10 */
- uint16_t ll_pck, fl_lines;
- uint16_t offset = 4;
- uint8_t gain_msb, gain_lsb;
- uint8_t intg_t_msb, intg_t_lsb;
- uint8_t ll_pck_msb, ll_pck_lsb, tmp;
-
- struct s5k3e2fx_i2c_reg_conf tbl[2];
-
- CDBG("Line:%d s5k3e2fx_write_exp_gain \n", __LINE__);
-
- if (s5k3e2fx_ctrl->sensormode == SENSOR_PREVIEW_MODE) {
-
- s5k3e2fx_ctrl->my_reg_gain = gain;
- s5k3e2fx_ctrl->my_reg_line_count = (uint16_t)line;
-
- fl_lines = s5k3e2fx_reg_pat[S_RES_PREVIEW].size_h +
- s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_l;
-
- ll_pck = s5k3e2fx_reg_pat[S_RES_PREVIEW].size_w +
- s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_p;
-
- } else {
-
- fl_lines = s5k3e2fx_reg_pat[S_RES_CAPTURE].size_h +
- s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_l;
-
- ll_pck = s5k3e2fx_reg_pat[S_RES_CAPTURE].size_w +
- s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_p;
- }
-
- if (gain > max_legal_gain)
- gain = max_legal_gain;
-
- /* in Q10 */
- line = (line * s5k3e2fx_ctrl->fps_divider);
-
- if (fl_lines < (line / 0x400))
- ll_ratio = (line / (fl_lines - offset));
- else
- ll_ratio = 0x400;
-
- /* update gain registers */
- gain_msb = (gain & 0xFF00) >> 8;
- gain_lsb = gain & 0x00FF;
- tbl[0].waddr = REG_ANALOGUE_GAIN_CODE_GLOBAL_MSB;
- tbl[0].bdata = gain_msb;
- tbl[1].waddr = REG_ANALOGUE_GAIN_CODE_GLOBAL_LSB;
- tbl[1].bdata = gain_lsb;
- rc = s5k3e2fx_i2c_write_table(&tbl[0], ARRAY_SIZE(tbl));
- if (rc < 0)
- goto write_gain_done;
-
- ll_pck = ll_pck * ll_ratio;
- ll_pck_msb = ((ll_pck / 0x400) & 0xFF00) >> 8;
- ll_pck_lsb = (ll_pck / 0x400) & 0x00FF;
- tbl[0].waddr = REG_LINE_LENGTH_PCK_MSB;
- tbl[0].bdata = s5k3e2fx_reg_pat[S_RES_PREVIEW].line_length_pck_msb;
- tbl[1].waddr = REG_LINE_LENGTH_PCK_LSB;
- tbl[1].bdata = s5k3e2fx_reg_pat[S_RES_PREVIEW].line_length_pck_lsb;
- rc = s5k3e2fx_i2c_write_table(&tbl[0], ARRAY_SIZE(tbl));
- if (rc < 0)
- goto write_gain_done;
-
- tmp = (ll_pck * 0x400) / ll_ratio;
- intg_t_msb = (tmp & 0xFF00) >> 8;
- intg_t_lsb = (tmp & 0x00FF);
- tbl[0].waddr = REG_COARSE_INTEGRATION_TIME;
- tbl[0].bdata = intg_t_msb;
- tbl[1].waddr = REG_COARSE_INTEGRATION_TIME_LSB;
- tbl[1].bdata = intg_t_lsb;
- rc = s5k3e2fx_i2c_write_table(&tbl[0], ARRAY_SIZE(tbl));
-
-write_gain_done:
- return rc;
-}
-
-static int32_t s5k3e2fx_set_pict_exp_gain(uint16_t gain, uint32_t line)
-{
- int32_t rc = 0;
-
- CDBG("Line:%d s5k3e2fx_set_pict_exp_gain \n", __LINE__);
-
- rc =
- s5k3e2fx_write_exp_gain(gain, line);
-
- return rc;
-}
-
-static int32_t s5k3e2fx_video_config(int mode, int res)
-{
- int32_t rc;
-
- switch (res) {
- case S_QTR_SIZE:
- rc = s5k3e2fx_setting(S_UPDATE_PERIODIC, S_RES_PREVIEW);
- if (rc < 0)
- return rc;
-
- CDBG("s5k3e2fx sensor configuration done!\n");
- break;
-
- case S_FULL_SIZE:
- rc = s5k3e2fx_setting(S_UPDATE_PERIODIC, S_RES_CAPTURE);
- if (rc < 0)
- return rc;
-
- break;
-
- default:
- return 0;
- } /* switch */
-
- s5k3e2fx_ctrl->prev_res = res;
- s5k3e2fx_ctrl->curr_res = res;
- s5k3e2fx_ctrl->sensormode = mode;
-
- rc =
- s5k3e2fx_write_exp_gain(s5k3e2fx_ctrl->my_reg_gain,
- s5k3e2fx_ctrl->my_reg_line_count);
-
- return rc;
-}
-
-static int32_t s5k3e2fx_snapshot_config(int mode)
-{
- int32_t rc = 0;
-
- rc = s5k3e2fx_setting(S_UPDATE_PERIODIC, S_RES_CAPTURE);
- if (rc < 0)
- return rc;
-
- s5k3e2fx_ctrl->curr_res = s5k3e2fx_ctrl->pict_res;
- s5k3e2fx_ctrl->sensormode = mode;
-
- return rc;
-}
-
-static int32_t s5k3e2fx_raw_snapshot_config(int mode)
-{
- int32_t rc = 0;
-
- rc = s5k3e2fx_setting(S_UPDATE_PERIODIC, S_RES_CAPTURE);
- if (rc < 0)
- return rc;
-
- s5k3e2fx_ctrl->curr_res = s5k3e2fx_ctrl->pict_res;
- s5k3e2fx_ctrl->sensormode = mode;
-
- return rc;
-}
-
-static int32_t s5k3e2fx_set_sensor_mode(int mode, int res)
-{
- int32_t rc = 0;
-
- switch (mode) {
- case SENSOR_PREVIEW_MODE:
- rc = s5k3e2fx_video_config(mode, res);
- break;
-
- case SENSOR_SNAPSHOT_MODE:
- rc = s5k3e2fx_snapshot_config(mode);
- break;
-
- case SENSOR_RAW_SNAPSHOT_MODE:
- rc = s5k3e2fx_raw_snapshot_config(mode);
- break;
-
- default:
- rc = -EINVAL;
- break;
- }
-
- return rc;
-}
-
-static int32_t s5k3e2fx_set_default_focus(void)
-{
- int32_t rc = 0;
-
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr,
- 0x3131, 0);
- if (rc < 0)
- return rc;
-
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr,
- 0x3132, 0);
- if (rc < 0)
- return rc;
-
- s5k3e2fx_ctrl->curr_lens_pos = 0;
-
- return rc;
-}
-
-static int32_t s5k3e2fx_move_focus(int direction, int32_t num_steps)
-{
- int32_t rc = 0;
- int32_t i;
- int16_t step_direction;
- int16_t actual_step;
- int16_t next_pos, pos_offset;
- int16_t init_code = 50;
- uint8_t next_pos_msb, next_pos_lsb;
- int16_t s_move[5];
- uint32_t gain; /* Q10 format */
-
- if (direction == MOVE_NEAR)
- step_direction = 20;
- else if (direction == MOVE_FAR)
- step_direction = -20;
- else {
- CDBG("s5k3e2fx_move_focus failed at line %d ...\n", __LINE__);
- return -EINVAL;
- }
-
- actual_step = step_direction * (int16_t)num_steps;
- pos_offset = init_code + s5k3e2fx_ctrl->curr_lens_pos;
- gain = ((actual_step << 10) / 5) >> 10;
-
- for (i = 0; i <= 4; i++)
- s_move[i] = gain;
-
- /* Ring Damping Code */
- for (i = 0; i <= 4; i++) {
- next_pos = (int16_t)(pos_offset + s_move[i]);
-
- if (next_pos > (738 + init_code))
- next_pos = 738 + init_code;
- else if (next_pos < 0)
- next_pos = 0;
-
- CDBG("next_position in damping mode = %d\n", next_pos);
- /* Writing the Values to the actuator */
- if (next_pos == init_code)
- next_pos = 0x00;
-
- next_pos_msb = next_pos >> 8;
- next_pos_lsb = next_pos & 0x00FF;
-
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr, 0x3131, next_pos_msb);
- if (rc < 0)
- break;
-
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr, 0x3132, next_pos_lsb);
- if (rc < 0)
- break;
-
- pos_offset = next_pos;
- s5k3e2fx_ctrl->curr_lens_pos = pos_offset - init_code;
- if (i < 4)
- mdelay(3);
- }
-
- return rc;
-}
-
-static int s5k3e2fx_sensor_config(void __user *argp)
-{
- struct sensor_cfg_data cdata;
- long rc = 0;
-
- if (copy_from_user(&cdata,
- (void *)argp,
- sizeof(struct sensor_cfg_data)))
- return -EFAULT;
-
- down(&s5k3e2fx_sem);
-
- CDBG("%s: cfgtype = %d\n", __func__, cdata.cfgtype);
- switch (cdata.cfgtype) {
- case CFG_GET_PICT_FPS:
- s5k3e2fx_get_pict_fps(cdata.cfg.gfps.prevfps,
- &(cdata.cfg.gfps.pictfps));
-
- if (copy_to_user((void *)argp, &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PREV_L_PF:
- cdata.cfg.prevl_pf = s5k3e2fx_get_prev_lines_pf();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PREV_P_PL:
- cdata.cfg.prevp_pl = s5k3e2fx_get_prev_pixels_pl();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_L_PF:
- cdata.cfg.pictl_pf = s5k3e2fx_get_pict_lines_pf();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_P_PL:
- cdata.cfg.pictp_pl = s5k3e2fx_get_pict_pixels_pl();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_MAX_EXP_LC:
- cdata.cfg.pict_max_exp_lc =
- s5k3e2fx_get_pict_max_exp_lc();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_SET_FPS:
- case CFG_SET_PICT_FPS:
- rc = s5k3e2fx_set_fps(&(cdata.cfg.fps));
- break;
-
- case CFG_SET_EXP_GAIN:
- rc =
- s5k3e2fx_write_exp_gain(cdata.cfg.exp_gain.gain,
- cdata.cfg.exp_gain.line);
- break;
-
- case CFG_SET_PICT_EXP_GAIN:
- CDBG("Line:%d CFG_SET_PICT_EXP_GAIN \n", __LINE__);
- rc =
- s5k3e2fx_set_pict_exp_gain(
- cdata.cfg.exp_gain.gain,
- cdata.cfg.exp_gain.line);
- break;
-
- case CFG_SET_MODE:
- rc =
- s5k3e2fx_set_sensor_mode(
- cdata.mode, cdata.rs);
- break;
-
- case CFG_PWR_DOWN:
- rc = s5k3e2fx_power_down();
- break;
-
- case CFG_MOVE_FOCUS:
- rc =
- s5k3e2fx_move_focus(
- cdata.cfg.focus.dir,
- cdata.cfg.focus.steps);
- break;
-
- case CFG_SET_DEFAULT_FOCUS:
- rc =
- s5k3e2fx_set_default_focus();
- break;
-
- case CFG_GET_AF_MAX_STEPS:
- case CFG_SET_EFFECT:
- case CFG_SET_LENS_SHADING:
- default:
- rc = -EINVAL;
- break;
- }
-
- up(&s5k3e2fx_sem);
- return rc;
-}
-
-static int s5k3e2fx_sensor_probe(const struct msm_camera_sensor_info *info,
- struct msm_sensor_ctrl *s)
-{
- int rc = 0;
-
- rc = i2c_add_driver(&s5k3e2fx_i2c_driver);
- if (rc < 0 || s5k3e2fx_client == NULL) {
- rc = -ENOTSUPP;
- goto probe_fail;
- }
-
- msm_camio_clk_rate_set(24000000);
- mdelay(20);
-
- rc = s5k3e2fx_probe_init_sensor(info);
- if (rc < 0)
- goto probe_fail;
-
- s->s_init = s5k3e2fx_sensor_open_init;
- s->s_release = s5k3e2fx_sensor_release;
- s->s_config = s5k3e2fx_sensor_config;
- s5k3e2fx_probe_init_done(info);
-
- return rc;
-
-probe_fail:
- CDBG("SENSOR PROBE FAILS!\n");
- return rc;
-}
-
-static int __s5k3e2fx_probe(struct platform_device *pdev)
-{
- return msm_camera_drv_start(pdev, s5k3e2fx_sensor_probe);
-}
-
-static struct platform_driver msm_camera_driver = {
- .probe = __s5k3e2fx_probe,
- .driver = {
- .name = "msm_camera_s5k3e2fx",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init s5k3e2fx_init(void)
-{
- return platform_driver_register(&msm_camera_driver);
-}
-
-module_init(s5k3e2fx_init);
-
diff --git a/trunk/drivers/staging/dream/camera/s5k3e2fx.h b/trunk/drivers/staging/dream/camera/s5k3e2fx.h
deleted file mode 100644
index 69bc75084457..000000000000
--- a/trunk/drivers/staging/dream/camera/s5k3e2fx.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#ifndef CAMSENSOR_S5K3E2FX
-#define CAMSENSOR_S5K3E2FX
-
-#include
-#endif /* CAMSENSOR_S5K3E2FX */
diff --git a/trunk/drivers/staging/dream/generic_gpio.c b/trunk/drivers/staging/dream/generic_gpio.c
deleted file mode 100644
index fe24d38345d0..000000000000
--- a/trunk/drivers/staging/dream/generic_gpio.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/* arch/arm/mach-msm/generic_gpio.c
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include "gpio_chip.h"
-
-#define GPIO_NUM_TO_CHIP_INDEX(gpio) ((gpio)>>5)
-
-struct gpio_state {
- unsigned long flags;
- int refcount;
-};
-
-static DEFINE_SPINLOCK(gpio_chips_lock);
-static LIST_HEAD(gpio_chip_list);
-static struct gpio_chip **gpio_chip_array;
-static unsigned long gpio_chip_array_size;
-
-int register_gpio_chip(struct gpio_chip *new_gpio_chip)
-{
- int err = 0;
- struct gpio_chip *gpio_chip;
- int i;
- unsigned long irq_flags;
- unsigned int chip_array_start_index, chip_array_end_index;
-
- new_gpio_chip->state = kzalloc((new_gpio_chip->end + 1 - new_gpio_chip->start) * sizeof(new_gpio_chip->state[0]), GFP_KERNEL);
- if (new_gpio_chip->state == NULL) {
- printk(KERN_ERR "register_gpio_chip: failed to allocate state\n");
- return -ENOMEM;
- }
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip_array_start_index = GPIO_NUM_TO_CHIP_INDEX(new_gpio_chip->start);
- chip_array_end_index = GPIO_NUM_TO_CHIP_INDEX(new_gpio_chip->end);
- if (chip_array_end_index >= gpio_chip_array_size) {
- struct gpio_chip **new_gpio_chip_array;
- unsigned long new_gpio_chip_array_size = chip_array_end_index + 1;
-
- new_gpio_chip_array = kmalloc(new_gpio_chip_array_size * sizeof(new_gpio_chip_array[0]), GFP_ATOMIC);
- if (new_gpio_chip_array == NULL) {
- printk(KERN_ERR "register_gpio_chip: failed to allocate array\n");
- err = -ENOMEM;
- goto failed;
- }
- for (i = 0; i < gpio_chip_array_size; i++)
- new_gpio_chip_array[i] = gpio_chip_array[i];
- for (i = gpio_chip_array_size; i < new_gpio_chip_array_size; i++)
- new_gpio_chip_array[i] = NULL;
- gpio_chip_array = new_gpio_chip_array;
- gpio_chip_array_size = new_gpio_chip_array_size;
- }
- list_for_each_entry(gpio_chip, &gpio_chip_list, list) {
- if (gpio_chip->start > new_gpio_chip->end) {
- list_add_tail(&new_gpio_chip->list, &gpio_chip->list);
- goto added;
- }
- if (gpio_chip->end >= new_gpio_chip->start) {
- printk(KERN_ERR "register_gpio_source %u-%u overlaps with %u-%u\n",
- new_gpio_chip->start, new_gpio_chip->end,
- gpio_chip->start, gpio_chip->end);
- err = -EBUSY;
- goto failed;
- }
- }
- list_add_tail(&new_gpio_chip->list, &gpio_chip_list);
-added:
- for (i = chip_array_start_index; i <= chip_array_end_index; i++) {
- if (gpio_chip_array[i] == NULL || gpio_chip_array[i]->start > new_gpio_chip->start)
- gpio_chip_array[i] = new_gpio_chip;
- }
-failed:
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
- if (err)
- kfree(new_gpio_chip->state);
- return err;
-}
-
-static struct gpio_chip *get_gpio_chip_locked(unsigned int gpio)
-{
- unsigned long i;
- struct gpio_chip *chip;
-
- i = GPIO_NUM_TO_CHIP_INDEX(gpio);
- if (i >= gpio_chip_array_size)
- return NULL;
- chip = gpio_chip_array[i];
- if (chip == NULL)
- return NULL;
- list_for_each_entry_from(chip, &gpio_chip_list, list) {
- if (gpio < chip->start)
- return NULL;
- if (gpio <= chip->end)
- return chip;
- }
- return NULL;
-}
-
-static int request_gpio(unsigned int gpio, unsigned long flags)
-{
- int err = 0;
- struct gpio_chip *chip;
- unsigned long irq_flags;
- unsigned long chip_index;
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip = get_gpio_chip_locked(gpio);
- if (chip == NULL) {
- err = -EINVAL;
- goto err;
- }
- chip_index = gpio - chip->start;
- if (chip->state[chip_index].refcount == 0) {
- chip->configure(chip, gpio, flags);
- chip->state[chip_index].flags = flags;
- chip->state[chip_index].refcount++;
- } else if ((flags & IRQF_SHARED) && (chip->state[chip_index].flags & IRQF_SHARED))
- chip->state[chip_index].refcount++;
- else
- err = -EBUSY;
-err:
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
- return err;
-}
-
-int gpio_request(unsigned gpio, const char *label)
-{
- return request_gpio(gpio, 0);
-}
-EXPORT_SYMBOL(gpio_request);
-
-void gpio_free(unsigned gpio)
-{
- struct gpio_chip *chip;
- unsigned long irq_flags;
- unsigned long chip_index;
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip = get_gpio_chip_locked(gpio);
- if (chip) {
- chip_index = gpio - chip->start;
- chip->state[chip_index].refcount--;
- }
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
-}
-EXPORT_SYMBOL(gpio_free);
-
-static int gpio_get_irq_num(unsigned int gpio, unsigned int *irqp, unsigned long *irqnumflagsp)
-{
- int ret = -ENOTSUPP;
- struct gpio_chip *chip;
- unsigned long irq_flags;
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip = get_gpio_chip_locked(gpio);
- if (chip && chip->get_irq_num)
- ret = chip->get_irq_num(chip, gpio, irqp, irqnumflagsp);
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
- return ret;
-}
-
-int gpio_to_irq(unsigned gpio)
-{
- int ret, irq;
- ret = gpio_get_irq_num(gpio, &irq, NULL);
- if (ret)
- return ret;
- return irq;
-}
-EXPORT_SYMBOL(gpio_to_irq);
-
-int gpio_configure(unsigned int gpio, unsigned long flags)
-{
- int ret = -ENOTSUPP;
- struct gpio_chip *chip;
- unsigned long irq_flags;
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip = get_gpio_chip_locked(gpio);
- if (chip)
- ret = chip->configure(chip, gpio, flags);
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
- return ret;
-}
-EXPORT_SYMBOL(gpio_configure);
-
-int gpio_direction_input(unsigned gpio)
-{
- return gpio_configure(gpio, GPIOF_INPUT);
-}
-EXPORT_SYMBOL(gpio_direction_input);
-
-int gpio_direction_output(unsigned gpio, int value)
-{
- gpio_set_value(gpio, value);
- return gpio_configure(gpio, GPIOF_DRIVE_OUTPUT);
-}
-EXPORT_SYMBOL(gpio_direction_output);
-
-int gpio_get_value(unsigned gpio)
-{
- int ret = -ENOTSUPP;
- struct gpio_chip *chip;
- unsigned long irq_flags;
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip = get_gpio_chip_locked(gpio);
- if (chip && chip->read)
- ret = chip->read(chip, gpio);
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
- return ret;
-}
-EXPORT_SYMBOL(gpio_get_value);
-
-void gpio_set_value(unsigned gpio, int on)
-{
- int ret = -ENOTSUPP;
- struct gpio_chip *chip;
- unsigned long irq_flags;
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip = get_gpio_chip_locked(gpio);
- if (chip && chip->write)
- ret = chip->write(chip, gpio, on);
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
-}
-EXPORT_SYMBOL(gpio_set_value);
-
-int gpio_read_detect_status(unsigned int gpio)
-{
- int ret = -ENOTSUPP;
- struct gpio_chip *chip;
- unsigned long irq_flags;
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip = get_gpio_chip_locked(gpio);
- if (chip && chip->read_detect_status)
- ret = chip->read_detect_status(chip, gpio);
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
- return ret;
-}
-EXPORT_SYMBOL(gpio_read_detect_status);
-
-int gpio_clear_detect_status(unsigned int gpio)
-{
- int ret = -ENOTSUPP;
- struct gpio_chip *chip;
- unsigned long irq_flags;
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip = get_gpio_chip_locked(gpio);
- if (chip && chip->clear_detect_status)
- ret = chip->clear_detect_status(chip, gpio);
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
- return ret;
-}
-EXPORT_SYMBOL(gpio_clear_detect_status);
diff --git a/trunk/drivers/staging/dream/gpio_axis.c b/trunk/drivers/staging/dream/gpio_axis.c
deleted file mode 100644
index eb54724b1d3a..000000000000
--- a/trunk/drivers/staging/dream/gpio_axis.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/* drivers/input/misc/gpio_axis.c
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include
-#include
-#include
-#include
-#include
-
-struct gpio_axis_state {
- struct input_dev *input_dev;
- struct gpio_event_axis_info *info;
- uint32_t pos;
-};
-
-uint16_t gpio_axis_4bit_gray_map_table[] = {
- [0x0] = 0x0, [0x1] = 0x1, /* 0000 0001 */
- [0x3] = 0x2, [0x2] = 0x3, /* 0011 0010 */
- [0x6] = 0x4, [0x7] = 0x5, /* 0110 0111 */
- [0x5] = 0x6, [0x4] = 0x7, /* 0101 0100 */
- [0xc] = 0x8, [0xd] = 0x9, /* 1100 1101 */
- [0xf] = 0xa, [0xe] = 0xb, /* 1111 1110 */
- [0xa] = 0xc, [0xb] = 0xd, /* 1010 1011 */
- [0x9] = 0xe, [0x8] = 0xf, /* 1001 1000 */
-};
-uint16_t gpio_axis_4bit_gray_map(struct gpio_event_axis_info *info, uint16_t in)
-{
- return gpio_axis_4bit_gray_map_table[in];
-}
-
-uint16_t gpio_axis_5bit_singletrack_map_table[] = {
- [0x10] = 0x00, [0x14] = 0x01, [0x1c] = 0x02, /* 10000 10100 11100 */
- [0x1e] = 0x03, [0x1a] = 0x04, [0x18] = 0x05, /* 11110 11010 11000 */
- [0x08] = 0x06, [0x0a] = 0x07, [0x0e] = 0x08, /* 01000 01010 01110 */
- [0x0f] = 0x09, [0x0d] = 0x0a, [0x0c] = 0x0b, /* 01111 01101 01100 */
- [0x04] = 0x0c, [0x05] = 0x0d, [0x07] = 0x0e, /* 00100 00101 00111 */
- [0x17] = 0x0f, [0x16] = 0x10, [0x06] = 0x11, /* 10111 10110 00110 */
- [0x02] = 0x12, [0x12] = 0x13, [0x13] = 0x14, /* 00010 10010 10011 */
- [0x1b] = 0x15, [0x0b] = 0x16, [0x03] = 0x17, /* 11011 01011 00011 */
- [0x01] = 0x18, [0x09] = 0x19, [0x19] = 0x1a, /* 00001 01001 11001 */
- [0x1d] = 0x1b, [0x15] = 0x1c, [0x11] = 0x1d, /* 11101 10101 10001 */
-};
-uint16_t gpio_axis_5bit_singletrack_map(
- struct gpio_event_axis_info *info, uint16_t in)
-{
- return gpio_axis_5bit_singletrack_map_table[in];
-}
-
-static void gpio_event_update_axis(struct gpio_axis_state *as, int report)
-{
- struct gpio_event_axis_info *ai = as->info;
- int i;
- int change;
- uint16_t state = 0;
- uint16_t pos;
- uint16_t old_pos = as->pos;
- for (i = ai->count - 1; i >= 0; i--)
- state = (state << 1) | gpio_get_value(ai->gpio[i]);
- pos = ai->map(ai, state);
- if (ai->flags & GPIOEAF_PRINT_RAW)
- pr_info("axis %d-%d raw %x, pos %d -> %d\n",
- ai->type, ai->code, state, old_pos, pos);
- if (report && pos != old_pos) {
- if (ai->type == EV_REL) {
- change = (ai->decoded_size + pos - old_pos) %
- ai->decoded_size;
- if (change > ai->decoded_size / 2)
- change -= ai->decoded_size;
- if (change == ai->decoded_size / 2) {
- if (ai->flags & GPIOEAF_PRINT_EVENT)
- pr_info("axis %d-%d unknown direction, "
- "pos %d -> %d\n", ai->type,
- ai->code, old_pos, pos);
- change = 0; /* no closest direction */
- }
- if (ai->flags & GPIOEAF_PRINT_EVENT)
- pr_info("axis %d-%d change %d\n",
- ai->type, ai->code, change);
- input_report_rel(as->input_dev, ai->code, change);
- } else {
- if (ai->flags & GPIOEAF_PRINT_EVENT)
- pr_info("axis %d-%d now %d\n",
- ai->type, ai->code, pos);
- input_event(as->input_dev, ai->type, ai->code, pos);
- }
- input_sync(as->input_dev);
- }
- as->pos = pos;
-}
-
-static irqreturn_t gpio_axis_irq_handler(int irq, void *dev_id)
-{
- struct gpio_axis_state *as = dev_id;
- gpio_event_update_axis(as, 1);
- return IRQ_HANDLED;
-}
-
-int gpio_event_axis_func(struct input_dev *input_dev,
- struct gpio_event_info *info, void **data, int func)
-{
- int ret;
- int i;
- int irq;
- struct gpio_event_axis_info *ai;
- struct gpio_axis_state *as;
-
- ai = container_of(info, struct gpio_event_axis_info, info);
- if (func == GPIO_EVENT_FUNC_SUSPEND) {
- for (i = 0; i < ai->count; i++)
- disable_irq(gpio_to_irq(ai->gpio[i]));
- return 0;
- }
- if (func == GPIO_EVENT_FUNC_RESUME) {
- for (i = 0; i < ai->count; i++)
- enable_irq(gpio_to_irq(ai->gpio[i]));
- return 0;
- }
-
- if (func == GPIO_EVENT_FUNC_INIT) {
- *data = as = kmalloc(sizeof(*as), GFP_KERNEL);
- if (as == NULL) {
- ret = -ENOMEM;
- goto err_alloc_axis_state_failed;
- }
- as->input_dev = input_dev;
- as->info = ai;
-
- input_set_capability(input_dev, ai->type, ai->code);
- if (ai->type == EV_ABS) {
- input_set_abs_params(input_dev, ai->code, 0,
- ai->decoded_size - 1, 0, 0);
- }
- for (i = 0; i < ai->count; i++) {
- ret = gpio_request(ai->gpio[i], "gpio_event_axis");
- if (ret < 0)
- goto err_request_gpio_failed;
- ret = gpio_direction_input(ai->gpio[i]);
- if (ret < 0)
- goto err_gpio_direction_input_failed;
- ret = irq = gpio_to_irq(ai->gpio[i]);
- if (ret < 0)
- goto err_get_irq_num_failed;
- ret = request_irq(irq, gpio_axis_irq_handler,
- IRQF_TRIGGER_RISING |
- IRQF_TRIGGER_FALLING,
- "gpio_event_axis", as);
- if (ret < 0)
- goto err_request_irq_failed;
- }
- gpio_event_update_axis(as, 0);
- return 0;
- }
-
- ret = 0;
- as = *data;
- for (i = ai->count - 1; i >= 0; i--) {
- free_irq(gpio_to_irq(ai->gpio[i]), as);
-err_request_irq_failed:
-err_get_irq_num_failed:
-err_gpio_direction_input_failed:
- gpio_free(ai->gpio[i]);
-err_request_gpio_failed:
- ;
- }
- kfree(as);
- *data = NULL;
-err_alloc_axis_state_failed:
- return ret;
-}
diff --git a/trunk/drivers/staging/dream/gpio_event.c b/trunk/drivers/staging/dream/gpio_event.c
deleted file mode 100644
index 97a511d11f49..000000000000
--- a/trunk/drivers/staging/dream/gpio_event.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/* drivers/input/misc/gpio_event.c
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-
-#include
-#include
-#include
-#include
-#include
-#include
-
-struct gpio_event {
- struct input_dev *input_dev;
- const struct gpio_event_platform_data *info;
- void *state[0];
-};
-
-static int gpio_input_event(
- struct input_dev *dev, unsigned int type, unsigned int code, int value)
-{
- int i;
- int ret = 0;
- int tmp_ret;
- struct gpio_event_info **ii;
- struct gpio_event *ip = input_get_drvdata(dev);
-
- for (i = 0, ii = ip->info->info; i < ip->info->info_count; i++, ii++) {
- if ((*ii)->event) {
- tmp_ret = (*ii)->event(ip->input_dev, *ii,
- &ip->state[i], type, code, value);
- if (tmp_ret)
- ret = tmp_ret;
- }
- }
- return ret;
-}
-
-static int gpio_event_call_all_func(struct gpio_event *ip, int func)
-{
- int i;
- int ret;
- struct gpio_event_info **ii;
-
- if (func == GPIO_EVENT_FUNC_INIT || func == GPIO_EVENT_FUNC_RESUME) {
- ii = ip->info->info;
- for (i = 0; i < ip->info->info_count; i++, ii++) {
- if ((*ii)->func == NULL) {
- ret = -ENODEV;
- pr_err("gpio_event_probe: Incomplete pdata, "
- "no function\n");
- goto err_no_func;
- }
- ret = (*ii)->func(ip->input_dev, *ii, &ip->state[i],
- func);
- if (ret) {
- pr_err("gpio_event_probe: function failed\n");
- goto err_func_failed;
- }
- }
- return 0;
- }
-
- ret = 0;
- i = ip->info->info_count;
- ii = ip->info->info + i;
- while (i > 0) {
- i--;
- ii--;
- (*ii)->func(ip->input_dev, *ii, &ip->state[i], func & ~1);
-err_func_failed:
-err_no_func:
- ;
- }
- return ret;
-}
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-void gpio_event_suspend(struct early_suspend *h)
-{
- struct gpio_event *ip;
- ip = container_of(h, struct gpio_event, early_suspend);
- gpio_event_call_all_func(ip, GPIO_EVENT_FUNC_SUSPEND);
- ip->info->power(ip->info, 0);
-}
-
-void gpio_event_resume(struct early_suspend *h)
-{
- struct gpio_event *ip;
- ip = container_of(h, struct gpio_event, early_suspend);
- ip->info->power(ip->info, 1);
- gpio_event_call_all_func(ip, GPIO_EVENT_FUNC_RESUME);
-}
-#endif
-
-static int __init gpio_event_probe(struct platform_device *pdev)
-{
- int err;
- struct gpio_event *ip;
- struct input_dev *input_dev;
- struct gpio_event_platform_data *event_info;
-
- event_info = pdev->dev.platform_data;
- if (event_info == NULL) {
- pr_err("gpio_event_probe: No pdata\n");
- return -ENODEV;
- }
- if (event_info->name == NULL ||
- event_info->info == NULL ||
- event_info->info_count == 0) {
- pr_err("gpio_event_probe: Incomplete pdata\n");
- return -ENODEV;
- }
- ip = kzalloc(sizeof(*ip) +
- sizeof(ip->state[0]) * event_info->info_count, GFP_KERNEL);
- if (ip == NULL) {
- err = -ENOMEM;
- pr_err("gpio_event_probe: Failed to allocate private data\n");
- goto err_kp_alloc_failed;
- }
- platform_set_drvdata(pdev, ip);
-
- input_dev = input_allocate_device();
- if (input_dev == NULL) {
- err = -ENOMEM;
- pr_err("gpio_event_probe: Failed to allocate input device\n");
- goto err_input_dev_alloc_failed;
- }
- input_set_drvdata(input_dev, ip);
- ip->input_dev = input_dev;
- ip->info = event_info;
- if (event_info->power) {
-#ifdef CONFIG_HAS_EARLYSUSPEND
- ip->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1;
- ip->early_suspend.suspend = gpio_event_suspend;
- ip->early_suspend.resume = gpio_event_resume;
- register_early_suspend(&ip->early_suspend);
-#endif
- ip->info->power(ip->info, 1);
- }
-
- input_dev->name = ip->info->name;
- input_dev->event = gpio_input_event;
-
- err = gpio_event_call_all_func(ip, GPIO_EVENT_FUNC_INIT);
- if (err)
- goto err_call_all_func_failed;
-
- err = input_register_device(input_dev);
- if (err) {
- pr_err("gpio_event_probe: Unable to register %s input device\n",
- input_dev->name);
- goto err_input_register_device_failed;
- }
-
- return 0;
-
-err_input_register_device_failed:
- gpio_event_call_all_func(ip, GPIO_EVENT_FUNC_UNINIT);
-err_call_all_func_failed:
- if (event_info->power) {
-#ifdef CONFIG_HAS_EARLYSUSPEND
- unregister_early_suspend(&ip->early_suspend);
-#endif
- ip->info->power(ip->info, 0);
- }
- input_free_device(input_dev);
-err_input_dev_alloc_failed:
- kfree(ip);
-err_kp_alloc_failed:
- return err;
-}
-
-static int gpio_event_remove(struct platform_device *pdev)
-{
- struct gpio_event *ip = platform_get_drvdata(pdev);
-
- gpio_event_call_all_func(ip, GPIO_EVENT_FUNC_UNINIT);
- if (ip->info->power) {
-#ifdef CONFIG_HAS_EARLYSUSPEND
- unregister_early_suspend(&ip->early_suspend);
-#endif
- ip->info->power(ip->info, 0);
- }
- input_unregister_device(ip->input_dev);
- kfree(ip);
- return 0;
-}
-
-static struct platform_driver gpio_event_driver = {
- .probe = gpio_event_probe,
- .remove = gpio_event_remove,
- .driver = {
- .name = GPIO_EVENT_DEV_NAME,
- },
-};
-
-static int __devinit gpio_event_init(void)
-{
- return platform_driver_register(&gpio_event_driver);
-}
-
-static void __exit gpio_event_exit(void)
-{
- platform_driver_unregister(&gpio_event_driver);
-}
-
-module_init(gpio_event_init);
-module_exit(gpio_event_exit);
-
-MODULE_DESCRIPTION("GPIO Event Driver");
-MODULE_LICENSE("GPL");
-
diff --git a/trunk/drivers/staging/dream/gpio_input.c b/trunk/drivers/staging/dream/gpio_input.c
deleted file mode 100644
index ca29e5eb070a..000000000000
--- a/trunk/drivers/staging/dream/gpio_input.c
+++ /dev/null
@@ -1,337 +0,0 @@
-/* drivers/input/misc/gpio_input.c
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include