From 07bcf6bd3e81b86b6e2f14fa19b8e5e4885e1913 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Fri, 16 May 2008 22:55:26 +0200 Subject: [PATCH] --- yaml --- r: 96834 b: refs/heads/master c: e9623b35599fcdbc00c16535cbefbb4d5578f4ab h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/x86/kernel/process.c | 29 ++++++++++++++++++++++++++++- 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 0f8df01bf151..5bb33522c36c 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 31f4d870b02e1590260ab7f2a9ff74306bd27e88 +refs/heads/master: e9623b35599fcdbc00c16535cbefbb4d5578f4ab diff --git a/trunk/arch/x86/kernel/process.c b/trunk/arch/x86/kernel/process.c index c7b6a694ca22..ba370dc8685b 100644 --- a/trunk/arch/x86/kernel/process.c +++ b/trunk/arch/x86/kernel/process.c @@ -110,6 +110,33 @@ static void poll_idle(void) cpu_relax(); } +/* + * mwait selection logic: + * + * It depends on the CPU. For AMD CPUs that support MWAIT this is + * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings + * then depend on a clock divisor and current Pstate of the core. If + * all cores of a processor are in halt state (C1) the processor can + * enter the C1E (C1 enhanced) state. If mwait is used this will never + * happen. + * + * idle=mwait overrides this decision and forces the usage of mwait. + */ +static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c) +{ + if (force_mwait) + return 1; + + if (c->x86_vendor == X86_VENDOR_AMD) { + switch(c->x86) { + case 0x10: + case 0x11: + return 0; + } + } + return 1; +} + void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) { static int selected; @@ -122,7 +149,7 @@ void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) " performance may degrade.\n"); } #endif - if (cpu_has(c, X86_FEATURE_MWAIT)) { + if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { /* * Skip, if setup has overridden idle. * One CPU supports mwait => All CPUs supports mwait