From 0827ed1e36ebb634908b719a278b0f5533e84bbd Mon Sep 17 00:00:00 2001 From: Jaecheol Lee Date: Thu, 2 Feb 2012 12:31:01 +0900 Subject: [PATCH] --- yaml --- r: 295724 b: refs/heads/master c: d074de8ef5a8b241c129690014138fcadcd72bc4 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-exynos/include/mach/regs-clock.h | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 62b5cd29c23e..64b9665fa434 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: a2b9676db08b3be717af16e333396a97eeee1745 +refs/heads/master: d074de8ef5a8b241c129690014138fcadcd72bc4 diff --git a/trunk/arch/arm/mach-exynos/include/mach/regs-clock.h b/trunk/arch/arm/mach-exynos/include/mach/regs-clock.h index 790f525d1557..b1a2aeb256fe 100644 --- a/trunk/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/trunk/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -160,6 +160,15 @@ #define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) #define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24) #define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) +#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28 +#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT) + +#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0 +#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) +#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4 +#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) +#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8 +#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT) #define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0) #define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)