diff --git a/[refs] b/[refs]
index 3a8d97fa5b97..af553083e80b 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 4bbd10fd312f50de74ba53f6cb968986da5dfe92
+refs/heads/master: e62687f995fd7ba0b68c3b0a4f4d9fd9d1c54ec2
diff --git a/trunk/include/asm-blackfin/mach-bf561/cdefBF561.h b/trunk/include/asm-blackfin/mach-bf561/cdefBF561.h
index 6e87ab269ffe..73d4d65249cd 100644
--- a/trunk/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ b/trunk/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -83,9 +83,9 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 
 /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
 #define bfin_read_SWRST()                    bfin_read_SICA_SWRST()
-#define bfin_write_SWRST()                   bfin_write_SICA_SWRST()
+#define bfin_write_SWRST(val)                bfin_write_SICA_SWRST(val)
 #define bfin_read_SYSCR()                    bfin_read_SICA_SYSCR()
-#define bfin_write_SYSCR()                   bfin_write_SICA_SYSCR()
+#define bfin_write_SYSCR(val)                bfin_write_SICA_SYSCR(val)
 
 /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
 #define bfin_read_SICA_SWRST()               bfin_read16(SICA_SWRST)