From 09a08aab29156f1c13ca4644b47e2477ecb6f21c Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 26 Oct 2012 10:58:12 +0200 Subject: [PATCH] --- yaml --- r: 345196 b: refs/heads/master c: cd986abbac6044c76b95fd512bc62329ef9959d0 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_display.c | 8 +++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index e70e87cd298e..62d47228bd52 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 4a0833ec48d3411042c0ccee3daec1cbca4c1999 +refs/heads/master: cd986abbac6044c76b95fd512bc62329ef9959d0 diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index 545e62fa8c77..54b1794c3403 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -2700,9 +2700,6 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) int pipe = intel_crtc->pipe; u32 reg, temp; - /* Write the TU size bits so error detection works */ - I915_WRITE(FDI_RX_TUSIZE1(pipe), - I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ reg = FDI_RX_CTL(pipe); @@ -3003,6 +3000,11 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) assert_transcoder_disabled(dev_priv, pipe); + /* Write the TU size bits before fdi link training, so that error + * detection works. */ + I915_WRITE(FDI_RX_TUSIZE1(pipe), + I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); + /* For PCH output, training FDI link */ dev_priv->display.fdi_link_train(crtc);