From 09c7240b41aa949c2dd525cfe1da8ff706cda904 Mon Sep 17 00:00:00 2001
From: Will Deacon <will.deacon@arm.com>
Date: Fri, 25 Nov 2011 19:23:36 +0100
Subject: [PATCH] --- yaml --- r: 276157 b: refs/heads/master c:
 fe41db7b3aca512e19b8ef4fbd5ad55545005d25 h: refs/heads/master i:   276155:
 e6b8b05320d3fd75dbba7b9a5a8d6001dcf26f8d v: v3

---
 [refs]                      |  2 +-
 trunk/arch/arm/common/gic.c | 13 ++++++++-----
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/[refs] b/[refs]
index e7e9263d69bf..e6f542645609 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: abdd7b91dab2f8b2e32e90e4b7e809ffb462a662
+refs/heads/master: fe41db7b3aca512e19b8ef4fbd5ad55545005d25
diff --git a/trunk/arch/arm/common/gic.c b/trunk/arch/arm/common/gic.c
index 43240f315dea..410a546060a2 100644
--- a/trunk/arch/arm/common/gic.c
+++ b/trunk/arch/arm/common/gic.c
@@ -582,13 +582,16 @@ void __init gic_init(unsigned int gic_nr, int irq_start,
 	 * For primary GICs, skip over SGIs.
 	 * For secondary GICs, skip over PPIs, too.
 	 */
+	domain->hwirq_base = 32;
 	if (gic_nr == 0) {
 		gic_cpu_base_addr = cpu_base;
-		domain->hwirq_base = 16;
-		if (irq_start > 0)
-			irq_start = (irq_start & ~31) + 16;
-	} else
-		domain->hwirq_base = 32;
+
+		if ((irq_start & 31) > 0) {
+			domain->hwirq_base = 16;
+			if (irq_start != -1)
+				irq_start = (irq_start & ~31) + 16;
+		}
+	}
 
 	/*
 	 * Find out how many interrupts are supported.