From 0a73be85f8350c3ae2f829f26881cc626a46b917 Mon Sep 17 00:00:00 2001 From: Martin Peres Date: Mon, 4 Jul 2011 09:41:34 +1000 Subject: [PATCH] --- yaml --- r: 269614 b: refs/heads/master c: f3f2f54e11ff6f3f39a108bfcf7e074b282e3a50 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/nouveau/nv04_pm.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 1eed91b59a72..9fd9aea9b8da 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 591b06d73bb8a2da879b1159342b8be192bf1119 +refs/heads/master: f3f2f54e11ff6f3f39a108bfcf7e074b282e3a50 diff --git a/trunk/drivers/gpu/drm/nouveau/nv04_pm.c b/trunk/drivers/gpu/drm/nouveau/nv04_pm.c index eb1c70dd82ed..9ae92a87b8cc 100644 --- a/trunk/drivers/gpu/drm/nouveau/nv04_pm.c +++ b/trunk/drivers/gpu/drm/nouveau/nv04_pm.c @@ -68,6 +68,7 @@ void nv04_pm_clock_set(struct drm_device *dev, void *pre_state) { struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; struct nv04_pm_state *state = pre_state; u32 reg = state->pll.reg; @@ -85,6 +86,9 @@ nv04_pm_clock_set(struct drm_device *dev, void *pre_state) nv_mask(dev, 0x1002c0, 0, 1 << 8); } + if (reg == NV_PRAMDAC_NVPLL_COEFF) + ptimer->init(dev); + kfree(state); }