From 0a90b3f9d03381f62555222c9e6c474bd33a5ed5 Mon Sep 17 00:00:00 2001 From: Bala Shanmugam Date: Mon, 15 Oct 2012 15:29:48 +0530 Subject: [PATCH] --- yaml --- r: 340979 b: refs/heads/master c: b55f6bb7c3f890c3d537516efa8746a4784c058d h: refs/heads/master i: 340977: e165e4cd755b45c6d95d95940bb8136691b1d112 340975: c6dda4f01e8b9d03897f44de362e1a52728c0817 v: v3 --- [refs] | 2 +- trunk/drivers/net/wireless/ath/ath9k/ar9003_mci.c | 6 ++++++ trunk/drivers/net/wireless/ath/ath9k/ar9003_phy.h | 1 + 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 942316fc15d6..f19e7f2dc682 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: d9575dad59de382dd1f1ddcaa6de38d9844691fe +refs/heads/master: b55f6bb7c3f890c3d537516efa8746a4784c058d diff --git a/trunk/drivers/net/wireless/ath/ath9k/ar9003_mci.c b/trunk/drivers/net/wireless/ath/ath9k/ar9003_mci.c index b2b994147aeb..c46d8f18d81d 100644 --- a/trunk/drivers/net/wireless/ath/ath9k/ar9003_mci.c +++ b/trunk/drivers/net/wireless/ath/ath9k/ar9003_mci.c @@ -750,6 +750,9 @@ int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan, mci_hw->bt_state = MCI_BT_AWAKE; + REG_CLR_BIT(ah, AR_PHY_TIMING4, + 1 << AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT); + if (caldata) { caldata->done_txiqcal_once = false; caldata->done_txclcal_once = false; @@ -759,6 +762,9 @@ int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan, if (!ath9k_hw_init_cal(ah, chan)) return -EIO; + REG_SET_BIT(ah, AR_PHY_TIMING4, + 1 << AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT); + exit: ar9003_mci_enable_interrupt(ah); return 0; diff --git a/trunk/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/trunk/drivers/net/wireless/ath/ath9k/ar9003_phy.h index 9a48e3d2f231..8f585233a788 100644 --- a/trunk/drivers/net/wireless/ath/ath9k/ar9003_phy.h +++ b/trunk/drivers/net/wireless/ath/ath9k/ar9003_phy.h @@ -32,6 +32,7 @@ #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c) #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc) #define AR_PHY_TX_IQCAL_CONTROL_3 (AR_CHAN_BASE + 0xb0) +#define AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT 16 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20