From 0ab332fb8c31b9486c24c7d7c80a1ff0b4b78bca Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Thu, 18 Oct 2012 18:06:10 +0200 Subject: [PATCH] --- yaml --- r: 340005 b: refs/heads/master c: eebdb17287443408c979dbc1cee594f6b770bc68 h: refs/heads/master i: 340003: 86b7c3f8ae4638f898dd00243c04618a10f5ec45 v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-imx/clk-imx51-imx53.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index d688a5ab3570..55e81e3b49fb 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 3ab3a350200c14350220fffde893f3afb640fd25 +refs/heads/master: eebdb17287443408c979dbc1cee594f6b770bc68 diff --git a/trunk/arch/arm/mach-imx/clk-imx51-imx53.c b/trunk/arch/arm/mach-imx/clk-imx51-imx53.c index abb71f6b4d60..6cb97952bbfb 100644 --- a/trunk/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/trunk/arch/arm/mach-imx/clk-imx51-imx53.c @@ -466,6 +466,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can"); clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can"); clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can"); + clk_register_clkdev(clk[dummy], NULL, "53fa4000.rtc"); /* set SDHC root clock to 200MHZ*/ clk_set_rate(clk[esdhc_a_podf], 200000000);