From 0acd33a11899e33e09f37c585258a8f4162a3c21 Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Wed, 27 Sep 2006 15:00:04 +0900
Subject: [PATCH] --- yaml --- r: 36255 b: refs/heads/master c:
 b7e108ee63624176af85b97d4d80bef6fe099395 h: refs/heads/master i:   36253:
 bed4b6a1abb105f529311ba76f7ef14b883a0c7a   36251:
 09c6e36555a3e38d150a96eb51971ae2714dc1e6   36247:
 af00eb2d378cd534ccfb4570fa39050d3980144f   36239:
 afa4c25ab06df4b7bf100b8f913624abe182d730   36223:
 d653080ab91fbf6d709672186ab539949c9e6274 v: v3

---
 [refs]                      |  2 +-
 trunk/arch/sh/kernel/head.S | 36 +++++++++++++++++++++++++++++++-----
 2 files changed, 32 insertions(+), 6 deletions(-)

diff --git a/[refs] b/[refs]
index 02464adb1965..e62ea1d39bd4 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 298476220d1f793ca0ac6c9e5dc817e1ad3e9851
+refs/heads/master: b7e108ee63624176af85b97d4d80bef6fe099395
diff --git a/trunk/arch/sh/kernel/head.S b/trunk/arch/sh/kernel/head.S
index 00cd4708ef46..c5e363872b91 100644
--- a/trunk/arch/sh/kernel/head.S
+++ b/trunk/arch/sh/kernel/head.S
@@ -12,6 +12,17 @@
  */
 #include <linux/linkage.h>
 
+#ifdef CONFIG_CPU_SH4A
+#define SYNCO()		synco
+
+#define PREFI(label, reg)	\
+	mov.l	label, reg;	\
+	prefi	@reg
+#else
+#define SYNCO()
+#define PREFI(label, reg)
+#endif
+
 	.section	.empty_zero_page, "aw"
 ENTRY(empty_zero_page)
 	.long	1		/* MOUNT_ROOT_RDONLY */
@@ -42,6 +53,17 @@ ENTRY(_stext)
 	!			Initialize global interrupt mask
 	mov	#0, r0
 	ldc	r0, r6_bank
+
+	/*
+	 * Prefetch if possible to reduce cache miss penalty.
+	 *
+	 * We do this early on for SH-4A as a micro-optimization,
+	 * as later on we will have speculative execution enabled
+	 * and this will become less of an issue.
+	 */
+	PREFI(5f, r0)
+	PREFI(6f, r0)
+
 	!
 	mov.l	2f, r0
 	mov	r0, r15		! Set initial r15 (stack pointer)
@@ -49,11 +71,7 @@ ENTRY(_stext)
 	shll8	r1		! r1 = 8192
 	sub	r1, r0		!
 	ldc	r0, r7_bank	! ... and initial thread_info
-	!
-	!			Additional CPU initialization
-	mov.l	6f, r0
-	jsr	@r0
-	 nop
+
 	!			Clear BSS area
 	mov.l	3f, r1
 	add	#4, r1
@@ -62,6 +80,14 @@ ENTRY(_stext)
 9:	cmp/hs	r2, r1
 	bf/s	9b		! while (r1 < r2)
 	 mov.l	r0,@-r2
+
+	!			Additional CPU initialization
+	mov.l	6f, r0
+	jsr	@r0
+	 nop
+
+	SYNCO()			! Wait for pending instructions..
+
 	!			Start kernel
 	mov.l	5f, r0
 	jmp	@r0