From 0af80838af45f8b1c67787a9b26c928b0e4fcfb7 Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Mon, 25 Jul 2011 11:13:13 +1000 Subject: [PATCH] --- yaml --- r: 258425 b: refs/heads/master c: 933b44732caad0c3b65224453c54846c75d97936 h: refs/heads/master i: 258423: 976c394ee7642d1865452bcafe6e1643611f0726 v: v3 --- [refs] | 2 +- trunk/drivers/staging/gma500/psb_intel_display.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 72848ae2cfb1..cf43c37ca1b4 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f1f3b8eab7491b6d9c2f03dfaaa7cb66a156f94c +refs/heads/master: 933b44732caad0c3b65224453c54846c75d97936 diff --git a/trunk/drivers/staging/gma500/psb_intel_display.c b/trunk/drivers/staging/gma500/psb_intel_display.c index 4f47d09d65de..09e378d5ddcb 100644 --- a/trunk/drivers/staging/gma500/psb_intel_display.c +++ b/trunk/drivers/staging/gma500/psb_intel_display.c @@ -331,7 +331,7 @@ static bool psb_intel_find_best_PLL(struct drm_crtc *crtc, int target, void psb_intel_wait_for_vblank(struct drm_device *dev) { /* Wait for 20ms, i.e. one cycle at 50hz. */ - udelay(20000); + mdelay(20); } int psb_intel_pipe_set_base(struct drm_crtc *crtc,