diff --git a/[refs] b/[refs] index dbc176e46205..27fc782434ce 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: bead4375731ad283cccbcbcb55bc7549c9746168 +refs/heads/master: 65707fb3794e9cf75665f9ef91cfb07c50d3ffa5 diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index 15b603cb577d..553b7cf17bfb 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -813,7 +813,7 @@ config ARCH_OMAP select GENERIC_CLOCKEVENTS select ARCH_HAS_HOLES_MEMORYMODEL help - Support for TI's OMAP platform (OMAP1/2/3/4). + Support for TI's OMAP platform (OMAP1 and OMAP2). config PLAT_SPEAR bool "ST SPEAr" diff --git a/trunk/arch/arm/configs/n8x0_defconfig b/trunk/arch/arm/configs/n8x0_defconfig new file mode 100644 index 000000000000..56aebb69411d --- /dev/null +++ b/trunk/arch/arm/configs/n8x0_defconfig @@ -0,0 +1,94 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_OMAP=y +CONFIG_ARCH_OMAP2=y +CONFIG_OMAP_RESET_CLOCKS=y +# CONFIG_OMAP_MUX is not set +# CONFIG_OMAP_MCBSP is not set +CONFIG_OMAP_MBOX_FWK=y +CONFIG_OMAP_32K_TIMER=y +CONFIG_ARCH_OMAP2420=y +CONFIG_MACH_NOKIA_N8X0=y +CONFIG_AEABI=y +CONFIG_LEDS=y +CONFIG_ZBOOT_ROM_TEXT=0x10C08000 +CONFIG_ZBOOT_ROM_BSS=0x10200000 +CONFIG_CMDLINE="root=/dev/mmcblk0p2 console=ttyS2,115200n8 debug earlyprintk rootwait" +CONFIG_FPE_NWFPE=y +CONFIG_VFP=y +CONFIG_PM=y +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_IPV6 is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_ONENAND=y +CONFIG_MTD_ONENAND_OMAP2=y +CONFIG_MTD_ONENAND_OTP=y +CONFIG_BLK_DEV_RAM=y +# CONFIG_MISC_DEVICES is not set +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_OMAP=y +CONFIG_SPI=y +CONFIG_SPI_OMAP24XX=y +# CONFIG_HWMON is not set +CONFIG_MENELAUS=y +CONFIG_REGULATOR=y +# CONFIG_VGA_CONSOLE is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_SUSPEND=y +# CONFIG_USB_OTG_WHITELIST is not set +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_OTG=y +CONFIG_USB_GADGET_MUSB_HDRC=y +# CONFIG_MUSB_PIO_ONLY is not set +CONFIG_USB_MUSB_DEBUG=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DEBUG=y +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_ETH=m +CONFIG_USB_ETH_EEM=y +CONFIG_MMC=y +CONFIG_MMC_OMAP=y +CONFIG_EXT3_FS=y +CONFIG_INOTIFY=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_LZO=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_INFO=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +CONFIG_CRC_CCITT=y diff --git a/trunk/arch/arm/configs/omap2plus_defconfig b/trunk/arch/arm/configs/omap3_defconfig similarity index 91% rename from trunk/arch/arm/configs/omap2plus_defconfig rename to trunk/arch/arm/configs/omap3_defconfig index 7deec89872c7..5db9a6be2054 100644 --- a/trunk/arch/arm/configs/omap2plus_defconfig +++ b/trunk/arch/arm/configs/omap3_defconfig @@ -53,18 +53,18 @@ CONFIG_MACH_SBC3530=y CONFIG_MACH_OMAP_3630SDP=y CONFIG_MACH_OMAP_4430SDP=y CONFIG_ARM_THUMBEE=y -CONFIG_ARM_L1_CACHE_SHIFT=5 -CONFIG_ARM_ERRATA_411920=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y -CONFIG_SMP=y -# CONFIG_LOCAL_TIMERS is not set CONFIG_AEABI=y CONFIG_LEDS=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyS2,115200" CONFIG_KEXEC=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_FPE_NWFPE=y CONFIG_VFP=y CONFIG_NEON=y @@ -87,23 +87,23 @@ CONFIG_IP_PNP_RARP=y # CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_NETFILTER=y -CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=y CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m +CONFIG_BT_BNEP=y CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m -CONFIG_BT_HCIUART=m +CONFIG_BT_HIDP=y +CONFIG_BT_HCIUART=y CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBPA10X=m -CONFIG_CFG80211=m -CONFIG_MAC80211=m +CONFIG_BT_HCIBCM203X=y +CONFIG_BT_HCIBPA10X=y +CONFIG_CFG80211=y +CONFIG_MAC80211=y CONFIG_MAC80211_RC_PID=y CONFIG_MAC80211_RC_DEFAULT_PID=y CONFIG_MAC80211_LEDS=y @@ -137,11 +137,9 @@ CONFIG_SMSC_PHY=y CONFIG_NET_ETHERNET=y CONFIG_SMC91X=y CONFIG_SMSC911X=y -CONFIG_KS8851=y -CONFIG_KS8851_MLL=y -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_USB=m -CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS=y +CONFIG_LIBERTAS_USB=y +CONFIG_LIBERTAS_SDIO=y CONFIG_LIBERTAS_DEBUG=y CONFIG_USB_USBNET=y CONFIG_USB_ALI_M5632=y @@ -203,8 +201,8 @@ CONFIG_FONTS=y CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_LOGO=y -CONFIG_SOUND=m -CONFIG_SND=m +CONFIG_SOUND=y +CONFIG_SND=y CONFIG_SND_MIXER_OSS=y CONFIG_SND_PCM_OSS=y CONFIG_SND_VERBOSE_PRINTK=y @@ -220,9 +218,9 @@ CONFIG_USB_DEVICEFS=y CONFIG_USB_SUSPEND=y # CONFIG_USB_OTG_WHITELIST is not set CONFIG_USB_MON=y -# CONFIG_USB_MUSB_HDRC is not set -# CONFIG_USB_MUSB_OTG is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_OTG=y +CONFIG_USB_GADGET_MUSB_HDRC=y CONFIG_USB_MUSB_DEBUG=y CONFIG_USB_WDM=y CONFIG_USB_STORAGE=y @@ -278,11 +276,12 @@ CONFIG_DEBUG_KERNEL=y CONFIG_SCHEDSTATS=y CONFIG_TIMER_STATS=y CONFIG_PROVE_LOCKING=y -# CONFIG_LOCK_STAT is not set +CONFIG_LOCK_STAT=y CONFIG_DEBUG_SPINLOCK_SLEEP=y # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO=y # CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_DEBUG_LL=y CONFIG_SECURITY=y CONFIG_CRYPTO_MICHAEL_MIC=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/trunk/arch/arm/configs/omap_4430sdp_defconfig b/trunk/arch/arm/configs/omap_4430sdp_defconfig new file mode 100644 index 000000000000..14c1e18c648f --- /dev/null +++ b/trunk/arch/arm/configs/omap_4430sdp_defconfig @@ -0,0 +1,125 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_ELF_CORE is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_OMAP=y +CONFIG_ARCH_OMAP4=y +# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set +# CONFIG_ARCH_OMAP2 is not set +# CONFIG_ARCH_OMAP3 is not set +# CONFIG_OMAP_MUX is not set +CONFIG_OMAP_32K_TIMER=y +CONFIG_OMAP_DM_TIMER=y +CONFIG_MACH_OMAP_4430SDP=y +# CONFIG_ARM_THUMB is not set +CONFIG_PL310_ERRATA_588369=y +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +# CONFIG_LOCAL_TIMERS is not set +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS2,115200n8 initrd=0x81600000,20M ramdisk_size=20480" +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_FW_LOADER is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_MISC_DEVICES is not set +CONFIG_NETDEVICES=y +CONFIG_NET_ETHERNET=y +CONFIG_KS8851=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_OMAP=y +CONFIG_SPI=y +CONFIG_SPI_OMAP24XX=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_OMAP_WATCHDOG=y +CONFIG_TWL4030_CORE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_TWL4030=y +# CONFIG_VGA_CONSOLE is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_OMAP_HS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_TWL4030=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_INOTIFY=y +CONFIG_QUOTA=y +CONFIG_QFMT_V2=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DETECT_SOFTLOCKUP is not set +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRC_CCITT=y +CONFIG_CRC_T10DIF=y +CONFIG_LIBCRC32C=y diff --git a/trunk/arch/arm/configs/omap_generic_2420_defconfig b/trunk/arch/arm/configs/omap_generic_2420_defconfig new file mode 100644 index 000000000000..ac08e51180dd --- /dev/null +++ b/trunk/arch/arm/configs/omap_generic_2420_defconfig @@ -0,0 +1,37 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_OMAP=y +CONFIG_ARCH_OMAP2=y +# CONFIG_OMAP_MUX is not set +CONFIG_MACH_OMAP_GENERIC=y +CONFIG_ARCH_OMAP2420=y +CONFIG_LEDS=y +CONFIG_ZBOOT_ROM_TEXT=0x10C08000 +CONFIG_ZBOOT_ROM_BSS=0x10200000 +CONFIG_FPE_NWFPE=y +CONFIG_BLK_DEV_RAM=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y +CONFIG_VIDEO_OUTPUT_CONTROL=m +# CONFIG_VGA_CONSOLE is not set +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_INOTIFY=y +CONFIG_ROMFS_FS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_LL=y +CONFIG_CRC_CCITT=y diff --git a/trunk/arch/arm/mach-omap1/Makefile b/trunk/arch/arm/mach-omap1/Makefile index 9a304d854e33..facfaeb1ae5c 100644 --- a/trunk/arch/arm/mach-omap1/Makefile +++ b/trunk/arch/arm/mach-omap1/Makefile @@ -12,7 +12,7 @@ obj-$(CONFIG_OMAP_MPU_TIMER) += time.o obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o # Power Management -obj-$(CONFIG_PM) += pm.o sleep.o pm_bus.o +obj-$(CONFIG_PM) += pm.o sleep.o # DSP obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o diff --git a/trunk/arch/arm/mach-omap1/board-htcherald.c b/trunk/arch/arm/mach-omap1/board-htcherald.c index 7ea75c11653c..311899ff5ffc 100644 --- a/trunk/arch/arm/mach-omap1/board-htcherald.c +++ b/trunk/arch/arm/mach-omap1/board-htcherald.c @@ -30,13 +30,6 @@ #include #include #include -#include -#include -#include -#include -#include -#include -#include #include #include @@ -46,7 +39,6 @@ #include #include #include -#include #include @@ -60,123 +52,13 @@ #define OMAP_LCDC_CTRL_LCD_EN (1 << 0) #define OMAP_LCDC_STAT_DONE (1 << 0) -/* GPIO definitions for the power button and keyboard slide switch */ -#define HTCHERALD_GPIO_POWER 139 -#define HTCHERALD_GPIO_SLIDE 174 -#define HTCHERALD_GIRQ_BTNS 141 - -/* GPIO definitions for the touchscreen */ -#define HTCHERALD_GPIO_TS 76 - -/* HTCPLD definitions */ - -/* - * CPLD Logic - * - * Chip 3 - 0x03 - * - * Function 7 6 5 4 3 2 1 0 - * ------------------------------------ - * DPAD light x x x x x x x 1 - * SoundDev x x x x 1 x x x - * Screen white 1 x x x x x x x - * MMC power on x x x x x 1 x x - * Happy times (n) 0 x x x x 1 x x - * - * Chip 4 - 0x04 - * - * Function 7 6 5 4 3 2 1 0 - * ------------------------------------ - * Keyboard light x x x x x x x 1 - * LCD Bright (4) x x x x x 1 1 x - * LCD Bright (3) x x x x x 0 1 x - * LCD Bright (2) x x x x x 1 0 x - * LCD Bright (1) x x x x x 0 0 x - * LCD Off x x x x 0 x x x - * LCD image (fb) 1 x x x x x x x - * LCD image (white) 0 x x x x x x x - * Caps lock LED x x 1 x x x x x - * - * Chip 5 - 0x05 - * - * Function 7 6 5 4 3 2 1 0 - * ------------------------------------ - * Red (solid) x x x x x 1 x x - * Red (flash) x x x x x x 1 x - * Green (GSM flash) x x x x 1 x x x - * Green (GSM solid) x x x 1 x x x x - * Green (wifi flash) x x 1 x x x x x - * Blue (bt flash) x 1 x x x x x x - * DPAD Int Enable 1 x x x x x x 0 - * - * (Combinations of the above can be made for different colors.) - * The direction pad interrupt enable must be set each time the - * interrupt is handled. - * - * Chip 6 - 0x06 - * - * Function 7 6 5 4 3 2 1 0 - * ------------------------------------ - * Vibrator x x x x 1 x x x - * Alt LED x x x 1 x x x x - * Screen white 1 x x x x x x x - * Screen white x x 1 x x x x x - * Screen white x 0 x x x x x x - * Enable kbd dpad x x x x x x 0 x - * Happy Times 0 1 0 x x x 0 x - */ - -/* - * HTCPLD GPIO lines start 16 after OMAP_MAX_GPIO_LINES to account - * for the 16 MPUIO lines. - */ -#define HTCPLD_GPIO_START_OFFSET (OMAP_MAX_GPIO_LINES + 16) -#define HTCPLD_IRQ(chip, offset) (OMAP_IRQ_END + 8 * (chip) + (offset)) -#define HTCPLD_BASE(chip, offset) \ - (HTCPLD_GPIO_START_OFFSET + 8 * (chip) + (offset)) - -#define HTCPLD_GPIO_LED_DPAD HTCPLD_BASE(0, 0) -#define HTCPLD_GPIO_LED_KBD HTCPLD_BASE(1, 0) -#define HTCPLD_GPIO_LED_CAPS HTCPLD_BASE(1, 5) -#define HTCPLD_GPIO_LED_RED_FLASH HTCPLD_BASE(2, 1) -#define HTCPLD_GPIO_LED_RED_SOLID HTCPLD_BASE(2, 2) -#define HTCPLD_GPIO_LED_GREEN_FLASH HTCPLD_BASE(2, 3) -#define HTCPLD_GPIO_LED_GREEN_SOLID HTCPLD_BASE(2, 4) -#define HTCPLD_GPIO_LED_WIFI HTCPLD_BASE(2, 5) -#define HTCPLD_GPIO_LED_BT HTCPLD_BASE(2, 6) -#define HTCPLD_GPIO_LED_VIBRATE HTCPLD_BASE(3, 3) -#define HTCPLD_GPIO_LED_ALT HTCPLD_BASE(3, 4) - -#define HTCPLD_GPIO_RIGHT_KBD HTCPLD_BASE(6, 7) -#define HTCPLD_GPIO_UP_KBD HTCPLD_BASE(6, 6) -#define HTCPLD_GPIO_LEFT_KBD HTCPLD_BASE(6, 5) -#define HTCPLD_GPIO_DOWN_KBD HTCPLD_BASE(6, 4) - -#define HTCPLD_GPIO_RIGHT_DPAD HTCPLD_BASE(7, 7) -#define HTCPLD_GPIO_UP_DPAD HTCPLD_BASE(7, 6) -#define HTCPLD_GPIO_LEFT_DPAD HTCPLD_BASE(7, 5) -#define HTCPLD_GPIO_DOWN_DPAD HTCPLD_BASE(7, 4) -#define HTCPLD_GPIO_ENTER_DPAD HTCPLD_BASE(7, 3) +static struct omap_lcd_config htcherald_lcd_config __initdata = { + .ctrl_name = "internal", +}; -/* - * The htcpld chip requires a gpio write to a specific line - * to re-enable interrupts after one has occurred. - */ -#define HTCPLD_GPIO_INT_RESET_HI HTCPLD_BASE(2, 7) -#define HTCPLD_GPIO_INT_RESET_LO HTCPLD_BASE(2, 0) - -/* Chip 5 */ -#define HTCPLD_IRQ_RIGHT_KBD HTCPLD_IRQ(0, 7) -#define HTCPLD_IRQ_UP_KBD HTCPLD_IRQ(0, 6) -#define HTCPLD_IRQ_LEFT_KBD HTCPLD_IRQ(0, 5) -#define HTCPLD_IRQ_DOWN_KBD HTCPLD_IRQ(0, 4) - -/* Chip 6 */ -#define HTCPLD_IRQ_RIGHT_DPAD HTCPLD_IRQ(1, 7) -#define HTCPLD_IRQ_UP_DPAD HTCPLD_IRQ(1, 6) -#define HTCPLD_IRQ_LEFT_DPAD HTCPLD_IRQ(1, 5) -#define HTCPLD_IRQ_DOWN_DPAD HTCPLD_IRQ(1, 4) -#define HTCPLD_IRQ_ENTER_DPAD HTCPLD_IRQ(1, 3) +static struct omap_board_config_kernel htcherald_config[] __initdata = { + { OMAP_TAG_LCD, &htcherald_lcd_config }, +}; /* Keyboard definition */ @@ -258,129 +140,6 @@ static struct platform_device kp_device = { .resource = kp_resources, }; -/* GPIO buttons for keyboard slide and power button */ -static struct gpio_keys_button herald_gpio_keys_table[] = { - {BTN_0, HTCHERALD_GPIO_POWER, 1, "POWER", EV_KEY, 1, 20}, - {SW_LID, HTCHERALD_GPIO_SLIDE, 0, "SLIDE", EV_SW, 1, 20}, - - {KEY_LEFT, HTCPLD_GPIO_LEFT_KBD, 1, "LEFT", EV_KEY, 1, 20}, - {KEY_RIGHT, HTCPLD_GPIO_RIGHT_KBD, 1, "RIGHT", EV_KEY, 1, 20}, - {KEY_UP, HTCPLD_GPIO_UP_KBD, 1, "UP", EV_KEY, 1, 20}, - {KEY_DOWN, HTCPLD_GPIO_DOWN_KBD, 1, "DOWN", EV_KEY, 1, 20}, - - {KEY_LEFT, HTCPLD_GPIO_LEFT_DPAD, 1, "DLEFT", EV_KEY, 1, 20}, - {KEY_RIGHT, HTCPLD_GPIO_RIGHT_DPAD, 1, "DRIGHT", EV_KEY, 1, 20}, - {KEY_UP, HTCPLD_GPIO_UP_DPAD, 1, "DUP", EV_KEY, 1, 20}, - {KEY_DOWN, HTCPLD_GPIO_DOWN_DPAD, 1, "DDOWN", EV_KEY, 1, 20}, - {KEY_ENTER, HTCPLD_GPIO_ENTER_DPAD, 1, "DENTER", EV_KEY, 1, 20}, -}; - -static struct gpio_keys_platform_data herald_gpio_keys_data = { - .buttons = herald_gpio_keys_table, - .nbuttons = ARRAY_SIZE(herald_gpio_keys_table), - .rep = 1, -}; - -static struct platform_device herald_gpiokeys_device = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &herald_gpio_keys_data, - }, -}; - -/* LEDs for the Herald. These connect to the HTCPLD GPIO device. */ -static struct gpio_led gpio_leds[] = { - {"dpad", NULL, HTCPLD_GPIO_LED_DPAD, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"kbd", NULL, HTCPLD_GPIO_LED_KBD, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"vibrate", NULL, HTCPLD_GPIO_LED_VIBRATE, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"green_solid", NULL, HTCPLD_GPIO_LED_GREEN_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"green_flash", NULL, HTCPLD_GPIO_LED_GREEN_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"red_solid", "mmc0", HTCPLD_GPIO_LED_RED_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"red_flash", NULL, HTCPLD_GPIO_LED_RED_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"wifi", NULL, HTCPLD_GPIO_LED_WIFI, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"bt", NULL, HTCPLD_GPIO_LED_BT, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"caps", NULL, HTCPLD_GPIO_LED_CAPS, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"alt", NULL, HTCPLD_GPIO_LED_ALT, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, -}; - -static struct gpio_led_platform_data gpio_leds_data = { - .leds = gpio_leds, - .num_leds = ARRAY_SIZE(gpio_leds), -}; - -static struct platform_device gpio_leds_device = { - .name = "leds-gpio", - .id = 0, - .dev = { - .platform_data = &gpio_leds_data, - }, -}; - -/* HTC PLD chips */ - -static struct resource htcpld_resources[] = { - [0] = { - .start = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS), - .end = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS), - .flags = IORESOURCE_IRQ, - }, -}; - -struct htcpld_chip_platform_data htcpld_chips[] = { - [0] = { - .addr = 0x03, - .reset = 0x04, - .num_gpios = 8, - .gpio_out_base = HTCPLD_BASE(0, 0), - .gpio_in_base = HTCPLD_BASE(4, 0), - }, - [1] = { - .addr = 0x04, - .reset = 0x8e, - .num_gpios = 8, - .gpio_out_base = HTCPLD_BASE(1, 0), - .gpio_in_base = HTCPLD_BASE(5, 0), - }, - [2] = { - .addr = 0x05, - .reset = 0x80, - .num_gpios = 8, - .gpio_out_base = HTCPLD_BASE(2, 0), - .gpio_in_base = HTCPLD_BASE(6, 0), - .irq_base = HTCPLD_IRQ(0, 0), - .num_irqs = 8, - }, - [3] = { - .addr = 0x06, - .reset = 0x40, - .num_gpios = 8, - .gpio_out_base = HTCPLD_BASE(3, 0), - .gpio_in_base = HTCPLD_BASE(7, 0), - .irq_base = HTCPLD_IRQ(1, 0), - .num_irqs = 8, - }, -}; - -struct htcpld_core_platform_data htcpld_pfdata = { - .int_reset_gpio_hi = HTCPLD_GPIO_INT_RESET_HI, - .int_reset_gpio_lo = HTCPLD_GPIO_INT_RESET_LO, - .i2c_adapter_id = 1, - - .chip = htcpld_chips, - .num_chip = ARRAY_SIZE(htcpld_chips), -}; - -static struct platform_device htcpld_device = { - .name = "i2c-htcpld", - .id = -1, - .resource = htcpld_resources, - .num_resources = ARRAY_SIZE(htcpld_resources), - .dev = { - .platform_data = &htcpld_pfdata, - }, -}; - /* USB Device */ static struct omap_usb_config htcherald_usb_config __initdata = { .otg = 0, @@ -391,72 +150,14 @@ static struct omap_usb_config htcherald_usb_config __initdata = { }; /* LCD Device resources */ -static struct omap_lcd_config htcherald_lcd_config __initdata = { - .ctrl_name = "internal", -}; - -static struct omap_board_config_kernel htcherald_config[] __initdata = { - { OMAP_TAG_LCD, &htcherald_lcd_config }, -}; - static struct platform_device lcd_device = { .name = "lcd_htcherald", .id = -1, }; -/* MMC Card */ -#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) -static struct omap_mmc_platform_data htc_mmc1_data = { - .nr_slots = 1, - .switch_slot = NULL, - .slots[0] = { - .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | - MMC_VDD_32_33 | MMC_VDD_33_34, - .name = "mmcblk", - .nomux = 1, - .wires = 4, - .switch_pin = -1, - }, -}; - -static struct omap_mmc_platform_data *htc_mmc_data[1]; -#endif - - -/* Platform devices for the Herald */ static struct platform_device *devices[] __initdata = { &kp_device, &lcd_device, - &htcpld_device, - &gpio_leds_device, - &herald_gpiokeys_device, -}; - -/* - * Touchscreen - */ -static const struct ads7846_platform_data htcherald_ts_platform_data = { - .model = 7846, - .keep_vref_on = 1, - .x_plate_ohms = 496, - .gpio_pendown = HTCHERALD_GPIO_TS, - .pressure_max = 100000, - .pressure_min = 5000, - .x_min = 528, - .x_max = 3760, - .y_min = 624, - .y_max = 3760, -}; - -static struct spi_board_info __initdata htcherald_spi_board_info[] = { - { - .modalias = "ads7846", - .platform_data = &htcherald_ts_platform_data, - .irq = OMAP_GPIO_IRQ(HTCHERALD_GPIO_TS), - .max_speed_hz = 2500000, - .bus_num = 2, - .chip_select = 1, - } }; /* @@ -577,7 +278,6 @@ static void __init htcherald_init(void) { printk(KERN_INFO "HTC Herald init.\n"); - /* Do board initialization before we register all the devices */ omap_gpio_init(); omap_board_config = htcherald_config; @@ -588,16 +288,6 @@ static void __init htcherald_init(void) htcherald_usb_enable(); omap1_usb_init(&htcherald_usb_config); - - spi_register_board_info(htcherald_spi_board_info, - ARRAY_SIZE(htcherald_spi_board_info)); - - omap_register_i2c_bus(1, 100, NULL, 0); - -#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) - htc_mmc_data[0] = &htc_mmc1_data; - omap1_init_mmc(htc_mmc_data, 1); -#endif } static void __init htcherald_init_irq(void) diff --git a/trunk/arch/arm/mach-omap1/pm_bus.c b/trunk/arch/arm/mach-omap1/pm_bus.c deleted file mode 100644 index 8b66392be745..000000000000 --- a/trunk/arch/arm/mach-omap1/pm_bus.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Runtime PM support code for OMAP1 - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * Copyright (C) 2010 Texas Instruments, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#ifdef CONFIG_PM_RUNTIME -static int omap1_pm_runtime_suspend(struct device *dev) -{ - struct clk *iclk, *fclk; - int ret = 0; - - dev_dbg(dev, "%s\n", __func__); - - ret = pm_generic_runtime_suspend(dev); - - fclk = clk_get(dev, "fck"); - if (!IS_ERR(fclk)) { - clk_disable(fclk); - clk_put(fclk); - } - - iclk = clk_get(dev, "ick"); - if (!IS_ERR(iclk)) { - clk_disable(iclk); - clk_put(iclk); - } - - return 0; -}; - -static int omap1_pm_runtime_resume(struct device *dev) -{ - int ret = 0; - struct clk *iclk, *fclk; - - dev_dbg(dev, "%s\n", __func__); - - iclk = clk_get(dev, "ick"); - if (!IS_ERR(iclk)) { - clk_enable(iclk); - clk_put(iclk); - } - - fclk = clk_get(dev, "fck"); - if (!IS_ERR(fclk)) { - clk_enable(fclk); - clk_put(fclk); - } - - return pm_generic_runtime_resume(dev); -}; - -static int __init omap1_pm_runtime_init(void) -{ - const struct dev_pm_ops *pm; - struct dev_pm_ops *omap_pm; - - pm = platform_bus_get_pm_ops(); - if (!pm) { - pr_err("%s: unable to get dev_pm_ops from platform_bus\n", - __func__); - return -ENODEV; - } - - omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL); - if (!omap_pm) { - pr_err("%s: unable to alloc memory for new dev_pm_ops\n", - __func__); - return -ENOMEM; - } - - omap_pm->runtime_suspend = omap1_pm_runtime_suspend; - omap_pm->runtime_resume = omap1_pm_runtime_resume; - - platform_bus_set_pm_ops(omap_pm); - - return 0; -} -core_initcall(omap1_pm_runtime_init); -#endif /* CONFIG_PM_RUNTIME */ diff --git a/trunk/arch/arm/mach-omap2/Kconfig b/trunk/arch/arm/mach-omap2/Kconfig index 1c4b2377862b..b48bacf0a7aa 100644 --- a/trunk/arch/arm/mach-omap2/Kconfig +++ b/trunk/arch/arm/mach-omap2/Kconfig @@ -35,7 +35,7 @@ config ARCH_OMAP3 default y select CPU_V7 select USB_ARCH_HAS_EHCI - select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4 + select ARM_L1_CACHE_SHIFT_6 config ARCH_OMAP4 bool "TI OMAP4" @@ -43,8 +43,6 @@ config ARCH_OMAP4 depends on ARCH_OMAP2PLUS select CPU_V7 select ARM_GIC - select PL310_ERRATA_588369 - select ARM_ERRATA_720789 comment "OMAP Core Type" depends on ARCH_OMAP2 @@ -137,26 +135,6 @@ config MACH_OMAP_LDP default y select OMAP_PACKAGE_CBB -config MACH_OMAP3530_LV_SOM - bool "OMAP3 Logic 3530 LV SOM board" - depends on ARCH_OMAP3 - select OMAP_PACKAGE_CBB - default y - help - Support for the LogicPD OMAP3530 SOM Development kit - for full description please see the products webpage at - http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit - -config MACH_OMAP3_TORPEDO - bool "OMAP3 Logic 35x Torpedo board" - depends on ARCH_OMAP3 - select OMAP_PACKAGE_CBB - default y - help - Support for the LogicPD OMAP35x Torpedo Development kit - for full description please see the products webpage at - http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit - config MACH_OVERO bool "Gumstix Overo board" depends on ARCH_OMAP3 @@ -236,13 +214,6 @@ config MACH_CM_T35 select OMAP_PACKAGE_CUS select OMAP_MUX -config MACH_CM_T3517 - bool "CompuLab CM-T3517 module" - depends on ARCH_OMAP3 - default y - select OMAP_PACKAGE_CBB - select OMAP_MUX - config MACH_IGEP0020 bool "IGEP v2 board" depends on ARCH_OMAP3 diff --git a/trunk/arch/arm/mach-omap2/Makefile b/trunk/arch/arm/mach-omap2/Makefile index 9edacb0ab035..29d40b2a4f5d 100644 --- a/trunk/arch/arm/mach-omap2/Makefile +++ b/trunk/arch/arm/mach-omap2/Makefile @@ -5,7 +5,7 @@ # Common support obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o -omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o +omap-2-3-common = irq.o sdrc.o hwmod-common = omap_hwmod.o \ omap_hwmod_common_data.o prcm-common = prcm.o powerdomain.o @@ -15,7 +15,7 @@ clock-common = clock.o clock_common_data.o \ obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) -obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) prm44xx.o $(hwmod-common) +obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) $(hwmod-common) obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o @@ -49,18 +49,14 @@ obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o # Power Management ifeq ($(CONFIG_PM),y) obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o -obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o -obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o pm_bus.o -obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o +obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o +obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o +obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a -ifeq ($(CONFIG_PM_VERBOSE),y) -CFLAGS_pm_bus.o += -DDEBUG -endif - endif # PRCM @@ -120,10 +116,6 @@ obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o \ obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \ board-flash.o \ hsmmc.o -obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o \ - hsmmc.o -obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o \ - hsmmc.o obj-$(CONFIG_MACH_OVERO) += board-overo.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o \ @@ -155,7 +147,6 @@ obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \ hsmmc.o obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \ hsmmc.o -obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ @@ -184,6 +175,3 @@ obj-y += $(nand-m) $(nand-y) smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o obj-y += $(smc91x-m) $(smc91x-y) - -smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o -obj-y += $(smsc911x-m) $(smsc911x-y) diff --git a/trunk/arch/arm/mach-omap2/board-2430sdp.c b/trunk/arch/arm/mach-omap2/board-2430sdp.c index fc178a022dd2..8538e4131d27 100644 --- a/trunk/arch/arm/mach-omap2/board-2430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-2430sdp.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -191,7 +190,7 @@ static int __init omap2430_i2c_init(void) static struct omap2_hsmmc_info mmc[] __initdata = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .ext_clock = 1, diff --git a/trunk/arch/arm/mach-omap2/board-3430sdp.c b/trunk/arch/arm/mach-omap2/board-3430sdp.c index 9ba2ee246a75..67b95b5f1a2f 100644 --- a/trunk/arch/arm/mach-omap2/board-3430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-3430sdp.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include @@ -42,7 +41,8 @@ #include #include -#include "board-flash.h" +#include + #include "mux.h" #include "sdram-qimonda-hyb18m512160af-6.h" #include "hsmmc.h" @@ -76,7 +76,7 @@ static struct cpuidle_params omap3_cpuidle_params_table[] = { {1, 10000, 30000, 300000}, }; -static uint32_t board_keymap[] = { +static int board_keymap[] = { KEY(0, 0, KEY_LEFT), KEY(0, 1, KEY_RIGHT), KEY(0, 2, KEY_A), @@ -353,12 +353,12 @@ static struct omap2_hsmmc_info mmc[] = { /* 8 bits (default) requires S6.3 == ON, * so the SIM card isn't used; else 4 bits. */ - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_wp = 4, }, { .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_wp = 7, }, {} /* Terminator */ diff --git a/trunk/arch/arm/mach-omap2/board-3630sdp.c b/trunk/arch/arm/mach-omap2/board-3630sdp.c index 2b2e0efd5570..b359c3f7bb39 100644 --- a/trunk/arch/arm/mach-omap2/board-3630sdp.c +++ b/trunk/arch/arm/mach-omap2/board-3630sdp.c @@ -21,8 +21,8 @@ #include #include +#include -#include "board-flash.h" #include "mux.h" #include "sdram-hynix-h8mbx00u0mer-0em.h" diff --git a/trunk/arch/arm/mach-omap2/board-4430sdp.c b/trunk/arch/arm/mach-omap2/board-4430sdp.c index d70b58002d2b..9447644774c2 100644 --- a/trunk/arch/arm/mach-omap2/board-4430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-4430sdp.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include @@ -33,17 +32,14 @@ #include #include #include +#include #include #include - #include "hsmmc.h" -#include "timer-gp.h" #define ETH_KS8851_IRQ 34 #define ETH_KS8851_POWER_ON 48 #define ETH_KS8851_QUART 138 -#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 -#define OMAP4_SFH7741_ENABLE_GPIO 188 static struct gpio_led sdp4430_gpio_leds[] = { { @@ -81,47 +77,11 @@ static struct gpio_led sdp4430_gpio_leds[] = { }; -static struct gpio_keys_button sdp4430_gpio_keys[] = { - { - .desc = "Proximity Sensor", - .type = EV_SW, - .code = SW_FRONT_PROXIMITY, - .gpio = OMAP4_SFH7741_SENSOR_OUTPUT_GPIO, - .active_low = 0, - } -}; - static struct gpio_led_platform_data sdp4430_led_data = { .leds = sdp4430_gpio_leds, .num_leds = ARRAY_SIZE(sdp4430_gpio_leds), }; -static int omap_prox_activate(struct device *dev) -{ - gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1); - return 0; -} - -static void omap_prox_deactivate(struct device *dev) -{ - gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 0); -} - -static struct gpio_keys_platform_data sdp4430_gpio_keys_data = { - .buttons = sdp4430_gpio_keys, - .nbuttons = ARRAY_SIZE(sdp4430_gpio_keys), - .enable = omap_prox_activate, - .disable = omap_prox_deactivate, -}; - -static struct platform_device sdp4430_gpio_keys_device = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &sdp4430_gpio_keys_data, - }, -}; - static struct platform_device sdp4430_leds_gpio = { .name = "leds-gpio", .id = -1, @@ -201,7 +161,6 @@ static struct platform_device sdp4430_lcd_device = { static struct platform_device *sdp4430_devices[] __initdata = { &sdp4430_lcd_device, - &sdp4430_gpio_keys_device, &sdp4430_leds_gpio, }; @@ -234,12 +193,12 @@ static struct omap_musb_board_data musb_board_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_wp = -EINVAL, }, { .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .nonremovable = true, @@ -453,11 +412,6 @@ static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = { I2C_BOARD_INFO("tmp105", 0x48), }, }; -static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = { - { - I2C_BOARD_INFO("hmc5843", 0x1e), - }, -}; static int __init omap4_i2c_init(void) { /* @@ -469,36 +423,14 @@ static int __init omap4_i2c_init(void) omap_register_i2c_bus(2, 400, NULL, 0); omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); - omap_register_i2c_bus(4, 400, sdp4430_i2c_4_boardinfo, - ARRAY_SIZE(sdp4430_i2c_4_boardinfo)); + omap_register_i2c_bus(4, 400, NULL, 0); return 0; } - -static void __init omap_sfh7741prox_init(void) -{ - int error; - - error = gpio_request(OMAP4_SFH7741_ENABLE_GPIO, "sfh7741"); - if (error < 0) { - pr_err("%s:failed to request GPIO %d, error %d\n", - __func__, OMAP4_SFH7741_ENABLE_GPIO, error); - return; - } - - error = gpio_direction_output(OMAP4_SFH7741_ENABLE_GPIO , 0); - if (error < 0) { - pr_err("%s: GPIO configuration failed: GPIO %d,error %d\n", - __func__, OMAP4_SFH7741_ENABLE_GPIO, error); - gpio_free(OMAP4_SFH7741_ENABLE_GPIO); - } -} - static void __init omap_4430sdp_init(void) { int status; omap4_i2c_init(); - omap_sfh7741prox_init(); platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); diff --git a/trunk/arch/arm/mach-omap2/board-am3517evm.c b/trunk/arch/arm/mach-omap2/board-am3517evm.c index b091741500de..4d0f58592864 100644 --- a/trunk/arch/arm/mach-omap2/board-am3517evm.c +++ b/trunk/arch/arm/mach-omap2/board-am3517evm.c @@ -106,7 +106,7 @@ static void am3517_disable_ethernet_int(void) regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); } -static void am3517_evm_ethernet_init(struct emac_platform_data *pdata) +void am3517_evm_ethernet_init(struct emac_platform_data *pdata) { unsigned int regval; @@ -139,6 +139,7 @@ static void am3517_evm_ethernet_init(struct emac_platform_data *pdata) static struct i2c_board_info __initdata am3517evm_i2c1_boardinfo[] = { { I2C_BOARD_INFO("s35390a", 0x30), + .type = "s35390a", }, }; @@ -346,7 +347,7 @@ static struct omap_dss_board_info am3517_evm_dss_data = { .default_device = &am3517_evm_lcd_device, }; -static struct platform_device am3517_evm_dss_device = { +struct platform_device am3517_evm_dss_device = { .name = "omapdss", .id = -1, .dev = { diff --git a/trunk/arch/arm/mach-omap2/board-cm-t35.c b/trunk/arch/arm/mach-omap2/board-cm-t35.c index 2b328b9b8e0a..e10bc109415c 100644 --- a/trunk/arch/arm/mach-omap2/board-cm-t35.c +++ b/trunk/arch/arm/mach-omap2/board-cm-t35.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include @@ -559,7 +558,7 @@ static struct twl4030_usb_data cm_t35_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static uint32_t cm_t35_keymap[] = { +static int cm_t35_keymap[] = { KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT), KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN), KEY(2, 0, KEY_RIGHT), KEY(2, 1, KEY_C), KEY(2, 2, KEY_D), @@ -580,14 +579,14 @@ static struct twl4030_keypad_data cm_t35_kp_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, { .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .transceiver = 1, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, diff --git a/trunk/arch/arm/mach-omap2/board-cm-t3517.c b/trunk/arch/arm/mach-omap2/board-cm-t3517.c deleted file mode 100644 index 1115b8ab5e1d..000000000000 --- a/trunk/arch/arm/mach-omap2/board-cm-t3517.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/board-cm-t3517.c - * - * Support for the CompuLab CM-T3517 modules - * - * Copyright (C) 2010 CompuLab, Ltd. - * Author: Igor Grinberg - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "mux.h" - -#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) -static struct gpio_led cm_t3517_leds[] = { - [0] = { - .gpio = 186, - .name = "cm-t3517:green", - .default_trigger = "heartbeat", - .active_low = 0, - }, -}; - -static struct gpio_led_platform_data cm_t3517_led_pdata = { - .num_leds = ARRAY_SIZE(cm_t3517_leds), - .leds = cm_t3517_leds, -}; - -static struct platform_device cm_t3517_led_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &cm_t3517_led_pdata, - }, -}; - -static void __init cm_t3517_init_leds(void) -{ - platform_device_register(&cm_t3517_led_device); -} -#else -static inline void cm_t3517_init_leds(void) {} -#endif - -#if defined(CONFIG_CAN_TI_HECC) || defined(CONFIG_CAN_TI_HECC_MODULE) -static struct resource cm_t3517_hecc_resources[] = { - { - .start = AM35XX_IPSS_HECC_BASE, - .end = AM35XX_IPSS_HECC_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_35XX_HECC0_IRQ, - .end = INT_35XX_HECC0_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct ti_hecc_platform_data cm_t3517_hecc_pdata = { - .scc_hecc_offset = AM35XX_HECC_SCC_HECC_OFFSET, - .scc_ram_offset = AM35XX_HECC_SCC_RAM_OFFSET, - .hecc_ram_offset = AM35XX_HECC_RAM_OFFSET, - .mbx_offset = AM35XX_HECC_MBOX_OFFSET, - .int_line = AM35XX_HECC_INT_LINE, - .version = AM35XX_HECC_VERSION, -}; - -static struct platform_device cm_t3517_hecc_device = { - .name = "ti_hecc", - .id = 1, - .num_resources = ARRAY_SIZE(cm_t3517_hecc_resources), - .resource = cm_t3517_hecc_resources, - .dev = { - .platform_data = &cm_t3517_hecc_pdata, - }, -}; - -static void cm_t3517_init_hecc(void) -{ - platform_device_register(&cm_t3517_hecc_device); -} -#else -static inline void cm_t3517_init_hecc(void) {} -#endif - -#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE) -#define RTC_IO_GPIO (153) -#define RTC_WR_GPIO (154) -#define RTC_RD_GPIO (160) -#define RTC_CS_GPIO (163) - -struct v3020_platform_data cm_t3517_v3020_pdata = { - .use_gpio = 1, - .gpio_cs = RTC_CS_GPIO, - .gpio_wr = RTC_WR_GPIO, - .gpio_rd = RTC_RD_GPIO, - .gpio_io = RTC_IO_GPIO, -}; - -static struct platform_device cm_t3517_rtc_device = { - .name = "v3020", - .id = -1, - .dev = { - .platform_data = &cm_t3517_v3020_pdata, - } -}; - -static void __init cm_t3517_init_rtc(void) -{ - platform_device_register(&cm_t3517_rtc_device); -} -#else -static inline void cm_t3517_init_rtc(void) {} -#endif - -#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE) -#define HSUSB1_RESET_GPIO (146) -#define HSUSB2_RESET_GPIO (147) -#define USB_HUB_RESET_GPIO (152) - -static struct ehci_hcd_omap_platform_data cm_t3517_ehci_pdata __initdata = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, - - .phy_reset = true, - .reset_gpio_port[0] = HSUSB1_RESET_GPIO, - .reset_gpio_port[1] = HSUSB2_RESET_GPIO, - .reset_gpio_port[2] = -EINVAL, -}; - -static int cm_t3517_init_usbh(void) -{ - int err; - - err = gpio_request(USB_HUB_RESET_GPIO, "usb hub rst"); - if (err) { - pr_err("CM-T3517: usb hub rst gpio request failed: %d\n", err); - } else { - gpio_direction_output(USB_HUB_RESET_GPIO, 0); - udelay(10); - gpio_set_value(USB_HUB_RESET_GPIO, 1); - msleep(1); - } - - usb_ehci_init(&cm_t3517_ehci_pdata); - - return 0; -} -#else -static inline int cm_t3517_init_usbh(void) -{ - return 0; -} -#endif - -#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) -#define NAND_BLOCK_SIZE SZ_128K - -static struct mtd_partition cm_t3517_nand_partitions[] = { - { - .name = "xloader", - .offset = 0, /* Offset = 0x00000 */ - .size = 4 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE - }, - { - .name = "uboot", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ - .size = 15 * NAND_BLOCK_SIZE, - }, - { - .name = "uboot environment", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ - .size = 2 * NAND_BLOCK_SIZE, - }, - { - .name = "linux", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ - .size = 32 * NAND_BLOCK_SIZE, - }, - { - .name = "rootfs", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */ - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct omap_nand_platform_data cm_t3517_nand_data = { - .parts = cm_t3517_nand_partitions, - .nr_parts = ARRAY_SIZE(cm_t3517_nand_partitions), - .dma_channel = -1, /* disable DMA in OMAP NAND driver */ - .cs = 0, -}; - -static void __init cm_t3517_init_nand(void) -{ - if (gpmc_nand_init(&cm_t3517_nand_data) < 0) - pr_err("CM-T3517: NAND initialization failed\n"); -} -#else -static inline void cm_t3517_init_nand(void) {} -#endif - -static struct omap_board_config_kernel cm_t3517_config[] __initdata = { -}; - -static void __init cm_t3517_init_irq(void) -{ - omap_board_config = cm_t3517_config; - omap_board_config_size = ARRAY_SIZE(cm_t3517_config); - - omap2_init_common_hw(NULL, NULL); - omap_init_irq(); - omap_gpio_init(); -} - -static struct omap_board_mux board_mux[] __initdata = { - /* GPIO186 - Green LED */ - OMAP3_MUX(SYS_CLKOUT2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), - /* RTC GPIOs: IO, WR#, RD#, CS# */ - OMAP3_MUX(MCBSP4_DR, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), - OMAP3_MUX(MCBSP4_DX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), - OMAP3_MUX(MCBSP_CLKS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), - OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), - /* HSUSB1 RESET */ - OMAP3_MUX(UART2_TX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), - /* HSUSB2 RESET */ - OMAP3_MUX(UART2_RX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), - /* CM-T3517 USB HUB nRESET */ - OMAP3_MUX(MCBSP4_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), - - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; - -static void __init cm_t3517_init(void) -{ - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap_serial_init(); - cm_t3517_init_leds(); - cm_t3517_init_nand(); - cm_t3517_init_rtc(); - cm_t3517_init_usbh(); - cm_t3517_init_hecc(); -} - -MACHINE_START(CM_T3517, "Compulab CM-T3517") - .phys_io = 0x48000000, - .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap3_map_io, - .reserve = omap_reserve, - .init_irq = cm_t3517_init_irq, - .init_machine = cm_t3517_init, - .timer = &omap_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-omap2/board-devkit8000.c b/trunk/arch/arm/mach-omap2/board-devkit8000.c index ad9ad956dd11..a07086d6a0b2 100644 --- a/trunk/arch/arm/mach-omap2/board-devkit8000.c +++ b/trunk/arch/arm/mach-omap2/board-devkit8000.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include @@ -45,6 +44,7 @@ #include #include #include +#include #include #include @@ -58,7 +58,6 @@ #include "mux.h" #include "hsmmc.h" -#include "timer-gp.h" #define NAND_BLOCK_SIZE SZ_128K @@ -106,7 +105,7 @@ static struct omap_nand_platform_data devkit8000_nand_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_wp = 29, }, {} /* Terminator */ @@ -199,7 +198,7 @@ static struct platform_device devkit8000_dss_device = { static struct regulator_consumer_supply devkit8000_vdda_dac_supply = REGULATOR_SUPPLY("vdda_dac", "omapdss"); -static uint32_t board_keymap[] = { +static int board_keymap[] = { KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3), diff --git a/trunk/arch/arm/mach-omap2/board-flash.c b/trunk/arch/arm/mach-omap2/board-flash.c index fd38c05bb47f..ac834aa7abf6 100644 --- a/trunk/arch/arm/mach-omap2/board-flash.c +++ b/trunk/arch/arm/mach-omap2/board-flash.c @@ -21,8 +21,7 @@ #include #include #include - -#include "board-flash.h" +#include #define REG_FPGA_REV 0x10 #define REG_FPGA_DIP_SWITCH_INPUT2 0x60 diff --git a/trunk/arch/arm/mach-omap2/board-igep0020.c b/trunk/arch/arm/mach-omap2/board-igep0020.c index c437031554b0..175f04339761 100644 --- a/trunk/arch/arm/mach-omap2/board-igep0020.c +++ b/trunk/arch/arm/mach-omap2/board-igep0020.c @@ -20,7 +20,6 @@ #include #include -#include #include #include @@ -108,7 +107,7 @@ static struct platform_device igep2_onenand_device = { }, }; -static void __init igep2_flash_init(void) +void __init igep2_flash_init(void) { u8 cs = 0; u8 onenandcs = GPMC_CS_NUM + 1; @@ -142,7 +141,7 @@ static void __init igep2_flash_init(void) } #else -static void __init igep2_flash_init(void) {} +void __init igep2_flash_init(void) {} #endif #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) @@ -249,13 +248,13 @@ static struct regulator_init_data igep2_vmmc2 = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, { .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, diff --git a/trunk/arch/arm/mach-omap2/board-ldp.c b/trunk/arch/arm/mach-omap2/board-ldp.c index 7c1e6ad3972e..00d9b13b01c5 100644 --- a/trunk/arch/arm/mach-omap2/board-ldp.c +++ b/trunk/arch/arm/mach-omap2/board-ldp.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include @@ -45,7 +44,6 @@ #include #include -#include "board-flash.h" #include "mux.h" #include "hsmmc.h" @@ -84,7 +82,7 @@ static struct platform_device ldp_smsc911x_device = { }, }; -static uint32_t board_keymap[] = { +static int board_keymap[] = { KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3), @@ -364,7 +362,7 @@ static int __init omap_i2c_init(void) static struct omap2_hsmmc_info mmc[] __initdata = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, diff --git a/trunk/arch/arm/mach-omap2/board-n8x0.c b/trunk/arch/arm/mach-omap2/board-n8x0.c index abdcc3963a17..a3e2b49aa39f 100644 --- a/trunk/arch/arm/mach-omap2/board-n8x0.c +++ b/trunk/arch/arm/mach-omap2/board-n8x0.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include @@ -384,6 +383,15 @@ static void n8x0_mmc_callback(void *data, u8 card_mask) omap_mmc_notify_cover_event(mmc_device, index, *openp); } +void n8x0_mmc_slot1_cover_handler(void *arg, int closed_state) +{ + if (mmc_device == NULL) + return; + + slot1_cover_open = !closed_state; + omap_mmc_notify_cover_event(mmc_device, 0, closed_state); +} + static int n8x0_mmc_late_init(struct device *dev) { int r, bit, *openp; @@ -503,7 +511,7 @@ static struct omap_mmc_platform_data mmc1_data = { static struct omap_mmc_platform_data *mmc_data[OMAP24XX_NR_MMC]; -static void __init n8x0_mmc_init(void) +void __init n8x0_mmc_init(void) { int err; @@ -552,6 +560,11 @@ static void __init n8x0_mmc_init(void) void __init n8x0_mmc_init(void) { } + +void n8x0_mmc_slot1_cover_handler(void *arg, int state) +{ +} + #endif /* CONFIG_MMC_OMAP */ #ifdef CONFIG_MENELAUS @@ -601,35 +614,29 @@ static int n8x0_menelaus_late_init(struct device *dev) return 0; } -#else -static int n8x0_menelaus_late_init(struct device *dev) -{ - return 0; -} -#endif - -static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = { - .late_init = n8x0_menelaus_late_init, -}; - -static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = { +static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] = { { I2C_BOARD_INFO("menelaus", 0x72), .irq = INT_24XX_SYS_NIRQ, - .platform_data = &n8x0_menelaus_platform_data, }, }; -static struct aic3x_pdata n810_aic33_data __initdata = { - .gpio_reset = 118, +static struct menelaus_platform_data n8x0_menelaus_platform_data = { + .late_init = n8x0_menelaus_late_init, }; -static struct i2c_board_info n810_i2c_board_info_2[] __initdata = { - { - I2C_BOARD_INFO("tlv320aic3x", 0x18), - .platform_data = &n810_aic33_data, - }, -}; +static void __init n8x0_menelaus_init(void) +{ + n8x0_i2c_board_info_1[0].platform_data = &n8x0_menelaus_platform_data; + omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, + ARRAY_SIZE(n8x0_i2c_board_info_1)); +} + +#else +static inline void __init n8x0_menelaus_init(void) +{ +} +#endif static void __init n8x0_map_io(void) { @@ -646,11 +653,6 @@ static void __init n8x0_init_irq(void) #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { - /* I2S codec port pins for McBSP block */ - OMAP2420_MUX(EAC_AC_SCLK, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), - OMAP2420_MUX(EAC_AC_FS, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), - OMAP2420_MUX(EAC_AC_DIN, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), - OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else @@ -663,14 +665,9 @@ static void __init n8x0_init_machine(void) /* FIXME: add n810 spi devices */ spi_register_board_info(n800_spi_board_info, ARRAY_SIZE(n800_spi_board_info)); - omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, - ARRAY_SIZE(n8x0_i2c_board_info_1)); - omap_register_i2c_bus(2, 400, NULL, 0); - if (machine_is_nokia_n810()) - i2c_register_board_info(2, n810_i2c_board_info_2, - ARRAY_SIZE(n810_i2c_board_info_2)); omap_serial_init(); + n8x0_menelaus_init(); n8x0_onenand_init(); n8x0_mmc_init(); n8x0_usb_init(); diff --git a/trunk/arch/arm/mach-omap2/board-omap3beagle.c b/trunk/arch/arm/mach-omap2/board-omap3beagle.c index 73689c082b26..87969c7df652 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3beagle.c +++ b/trunk/arch/arm/mach-omap2/board-omap3beagle.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include @@ -44,100 +43,13 @@ #include #include #include +#include #include "mux.h" #include "hsmmc.h" -#include "timer-gp.h" #define NAND_BLOCK_SIZE SZ_128K -/* - * OMAP3 Beagle revision - * Run time detection of Beagle revision is done by reading GPIO. - * GPIO ID - - * AXBX = GPIO173, GPIO172, GPIO171: 1 1 1 - * C1_3 = GPIO173, GPIO172, GPIO171: 1 1 0 - * C4 = GPIO173, GPIO172, GPIO171: 1 0 1 - * XM = GPIO173, GPIO172, GPIO171: 0 0 0 - */ -enum { - OMAP3BEAGLE_BOARD_UNKN = 0, - OMAP3BEAGLE_BOARD_AXBX, - OMAP3BEAGLE_BOARD_C1_3, - OMAP3BEAGLE_BOARD_C4, - OMAP3BEAGLE_BOARD_XM, -}; - -static u8 omap3_beagle_version; - -static u8 omap3_beagle_get_rev(void) -{ - return omap3_beagle_version; -} - -static void __init omap3_beagle_init_rev(void) -{ - int ret; - u16 beagle_rev = 0; - - omap_mux_init_gpio(171, OMAP_PIN_INPUT_PULLUP); - omap_mux_init_gpio(172, OMAP_PIN_INPUT_PULLUP); - omap_mux_init_gpio(173, OMAP_PIN_INPUT_PULLUP); - - ret = gpio_request(171, "rev_id_0"); - if (ret < 0) - goto fail0; - - ret = gpio_request(172, "rev_id_1"); - if (ret < 0) - goto fail1; - - ret = gpio_request(173, "rev_id_2"); - if (ret < 0) - goto fail2; - - gpio_direction_input(171); - gpio_direction_input(172); - gpio_direction_input(173); - - beagle_rev = gpio_get_value(171) | (gpio_get_value(172) << 1) - | (gpio_get_value(173) << 2); - - switch (beagle_rev) { - case 7: - printk(KERN_INFO "OMAP3 Beagle Rev: Ax/Bx\n"); - omap3_beagle_version = OMAP3BEAGLE_BOARD_AXBX; - break; - case 6: - printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n"); - omap3_beagle_version = OMAP3BEAGLE_BOARD_C1_3; - break; - case 5: - printk(KERN_INFO "OMAP3 Beagle Rev: C4\n"); - omap3_beagle_version = OMAP3BEAGLE_BOARD_C4; - break; - case 0: - printk(KERN_INFO "OMAP3 Beagle Rev: xM\n"); - omap3_beagle_version = OMAP3BEAGLE_BOARD_XM; - break; - default: - printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev); - omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN; - } - - return; - -fail2: - gpio_free(172); -fail1: - gpio_free(171); -fail0: - printk(KERN_ERR "Unable to get revision detection GPIO pins\n"); - omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN; - - return; -} - static struct mtd_partition omap3beagle_nand_partitions[] = { /* All the partition sizes are listed in terms of NAND block size */ { @@ -254,7 +166,7 @@ static void __init beagle_display_init(void) static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_wp = 29, }, {} /* Terminator */ @@ -273,10 +185,7 @@ static struct gpio_led gpio_leds[]; static int beagle_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { - if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) { - mmc[0].gpio_wp = -EINVAL; - } else if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C1_3) || - (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C4)) { + if (system_rev >= 0x20 && system_rev <= 0x34301000) { omap_mux_init_gpio(23, OMAP_PIN_INPUT); mmc[0].gpio_wp = 23; } else { @@ -413,19 +322,13 @@ static struct i2c_board_info __initdata beagle_i2c_boardinfo[] = { }, }; -static struct i2c_board_info __initdata beagle_i2c_eeprom[] = { - { - I2C_BOARD_INFO("eeprom", 0x50), - }, -}; - static int __init omap3_beagle_i2c_init(void) { omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo, ARRAY_SIZE(beagle_i2c_boardinfo)); /* Bus 3 is attached to the DVI port where devices like the pico DLP * projector don't work reliably with 400kHz */ - omap_register_i2c_bus(3, 100, beagle_i2c_eeprom, ARRAY_SIZE(beagle_i2c_eeprom)); + omap_register_i2c_bus(3, 100, NULL, 0); return 0; } @@ -561,7 +464,6 @@ static struct omap_musb_board_data musb_board_data = { static void __init omap3_beagle_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap3_beagle_init_rev(); omap3_beagle_i2c_init(); platform_add_devices(omap3_beagle_devices, ARRAY_SIZE(omap3_beagle_devices)); diff --git a/trunk/arch/arm/mach-omap2/board-omap3evm.c b/trunk/arch/arm/mach-omap2/board-omap3evm.c index 6339927f07b2..f76d9c0a47a1 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3evm.c +++ b/trunk/arch/arm/mach-omap2/board-omap3evm.c @@ -31,7 +31,6 @@ #include #include -#include #include #include @@ -371,7 +370,7 @@ static struct regulator_init_data omap3evm_vsim = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = 63, }, @@ -447,7 +446,7 @@ static struct twl4030_usb_data omap3evm_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static uint32_t board_keymap[] = { +static int board_keymap[] = { KEY(0, 0, KEY_LEFT), KEY(0, 1, KEY_DOWN), KEY(0, 2, KEY_ENTER), @@ -585,7 +584,7 @@ static int ads7846_get_pendown_state(void) return !gpio_get_value(OMAP3_EVM_TS_GPIO); } -static struct ads7846_platform_data ads7846_config = { +struct ads7846_platform_data ads7846_config = { .x_max = 0x0fff, .y_max = 0x0fff, .x_plate_ohms = 180, @@ -604,7 +603,7 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = { .single_channel = 1, /* 0: slave, 1: master */ }; -static struct spi_board_info omap3evm_spi_board_info[] = { +struct spi_board_info omap3evm_spi_board_info[] = { [0] = { .modalias = "ads7846", .bus_num = 1, diff --git a/trunk/arch/arm/mach-omap2/board-omap3logic.c b/trunk/arch/arm/mach-omap2/board-omap3logic.c deleted file mode 100644 index 3151cf269a59..000000000000 --- a/trunk/arch/arm/mach-omap2/board-omap3logic.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/board-omap3logic.c - * - * Copyright (C) 2010 Li-Pro.Net - * Stephan Linz - * - * Copyright (C) 2010 Logic Product Development, Inc. - * Peter Barada - * - * Modified from Beagle, EVM, and RX51 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include -#include -#include -#include - -#include "mux.h" -#include "hsmmc.h" -#include "timer-gp.h" - -#include -#include -#include -#include -#include -#include -#include - -#define OMAP3LOGIC_SMSC911X_CS 1 - -#define OMAP3530_LV_SOM_MMC_GPIO_CD 110 -#define OMAP3530_LV_SOM_MMC_GPIO_WP 126 -#define OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ 152 - -#define OMAP3_TORPEDO_MMC_GPIO_CD 127 -#define OMAP3_TORPEDO_SMSC911X_GPIO_IRQ 129 - -static struct regulator_consumer_supply omap3logic_vmmc1_supply = { - .supply = "vmmc", -}; - -/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ -static struct regulator_init_data omap3logic_vmmc1 = { - .constraints = { - .name = "VMMC1", - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &omap3logic_vmmc1_supply, -}; - -static struct twl4030_gpio_platform_data omap3logic_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, - .use_leds = true, - .pullups = BIT(1), - .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) - | BIT(13) | BIT(15) | BIT(16) | BIT(17), -}; - -static struct twl4030_platform_data omap3logic_twldata = { - .irq_base = TWL4030_IRQ_BASE, - .irq_end = TWL4030_IRQ_END, - - /* platform_data for children goes here */ - .gpio = &omap3logic_gpio_data, - .vmmc1 = &omap3logic_vmmc1, -}; - -static struct i2c_board_info __initdata omap3logic_i2c_boardinfo[] = { - { - I2C_BOARD_INFO("twl4030", 0x48), - .flags = I2C_CLIENT_WAKE, - .irq = INT_34XX_SYS_NIRQ, - .platform_data = &omap3logic_twldata, - }, -}; - -static int __init omap3logic_i2c_init(void) -{ - omap_register_i2c_bus(1, 2600, omap3logic_i2c_boardinfo, - ARRAY_SIZE(omap3logic_i2c_boardinfo)); - return 0; -} - -static struct omap2_hsmmc_info __initdata board_mmc_info[] = { - { - .name = "external", - .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, - .gpio_cd = -EINVAL, - .gpio_wp = -EINVAL, - }, - {} /* Terminator */ -}; - -static void __init board_mmc_init(void) -{ - if (machine_is_omap3530_lv_som()) { - /* OMAP3530 LV SOM board */ - board_mmc_info[0].gpio_cd = OMAP3530_LV_SOM_MMC_GPIO_CD; - board_mmc_info[0].gpio_wp = OMAP3530_LV_SOM_MMC_GPIO_WP; - omap_mux_init_signal("gpio_110", OMAP_PIN_OUTPUT); - omap_mux_init_signal("gpio_126", OMAP_PIN_OUTPUT); - } else if (machine_is_omap3_torpedo()) { - /* OMAP3 Torpedo board */ - board_mmc_info[0].gpio_cd = OMAP3_TORPEDO_MMC_GPIO_CD; - omap_mux_init_signal("gpio_127", OMAP_PIN_OUTPUT); - } else { - /* unsupported board */ - printk(KERN_ERR "%s(): unknown machine type\n", __func__); - return; - } - - omap2_hsmmc_init(board_mmc_info); - /* link regulators to MMC adapters */ - omap3logic_vmmc1_supply.dev = board_mmc_info[0].dev; -} - -static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = { - .cs = OMAP3LOGIC_SMSC911X_CS, - .gpio_irq = -EINVAL, - .gpio_reset = -EINVAL, - .flags = IORESOURCE_IRQ_LOWLEVEL, -}; - -/* TODO/FIXME (comment by Peter Barada, LogicPD): - * Fix the PBIAS voltage for Torpedo MMC1 pins that - * are used for other needs (IRQs, etc). */ -static void omap3torpedo_fix_pbias_voltage(void) -{ - u16 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; - u32 reg; - - if (machine_is_omap3_torpedo()) - { - /* Set the bias for the pin */ - reg = omap_ctrl_readl(control_pbias_offset); - - reg &= ~OMAP343X_PBIASLITEPWRDNZ1; - omap_ctrl_writel(reg, control_pbias_offset); - - /* 100ms delay required for PBIAS configuration */ - msleep(100); - - reg |= OMAP343X_PBIASLITEVMODE1; - reg |= OMAP343X_PBIASLITEPWRDNZ1; - omap_ctrl_writel(reg | 0x300, control_pbias_offset); - } -} - -static inline void __init board_smsc911x_init(void) -{ - if (machine_is_omap3530_lv_som()) { - /* OMAP3530 LV SOM board */ - board_smsc911x_data.gpio_irq = - OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ; - omap_mux_init_signal("gpio_152", OMAP_PIN_INPUT); - } else if (machine_is_omap3_torpedo()) { - /* OMAP3 Torpedo board */ - board_smsc911x_data.gpio_irq = OMAP3_TORPEDO_SMSC911X_GPIO_IRQ; - omap_mux_init_signal("gpio_129", OMAP_PIN_INPUT); - } else { - /* unsupported board */ - printk(KERN_ERR "%s(): unknown machine type\n", __func__); - return; - } - - gpmc_smsc911x_init(&board_smsc911x_data); -} - -static void __init omap3logic_init_irq(void) -{ - omap2_init_common_hw(NULL, NULL); - omap_init_irq(); - omap_gpio_init(); -} - -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - -static void __init omap3logic_init(void) -{ - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap3torpedo_fix_pbias_voltage(); - omap3logic_i2c_init(); - omap_serial_init(); - board_mmc_init(); - board_smsc911x_init(); - - /* Ensure SDRC pins are mux'd for self-refresh */ - omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); - omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); -} - -MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board") - .phys_io = 0x48000000, - .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap3_map_io, - .init_irq = omap3logic_init_irq, - .init_machine = omap3logic_init, - .timer = &omap_timer, -MACHINE_END - -MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board") - .phys_io = 0x48000000, - .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap3_map_io, - .init_irq = omap3logic_init_irq, - .init_machine = omap3logic_init, - .timer = &omap_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-omap2/board-omap3pandora.c b/trunk/arch/arm/mach-omap2/board-omap3pandora.c index 2d2e6fc127ac..dd3af2be13be 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3pandora.c +++ b/trunk/arch/arm/mach-omap2/board-omap3pandora.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include @@ -277,14 +276,14 @@ static void pandora_wl1251_init_card(struct mmc_card *card) static struct omap2_hsmmc_info omap3pandora_mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = 126, .ext_clock = 0, }, { .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = 127, .ext_clock = 1, @@ -292,7 +291,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = { }, { .mmc = 3, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .init_card = pandora_wl1251_init_card, diff --git a/trunk/arch/arm/mach-omap2/board-omap3stalker.c b/trunk/arch/arm/mach-omap2/board-omap3stalker.c index db644c1e9d62..bcd01d278c65 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3stalker.c +++ b/trunk/arch/arm/mach-omap2/board-omap3stalker.c @@ -26,7 +26,6 @@ #include #include -#include #include #include @@ -39,6 +38,7 @@ #include #include #include +#include #include #include @@ -52,7 +52,6 @@ #include "sdram-micron-mt46h32m32lf-6.h" #include "mux.h" #include "hsmmc.h" -#include "timer-gp.h" #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) #define OMAP3STALKER_ETHR_START 0x2c000000 @@ -276,7 +275,7 @@ static struct regulator_init_data omap3stalker_vsim = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = 23, }, @@ -390,7 +389,7 @@ static struct twl4030_usb_data omap3stalker_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static uint32_t board_keymap[] = { +static int board_keymap[] = { KEY(0, 0, KEY_LEFT), KEY(0, 1, KEY_DOWN), KEY(0, 2, KEY_ENTER), @@ -565,7 +564,7 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = { .single_channel = 1, /* 0: slave, 1: master */ }; -static struct spi_board_info omap3stalker_spi_board_info[] = { +struct spi_board_info omap3stalker_spi_board_info[] = { [0] = { .modalias = "ads7846", .bus_num = 1, diff --git a/trunk/arch/arm/mach-omap2/board-omap3touchbook.c b/trunk/arch/arm/mach-omap2/board-omap3touchbook.c index 7d569380d649..663c62d271e8 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/trunk/arch/arm/mach-omap2/board-omap3touchbook.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include @@ -48,10 +47,10 @@ #include #include #include +#include #include "mux.h" #include "hsmmc.h" -#include "timer-gp.h" #include @@ -62,7 +61,7 @@ #define TB_BL_PWM_TIMER 9 #define TB_KILL_POWER_GPIO 168 -static unsigned long touchbook_revision; +unsigned long touchbook_revision; static struct mtd_partition omap3touchbook_nand_partitions[] = { /* All the partition sizes are listed in terms of NAND block size */ @@ -109,7 +108,7 @@ static struct omap_nand_platform_data omap3touchbook_nand_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_wp = 29, }, {} /* Terminator */ diff --git a/trunk/arch/arm/mach-omap2/board-omap4panda.c b/trunk/arch/arm/mach-omap2/board-omap4panda.c index 83bd1fe5e323..c03d1d56db56 100644 --- a/trunk/arch/arm/mach-omap2/board-omap4panda.c +++ b/trunk/arch/arm/mach-omap2/board-omap4panda.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -35,42 +34,12 @@ #include #include #include +#include #include #include #include "hsmmc.h" -#include "timer-gp.h" -static struct gpio_led gpio_leds[] = { - { - .name = "pandaboard::status1", - .default_trigger = "heartbeat", - .gpio = 7, - }, - { - .name = "pandaboard::status2", - .default_trigger = "mmc0", - .gpio = 8, - }, -}; - -static struct gpio_led_platform_data gpio_led_info = { - .leds = gpio_leds, - .num_leds = ARRAY_SIZE(gpio_leds), -}; - -static struct platform_device leds_gpio = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &gpio_led_info, - }, -}; - -static struct platform_device *panda_devices[] __initdata = { - &leds_gpio, -}; - static void __init omap4_panda_init_irq(void) { omap2_init_common_hw(NULL, NULL); @@ -87,7 +56,7 @@ static struct omap_musb_board_data musb_board_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_wp = -EINVAL, }, {} /* Terminator */ @@ -305,8 +274,9 @@ static int __init omap4_panda_i2c_init(void) } static void __init omap4_panda_init(void) { + int status; + omap4_panda_i2c_init(); - platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); /* OMAP4 Panda uses internal transceiver so register nop transceiver */ diff --git a/trunk/arch/arm/mach-omap2/board-overo.c b/trunk/arch/arm/mach-omap2/board-overo.c index 93441e5b36ef..4c4843618350 100644 --- a/trunk/arch/arm/mach-omap2/board-overo.c +++ b/trunk/arch/arm/mach-omap2/board-overo.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include @@ -304,13 +303,13 @@ static void __init overo_flash_init(void) static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, { .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .transceiver = true, diff --git a/trunk/arch/arm/mach-omap2/board-rx51-peripherals.c b/trunk/arch/arm/mach-omap2/board-rx51-peripherals.c index 25a273dfb9cd..9a5eb87425fc 100644 --- a/trunk/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/trunk/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -32,8 +32,6 @@ #include #include -#include - #include #include @@ -186,7 +184,7 @@ static void __init rx51_add_gpio_keys(void) } #endif /* CONFIG_KEYBOARD_GPIO || CONFIG_KEYBOARD_GPIO_MODULE */ -static uint32_t board_keymap[] = { +static int board_keymap[] = { /* * Note that KEY(x, 8, KEY_XXX) entries represent "entrire row * connected to the ground" matrix state. @@ -304,7 +302,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .cover_only = true, .gpio_cd = 160, .gpio_wp = -EINVAL, @@ -313,8 +311,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "internal", .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, - /* See also rx51_mmc2_remux */ + .wires = 8, /* See also rx51_mmc2_remux */ .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .nonremovable = true, diff --git a/trunk/arch/arm/mach-omap2/board-rx51-sdram.c b/trunk/arch/arm/mach-omap2/board-rx51-sdram.c index a43b2c5c838b..f392844195d2 100644 --- a/trunk/arch/arm/mach-omap2/board-rx51-sdram.c +++ b/trunk/arch/arm/mach-omap2/board-rx51-sdram.c @@ -43,7 +43,7 @@ struct sdram_timings { u32 tWTR; }; -static struct omap_sdrc_params rx51_sdrc_params[4]; +struct omap_sdrc_params rx51_sdrc_params[4]; static const struct sdram_timings rx51_timings[] = { { diff --git a/trunk/arch/arm/mach-omap2/board-rx51-video.c b/trunk/arch/arm/mach-omap2/board-rx51-video.c index 85503fed4e13..5a1005ba9815 100644 --- a/trunk/arch/arm/mach-omap2/board-rx51-video.c +++ b/trunk/arch/arm/mach-omap2/board-rx51-video.c @@ -20,8 +20,6 @@ #include #include -#include - #include "mux.h" #define RX51_LCD_RESET_GPIO 90 diff --git a/trunk/arch/arm/mach-omap2/board-zoom-debugboard.c b/trunk/arch/arm/mach-omap2/board-zoom-debugboard.c index 007ebdc6c993..1d7f827b0408 100644 --- a/trunk/arch/arm/mach-omap2/board-zoom-debugboard.c +++ b/trunk/arch/arm/mach-omap2/board-zoom-debugboard.c @@ -16,8 +16,6 @@ #include -#include - #define ZOOM_SMSC911X_CS 7 #define ZOOM_SMSC911X_GPIO 158 #define ZOOM_QUADUART_CS 3 diff --git a/trunk/arch/arm/mach-omap2/board-zoom-peripherals.c b/trunk/arch/arm/mach-omap2/board-zoom-peripherals.c index 073fd9b4c36d..6b3984964cc5 100644 --- a/trunk/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/trunk/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include @@ -25,13 +24,11 @@ #include #include -#include - #include "mux.h" #include "hsmmc.h" /* Zoom2 has Qwerty keyboard*/ -static uint32_t board_keymap[] = { +static int board_keymap[] = { KEY(0, 0, KEY_E), KEY(0, 1, KEY_R), KEY(0, 2, KEY_T), @@ -158,14 +155,14 @@ static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_wp = -EINVAL, .power_saving = true, }, { .name = "internal", .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .nonremovable = true, diff --git a/trunk/arch/arm/mach-omap2/board-zoom2.c b/trunk/arch/arm/mach-omap2/board-zoom2.c index d356ef5336c0..3ad9ecf7f5e2 100644 --- a/trunk/arch/arm/mach-omap2/board-zoom2.c +++ b/trunk/arch/arm/mach-omap2/board-zoom2.c @@ -23,7 +23,6 @@ #include -#include "board-flash.h" #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" diff --git a/trunk/arch/arm/mach-omap2/board-zoom3.c b/trunk/arch/arm/mach-omap2/board-zoom3.c index 95895d5bfd17..6ca0b8341615 100644 --- a/trunk/arch/arm/mach-omap2/board-zoom3.c +++ b/trunk/arch/arm/mach-omap2/board-zoom3.c @@ -22,7 +22,6 @@ #include #include -#include "board-flash.h" #include "mux.h" #include "sdram-hynix-h8mbx00u0mer-0em.h" diff --git a/trunk/arch/arm/mach-omap2/clock2420_data.c b/trunk/arch/arm/mach-omap2/clock2420_data.c index 5f2066a6ba74..37d65d62ed8f 100644 --- a/trunk/arch/arm/mach-omap2/clock2420_data.c +++ b/trunk/arch/arm/mach-omap2/clock2420_data.c @@ -1838,7 +1838,7 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "des_ick", &des_ick, CK_242X), CLK("omap-sham", "ick", &sha_ick, CK_242X), CLK("omap_rng", "ick", &rng_ick, CK_242X), - CLK("omap-aes", "ick", &aes_ick, CK_242X), + CLK(NULL, "aes_ick", &aes_ick, CK_242X), CLK(NULL, "pka_ick", &pka_ick, CK_242X), CLK(NULL, "usb_fck", &usb_fck, CK_242X), CLK("musb_hdrc", "fck", &osc_ck, CK_242X), diff --git a/trunk/arch/arm/mach-omap2/clock2430_data.c b/trunk/arch/arm/mach-omap2/clock2430_data.c index 701a1716019e..b33118fb6a87 100644 --- a/trunk/arch/arm/mach-omap2/clock2430_data.c +++ b/trunk/arch/arm/mach-omap2/clock2430_data.c @@ -1926,7 +1926,7 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "des_ick", &des_ick, CK_243X), CLK("omap-sham", "ick", &sha_ick, CK_243X), CLK("omap_rng", "ick", &rng_ick, CK_243X), - CLK("omap-aes", "ick", &aes_ick, CK_243X), + CLK(NULL, "aes_ick", &aes_ick, CK_243X), CLK(NULL, "pka_ick", &pka_ick, CK_243X), CLK(NULL, "usb_fck", &usb_fck, CK_243X), CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), diff --git a/trunk/arch/arm/mach-omap2/clock3xxx_data.c b/trunk/arch/arm/mach-omap2/clock3xxx_data.c index c73906d17458..dfdce2d82779 100644 --- a/trunk/arch/arm/mach-omap2/clock3xxx_data.c +++ b/trunk/arch/arm/mach-omap2/clock3xxx_data.c @@ -3288,7 +3288,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX), CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX), CLK(NULL, "icr_ick", &icr_ick, CK_343X), - CLK("omap-aes", "ick", &aes2_ick, CK_343X), + CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), CLK("omap-sham", "ick", &sha12_ick, CK_343X), CLK(NULL, "des2_ick", &des2_ick, CK_343X), CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), diff --git a/trunk/arch/arm/mach-omap2/clock44xx_data.c b/trunk/arch/arm/mach-omap2/clock44xx_data.c index 67fac44cb6e6..e10db7a90cb2 100644 --- a/trunk/arch/arm/mach-omap2/clock44xx_data.c +++ b/trunk/arch/arm/mach-omap2/clock44xx_data.c @@ -17,15 +17,12 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * - * XXX Some of the ES1 clocks have been removed/changed; once support - * is added for discriminating clocks by ES level, these should be added back - * in. */ #include #include #include + #include #include @@ -178,27 +175,21 @@ static struct clk sys_clkin_ck = { .recalc = &omap2_clksel_recalc, }; -static struct clk tie_low_clock_ck = { - .name = "tie_low_clock_ck", - .rate = 0, - .ops = &clkops_null, -}; - static struct clk utmi_phy_clkout_ck = { .name = "utmi_phy_clkout_ck", - .rate = 60000000, + .rate = 12000000, .ops = &clkops_null, }; static struct clk xclk60mhsp1_ck = { .name = "xclk60mhsp1_ck", - .rate = 60000000, + .rate = 12000000, .ops = &clkops_null, }; static struct clk xclk60mhsp2_ck = { .name = "xclk60mhsp2_ck", - .rate = 60000000, + .rate = 12000000, .ops = &clkops_null, }; @@ -210,23 +201,39 @@ static struct clk xclk60motg_ck = { /* Module clocks and DPLL outputs */ -static const struct clksel abe_dpll_bypass_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, +static const struct clksel_rate div2_1to2_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_4430 }, + { .div = 2, .val = 1, .flags = RATE_IN_4430 }, + { .div = 0 }, +}; + +static const struct clksel dpll_sys_ref_clk_div[] = { + { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, { .parent = NULL }, }; -static struct clk abe_dpll_bypass_clk_mux_ck = { - .name = "abe_dpll_bypass_clk_mux_ck", +static struct clk dpll_sys_ref_clk = { + .name = "dpll_sys_ref_clk", .parent = &sys_clkin_ck, + .clksel = dpll_sys_ref_clk_div, + .clksel_reg = OMAP4430_CM_DPLL_SYS_REF_CLKSEL, + .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, .ops = &clkops_null, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static const struct clksel abe_dpll_refclk_mux_sel[] = { + { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, + { .parent = NULL }, }; static struct clk abe_dpll_refclk_mux_ck = { .name = "abe_dpll_refclk_mux_ck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, + .parent = &dpll_sys_ref_clk, + .clksel = abe_dpll_refclk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL, .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, @@ -237,7 +244,7 @@ static struct clk abe_dpll_refclk_mux_ck = { /* DPLL_ABE */ static struct dpll_data dpll_abe_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, - .clk_bypass = &abe_dpll_bypass_clk_mux_ck, + .clk_bypass = &sys_clkin_ck, .clk_ref = &abe_dpll_refclk_mux_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), @@ -303,12 +310,6 @@ static struct clk abe_clk = { .set_rate = &omap2_clksel_set_rate, }; -static const struct clksel_rate div2_1to2_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - static const struct clksel aess_fclk_div[] = { { .parent = &abe_clk, .rates = div2_1to2_rates }, { .parent = NULL }, @@ -379,14 +380,14 @@ static struct clk dpll_abe_m3_ck = { }; static const struct clksel core_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; static struct clk core_hsd_byp_clk_mux_ck = { .name = "core_hsd_byp_clk_mux_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .clksel = core_hsd_byp_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, @@ -399,7 +400,7 @@ static struct clk core_hsd_byp_clk_mux_ck = { static struct dpll_data dpll_core_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, .clk_bypass = &core_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, + .clk_ref = &dpll_sys_ref_clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, @@ -417,7 +418,7 @@ static struct dpll_data dpll_core_dd = { static struct clk dpll_core_ck = { .name = "dpll_core_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_core_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_null, @@ -595,14 +596,14 @@ static struct clk dpll_core_m7_ck = { }; static const struct clksel iva_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, { .parent = NULL }, }; static struct clk iva_hsd_byp_clk_mux_ck = { .name = "iva_hsd_byp_clk_mux_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .ops = &clkops_null, .recalc = &followparent_recalc, }; @@ -611,7 +612,7 @@ static struct clk iva_hsd_byp_clk_mux_ck = { static struct dpll_data dpll_iva_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, .clk_bypass = &iva_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, + .clk_ref = &dpll_sys_ref_clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, @@ -629,7 +630,7 @@ static struct dpll_data dpll_iva_dd = { static struct clk dpll_iva_ck = { .name = "dpll_iva_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_iva_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -671,7 +672,7 @@ static struct clk dpll_iva_m5_ck = { static struct dpll_data dpll_mpu_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, .clk_bypass = &div_mpu_hs_clk, - .clk_ref = &sys_clkin_ck, + .clk_ref = &dpll_sys_ref_clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, @@ -689,7 +690,7 @@ static struct dpll_data dpll_mpu_dd = { static struct clk dpll_mpu_ck = { .name = "dpll_mpu_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_mpu_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -723,14 +724,14 @@ static struct clk per_hs_clk_div_ck = { }; static const struct clksel per_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; static struct clk per_hsd_byp_clk_mux_ck = { .name = "per_hsd_byp_clk_mux_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .clksel = per_hsd_byp_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER, @@ -743,7 +744,7 @@ static struct clk per_hsd_byp_clk_mux_ck = { static struct dpll_data dpll_per_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, .clk_bypass = &per_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, + .clk_ref = &dpll_sys_ref_clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, @@ -761,7 +762,7 @@ static struct dpll_data dpll_per_dd = { static struct clk dpll_per_ck = { .name = "dpll_per_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_per_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -857,8 +858,8 @@ static struct clk dpll_per_m7_ck = { /* DPLL_UNIPRO */ static struct dpll_data dpll_unipro_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, + .clk_bypass = &dpll_sys_ref_clk, + .clk_ref = &dpll_sys_ref_clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO, @@ -876,7 +877,7 @@ static struct dpll_data dpll_unipro_dd = { static struct clk dpll_unipro_ck = { .name = "dpll_unipro_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_unipro_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -913,8 +914,7 @@ static struct clk usb_hs_clk_div_ck = { static struct dpll_data dpll_usb_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, .clk_bypass = &usb_hs_clk_div_ck, - .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL, - .clk_ref = &sys_clkin_ck, + .clk_ref = &dpll_sys_ref_clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, @@ -927,12 +927,13 @@ static struct dpll_data dpll_usb_dd = { .max_multiplier = OMAP4430_MAX_DPLL_MULT, .max_divider = OMAP4430_MAX_DPLL_DIV, .min_divider = 1, + .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL }; static struct clk dpll_usb_ck = { .name = "dpll_usb_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_usb_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -1221,7 +1222,7 @@ static struct clk per_abe_24m_fclk = { static const struct clksel pmd_stm_clock_mux_sel[] = { { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, - { .parent = &tie_low_clock_ck, .rates = div_1_2_rates }, + { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates }, { .parent = NULL }, }; @@ -1239,15 +1240,10 @@ static struct clk pmd_trace_clk_mux_ck = { .recalc = &followparent_recalc, }; -static const struct clksel syc_clk_div_div[] = { - { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; - static struct clk syc_clk_div_ck = { .name = "syc_clk_div_ck", .parent = &sys_clkin_ck, - .clksel = syc_clk_div_div, + .clksel = dpll_sys_ref_clk_div, .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL, .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, .ops = &clkops_null, @@ -1288,13 +1284,13 @@ static struct clk aess_fck = { .recalc = &followparent_recalc, }; -static struct clk bandgap_fclk = { - .name = "bandgap_fclk", +static struct clk cust_efuse_fck = { + .name = "cust_efuse_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, + .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_cefuse_clkdm", + .parent = &sys_clkin_ck, .recalc = &followparent_recalc, }; @@ -1348,56 +1344,6 @@ static struct clk dmic_fck = { .clkdm_name = "abe_clkdm", }; -static struct clk dsp_fck = { - .name = "dsp_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "tesla_clkdm", - .parent = &dpll_iva_m4_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dss_sys_clk = { - .name = "dss_sys_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, - .clkdm_name = "l3_dss_clkdm", - .parent = &syc_clk_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dss_tv_clk = { - .name = "dss_tv_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, - .clkdm_name = "l3_dss_clkdm", - .parent = &extalt_clkin_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dss_dss_clk = { - .name = "dss_dss_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, - .clkdm_name = "l3_dss_clkdm", - .parent = &dpll_per_m5_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dss_48mhz_clk = { - .name = "dss_48mhz_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, - .clkdm_name = "l3_dss_clkdm", - .parent = &func_48mc_fclk, - .recalc = &followparent_recalc, -}; - static struct clk dss_fck = { .name = "dss_fck", .ops = &clkops_omap2_dflt, @@ -1408,18 +1354,18 @@ static struct clk dss_fck = { .recalc = &followparent_recalc, }; -static struct clk efuse_ctrl_cust_fck = { - .name = "efuse_ctrl_cust_fck", +static struct clk ducati_ick = { + .name = "ducati_ick", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_cefuse_clkdm", - .parent = &sys_clkin_ck, + .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .clkdm_name = "ducati_clkdm", + .parent = &ducati_clk_mux_ck, .recalc = &followparent_recalc, }; -static struct clk emif1_fck = { - .name = "emif1_fck", +static struct clk emif1_ick = { + .name = "emif1_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1429,8 +1375,8 @@ static struct clk emif1_fck = { .recalc = &followparent_recalc, }; -static struct clk emif2_fck = { - .name = "emif2_fck", +static struct clk emif2_ick = { + .name = "emif2_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1461,24 +1407,42 @@ static struct clk fdif_fck = { .clkdm_name = "iss_clkdm", }; -static struct clk fpka_fck = { - .name = "fpka_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, +static const struct clksel per_sgx_fclk_div[] = { + { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, + { .parent = NULL }, +}; + +static struct clk per_sgx_fclk = { + .name = "per_sgx_fclk", + .parent = &dpll_per_m2x2_ck, + .clksel = per_sgx_fclk_div, + .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_PER_192M_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static const struct clksel sgx_clk_mux_sel[] = { + { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates }, + { .parent = &per_sgx_fclk, .rates = div_1_1_rates }, + { .parent = NULL }, }; -static struct clk gpio1_dbclk = { - .name = "gpio1_dbclk", +/* Merged sgx_clk_mux into gfx */ +static struct clk gfx_fck = { + .name = "gfx_fck", + .parent = &dpll_core_m7_ck, + .clksel = sgx_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l3_gfx_clkdm", }; static struct clk gpio1_ick = { @@ -1491,16 +1455,6 @@ static struct clk gpio1_ick = { .recalc = &followparent_recalc, }; -static struct clk gpio2_dbclk = { - .name = "gpio2_dbclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - static struct clk gpio2_ick = { .name = "gpio2_ick", .ops = &clkops_omap2_dflt, @@ -1511,16 +1465,6 @@ static struct clk gpio2_ick = { .recalc = &followparent_recalc, }; -static struct clk gpio3_dbclk = { - .name = "gpio3_dbclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - static struct clk gpio3_ick = { .name = "gpio3_ick", .ops = &clkops_omap2_dflt, @@ -1531,16 +1475,6 @@ static struct clk gpio3_ick = { .recalc = &followparent_recalc, }; -static struct clk gpio4_dbclk = { - .name = "gpio4_dbclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - static struct clk gpio4_ick = { .name = "gpio4_ick", .ops = &clkops_omap2_dflt, @@ -1551,16 +1485,6 @@ static struct clk gpio4_ick = { .recalc = &followparent_recalc, }; -static struct clk gpio5_dbclk = { - .name = "gpio5_dbclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - static struct clk gpio5_ick = { .name = "gpio5_ick", .ops = &clkops_omap2_dflt, @@ -1571,16 +1495,6 @@ static struct clk gpio5_ick = { .recalc = &followparent_recalc, }; -static struct clk gpio6_dbclk = { - .name = "gpio6_dbclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - static struct clk gpio6_ick = { .name = "gpio6_ick", .ops = &clkops_omap2_dflt, @@ -1601,114 +1515,278 @@ static struct clk gpmc_ick = { .recalc = &followparent_recalc, }; -static const struct clksel sgx_clk_mux_sel[] = { - { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates }, +static const struct clksel dmt1_clk_mux_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; -/* Merged sgx_clk_mux into gpu */ -static struct clk gpu_fck = { - .name = "gpu_fck", - .parent = &dpll_core_m7_ck, - .clksel = sgx_clk_mux_sel, +/* + * Merged dmt1_clk_mux into gptimer1 + * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention + */ +static struct clk gpt1_fck = { + .name = "gpt1_fck", + .parent = &sys_clkin_ck, + .clksel = dmt1_clk_mux_sel, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, + .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, .ops = &clkops_omap2_dflt, .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, + .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_gfx_clkdm", + .clkdm_name = "l4_wkup_clkdm", }; -static struct clk hdq1w_fck = { - .name = "hdq1w_fck", +/* + * Merged cm2_dm10_mux into gptimer10 + * gptimer10 renamed temporarily into gpt10 to match OMAP3 convention + */ +static struct clk gpt10_fck = { + .name = "gpt10_fck", + .parent = &sys_clkin_ck, + .clksel = dmt1_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", - .parent = &func_12m_fclk, - .recalc = &followparent_recalc, -}; - -static const struct clksel hsi_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, }; -/* Merged hsi_fclk into hsi */ -static struct clk hsi_fck = { - .name = "hsi_fck", - .parent = &dpll_per_m2x2_ck, - .clksel = hsi_fclk_div, - .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, +/* + * Merged cm2_dm11_mux into gptimer11 + * gptimer11 renamed temporarily into gpt11 to match OMAP3 convention + */ +static struct clk gpt11_fck = { + .name = "gpt11_fck", + .parent = &sys_clkin_ck, + .clksel = dmt1_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, .ops = &clkops_omap2_dflt, .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", -}; - -static struct clk i2c1_fck = { - .name = "i2c1_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, }; -static struct clk i2c2_fck = { - .name = "i2c2_fck", +/* + * Merged cm2_dm2_mux into gptimer2 + * gptimer2 renamed temporarily into gpt2 to match OMAP3 convention + */ +static struct clk gpt2_fck = { + .name = "gpt2_fck", + .parent = &sys_clkin_ck, + .clksel = dmt1_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, }; -static struct clk i2c3_fck = { - .name = "i2c3_fck", +/* + * Merged cm2_dm3_mux into gptimer3 + * gptimer3 renamed temporarily into gpt3 to match OMAP3 convention + */ +static struct clk gpt3_fck = { + .name = "gpt3_fck", + .parent = &sys_clkin_ck, + .clksel = dmt1_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, }; -static struct clk i2c4_fck = { - .name = "i2c4_fck", +/* + * Merged cm2_dm4_mux into gptimer4 + * gptimer4 renamed temporarily into gpt4 to match OMAP3 convention + */ +static struct clk gpt4_fck = { + .name = "gpt4_fck", + .parent = &sys_clkin_ck, + .clksel = dmt1_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, +}; + +static const struct clksel timer5_sync_mux_sel[] = { + { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +/* + * Merged timer5_sync_mux into gptimer5 + * gptimer5 renamed temporarily into gpt5 to match OMAP3 convention + */ +static struct clk gpt5_fck = { + .name = "gpt5_fck", + .parent = &syc_clk_div_ck, + .clksel = timer5_sync_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", +}; + +/* + * Merged timer6_sync_mux into gptimer6 + * gptimer6 renamed temporarily into gpt6 to match OMAP3 convention + */ +static struct clk gpt6_fck = { + .name = "gpt6_fck", + .parent = &syc_clk_div_ck, + .clksel = timer5_sync_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", +}; + +/* + * Merged timer7_sync_mux into gptimer7 + * gptimer7 renamed temporarily into gpt7 to match OMAP3 convention + */ +static struct clk gpt7_fck = { + .name = "gpt7_fck", + .parent = &syc_clk_div_ck, + .clksel = timer5_sync_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", +}; + +/* + * Merged timer8_sync_mux into gptimer8 + * gptimer8 renamed temporarily into gpt8 to match OMAP3 convention + */ +static struct clk gpt8_fck = { + .name = "gpt8_fck", + .parent = &syc_clk_div_ck, + .clksel = timer5_sync_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", +}; + +/* + * Merged cm2_dm9_mux into gptimer9 + * gptimer9 renamed temporarily into gpt9 to match OMAP3 convention + */ +static struct clk gpt9_fck = { + .name = "gpt9_fck", + .parent = &sys_clkin_ck, + .clksel = dmt1_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", +}; + +static struct clk hdq1w_fck = { + .name = "hdq1w_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", + .parent = &func_12m_fclk, .recalc = &followparent_recalc, }; -static struct clk ipu_fck = { - .name = "ipu_fck", +/* Merged hsi_fclk into hsi */ +static struct clk hsi_ick = { + .name = "hsi_ick", + .parent = &dpll_per_m2x2_ck, + .clksel = per_sgx_fclk_div, + .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "ducati_clkdm", - .parent = &ducati_clk_mux_ck, + .clkdm_name = "l3_init_clkdm", +}; + +static struct clk i2c1_fck = { + .name = "i2c1_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", + .parent = &func_96m_fclk, .recalc = &followparent_recalc, }; -static struct clk iss_ctrlclk = { - .name = "iss_ctrlclk", +static struct clk i2c2_fck = { + .name = "i2c2_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, - .clkdm_name = "iss_clkdm", + .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", + .parent = &func_96m_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk i2c3_fck = { + .name = "i2c3_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", + .parent = &func_96m_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk i2c4_fck = { + .name = "i2c4_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", .parent = &func_96m_fclk, .recalc = &followparent_recalc, }; @@ -1723,8 +1801,8 @@ static struct clk iss_fck = { .recalc = &followparent_recalc, }; -static struct clk iva_fck = { - .name = "iva_fck", +static struct clk ivahd_ick = { + .name = "ivahd_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1733,8 +1811,8 @@ static struct clk iva_fck = { .recalc = &followparent_recalc, }; -static struct clk kbd_fck = { - .name = "kbd_fck", +static struct clk keyboard_fck = { + .name = "keyboard_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -1743,8 +1821,8 @@ static struct clk kbd_fck = { .recalc = &followparent_recalc, }; -static struct clk l3_instr_ick = { - .name = "l3_instr_ick", +static struct clk l3_instr_interconnect_ick = { + .name = "l3_instr_interconnect_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1753,8 +1831,8 @@ static struct clk l3_instr_ick = { .recalc = &followparent_recalc, }; -static struct clk l3_main_3_ick = { - .name = "l3_main_3_ick", +static struct clk l3_interconnect_3_ick = { + .name = "l3_interconnect_3_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1927,16 +2005,6 @@ static struct clk mcbsp4_fck = { .clkdm_name = "l4_per_clkdm", }; -static struct clk mcpdm_fck = { - .name = "mcpdm_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &pad_clks_ck, - .recalc = &followparent_recalc, -}; - static struct clk mcspi1_fck = { .name = "mcspi1_fck", .ops = &clkops_omap2_dflt, @@ -2037,33 +2105,33 @@ static struct clk mmc5_fck = { .recalc = &followparent_recalc, }; -static struct clk ocp2scp_usb_phy_phy_48m = { - .name = "ocp2scp_usb_phy_phy_48m", +static struct clk ocp_wp1_ick = { + .name = "ocp_wp1_ick", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &func_48m_fclk, + .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .clkdm_name = "l3_instr_clkdm", + .parent = &l3_div_ck, .recalc = &followparent_recalc, }; -static struct clk ocp2scp_usb_phy_ick = { - .name = "ocp2scp_usb_phy_ick", +static struct clk pdm_fck = { + .name = "pdm_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &l4_div_ck, + .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", + .parent = &pad_clks_ck, .recalc = &followparent_recalc, }; -static struct clk ocp_wp_noc_ick = { - .name = "ocp_wp_noc_ick", +static struct clk pkaeip29_fck = { + .name = "pkaeip29_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_instr_clkdm", - .parent = &l3_div_ck, + .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_secure_clkdm", + .parent = &l4_div_ck, .recalc = &followparent_recalc, }; @@ -2077,8 +2145,8 @@ static struct clk rng_ick = { .recalc = &followparent_recalc, }; -static struct clk sha2md5_fck = { - .name = "sha2md5_fck", +static struct clk sha2md51_fck = { + .name = "sha2md51_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2087,8 +2155,8 @@ static struct clk sha2md5_fck = { .recalc = &followparent_recalc, }; -static struct clk sl2if_ick = { - .name = "sl2if_ick", +static struct clk sl2_ick = { + .name = "sl2_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -2097,334 +2165,123 @@ static struct clk sl2if_ick = { .recalc = &followparent_recalc, }; -static struct clk slimbus1_fclk_1 = { - .name = "slimbus1_fclk_1", +static struct clk slimbus1_fck = { + .name = "slimbus1_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "abe_clkdm", - .parent = &func_24m_clk, + .parent = &ocp_abe_iclk, .recalc = &followparent_recalc, }; -static struct clk slimbus1_fclk_0 = { - .name = "slimbus1_fclk_0", +static struct clk slimbus2_fck = { + .name = "slimbus2_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT, - .clkdm_name = "abe_clkdm", - .parent = &abe_24m_fclk, + .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", + .parent = &l4_div_ck, .recalc = &followparent_recalc, }; -static struct clk slimbus1_fclk_2 = { - .name = "slimbus1_fclk_2", +static struct clk sr_core_fck = { + .name = "sr_core_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT, - .clkdm_name = "abe_clkdm", - .parent = &pad_clks_ck, + .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_ao_clkdm", + .parent = &l4_wkup_clk_mux_ck, .recalc = &followparent_recalc, }; -static struct clk slimbus1_slimbus_clk = { - .name = "slimbus1_slimbus_clk", +static struct clk sr_iva_fck = { + .name = "sr_iva_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, - .clkdm_name = "abe_clkdm", - .parent = &slimbus_clk, + .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_ao_clkdm", + .parent = &l4_wkup_clk_mux_ck, .recalc = &followparent_recalc, }; -static struct clk slimbus1_fck = { - .name = "slimbus1_fck", +static struct clk sr_mpu_fck = { + .name = "sr_mpu_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &ocp_abe_iclk, + .clkdm_name = "l4_ao_clkdm", + .parent = &l4_wkup_clk_mux_ck, .recalc = &followparent_recalc, }; -static struct clk slimbus2_fclk_1 = { - .name = "slimbus2_fclk_1", +static struct clk tesla_ick = { + .name = "tesla_ick", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &per_abe_24m_fclk, + .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .clkdm_name = "tesla_clkdm", + .parent = &dpll_iva_m4_ck, .recalc = &followparent_recalc, }; -static struct clk slimbus2_fclk_0 = { - .name = "slimbus2_fclk_0", +static struct clk uart1_fck = { + .name = "uart1_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, + .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", - .parent = &func_24mc_fclk, + .parent = &func_48m_fclk, .recalc = &followparent_recalc, }; -static struct clk slimbus2_slimbus_clk = { - .name = "slimbus2_slimbus_clk", +static struct clk uart2_fck = { + .name = "uart2_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, + .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", - .parent = &pad_slimbus_core_clks_ck, + .parent = &func_48m_fclk, .recalc = &followparent_recalc, }; -static struct clk slimbus2_fck = { - .name = "slimbus2_fck", +static struct clk uart3_fck = { + .name = "uart3_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, + .parent = &func_48m_fclk, .recalc = &followparent_recalc, }; -static struct clk smartreflex_core_fck = { - .name = "smartreflex_core_fck", +static struct clk uart4_fck = { + .name = "uart4_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, + .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_ao_clkdm", - .parent = &l4_wkup_clk_mux_ck, + .clkdm_name = "l4_per_clkdm", + .parent = &func_48m_fclk, .recalc = &followparent_recalc, }; -static struct clk smartreflex_iva_fck = { - .name = "smartreflex_iva_fck", +static struct clk unipro1_fck = { + .name = "unipro1_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, + .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_ao_clkdm", - .parent = &l4_wkup_clk_mux_ck, + .clkdm_name = "l3_init_clkdm", + .parent = &func_96m_fclk, .recalc = &followparent_recalc, }; -static struct clk smartreflex_mpu_fck = { - .name = "smartreflex_mpu_fck", +static struct clk usb_host_fck = { + .name = "usb_host_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_ao_clkdm", - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -/* Merged dmt1_clk_mux into timer1 */ -static struct clk timer1_fck = { - .name = "timer1_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_wkup_clkdm", -}; - -/* Merged cm2_dm10_mux into timer10 */ -static struct clk timer10_fck = { - .name = "timer10_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* Merged cm2_dm11_mux into timer11 */ -static struct clk timer11_fck = { - .name = "timer11_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* Merged cm2_dm2_mux into timer2 */ -static struct clk timer2_fck = { - .name = "timer2_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* Merged cm2_dm3_mux into timer3 */ -static struct clk timer3_fck = { - .name = "timer3_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* Merged cm2_dm4_mux into timer4 */ -static struct clk timer4_fck = { - .name = "timer4_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -static const struct clksel timer5_sync_mux_sel[] = { - { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -/* Merged timer5_sync_mux into timer5 */ -static struct clk timer5_fck = { - .name = "timer5_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* Merged timer6_sync_mux into timer6 */ -static struct clk timer6_fck = { - .name = "timer6_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* Merged timer7_sync_mux into timer7 */ -static struct clk timer7_fck = { - .name = "timer7_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* Merged timer8_sync_mux into timer8 */ -static struct clk timer8_fck = { - .name = "timer8_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* Merged cm2_dm9_mux into timer9 */ -static struct clk timer9_fck = { - .name = "timer9_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -static struct clk uart1_fck = { - .name = "uart1_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk uart2_fck = { - .name = "uart2_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk uart3_fck = { - .name = "uart3_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk uart4_fck = { - .name = "uart4_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, + .clkdm_name = "l3_init_clkdm", + .parent = &init_60m_fclk, .recalc = &followparent_recalc, }; @@ -2438,138 +2295,75 @@ static struct clk usb_host_fs_fck = { .recalc = &followparent_recalc, }; -static struct clk usb_host_hs_utmi_p3_clk = { - .name = "usb_host_hs_utmi_p3_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_hsic60m_p1_clk = { - .name = "usb_host_hs_hsic60m_p1_clk", +static struct clk usb_otg_ick = { + .name = "usb_otg_ick", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_hsic60m_p2_clk = { - .name = "usb_host_hs_hsic60m_p2_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static const struct clksel utmi_p1_gfclk_sel[] = { - { .parent = &init_60m_fclk, .rates = div_1_0_rates }, - { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk utmi_p1_gfclk = { - .name = "utmi_p1_gfclk", - .parent = &init_60m_fclk, - .clksel = utmi_p1_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk usb_host_hs_utmi_p1_clk = { - .name = "usb_host_hs_utmi_p1_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, + .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_init_clkdm", - .parent = &utmi_p1_gfclk, + .parent = &l3_div_ck, .recalc = &followparent_recalc, }; -static const struct clksel utmi_p2_gfclk_sel[] = { - { .parent = &init_60m_fclk, .rates = div_1_0_rates }, - { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk utmi_p2_gfclk = { - .name = "utmi_p2_gfclk", - .parent = &init_60m_fclk, - .clksel = utmi_p2_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk usb_host_hs_utmi_p2_clk = { - .name = "usb_host_hs_utmi_p2_clk", +static struct clk usb_tll_ick = { + .name = "usb_tll_ick", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, + .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_init_clkdm", - .parent = &utmi_p2_gfclk, + .parent = &l4_div_ck, .recalc = &followparent_recalc, }; -static struct clk usb_host_hs_hsic480m_p1_clk = { - .name = "usb_host_hs_hsic480m_p1_clk", +static struct clk usbphyocp2scp_ick = { + .name = "usbphyocp2scp_ick", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, + .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_init_clkdm", - .parent = &dpll_usb_m2_ck, + .parent = &l4_div_ck, .recalc = &followparent_recalc, }; -static struct clk usb_host_hs_hsic480m_p2_clk = { - .name = "usb_host_hs_hsic480m_p2_clk", +static struct clk usim_fck = { + .name = "usim_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &dpll_usb_m2_ck, + .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_wkup_clkdm", + .parent = &sys_32k_ck, .recalc = &followparent_recalc, }; -static struct clk usb_host_hs_func48mclk = { - .name = "usb_host_hs_func48mclk", +static struct clk wdt2_fck = { + .name = "wdt2_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &func_48mc_fclk, + .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_wkup_clkdm", + .parent = &sys_32k_ck, .recalc = &followparent_recalc, }; -static struct clk usb_host_hs_fck = { - .name = "usb_host_hs_fck", +static struct clk wdt3_fck = { + .name = "wdt3_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, + .clkdm_name = "abe_clkdm", + .parent = &sys_32k_ck, .recalc = &followparent_recalc, }; +/* Remaining optional clocks */ static const struct clksel otg_60m_gfclk_sel[] = { { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates }, { .parent = &xclk60motg_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; -static struct clk otg_60m_gfclk = { - .name = "otg_60m_gfclk", +static struct clk otg_60m_gfclk_ck = { + .name = "otg_60m_gfclk_ck", .parent = &utmi_phy_clkout_ck, .clksel = otg_60m_gfclk_sel, .init = &omap2_init_clksel_parent, @@ -2579,74 +2373,38 @@ static struct clk otg_60m_gfclk = { .recalc = &omap2_clksel_recalc, }; -static struct clk usb_otg_hs_xclk = { - .name = "usb_otg_hs_xclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &otg_60m_gfclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_otg_hs_ick = { - .name = "usb_otg_hs_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usb_phy_cm_clk32k = { - .name = "usb_phy_cm_clk32k", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT, - .clkdm_name = "l4_ao_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usb_tll_hs_usb_ch2_clk = { - .name = "usb_tll_hs_usb_ch2_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, +static const struct clksel stm_clk_div_div[] = { + { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, + { .parent = NULL }, }; -static struct clk usb_tll_hs_usb_ch0_clk = { - .name = "usb_tll_hs_usb_ch0_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, +static struct clk stm_clk_div_ck = { + .name = "stm_clk_div_ck", + .parent = &pmd_stm_clock_mux_ck, + .clksel = stm_clk_div_div, + .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, }; -static struct clk usb_tll_hs_usb_ch1_clk = { - .name = "usb_tll_hs_usb_ch1_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, +static const struct clksel trace_clk_div_div[] = { + { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, + { .parent = NULL }, }; -static struct clk usb_tll_hs_ick = { - .name = "usb_tll_hs_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, +static struct clk trace_clk_div_ck = { + .name = "trace_clk_div_ck", + .parent = &pmd_trace_clk_mux_ck, + .clksel = trace_clk_div_div, + .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, }; static const struct clksel_rate div2_14to18_rates[] = { @@ -2660,8 +2418,8 @@ static const struct clksel usim_fclk_div[] = { { .parent = NULL }, }; -static struct clk usim_ck = { - .name = "usim_ck", +static struct clk usim_fclk = { + .name = "usim_fclk", .parent = &dpll_per_m4_ck, .clksel = usim_fclk_div, .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, @@ -2672,79 +2430,38 @@ static struct clk usim_ck = { .set_rate = &omap2_clksel_set_rate, }; -static struct clk usim_fclk = { - .name = "usim_fclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT, - .clkdm_name = "l4_wkup_clkdm", - .parent = &usim_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usim_fck = { - .name = "usim_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk wd_timer2_fck = { - .name = "wd_timer2_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk wd_timer3_fck = { - .name = "wd_timer3_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -/* Remaining optional clocks */ -static const struct clksel stm_clk_div_div[] = { - { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, +static const struct clksel utmi_p1_gfclk_sel[] = { + { .parent = &init_60m_fclk, .rates = div_1_0_rates }, + { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; -static struct clk stm_clk_div_ck = { - .name = "stm_clk_div_ck", - .parent = &pmd_stm_clock_mux_ck, - .clksel = stm_clk_div_div, - .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK, +static struct clk utmi_p1_gfclk_ck = { + .name = "utmi_p1_gfclk_ck", + .parent = &init_60m_fclk, + .clksel = utmi_p1_gfclk_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, .ops = &clkops_null, .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, }; -static const struct clksel trace_clk_div_div[] = { - { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, +static const struct clksel utmi_p2_gfclk_sel[] = { + { .parent = &init_60m_fclk, .rates = div_1_0_rates }, + { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; -static struct clk trace_clk_div_ck = { - .name = "trace_clk_div_ck", - .parent = &pmd_trace_clk_mux_ck, - .clksel = trace_clk_div_div, - .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, +static struct clk utmi_p2_gfclk_ck = { + .name = "utmi_p2_gfclk_ck", + .parent = &init_60m_fclk, + .clksel = utmi_p2_gfclk_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, .ops = &clkops_null, .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, }; /* @@ -2766,12 +2483,11 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), - CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), - CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), + CLK(NULL, "dpll_sys_ref_clk", &dpll_sys_ref_clk, CK_443X), CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), @@ -2841,48 +2557,46 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), CLK(NULL, "aess_fck", &aess_fck, CK_443X), - CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), + CLK(NULL, "cust_efuse_fck", &cust_efuse_fck, CK_443X), CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), - CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), - CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), - CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), - CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), - CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), CLK(NULL, "dss_fck", &dss_fck, CK_443X), - CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), - CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), - CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), + CLK(NULL, "ducati_ick", &ducati_ick, CK_443X), + CLK(NULL, "emif1_ick", &emif1_ick, CK_443X), + CLK(NULL, "emif2_ick", &emif2_ick, CK_443X), CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), - CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), - CLK(NULL, "gpio1_dbck", &gpio1_dbclk, CK_443X), + CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X), + CLK(NULL, "gfx_fck", &gfx_fck, CK_443X), CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), - CLK(NULL, "gpio2_dbck", &gpio2_dbclk, CK_443X), CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), - CLK(NULL, "gpio3_dbck", &gpio3_dbclk, CK_443X), CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), - CLK(NULL, "gpio4_dbck", &gpio4_dbclk, CK_443X), CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), - CLK(NULL, "gpio5_dbck", &gpio5_dbclk, CK_443X), CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), - CLK(NULL, "gpio6_dbck", &gpio6_dbclk, CK_443X), CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), - CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_443X), + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_443X), + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_443X), + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_443X), + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_443X), + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_443X), + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_443X), + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_443X), + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_443X), + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_443X), + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_443X), CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), - CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), + CLK(NULL, "hsi_ick", &hsi_ick, CK_443X), CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X), CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X), CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X), CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X), - CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), - CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), CLK(NULL, "iss_fck", &iss_fck, CK_443X), - CLK(NULL, "iva_fck", &iva_fck, CK_443X), - CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), - CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), - CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), + CLK(NULL, "ivahd_ick", &ivahd_ick, CK_443X), + CLK(NULL, "keyboard_fck", &keyboard_fck, CK_443X), + CLK(NULL, "l3_instr_interconnect_ick", &l3_instr_interconnect_ick, CK_443X), + CLK(NULL, "l3_interconnect_3_ick", &l3_interconnect_3_ick, CK_443X), CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), @@ -2893,7 +2607,6 @@ static struct omap_clk omap44xx_clks[] = { CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), - CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), @@ -2903,66 +2616,43 @@ static struct omap_clk omap44xx_clks[] = { CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), - CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), - CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), - CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), + CLK(NULL, "ocp_wp1_ick", &ocp_wp1_ick, CK_443X), + CLK(NULL, "pdm_fck", &pdm_fck, CK_443X), + CLK(NULL, "pkaeip29_fck", &pkaeip29_fck, CK_443X), CLK("omap_rng", "ick", &rng_ick, CK_443X), - CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), - CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), - CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), - CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), - CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), - CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), + CLK(NULL, "sha2md51_fck", &sha2md51_fck, CK_443X), + CLK(NULL, "sl2_ick", &sl2_ick, CK_443X), CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), - CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), - CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), - CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), - CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), - CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), - CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), - CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X), - CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X), - CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X), - CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X), - CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X), - CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X), - CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X), - CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X), - CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X), - CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X), - CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X), + CLK(NULL, "sr_core_fck", &sr_core_fck, CK_443X), + CLK(NULL, "sr_iva_fck", &sr_iva_fck, CK_443X), + CLK(NULL, "sr_mpu_fck", &sr_mpu_fck, CK_443X), + CLK(NULL, "tesla_ick", &tesla_ick, CK_443X), CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), + CLK(NULL, "unipro1_fck", &unipro1_fck, CK_443X), + CLK(NULL, "usb_host_fck", &usb_host_fck, CK_443X), CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), - CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), - CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), - CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), - CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), - CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), - CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), - CLK("musb_hdrc", "ick", &usb_otg_hs_ick, CK_443X), - CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), - CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), - CLK(NULL, "usim_ck", &usim_ck, CK_443X), - CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), + CLK("musb_hdrc", "ick", &usb_otg_ick, CK_443X), + CLK(NULL, "usb_tll_ick", &usb_tll_ick, CK_443X), + CLK(NULL, "usbphyocp2scp_ick", &usbphyocp2scp_ick, CK_443X), CLK(NULL, "usim_fck", &usim_fck, CK_443X), - CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), - CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), + CLK("omap_wdt", "fck", &wdt2_fck, CK_443X), + CLK(NULL, "wdt3_fck", &wdt3_fck, CK_443X), + CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X), CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), + CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), + CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X), + CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X), + CLK(NULL, "gpio1_dbck", &dummy_ck, CK_443X), + CLK(NULL, "gpio2_dbck", &dummy_ck, CK_443X), + CLK(NULL, "gpio3_dbck", &dummy_ck, CK_443X), + CLK(NULL, "gpio4_dbck", &dummy_ck, CK_443X), + CLK(NULL, "gpio5_dbck", &dummy_ck, CK_443X), + CLK(NULL, "gpio6_dbck", &dummy_ck, CK_443X), CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), @@ -2979,19 +2669,19 @@ static struct omap_clk omap44xx_clks[] = { CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X), CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X), CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X), CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), diff --git a/trunk/arch/arm/mach-omap2/cm-regbits-44xx.h b/trunk/arch/arm/mach-omap2/cm-regbits-44xx.h index 0b72be433776..ac8458e43252 100644 --- a/trunk/arch/arm/mach-omap2/cm-regbits-44xx.h +++ b/trunk/arch/arm/mach-omap2/cm-regbits-44xx.h @@ -1,8 +1,8 @@ /* * OMAP44xx Clock Management register bits * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * Copyright (C) 2009-2010 Nokia Corporation + * Copyright (C) 2009 Texas Instruments, Inc. + * Copyright (C) 2009 Nokia Corporation * * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) @@ -25,459 +25,453 @@ #include "cm.h" -/* - * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, - * CM_TESLA_DYNAMICDEP - */ +/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_ABE_DYNDEP_SHIFT 3 -#define OMAP4430_ABE_DYNDEP_MASK (1 << 3) +#define OMAP4430_ABE_DYNDEP_MASK BITFIELD(3, 3) /* - * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, - * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, + * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, + * CM_TESLA_STATICDEP */ #define OMAP4430_ABE_STATDEP_SHIFT 3 -#define OMAP4430_ABE_STATDEP_MASK (1 << 3) +#define OMAP4430_ABE_STATDEP_MASK BITFIELD(3, 3) -/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ +/* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 -#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) +#define OMAP4430_ALWONCORE_DYNDEP_MASK BITFIELD(16, 16) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 -#define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16) +#define OMAP4430_ALWONCORE_STATDEP_MASK BITFIELD(16, 16) /* - * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, - * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY, - * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, - * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB + * Used by CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB, + * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, + * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU */ #define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 -#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) +#define OMAP4430_AUTO_DPLL_MODE_MASK BITFIELD(0, 2) -/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ +/* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 -#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) +#define OMAP4430_CEFUSE_DYNDEP_MASK BITFIELD(17, 17) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_CEFUSE_STATDEP_SHIFT 17 -#define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17) +#define OMAP4430_CEFUSE_STATDEP_MASK BITFIELD(17, 17) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) +#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK BITFIELD(13, 13) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12) +#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK BITFIELD(12, 12) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK BITFIELD(9, 9) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11) +#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK BITFIELD(11, 11) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK BITFIELD(8, 8) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) +#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK BITFIELD(11, 11) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) +#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK BITFIELD(12, 12) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) +#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK BITFIELD(13, 13) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9) - -/* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12) +#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK BITFIELD(9, 9) /* Used by CM_EMU_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK BITFIELD(9, 9) /* Used by CM_CEFUSE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK BITFIELD(9, 9) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK BITFIELD(9, 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK BITFIELD(9, 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) +#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK BITFIELD(10, 10) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) +#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK BITFIELD(11, 11) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) +#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK BITFIELD(12, 12) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) +#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK BITFIELD(13, 13) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 -#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) +#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK BITFIELD(14, 14) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10) +#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK BITFIELD(10, 10) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK BITFIELD(9, 9) /* Used by CM_DUCATI_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK BITFIELD(8, 8) + +/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ +#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK BITFIELD(10, 10) /* Used by CM_EMU_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK BITFIELD(8, 8) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) +#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK BITFIELD(10, 10) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 -#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) +#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK BITFIELD(15, 15) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) +#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK BITFIELD(10, 10) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) +#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK BITFIELD(11, 11) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 -#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) +#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK BITFIELD(20, 20) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 -#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) +#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK BITFIELD(26, 26) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 -#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) +#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK BITFIELD(21, 21) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 -#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) +#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK BITFIELD(27, 27) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT 31 +#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK BITFIELD(31, 31) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) +#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK BITFIELD(13, 13) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) +#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK BITFIELD(12, 12) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 -#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) +#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK BITFIELD(28, 28) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 -#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) +#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK BITFIELD(29, 29) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) +#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK BITFIELD(11, 11) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 -#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) +#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK BITFIELD(16, 16) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK BITFIELD(17, 17) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK BITFIELD(18, 18) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK BITFIELD(19, 19) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK BITFIELD(8, 8) /* Used by CM_IVAHD_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK BITFIELD(8, 8) -/* Used by CM_D2D_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) +/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ +#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT 14 +#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK BITFIELD(14, 14) /* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK BITFIELD(8, 8) /* Used by CM_D2D_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK BITFIELD(8, 8) /* Used by CM_SDMA_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK BITFIELD(8, 8) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK BITFIELD(8, 8) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK BITFIELD(8, 8) /* Used by CM_GFX_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L3INSTR_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L4SEC_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK BITFIELD(8, 8) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK BITFIELD(8, 8) /* Used by CM_CEFUSE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK BITFIELD(8, 8) /* Used by CM_D2D_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK BITFIELD(9, 9) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK BITFIELD(9, 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L4SEC_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK BITFIELD(9, 9) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) +#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK BITFIELD(12, 12) /* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK BITFIELD(8, 8) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK BITFIELD(9, 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 -#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) +#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK BITFIELD(16, 16) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 -#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) +#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK BITFIELD(17, 17) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 -#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) +#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK BITFIELD(18, 18) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 -#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) +#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK BITFIELD(19, 19) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 -#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) +#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK BITFIELD(25, 25) + +/* Used by CM_EMU_CLKSTCTRL */ +#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK BITFIELD(10, 10) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 -#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) +#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK BITFIELD(20, 20) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 -#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21) +#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK BITFIELD(21, 21) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 -#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) +#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK BITFIELD(22, 22) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 -#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) +#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK BITFIELD(24, 24) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) +#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK BITFIELD(10, 10) /* Used by CM_GFX_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK BITFIELD(9, 9) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11) +#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK BITFIELD(11, 11) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10) +#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK BITFIELD(10, 10) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK BITFIELD(9, 9) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK BITFIELD(8, 8) /* Used by CM_TESLA_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 -#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) +#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK BITFIELD(22, 22) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 -#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) +#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK BITFIELD(23, 23) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 -#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 -#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) +#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK BITFIELD(24, 24) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 -#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) +#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK BITFIELD(15, 15) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) +#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK BITFIELD(10, 10) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 -#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) +#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK BITFIELD(30, 30) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 -#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) +#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK BITFIELD(25, 25) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) +#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK BITFIELD(11, 11) /* - * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, - * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, - * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, + * Used by CM_WKUP_TIMER1_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, - * CM_WKUP_TIMER1_CLKCTRL + * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, + * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, + * CM1_ABE_TIMER8_CLKCTRL */ #define OMAP4430_CLKSEL_SHIFT 24 -#define OMAP4430_CLKSEL_MASK (1 << 24) +#define OMAP4430_CLKSEL_MASK BITFIELD(24, 24) /* * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, - * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ + * CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, + * CM_CLKSEL_USB_60MHZ */ #define OMAP4430_CLKSEL_0_0_SHIFT 0 -#define OMAP4430_CLKSEL_0_0_MASK (1 << 0) +#define OMAP4430_CLKSEL_0_0_MASK BITFIELD(0, 0) /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ #define OMAP4430_CLKSEL_0_1_SHIFT 0 -#define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0) +#define OMAP4430_CLKSEL_0_1_MASK BITFIELD(0, 1) /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ #define OMAP4430_CLKSEL_24_25_SHIFT 24 -#define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24) +#define OMAP4430_CLKSEL_24_25_MASK BITFIELD(24, 25) /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ #define OMAP4430_CLKSEL_60M_SHIFT 24 -#define OMAP4430_CLKSEL_60M_MASK (1 << 24) +#define OMAP4430_CLKSEL_60M_MASK BITFIELD(24, 24) /* Used by CM1_ABE_AESS_CLKCTRL */ #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) +#define OMAP4430_CLKSEL_AESS_FCLK_MASK BITFIELD(24, 24) -/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ +/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_CORE_SHIFT 0 -#define OMAP4430_CLKSEL_CORE_MASK (1 << 0) +#define OMAP4430_CLKSEL_CORE_MASK BITFIELD(0, 0) -/* - * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE, - * CM_SHADOW_FREQ_CONFIG2 - */ +/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ #define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 -#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) +#define OMAP4430_CLKSEL_CORE_1_1_MASK BITFIELD(1, 1) /* Used by CM_WKUP_USIM_CLKCTRL */ #define OMAP4430_CLKSEL_DIV_SHIFT 24 -#define OMAP4430_CLKSEL_DIV_MASK (1 << 24) +#define OMAP4430_CLKSEL_DIV_MASK BITFIELD(24, 24) /* Used by CM_CAM_FDIF_CLKCTRL */ #define OMAP4430_CLKSEL_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) +#define OMAP4430_CLKSEL_FCLK_MASK BITFIELD(24, 25) /* Used by CM_L4PER_MCBSP4_CLKCTRL */ #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25) +#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK BITFIELD(25, 25) /* * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL, @@ -485,869 +479,836 @@ * CM1_ABE_MCBSP3_CLKCTRL */ #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) +#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK BITFIELD(26, 27) -/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ +/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_L3_SHIFT 4 -#define OMAP4430_CLKSEL_L3_MASK (1 << 4) +#define OMAP4430_CLKSEL_L3_MASK BITFIELD(4, 4) -/* - * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE, - * CM_SHADOW_FREQ_CONFIG2 - */ +/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 -#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) +#define OMAP4430_CLKSEL_L3_SHADOW_MASK BITFIELD(2, 2) -/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ +/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_L4_SHIFT 8 -#define OMAP4430_CLKSEL_L4_MASK (1 << 8) +#define OMAP4430_CLKSEL_L4_MASK BITFIELD(8, 8) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_CLKSEL_OPP_SHIFT 0 -#define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0) +#define OMAP4430_CLKSEL_OPP_MASK BITFIELD(0, 1) + +/* Used by CM_GFX_GFX_CLKCTRL */ +#define OMAP4430_CLKSEL_PER_192M_SHIFT 25 +#define OMAP4430_CLKSEL_PER_192M_MASK BITFIELD(25, 26) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 -#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27) +#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK BITFIELD(27, 29) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 -#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) +#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK BITFIELD(24, 26) /* Used by CM_GFX_GFX_CLKCTRL */ #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) +#define OMAP4430_CLKSEL_SGX_FCLK_MASK BITFIELD(24, 24) /* * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL */ #define OMAP4430_CLKSEL_SOURCE_SHIFT 24 -#define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) +#define OMAP4430_CLKSEL_SOURCE_MASK BITFIELD(24, 25) /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 -#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) +#define OMAP4430_CLKSEL_SOURCE_24_24_MASK BITFIELD(24, 24) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 -#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) +#define OMAP4430_CLKSEL_UTMI_P1_MASK BITFIELD(24, 24) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 -#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) +#define OMAP4430_CLKSEL_UTMI_P2_MASK BITFIELD(25, 25) /* - * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL, - * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL, - * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL, - * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL, - * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL, - * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE, - * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL, - * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL, - * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL, - * CM_WKUP_CLKSTCTRL + * Used by CM_WKUP_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_D2D_CLKSTCTRL, + * CM_DUCATI_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL, + * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, + * CM_SDMA_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL, + * CM_L3INIT_CLKSTCTRL, CM_CAM_CLKSTCTRL, CM_CEFUSE_CLKSTCTRL, + * CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3_1_CLKSTCTRL_RESTORE, + * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL_RESTORE, + * CM_L4PER_CLKSTCTRL_RESTORE, CM_MEMIF_CLKSTCTRL_RESTORE, CM_ALWON_CLKSTCTRL, + * CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL, + * CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKTRCTRL_SHIFT 0 -#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) +#define OMAP4430_CLKTRCTRL_MASK BITFIELD(0, 1) /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 -#define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) +#define OMAP4430_CORE_DPLL_EMU_DIV_MASK BITFIELD(0, 6) /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 -#define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_CUSTOM_SHIFT 6 -#define OMAP4430_CUSTOM_MASK (0x3 << 6) +#define OMAP4430_CORE_DPLL_EMU_MULT_MASK BITFIELD(8, 18) -/* - * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP_RESTORE - */ +/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ #define OMAP4430_D2D_DYNDEP_SHIFT 18 -#define OMAP4430_D2D_DYNDEP_MASK (1 << 18) +#define OMAP4430_D2D_DYNDEP_MASK BITFIELD(18, 18) /* Used by CM_MPU_STATICDEP */ #define OMAP4430_D2D_STATDEP_SHIFT 18 -#define OMAP4430_D2D_STATDEP_MASK (1 << 18) +#define OMAP4430_D2D_STATDEP_MASK BITFIELD(18, 18) /* - * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, - * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY, - * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU, - * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, - * CM_SSC_DELTAMSTEP_DPLL_USB + * Used by CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, + * CM_SSC_DELTAMSTEP_DPLL_USB, CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, + * CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, + * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, + * CM_SSC_DELTAMSTEP_DPLL_MPU */ #define OMAP4430_DELTAMSTEP_SHIFT 0 -#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) +#define OMAP4430_DELTAMSTEP_MASK BITFIELD(0, 19) -/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ +/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_DLL_OVERRIDE_SHIFT 2 -#define OMAP4430_DLL_OVERRIDE_MASK (1 << 2) +#define OMAP4430_DLL_OVERRIDE_MASK BITFIELD(2, 2) /* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */ #define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0 -#define OMAP4430_DLL_OVERRIDE_0_0_MASK (1 << 0) +#define OMAP4430_DLL_OVERRIDE_0_0_MASK BITFIELD(0, 0) -/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ +/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_DLL_RESET_SHIFT 3 -#define OMAP4430_DLL_RESET_MASK (1 << 3) +#define OMAP4430_DLL_RESET_MASK BITFIELD(3, 3) /* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, - * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, - * CM_CLKSEL_DPLL_USB + * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB, + * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, + * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU */ #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 -#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) +#define OMAP4430_DPLL_BYP_CLKSEL_MASK BITFIELD(23, 23) /* Used by CM_CLKDCOLDO_DPLL_USB */ #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) +#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK BITFIELD(8, 8) -/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */ +/* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */ #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 -#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) +#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK BITFIELD(20, 20) /* - * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, - * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER + * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, + * CM_DIV_M3_DPLL_CORE */ #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 -#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) +#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK BITFIELD(0, 4) /* - * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, - * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER + * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, + * CM_DIV_M3_DPLL_CORE */ #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 -#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) +#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK BITFIELD(5, 5) /* - * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, - * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER + * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, + * CM_DIV_M3_DPLL_CORE */ #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) +#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK BITFIELD(8, 8) -/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ +/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 -#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) +#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BITFIELD(10, 10) /* - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, - * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO + * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, + * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, + * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU */ #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 -#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) +#define OMAP4430_DPLL_CLKOUT_DIV_MASK BITFIELD(0, 4) /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 -#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) +#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK BITFIELD(0, 6) /* - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, - * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO + * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, + * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, + * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU */ #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) +#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK BITFIELD(5, 5) /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) +#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK BITFIELD(7, 7) /* - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, - * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB + * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE, + * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, + * CM_DIV_M2_DPLL_MPU */ #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) +#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BITFIELD(8, 8) -/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ +/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 -#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) +#define OMAP4430_DPLL_CORE_DPLL_EN_MASK BITFIELD(8, 10) -/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ +/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 -#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) +#define OMAP4430_DPLL_CORE_M2_DIV_MASK BITFIELD(11, 15) -/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ +/* Used by CM_SHADOW_FREQ_CONFIG2 */ #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 -#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) +#define OMAP4430_DPLL_CORE_M5_DIV_MASK BITFIELD(3, 7) + +/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ +#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT 1 +#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK BITFIELD(1, 1) /* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, - * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO + * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, + * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, + * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU */ #define OMAP4430_DPLL_DIV_SHIFT 0 -#define OMAP4430_DPLL_DIV_MASK (0x7f << 0) +#define OMAP4430_DPLL_DIV_MASK BITFIELD(0, 6) /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_DIV_0_7_SHIFT 0 -#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) +#define OMAP4430_DPLL_DIV_0_7_MASK BITFIELD(0, 7) /* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER + * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK BITFIELD(8, 8) /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 -#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) +#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK BITFIELD(3, 3) /* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, - * CM_CLKMODE_DPLL_USB + * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ #define OMAP4430_DPLL_EN_SHIFT 0 -#define OMAP4430_DPLL_EN_MASK (0x7 << 0) +#define OMAP4430_DPLL_EN_MASK BITFIELD(0, 2) /* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO + * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ #define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 -#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) +#define OMAP4430_DPLL_LPMODE_EN_MASK BITFIELD(10, 10) /* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, - * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO + * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, + * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, + * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU */ #define OMAP4430_DPLL_MULT_SHIFT 8 -#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) +#define OMAP4430_DPLL_MULT_MASK BITFIELD(8, 18) /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_MULT_USB_SHIFT 8 -#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) +#define OMAP4430_DPLL_MULT_USB_MASK BITFIELD(8, 19) /* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO + * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ #define OMAP4430_DPLL_REGM4XEN_SHIFT 11 -#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) +#define OMAP4430_DPLL_REGM4XEN_MASK BITFIELD(11, 11) /* Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_SD_DIV_SHIFT 24 -#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) +#define OMAP4430_DPLL_SD_DIV_MASK BITFIELD(24, 31) /* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, - * CM_CLKMODE_DPLL_USB + * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ #define OMAP4430_DPLL_SSC_ACK_SHIFT 13 -#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) +#define OMAP4430_DPLL_SSC_ACK_MASK BITFIELD(13, 13) /* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, - * CM_CLKMODE_DPLL_USB + * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 -#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) +#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK BITFIELD(14, 14) /* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, - * CM_CLKMODE_DPLL_USB + * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ #define OMAP4430_DPLL_SSC_EN_SHIFT 12 -#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) +#define OMAP4430_DPLL_SSC_EN_MASK BITFIELD(12, 12) -/* - * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE - */ +/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ #define OMAP4430_DSS_DYNDEP_SHIFT 8 -#define OMAP4430_DSS_DYNDEP_MASK (1 << 8) +#define OMAP4430_DSS_DYNDEP_MASK BITFIELD(8, 8) /* - * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE + * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, + * CM_MPU_STATICDEP */ #define OMAP4430_DSS_STATDEP_SHIFT 8 -#define OMAP4430_DSS_STATDEP_MASK (1 << 8) +#define OMAP4430_DSS_STATDEP_MASK BITFIELD(8, 8) -/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ +/* Used by CM_L3_2_DYNAMICDEP */ #define OMAP4430_DUCATI_DYNDEP_SHIFT 0 -#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) +#define OMAP4430_DUCATI_DYNDEP_MASK BITFIELD(0, 0) -/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */ +/* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */ #define OMAP4430_DUCATI_STATDEP_SHIFT 0 -#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) +#define OMAP4430_DUCATI_STATDEP_MASK BITFIELD(0, 0) -/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ +/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_FREQ_UPDATE_SHIFT 0 -#define OMAP4430_FREQ_UPDATE_MASK (1 << 0) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_FUNC_SHIFT 16 -#define OMAP4430_FUNC_MASK (0xfff << 16) +#define OMAP4430_FREQ_UPDATE_MASK BITFIELD(0, 0) -/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ +/* Used by CM_L3_2_DYNAMICDEP */ #define OMAP4430_GFX_DYNDEP_SHIFT 10 -#define OMAP4430_GFX_DYNDEP_MASK (1 << 10) +#define OMAP4430_GFX_DYNDEP_MASK BITFIELD(10, 10) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_GFX_STATDEP_SHIFT 10 -#define OMAP4430_GFX_STATDEP_MASK (1 << 10) +#define OMAP4430_GFX_STATDEP_MASK BITFIELD(10, 10) -/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ +/* Used by CM_SHADOW_FREQ_CONFIG2 */ #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 -#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) +#define OMAP4430_GPMC_FREQ_UPDATE_MASK BITFIELD(0, 0) /* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER + * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA */ #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) +#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK BITFIELD(0, 4) /* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER + * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA */ #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK BITFIELD(5, 5) /* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER + * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA */ #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK BITFIELD(8, 8) /* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER + * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA */ #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) +#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK BITFIELD(12, 12) /* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER + * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA */ #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) +#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK BITFIELD(0, 4) /* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER + * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA */ #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK BITFIELD(5, 5) /* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER + * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA */ #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK BITFIELD(8, 8) /* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER + * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA */ #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) +#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK BITFIELD(12, 12) /* - * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER + * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY */ #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) +#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK BITFIELD(0, 4) /* - * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER + * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY */ #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK BITFIELD(5, 5) /* - * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER + * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY */ #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK BITFIELD(8, 8) /* - * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER + * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY */ #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) +#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK BITFIELD(12, 12) /* - * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_PER + * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_CORE */ #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) +#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK BITFIELD(0, 4) /* - * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_PER + * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_CORE */ #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK BITFIELD(5, 5) /* - * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_PER + * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_CORE */ #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK BITFIELD(8, 8) /* - * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_PER + * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_CORE */ #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) - -/* - * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, - * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, - * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, - * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, - * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, - * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, - * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, - * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, - * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE, - * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, - * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, - * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, - * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, +#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK BITFIELD(12, 12) + +/* + * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, + * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, + * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, + * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, + * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, + * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, + * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, + * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, + * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, + * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, + * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, + * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, + * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, + * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, + * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, + * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, + * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, + * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, + * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, + * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, + * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, + * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, + * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, + * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, + * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, + * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, + * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, + * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, + * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, + * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, - * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, - * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, - * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE, - * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, - * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, - * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, - * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, - * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, - * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, - * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, - * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, - * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, - * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, - * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, - * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, - * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, - * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, - * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, - * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, - * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, - * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, - * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, - * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, - * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, - * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, - * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, - * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, - * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, - * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, - * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL + * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, + * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, + * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, + * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, + * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, + * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE, + * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, + * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE, + * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, + * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL, + * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, + * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL, + * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, + * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL, + * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL, + * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, + * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL */ #define OMAP4430_IDLEST_SHIFT 16 -#define OMAP4430_IDLEST_MASK (0x3 << 16) +#define OMAP4430_IDLEST_MASK BITFIELD(16, 17) -/* - * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, - * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE - */ +/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ #define OMAP4430_ISS_DYNDEP_SHIFT 9 -#define OMAP4430_ISS_DYNDEP_MASK (1 << 9) +#define OMAP4430_ISS_DYNDEP_MASK BITFIELD(9, 9) /* - * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, + * CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_ISS_STATDEP_SHIFT 9 -#define OMAP4430_ISS_STATDEP_MASK (1 << 9) +#define OMAP4430_ISS_STATDEP_MASK BITFIELD(9, 9) -/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */ +/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_IVAHD_DYNDEP_SHIFT 2 -#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) +#define OMAP4430_IVAHD_DYNDEP_MASK BITFIELD(2, 2) /* - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, - * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, - * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, + * CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP, + * CM_TESLA_STATICDEP */ #define OMAP4430_IVAHD_STATDEP_SHIFT 2 -#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) +#define OMAP4430_IVAHD_STATDEP_MASK BITFIELD(2, 2) -/* - * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE - */ +/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ #define OMAP4430_L3INIT_DYNDEP_SHIFT 7 -#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) +#define OMAP4430_L3INIT_DYNDEP_MASK BITFIELD(7, 7) /* - * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, - * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, - * CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L3INIT_STATDEP_SHIFT 7 -#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) +#define OMAP4430_L3INIT_STATDEP_MASK BITFIELD(7, 7) /* - * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP, - * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP + * Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, + * CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_L3_1_DYNDEP_SHIFT 5 -#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) +#define OMAP4430_L3_1_DYNDEP_MASK BITFIELD(5, 5) /* - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, - * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, - * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, + * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, + * CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L3_1_STATDEP_SHIFT 5 -#define OMAP4430_L3_1_STATDEP_MASK (1 << 5) +#define OMAP4430_L3_1_STATDEP_MASK BITFIELD(5, 5) /* - * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, - * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, - * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, - * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP + * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, + * CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_SDMA_DYNAMICDEP, + * CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, + * CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP */ #define OMAP4430_L3_2_DYNDEP_SHIFT 6 -#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) +#define OMAP4430_L3_2_DYNDEP_MASK BITFIELD(6, 6) /* - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, - * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, - * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, + * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, + * CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L3_2_STATDEP_SHIFT 6 -#define OMAP4430_L3_2_STATDEP_MASK (1 << 6) +#define OMAP4430_L3_2_STATDEP_MASK BITFIELD(6, 6) -/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */ +/* Used by CM_L3_1_DYNAMICDEP */ #define OMAP4430_L4CFG_DYNDEP_SHIFT 12 -#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) +#define OMAP4430_L4CFG_DYNDEP_MASK BITFIELD(12, 12) /* - * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, - * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, + * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, + * CM_TESLA_STATICDEP */ #define OMAP4430_L4CFG_STATDEP_SHIFT 12 -#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) +#define OMAP4430_L4CFG_STATDEP_MASK BITFIELD(12, 12) -/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ +/* Used by CM_L3_2_DYNAMICDEP */ #define OMAP4430_L4PER_DYNDEP_SHIFT 13 -#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) +#define OMAP4430_L4PER_DYNDEP_MASK BITFIELD(13, 13) /* - * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, - * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, + * CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, + * CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L4PER_STATDEP_SHIFT 13 -#define OMAP4430_L4PER_STATDEP_MASK (1 << 13) +#define OMAP4430_L4PER_STATDEP_MASK BITFIELD(13, 13) -/* - * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, - * CM_L4PER_DYNAMICDEP_RESTORE - */ +/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ #define OMAP4430_L4SEC_DYNDEP_SHIFT 14 -#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) +#define OMAP4430_L4SEC_DYNDEP_MASK BITFIELD(14, 14) /* - * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE + * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */ #define OMAP4430_L4SEC_STATDEP_SHIFT 14 -#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) +#define OMAP4430_L4SEC_STATDEP_MASK BITFIELD(14, 14) -/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ +/* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 -#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) +#define OMAP4430_L4WKUP_DYNDEP_MASK BITFIELD(15, 15) /* - * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 -#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) +#define OMAP4430_L4WKUP_STATDEP_MASK BITFIELD(15, 15) /* - * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP, - * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP + * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, + * CM_MPU_DYNAMICDEP */ #define OMAP4430_MEMIF_DYNDEP_SHIFT 4 -#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) +#define OMAP4430_MEMIF_DYNDEP_MASK BITFIELD(4, 4) /* - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, - * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, - * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, + * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, + * CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_MEMIF_STATDEP_SHIFT 4 -#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) +#define OMAP4430_MEMIF_STATDEP_MASK BITFIELD(4, 4) /* - * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, - * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, - * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, - * CM_SSC_MODFREQDIV_DPLL_USB + * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, + * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, + * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, + * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, + * CM_SSC_MODFREQDIV_DPLL_MPU */ #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 -#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) +#define OMAP4430_MODFREQDIV_EXPONENT_MASK BITFIELD(8, 10) /* - * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, - * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, - * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, - * CM_SSC_MODFREQDIV_DPLL_USB + * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, + * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, + * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, + * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, + * CM_SSC_MODFREQDIV_DPLL_MPU */ #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 -#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) - -/* - * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, - * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, - * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, - * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, - * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, - * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, - * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, - * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, - * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE, - * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, - * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, - * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, - * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, +#define OMAP4430_MODFREQDIV_MANTISSA_MASK BITFIELD(0, 6) + +/* + * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, + * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, + * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, + * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, + * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, + * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, + * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, + * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, + * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, + * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, + * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, + * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, + * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, + * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, + * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, + * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, + * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, + * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, + * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, + * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, + * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, + * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, + * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, + * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, + * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, + * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, + * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, + * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, + * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, + * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, - * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, - * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, - * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE, - * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, - * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, - * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, - * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, - * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, - * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, - * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, - * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, - * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, - * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, - * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, - * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, - * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, - * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, - * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, - * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, - * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, - * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, - * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, - * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, - * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, - * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, - * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, - * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, - * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, - * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, - * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL + * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, + * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, + * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, + * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, + * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, + * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE, + * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, + * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE, + * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, + * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL, + * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, + * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL, + * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, + * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL, + * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL, + * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, + * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL */ #define OMAP4430_MODULEMODE_SHIFT 0 -#define OMAP4430_MODULEMODE_MASK (0x3 << 0) +#define OMAP4430_MODULEMODE_MASK BITFIELD(0, 1) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) +#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK BITFIELD(9, 9) /* Used by CM_WKUP_BANDGAP_CLKCTRL */ #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 -#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK BITFIELD(8, 8) -/* Used by CM_ALWON_USBPHY_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 -#define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8) +/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ +#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 9 +#define OMAP4430_OPTFCLKEN_CLK32K_MASK BITFIELD(9, 9) /* Used by CM_CAM_ISS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK BITFIELD(8, 8) /* - * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, - * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, - * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL + * Used by CM_WKUP_GPIO1_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, + * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, + * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, + * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, + * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_DBCLK_MASK BITFIELD(8, 8) /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK BITFIELD(8, 8) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8) - -/* Used by CM_WKUP_USIM_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_DSSCLK_MASK BITFIELD(8, 8) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 -#define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_FCLK0_MASK BITFIELD(8, 8) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 -#define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9) +#define OMAP4430_OPTFCLKEN_FCLK1_MASK BITFIELD(9, 9) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 -#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) +#define OMAP4430_OPTFCLKEN_FCLK2_MASK BITFIELD(10, 10) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 -#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) +#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK BITFIELD(15, 15) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 -#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) +#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK BITFIELD(13, 13) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 -#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) +#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK BITFIELD(14, 14) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 -#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) +#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK BITFIELD(11, 11) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 -#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) +#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK BITFIELD(12, 12) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK BITFIELD(8, 8) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9) +#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK BITFIELD(9, 9) /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 -#define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_PHY_48M_MASK BITFIELD(8, 8) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10) +#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK BITFIELD(10, 10) /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11) +#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK BITFIELD(11, 11) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) +#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK BITFIELD(10, 10) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 -#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) +#define OMAP4430_OPTFCLKEN_TV_CLK_MASK BITFIELD(11, 11) /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) +#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK BITFIELD(9, 9) /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) +#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK BITFIELD(10, 10) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) +#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK BITFIELD(9, 9) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) +#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK BITFIELD(10, 10) /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_XCLK_MASK BITFIELD(8, 8) -/* Used by CM_EMU_OVERRIDE_DPLL_CORE */ +/* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 -#define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19) +#define OMAP4430_OVERRIDE_ENABLE_MASK BITFIELD(19, 19) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 -#define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8) +#define OMAP4430_PAD_CLKS_GATE_MASK BITFIELD(8, 8) /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ #define OMAP4430_PERF_CURRENT_SHIFT 0 -#define OMAP4430_PERF_CURRENT_MASK (0xff << 0) +#define OMAP4430_PERF_CURRENT_MASK BITFIELD(0, 7) /* * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3, @@ -1355,173 +1316,159 @@ * CM_IVA_DVFS_PERF_TESLA */ #define OMAP4430_PERF_REQ_SHIFT 0 -#define OMAP4430_PERF_REQ_MASK (0xff << 0) +#define OMAP4430_PERF_REQ_MASK BITFIELD(0, 7) + +/* Used by CM_EMU_OVERRIDE_DPLL_PER */ +#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT 0 +#define OMAP4430_PER_DPLL_EMU_DIV_MASK BITFIELD(0, 6) + +/* Used by CM_EMU_OVERRIDE_DPLL_PER */ +#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT 8 +#define OMAP4430_PER_DPLL_EMU_MULT_MASK BITFIELD(8, 18) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE1_COMPLETED_SHIFT 0 -#define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0) +#define OMAP4430_PHASE1_COMPLETED_MASK BITFIELD(0, 0) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 -#define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1) +#define OMAP4430_PHASE2A_COMPLETED_MASK BITFIELD(1, 1) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 -#define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2) +#define OMAP4430_PHASE2B_COMPLETED_MASK BITFIELD(2, 2) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 -#define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20) +#define OMAP4430_PMD_STM_MUX_CTRL_MASK BITFIELD(20, 21) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 -#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) +#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK BITFIELD(22, 23) -/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */ +/* Used by CM_DYN_DEP_PRESCAL */ #define OMAP4430_PRESCAL_SHIFT 0 -#define OMAP4430_PRESCAL_MASK (0x3f << 0) +#define OMAP4430_PRESCAL_MASK BITFIELD(0, 5) -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_R_RTL_SHIFT 11 -#define OMAP4430_R_RTL_MASK (0x1f << 11) +/* Used by REVISION_CM2, REVISION_CM1 */ +#define OMAP4430_REV_SHIFT 0 +#define OMAP4430_REV_MASK BITFIELD(0, 7) /* - * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, - * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE + * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, + * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ #define OMAP4430_SAR_MODE_SHIFT 4 -#define OMAP4430_SAR_MODE_MASK (1 << 4) +#define OMAP4430_SAR_MODE_MASK BITFIELD(4, 4) /* Used by CM_SCALE_FCLK */ #define OMAP4430_SCALE_FCLK_SHIFT 0 -#define OMAP4430_SCALE_FCLK_MASK (1 << 0) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_SCHEME_SHIFT 30 -#define OMAP4430_SCHEME_MASK (0x3 << 30) +#define OMAP4430_SCALE_FCLK_MASK BITFIELD(0, 0) -/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ +/* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_SDMA_DYNDEP_SHIFT 11 -#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) +#define OMAP4430_SDMA_DYNDEP_MASK BITFIELD(11, 11) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_SDMA_STATDEP_SHIFT 11 -#define OMAP4430_SDMA_STATDEP_MASK (1 << 11) +#define OMAP4430_SDMA_STATDEP_MASK BITFIELD(11, 11) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 -#define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10) +#define OMAP4430_SLIMBUS_CLK_GATE_MASK BITFIELD(10, 10) /* - * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, - * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, - * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, - * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, + * Used by CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, + * CM_DUCATI_DUCATI_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, + * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, - * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, - * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, - * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL + * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, + * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, + * CM_CAM_ISS_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, + * CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, + * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL */ #define OMAP4430_STBYST_SHIFT 18 -#define OMAP4430_STBYST_MASK (1 << 18) +#define OMAP4430_STBYST_MASK BITFIELD(18, 18) /* - * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, - * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, - * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB + * Used by CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB, + * CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, + * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU */ #define OMAP4430_ST_DPLL_CLK_SHIFT 0 -#define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) +#define OMAP4430_ST_DPLL_CLK_MASK BITFIELD(0, 0) /* Used by CM_CLKDCOLDO_DPLL_USB */ #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) +#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK BITFIELD(9, 9) /* - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, - * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB + * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE, + * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, + * CM_DIV_M2_DPLL_MPU */ #define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) +#define OMAP4430_ST_DPLL_CLKOUT_MASK BITFIELD(9, 9) /* - * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, - * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER + * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, + * CM_DIV_M3_DPLL_CORE */ #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) +#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK BITFIELD(9, 9) -/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ +/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 -#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) +#define OMAP4430_ST_DPLL_CLKOUTX2_MASK BITFIELD(11, 11) /* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER + * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA */ #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK BITFIELD(9, 9) /* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER + * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA */ #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK BITFIELD(9, 9) /* - * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER + * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY */ #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK BITFIELD(9, 9) /* - * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_PER + * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_CORE */ #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) - -/* - * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, - * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, - * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB - */ -#define OMAP4430_ST_MN_BYPASS_SHIFT 8 -#define OMAP4430_ST_MN_BYPASS_MASK (1 << 8) +#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK BITFIELD(9, 9) /* Used by CM_SYS_CLKSEL */ #define OMAP4430_SYS_CLKSEL_SHIFT 0 -#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) +#define OMAP4430_SYS_CLKSEL_MASK BITFIELD(0, 2) -/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ +/* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_TESLA_DYNDEP_SHIFT 1 -#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) +#define OMAP4430_TESLA_DYNDEP_MASK BITFIELD(1, 1) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_TESLA_STATDEP_SHIFT 1 -#define OMAP4430_TESLA_STATDEP_MASK (1 << 1) +#define OMAP4430_TESLA_STATDEP_MASK BITFIELD(1, 1) /* - * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP, - * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, - * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, - * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP + * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, + * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, + * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_WINDOWSIZE_SHIFT 24 -#define OMAP4430_WINDOWSIZE_MASK (0xf << 24) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_X_MAJOR_SHIFT 8 -#define OMAP4430_X_MAJOR_MASK (0x7 << 8) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_Y_MINOR_SHIFT 0 -#define OMAP4430_Y_MINOR_MASK (0x3f << 0) +#define OMAP4430_WINDOWSIZE_MASK BITFIELD(24, 27) #endif diff --git a/trunk/arch/arm/mach-omap2/cm44xx.h b/trunk/arch/arm/mach-omap2/cm44xx.h index 3c35a87cb90c..336d94889e5b 100644 --- a/trunk/arch/arm/mach-omap2/cm44xx.h +++ b/trunk/arch/arm/mach-omap2/cm44xx.h @@ -195,42 +195,6 @@ #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088) -/* CM1.RESTORE_CM1 register offsets */ -#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000 -#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000) -#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004 -#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004) -#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008 -#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008) -#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c -#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c) -#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010 -#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010) -#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014 -#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014) -#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018 -#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018) -#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c -#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024 -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024) -#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028 -#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028) -#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c -#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c) -#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030 -#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030) -#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034 -#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034) -#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038 -#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0038) -#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c -#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x003c) -#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040 -#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0040) - /* CM2 */ /* CM2.OCP_SOCKET_CM2 register offsets */ @@ -288,6 +252,8 @@ #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068) #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c) +#define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET 0x0070 +#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070) #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 #define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080) #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 @@ -330,8 +296,6 @@ #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030) #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038) -#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0040) /* CM2.CORE_CM2 register offsets */ #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 @@ -614,54 +578,4 @@ #define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000) #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020) - -/* CM2.RESTORE_CM2 register offsets */ -#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000 -#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000) -#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004 -#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004) -#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008 -#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008) -#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c -#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c) -#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010 -#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010) -#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014 -#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014) -#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018 -#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018) -#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c -#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c) -#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020 -#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020) -#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024 -#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024) -#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028 -#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028) -#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c -#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c) -#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030 -#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030) -#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034 -#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034) -#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038 -#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038) -#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c -#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c) -#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040 -#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040) -#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044 -#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0044) -#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048 -#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0048) -#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c -#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x004c) -#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050 -#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0050) -#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054 -#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0054) -#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058 -#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0058) -#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c -#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x005c) #endif diff --git a/trunk/arch/arm/mach-omap2/cm4xxx.c b/trunk/arch/arm/mach-omap2/cm4xxx.c index f8a660a1a4a6..b101091e95d6 100644 --- a/trunk/arch/arm/mach-omap2/cm4xxx.c +++ b/trunk/arch/arm/mach-omap2/cm4xxx.c @@ -43,6 +43,7 @@ * using separate functional clock * 0x3 disabled: Module is disabled and cannot be accessed * + * TODO: Need to handle module accessible in idle state */ int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg) { @@ -51,11 +52,9 @@ int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg) if (!clkctrl_reg) return 0; - omap_test_timeout(( - ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) || - (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >> - OMAP4430_IDLEST_SHIFT) == 0x2)), - MAX_MODULE_READY_TIME, i); + omap_test_timeout(((__raw_readl(clkctrl_reg) & + OMAP4430_IDLEST_MASK) == 0), + MAX_MODULE_READY_TIME, i); return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; } diff --git a/trunk/arch/arm/mach-omap2/control.c b/trunk/arch/arm/mach-omap2/control.c index 5d9b30dd6e56..a8d20eef2306 100644 --- a/trunk/arch/arm/mach-omap2/control.c +++ b/trunk/arch/arm/mach-omap2/control.c @@ -23,10 +23,8 @@ #include "cm.h" #include "prm.h" #include "sdrc.h" -#include "pm.h" static void __iomem *omap2_ctrl_base; -static void __iomem *omap4_ctrl_pad_base; #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) struct omap3_scratchpad { @@ -139,7 +137,6 @@ static struct omap3_control_regs control_context; #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) -#define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) void __init omap2_set_globals_control(struct omap_globals *omap2_globals) { @@ -148,12 +145,6 @@ void __init omap2_set_globals_control(struct omap_globals *omap2_globals) omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K); WARN_ON(!omap2_ctrl_base); } - - /* Static mapping, never released */ - if (omap2_globals->ctrl_pad) { - omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K); - WARN_ON(!omap4_ctrl_pad_base); - } } void __iomem *omap_ctrl_base_get(void) @@ -191,23 +182,6 @@ void omap_ctrl_writel(u32 val, u16 offset) __raw_writel(val, OMAP_CTRL_REGADDR(offset)); } -/* - * On OMAP4 control pad are not addressable from control - * core base. So the common omap_ctrl_read/write APIs breaks - * Hence export separate APIs to manage the omap4 pad control - * registers. This APIs will work only for OMAP4 - */ - -u32 omap4_ctrl_pad_readl(u16 offset) -{ - return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset)); -} - -void omap4_ctrl_pad_writel(u32 val, u16 offset) -{ - __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset)); -} - #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) /* * Clears the scratchpad contents in case of cold boot- @@ -216,7 +190,7 @@ void omap4_ctrl_pad_writel(u32 val, u16 offset) void omap3_clear_scratchpad_contents(void) { u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; - void __iomem *v_addr; + u32 *v_addr; u32 offset = 0; v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & @@ -232,7 +206,7 @@ void omap3_clear_scratchpad_contents(void) /* Populate the scratchpad structure with restore structure */ void omap3_save_scratchpad_contents(void) { - void __iomem *scratchpad_address; + void * __iomem scratchpad_address; u32 arm_context_addr; struct omap3_scratchpad scratchpad_contents; struct omap3_scratchpad_prcm_block prcm_block_contents; diff --git a/trunk/arch/arm/mach-omap2/cpuidle34xx.c b/trunk/arch/arm/mach-omap2/cpuidle34xx.c index 8ea012ef0b5a..703b5ec88e98 100644 --- a/trunk/arch/arm/mach-omap2/cpuidle34xx.c +++ b/trunk/arch/arm/mach-omap2/cpuidle34xx.c @@ -272,10 +272,8 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev, */ per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd); if ((per_next_state == PWRDM_POWER_OFF) && - (core_next_state > PWRDM_POWER_RET)) { + (core_next_state > PWRDM_POWER_RET)) per_next_state = PWRDM_POWER_RET; - pwrdm_set_next_pwrst(per_pd, per_next_state); - } /* Are we changing PER target state? */ if (per_next_state != per_saved_state) diff --git a/trunk/arch/arm/mach-omap2/devices.c b/trunk/arch/arm/mach-omap2/devices.c index 9e5d51bee94a..2dbb265bedd4 100644 --- a/trunk/arch/arm/mach-omap2/devices.c +++ b/trunk/arch/arm/mach-omap2/devices.c @@ -498,76 +498,6 @@ static void omap_init_sham(void) static inline void omap_init_sham(void) { } #endif -#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE) - -#ifdef CONFIG_ARCH_OMAP2 -static struct resource omap2_aes_resources[] = { - { - .start = OMAP24XX_SEC_AES_BASE, - .end = OMAP24XX_SEC_AES_BASE + 0x4C, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP24XX_DMA_AES_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = OMAP24XX_DMA_AES_RX, - .flags = IORESOURCE_DMA, - } -}; -static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources); -#else -#define omap2_aes_resources NULL -#define omap2_aes_resources_sz 0 -#endif - -#ifdef CONFIG_ARCH_OMAP3 -static struct resource omap3_aes_resources[] = { - { - .start = OMAP34XX_SEC_AES_BASE, - .end = OMAP34XX_SEC_AES_BASE + 0x4C, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP34XX_DMA_AES2_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = OMAP34XX_DMA_AES2_RX, - .flags = IORESOURCE_DMA, - } -}; -static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources); -#else -#define omap3_aes_resources NULL -#define omap3_aes_resources_sz 0 -#endif - -static struct platform_device aes_device = { - .name = "omap-aes", - .id = -1, -}; - -static void omap_init_aes(void) -{ - if (cpu_is_omap24xx()) { - aes_device.resource = omap2_aes_resources; - aes_device.num_resources = omap2_aes_resources_sz; - } else if (cpu_is_omap34xx()) { - aes_device.resource = omap3_aes_resources; - aes_device.num_resources = omap3_aes_resources_sz; - } else { - pr_err("%s: platform not supported\n", __func__); - return; - } - platform_device_register(&aes_device); -} - -#else -static inline void omap_init_aes(void) { } -#endif - /*-------------------------------------------------------------------------*/ #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) @@ -694,7 +624,7 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, omap_mux_init_signal("sdmmc_dat0", 0); omap_mux_init_signal("sdmmc_dat_dir0", 0); omap_mux_init_signal("sdmmc_cmd_dir", 0); - if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { + if (mmc_controller->slots[0].wires == 4) { omap_mux_init_signal("sdmmc_dat1", 0); omap_mux_init_signal("sdmmc_dat2", 0); omap_mux_init_signal("sdmmc_dat3", 0); @@ -722,8 +652,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc1_dat0", OMAP_PIN_INPUT_PULLUP); - if (mmc_controller->slots[0].caps & - (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { + if (mmc_controller->slots[0].wires == 4 || + mmc_controller->slots[0].wires == 8) { omap_mux_init_signal("sdmmc1_dat1", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc1_dat2", @@ -731,8 +661,7 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, omap_mux_init_signal("sdmmc1_dat3", OMAP_PIN_INPUT_PULLUP); } - if (mmc_controller->slots[0].caps & - MMC_CAP_8_BIT_DATA) { + if (mmc_controller->slots[0].wires == 8) { omap_mux_init_signal("sdmmc1_dat4", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc1_dat5", @@ -756,8 +685,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed * in the board-*.c files */ - if (mmc_controller->slots[0].caps & - (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { + if (mmc_controller->slots[0].wires == 4 || + mmc_controller->slots[0].wires == 8) { omap_mux_init_signal("sdmmc2_dat1", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc2_dat2", @@ -765,8 +694,7 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, omap_mux_init_signal("sdmmc2_dat3", OMAP_PIN_INPUT_PULLUP); } - if (mmc_controller->slots[0].caps & - MMC_CAP_8_BIT_DATA) { + if (mmc_controller->slots[0].wires == 8) { omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", @@ -926,7 +854,6 @@ static int __init omap2_init_devices(void) omap_hdq_init(); omap_init_sti(); omap_init_sham(); - omap_init_aes(); omap_init_vout(); return 0; diff --git a/trunk/arch/arm/mach-omap2/gpmc-smsc911x.c b/trunk/arch/arm/mach-omap2/gpmc-smsc911x.c deleted file mode 100644 index 703f150dd01d..000000000000 --- a/trunk/arch/arm/mach-omap2/gpmc-smsc911x.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/gpmc-smsc911x.c - * - * Copyright (C) 2009 Li-Pro.Net - * Stephan Linz - * - * Modified from linux/arch/arm/mach-omap2/gpmc-smc91x.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -static struct omap_smsc911x_platform_data *gpmc_cfg; - -static struct resource gpmc_smsc911x_resources[] = { - [0] = { - .flags = IORESOURCE_MEM, - }, - [1] = { - .flags = IORESOURCE_IRQ, - }, -}; - -static struct smsc911x_platform_config gpmc_smsc911x_config = { - .phy_interface = PHY_INTERFACE_MODE_MII, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .flags = SMSC911X_USE_16BIT, -}; - -static struct platform_device gpmc_smsc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(gpmc_smsc911x_resources), - .resource = gpmc_smsc911x_resources, - .dev = { - .platform_data = &gpmc_smsc911x_config, - }, -}; - -/* - * Initialize smsc911x device connected to the GPMC. Note that we - * assume that pin multiplexing is done in the board-*.c file, - * or in the bootloader. - */ -void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data) -{ - unsigned long cs_mem_base; - int ret; - - gpmc_cfg = board_data; - - if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) { - printk(KERN_ERR "Failed to request GPMC mem for smsc911x\n"); - return; - } - - gpmc_smsc911x_resources[0].start = cs_mem_base + 0x0; - gpmc_smsc911x_resources[0].end = cs_mem_base + 0xff; - - if (gpio_request(gpmc_cfg->gpio_irq, "smsc911x irq") < 0) { - printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n", - gpmc_cfg->gpio_irq); - goto free1; - } - - gpio_direction_input(gpmc_cfg->gpio_irq); - gpmc_smsc911x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq); - gpmc_smsc911x_resources[1].flags |= - (gpmc_cfg->flags & IRQF_TRIGGER_MASK); - - if (gpio_is_valid(gpmc_cfg->gpio_reset)) { - ret = gpio_request(gpmc_cfg->gpio_reset, "smsc911x reset"); - if (ret) { - printk(KERN_ERR "Failed to request GPIO%d for smsc911x reset\n", - gpmc_cfg->gpio_reset); - goto free2; - } - - gpio_direction_output(gpmc_cfg->gpio_reset, 1); - gpio_set_value(gpmc_cfg->gpio_reset, 0); - msleep(100); - gpio_set_value(gpmc_cfg->gpio_reset, 1); - } - - if (platform_device_register(&gpmc_smsc911x_device) < 0) { - printk(KERN_ERR "Unable to register smsc911x device\n"); - gpio_free(gpmc_cfg->gpio_reset); - goto free2; - } - - return; - -free2: - gpio_free(gpmc_cfg->gpio_irq); -free1: - gpmc_cs_free(gpmc_cfg->cs); - - printk(KERN_ERR "Could not initialize smsc911x\n"); -} diff --git a/trunk/arch/arm/mach-omap2/hsmmc.c b/trunk/arch/arm/mach-omap2/hsmmc.c index eb92b8107d2c..c8f647b6205e 100644 --- a/trunk/arch/arm/mach-omap2/hsmmc.c +++ b/trunk/arch/arm/mach-omap2/hsmmc.c @@ -135,11 +135,10 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, * * FIXME handle VMMC1A as needed ... */ - reg = omap4_ctrl_pad_readl(control_pbias_offset); - reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | - OMAP4_MMC1_PWRDNZ_MASK | - OMAP4_USBC1_ICUSB_PWRDNZ_MASK); - omap4_ctrl_pad_writel(reg, control_pbias_offset); + reg = omap_ctrl_readl(control_pbias_offset); + reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | + OMAP4_USBC1_ICUSB_PWRDNZ); + omap_ctrl_writel(reg, control_pbias_offset); } static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, @@ -148,33 +147,30 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, u32 reg; if (power_on) { - reg = omap4_ctrl_pad_readl(control_pbias_offset); - reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK; + reg = omap_ctrl_readl(control_pbias_offset); + reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ; if ((1 << vdd) <= MMC_VDD_165_195) - reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK; + reg &= ~OMAP4_MMC1_PBIASLITE_VMODE; else - reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK; - reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | - OMAP4_MMC1_PWRDNZ_MASK | - OMAP4_USBC1_ICUSB_PWRDNZ_MASK); - omap4_ctrl_pad_writel(reg, control_pbias_offset); + reg |= OMAP4_MMC1_PBIASLITE_VMODE; + reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | + OMAP4_USBC1_ICUSB_PWRDNZ); + omap_ctrl_writel(reg, control_pbias_offset); /* 4 microsec delay for comparator to generate an error*/ udelay(4); - reg = omap4_ctrl_pad_readl(control_pbias_offset); - if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) { + reg = omap_ctrl_readl(control_pbias_offset); + if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR) { pr_err("Pbias Voltage is not same as LDO\n"); /* Caution : On VMODE_ERROR Power Down MMC IO */ - reg &= ~(OMAP4_MMC1_PWRDNZ_MASK | - OMAP4_USBC1_ICUSB_PWRDNZ_MASK); - omap4_ctrl_pad_writel(reg, control_pbias_offset); + reg &= ~(OMAP4_MMC1_PWRDNZ | OMAP4_USBC1_ICUSB_PWRDNZ); + omap_ctrl_writel(reg, control_pbias_offset); } } else { - reg = omap4_ctrl_pad_readl(control_pbias_offset); - reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | - OMAP4_MMC1_PWRDNZ_MASK | - OMAP4_MMC1_PBIASLITE_VMODE_MASK | - OMAP4_USBC1_ICUSB_PWRDNZ_MASK); - omap4_ctrl_pad_writel(reg, control_pbias_offset); + reg = omap_ctrl_readl(control_pbias_offset); + reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | + OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ | + OMAP4_USBC1_ICUSB_PWRDNZ); + omap_ctrl_writel(reg, control_pbias_offset); } } @@ -222,18 +218,17 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; } } else { - control_pbias_offset = - OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; - control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; - reg = omap4_ctrl_pad_readl(control_mmc1); - reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | - OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); - reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | - OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); - reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| - OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | - OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); - omap4_ctrl_pad_writel(reg, control_mmc1); + control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE; + control_mmc1 = OMAP44XX_CONTROL_MMC1; + reg = omap_ctrl_readl(control_mmc1); + reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 | + OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1); + reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 | + OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3); + reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL | + OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL | + OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL); + omap_ctrl_writel(reg, control_mmc1); } for (c = controllers; c->mmc; c++) { @@ -263,7 +258,7 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) "mmc%islot%i", c->mmc, 1); mmc->slots[0].name = hc->name; mmc->nr_slots = 1; - mmc->slots[0].caps = c->caps; + mmc->slots[0].wires = c->wires; mmc->slots[0].internal_clock = !c->ext_clock; mmc->dma_mask = 0xffffffff; @@ -321,20 +316,16 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) } /* Omap3630 HSMMC1 supports only 4-bit */ - if (cpu_is_omap3630() && - (c->caps & MMC_CAP_8_BIT_DATA)) { - c->caps &= ~MMC_CAP_8_BIT_DATA; - c->caps |= MMC_CAP_4_BIT_DATA; - mmc->slots[0].caps = c->caps; + if (cpu_is_omap3630() && c->wires > 4) { + c->wires = 4; + mmc->slots[0].wires = c->wires; } break; case 2: if (c->ext_clock) c->transceiver = 1; - if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { - c->caps &= ~MMC_CAP_8_BIT_DATA; - c->caps |= MMC_CAP_4_BIT_DATA; - } + if (c->transceiver && c->wires > 4) + c->wires = 4; /* FALLTHROUGH */ case 3: if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { diff --git a/trunk/arch/arm/mach-omap2/hsmmc.h b/trunk/arch/arm/mach-omap2/hsmmc.h index 281e97287adf..1fe6f0187177 100644 --- a/trunk/arch/arm/mach-omap2/hsmmc.h +++ b/trunk/arch/arm/mach-omap2/hsmmc.h @@ -10,8 +10,7 @@ struct mmc_card; struct omap2_hsmmc_info { u8 mmc; /* controller 1/2/3 */ - u32 caps; /* 4/8 wires and any additional host - * capabilities OR'd (ref. linux/mmc/host.h) */ + u8 wires; /* 1/4/8 wires */ bool transceiver; /* MMC-2 option */ bool ext_clock; /* use external pin for input clock */ bool cover_only; /* No card detect - just cover switch */ diff --git a/trunk/arch/arm/mach-omap2/id.c b/trunk/arch/arm/mach-omap2/id.c index 0412233da2b3..9a879f959509 100644 --- a/trunk/arch/arm/mach-omap2/id.c +++ b/trunk/arch/arm/mach-omap2/id.c @@ -60,7 +60,7 @@ int omap_type(void) } else if (cpu_is_omap34xx()) { val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); } else if (cpu_is_omap44xx()) { - val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); + val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS); } else { pr_err("Cannot detect omap type!\n"); goto out; @@ -298,6 +298,7 @@ static void __init omap4_check_revision(void) u32 idcode; u16 hawkeye; u8 rev; + char *rev_name = "ES1.0"; /* * The IC rev detection is done with hawkeye and rev. @@ -308,39 +309,14 @@ static void __init omap4_check_revision(void) hawkeye = (idcode >> 12) & 0xffff; rev = (idcode >> 28) & 0xff; - /* - * Few initial ES2.0 samples IDCODE is same as ES1.0 - * Use ARM register to detect the correct ES version - */ - if (!rev) { - idcode = read_cpuid(CPUID_ID); - rev = (idcode & 0xf) - 1; - } - - switch (hawkeye) { - case 0xb852: - switch (rev) { - case 0: - omap_revision = OMAP4430_REV_ES1_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES1; - break; - case 1: - omap_revision = OMAP4430_REV_ES2_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES2; - break; - default: - omap_revision = OMAP4430_REV_ES2_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES2; - } - break; - default: - /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP4430_REV_ES2_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES2; + if ((hawkeye == 0xb852) && (rev == 0x0)) { + omap_revision = OMAP4430_REV_ES1_0; + omap_chip.oc |= CHIP_IS_OMAP4430ES1; + pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); + return; } - pr_info("OMAP%04x ES%d.0\n", - omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1); + pr_err("Unknown OMAP4 CPU id\n"); } #define OMAP3_SHOW_FEATURE(feat) \ diff --git a/trunk/arch/arm/mach-omap2/board-flash.h b/trunk/arch/arm/mach-omap2/include/mach/board-flash.h similarity index 88% rename from trunk/arch/arm/mach-omap2/board-flash.h rename to trunk/arch/arm/mach-omap2/include/mach/board-flash.h index 69befe00dd2f..b2242ae2bb6f 100644 --- a/trunk/arch/arm/mach-omap2/board-flash.h +++ b/trunk/arch/arm/mach-omap2/include/mach/board-flash.h @@ -26,5 +26,3 @@ struct flash_partitions { extern void board_flash_init(struct flash_partitions [], char chip_sel[][GPMC_CS_NUM]); -extern void board_nand_init(struct mtd_partition *nand_parts, - u8 nr_parts, u8 cs); diff --git a/trunk/arch/arm/mach-omap2/include/mach/board-rx51.h b/trunk/arch/arm/mach-omap2/include/mach/board-rx51.h deleted file mode 100644 index b76f49e7eed5..000000000000 --- a/trunk/arch/arm/mach-omap2/include/mach/board-rx51.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Defines for rx51 boards - */ - -#ifndef _OMAP_BOARD_RX51_H -#define _OMAP_BOARD_RX51_H - -extern void __init rx51_peripherals_init(void); -extern void __init rx51_video_mem_init(void); - -#endif diff --git a/trunk/arch/arm/mach-omap2/include/mach/board-zoom.h b/trunk/arch/arm/mach-omap2/include/mach/board-zoom.h index 3986f2476b1c..3af69d2c3dcd 100644 --- a/trunk/arch/arm/mach-omap2/include/mach/board-zoom.h +++ b/trunk/arch/arm/mach-omap2/include/mach/board-zoom.h @@ -1,7 +1,11 @@ /* * Defines for zoom boards */ +#include +#include + #define ZOOM_NAND_CS 0 +extern void __init board_nand_init(struct mtd_partition *, u8 nr_parts, u8 cs); extern int __init zoom_debugboard_init(void); extern void __init zoom_peripherals_init(void); diff --git a/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h deleted file mode 100644 index 2f7ac70a20d8..000000000000 --- a/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h +++ /dev/null @@ -1,391 +0,0 @@ -/* - * OMAP44xx CTRL_MODULE_CORE registers and bitfields - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * - * Benoit Cousson (b-cousson@ti.com) - * Santosh Shilimkar (santosh.shilimkar@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H - - -/* Base address */ -#define OMAP4_CTRL_MODULE_CORE 0x4a002000 - -/* Registers offset */ -#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000 -#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004 -#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200 -#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268 -#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 -#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300 -#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314 -#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318 -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320 -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324 -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328 -#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c -#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330 -#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334 -#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c -#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340 -#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350 -#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400 -#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408 -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430 -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434 -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438 -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440 -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444 -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448 -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450 -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc - -/* Registers shifts and masks */ - -/* IP_REVISION */ -#define OMAP4_IP_REV_SCHEME_SHIFT 30 -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) -#define OMAP4_IP_REV_FUNC_SHIFT 16 -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) -#define OMAP4_IP_REV_RTL_SHIFT 11 -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) -#define OMAP4_IP_REV_MAJOR_SHIFT 8 -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) -#define OMAP4_IP_REV_CUSTOM_SHIFT 6 -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) -#define OMAP4_IP_REV_MINOR_SHIFT 0 -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) - -/* IP_HWINFO */ -#define OMAP4_IP_HWINFO_SHIFT 0 -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) - -/* IP_SYSCONFIG */ -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) - -/* STD_FUSE_DIE_ID_0 */ -#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0 -#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0) - -/* ID_CODE */ -#define OMAP4_STD_FUSE_IDCODE_SHIFT 0 -#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0) - -/* STD_FUSE_DIE_ID_1 */ -#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0 -#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0) - -/* STD_FUSE_DIE_ID_2 */ -#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0 -#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0) - -/* STD_FUSE_DIE_ID_3 */ -#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0 -#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0) - -/* STD_FUSE_PROD_ID_0 */ -#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0 -#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0) - -/* STD_FUSE_PROD_ID_1 */ -#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0 -#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0) - -/* STD_FUSE_USB_CONF */ -#define OMAP4_USB_PROD_ID_SHIFT 16 -#define OMAP4_USB_PROD_ID_MASK (0xffff << 16) -#define OMAP4_USB_VENDOR_ID_SHIFT 0 -#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0) - -/* STD_FUSE_OPP_VDD_WKUP */ -#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0 -#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0) - -/* STD_FUSE_OPP_BGAP */ -#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0 -#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0) - -/* STD_FUSE_OPP_DPLL_0 */ -#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0 -#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0) - -/* STD_FUSE_OPP_DPLL_1 */ -#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0 -#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0) - -/* STATUS */ -#define OMAP4_ATTILA_CONF_SHIFT 11 -#define OMAP4_ATTILA_CONF_MASK (0x3 << 11) -#define OMAP4_DEVICE_TYPE_SHIFT 8 -#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8) -#define OMAP4_SYS_BOOT_SHIFT 0 -#define OMAP4_SYS_BOOT_MASK (0xff << 0) - -/* DEV_CONF */ -#define OMAP4_DEV_CONF_SHIFT 1 -#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1) -#define OMAP4_USBPHY_PD_SHIFT 0 -#define OMAP4_USBPHY_PD_MASK (1 << 0) - -/* LDOVBB_IVA_VOLTAGE_CTRL */ -#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26 -#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26) -#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21 -#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21) -#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16 -#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16) -#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10 -#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10) -#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5 -#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5) -#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0 -#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0) - -/* LDOVBB_MPU_VOLTAGE_CTRL */ -#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26 -#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26) -#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21 -#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21) -#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16 -#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16) -#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10 -#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10) -#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5 -#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5) -#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0 -#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0) - -/* LDOSRAM_IVA_VOLTAGE_CTRL */ -#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26 -#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26) -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21 -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21) -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16 -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16) -#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10 -#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10) -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5 -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5) -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0 -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0) - -/* LDOSRAM_MPU_VOLTAGE_CTRL */ -#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26 -#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26) -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21 -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21) -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16 -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16) -#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10 -#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10) -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5 -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5) -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0 -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0) - -/* LDOSRAM_CORE_VOLTAGE_CTRL */ -#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26 -#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26) -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21 -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21) -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16 -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16) -#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10 -#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10) -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5 -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5) -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0 -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0) - -/* TEMP_SENSOR */ -#define OMAP4_BGAP_TEMPSOFF_SHIFT 12 -#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12) -#define OMAP4_BGAP_TSHUT_SHIFT 11 -#define OMAP4_BGAP_TSHUT_MASK (1 << 11) -#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10 -#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10) -#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9 -#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9) -#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8 -#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8) -#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0 -#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0) - -/* DPLL_NWELL_TRIM_0 */ -#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29 -#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) -#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24 -#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24) -#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23 -#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) -#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18 -#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18) -#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17 -#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) -#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12 -#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12) -#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11 -#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) -#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6 -#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6) -#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5 -#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) -#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0 -#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0) - -/* DPLL_NWELL_TRIM_1 */ -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29 -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24 -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24) -#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23 -#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) -#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18 -#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18) -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17 -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) -#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12 -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12) -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11 -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) -#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6 -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6) -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5 -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) -#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0 -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0) - -/* USBOTGHS_CONTROL */ -#define OMAP4_DISCHRGVBUS_SHIFT 8 -#define OMAP4_DISCHRGVBUS_MASK (1 << 8) -#define OMAP4_CHRGVBUS_SHIFT 7 -#define OMAP4_CHRGVBUS_MASK (1 << 7) -#define OMAP4_DRVVBUS_SHIFT 6 -#define OMAP4_DRVVBUS_MASK (1 << 6) -#define OMAP4_IDPULLUP_SHIFT 5 -#define OMAP4_IDPULLUP_MASK (1 << 5) -#define OMAP4_IDDIG_SHIFT 4 -#define OMAP4_IDDIG_MASK (1 << 4) -#define OMAP4_SESSEND_SHIFT 3 -#define OMAP4_SESSEND_MASK (1 << 3) -#define OMAP4_VBUSVALID_SHIFT 2 -#define OMAP4_VBUSVALID_MASK (1 << 2) -#define OMAP4_BVALID_SHIFT 1 -#define OMAP4_BVALID_MASK (1 << 1) -#define OMAP4_AVALID_SHIFT 0 -#define OMAP4_AVALID_MASK (1 << 0) - -/* DSS_CONTROL */ -#define OMAP4_DSS_MUX6_SELECT_SHIFT 0 -#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0) - -/* HWOBS_CONTROL */ -#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3 -#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3) -#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2 -#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2) -#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1 -#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1) -#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0 -#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0) - -/* DEBOBS_FINAL_MUX_SEL */ -#define OMAP4_SELECT_SHIFT 0 -#define OMAP4_SELECT_MASK (0xffffffff << 0) - -/* DEBOBS_MMR_MPU */ -#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0 -#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0) - -/* CONF_SDMA_REQ_SEL0 */ -#define OMAP4_MULT_SHIFT 0 -#define OMAP4_MULT_MASK (0x7f << 0) - -/* CONF_CLK_SEL0 */ -#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0 -#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0) - -/* CONF_CLK_SEL1 */ -#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0 -#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0) - -/* CONF_CLK_SEL2 */ -#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0 -#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0) - -/* CONF_DPLL_FREQLOCK_SEL */ -#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0 -#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0) - -/* CONF_DPLL_TINITZ_SEL */ -#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0 -#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0) - -/* CONF_DPLL_PHASELOCK_SEL */ -#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0 -#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0) - -/* CONF_DEBUG_SEL_TST_0 */ -#define OMAP4_MODE_SHIFT 0 -#define OMAP4_MODE_MASK (0xf << 0) - -#endif diff --git a/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h deleted file mode 100644 index c88420de1151..000000000000 --- a/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h +++ /dev/null @@ -1,1409 +0,0 @@ -/* - * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * - * Benoit Cousson (b-cousson@ti.com) - * Santosh Shilimkar (santosh.shilimkar@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H - - -/* Base address */ -#define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000 - -/* Registers offset */ -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000 -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004 -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010 -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8 -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0 -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4 -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8 -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660 -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664 -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c - -/* Registers shifts and masks */ - -/* IP_REVISION */ -#define OMAP4_IP_REV_SCHEME_SHIFT 30 -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) -#define OMAP4_IP_REV_FUNC_SHIFT 16 -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) -#define OMAP4_IP_REV_RTL_SHIFT 11 -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) -#define OMAP4_IP_REV_MAJOR_SHIFT 8 -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) -#define OMAP4_IP_REV_CUSTOM_SHIFT 6 -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) -#define OMAP4_IP_REV_MINOR_SHIFT 0 -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) - -/* IP_HWINFO */ -#define OMAP4_IP_HWINFO_SHIFT 0 -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) - -/* IP_SYSCONFIG */ -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) - -/* PADCONF_WAKEUPEVENT_0 */ -#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_1 */ -#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_2 */ -#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_3 */ -#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_4 */ -#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_5 */ -#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_6 */ -#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* CONTROL_PADCONF_GLOBAL */ -#define OMAP4_FORCE_OFFMODE_EN_SHIFT 31 -#define OMAP4_FORCE_OFFMODE_EN_MASK (1 << 31) - -/* CONTROL_PADCONF_MODE */ -#define OMAP4_VDDS_DV_BANK0_SHIFT 31 -#define OMAP4_VDDS_DV_BANK0_MASK (1 << 31) -#define OMAP4_VDDS_DV_BANK1_SHIFT 30 -#define OMAP4_VDDS_DV_BANK1_MASK (1 << 30) -#define OMAP4_VDDS_DV_BANK3_SHIFT 29 -#define OMAP4_VDDS_DV_BANK3_MASK (1 << 29) -#define OMAP4_VDDS_DV_BANK4_SHIFT 28 -#define OMAP4_VDDS_DV_BANK4_MASK (1 << 28) -#define OMAP4_VDDS_DV_BANK5_SHIFT 27 -#define OMAP4_VDDS_DV_BANK5_MASK (1 << 27) -#define OMAP4_VDDS_DV_BANK6_SHIFT 26 -#define OMAP4_VDDS_DV_BANK6_MASK (1 << 26) -#define OMAP4_VDDS_DV_C2C_SHIFT 25 -#define OMAP4_VDDS_DV_C2C_MASK (1 << 25) -#define OMAP4_VDDS_DV_CAM_SHIFT 24 -#define OMAP4_VDDS_DV_CAM_MASK (1 << 24) -#define OMAP4_VDDS_DV_GPMC_SHIFT 23 -#define OMAP4_VDDS_DV_GPMC_MASK (1 << 23) -#define OMAP4_VDDS_DV_SDMMC2_SHIFT 22 -#define OMAP4_VDDS_DV_SDMMC2_MASK (1 << 22) - -/* CONTROL_SMART1IO_PADCONF_0 */ -#define OMAP4_ABE_DR0_SC_SHIFT 30 -#define OMAP4_ABE_DR0_SC_MASK (0x3 << 30) -#define OMAP4_CAM_DR0_SC_SHIFT 28 -#define OMAP4_CAM_DR0_SC_MASK (0x3 << 28) -#define OMAP4_FREF_DR2_SC_SHIFT 26 -#define OMAP4_FREF_DR2_SC_MASK (0x3 << 26) -#define OMAP4_FREF_DR3_SC_SHIFT 24 -#define OMAP4_FREF_DR3_SC_MASK (0x3 << 24) -#define OMAP4_GPIO_DR8_SC_SHIFT 22 -#define OMAP4_GPIO_DR8_SC_MASK (0x3 << 22) -#define OMAP4_GPIO_DR9_SC_SHIFT 20 -#define OMAP4_GPIO_DR9_SC_MASK (0x3 << 20) -#define OMAP4_GPMC_DR2_SC_SHIFT 18 -#define OMAP4_GPMC_DR2_SC_MASK (0x3 << 18) -#define OMAP4_GPMC_DR3_SC_SHIFT 16 -#define OMAP4_GPMC_DR3_SC_MASK (0x3 << 16) -#define OMAP4_GPMC_DR6_SC_SHIFT 14 -#define OMAP4_GPMC_DR6_SC_MASK (0x3 << 14) -#define OMAP4_HDMI_DR0_SC_SHIFT 12 -#define OMAP4_HDMI_DR0_SC_MASK (0x3 << 12) -#define OMAP4_MCSPI1_DR0_SC_SHIFT 10 -#define OMAP4_MCSPI1_DR0_SC_MASK (0x3 << 10) -#define OMAP4_UART1_DR0_SC_SHIFT 8 -#define OMAP4_UART1_DR0_SC_MASK (0x3 << 8) -#define OMAP4_UART3_DR0_SC_SHIFT 6 -#define OMAP4_UART3_DR0_SC_MASK (0x3 << 6) -#define OMAP4_UART3_DR1_SC_SHIFT 4 -#define OMAP4_UART3_DR1_SC_MASK (0x3 << 4) -#define OMAP4_UNIPRO_DR0_SC_SHIFT 2 -#define OMAP4_UNIPRO_DR0_SC_MASK (0x3 << 2) -#define OMAP4_UNIPRO_DR1_SC_SHIFT 0 -#define OMAP4_UNIPRO_DR1_SC_MASK (0x3 << 0) - -/* CONTROL_SMART1IO_PADCONF_1 */ -#define OMAP4_ABE_DR0_LB_SHIFT 30 -#define OMAP4_ABE_DR0_LB_MASK (0x3 << 30) -#define OMAP4_CAM_DR0_LB_SHIFT 28 -#define OMAP4_CAM_DR0_LB_MASK (0x3 << 28) -#define OMAP4_FREF_DR2_LB_SHIFT 26 -#define OMAP4_FREF_DR2_LB_MASK (0x3 << 26) -#define OMAP4_FREF_DR3_LB_SHIFT 24 -#define OMAP4_FREF_DR3_LB_MASK (0x3 << 24) -#define OMAP4_GPIO_DR8_LB_SHIFT 22 -#define OMAP4_GPIO_DR8_LB_MASK (0x3 << 22) -#define OMAP4_GPIO_DR9_LB_SHIFT 20 -#define OMAP4_GPIO_DR9_LB_MASK (0x3 << 20) -#define OMAP4_GPMC_DR2_LB_SHIFT 18 -#define OMAP4_GPMC_DR2_LB_MASK (0x3 << 18) -#define OMAP4_GPMC_DR3_LB_SHIFT 16 -#define OMAP4_GPMC_DR3_LB_MASK (0x3 << 16) -#define OMAP4_GPMC_DR6_LB_SHIFT 14 -#define OMAP4_GPMC_DR6_LB_MASK (0x3 << 14) -#define OMAP4_HDMI_DR0_LB_SHIFT 12 -#define OMAP4_HDMI_DR0_LB_MASK (0x3 << 12) -#define OMAP4_MCSPI1_DR0_LB_SHIFT 10 -#define OMAP4_MCSPI1_DR0_LB_MASK (0x3 << 10) -#define OMAP4_UART1_DR0_LB_SHIFT 8 -#define OMAP4_UART1_DR0_LB_MASK (0x3 << 8) -#define OMAP4_UART3_DR0_LB_SHIFT 6 -#define OMAP4_UART3_DR0_LB_MASK (0x3 << 6) -#define OMAP4_UART3_DR1_LB_SHIFT 4 -#define OMAP4_UART3_DR1_LB_MASK (0x3 << 4) -#define OMAP4_UNIPRO_DR0_LB_SHIFT 2 -#define OMAP4_UNIPRO_DR0_LB_MASK (0x3 << 2) -#define OMAP4_UNIPRO_DR1_LB_SHIFT 0 -#define OMAP4_UNIPRO_DR1_LB_MASK (0x3 << 0) - -/* CONTROL_SMART2IO_PADCONF_0 */ -#define OMAP4_C2C_DR0_LB_SHIFT 31 -#define OMAP4_C2C_DR0_LB_MASK (1 << 31) -#define OMAP4_DPM_DR1_LB_SHIFT 30 -#define OMAP4_DPM_DR1_LB_MASK (1 << 30) -#define OMAP4_DPM_DR2_LB_SHIFT 29 -#define OMAP4_DPM_DR2_LB_MASK (1 << 29) -#define OMAP4_DPM_DR3_LB_SHIFT 28 -#define OMAP4_DPM_DR3_LB_MASK (1 << 28) -#define OMAP4_GPIO_DR0_LB_SHIFT 27 -#define OMAP4_GPIO_DR0_LB_MASK (1 << 27) -#define OMAP4_GPIO_DR1_LB_SHIFT 26 -#define OMAP4_GPIO_DR1_LB_MASK (1 << 26) -#define OMAP4_GPIO_DR10_LB_SHIFT 25 -#define OMAP4_GPIO_DR10_LB_MASK (1 << 25) -#define OMAP4_GPIO_DR2_LB_SHIFT 24 -#define OMAP4_GPIO_DR2_LB_MASK (1 << 24) -#define OMAP4_GPMC_DR0_LB_SHIFT 23 -#define OMAP4_GPMC_DR0_LB_MASK (1 << 23) -#define OMAP4_GPMC_DR1_LB_SHIFT 22 -#define OMAP4_GPMC_DR1_LB_MASK (1 << 22) -#define OMAP4_GPMC_DR4_LB_SHIFT 21 -#define OMAP4_GPMC_DR4_LB_MASK (1 << 21) -#define OMAP4_GPMC_DR5_LB_SHIFT 20 -#define OMAP4_GPMC_DR5_LB_MASK (1 << 20) -#define OMAP4_GPMC_DR7_LB_SHIFT 19 -#define OMAP4_GPMC_DR7_LB_MASK (1 << 19) -#define OMAP4_HSI2_DR0_LB_SHIFT 18 -#define OMAP4_HSI2_DR0_LB_MASK (1 << 18) -#define OMAP4_HSI2_DR1_LB_SHIFT 17 -#define OMAP4_HSI2_DR1_LB_MASK (1 << 17) -#define OMAP4_HSI2_DR2_LB_SHIFT 16 -#define OMAP4_HSI2_DR2_LB_MASK (1 << 16) -#define OMAP4_KPD_DR0_LB_SHIFT 15 -#define OMAP4_KPD_DR0_LB_MASK (1 << 15) -#define OMAP4_KPD_DR1_LB_SHIFT 14 -#define OMAP4_KPD_DR1_LB_MASK (1 << 14) -#define OMAP4_PDM_DR0_LB_SHIFT 13 -#define OMAP4_PDM_DR0_LB_MASK (1 << 13) -#define OMAP4_SDMMC2_DR0_LB_SHIFT 12 -#define OMAP4_SDMMC2_DR0_LB_MASK (1 << 12) -#define OMAP4_SDMMC3_DR0_LB_SHIFT 11 -#define OMAP4_SDMMC3_DR0_LB_MASK (1 << 11) -#define OMAP4_SDMMC4_DR0_LB_SHIFT 10 -#define OMAP4_SDMMC4_DR0_LB_MASK (1 << 10) -#define OMAP4_SDMMC4_DR1_LB_SHIFT 9 -#define OMAP4_SDMMC4_DR1_LB_MASK (1 << 9) -#define OMAP4_SPI3_DR0_LB_SHIFT 8 -#define OMAP4_SPI3_DR0_LB_MASK (1 << 8) -#define OMAP4_SPI3_DR1_LB_SHIFT 7 -#define OMAP4_SPI3_DR1_LB_MASK (1 << 7) -#define OMAP4_UART3_DR2_LB_SHIFT 6 -#define OMAP4_UART3_DR2_LB_MASK (1 << 6) -#define OMAP4_UART3_DR3_LB_SHIFT 5 -#define OMAP4_UART3_DR3_LB_MASK (1 << 5) -#define OMAP4_UART3_DR4_LB_SHIFT 4 -#define OMAP4_UART3_DR4_LB_MASK (1 << 4) -#define OMAP4_UART3_DR5_LB_SHIFT 3 -#define OMAP4_UART3_DR5_LB_MASK (1 << 3) -#define OMAP4_USBA0_DR1_LB_SHIFT 2 -#define OMAP4_USBA0_DR1_LB_MASK (1 << 2) -#define OMAP4_USBA_DR2_LB_SHIFT 1 -#define OMAP4_USBA_DR2_LB_MASK (1 << 1) - -/* CONTROL_SMART2IO_PADCONF_1 */ -#define OMAP4_USBB1_DR0_LB_SHIFT 31 -#define OMAP4_USBB1_DR0_LB_MASK (1 << 31) -#define OMAP4_USBB2_DR0_LB_SHIFT 30 -#define OMAP4_USBB2_DR0_LB_MASK (1 << 30) -#define OMAP4_USBA0_DR0_LB_SHIFT 29 -#define OMAP4_USBA0_DR0_LB_MASK (1 << 29) - -/* CONTROL_SMART3IO_PADCONF_0 */ -#define OMAP4_DMIC_DR0_MB_SHIFT 30 -#define OMAP4_DMIC_DR0_MB_MASK (0x3 << 30) -#define OMAP4_GPIO_DR3_MB_SHIFT 28 -#define OMAP4_GPIO_DR3_MB_MASK (0x3 << 28) -#define OMAP4_GPIO_DR4_MB_SHIFT 26 -#define OMAP4_GPIO_DR4_MB_MASK (0x3 << 26) -#define OMAP4_GPIO_DR5_MB_SHIFT 24 -#define OMAP4_GPIO_DR5_MB_MASK (0x3 << 24) -#define OMAP4_GPIO_DR6_MB_SHIFT 22 -#define OMAP4_GPIO_DR6_MB_MASK (0x3 << 22) -#define OMAP4_HSI_DR1_MB_SHIFT 20 -#define OMAP4_HSI_DR1_MB_MASK (0x3 << 20) -#define OMAP4_HSI_DR2_MB_SHIFT 18 -#define OMAP4_HSI_DR2_MB_MASK (0x3 << 18) -#define OMAP4_HSI_DR3_MB_SHIFT 16 -#define OMAP4_HSI_DR3_MB_MASK (0x3 << 16) -#define OMAP4_MCBSP2_DR0_MB_SHIFT 14 -#define OMAP4_MCBSP2_DR0_MB_MASK (0x3 << 14) -#define OMAP4_MCSPI4_DR0_MB_SHIFT 12 -#define OMAP4_MCSPI4_DR0_MB_MASK (0x3 << 12) -#define OMAP4_MCSPI4_DR1_MB_SHIFT 10 -#define OMAP4_MCSPI4_DR1_MB_MASK (0x3 << 10) -#define OMAP4_SDMMC3_DR0_MB_SHIFT 8 -#define OMAP4_SDMMC3_DR0_MB_MASK (0x3 << 8) -#define OMAP4_SPI2_DR0_MB_SHIFT 0 -#define OMAP4_SPI2_DR0_MB_MASK (0x3 << 0) - -/* CONTROL_SMART3IO_PADCONF_1 */ -#define OMAP4_SPI2_DR1_MB_SHIFT 30 -#define OMAP4_SPI2_DR1_MB_MASK (0x3 << 30) -#define OMAP4_SPI2_DR2_MB_SHIFT 28 -#define OMAP4_SPI2_DR2_MB_MASK (0x3 << 28) -#define OMAP4_UART2_DR0_MB_SHIFT 26 -#define OMAP4_UART2_DR0_MB_MASK (0x3 << 26) -#define OMAP4_UART2_DR1_MB_SHIFT 24 -#define OMAP4_UART2_DR1_MB_MASK (0x3 << 24) -#define OMAP4_UART4_DR0_MB_SHIFT 22 -#define OMAP4_UART4_DR0_MB_MASK (0x3 << 22) -#define OMAP4_HSI_DR0_MB_SHIFT 20 -#define OMAP4_HSI_DR0_MB_MASK (0x3 << 20) - -/* CONTROL_SMART3IO_PADCONF_2 */ -#define OMAP4_DMIC_DR0_LB_SHIFT 31 -#define OMAP4_DMIC_DR0_LB_MASK (1 << 31) -#define OMAP4_GPIO_DR3_LB_SHIFT 30 -#define OMAP4_GPIO_DR3_LB_MASK (1 << 30) -#define OMAP4_GPIO_DR4_LB_SHIFT 29 -#define OMAP4_GPIO_DR4_LB_MASK (1 << 29) -#define OMAP4_GPIO_DR5_LB_SHIFT 28 -#define OMAP4_GPIO_DR5_LB_MASK (1 << 28) -#define OMAP4_GPIO_DR6_LB_SHIFT 27 -#define OMAP4_GPIO_DR6_LB_MASK (1 << 27) -#define OMAP4_HSI_DR1_LB_SHIFT 26 -#define OMAP4_HSI_DR1_LB_MASK (1 << 26) -#define OMAP4_HSI_DR2_LB_SHIFT 25 -#define OMAP4_HSI_DR2_LB_MASK (1 << 25) -#define OMAP4_HSI_DR3_LB_SHIFT 24 -#define OMAP4_HSI_DR3_LB_MASK (1 << 24) -#define OMAP4_MCBSP2_DR0_LB_SHIFT 23 -#define OMAP4_MCBSP2_DR0_LB_MASK (1 << 23) -#define OMAP4_MCSPI4_DR0_LB_SHIFT 22 -#define OMAP4_MCSPI4_DR0_LB_MASK (1 << 22) -#define OMAP4_MCSPI4_DR1_LB_SHIFT 21 -#define OMAP4_MCSPI4_DR1_LB_MASK (1 << 21) -#define OMAP4_SLIMBUS2_DR0_LB_SHIFT 18 -#define OMAP4_SLIMBUS2_DR0_LB_MASK (1 << 18) -#define OMAP4_SPI2_DR0_LB_SHIFT 16 -#define OMAP4_SPI2_DR0_LB_MASK (1 << 16) -#define OMAP4_SPI2_DR1_LB_SHIFT 15 -#define OMAP4_SPI2_DR1_LB_MASK (1 << 15) -#define OMAP4_SPI2_DR2_LB_SHIFT 14 -#define OMAP4_SPI2_DR2_LB_MASK (1 << 14) -#define OMAP4_UART2_DR0_LB_SHIFT 13 -#define OMAP4_UART2_DR0_LB_MASK (1 << 13) -#define OMAP4_UART2_DR1_LB_SHIFT 12 -#define OMAP4_UART2_DR1_LB_MASK (1 << 12) -#define OMAP4_UART4_DR0_LB_SHIFT 11 -#define OMAP4_UART4_DR0_LB_MASK (1 << 11) -#define OMAP4_HSI_DR0_LB_SHIFT 10 -#define OMAP4_HSI_DR0_LB_MASK (1 << 10) - -/* CONTROL_USBB_HSIC */ -#define OMAP4_USBB2_DR1_SR_SHIFT 30 -#define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30) -#define OMAP4_USBB2_DR1_I_SHIFT 27 -#define OMAP4_USBB2_DR1_I_MASK (0x7 << 27) -#define OMAP4_USBB1_DR1_SR_SHIFT 25 -#define OMAP4_USBB1_DR1_SR_MASK (0x3 << 25) -#define OMAP4_USBB1_DR1_I_SHIFT 22 -#define OMAP4_USBB1_DR1_I_MASK (0x7 << 22) -#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT 20 -#define OMAP4_USBB1_HSIC_DATA_WD_MASK (0x3 << 20) -#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT 18 -#define OMAP4_USBB1_HSIC_STROBE_WD_MASK (0x3 << 18) -#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT 16 -#define OMAP4_USBB2_HSIC_DATA_WD_MASK (0x3 << 16) -#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT 14 -#define OMAP4_USBB2_HSIC_STROBE_WD_MASK (0x3 << 14) -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 13 -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 13) -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT 11 -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 11) -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 10 -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 10) -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT 8 -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 8) -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 7 -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 7) -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT 5 -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 5) -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 4 -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 4) -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT 2 -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 2) - -/* CONTROL_SLIMBUS */ -#define OMAP4_SLIMBUS1_DR0_MB_SHIFT 30 -#define OMAP4_SLIMBUS1_DR0_MB_MASK (0x3 << 30) -#define OMAP4_SLIMBUS1_DR1_MB_SHIFT 28 -#define OMAP4_SLIMBUS1_DR1_MB_MASK (0x3 << 28) -#define OMAP4_SLIMBUS2_DR0_MB_SHIFT 26 -#define OMAP4_SLIMBUS2_DR0_MB_MASK (0x3 << 26) -#define OMAP4_SLIMBUS2_DR1_MB_SHIFT 24 -#define OMAP4_SLIMBUS2_DR1_MB_MASK (0x3 << 24) -#define OMAP4_SLIMBUS2_DR2_MB_SHIFT 22 -#define OMAP4_SLIMBUS2_DR2_MB_MASK (0x3 << 22) -#define OMAP4_SLIMBUS2_DR3_MB_SHIFT 20 -#define OMAP4_SLIMBUS2_DR3_MB_MASK (0x3 << 20) -#define OMAP4_SLIMBUS1_DR0_LB_SHIFT 19 -#define OMAP4_SLIMBUS1_DR0_LB_MASK (1 << 19) -#define OMAP4_SLIMBUS2_DR1_LB_SHIFT 18 -#define OMAP4_SLIMBUS2_DR1_LB_MASK (1 << 18) - -/* CONTROL_PBIASLITE */ -#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT 31 -#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK (1 << 31) -#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT 30 -#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 30) -#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT 29 -#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK (1 << 29) -#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT 28 -#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK (1 << 28) -#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT 27 -#define OMAP4_USIM_PBIASLITE_VMODE_MASK (1 << 27) -#define OMAP4_MMC1_PWRDNZ_SHIFT 26 -#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26) -#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT 25 -#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK (1 << 25) -#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT 24 -#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 24) -#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT 23 -#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23) -#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT 22 -#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22) -#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT 21 -#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21) -#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT 20 -#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK (1 << 20) - -/* CONTROL_I2C_0 */ -#define OMAP4_I2C4_SDA_GLFENB_SHIFT 31 -#define OMAP4_I2C4_SDA_GLFENB_MASK (1 << 31) -#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT 29 -#define OMAP4_I2C4_SDA_LOAD_BITS_MASK (0x3 << 29) -#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT 28 -#define OMAP4_I2C4_SDA_PULLUPRESX_MASK (1 << 28) -#define OMAP4_I2C3_SDA_GLFENB_SHIFT 27 -#define OMAP4_I2C3_SDA_GLFENB_MASK (1 << 27) -#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT 25 -#define OMAP4_I2C3_SDA_LOAD_BITS_MASK (0x3 << 25) -#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT 24 -#define OMAP4_I2C3_SDA_PULLUPRESX_MASK (1 << 24) -#define OMAP4_I2C2_SDA_GLFENB_SHIFT 23 -#define OMAP4_I2C2_SDA_GLFENB_MASK (1 << 23) -#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT 21 -#define OMAP4_I2C2_SDA_LOAD_BITS_MASK (0x3 << 21) -#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT 20 -#define OMAP4_I2C2_SDA_PULLUPRESX_MASK (1 << 20) -#define OMAP4_I2C1_SDA_GLFENB_SHIFT 19 -#define OMAP4_I2C1_SDA_GLFENB_MASK (1 << 19) -#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT 17 -#define OMAP4_I2C1_SDA_LOAD_BITS_MASK (0x3 << 17) -#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT 16 -#define OMAP4_I2C1_SDA_PULLUPRESX_MASK (1 << 16) -#define OMAP4_I2C4_SCL_GLFENB_SHIFT 15 -#define OMAP4_I2C4_SCL_GLFENB_MASK (1 << 15) -#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT 13 -#define OMAP4_I2C4_SCL_LOAD_BITS_MASK (0x3 << 13) -#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT 12 -#define OMAP4_I2C4_SCL_PULLUPRESX_MASK (1 << 12) -#define OMAP4_I2C3_SCL_GLFENB_SHIFT 11 -#define OMAP4_I2C3_SCL_GLFENB_MASK (1 << 11) -#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT 9 -#define OMAP4_I2C3_SCL_LOAD_BITS_MASK (0x3 << 9) -#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT 8 -#define OMAP4_I2C3_SCL_PULLUPRESX_MASK (1 << 8) -#define OMAP4_I2C2_SCL_GLFENB_SHIFT 7 -#define OMAP4_I2C2_SCL_GLFENB_MASK (1 << 7) -#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT 5 -#define OMAP4_I2C2_SCL_LOAD_BITS_MASK (0x3 << 5) -#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT 4 -#define OMAP4_I2C2_SCL_PULLUPRESX_MASK (1 << 4) -#define OMAP4_I2C1_SCL_GLFENB_SHIFT 3 -#define OMAP4_I2C1_SCL_GLFENB_MASK (1 << 3) -#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT 1 -#define OMAP4_I2C1_SCL_LOAD_BITS_MASK (0x3 << 1) -#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT 0 -#define OMAP4_I2C1_SCL_PULLUPRESX_MASK (1 << 0) - -/* CONTROL_CAMERA_RX */ -#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT 31 -#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK (1 << 31) -#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29 -#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29) -#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24 -#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24) -#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT 22 -#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK (0x3 << 22) -#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21 -#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21) -#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19 -#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19) -#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18 -#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18) -#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16 -#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16) - -/* CONTROL_AVDAC */ -#define OMAP4_AVDAC_ACEN_SHIFT 31 -#define OMAP4_AVDAC_ACEN_MASK (1 << 31) -#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT 30 -#define OMAP4_AVDAC_TVOUTBYPASS_MASK (1 << 30) -#define OMAP4_AVDAC_INPUTINV_SHIFT 29 -#define OMAP4_AVDAC_INPUTINV_MASK (1 << 29) -#define OMAP4_AVDAC_CTL_SHIFT 13 -#define OMAP4_AVDAC_CTL_MASK (0xffff << 13) -#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT 12 -#define OMAP4_AVDAC_CTL_WR_ACK_MASK (1 << 12) - -/* CONTROL_HDMI_TX_PHY */ -#define OMAP4_HDMITXPHY_PADORDER_SHIFT 31 -#define OMAP4_HDMITXPHY_PADORDER_MASK (1 << 31) -#define OMAP4_HDMITXPHY_TXVALID_SHIFT 30 -#define OMAP4_HDMITXPHY_TXVALID_MASK (1 << 30) -#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT 29 -#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK (1 << 29) -#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT 28 -#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK (1 << 28) - -/* CONTROL_MMC2 */ -#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT 31 -#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK (1 << 31) - -/* CONTROL_DSIPHY */ -#define OMAP4_DSI2_LANEENABLE_SHIFT 29 -#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) -#define OMAP4_DSI1_LANEENABLE_SHIFT 24 -#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) -#define OMAP4_DSI1_PIPD_SHIFT 19 -#define OMAP4_DSI1_PIPD_MASK (0x1f << 19) -#define OMAP4_DSI2_PIPD_SHIFT 14 -#define OMAP4_DSI2_PIPD_MASK (0x1f << 14) - -/* CONTROL_MCBSPLP */ -#define OMAP4_ALBCTRLRX_FSX_SHIFT 31 -#define OMAP4_ALBCTRLRX_FSX_MASK (1 << 31) -#define OMAP4_ALBCTRLRX_CLKX_SHIFT 30 -#define OMAP4_ALBCTRLRX_CLKX_MASK (1 << 30) -#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT 29 -#define OMAP4_ABE_MCBSP1_DR_EN_MASK (1 << 29) - -/* CONTROL_USB2PHYCORE */ -#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT 31 -#define OMAP4_USB2PHY_AUTORESUME_EN_MASK (1 << 31) -#define OMAP4_USB2PHY_DISCHGDET_SHIFT 30 -#define OMAP4_USB2PHY_DISCHGDET_MASK (1 << 30) -#define OMAP4_USB2PHY_GPIOMODE_SHIFT 29 -#define OMAP4_USB2PHY_GPIOMODE_MASK (1 << 29) -#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT 28 -#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK (1 << 28) -#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT 27 -#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK (1 << 27) -#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT 26 -#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK (1 << 26) -#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT 25 -#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK (1 << 25) -#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT 24 -#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK (1 << 24) -#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT 21 -#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK (0x7 << 21) -#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT 20 -#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK (1 << 20) -#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT 19 -#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK (1 << 19) -#define OMAP4_USB2PHY_DATADET_SHIFT 18 -#define OMAP4_USB2PHY_DATADET_MASK (1 << 18) -#define OMAP4_USB2PHY_SINKONDP_SHIFT 17 -#define OMAP4_USB2PHY_SINKONDP_MASK (1 << 17) -#define OMAP4_USB2PHY_SRCONDM_SHIFT 16 -#define OMAP4_USB2PHY_SRCONDM_MASK (1 << 16) -#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT 15 -#define OMAP4_USB2PHY_RESTARTCHGDET_MASK (1 << 15) -#define OMAP4_USB2PHY_CHGDETDONE_SHIFT 14 -#define OMAP4_USB2PHY_CHGDETDONE_MASK (1 << 14) -#define OMAP4_USB2PHY_CHGDETECTED_SHIFT 13 -#define OMAP4_USB2PHY_CHGDETECTED_MASK (1 << 13) -#define OMAP4_USB2PHY_MCPCPUEN_SHIFT 12 -#define OMAP4_USB2PHY_MCPCPUEN_MASK (1 << 12) -#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT 11 -#define OMAP4_USB2PHY_MCPCMODEEN_MASK (1 << 11) -#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT 10 -#define OMAP4_USB2PHY_RESETDONEMCLK_MASK (1 << 10) -#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT 9 -#define OMAP4_USB2PHY_UTMIRESETDONE_MASK (1 << 9) -#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT 8 -#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK (1 << 8) -#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT 7 -#define OMAP4_USB2PHY_DATAPOLARITYN_MASK (1 << 7) -#define OMAP4_USBDPLL_FREQLOCK_SHIFT 6 -#define OMAP4_USBDPLL_FREQLOCK_MASK (1 << 6) -#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT 5 -#define OMAP4_USB2PHY_RESETDONETCLK_MASK (1 << 5) - -/* CONTROL_I2C_1 */ -#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT 31 -#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK (1 << 31) -#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT 29 -#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK (0x3 << 29) -#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT 28 -#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28) -#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT 27 -#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK (1 << 27) -#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT 25 -#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK (0x3 << 25) -#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT 24 -#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24) -#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT 23 -#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK (1 << 23) -#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT 22 -#define OMAP4_HDMI_DDC_SDA_NMODE_MASK (1 << 22) -#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT 21 -#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK (1 << 21) -#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT 20 -#define OMAP4_HDMI_DDC_SCL_NMODE_MASK (1 << 20) - -/* CONTROL_MMC1 */ -#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT 31 -#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31) -#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT 30 -#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30) -#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT 29 -#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29) -#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT 28 -#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28) -#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT 27 -#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27) -#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT 26 -#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26) -#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT 25 -#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25) -#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT 24 -#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK (1 << 24) -#define OMAP4_USB_FD_CDEN_SHIFT 23 -#define OMAP4_USB_FD_CDEN_MASK (1 << 23) -#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT 22 -#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK (1 << 22) -#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT 21 -#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK (1 << 21) - -/* CONTROL_HSI */ -#define OMAP4_HSI1_CALLOOP_SEL_SHIFT 31 -#define OMAP4_HSI1_CALLOOP_SEL_MASK (1 << 31) -#define OMAP4_HSI1_CALMUX_SEL_SHIFT 30 -#define OMAP4_HSI1_CALMUX_SEL_MASK (1 << 30) -#define OMAP4_HSI2_CALLOOP_SEL_SHIFT 29 -#define OMAP4_HSI2_CALLOOP_SEL_MASK (1 << 29) -#define OMAP4_HSI2_CALMUX_SEL_SHIFT 28 -#define OMAP4_HSI2_CALMUX_SEL_MASK (1 << 28) - -/* CONTROL_USB */ -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT 31 -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK (1 << 31) -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT 30 -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK (1 << 30) - -/* CONTROL_HDQ */ -#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT 31 -#define OMAP4_HDQ_SIO_PWRDNZ_MASK (1 << 31) - -/* CONTROL_LPDDR2IO1_0 */ -#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT 30 -#define OMAP4_LPDDR2IO1_GR4_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO1_GR4_I_SHIFT 27 -#define OMAP4_LPDDR2IO1_GR4_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT 25 -#define OMAP4_LPDDR2IO1_GR4_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT 22 -#define OMAP4_LPDDR2IO1_GR3_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO1_GR3_I_SHIFT 19 -#define OMAP4_LPDDR2IO1_GR3_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT 17 -#define OMAP4_LPDDR2IO1_GR3_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT 14 -#define OMAP4_LPDDR2IO1_GR2_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO1_GR2_I_SHIFT 11 -#define OMAP4_LPDDR2IO1_GR2_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT 9 -#define OMAP4_LPDDR2IO1_GR2_WD_MASK (0x3 << 9) -#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT 6 -#define OMAP4_LPDDR2IO1_GR1_SR_MASK (0x3 << 6) -#define OMAP4_LPDDR2IO1_GR1_I_SHIFT 3 -#define OMAP4_LPDDR2IO1_GR1_I_MASK (0x7 << 3) -#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT 1 -#define OMAP4_LPDDR2IO1_GR1_WD_MASK (0x3 << 1) - -/* CONTROL_LPDDR2IO1_1 */ -#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT 30 -#define OMAP4_LPDDR2IO1_GR8_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO1_GR8_I_SHIFT 27 -#define OMAP4_LPDDR2IO1_GR8_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT 25 -#define OMAP4_LPDDR2IO1_GR8_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT 22 -#define OMAP4_LPDDR2IO1_GR7_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO1_GR7_I_SHIFT 19 -#define OMAP4_LPDDR2IO1_GR7_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT 17 -#define OMAP4_LPDDR2IO1_GR7_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT 14 -#define OMAP4_LPDDR2IO1_GR6_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO1_GR6_I_SHIFT 11 -#define OMAP4_LPDDR2IO1_GR6_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT 9 -#define OMAP4_LPDDR2IO1_GR6_WD_MASK (0x3 << 9) -#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT 6 -#define OMAP4_LPDDR2IO1_GR5_SR_MASK (0x3 << 6) -#define OMAP4_LPDDR2IO1_GR5_I_SHIFT 3 -#define OMAP4_LPDDR2IO1_GR5_I_MASK (0x7 << 3) -#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT 1 -#define OMAP4_LPDDR2IO1_GR5_WD_MASK (0x3 << 1) - -/* CONTROL_LPDDR2IO1_2 */ -#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT 30 -#define OMAP4_LPDDR2IO1_GR11_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO1_GR11_I_SHIFT 27 -#define OMAP4_LPDDR2IO1_GR11_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT 25 -#define OMAP4_LPDDR2IO1_GR11_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT 22 -#define OMAP4_LPDDR2IO1_GR10_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO1_GR10_I_SHIFT 19 -#define OMAP4_LPDDR2IO1_GR10_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT 17 -#define OMAP4_LPDDR2IO1_GR10_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT 14 -#define OMAP4_LPDDR2IO1_GR9_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO1_GR9_I_SHIFT 11 -#define OMAP4_LPDDR2IO1_GR9_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT 9 -#define OMAP4_LPDDR2IO1_GR9_WD_MASK (0x3 << 9) - -/* CONTROL_LPDDR2IO1_3 */ -#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT 31 -#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK (1 << 31) -#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT 30 -#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK (1 << 30) -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT 29 -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK (1 << 29) -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT 28 -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK (1 << 28) -#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT 27 -#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK (1 << 27) -#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT 26 -#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK (1 << 26) -#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT 25 -#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK (1 << 25) -#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT 24 -#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK (1 << 24) -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT 23 -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK (1 << 23) -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT 22 -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK (1 << 22) -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT 21 -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK (1 << 21) -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT 20 -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK (1 << 20) -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT 19 -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK (1 << 19) -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT 18 -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK (1 << 18) -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT 17 -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK (1 << 17) -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT 16 -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK (1 << 16) -#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT 15 -#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK (1 << 15) -#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT 14 -#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK (1 << 14) -#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT 13 -#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13) -#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12 -#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12) - -/* CONTROL_LPDDR2IO2_0 */ -#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30 -#define OMAP4_LPDDR2IO2_GR4_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO2_GR4_I_SHIFT 27 -#define OMAP4_LPDDR2IO2_GR4_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT 25 -#define OMAP4_LPDDR2IO2_GR4_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT 22 -#define OMAP4_LPDDR2IO2_GR3_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO2_GR3_I_SHIFT 19 -#define OMAP4_LPDDR2IO2_GR3_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT 17 -#define OMAP4_LPDDR2IO2_GR3_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT 14 -#define OMAP4_LPDDR2IO2_GR2_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO2_GR2_I_SHIFT 11 -#define OMAP4_LPDDR2IO2_GR2_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT 9 -#define OMAP4_LPDDR2IO2_GR2_WD_MASK (0x3 << 9) -#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT 6 -#define OMAP4_LPDDR2IO2_GR1_SR_MASK (0x3 << 6) -#define OMAP4_LPDDR2IO2_GR1_I_SHIFT 3 -#define OMAP4_LPDDR2IO2_GR1_I_MASK (0x7 << 3) -#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT 1 -#define OMAP4_LPDDR2IO2_GR1_WD_MASK (0x3 << 1) - -/* CONTROL_LPDDR2IO2_1 */ -#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT 30 -#define OMAP4_LPDDR2IO2_GR8_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO2_GR8_I_SHIFT 27 -#define OMAP4_LPDDR2IO2_GR8_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT 25 -#define OMAP4_LPDDR2IO2_GR8_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT 22 -#define OMAP4_LPDDR2IO2_GR7_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO2_GR7_I_SHIFT 19 -#define OMAP4_LPDDR2IO2_GR7_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT 17 -#define OMAP4_LPDDR2IO2_GR7_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT 14 -#define OMAP4_LPDDR2IO2_GR6_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO2_GR6_I_SHIFT 11 -#define OMAP4_LPDDR2IO2_GR6_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT 9 -#define OMAP4_LPDDR2IO2_GR6_WD_MASK (0x3 << 9) -#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT 6 -#define OMAP4_LPDDR2IO2_GR5_SR_MASK (0x3 << 6) -#define OMAP4_LPDDR2IO2_GR5_I_SHIFT 3 -#define OMAP4_LPDDR2IO2_GR5_I_MASK (0x7 << 3) -#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT 1 -#define OMAP4_LPDDR2IO2_GR5_WD_MASK (0x3 << 1) - -/* CONTROL_LPDDR2IO2_2 */ -#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT 30 -#define OMAP4_LPDDR2IO2_GR11_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO2_GR11_I_SHIFT 27 -#define OMAP4_LPDDR2IO2_GR11_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT 25 -#define OMAP4_LPDDR2IO2_GR11_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT 22 -#define OMAP4_LPDDR2IO2_GR10_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO2_GR10_I_SHIFT 19 -#define OMAP4_LPDDR2IO2_GR10_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT 17 -#define OMAP4_LPDDR2IO2_GR10_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT 14 -#define OMAP4_LPDDR2IO2_GR9_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO2_GR9_I_SHIFT 11 -#define OMAP4_LPDDR2IO2_GR9_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT 9 -#define OMAP4_LPDDR2IO2_GR9_WD_MASK (0x3 << 9) - -/* CONTROL_LPDDR2IO2_3 */ -#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT 31 -#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK (1 << 31) -#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT 30 -#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK (1 << 30) -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT 29 -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK (1 << 29) -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT 28 -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK (1 << 28) -#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT 27 -#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK (1 << 27) -#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT 26 -#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK (1 << 26) -#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT 25 -#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK (1 << 25) -#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT 24 -#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK (1 << 24) -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT 23 -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK (1 << 23) -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT 22 -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK (1 << 22) -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT 21 -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK (1 << 21) -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT 20 -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK (1 << 20) -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT 19 -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK (1 << 19) -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT 18 -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK (1 << 18) -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT 17 -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK (1 << 17) -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT 16 -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK (1 << 16) -#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT 15 -#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK (1 << 15) -#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT 14 -#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK (1 << 14) -#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT 13 -#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK (1 << 13) -#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT 12 -#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK (1 << 12) - -/* CONTROL_BUS_HOLD */ -#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT 31 -#define OMAP4_ABE_DMIC_DIN3_EN_MASK (1 << 31) -#define OMAP4_MCSPI1_CS3_EN_SHIFT 30 -#define OMAP4_MCSPI1_CS3_EN_MASK (1 << 30) - -/* CONTROL_C2C */ -#define OMAP4_MIRROR_MODE_EN_SHIFT 31 -#define OMAP4_MIRROR_MODE_EN_MASK (1 << 31) -#define OMAP4_C2C_SPARE_SHIFT 24 -#define OMAP4_C2C_SPARE_MASK (0x7f << 24) - -/* CORE_CONTROL_SPARE_RW */ -#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT 0 -#define OMAP4_CORE_CONTROL_SPARE_RW_MASK (0xffffffff << 0) - -/* CORE_CONTROL_SPARE_R */ -#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT 0 -#define OMAP4_CORE_CONTROL_SPARE_R_MASK (0xffffffff << 0) - -/* CORE_CONTROL_SPARE_R_C0 */ -#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT 31 -#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK (1 << 31) -#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT 30 -#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK (1 << 30) -#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT 29 -#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK (1 << 29) -#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT 28 -#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK (1 << 28) -#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT 27 -#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK (1 << 27) -#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT 26 -#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK (1 << 26) -#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT 25 -#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK (1 << 25) -#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT 24 -#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK (1 << 24) - -/* CONTROL_EFUSE_1 */ -#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT 24 -#define OMAP4_AVDAC_TRIM_BYTE3_MASK (0x7f << 24) -#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT 16 -#define OMAP4_AVDAC_TRIM_BYTE2_MASK (0xff << 16) -#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT 8 -#define OMAP4_AVDAC_TRIM_BYTE1_MASK (0xff << 8) -#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT 0 -#define OMAP4_AVDAC_TRIM_BYTE0_MASK (0xff << 0) - -/* CONTROL_EFUSE_2 */ -#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT 31 -#define OMAP4_EFUSE_SMART2TEST_P0_MASK (1 << 31) -#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT 30 -#define OMAP4_EFUSE_SMART2TEST_P1_MASK (1 << 30) -#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT 29 -#define OMAP4_EFUSE_SMART2TEST_P2_MASK (1 << 29) -#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT 28 -#define OMAP4_EFUSE_SMART2TEST_P3_MASK (1 << 28) -#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT 27 -#define OMAP4_EFUSE_SMART2TEST_N0_MASK (1 << 27) -#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT 26 -#define OMAP4_EFUSE_SMART2TEST_N1_MASK (1 << 26) -#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT 25 -#define OMAP4_EFUSE_SMART2TEST_N2_MASK (1 << 25) -#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT 24 -#define OMAP4_EFUSE_SMART2TEST_N3_MASK (1 << 24) -#define OMAP4_LPDDR2_PTV_N1_SHIFT 23 -#define OMAP4_LPDDR2_PTV_N1_MASK (1 << 23) -#define OMAP4_LPDDR2_PTV_N2_SHIFT 22 -#define OMAP4_LPDDR2_PTV_N2_MASK (1 << 22) -#define OMAP4_LPDDR2_PTV_N3_SHIFT 21 -#define OMAP4_LPDDR2_PTV_N3_MASK (1 << 21) -#define OMAP4_LPDDR2_PTV_N4_SHIFT 20 -#define OMAP4_LPDDR2_PTV_N4_MASK (1 << 20) -#define OMAP4_LPDDR2_PTV_N5_SHIFT 19 -#define OMAP4_LPDDR2_PTV_N5_MASK (1 << 19) -#define OMAP4_LPDDR2_PTV_P1_SHIFT 18 -#define OMAP4_LPDDR2_PTV_P1_MASK (1 << 18) -#define OMAP4_LPDDR2_PTV_P2_SHIFT 17 -#define OMAP4_LPDDR2_PTV_P2_MASK (1 << 17) -#define OMAP4_LPDDR2_PTV_P3_SHIFT 16 -#define OMAP4_LPDDR2_PTV_P3_MASK (1 << 16) -#define OMAP4_LPDDR2_PTV_P4_SHIFT 15 -#define OMAP4_LPDDR2_PTV_P4_MASK (1 << 15) -#define OMAP4_LPDDR2_PTV_P5_SHIFT 14 -#define OMAP4_LPDDR2_PTV_P5_MASK (1 << 14) - -/* CONTROL_EFUSE_3 */ -#define OMAP4_STD_FUSE_SPARE_1_SHIFT 24 -#define OMAP4_STD_FUSE_SPARE_1_MASK (0xff << 24) -#define OMAP4_STD_FUSE_SPARE_2_SHIFT 16 -#define OMAP4_STD_FUSE_SPARE_2_MASK (0xff << 16) -#define OMAP4_STD_FUSE_SPARE_3_SHIFT 8 -#define OMAP4_STD_FUSE_SPARE_3_MASK (0xff << 8) -#define OMAP4_STD_FUSE_SPARE_4_SHIFT 0 -#define OMAP4_STD_FUSE_SPARE_4_MASK (0xff << 0) - -/* CONTROL_EFUSE_4 */ -#define OMAP4_STD_FUSE_SPARE_5_SHIFT 24 -#define OMAP4_STD_FUSE_SPARE_5_MASK (0xff << 24) -#define OMAP4_STD_FUSE_SPARE_6_SHIFT 16 -#define OMAP4_STD_FUSE_SPARE_6_MASK (0xff << 16) -#define OMAP4_STD_FUSE_SPARE_7_SHIFT 8 -#define OMAP4_STD_FUSE_SPARE_7_MASK (0xff << 8) -#define OMAP4_STD_FUSE_SPARE_8_SHIFT 0 -#define OMAP4_STD_FUSE_SPARE_8_MASK (0xff << 0) - -#endif diff --git a/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h deleted file mode 100644 index 17c9b37042c0..000000000000 --- a/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * - * Benoit Cousson (b-cousson@ti.com) - * Santosh Shilimkar (santosh.shilimkar@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H - - -/* Base address */ -#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000 - -/* Registers offset */ -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000 -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004 -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010 -#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614 -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618 -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c - -/* Registers shifts and masks */ - -/* IP_REVISION */ -#define OMAP4_IP_REV_SCHEME_SHIFT 30 -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) -#define OMAP4_IP_REV_FUNC_SHIFT 16 -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) -#define OMAP4_IP_REV_RTL_SHIFT 11 -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) -#define OMAP4_IP_REV_MAJOR_SHIFT 8 -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) -#define OMAP4_IP_REV_CUSTOM_SHIFT 6 -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) -#define OMAP4_IP_REV_MINOR_SHIFT 0 -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) - -/* IP_HWINFO */ -#define OMAP4_IP_HWINFO_SHIFT 0 -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) - -/* IP_SYSCONFIG */ -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) - -/* PADCONF_WAKEUPEVENT_0 */ -#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* CONTROL_SMART1NOPMIO_PADCONF_0 */ -#define OMAP4_FREF_DR0_SC_SHIFT 30 -#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30) -#define OMAP4_FREF_DR1_SC_SHIFT 28 -#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28) -#define OMAP4_FREF_DR4_SC_SHIFT 26 -#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26) -#define OMAP4_FREF_DR5_SC_SHIFT 24 -#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24) -#define OMAP4_FREF_DR6_SC_SHIFT 22 -#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22) -#define OMAP4_FREF_DR7_SC_SHIFT 20 -#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20) -#define OMAP4_GPIO_DR7_SC_SHIFT 18 -#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18) -#define OMAP4_DPM_DR0_SC_SHIFT 14 -#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14) -#define OMAP4_SIM_DR0_SC_SHIFT 12 -#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12) - -/* CONTROL_SMART1NOPMIO_PADCONF_1 */ -#define OMAP4_FREF_DR0_LB_SHIFT 30 -#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30) -#define OMAP4_FREF_DR1_LB_SHIFT 28 -#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28) -#define OMAP4_FREF_DR4_LB_SHIFT 26 -#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26) -#define OMAP4_FREF_DR5_LB_SHIFT 24 -#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24) -#define OMAP4_FREF_DR6_LB_SHIFT 22 -#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22) -#define OMAP4_FREF_DR7_LB_SHIFT 20 -#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20) -#define OMAP4_GPIO_DR7_LB_SHIFT 18 -#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18) -#define OMAP4_DPM_DR0_LB_SHIFT 14 -#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14) -#define OMAP4_SIM_DR0_LB_SHIFT 12 -#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12) - -/* CONTROL_PADCONF_MODE */ -#define OMAP4_VDDS_DV_FREF_SHIFT 31 -#define OMAP4_VDDS_DV_FREF_MASK (1 << 31) -#define OMAP4_VDDS_DV_BANK2_SHIFT 30 -#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30) - -/* CONTROL_XTAL_OSCILLATOR */ -#define OMAP4_OSCILLATOR_BOOST_SHIFT 31 -#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31) -#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30 -#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30) - -/* CONTROL_USIMIO */ -#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31 -#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31) -#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29 -#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29) -#define OMAP4_USIM_PWRDNZ_SHIFT 28 -#define OMAP4_USIM_PWRDNZ_MASK (1 << 28) - -/* CONTROL_I2C_2 */ -#define OMAP4_SR_SDA_GLFENB_SHIFT 31 -#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31) -#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29 -#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29) -#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28 -#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28) -#define OMAP4_SR_SCL_GLFENB_SHIFT 27 -#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27) -#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25 -#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25) -#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24 -#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24) - -/* CONTROL_JTAG */ -#define OMAP4_JTAG_NTRST_EN_SHIFT 31 -#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31) -#define OMAP4_JTAG_TCK_EN_SHIFT 30 -#define OMAP4_JTAG_TCK_EN_MASK (1 << 30) -#define OMAP4_JTAG_RTCK_EN_SHIFT 29 -#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29) -#define OMAP4_JTAG_TDI_EN_SHIFT 28 -#define OMAP4_JTAG_TDI_EN_MASK (1 << 28) -#define OMAP4_JTAG_TDO_EN_SHIFT 27 -#define OMAP4_JTAG_TDO_EN_MASK (1 << 27) - -/* CONTROL_SYS */ -#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31 -#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31) - -/* WKUP_CONTROL_SPARE_RW */ -#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0 -#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0) - -/* WKUP_CONTROL_SPARE_R */ -#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0 -#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0) - -/* WKUP_CONTROL_SPARE_R_C0 */ -#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31 -#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31) -#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30 -#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30) -#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29 -#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29) -#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28 -#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28) -#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27 -#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27) -#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26 -#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26) -#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25 -#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25) -#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24 -#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24) - -#endif diff --git a/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h deleted file mode 100644 index a0af9baec3f7..000000000000 --- a/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * OMAP44xx CTRL_MODULE_WKUP registers and bitfields - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * - * Benoit Cousson (b-cousson@ti.com) - * Santosh Shilimkar (santosh.shilimkar@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H - - -/* Base address */ -#define OMAP4_CTRL_MODULE_WKUP 0x4a30c000 - -/* Registers offset */ -#define OMAP4_CTRL_MODULE_WKUP_IP_REVISION 0x0000 -#define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO 0x0004 -#define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG 0x0010 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0 0x0460 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1 0x0464 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2 0x0468 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3 0x046c -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4 0x0470 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5 0x0474 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6 0x0478 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7 0x047c -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8 0x0480 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9 0x0484 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10 0x0488 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11 0x048c -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12 0x0490 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13 0x0494 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14 0x0498 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15 0x049c -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16 0x04a0 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17 0x04a4 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18 0x04a8 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19 0x04ac -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20 0x04b0 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21 0x04b4 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22 0x04b8 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23 0x04bc -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24 0x04c0 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25 0x04c4 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26 0x04c8 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27 0x04cc -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28 0x04d0 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29 0x04d4 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30 0x04d8 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31 0x04dc - -/* Registers shifts and masks */ - -/* IP_REVISION */ -#define OMAP4_IP_REV_SCHEME_SHIFT 30 -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) -#define OMAP4_IP_REV_FUNC_SHIFT 16 -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) -#define OMAP4_IP_REV_RTL_SHIFT 11 -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) -#define OMAP4_IP_REV_MAJOR_SHIFT 8 -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) -#define OMAP4_IP_REV_CUSTOM_SHIFT 6 -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) -#define OMAP4_IP_REV_MINOR_SHIFT 0 -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) - -/* IP_HWINFO */ -#define OMAP4_IP_HWINFO_SHIFT 0 -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) - -/* IP_SYSCONFIG */ -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) - -/* CONF_DEBUG_SEL_TST_0 */ -#define OMAP4_WKUP_MODE_SHIFT 0 -#define OMAP4_WKUP_MODE_MASK (1 << 0) - -#endif diff --git a/trunk/arch/arm/mach-omap2/io.c b/trunk/arch/arm/mach-omap2/io.c index 40562ddd3ee4..490d87082fad 100644 --- a/trunk/arch/arm/mach-omap2/io.c +++ b/trunk/arch/arm/mach-omap2/io.c @@ -36,7 +36,6 @@ #include "clock2xxx.h" #include "clock3xxx.h" #include "clock44xx.h" -#include "io.h" #include #include diff --git a/trunk/arch/arm/mach-omap2/io.h b/trunk/arch/arm/mach-omap2/io.h deleted file mode 100644 index fd230c6cded5..000000000000 --- a/trunk/arch/arm/mach-omap2/io.h +++ /dev/null @@ -1,7 +0,0 @@ - -#ifndef __MACH_OMAP2_IO_H__ -#define __MACH_OMAP2_IO_H__ - -extern int __init omap_sram_init(void); - -#endif /* __MACH_OMAP2_IO_H__ */ diff --git a/trunk/arch/arm/mach-omap2/irq.c b/trunk/arch/arm/mach-omap2/irq.c index 32eeabe9d2ab..26aeef560aa3 100644 --- a/trunk/arch/arm/mach-omap2/irq.c +++ b/trunk/arch/arm/mach-omap2/irq.c @@ -47,6 +47,7 @@ static struct omap_irq_bank { } __attribute__ ((aligned(4))) irq_banks[] = { { /* MPU INTC */ + .base_reg = 0, .nr_irqs = 96, }, }; diff --git a/trunk/arch/arm/mach-omap2/mailbox.c b/trunk/arch/arm/mach-omap2/mailbox.c index 40ddecab93a9..42dbfa46e656 100644 --- a/trunk/arch/arm/mach-omap2/mailbox.c +++ b/trunk/arch/arm/mach-omap2/mailbox.c @@ -181,7 +181,7 @@ static int omap2_mbox_fifo_full(struct omap_mbox *mbox) static void omap2_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { - struct omap_mbox2_priv *p = mbox->priv; + struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; l = mbox_read_reg(p->irqenable); @@ -192,7 +192,7 @@ static void omap2_mbox_enable_irq(struct omap_mbox *mbox, static void omap2_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { - struct omap_mbox2_priv *p = mbox->priv; + struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; l = mbox_read_reg(p->irqdisable); l &= ~bit; @@ -202,7 +202,7 @@ static void omap2_mbox_disable_irq(struct omap_mbox *mbox, static void omap2_mbox_ack_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { - struct omap_mbox2_priv *p = mbox->priv; + struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; mbox_write_reg(bit, p->irqstatus); @@ -214,7 +214,7 @@ static void omap2_mbox_ack_irq(struct omap_mbox *mbox, static int omap2_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { - struct omap_mbox2_priv *p = mbox->priv; + struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; u32 enable = mbox_read_reg(p->irqenable); u32 status = mbox_read_reg(p->irqstatus); diff --git a/trunk/arch/arm/mach-omap2/mcbsp.c b/trunk/arch/arm/mach-omap2/mcbsp.c index 88b8790e4fec..467aae245781 100644 --- a/trunk/arch/arm/mach-omap2/mcbsp.c +++ b/trunk/arch/arm/mach-omap2/mcbsp.c @@ -23,6 +23,29 @@ #include #include +#include "mux.h" + +static void omap2_mcbsp2_mux_setup(void) +{ + omap_mux_init_signal("eac_ac_sclk.mcbsp2_clkx", OMAP_PULL_ENA); + omap_mux_init_signal("eac_ac_fs.mcbsp2_fsx", OMAP_PULL_ENA); + omap_mux_init_signal("eac_ac_din.mcbsp2_dr", OMAP_PULL_ENA); + omap_mux_init_signal("eac_ac_dout.mcbsp2_dx", OMAP_PULL_ENA); + omap_mux_init_gpio(117, OMAP_PULL_ENA); + /* + * TODO: Need to add MUX settings for OMAP 2430 SDP + */ +} + +static void omap2_mcbsp_request(unsigned int id) +{ + if (cpu_is_omap2420() && (id == OMAP_MCBSP2)) + omap2_mcbsp2_mux_setup(); +} + +static struct omap_mcbsp_ops omap2_mcbsp_ops = { + .request = omap2_mcbsp_request, +}; #ifdef CONFIG_ARCH_OMAP2420 static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { @@ -32,6 +55,7 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, + .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP24XX_MCBSP2_BASE, @@ -39,6 +63,7 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, + .ops = &omap2_mcbsp_ops, }, }; #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) @@ -57,6 +82,7 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, + .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP24XX_MCBSP2_BASE, @@ -64,6 +90,7 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, + .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP2430_MCBSP3_BASE, @@ -71,6 +98,7 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, .rx_irq = INT_24XX_MCBSP3_IRQ_RX, .tx_irq = INT_24XX_MCBSP3_IRQ_TX, + .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP2430_MCBSP4_BASE, @@ -78,6 +106,7 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, .rx_irq = INT_24XX_MCBSP4_IRQ_RX, .tx_irq = INT_24XX_MCBSP4_IRQ_TX, + .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP2430_MCBSP5_BASE, @@ -85,6 +114,7 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, .rx_irq = INT_24XX_MCBSP5_IRQ_RX, .tx_irq = INT_24XX_MCBSP5_IRQ_TX, + .ops = &omap2_mcbsp_ops, }, }; #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) @@ -103,6 +133,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, + .ops = &omap2_mcbsp_ops, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { @@ -112,6 +143,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, + .ops = &omap2_mcbsp_ops, .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ }, { @@ -121,6 +153,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, .rx_irq = INT_24XX_MCBSP3_IRQ_RX, .tx_irq = INT_24XX_MCBSP3_IRQ_TX, + .ops = &omap2_mcbsp_ops, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { @@ -129,6 +162,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, .rx_irq = INT_24XX_MCBSP4_IRQ_RX, .tx_irq = INT_24XX_MCBSP4_IRQ_TX, + .ops = &omap2_mcbsp_ops, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { @@ -137,6 +171,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, .rx_irq = INT_24XX_MCBSP5_IRQ_RX, .tx_irq = INT_24XX_MCBSP5_IRQ_TX, + .ops = &omap2_mcbsp_ops, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, }; @@ -154,24 +189,28 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, .tx_irq = OMAP44XX_IRQ_MCBSP1, + .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP2_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, .tx_irq = OMAP44XX_IRQ_MCBSP2, + .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP3_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, .tx_irq = OMAP44XX_IRQ_MCBSP3, + .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP4_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, .tx_irq = OMAP44XX_IRQ_MCBSP4, + .ops = &omap2_mcbsp_ops, }, }; #define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) diff --git a/trunk/arch/arm/mach-omap2/mux.c b/trunk/arch/arm/mach-omap2/mux.c index 6c2f8f0c0edb..ab403b2ed26b 100644 --- a/trunk/arch/arm/mach-omap2/mux.c +++ b/trunk/arch/arm/mach-omap2/mux.c @@ -87,7 +87,7 @@ static char *omap_mux_options; int __init omap_mux_init_gpio(int gpio, int val) { struct omap_mux_entry *e; - struct omap_mux *gpio_mux = NULL; + struct omap_mux *gpio_mux; u16 old_mode; u16 mux_mode; int found = 0; diff --git a/trunk/arch/arm/mach-omap2/mux2420.c b/trunk/arch/arm/mach-omap2/mux2420.c index 414af5434456..fdb04a7eb8aa 100644 --- a/trunk/arch/arm/mach-omap2/mux2420.c +++ b/trunk/arch/arm/mach-omap2/mux2420.c @@ -507,7 +507,7 @@ static struct omap_mux __initdata omap2420_muxmodes[] = { * Balls for 447-pin POP package */ #ifdef CONFIG_DEBUG_FS -static struct omap_ball __initdata omap2420_pop_ball[] = { +struct omap_ball __initdata omap2420_pop_ball[] = { _OMAP2420_BALLENTRY(CAM_D0, "y4", NULL), _OMAP2420_BALLENTRY(CAM_D1, "y3", NULL), _OMAP2420_BALLENTRY(CAM_D2, "u7", NULL), diff --git a/trunk/arch/arm/mach-omap2/mux2430.c b/trunk/arch/arm/mach-omap2/mux2430.c index 84d2c5a7ecd7..7dcaaa8af32a 100644 --- a/trunk/arch/arm/mach-omap2/mux2430.c +++ b/trunk/arch/arm/mach-omap2/mux2430.c @@ -586,7 +586,7 @@ static struct omap_mux __initdata omap2430_muxmodes[] = { * 447-pin s-PBGA Package, 0.00mm Ball Pitch (Bottom) */ #ifdef CONFIG_DEBUG_FS -static struct omap_ball __initdata omap2430_pop_ball[] = { +struct omap_ball __initdata omap2430_pop_ball[] = { _OMAP2430_BALLENTRY(CAM_D0, "t8", NULL), _OMAP2430_BALLENTRY(CAM_D1, "t4", NULL), _OMAP2430_BALLENTRY(CAM_D10, "r4", NULL), diff --git a/trunk/arch/arm/mach-omap2/mux34xx.c b/trunk/arch/arm/mach-omap2/mux34xx.c index 574e54ea3ab7..f64d7eea3451 100644 --- a/trunk/arch/arm/mach-omap2/mux34xx.c +++ b/trunk/arch/arm/mach-omap2/mux34xx.c @@ -931,7 +931,7 @@ struct omap_ball __initdata omap3_cbc_ball[] = { * Signals different on CUS package compared to superset */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS) -static struct omap_mux __initdata omap3_cus_subset[] = { +struct omap_mux __initdata omap3_cus_subset[] = { _OMAP3_MUXENTRY(CAM_D10, 109, "cam_d10", NULL, NULL, NULL, "gpio_109", NULL, NULL, "safe_mode"), @@ -1077,7 +1077,7 @@ static struct omap_mux __initdata omap3_cus_subset[] = { */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ && defined(CONFIG_OMAP_PACKAGE_CUS) -static struct omap_ball __initdata omap3_cus_ball[] = { +struct omap_ball __initdata omap3_cus_ball[] = { _OMAP3_BALLENTRY(CAM_D0, "ab18", NULL), _OMAP3_BALLENTRY(CAM_D1, "ac18", NULL), _OMAP3_BALLENTRY(CAM_D10, "f21", NULL), @@ -1269,7 +1269,7 @@ static struct omap_ball __initdata omap3_cus_ball[] = { * Signals different on CBB package comapared to superset */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB) -static struct omap_mux __initdata omap3_cbb_subset[] = { +struct omap_mux __initdata omap3_cbb_subset[] = { _OMAP3_MUXENTRY(CAM_D10, 109, "cam_d10", NULL, NULL, NULL, "gpio_109", NULL, NULL, "safe_mode"), @@ -1390,7 +1390,7 @@ static struct omap_mux __initdata omap3_cbb_subset[] = { */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ && defined(CONFIG_OMAP_PACKAGE_CBB) -static struct omap_ball __initdata omap3_cbb_ball[] = { +struct omap_ball __initdata omap3_cbb_ball[] = { _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL), _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL), _OMAP3_BALLENTRY(CAM_D10, "b25", NULL), @@ -1600,7 +1600,7 @@ static struct omap_ball __initdata omap3_cbb_ball[] = { * Signals different on 36XX CBP package comapared to 34XX CBC package */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP) -static struct omap_mux __initdata omap36xx_cbp_subset[] = { +struct omap_mux __initdata omap36xx_cbp_subset[] = { _OMAP3_MUXENTRY(CAM_D0, 99, "cam_d0", NULL, "csi2_dx2", NULL, "gpio_99", NULL, NULL, "safe_mode"), @@ -1818,7 +1818,7 @@ static struct omap_mux __initdata omap36xx_cbp_subset[] = { */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ && defined (CONFIG_OMAP_PACKAGE_CBP) -static struct omap_ball __initdata omap36xx_cbp_ball[] = { +struct omap_ball __initdata omap36xx_cbp_ball[] = { _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL), _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL), _OMAP3_BALLENTRY(CAM_D10, "b25", NULL), diff --git a/trunk/arch/arm/mach-omap2/omap4-common.c b/trunk/arch/arm/mach-omap2/omap4-common.c index 923f9f5f91ce..13dc9794dcc2 100644 --- a/trunk/arch/arm/mach-omap2/omap4-common.c +++ b/trunk/arch/arm/mach-omap2/omap4-common.c @@ -61,14 +61,10 @@ static int __init omap_l2_cache_init(void) omap_smc1(0x102, 0x1); /* - * 16-way associativity, parity disabled - * Way size - 32KB (es1.0) - * Way size - 64KB (es2.0 +) + * 32KB way size, 16-way associativity, + * parity disabled */ - if (omap_rev() == OMAP4430_REV_ES1_0) - l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); - else - l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff); + l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); return 0; } diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod.c b/trunk/arch/arm/mach-omap2/omap_hwmod.c index 955861acc0c4..cb911d7d1a3c 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod.c @@ -13,102 +13,10 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Introduction - * ------------ - * One way to view an OMAP SoC is as a collection of largely unrelated - * IP blocks connected by interconnects. The IP blocks include - * devices such as ARM processors, audio serial interfaces, UARTs, - * etc. Some of these devices, like the DSP, are created by TI; - * others, like the SGX, largely originate from external vendors. In - * TI's documentation, on-chip devices are referred to as "OMAP - * modules." Some of these IP blocks are identical across several - * OMAP versions. Others are revised frequently. - * - * These OMAP modules are tied together by various interconnects. - * Most of the address and data flow between modules is via OCP-based - * interconnects such as the L3 and L4 buses; but there are other - * interconnects that distribute the hardware clock tree, handle idle - * and reset signaling, supply power, and connect the modules to - * various pads or balls on the OMAP package. - * - * OMAP hwmod provides a consistent way to describe the on-chip - * hardware blocks and their integration into the rest of the chip. - * This description can be automatically generated from the TI - * hardware database. OMAP hwmod provides a standard, consistent API - * to reset, enable, idle, and disable these hardware blocks. And - * hwmod provides a way for other core code, such as the Linux device - * code or the OMAP power management and address space mapping code, - * to query the hardware database. - * - * Using hwmod - * ----------- - * Drivers won't call hwmod functions directly. That is done by the - * omap_device code, and in rare occasions, by custom integration code - * in arch/arm/ *omap*. The omap_device code includes functions to - * build a struct platform_device using omap_hwmod data, and that is - * currently how hwmod data is communicated to drivers and to the - * Linux driver model. Most drivers will call omap_hwmod functions only - * indirectly, via pm_runtime*() functions. - * - * From a layering perspective, here is where the OMAP hwmod code - * fits into the kernel software stack: - * - * +-------------------------------+ - * | Device driver code | - * | (e.g., drivers/) | - * +-------------------------------+ - * | Linux driver model | - * | (platform_device / | - * | platform_driver data/code) | - * +-------------------------------+ - * | OMAP core-driver integration | - * |(arch/arm/mach-omap2/devices.c)| - * +-------------------------------+ - * | omap_device code | - * | (../plat-omap/omap_device.c) | - * +-------------------------------+ - * ----> | omap_hwmod code/data | <----- - * | (../mach-omap2/omap_hwmod*) | - * +-------------------------------+ - * | OMAP clock/PRCM/register fns | - * | (__raw_{read,write}l, clk*) | - * +-------------------------------+ - * - * Device drivers should not contain any OMAP-specific code or data in - * them. They should only contain code to operate the IP block that - * the driver is responsible for. This is because these IP blocks can - * also appear in other SoCs, either from TI (such as DaVinci) or from - * other manufacturers; and drivers should be reusable across other - * platforms. - * - * The OMAP hwmod code also will attempt to reset and idle all on-chip - * devices upon boot. The goal here is for the kernel to be - * completely self-reliant and independent from bootloaders. This is - * to ensure a repeatable configuration, both to ensure consistent - * runtime behavior, and to make it easier for others to reproduce - * bugs. - * - * OMAP module activity states - * --------------------------- - * The hwmod code considers modules to be in one of several activity - * states. IP blocks start out in an UNKNOWN state, then once they - * are registered via the hwmod code, proceed to the REGISTERED state. - * Once their clock names are resolved to clock pointers, the module - * enters the CLKS_INITED state; and finally, once the module has been - * reset and the integration registers programmed, the INITIALIZED state - * is entered. The hwmod code will then place the module into either - * the IDLE state to save power, or in the case of a critical system - * module, the ENABLED state. - * - * OMAP core integration code can then call omap_hwmod*() functions - * directly to move the module between the IDLE, ENABLED, and DISABLED - * states, as needed. This is done during both the PM idle loop, and - * in the OMAP core integration code's implementation of the PM runtime - * functions. - * - * References - * ---------- - * This is a partial list. + * This code manages "OMAP modules" (on-chip devices) and their + * integration with Linux device driver and bus code. + * + * References: * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) @@ -142,13 +50,11 @@ #include #include #include -#include #include "cm.h" -#include "prm.h" -/* Maximum microseconds to wait for OMAP module to softreset */ -#define MAX_MODULE_SOFTRESET_WAIT 10000 +/* Maximum microseconds to wait for OMAP module to reset */ +#define MAX_MODULE_RESET_WAIT 10000 /* Name of the OMAP hwmod for the MPU */ #define MPU_INITIATOR_NAME "mpu" @@ -638,36 +544,6 @@ static int _disable_clocks(struct omap_hwmod *oh) return 0; } -static void _enable_optional_clocks(struct omap_hwmod *oh) -{ - struct omap_hwmod_opt_clk *oc; - int i; - - pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); - - for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) - if (oc->_clk) { - pr_debug("omap_hwmod: enable %s:%s\n", oc->role, - oc->_clk->name); - clk_enable(oc->_clk); - } -} - -static void _disable_optional_clocks(struct omap_hwmod *oh) -{ - struct omap_hwmod_opt_clk *oc; - int i; - - pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); - - for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) - if (oc->_clk) { - pr_debug("omap_hwmod: disable %s:%s\n", oc->role, - oc->_clk->name); - clk_disable(oc->_clk); - } -} - /** * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use * @oh: struct omap_hwmod * @@ -746,7 +622,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) } /** - * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG + * _sysc_enable - try to bring a module out of idle via OCP_SYSCONFIG * @oh: struct omap_hwmod * * * If module is marked as SWSUP_SIDLE, force the module out of slave @@ -754,7 +630,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) * as SWSUP_MSUSPEND, force the module out of master standby; * otherwise, configure it for smart-standby. No return value. */ -static void _enable_sysc(struct omap_hwmod *oh) +static void _sysc_enable(struct omap_hwmod *oh) { u8 idlemode, sf; u32 v; @@ -777,6 +653,14 @@ static void _enable_sysc(struct omap_hwmod *oh) _set_master_standbymode(oh, idlemode, &v); } + if (sf & SYSC_HAS_AUTOIDLE) { + idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? + 0 : 1; + _set_module_autoidle(oh, idlemode, &v); + } + + /* XXX OCP ENAWAKEUP bit? */ + /* * XXX The clock framework should handle this, by * calling into this code. But this must wait until the @@ -787,25 +671,10 @@ static void _enable_sysc(struct omap_hwmod *oh) _set_clockactivity(oh, oh->class->sysc->clockact, &v); _write_sysconfig(v, oh); - - /* If slave is in SMARTIDLE, also enable wakeup */ - if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) - _enable_wakeup(oh); - - /* - * Set the autoidle bit only after setting the smartidle bit - * Setting this will not have any impact on the other modules. - */ - if (sf & SYSC_HAS_AUTOIDLE) { - idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? - 0 : 1; - _set_module_autoidle(oh, idlemode, &v); - _write_sysconfig(v, oh); - } } /** - * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG + * _sysc_idle - try to put a module into idle via OCP_SYSCONFIG * @oh: struct omap_hwmod * * * If module is marked as SWSUP_SIDLE, force the module into slave @@ -813,7 +682,7 @@ static void _enable_sysc(struct omap_hwmod *oh) * as SWSUP_MSUSPEND, force the module into master standby; otherwise, * configure it for smart-standby. No return value. */ -static void _idle_sysc(struct omap_hwmod *oh) +static void _sysc_idle(struct omap_hwmod *oh) { u8 idlemode, sf; u32 v; @@ -840,13 +709,13 @@ static void _idle_sysc(struct omap_hwmod *oh) } /** - * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG + * _sysc_shutdown - force a module into idle via OCP_SYSCONFIG * @oh: struct omap_hwmod * * * Force the module into slave idle and master suspend. No return * value. */ -static void _shutdown_sysc(struct omap_hwmod *oh) +static void _sysc_shutdown(struct omap_hwmod *oh) { u32 v; u8 sf; @@ -898,10 +767,10 @@ static struct omap_hwmod *_lookup(const char *name) * @data: not used; pass NULL * * Called by omap_hwmod_late_init() (after omap2_clk_init()). - * Resolves all clock names embedded in the hwmod. Returns -EINVAL if - * the omap_hwmod has not yet been registered or if the clocks have - * already been initialized, 0 on success, or a non-zero error on - * failure. + * Resolves all clock names embedded in the hwmod. Must be called + * with omap_hwmod_mutex held. Returns -EINVAL if the omap_hwmod + * has not yet been registered or if the clocks have already been + * initialized, 0 on success, or a non-zero error on failure. */ static int _init_clocks(struct omap_hwmod *oh, void *data) { @@ -964,203 +833,57 @@ static int _wait_target_ready(struct omap_hwmod *oh) return ret; } -/** - * _lookup_hardreset - return the register bit shift for this hwmod/reset line - * @oh: struct omap_hwmod * - * @name: name of the reset line in the context of this hwmod - * - * Return the bit position of the reset line that match the - * input name. Return -ENOENT if not found. - */ -static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name) -{ - int i; - - for (i = 0; i < oh->rst_lines_cnt; i++) { - const char *rst_line = oh->rst_lines[i].name; - if (!strcmp(rst_line, name)) { - u8 shift = oh->rst_lines[i].rst_shift; - pr_debug("omap_hwmod: %s: _lookup_hardreset: %s: %d\n", - oh->name, rst_line, shift); - - return shift; - } - } - - return -ENOENT; -} - -/** - * _assert_hardreset - assert the HW reset line of submodules - * contained in the hwmod module. - * @oh: struct omap_hwmod * - * @name: name of the reset line to lookup and assert - * - * Some IP like dsp, ipu or iva contain processor that require - * an HW reset line to be assert / deassert in order to enable fully - * the IP. - */ -static int _assert_hardreset(struct omap_hwmod *oh, const char *name) -{ - u8 shift; - - if (!oh) - return -EINVAL; - - shift = _lookup_hardreset(oh, name); - if (IS_ERR_VALUE(shift)) - return shift; - - if (cpu_is_omap24xx() || cpu_is_omap34xx()) - return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, - shift); - else if (cpu_is_omap44xx()) - return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg, - shift); - else - return -EINVAL; -} - -/** - * _deassert_hardreset - deassert the HW reset line of submodules contained - * in the hwmod module. - * @oh: struct omap_hwmod * - * @name: name of the reset line to look up and deassert - * - * Some IP like dsp, ipu or iva contain processor that require - * an HW reset line to be assert / deassert in order to enable fully - * the IP. - */ -static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) -{ - u8 shift; - int r; - - if (!oh) - return -EINVAL; - - shift = _lookup_hardreset(oh, name); - if (IS_ERR_VALUE(shift)) - return shift; - - if (cpu_is_omap24xx() || cpu_is_omap34xx()) - r = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, - shift); - else if (cpu_is_omap44xx()) - r = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg, - shift); - else - return -EINVAL; - - if (r == -EBUSY) - pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); - - return r; -} - -/** - * _read_hardreset - read the HW reset line state of submodules - * contained in the hwmod module - * @oh: struct omap_hwmod * - * @name: name of the reset line to look up and read - * - * Return the state of the reset line. - */ -static int _read_hardreset(struct omap_hwmod *oh, const char *name) -{ - u8 shift; - - if (!oh) - return -EINVAL; - - shift = _lookup_hardreset(oh, name); - if (IS_ERR_VALUE(shift)) - return shift; - - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { - return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, - shift); - } else if (cpu_is_omap44xx()) { - return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg, - shift); - } else { - return -EINVAL; - } -} - /** * _reset - reset an omap_hwmod * @oh: struct omap_hwmod * * * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be - * enabled for this to work. Returns -EINVAL if the hwmod cannot be - * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if - * the module did not reset in time, or 0 upon success. - * - * In OMAP3 a specific SYSSTATUS register is used to get the reset status. - * Starting in OMAP4, some IPs does not have SYSSTATUS register and instead - * use the SYSCONFIG softreset bit to provide the status. - * - * Note that some IP like McBSP does have a reset control but no reset status. + * enabled for this to work. Must be called with omap_hwmod_mutex + * held. Returns -EINVAL if the hwmod cannot be reset this way or if + * the hwmod is in the wrong state, -ETIMEDOUT if the module did not + * reset in time, or 0 upon success. */ static int _reset(struct omap_hwmod *oh) { - u32 v; + u32 r, v; int c = 0; - int ret = 0; if (!oh->class->sysc || - !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) + !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET) || + (oh->class->sysc->sysc_flags & SYSS_MISSING)) return -EINVAL; /* clocks must be on for this operation */ if (oh->_state != _HWMOD_STATE_ENABLED) { - pr_warning("omap_hwmod: %s: reset can only be entered from " - "enabled state\n", oh->name); + WARN(1, "omap_hwmod: %s: reset can only be entered from " + "enabled state\n", oh->name); return -EINVAL; } - /* For some modules, all optionnal clocks need to be enabled as well */ - if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) - _enable_optional_clocks(oh); - pr_debug("omap_hwmod: %s: resetting\n", oh->name); v = oh->_sysc_cache; - ret = _set_softreset(oh, &v); - if (ret) - goto dis_opt_clks; + r = _set_softreset(oh, &v); + if (r) + return r; _write_sysconfig(v, oh); - if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) - omap_test_timeout((omap_hwmod_readl(oh, - oh->class->sysc->syss_offs) - & SYSS_RESETDONE_MASK), - MAX_MODULE_SOFTRESET_WAIT, c); - else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) - omap_test_timeout(!(omap_hwmod_readl(oh, - oh->class->sysc->sysc_offs) - & SYSC_TYPE2_SOFTRESET_MASK), - MAX_MODULE_SOFTRESET_WAIT, c); - - if (c == MAX_MODULE_SOFTRESET_WAIT) - pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", - oh->name, MAX_MODULE_SOFTRESET_WAIT); + omap_test_timeout((omap_hwmod_readl(oh, oh->class->sysc->syss_offs) & + SYSS_RESETDONE_MASK), + MAX_MODULE_RESET_WAIT, c); + + if (c == MAX_MODULE_RESET_WAIT) + WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n", + oh->name, MAX_MODULE_RESET_WAIT); else - pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); + pr_debug("omap_hwmod: %s: reset in %d usec\n", oh->name, c); /* * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from * _wait_target_ready() or _reset() */ - ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; - -dis_opt_clks: - if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) - _disable_optional_clocks(oh); - - return ret; + return (c == MAX_MODULE_RESET_WAIT) ? -ETIMEDOUT : 0; } /** @@ -1168,11 +891,9 @@ static int _reset(struct omap_hwmod *oh) * @oh: struct omap_hwmod * * * Enables an omap_hwmod @oh such that the MPU can access the hwmod's - * register target. (This function has a full name -- - * _omap_hwmod_enable() rather than simply _enable() -- because it is - * currently required by the pm34xx.c idle loop.) Returns -EINVAL if - * the hwmod is in the wrong state or passes along the return value of - * _wait_target_ready(). + * register target. Must be called with omap_hwmod_mutex held. + * Returns -EINVAL if the hwmod is in the wrong state or passes along + * the return value of _wait_target_ready(). */ int _omap_hwmod_enable(struct omap_hwmod *oh) { @@ -1188,15 +909,6 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: enabling\n", oh->name); - /* - * If an IP contains only one HW reset line, then de-assert it in order - * to allow to enable the clocks. Otherwise the PRCM will return - * Intransition status, and the init will failed. - */ - if ((oh->_state == _HWMOD_STATE_INITIALIZED || - oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) - _deassert_hardreset(oh, oh->rst_lines[0].name); - /* XXX mux balls */ _add_initiator_dep(oh, mpu_oh); @@ -1210,7 +922,7 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) if (oh->class->sysc) { if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) _update_sysc_cache(oh); - _enable_sysc(oh); + _sysc_enable(oh); } } else { pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", @@ -1221,14 +933,12 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) } /** - * _omap_hwmod_idle - idle an omap_hwmod + * _idle - idle an omap_hwmod * @oh: struct omap_hwmod * * * Idles an omap_hwmod @oh. This should be called once the hwmod has - * no further work. (This function has a full name -- - * _omap_hwmod_idle() rather than simply _idle() -- because it is - * currently required by the pm34xx.c idle loop.) Returns -EINVAL if - * the hwmod is in the wrong state or returns 0. + * no further work. Returns -EINVAL if the hwmod is in the wrong + * state or returns 0. */ int _omap_hwmod_idle(struct omap_hwmod *oh) { @@ -1241,7 +951,7 @@ int _omap_hwmod_idle(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: idling\n", oh->name); if (oh->class->sysc) - _idle_sysc(oh); + _sysc_idle(oh); _del_initiator_dep(oh, mpu_oh); _disable_clocks(oh); @@ -1271,21 +981,10 @@ static int _shutdown(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: disabling\n", oh->name); if (oh->class->sysc) - _shutdown_sysc(oh); - - /* - * If an IP contains only one HW reset line, then assert it - * before disabling the clocks and shutting down the IP. - */ - if (oh->rst_lines_cnt == 1) - _assert_hardreset(oh, oh->rst_lines[0].name); - - /* clocks and deps are already disabled in idle */ - if (oh->_state == _HWMOD_STATE_ENABLED) { - _del_initiator_dep(oh, mpu_oh); - /* XXX what about the other system initiators here? dma, dsp */ - _disable_clocks(oh); - } + _sysc_shutdown(oh); + _del_initiator_dep(oh, mpu_oh); + /* XXX what about the other system initiators here? DMA, tesla, d2d */ + _disable_clocks(oh); /* XXX Should this code also force-disable the optional clocks? */ /* XXX mux any associated balls to safe mode */ @@ -1301,10 +1000,11 @@ static int _shutdown(struct omap_hwmod *oh) * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1 * * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh - * OCP_SYSCONFIG register. @skip_setup_idle is intended to be used on - * a system that will not call omap_hwmod_enable() to enable devices - * (e.g., a system without PM runtime). Returns -EINVAL if the hwmod - * is in the wrong state or returns 0. + * OCP_SYSCONFIG register. Must be called with omap_hwmod_mutex held. + * @skip_setup_idle is intended to be used on a system that will not + * call omap_hwmod_enable() to enable devices (e.g., a system without + * PM runtime). Returns -EINVAL if the hwmod is in the wrong state or + * returns 0. */ static int _setup(struct omap_hwmod *oh, void *data) { @@ -1334,19 +1034,8 @@ static int _setup(struct omap_hwmod *oh, void *data) } } - mutex_init(&oh->_mutex); oh->_state = _HWMOD_STATE_INITIALIZED; - /* - * In the case of hwmod with hardreset that should not be - * de-assert at boot time, we have to keep the module - * initialized, because we cannot enable it properly with the - * reset asserted. Exit without warning because that behavior is - * expected. - */ - if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1) - return 0; - r = _omap_hwmod_enable(oh); if (r) { pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", @@ -1355,16 +1044,16 @@ static int _setup(struct omap_hwmod *oh, void *data) } if (!(oh->flags & HWMOD_INIT_NO_RESET)) { - _reset(oh); - /* - * OCP_SYSCONFIG bits need to be reprogrammed after a softreset. - * The _omap_hwmod_enable() function should be split to - * avoid the rewrite of the OCP_SYSCONFIG register. + * XXX Do the OCP_SYSCONFIG bits need to be + * reprogrammed after a reset? If not, then this can + * be removed. If they do, then probably the + * _omap_hwmod_enable() function should be split to avoid the + * rewrite of the OCP_SYSCONFIG register. */ if (oh->class->sysc) { _update_sysc_cache(oh); - _enable_sysc(oh); + _sysc_enable(oh); } } @@ -1620,7 +1309,7 @@ int omap_hwmod_unregister(struct omap_hwmod *oh) * omap_hwmod_enable - enable an omap_hwmod * @oh: struct omap_hwmod * * - * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). + * Enable an omap_hwomd @oh. Intended to be called by omap_device_enable(). * Returns -EINVAL on error or passes along the return value from _enable(). */ int omap_hwmod_enable(struct omap_hwmod *oh) @@ -1630,9 +1319,9 @@ int omap_hwmod_enable(struct omap_hwmod *oh) if (!oh) return -EINVAL; - mutex_lock(&oh->_mutex); + mutex_lock(&omap_hwmod_mutex); r = _omap_hwmod_enable(oh); - mutex_unlock(&oh->_mutex); + mutex_unlock(&omap_hwmod_mutex); return r; } @@ -1642,7 +1331,7 @@ int omap_hwmod_enable(struct omap_hwmod *oh) * omap_hwmod_idle - idle an omap_hwmod * @oh: struct omap_hwmod * * - * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). + * Idle an omap_hwomd @oh. Intended to be called by omap_device_idle(). * Returns -EINVAL on error or passes along the return value from _idle(). */ int omap_hwmod_idle(struct omap_hwmod *oh) @@ -1650,9 +1339,9 @@ int omap_hwmod_idle(struct omap_hwmod *oh) if (!oh) return -EINVAL; - mutex_lock(&oh->_mutex); + mutex_lock(&omap_hwmod_mutex); _omap_hwmod_idle(oh); - mutex_unlock(&oh->_mutex); + mutex_unlock(&omap_hwmod_mutex); return 0; } @@ -1661,7 +1350,7 @@ int omap_hwmod_idle(struct omap_hwmod *oh) * omap_hwmod_shutdown - shutdown an omap_hwmod * @oh: struct omap_hwmod * * - * Shutdown an omap_hwmod @oh. Intended to be called by + * Shutdown an omap_hwomd @oh. Intended to be called by * omap_device_shutdown(). Returns -EINVAL on error or passes along * the return value from _shutdown(). */ @@ -1670,9 +1359,9 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh) if (!oh) return -EINVAL; - mutex_lock(&oh->_mutex); + mutex_lock(&omap_hwmod_mutex); _shutdown(oh); - mutex_unlock(&oh->_mutex); + mutex_unlock(&omap_hwmod_mutex); return 0; } @@ -1685,9 +1374,9 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh) */ int omap_hwmod_enable_clocks(struct omap_hwmod *oh) { - mutex_lock(&oh->_mutex); + mutex_lock(&omap_hwmod_mutex); _enable_clocks(oh); - mutex_unlock(&oh->_mutex); + mutex_unlock(&omap_hwmod_mutex); return 0; } @@ -1700,9 +1389,9 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh) */ int omap_hwmod_disable_clocks(struct omap_hwmod *oh) { - mutex_lock(&oh->_mutex); + mutex_lock(&omap_hwmod_mutex); _disable_clocks(oh); - mutex_unlock(&oh->_mutex); + mutex_unlock(&omap_hwmod_mutex); return 0; } @@ -1741,18 +1430,20 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) * * Under some conditions, a driver may wish to reset the entire device. * Called from omap_device code. Returns -EINVAL on error or passes along - * the return value from _reset(). + * the return value from _reset()/_enable(). */ int omap_hwmod_reset(struct omap_hwmod *oh) { int r; - if (!oh) + if (!oh || !(oh->_state & _HWMOD_STATE_ENABLED)) return -EINVAL; - mutex_lock(&oh->_mutex); + mutex_lock(&omap_hwmod_mutex); r = _reset(oh); - mutex_unlock(&oh->_mutex); + if (!r) + r = _omap_hwmod_enable(oh); + mutex_unlock(&omap_hwmod_mutex); return r; } @@ -1777,7 +1468,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh) { int ret, i; - ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt; + ret = oh->mpu_irqs_cnt + oh->sdma_chs_cnt; for (i = 0; i < oh->slaves_cnt; i++) ret += oh->slaves[i]->addr_cnt; @@ -1810,10 +1501,10 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) r++; } - for (i = 0; i < oh->sdma_reqs_cnt; i++) { - (res + r)->name = (oh->sdma_reqs + i)->name; - (res + r)->start = (oh->sdma_reqs + i)->dma_req; - (res + r)->end = (oh->sdma_reqs + i)->dma_req; + for (i = 0; i < oh->sdma_chs_cnt; i++) { + (res + r)->name = (oh->sdma_chs + i)->name; + (res + r)->start = (oh->sdma_chs + i)->dma_ch; + (res + r)->end = (oh->sdma_chs + i)->dma_ch; (res + r)->flags = IORESOURCE_DMA; r++; } @@ -1953,9 +1644,9 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) return -EINVAL; - mutex_lock(&oh->_mutex); + mutex_lock(&omap_hwmod_mutex); _enable_wakeup(oh); - mutex_unlock(&oh->_mutex); + mutex_unlock(&omap_hwmod_mutex); return 0; } @@ -1978,91 +1669,13 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) return -EINVAL; - mutex_lock(&oh->_mutex); + mutex_lock(&omap_hwmod_mutex); _disable_wakeup(oh); - mutex_unlock(&oh->_mutex); + mutex_unlock(&omap_hwmod_mutex); return 0; } -/** - * omap_hwmod_assert_hardreset - assert the HW reset line of submodules - * contained in the hwmod module. - * @oh: struct omap_hwmod * - * @name: name of the reset line to lookup and assert - * - * Some IP like dsp, ipu or iva contain processor that require - * an HW reset line to be assert / deassert in order to enable fully - * the IP. Returns -EINVAL if @oh is null or if the operation is not - * yet supported on this OMAP; otherwise, passes along the return value - * from _assert_hardreset(). - */ -int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) -{ - int ret; - - if (!oh) - return -EINVAL; - - mutex_lock(&oh->_mutex); - ret = _assert_hardreset(oh, name); - mutex_unlock(&oh->_mutex); - - return ret; -} - -/** - * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules - * contained in the hwmod module. - * @oh: struct omap_hwmod * - * @name: name of the reset line to look up and deassert - * - * Some IP like dsp, ipu or iva contain processor that require - * an HW reset line to be assert / deassert in order to enable fully - * the IP. Returns -EINVAL if @oh is null or if the operation is not - * yet supported on this OMAP; otherwise, passes along the return value - * from _deassert_hardreset(). - */ -int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) -{ - int ret; - - if (!oh) - return -EINVAL; - - mutex_lock(&oh->_mutex); - ret = _deassert_hardreset(oh, name); - mutex_unlock(&oh->_mutex); - - return ret; -} - -/** - * omap_hwmod_read_hardreset - read the HW reset line state of submodules - * contained in the hwmod module - * @oh: struct omap_hwmod * - * @name: name of the reset line to look up and read - * - * Return the current state of the hwmod @oh's reset line named @name: - * returns -EINVAL upon parameter error or if this operation - * is unsupported on the current OMAP; otherwise, passes along the return - * value from _read_hardreset(). - */ -int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) -{ - int ret; - - if (!oh) - return -EINVAL; - - mutex_lock(&oh->_mutex); - ret = _read_hardreset(oh, name); - mutex_unlock(&oh->_mutex); - - return ret; -} - - /** * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname * @classname: struct omap_hwmod_class name to search for diff --git a/trunk/arch/arm/mach-omap2/pm-debug.c b/trunk/arch/arm/mach-omap2/pm-debug.c index 5e81517a7af2..af00c174d7a9 100644 --- a/trunk/arch/arm/mach-omap2/pm-debug.c +++ b/trunk/arch/arm/mach-omap2/pm-debug.c @@ -167,7 +167,7 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) static void pm_dbg_regset_store(u32 *ptr); -static struct dentry *pm_dbg_dir; +struct dentry *pm_dbg_dir; static int pm_dbg_init_done; diff --git a/trunk/arch/arm/mach-omap2/pm34xx.c b/trunk/arch/arm/mach-omap2/pm34xx.c index ac572aaebb0f..d2b940c7215d 100644 --- a/trunk/arch/arm/mach-omap2/pm34xx.c +++ b/trunk/arch/arm/mach-omap2/pm34xx.c @@ -310,7 +310,7 @@ static void restore_control_register(u32 val) /* Function to restore the table entry that was modified for enabling MMU */ static void restore_table_entry(void) { - void __iomem *scratchpad_address; + u32 *scratchpad_address; u32 previous_value, control_reg_value; u32 *address; diff --git a/trunk/arch/arm/mach-omap2/pm_bus.c b/trunk/arch/arm/mach-omap2/pm_bus.c deleted file mode 100644 index 784989f8f2f5..000000000000 --- a/trunk/arch/arm/mach-omap2/pm_bus.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Runtime PM support code for OMAP - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * Copyright (C) 2010 Texas Instruments, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include -#include -#include -#include -#include -#include - -#include -#include - -#ifdef CONFIG_PM_RUNTIME -int omap_pm_runtime_suspend(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - int r, ret = 0; - - dev_dbg(dev, "%s\n", __func__); - - ret = pm_generic_runtime_suspend(dev); - - if (!ret && dev->parent == &omap_device_parent) { - r = omap_device_idle(pdev); - WARN_ON(r); - } - - return ret; -}; - -int omap_pm_runtime_resume(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - int r; - - dev_dbg(dev, "%s\n", __func__); - - if (dev->parent == &omap_device_parent) { - r = omap_device_enable(pdev); - WARN_ON(r); - } - - return pm_generic_runtime_resume(dev); -}; -#else -#define omap_pm_runtime_suspend NULL -#define omap_pm_runtime_resume NULL -#endif /* CONFIG_PM_RUNTIME */ - -static int __init omap_pm_runtime_init(void) -{ - const struct dev_pm_ops *pm; - struct dev_pm_ops *omap_pm; - - pm = platform_bus_get_pm_ops(); - if (!pm) { - pr_err("%s: unable to get dev_pm_ops from platform_bus\n", - __func__); - return -ENODEV; - } - - omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL); - if (!omap_pm) { - pr_err("%s: unable to alloc memory for new dev_pm_ops\n", - __func__); - return -ENOMEM; - } - - omap_pm->runtime_suspend = omap_pm_runtime_suspend; - omap_pm->runtime_resume = omap_pm_runtime_resume; - - platform_bus_set_pm_ops(omap_pm); - - return 0; -} -core_initcall(omap_pm_runtime_init); diff --git a/trunk/arch/arm/mach-omap2/powerdomains44xx.h b/trunk/arch/arm/mach-omap2/powerdomains44xx.h index 9c01b55d6102..c7219513472a 100644 --- a/trunk/arch/arm/mach-omap2/powerdomains44xx.h +++ b/trunk/arch/arm/mach-omap2/powerdomains44xx.h @@ -98,7 +98,7 @@ static struct powerdomain dss_44xx_pwrdm = { .prcm_offs = OMAP4430_PRM_DSS_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF, + .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 1, .pwrsts_mem_ret = { [0] = PWRDM_POWER_OFF, /* dss_mem */ diff --git a/trunk/arch/arm/mach-omap2/prcm.c b/trunk/arch/arm/mach-omap2/prcm.c index a48a1e24f42b..c20137497c92 100644 --- a/trunk/arch/arm/mach-omap2/prcm.c +++ b/trunk/arch/arm/mach-omap2/prcm.c @@ -33,7 +33,6 @@ #include "cm.h" #include "prm.h" #include "prm-regbits-24xx.h" -#include "prm-regbits-44xx.h" static void __iomem *prm_base; static void __iomem *cm_base; @@ -119,7 +118,7 @@ struct omap3_prcm_regs { u32 wkup_pm_wken; }; -static struct omap3_prcm_regs prcm_context; +struct omap3_prcm_regs prcm_context; u32 omap_prcm_get_reset_sources(void) { @@ -162,8 +161,8 @@ void omap_prcm_arch_reset(char mode, const char *cmd) prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, OMAP2_RM_RSTCTRL); if (cpu_is_omap44xx()) - prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK, - prcm_offs, OMAP4_RM_RSTCTRL); + prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, + OMAP4_RM_RSTCTRL); } static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) @@ -216,30 +215,6 @@ u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) return v; } -/* Read a PRM register, AND it, and shift the result down to bit 0 */ -u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask) -{ - u32 v; - - v = __raw_readl(reg); - v &= mask; - v >>= __ffs(mask); - - return v; -} - -/* Read-modify-write a register in a PRM module. Caller must lock */ -u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg) -{ - u32 v; - - v = __raw_readl(reg); - v &= ~mask; - v |= bits; - __raw_writel(v, reg); - - return v; -} /* Read a register in a CM module */ u32 cm_read_mod_reg(s16 module, u16 idx) { diff --git a/trunk/arch/arm/mach-omap2/prm-regbits-44xx.h b/trunk/arch/arm/mach-omap2/prm-regbits-44xx.h index 25b19b610177..597be4a2b9ff 100644 --- a/trunk/arch/arm/mach-omap2/prm-regbits-44xx.h +++ b/trunk/arch/arm/mach-omap2/prm-regbits-44xx.h @@ -1,8 +1,8 @@ /* * OMAP44xx Power Management register bits * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * Copyright (C) 2009-2010 Nokia Corporation + * Copyright (C) 2009 Texas Instruments, Inc. + * Copyright (C) 2009 Nokia Corporation * * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) @@ -30,611 +30,587 @@ * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1 -#define OMAP4430_ABBOFF_ACT_EXPORT_MASK (1 << 1) +#define OMAP4430_ABBOFF_ACT_EXPORT_MASK BITFIELD(1, 1) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2 -#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) +#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK BITFIELD(2, 2) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31 -#define OMAP4430_ABB_IVA_DONE_EN_MASK (1 << 31) +#define OMAP4430_ABB_IVA_DONE_EN_MASK BITFIELD(31, 31) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31 -#define OMAP4430_ABB_IVA_DONE_ST_MASK (1 << 31) +#define OMAP4430_ABB_IVA_DONE_ST_MASK BITFIELD(31, 31) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7 -#define OMAP4430_ABB_MPU_DONE_EN_MASK (1 << 7) +#define OMAP4430_ABB_MPU_DONE_EN_MASK BITFIELD(7, 7) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7 -#define OMAP4430_ABB_MPU_DONE_ST_MASK (1 << 7) +#define OMAP4430_ABB_MPU_DONE_ST_MASK BITFIELD(7, 7) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2 -#define OMAP4430_ACTIVE_FBB_SEL_MASK (1 << 2) +#define OMAP4430_ACTIVE_FBB_SEL_MASK BITFIELD(2, 2) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1 -#define OMAP4430_ACTIVE_RBB_SEL_MASK (1 << 1) +#define OMAP4430_ACTIVE_RBB_SEL_MASK BITFIELD(1, 1) /* Used by PM_ABE_PWRSTCTRL */ #define OMAP4430_AESSMEM_ONSTATE_SHIFT 16 -#define OMAP4430_AESSMEM_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_AESSMEM_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_ABE_PWRSTCTRL */ #define OMAP4430_AESSMEM_RETSTATE_SHIFT 8 -#define OMAP4430_AESSMEM_RETSTATE_MASK (1 << 8) +#define OMAP4430_AESSMEM_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_ABE_PWRSTST */ #define OMAP4430_AESSMEM_STATEST_SHIFT 4 -#define OMAP4430_AESSMEM_STATEST_MASK (0x3 << 4) +#define OMAP4430_AESSMEM_STATEST_MASK BITFIELD(4, 5) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_AIPOFF_SHIFT 8 -#define OMAP4430_AIPOFF_MASK (1 << 8) +#define OMAP4430_AIPOFF_MASK BITFIELD(8, 8) /* Used by PRM_VOLTCTRL */ #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0 -#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) +#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK BITFIELD(0, 1) /* Used by PRM_VOLTCTRL */ #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4 -#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK (0x3 << 4) +#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK BITFIELD(4, 5) /* Used by PRM_VOLTCTRL */ #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2 -#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_BYPS_RA_ERR_SHIFT 25 -#define OMAP4430_BYPS_RA_ERR_MASK (1 << 25) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_BYPS_SA_ERR_SHIFT 24 -#define OMAP4430_BYPS_SA_ERR_MASK (1 << 24) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT 26 -#define OMAP4430_BYPS_TIMEOUT_ERR_MASK (1 << 26) - -/* Used by PRM_RSTST */ -#define OMAP4430_C2C_RST_SHIFT 10 -#define OMAP4430_C2C_RST_MASK (1 << 10) +#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK BITFIELD(2, 3) /* Used by PM_CAM_PWRSTCTRL */ #define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_CAM_MEM_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_CAM_MEM_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_CAM_PWRSTST */ #define OMAP4430_CAM_MEM_STATEST_SHIFT 4 -#define OMAP4430_CAM_MEM_STATEST_MASK (0x3 << 4) +#define OMAP4430_CAM_MEM_STATEST_MASK BITFIELD(4, 5) /* Used by PRM_CLKREQCTRL */ #define OMAP4430_CLKREQ_COND_SHIFT 0 -#define OMAP4430_CLKREQ_COND_MASK (0x7 << 0) +#define OMAP4430_CLKREQ_COND_MASK BITFIELD(0, 2) /* Used by PRM_VC_VAL_SMPS_RA_CMD */ #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0 -#define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) +#define OMAP4430_CMDRA_VDD_CORE_L_MASK BITFIELD(0, 7) /* Used by PRM_VC_VAL_SMPS_RA_CMD */ #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8 -#define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) +#define OMAP4430_CMDRA_VDD_IVA_L_MASK BITFIELD(8, 15) /* Used by PRM_VC_VAL_SMPS_RA_CMD */ #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16 -#define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) +#define OMAP4430_CMDRA_VDD_MPU_L_MASK BITFIELD(16, 23) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_CMD_VDD_CORE_L_SHIFT 4 -#define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4) +#define OMAP4430_CMD_VDD_CORE_L_MASK BITFIELD(4, 4) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_CMD_VDD_IVA_L_SHIFT 12 -#define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12) +#define OMAP4430_CMD_VDD_IVA_L_MASK BITFIELD(12, 12) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_CMD_VDD_MPU_L_SHIFT 17 -#define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17) +#define OMAP4430_CMD_VDD_MPU_L_MASK BITFIELD(17, 17) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18 -#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) +#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK BITFIELD(18, 19) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9 -#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9) +#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK BITFIELD(9, 9) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6 -#define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6) +#define OMAP4430_CORE_OCMRAM_STATEST_MASK BITFIELD(6, 7) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8 -#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) +#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4 -#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) - -/* Used by REVISION_PRM */ -#define OMAP4430_CUSTOM_SHIFT 6 -#define OMAP4430_CUSTOM_MASK (0x3 << 6) +#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK BITFIELD(4, 5) /* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_DATA_SHIFT 16 -#define OMAP4430_DATA_MASK (0xff << 16) +#define OMAP4430_DATA_MASK BITFIELD(16, 23) /* Used by PRM_DEVICE_OFF_CTRL */ #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0 -#define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0) +#define OMAP4430_DEVICE_OFF_ENABLE_MASK BITFIELD(0, 0) /* Used by PRM_VC_CFG_I2C_MODE */ #define OMAP4430_DFILTEREN_SHIFT 6 -#define OMAP4430_DFILTEREN_MASK (1 << 6) +#define OMAP4430_DFILTEREN_MASK BITFIELD(6, 6) -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP - */ -#define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0 -#define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ +/* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4 -#define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4) +#define OMAP4430_DPLL_ABE_RECAL_EN_MASK BITFIELD(4, 4) -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ +/* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4 -#define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4) +#define OMAP4430_DPLL_ABE_RECAL_ST_MASK BITFIELD(4, 4) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0 -#define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0) +#define OMAP4430_DPLL_CORE_RECAL_EN_MASK BITFIELD(0, 0) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0 -#define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0) +#define OMAP4430_DPLL_CORE_RECAL_ST_MASK BITFIELD(0, 0) /* Used by PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6 -#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6) +#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK BITFIELD(6, 6) /* Used by PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6 -#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6) +#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK BITFIELD(6, 6) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2 -#define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2) +#define OMAP4430_DPLL_IVA_RECAL_EN_MASK BITFIELD(2, 2) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2 -#define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2) +#define OMAP4430_DPLL_IVA_RECAL_ST_MASK BITFIELD(2, 2) /* Used by PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1 -#define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1) +#define OMAP4430_DPLL_MPU_RECAL_EN_MASK BITFIELD(1, 1) /* Used by PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1 -#define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1) +#define OMAP4430_DPLL_MPU_RECAL_ST_MASK BITFIELD(1, 1) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3 -#define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3) +#define OMAP4430_DPLL_PER_RECAL_EN_MASK BITFIELD(3, 3) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3 -#define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3) +#define OMAP4430_DPLL_PER_RECAL_ST_MASK BITFIELD(3, 3) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7 -#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7) +#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK BITFIELD(7, 7) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7 -#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7) +#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK BITFIELD(7, 7) + +/* Used by PRM_IRQENABLE_MPU */ +#define OMAP4430_DPLL_USB_RECAL_EN_SHIFT 5 +#define OMAP4430_DPLL_USB_RECAL_EN_MASK BITFIELD(5, 5) + +/* Used by PRM_IRQSTATUS_MPU */ +#define OMAP4430_DPLL_USB_RECAL_ST_SHIFT 5 +#define OMAP4430_DPLL_USB_RECAL_ST_MASK BITFIELD(5, 5) /* Used by PM_DSS_PWRSTCTRL */ #define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_DSS_MEM_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_DSS_PWRSTCTRL */ #define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8 -#define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8) +#define OMAP4430_DSS_MEM_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_DSS_PWRSTST */ #define OMAP4430_DSS_MEM_STATEST_SHIFT 4 -#define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4) +#define OMAP4430_DSS_MEM_STATEST_MASK BITFIELD(4, 5) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20 -#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20) +#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK BITFIELD(20, 21) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10 -#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10) +#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK BITFIELD(10, 10) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8 -#define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8) +#define OMAP4430_DUCATI_L2RAM_STATEST_MASK BITFIELD(8, 9) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22 -#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22) +#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK BITFIELD(22, 23) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11 -#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11) +#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK BITFIELD(11, 11) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 -#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10) +#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK BITFIELD(10, 11) /* Used by RM_MPU_RSTST */ #define OMAP4430_EMULATION_RST_SHIFT 0 -#define OMAP4430_EMULATION_RST_MASK (1 << 0) +#define OMAP4430_EMULATION_RST_MASK BITFIELD(0, 0) /* Used by RM_DUCATI_RSTST */ #define OMAP4430_EMULATION_RST1ST_SHIFT 3 -#define OMAP4430_EMULATION_RST1ST_MASK (1 << 3) +#define OMAP4430_EMULATION_RST1ST_MASK BITFIELD(3, 3) /* Used by RM_DUCATI_RSTST */ #define OMAP4430_EMULATION_RST2ST_SHIFT 4 -#define OMAP4430_EMULATION_RST2ST_MASK (1 << 4) +#define OMAP4430_EMULATION_RST2ST_MASK BITFIELD(4, 4) /* Used by RM_IVAHD_RSTST */ #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3 -#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3) +#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK BITFIELD(3, 3) /* Used by RM_IVAHD_RSTST */ #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4 -#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4) +#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK BITFIELD(4, 4) /* Used by PM_EMU_PWRSTCTRL */ #define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_EMU_BANK_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_EMU_PWRSTST */ #define OMAP4430_EMU_BANK_STATEST_SHIFT 4 -#define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4) +#define OMAP4430_EMU_BANK_STATEST_MASK BITFIELD(4, 5) + +/* + * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, + * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP + */ +#define OMAP4430_ENABLE_RTA_EXPORT_SHIFT 0 +#define OMAP4430_ENABLE_RTA_EXPORT_MASK BITFIELD(0, 0) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ -#define OMAP4430_ENFUNC1_EXPORT_SHIFT 3 -#define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3) +#define OMAP4430_ENFUNC1_SHIFT 3 +#define OMAP4430_ENFUNC1_MASK BITFIELD(3, 3) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ -#define OMAP4430_ENFUNC3_EXPORT_SHIFT 5 -#define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5) +#define OMAP4430_ENFUNC3_SHIFT 5 +#define OMAP4430_ENFUNC3_MASK BITFIELD(5, 5) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_ENFUNC4_SHIFT 6 -#define OMAP4430_ENFUNC4_MASK (1 << 6) +#define OMAP4430_ENFUNC4_MASK BITFIELD(6, 6) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_ENFUNC5_SHIFT 7 -#define OMAP4430_ENFUNC5_MASK (1 << 7) +#define OMAP4430_ENFUNC5_MASK BITFIELD(7, 7) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_ERRORGAIN_SHIFT 16 -#define OMAP4430_ERRORGAIN_MASK (0xff << 16) +#define OMAP4430_ERRORGAIN_MASK BITFIELD(16, 23) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_ERROROFFSET_SHIFT 24 -#define OMAP4430_ERROROFFSET_MASK (0xff << 24) +#define OMAP4430_ERROROFFSET_MASK BITFIELD(24, 31) /* Used by PRM_RSTST */ #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 -#define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5) +#define OMAP4430_EXTERNAL_WARM_RST_MASK BITFIELD(5, 5) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_FORCEUPDATE_SHIFT 1 -#define OMAP4430_FORCEUPDATE_MASK (1 << 1) +#define OMAP4430_FORCEUPDATE_MASK BITFIELD(1, 1) /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ #define OMAP4430_FORCEUPDATEWAIT_SHIFT 8 -#define OMAP4430_FORCEUPDATEWAIT_MASK (0xffffff << 8) +#define OMAP4430_FORCEUPDATEWAIT_MASK BITFIELD(8, 31) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ #define OMAP4430_FORCEWKUP_EN_SHIFT 10 -#define OMAP4430_FORCEWKUP_EN_MASK (1 << 10) +#define OMAP4430_FORCEWKUP_EN_MASK BITFIELD(10, 10) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ #define OMAP4430_FORCEWKUP_ST_SHIFT 10 -#define OMAP4430_FORCEWKUP_ST_MASK (1 << 10) - -/* Used by REVISION_PRM */ -#define OMAP4430_FUNC_SHIFT 16 -#define OMAP4430_FUNC_MASK (0xfff << 16) +#define OMAP4430_FORCEWKUP_ST_MASK BITFIELD(10, 10) /* Used by PM_GFX_PWRSTCTRL */ #define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_GFX_MEM_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_GFX_MEM_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_GFX_PWRSTST */ #define OMAP4430_GFX_MEM_STATEST_SHIFT 4 -#define OMAP4430_GFX_MEM_STATEST_MASK (0x3 << 4) +#define OMAP4430_GFX_MEM_STATEST_MASK BITFIELD(4, 5) /* Used by PRM_RSTST */ #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 -#define OMAP4430_GLOBAL_COLD_RST_MASK (1 << 0) +#define OMAP4430_GLOBAL_COLD_RST_MASK BITFIELD(0, 0) /* Used by PRM_RSTST */ #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 -#define OMAP4430_GLOBAL_WARM_SW_RST_MASK (1 << 1) +#define OMAP4430_GLOBAL_WARM_SW_RST_MASK BITFIELD(1, 1) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_GLOBAL_WUEN_SHIFT 16 -#define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) +#define OMAP4430_GLOBAL_WUEN_MASK BITFIELD(16, 16) /* Used by PRM_VC_CFG_I2C_MODE */ #define OMAP4430_HSMCODE_SHIFT 0 -#define OMAP4430_HSMCODE_MASK (0x7 << 0) +#define OMAP4430_HSMCODE_MASK BITFIELD(0, 2) /* Used by PRM_VC_CFG_I2C_MODE */ #define OMAP4430_HSMODEEN_SHIFT 3 -#define OMAP4430_HSMODEEN_MASK (1 << 3) +#define OMAP4430_HSMODEEN_MASK BITFIELD(3, 3) /* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_HSSCLH_SHIFT 16 -#define OMAP4430_HSSCLH_MASK (0xff << 16) +#define OMAP4430_HSSCLH_MASK BITFIELD(16, 23) /* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_HSSCLL_SHIFT 24 -#define OMAP4430_HSSCLL_MASK (0xff << 24) +#define OMAP4430_HSSCLL_MASK BITFIELD(24, 31) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_HWA_MEM_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_HWA_MEM_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8 -#define OMAP4430_HWA_MEM_RETSTATE_MASK (1 << 8) +#define OMAP4430_HWA_MEM_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_IVAHD_PWRSTST */ #define OMAP4430_HWA_MEM_STATEST_SHIFT 4 -#define OMAP4430_HWA_MEM_STATEST_MASK (0x3 << 4) +#define OMAP4430_HWA_MEM_STATEST_MASK BITFIELD(4, 5) /* Used by RM_MPU_RSTST */ #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1 -#define OMAP4430_ICECRUSHER_MPU_RST_MASK (1 << 1) +#define OMAP4430_ICECRUSHER_MPU_RST_MASK BITFIELD(1, 1) /* Used by RM_DUCATI_RSTST */ #define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5 -#define OMAP4430_ICECRUSHER_RST1ST_MASK (1 << 5) +#define OMAP4430_ICECRUSHER_RST1ST_MASK BITFIELD(5, 5) /* Used by RM_DUCATI_RSTST */ #define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6 -#define OMAP4430_ICECRUSHER_RST2ST_MASK (1 << 6) +#define OMAP4430_ICECRUSHER_RST2ST_MASK BITFIELD(6, 6) /* Used by RM_IVAHD_RSTST */ #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5 -#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK (1 << 5) +#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK BITFIELD(5, 5) /* Used by RM_IVAHD_RSTST */ #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6 -#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK (1 << 6) +#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK BITFIELD(6, 6) /* Used by PRM_RSTST */ #define OMAP4430_ICEPICK_RST_SHIFT 9 -#define OMAP4430_ICEPICK_RST_MASK (1 << 9) +#define OMAP4430_ICEPICK_RST_MASK BITFIELD(9, 9) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_INITVDD_SHIFT 2 -#define OMAP4430_INITVDD_MASK (1 << 2) +#define OMAP4430_INITVDD_MASK BITFIELD(2, 2) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_INITVOLTAGE_SHIFT 8 -#define OMAP4430_INITVOLTAGE_MASK (0xff << 8) +#define OMAP4430_INITVOLTAGE_MASK BITFIELD(8, 15) /* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, - * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, - * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST + * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, + * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, + * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST */ #define OMAP4430_INTRANSITION_SHIFT 20 -#define OMAP4430_INTRANSITION_MASK (1 << 20) +#define OMAP4430_INTRANSITION_MASK BITFIELD(20, 20) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_IO_EN_SHIFT 9 -#define OMAP4430_IO_EN_MASK (1 << 9) +#define OMAP4430_IO_EN_MASK BITFIELD(9, 9) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_IO_ON_STATUS_SHIFT 5 -#define OMAP4430_IO_ON_STATUS_MASK (1 << 5) +#define OMAP4430_IO_ON_STATUS_MASK BITFIELD(5, 5) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_IO_ST_SHIFT 9 -#define OMAP4430_IO_ST_MASK (1 << 9) +#define OMAP4430_IO_ST_MASK BITFIELD(9, 9) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0 -#define OMAP4430_ISOCLK_OVERRIDE_MASK (1 << 0) +#define OMAP4430_ISOCLK_OVERRIDE_MASK BITFIELD(0, 0) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_ISOCLK_STATUS_SHIFT 1 -#define OMAP4430_ISOCLK_STATUS_MASK (1 << 1) +#define OMAP4430_ISOCLK_STATUS_MASK BITFIELD(1, 1) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_ISOOVR_EXTEND_SHIFT 4 -#define OMAP4430_ISOOVR_EXTEND_MASK (1 << 4) +#define OMAP4430_ISOOVR_EXTEND_MASK BITFIELD(4, 4) /* Used by PRM_IO_COUNT */ #define OMAP4430_ISO_2_ON_TIME_SHIFT 0 -#define OMAP4430_ISO_2_ON_TIME_MASK (0xff << 0) +#define OMAP4430_ISO_2_ON_TIME_MASK BITFIELD(0, 7) /* Used by PM_L3INIT_PWRSTCTRL */ #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16 -#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_L3INIT_PWRSTCTRL */ #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8 -#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK (1 << 8) +#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_L3INIT_PWRSTST */ #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4 -#define OMAP4430_L3INIT_BANK1_STATEST_MASK (0x3 << 4) - -/* - * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST, - * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST - */ -#define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 -#define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) +#define OMAP4430_L3INIT_BANK1_STATEST_MASK BITFIELD(4, 5) /* - * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, - * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, - * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL + * Used by PM_CORE_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, + * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, + * PM_IVAHD_PWRSTCTRL */ #define OMAP4430_LOGICRETSTATE_SHIFT 2 -#define OMAP4430_LOGICRETSTATE_MASK (1 << 2) +#define OMAP4430_LOGICRETSTATE_MASK BITFIELD(2, 2) /* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, - * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, - * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST + * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, + * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, + * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST */ #define OMAP4430_LOGICSTATEST_SHIFT 2 -#define OMAP4430_LOGICSTATEST_MASK (1 << 2) +#define OMAP4430_LOGICSTATEST_MASK BITFIELD(2, 2) /* - * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, - * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, - * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, - * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, - * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT, - * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT, - * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT, - * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, - * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT, - * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, + * Used by RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, + * RM_WKUP_L4WKUP_CONTEXT, RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, + * RM_WKUP_SYNCTIMER_CONTEXT, RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, + * RM_WKUP_USIM_CONTEXT, RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT, + * RM_EMU_DEBUGSS_CONTEXT, RM_D2D_SAD2D_CONTEXT, RM_D2D_SAD2D_FW_CONTEXT, + * RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, + * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_OCP_WP1_CONTEXT, + * RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, RM_L3_2_OCMC_RAM_CONTEXT, + * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, RM_MEMIF_DLL_CONTEXT, + * RM_MEMIF_DLL_H_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, + * RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, - * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT, - * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, - * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, - * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT, - * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT, - * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT, - * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, - * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT, - * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT, - * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT, - * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT, - * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT, - * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT, - * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, - * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT, - * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, - * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT, - * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT, - * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT, - * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT, - * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT + * RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, + * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, + * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, + * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, + * RM_ABE_WDT3_CONTEXT, RM_GFX_GFX_CONTEXT, RM_MPU_MPU_CONTEXT, + * RM_CEFUSE_CEFUSE_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, + * RM_ALWON_SR_CORE_CONTEXT, RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, + * RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, RM_L4PER_ADC_CONTEXT, + * RM_L4PER_DMTIMER10_CONTEXT, RM_L4PER_DMTIMER11_CONTEXT, + * RM_L4PER_DMTIMER2_CONTEXT, RM_L4PER_DMTIMER3_CONTEXT, + * RM_L4PER_DMTIMER4_CONTEXT, RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, + * RM_L4PER_HDQ1W_CONTEXT, RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, + * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, + * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, + * RM_L4PER_MCASP3_CONTEXT, RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, + * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, + * RM_L4PER_MGATE_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, + * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_MSPROHG_CONTEXT, + * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT, + * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT */ #define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0 -#define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) +#define OMAP4430_LOSTCONTEXT_DFF_MASK BITFIELD(0, 0) /* * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT, - * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, - * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, - * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT, - * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT, - * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, + * RM_D2D_SAD2D_FW_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT, * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, - * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, - * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, - * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, - * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, - * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, - * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, - * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, - * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, - * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT + * RM_L4CFG_MAILBOX_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, + * RM_MEMIF_EMIF_2_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, + * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_L3INIT_HSI_CONTEXT, + * RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_MMC6_CONTEXT, + * RM_L3INIT_USB_HOST_CONTEXT, RM_L3INIT_USB_HOST_FS_CONTEXT, + * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_USB_TLL_CONTEXT, RM_DSS_DSS_CONTEXT, + * RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, RM_L4PER_GPIO4_CONTEXT, + * RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, RM_L4PER_I2C1_CONTEXT, + * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, + * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4SEC_AES1_CONTEXT, + * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT, + * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT */ #define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1 -#define OMAP4430_LOSTCONTEXT_RFF_MASK (1 << 1) +#define OMAP4430_LOSTCONTEXT_RFF_MASK BITFIELD(1, 1) /* Used by RM_ABE_AESS_CONTEXT */ #define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8 -#define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) +#define OMAP4430_LOSTMEM_AESSMEM_MASK BITFIELD(8, 8) /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_CAM_MEM_MASK (1 << 8) +#define OMAP4430_LOSTMEM_CAM_MEM_MASK BITFIELD(8, 8) /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8) +#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK BITFIELD(8, 8) /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9 -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK (1 << 9) +#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK BITFIELD(9, 9) /* Used by RM_L3_2_OCMC_RAM_CONTEXT */ #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) +#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK BITFIELD(8, 8) /* * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, * RM_SDMA_SDMA_CONTEXT */ #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) +#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK BITFIELD(8, 8) /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_DSS_MEM_MASK (1 << 8) +#define OMAP4430_LOSTMEM_DSS_MEM_MASK BITFIELD(8, 8) /* Used by RM_DUCATI_DUCATI_CONTEXT */ #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9 -#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK (1 << 9) +#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK BITFIELD(9, 9) /* Used by RM_DUCATI_DUCATI_CONTEXT */ #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8 -#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK (1 << 8) +#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK BITFIELD(8, 8) /* Used by RM_EMU_DEBUGSS_CONTEXT */ #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_EMU_BANK_MASK (1 << 8) +#define OMAP4430_LOSTMEM_EMU_BANK_MASK BITFIELD(8, 8) /* Used by RM_GFX_GFX_CONTEXT */ #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_GFX_MEM_MASK (1 << 8) +#define OMAP4430_LOSTMEM_GFX_MEM_MASK BITFIELD(8, 8) /* Used by RM_IVAHD_IVAHD_CONTEXT */ #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10 -#define OMAP4430_LOSTMEM_HWA_MEM_MASK (1 << 10) +#define OMAP4430_LOSTMEM_HWA_MEM_MASK BITFIELD(10, 10) /* * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT, @@ -644,19 +620,19 @@ * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT */ #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8 -#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) +#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK BITFIELD(8, 8) /* Used by RM_MPU_MPU_CONTEXT */ #define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8 -#define OMAP4430_LOSTMEM_MPU_L1_MASK (1 << 8) +#define OMAP4430_LOSTMEM_MPU_L1_MASK BITFIELD(8, 8) /* Used by RM_MPU_MPU_CONTEXT */ #define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9 -#define OMAP4430_LOSTMEM_MPU_L2_MASK (1 << 9) +#define OMAP4430_LOSTMEM_MPU_L2_MASK BITFIELD(9, 9) /* Used by RM_MPU_MPU_CONTEXT */ #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10 -#define OMAP4430_LOSTMEM_MPU_RAM_MASK (1 << 10) +#define OMAP4430_LOSTMEM_MPU_RAM_MASK BITFIELD(10, 10) /* * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, @@ -664,14 +640,14 @@ * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT */ #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) +#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK BITFIELD(8, 8) /* * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT */ #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8 -#define OMAP4430_LOSTMEM_PERIHPMEM_MASK (1 << 8) +#define OMAP4430_LOSTMEM_PERIHPMEM_MASK BITFIELD(8, 8) /* * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT, @@ -679,237 +655,245 @@ * RM_L4SEC_CRYPTODMA_CONTEXT */ #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK (1 << 8) +#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK BITFIELD(8, 8) /* Used by RM_IVAHD_SL2_CONTEXT */ #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_SL2_MEM_MASK (1 << 8) +#define OMAP4430_LOSTMEM_SL2_MEM_MASK BITFIELD(8, 8) /* Used by RM_IVAHD_IVAHD_CONTEXT */ #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_TCM1_MEM_MASK (1 << 8) +#define OMAP4430_LOSTMEM_TCM1_MEM_MASK BITFIELD(8, 8) /* Used by RM_IVAHD_IVAHD_CONTEXT */ #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9 -#define OMAP4430_LOSTMEM_TCM2_MEM_MASK (1 << 9) +#define OMAP4430_LOSTMEM_TCM2_MEM_MASK BITFIELD(9, 9) /* Used by RM_TESLA_TESLA_CONTEXT */ #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10 -#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK (1 << 10) +#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK BITFIELD(10, 10) /* Used by RM_TESLA_TESLA_CONTEXT */ #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8 -#define OMAP4430_LOSTMEM_TESLA_L1_MASK (1 << 8) +#define OMAP4430_LOSTMEM_TESLA_L1_MASK BITFIELD(8, 8) /* Used by RM_TESLA_TESLA_CONTEXT */ #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9 -#define OMAP4430_LOSTMEM_TESLA_L2_MASK (1 << 9) +#define OMAP4430_LOSTMEM_TESLA_L2_MASK BITFIELD(9, 9) /* Used by RM_WKUP_SARRAM_CONTEXT */ #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_WKUP_BANK_MASK (1 << 8) +#define OMAP4430_LOSTMEM_WKUP_BANK_MASK BITFIELD(8, 8) /* - * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, - * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL, - * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL + * Used by PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, + * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, + * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL */ #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 -#define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) +#define OMAP4430_LOWPOWERSTATECHANGE_MASK BITFIELD(4, 4) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP4430_MEMORYCHANGE_SHIFT 3 +#define OMAP4430_MEMORYCHANGE_MASK BITFIELD(3, 3) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_MODEM_READY_SHIFT 1 -#define OMAP4430_MODEM_READY_MASK (1 << 1) +#define OMAP4430_MODEM_READY_MASK BITFIELD(1, 1) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9 -#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) +#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK BITFIELD(9, 9) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_MODEM_SLEEP_ST_SHIFT 16 -#define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16) +#define OMAP4430_MODEM_SLEEP_ST_MASK BITFIELD(16, 16) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8 -#define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8) +#define OMAP4430_MODEM_WAKE_IRQ_MASK BITFIELD(8, 8) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_L1_ONSTATE_SHIFT 16 -#define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_MPU_L1_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_L1_RETSTATE_SHIFT 8 -#define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8) +#define OMAP4430_MPU_L1_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_MPU_PWRSTST */ #define OMAP4430_MPU_L1_STATEST_SHIFT 4 -#define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4) +#define OMAP4430_MPU_L1_STATEST_MASK BITFIELD(4, 5) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_L2_ONSTATE_SHIFT 18 -#define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18) +#define OMAP4430_MPU_L2_ONSTATE_MASK BITFIELD(18, 19) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_L2_RETSTATE_SHIFT 9 -#define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9) +#define OMAP4430_MPU_L2_RETSTATE_MASK BITFIELD(9, 9) /* Used by PM_MPU_PWRSTST */ #define OMAP4430_MPU_L2_STATEST_SHIFT 6 -#define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6) +#define OMAP4430_MPU_L2_STATEST_MASK BITFIELD(6, 7) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20 -#define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20) +#define OMAP4430_MPU_RAM_ONSTATE_MASK BITFIELD(20, 21) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10 -#define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10) +#define OMAP4430_MPU_RAM_RETSTATE_MASK BITFIELD(10, 10) /* Used by PM_MPU_PWRSTST */ #define OMAP4430_MPU_RAM_STATEST_SHIFT 8 -#define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8) +#define OMAP4430_MPU_RAM_STATEST_MASK BITFIELD(8, 9) /* Used by PRM_RSTST */ #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 -#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2) +#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK BITFIELD(2, 2) /* Used by PRM_RSTST */ #define OMAP4430_MPU_WDT_RST_SHIFT 3 -#define OMAP4430_MPU_WDT_RST_MASK (1 << 3) +#define OMAP4430_MPU_WDT_RST_MASK BITFIELD(3, 3) /* Used by PM_L4PER_PWRSTCTRL */ #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18 -#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18) +#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK BITFIELD(18, 19) /* Used by PM_L4PER_PWRSTCTRL */ #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9 -#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9) +#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK BITFIELD(9, 9) /* Used by PM_L4PER_PWRSTST */ #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6 -#define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6) +#define OMAP4430_NONRETAINED_BANK_STATEST_MASK BITFIELD(6, 7) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24 -#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) +#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK BITFIELD(24, 25) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12 -#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) +#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK BITFIELD(12, 12) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12 -#define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) +#define OMAP4430_OCP_NRET_BANK_STATEST_MASK BITFIELD(12, 13) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ #define OMAP4430_OFF_SHIFT 0 -#define OMAP4430_OFF_MASK (0xff << 0) +#define OMAP4430_OFF_MASK BITFIELD(0, 7) + +/* Used by PRM_LDO_BANDGAP_CTRL */ +#define OMAP4430_OFF_ENABLE_SHIFT 0 +#define OMAP4430_OFF_ENABLE_MASK BITFIELD(0, 0) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ #define OMAP4430_ON_SHIFT 24 -#define OMAP4430_ON_MASK (0xff << 24) +#define OMAP4430_ON_MASK BITFIELD(24, 31) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ #define OMAP4430_ONLP_SHIFT 16 -#define OMAP4430_ONLP_MASK (0xff << 16) +#define OMAP4430_ONLP_MASK BITFIELD(16, 23) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ #define OMAP4430_OPP_CHANGE_SHIFT 2 -#define OMAP4430_OPP_CHANGE_MASK (1 << 2) +#define OMAP4430_OPP_CHANGE_MASK BITFIELD(2, 2) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ #define OMAP4430_OPP_SEL_SHIFT 0 -#define OMAP4430_OPP_SEL_MASK (0x3 << 0) +#define OMAP4430_OPP_SEL_MASK BITFIELD(0, 1) /* Used by PRM_SRAM_COUNT */ #define OMAP4430_PCHARGECNT_VALUE_SHIFT 0 -#define OMAP4430_PCHARGECNT_VALUE_MASK (0x3f << 0) +#define OMAP4430_PCHARGECNT_VALUE_MASK BITFIELD(0, 5) /* Used by PRM_PSCON_COUNT */ #define OMAP4430_PCHARGE_TIME_SHIFT 0 -#define OMAP4430_PCHARGE_TIME_MASK (0xff << 0) +#define OMAP4430_PCHARGE_TIME_MASK BITFIELD(0, 7) /* Used by PM_ABE_PWRSTCTRL */ #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20 -#define OMAP4430_PERIPHMEM_ONSTATE_MASK (0x3 << 20) +#define OMAP4430_PERIPHMEM_ONSTATE_MASK BITFIELD(20, 21) /* Used by PM_ABE_PWRSTCTRL */ #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10 -#define OMAP4430_PERIPHMEM_RETSTATE_MASK (1 << 10) +#define OMAP4430_PERIPHMEM_RETSTATE_MASK BITFIELD(10, 10) /* Used by PM_ABE_PWRSTST */ #define OMAP4430_PERIPHMEM_STATEST_SHIFT 8 -#define OMAP4430_PERIPHMEM_STATEST_MASK (0x3 << 8) +#define OMAP4430_PERIPHMEM_STATEST_MASK BITFIELD(8, 9) /* Used by PRM_PHASE1_CNDP */ #define OMAP4430_PHASE1_CNDP_SHIFT 0 -#define OMAP4430_PHASE1_CNDP_MASK (0xffffffff << 0) +#define OMAP4430_PHASE1_CNDP_MASK BITFIELD(0, 31) /* Used by PRM_PHASE2A_CNDP */ #define OMAP4430_PHASE2A_CNDP_SHIFT 0 -#define OMAP4430_PHASE2A_CNDP_MASK (0xffffffff << 0) +#define OMAP4430_PHASE2A_CNDP_MASK BITFIELD(0, 31) /* Used by PRM_PHASE2B_CNDP */ #define OMAP4430_PHASE2B_CNDP_SHIFT 0 -#define OMAP4430_PHASE2B_CNDP_MASK (0xffffffff << 0) +#define OMAP4430_PHASE2B_CNDP_MASK BITFIELD(0, 31) /* Used by PRM_PSCON_COUNT */ #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8 -#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) +#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK BITFIELD(8, 15) /* - * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, - * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL, - * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, - * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL + * Used by PM_EMU_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, + * PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, + * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, + * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL */ #define OMAP4430_POWERSTATE_SHIFT 0 -#define OMAP4430_POWERSTATE_MASK (0x3 << 0) +#define OMAP4430_POWERSTATE_MASK BITFIELD(0, 1) /* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, - * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, - * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST + * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, + * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, + * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST */ #define OMAP4430_POWERSTATEST_SHIFT 0 -#define OMAP4430_POWERSTATEST_MASK (0x3 << 0) +#define OMAP4430_POWERSTATEST_MASK BITFIELD(0, 1) /* Used by PRM_PWRREQCTRL */ #define OMAP4430_PWRREQ_COND_SHIFT 0 -#define OMAP4430_PWRREQ_COND_MASK (0x3 << 0) +#define OMAP4430_PWRREQ_COND_MASK BITFIELD(0, 1) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3 -#define OMAP4430_RACEN_VDD_CORE_L_MASK (1 << 3) +#define OMAP4430_RACEN_VDD_CORE_L_MASK BITFIELD(3, 3) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11 -#define OMAP4430_RACEN_VDD_IVA_L_MASK (1 << 11) +#define OMAP4430_RACEN_VDD_IVA_L_MASK BITFIELD(11, 11) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20 -#define OMAP4430_RACEN_VDD_MPU_L_MASK (1 << 20) +#define OMAP4430_RACEN_VDD_MPU_L_MASK BITFIELD(20, 20) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAC_VDD_CORE_L_SHIFT 2 -#define OMAP4430_RAC_VDD_CORE_L_MASK (1 << 2) +#define OMAP4430_RAC_VDD_CORE_L_MASK BITFIELD(2, 2) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAC_VDD_IVA_L_SHIFT 10 -#define OMAP4430_RAC_VDD_IVA_L_MASK (1 << 10) +#define OMAP4430_RAC_VDD_IVA_L_MASK BITFIELD(10, 10) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAC_VDD_MPU_L_SHIFT 19 -#define OMAP4430_RAC_VDD_MPU_L_MASK (1 << 19) +#define OMAP4430_RAC_VDD_MPU_L_MASK BITFIELD(19, 19) /* * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, @@ -917,7 +901,7 @@ * PRM_VOLTSETUP_MPU_RET_SLEEP */ #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 -#define OMAP4430_RAMP_DOWN_COUNT_MASK (0x3f << 16) +#define OMAP4430_RAMP_DOWN_COUNT_MASK BITFIELD(16, 21) /* * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, @@ -925,7 +909,7 @@ * PRM_VOLTSETUP_MPU_RET_SLEEP */ #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24 -#define OMAP4430_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) +#define OMAP4430_RAMP_DOWN_PRESCAL_MASK BITFIELD(24, 25) /* * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, @@ -933,7 +917,7 @@ * PRM_VOLTSETUP_MPU_RET_SLEEP */ #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 -#define OMAP4430_RAMP_UP_COUNT_MASK (0x3f << 0) +#define OMAP4430_RAMP_UP_COUNT_MASK BITFIELD(0, 5) /* * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, @@ -941,1381 +925,1281 @@ * PRM_VOLTSETUP_MPU_RET_SLEEP */ #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 -#define OMAP4430_RAMP_UP_PRESCAL_MASK (0x3 << 8) +#define OMAP4430_RAMP_UP_PRESCAL_MASK BITFIELD(8, 9) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAV_VDD_CORE_L_SHIFT 1 -#define OMAP4430_RAV_VDD_CORE_L_MASK (1 << 1) +#define OMAP4430_RAV_VDD_CORE_L_MASK BITFIELD(1, 1) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAV_VDD_IVA_L_SHIFT 9 -#define OMAP4430_RAV_VDD_IVA_L_MASK (1 << 9) +#define OMAP4430_RAV_VDD_IVA_L_MASK BITFIELD(9, 9) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAV_VDD_MPU_L_SHIFT 18 -#define OMAP4430_RAV_VDD_MPU_L_MASK (1 << 18) +#define OMAP4430_RAV_VDD_MPU_L_MASK BITFIELD(18, 18) /* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_REGADDR_SHIFT 8 -#define OMAP4430_REGADDR_MASK (0xff << 8) +#define OMAP4430_REGADDR_MASK BITFIELD(8, 15) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ #define OMAP4430_RET_SHIFT 8 -#define OMAP4430_RET_MASK (0xff << 8) +#define OMAP4430_RET_MASK BITFIELD(8, 15) /* Used by PM_L4PER_PWRSTCTRL */ #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_RETAINED_BANK_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_RETAINED_BANK_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_L4PER_PWRSTCTRL */ #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8 -#define OMAP4430_RETAINED_BANK_RETSTATE_MASK (1 << 8) +#define OMAP4430_RETAINED_BANK_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_L4PER_PWRSTST */ #define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4 -#define OMAP4430_RETAINED_BANK_STATEST_MASK (0x3 << 4) +#define OMAP4430_RETAINED_BANK_STATEST_MASK BITFIELD(4, 5) /* * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, * PRM_LDO_SRAM_MPU_CTRL */ #define OMAP4430_RETMODE_ENABLE_SHIFT 0 -#define OMAP4430_RETMODE_ENABLE_MASK (1 << 0) +#define OMAP4430_RETMODE_ENABLE_MASK BITFIELD(0, 0) -/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ +/* Used by REVISION_PRM */ +#define OMAP4430_REV_SHIFT 0 +#define OMAP4430_REV_MASK BITFIELD(0, 7) + +/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ #define OMAP4430_RST1_SHIFT 0 -#define OMAP4430_RST1_MASK (1 << 0) +#define OMAP4430_RST1_MASK BITFIELD(0, 0) -/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ +/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ #define OMAP4430_RST1ST_SHIFT 0 -#define OMAP4430_RST1ST_MASK (1 << 0) +#define OMAP4430_RST1ST_MASK BITFIELD(0, 0) -/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ +/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ #define OMAP4430_RST2_SHIFT 1 -#define OMAP4430_RST2_MASK (1 << 1) +#define OMAP4430_RST2_MASK BITFIELD(1, 1) -/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ +/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ #define OMAP4430_RST2ST_SHIFT 1 -#define OMAP4430_RST2ST_MASK (1 << 1) +#define OMAP4430_RST2ST_MASK BITFIELD(1, 1) /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ #define OMAP4430_RST3_SHIFT 2 -#define OMAP4430_RST3_MASK (1 << 2) +#define OMAP4430_RST3_MASK BITFIELD(2, 2) /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ #define OMAP4430_RST3ST_SHIFT 2 -#define OMAP4430_RST3ST_MASK (1 << 2) +#define OMAP4430_RST3ST_MASK BITFIELD(2, 2) /* Used by PRM_RSTTIME */ #define OMAP4430_RSTTIME1_SHIFT 0 -#define OMAP4430_RSTTIME1_MASK (0x3ff << 0) +#define OMAP4430_RSTTIME1_MASK BITFIELD(0, 9) /* Used by PRM_RSTTIME */ #define OMAP4430_RSTTIME2_SHIFT 10 -#define OMAP4430_RSTTIME2_MASK (0x1f << 10) +#define OMAP4430_RSTTIME2_MASK BITFIELD(10, 14) /* Used by PRM_RSTCTRL */ #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1 -#define OMAP4430_RST_GLOBAL_COLD_SW_MASK (1 << 1) +#define OMAP4430_RST_GLOBAL_COLD_SW_MASK BITFIELD(1, 1) /* Used by PRM_RSTCTRL */ #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0 -#define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) - -/* Used by REVISION_PRM */ -#define OMAP4430_R_RTL_SHIFT 11 -#define OMAP4430_R_RTL_MASK (0x1f << 11) +#define OMAP4430_RST_GLOBAL_WARM_SW_MASK BITFIELD(0, 0) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 -#define OMAP4430_SA_VDD_CORE_L_MASK (1 << 0) +#define OMAP4430_SA_VDD_CORE_L_MASK BITFIELD(0, 0) /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0 -#define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) +#define OMAP4430_SA_VDD_CORE_L_0_6_MASK BITFIELD(0, 6) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 -#define OMAP4430_SA_VDD_IVA_L_MASK (1 << 8) +#define OMAP4430_SA_VDD_IVA_L_MASK BITFIELD(8, 8) /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8 -#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) +#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK BITFIELD(8, 14) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 -#define OMAP4430_SA_VDD_MPU_L_MASK (1 << 16) +#define OMAP4430_SA_VDD_MPU_L_MASK BITFIELD(16, 16) /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16 -#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) - -/* Used by REVISION_PRM */ -#define OMAP4430_SCHEME_SHIFT 30 -#define OMAP4430_SCHEME_MASK (0x3 << 30) +#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK BITFIELD(16, 22) /* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_SCLH_SHIFT 0 -#define OMAP4430_SCLH_MASK (0xff << 0) +#define OMAP4430_SCLH_MASK BITFIELD(0, 7) /* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_SCLL_SHIFT 8 -#define OMAP4430_SCLL_MASK (0xff << 8) +#define OMAP4430_SCLL_MASK BITFIELD(8, 15) /* Used by PRM_RSTST */ #define OMAP4430_SECURE_WDT_RST_SHIFT 4 -#define OMAP4430_SECURE_WDT_RST_MASK (1 << 4) +#define OMAP4430_SECURE_WDT_RST_MASK BITFIELD(4, 4) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18 -#define OMAP4430_SL2_MEM_ONSTATE_MASK (0x3 << 18) +#define OMAP4430_SL2_MEM_ONSTATE_MASK BITFIELD(18, 19) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9 -#define OMAP4430_SL2_MEM_RETSTATE_MASK (1 << 9) +#define OMAP4430_SL2_MEM_RETSTATE_MASK BITFIELD(9, 9) /* Used by PM_IVAHD_PWRSTST */ #define OMAP4430_SL2_MEM_STATEST_SHIFT 6 -#define OMAP4430_SL2_MEM_STATEST_MASK (0x3 << 6) +#define OMAP4430_SL2_MEM_STATEST_MASK BITFIELD(6, 7) /* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_SLAVEADDR_SHIFT 0 -#define OMAP4430_SLAVEADDR_MASK (0x7f << 0) +#define OMAP4430_SLAVEADDR_MASK BITFIELD(0, 6) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_SLEEP_RBB_SEL_SHIFT 3 -#define OMAP4430_SLEEP_RBB_SEL_MASK (1 << 3) +#define OMAP4430_SLEEP_RBB_SEL_MASK BITFIELD(3, 3) /* Used by PRM_SRAM_COUNT */ #define OMAP4430_SLPCNT_VALUE_SHIFT 16 -#define OMAP4430_SLPCNT_VALUE_MASK (0xff << 16) +#define OMAP4430_SLPCNT_VALUE_MASK BITFIELD(16, 23) /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 -#define OMAP4430_SMPSWAITTIMEMAX_MASK (0xffff << 8) +#define OMAP4430_SMPSWAITTIMEMAX_MASK BITFIELD(8, 23) /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 -#define OMAP4430_SMPSWAITTIMEMIN_MASK (0xffff << 8) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_RA_ERR_CORE_SHIFT 1 -#define OMAP4430_SMPS_RA_ERR_CORE_MASK (1 << 1) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_RA_ERR_IVA_SHIFT 9 -#define OMAP4430_SMPS_RA_ERR_IVA_MASK (1 << 9) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_RA_ERR_MPU_SHIFT 17 -#define OMAP4430_SMPS_RA_ERR_MPU_MASK (1 << 17) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_SA_ERR_CORE_SHIFT 0 -#define OMAP4430_SMPS_SA_ERR_CORE_MASK (1 << 0) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_SA_ERR_IVA_SHIFT 8 -#define OMAP4430_SMPS_SA_ERR_IVA_MASK (1 << 8) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_SA_ERR_MPU_SHIFT 16 -#define OMAP4430_SMPS_SA_ERR_MPU_MASK (1 << 16) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 -#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT 10 -#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK (1 << 10) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT 18 -#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 18) +#define OMAP4430_SMPSWAITTIMEMIN_MASK BITFIELD(8, 23) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_SR2EN_SHIFT 0 -#define OMAP4430_SR2EN_MASK (1 << 0) +#define OMAP4430_SR2EN_MASK BITFIELD(0, 0) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ #define OMAP4430_SR2_IN_TRANSITION_SHIFT 6 -#define OMAP4430_SR2_IN_TRANSITION_MASK (1 << 6) +#define OMAP4430_SR2_IN_TRANSITION_MASK BITFIELD(6, 6) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ #define OMAP4430_SR2_STATUS_SHIFT 3 -#define OMAP4430_SR2_STATUS_MASK (0x3 << 3) +#define OMAP4430_SR2_STATUS_MASK BITFIELD(3, 4) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8 -#define OMAP4430_SR2_WTCNT_VALUE_MASK (0xff << 8) +#define OMAP4430_SR2_WTCNT_VALUE_MASK BITFIELD(8, 15) /* * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, * PRM_LDO_SRAM_MPU_CTRL */ #define OMAP4430_SRAMLDO_STATUS_SHIFT 8 -#define OMAP4430_SRAMLDO_STATUS_MASK (1 << 8) +#define OMAP4430_SRAMLDO_STATUS_MASK BITFIELD(8, 8) /* * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, * PRM_LDO_SRAM_MPU_CTRL */ #define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9 -#define OMAP4430_SRAM_IN_TRANSITION_MASK (1 << 9) +#define OMAP4430_SRAM_IN_TRANSITION_MASK BITFIELD(9, 9) /* Used by PRM_VC_CFG_I2C_MODE */ #define OMAP4430_SRMODEEN_SHIFT 4 -#define OMAP4430_SRMODEEN_MASK (1 << 4) +#define OMAP4430_SRMODEEN_MASK BITFIELD(4, 4) /* Used by PRM_VOLTSETUP_WARMRESET */ #define OMAP4430_STABLE_COUNT_SHIFT 0 -#define OMAP4430_STABLE_COUNT_MASK (0x3f << 0) +#define OMAP4430_STABLE_COUNT_MASK BITFIELD(0, 5) /* Used by PRM_VOLTSETUP_WARMRESET */ #define OMAP4430_STABLE_PRESCAL_SHIFT 8 -#define OMAP4430_STABLE_PRESCAL_MASK (0x3 << 8) - -/* Used by PRM_LDO_BANDGAP_SETUP */ -#define OMAP4430_STARTUP_COUNT_SHIFT 0 -#define OMAP4430_STARTUP_COUNT_MASK (0xff << 0) - -/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ -#define OMAP4430_STARTUP_COUNT_24_31_SHIFT 24 -#define OMAP4430_STARTUP_COUNT_24_31_MASK (0xff << 24) +#define OMAP4430_STABLE_PRESCAL_MASK BITFIELD(8, 9) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20 -#define OMAP4430_TCM1_MEM_ONSTATE_MASK (0x3 << 20) +#define OMAP4430_TCM1_MEM_ONSTATE_MASK BITFIELD(20, 21) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10 -#define OMAP4430_TCM1_MEM_RETSTATE_MASK (1 << 10) +#define OMAP4430_TCM1_MEM_RETSTATE_MASK BITFIELD(10, 10) /* Used by PM_IVAHD_PWRSTST */ #define OMAP4430_TCM1_MEM_STATEST_SHIFT 8 -#define OMAP4430_TCM1_MEM_STATEST_MASK (0x3 << 8) +#define OMAP4430_TCM1_MEM_STATEST_MASK BITFIELD(8, 9) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22 -#define OMAP4430_TCM2_MEM_ONSTATE_MASK (0x3 << 22) +#define OMAP4430_TCM2_MEM_ONSTATE_MASK BITFIELD(22, 23) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11 -#define OMAP4430_TCM2_MEM_RETSTATE_MASK (1 << 11) +#define OMAP4430_TCM2_MEM_RETSTATE_MASK BITFIELD(11, 11) /* Used by PM_IVAHD_PWRSTST */ #define OMAP4430_TCM2_MEM_STATEST_SHIFT 10 -#define OMAP4430_TCM2_MEM_STATEST_MASK (0x3 << 10) +#define OMAP4430_TCM2_MEM_STATEST_MASK BITFIELD(10, 11) /* Used by RM_TESLA_RSTST */ #define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2 -#define OMAP4430_TESLASS_EMU_RSTST_MASK (1 << 2) +#define OMAP4430_TESLASS_EMU_RSTST_MASK BITFIELD(2, 2) /* Used by RM_TESLA_RSTST */ #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3 -#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK (1 << 3) +#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK BITFIELD(3, 3) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20 -#define OMAP4430_TESLA_EDMA_ONSTATE_MASK (0x3 << 20) +#define OMAP4430_TESLA_EDMA_ONSTATE_MASK BITFIELD(20, 21) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10 -#define OMAP4430_TESLA_EDMA_RETSTATE_MASK (1 << 10) +#define OMAP4430_TESLA_EDMA_RETSTATE_MASK BITFIELD(10, 10) /* Used by PM_TESLA_PWRSTST */ #define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8 -#define OMAP4430_TESLA_EDMA_STATEST_MASK (0x3 << 8) +#define OMAP4430_TESLA_EDMA_STATEST_MASK BITFIELD(8, 9) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16 -#define OMAP4430_TESLA_L1_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_TESLA_L1_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8 -#define OMAP4430_TESLA_L1_RETSTATE_MASK (1 << 8) +#define OMAP4430_TESLA_L1_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_TESLA_PWRSTST */ #define OMAP4430_TESLA_L1_STATEST_SHIFT 4 -#define OMAP4430_TESLA_L1_STATEST_MASK (0x3 << 4) +#define OMAP4430_TESLA_L1_STATEST_MASK BITFIELD(4, 5) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18 -#define OMAP4430_TESLA_L2_ONSTATE_MASK (0x3 << 18) +#define OMAP4430_TESLA_L2_ONSTATE_MASK BITFIELD(18, 19) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9 -#define OMAP4430_TESLA_L2_RETSTATE_MASK (1 << 9) +#define OMAP4430_TESLA_L2_RETSTATE_MASK BITFIELD(9, 9) /* Used by PM_TESLA_PWRSTST */ #define OMAP4430_TESLA_L2_STATEST_SHIFT 6 -#define OMAP4430_TESLA_L2_STATEST_MASK (0x3 << 6) +#define OMAP4430_TESLA_L2_STATEST_MASK BITFIELD(6, 7) /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_TIMEOUT_SHIFT 0 -#define OMAP4430_TIMEOUT_MASK (0xffff << 0) +#define OMAP4430_TIMEOUT_MASK BITFIELD(0, 15) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_TIMEOUTEN_SHIFT 3 -#define OMAP4430_TIMEOUTEN_MASK (1 << 3) +#define OMAP4430_TIMEOUTEN_MASK BITFIELD(3, 3) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_TRANSITION_EN_SHIFT 8 -#define OMAP4430_TRANSITION_EN_MASK (1 << 8) +#define OMAP4430_TRANSITION_EN_MASK BITFIELD(8, 8) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_TRANSITION_ST_SHIFT 8 -#define OMAP4430_TRANSITION_ST_MASK (1 << 8) +#define OMAP4430_TRANSITION_ST_MASK BITFIELD(8, 8) /* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_VALID_SHIFT 24 -#define OMAP4430_VALID_MASK (1 << 24) +#define OMAP4430_VALID_MASK BITFIELD(24, 24) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_BYPASSACK_EN_SHIFT 14 -#define OMAP4430_VC_BYPASSACK_EN_MASK (1 << 14) +#define OMAP4430_VC_BYPASSACK_EN_MASK BITFIELD(14, 14) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_BYPASSACK_ST_SHIFT 14 -#define OMAP4430_VC_BYPASSACK_ST_MASK (1 << 14) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_CORE_VPACK_EN_SHIFT 22 -#define OMAP4430_VC_CORE_VPACK_EN_MASK (1 << 22) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_CORE_VPACK_ST_SHIFT 22 -#define OMAP4430_VC_CORE_VPACK_ST_MASK (1 << 22) +#define OMAP4430_VC_BYPASSACK_ST_MASK BITFIELD(14, 14) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30 -#define OMAP4430_VC_IVA_VPACK_EN_MASK (1 << 30) +#define OMAP4430_VC_IVA_VPACK_EN_MASK BITFIELD(30, 30) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30 -#define OMAP4430_VC_IVA_VPACK_ST_MASK (1 << 30) +#define OMAP4430_VC_IVA_VPACK_ST_MASK BITFIELD(30, 30) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6 -#define OMAP4430_VC_MPU_VPACK_EN_MASK (1 << 6) +#define OMAP4430_VC_MPU_VPACK_EN_MASK BITFIELD(6, 6) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6 -#define OMAP4430_VC_MPU_VPACK_ST_MASK (1 << 6) +#define OMAP4430_VC_MPU_VPACK_ST_MASK BITFIELD(6, 6) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_RAERR_EN_SHIFT 12 -#define OMAP4430_VC_RAERR_EN_MASK (1 << 12) +#define OMAP4430_VC_RAERR_EN_MASK BITFIELD(12, 12) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_RAERR_ST_SHIFT 12 -#define OMAP4430_VC_RAERR_ST_MASK (1 << 12) +#define OMAP4430_VC_RAERR_ST_MASK BITFIELD(12, 12) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_SAERR_EN_SHIFT 11 -#define OMAP4430_VC_SAERR_EN_MASK (1 << 11) +#define OMAP4430_VC_SAERR_EN_MASK BITFIELD(11, 11) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_SAERR_ST_SHIFT 11 -#define OMAP4430_VC_SAERR_ST_MASK (1 << 11) +#define OMAP4430_VC_SAERR_ST_MASK BITFIELD(11, 11) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_TOERR_EN_SHIFT 13 -#define OMAP4430_VC_TOERR_EN_MASK (1 << 13) +#define OMAP4430_VC_TOERR_EN_MASK BITFIELD(13, 13) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_TOERR_ST_SHIFT 13 -#define OMAP4430_VC_TOERR_ST_MASK (1 << 13) +#define OMAP4430_VC_TOERR_ST_MASK BITFIELD(13, 13) /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_VDDMAX_SHIFT 24 -#define OMAP4430_VDDMAX_MASK (0xff << 24) +#define OMAP4430_VDDMAX_MASK BITFIELD(24, 31) /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_VDDMIN_SHIFT 16 -#define OMAP4430_VDDMIN_MASK (0xff << 16) +#define OMAP4430_VDDMIN_MASK BITFIELD(16, 23) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12 -#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK (1 << 12) +#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK BITFIELD(12, 12) /* Used by PRM_RSTST */ #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 -#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) +#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK BITFIELD(8, 8) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14 -#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK (1 << 14) +#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK BITFIELD(14, 14) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9 -#define OMAP4430_VDD_IVA_PRESENCE_MASK (1 << 9) +#define OMAP4430_VDD_IVA_PRESENCE_MASK BITFIELD(9, 9) /* Used by PRM_RSTST */ #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 -#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK (1 << 7) +#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK BITFIELD(7, 7) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13 -#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK (1 << 13) +#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK BITFIELD(13, 13) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8 -#define OMAP4430_VDD_MPU_PRESENCE_MASK (1 << 8) +#define OMAP4430_VDD_MPU_PRESENCE_MASK BITFIELD(8, 8) /* Used by PRM_RSTST */ #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 -#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_RA_ERR_CORE_SHIFT 4 -#define OMAP4430_VFSM_RA_ERR_CORE_MASK (1 << 4) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_RA_ERR_IVA_SHIFT 12 -#define OMAP4430_VFSM_RA_ERR_IVA_MASK (1 << 12) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_RA_ERR_MPU_SHIFT 20 -#define OMAP4430_VFSM_RA_ERR_MPU_MASK (1 << 20) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_SA_ERR_CORE_SHIFT 3 -#define OMAP4430_VFSM_SA_ERR_CORE_MASK (1 << 3) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_SA_ERR_IVA_SHIFT 11 -#define OMAP4430_VFSM_SA_ERR_IVA_MASK (1 << 11) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_SA_ERR_MPU_SHIFT 19 -#define OMAP4430_VFSM_SA_ERR_MPU_MASK (1 << 19) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 -#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT 13 -#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK (1 << 13) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT 21 -#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 21) +#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK BITFIELD(6, 6) /* Used by PRM_VC_VAL_SMPS_RA_VOL */ #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0 -#define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) +#define OMAP4430_VOLRA_VDD_CORE_L_MASK BITFIELD(0, 7) /* Used by PRM_VC_VAL_SMPS_RA_VOL */ #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8 -#define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) +#define OMAP4430_VOLRA_VDD_IVA_L_MASK BITFIELD(8, 15) /* Used by PRM_VC_VAL_SMPS_RA_VOL */ #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16 -#define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) +#define OMAP4430_VOLRA_VDD_MPU_L_MASK BITFIELD(16, 23) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_VPENABLE_SHIFT 0 -#define OMAP4430_VPENABLE_MASK (1 << 0) +#define OMAP4430_VPENABLE_MASK BITFIELD(0, 0) /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ #define OMAP4430_VPINIDLE_SHIFT 0 -#define OMAP4430_VPINIDLE_MASK (1 << 0) +#define OMAP4430_VPINIDLE_MASK BITFIELD(0, 0) /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ #define OMAP4430_VPVOLTAGE_SHIFT 0 -#define OMAP4430_VPVOLTAGE_MASK (0xff << 0) +#define OMAP4430_VPVOLTAGE_MASK BITFIELD(0, 7) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20 -#define OMAP4430_VP_CORE_EQVALUE_EN_MASK (1 << 20) +#define OMAP4430_VP_CORE_EQVALUE_EN_MASK BITFIELD(20, 20) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20 -#define OMAP4430_VP_CORE_EQVALUE_ST_MASK (1 << 20) +#define OMAP4430_VP_CORE_EQVALUE_ST_MASK BITFIELD(20, 20) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18 -#define OMAP4430_VP_CORE_MAXVDD_EN_MASK (1 << 18) +#define OMAP4430_VP_CORE_MAXVDD_EN_MASK BITFIELD(18, 18) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18 -#define OMAP4430_VP_CORE_MAXVDD_ST_MASK (1 << 18) +#define OMAP4430_VP_CORE_MAXVDD_ST_MASK BITFIELD(18, 18) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17 -#define OMAP4430_VP_CORE_MINVDD_EN_MASK (1 << 17) +#define OMAP4430_VP_CORE_MINVDD_EN_MASK BITFIELD(17, 17) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17 -#define OMAP4430_VP_CORE_MINVDD_ST_MASK (1 << 17) +#define OMAP4430_VP_CORE_MINVDD_ST_MASK BITFIELD(17, 17) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19 -#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) +#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK BITFIELD(19, 19) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19 -#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) +#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK BITFIELD(19, 19) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 -#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) +#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK BITFIELD(16, 16) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 -#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) +#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK BITFIELD(16, 16) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21 -#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK (1 << 21) +#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK BITFIELD(21, 21) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21 -#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) +#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK BITFIELD(21, 21) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28 -#define OMAP4430_VP_IVA_EQVALUE_EN_MASK (1 << 28) +#define OMAP4430_VP_IVA_EQVALUE_EN_MASK BITFIELD(28, 28) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28 -#define OMAP4430_VP_IVA_EQVALUE_ST_MASK (1 << 28) +#define OMAP4430_VP_IVA_EQVALUE_ST_MASK BITFIELD(28, 28) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26 -#define OMAP4430_VP_IVA_MAXVDD_EN_MASK (1 << 26) +#define OMAP4430_VP_IVA_MAXVDD_EN_MASK BITFIELD(26, 26) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26 -#define OMAP4430_VP_IVA_MAXVDD_ST_MASK (1 << 26) +#define OMAP4430_VP_IVA_MAXVDD_ST_MASK BITFIELD(26, 26) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25 -#define OMAP4430_VP_IVA_MINVDD_EN_MASK (1 << 25) +#define OMAP4430_VP_IVA_MINVDD_EN_MASK BITFIELD(25, 25) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25 -#define OMAP4430_VP_IVA_MINVDD_ST_MASK (1 << 25) +#define OMAP4430_VP_IVA_MINVDD_ST_MASK BITFIELD(25, 25) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27 -#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK (1 << 27) +#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK BITFIELD(27, 27) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27 -#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK (1 << 27) +#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK BITFIELD(27, 27) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24 -#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK (1 << 24) +#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK BITFIELD(24, 24) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24 -#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK (1 << 24) +#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK BITFIELD(24, 24) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29 -#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK (1 << 29) +#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK BITFIELD(29, 29) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29 -#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) +#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK BITFIELD(29, 29) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4 -#define OMAP4430_VP_MPU_EQVALUE_EN_MASK (1 << 4) +#define OMAP4430_VP_MPU_EQVALUE_EN_MASK BITFIELD(4, 4) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4 -#define OMAP4430_VP_MPU_EQVALUE_ST_MASK (1 << 4) +#define OMAP4430_VP_MPU_EQVALUE_ST_MASK BITFIELD(4, 4) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2 -#define OMAP4430_VP_MPU_MAXVDD_EN_MASK (1 << 2) +#define OMAP4430_VP_MPU_MAXVDD_EN_MASK BITFIELD(2, 2) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2 -#define OMAP4430_VP_MPU_MAXVDD_ST_MASK (1 << 2) +#define OMAP4430_VP_MPU_MAXVDD_ST_MASK BITFIELD(2, 2) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1 -#define OMAP4430_VP_MPU_MINVDD_EN_MASK (1 << 1) +#define OMAP4430_VP_MPU_MINVDD_EN_MASK BITFIELD(1, 1) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1 -#define OMAP4430_VP_MPU_MINVDD_ST_MASK (1 << 1) +#define OMAP4430_VP_MPU_MINVDD_ST_MASK BITFIELD(1, 1) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3 -#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) +#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK BITFIELD(3, 3) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3 -#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) +#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK BITFIELD(3, 3) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 -#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) +#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK BITFIELD(0, 0) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 -#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) +#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK BITFIELD(0, 0) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5 -#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK (1 << 5) +#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK BITFIELD(5, 5) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5 -#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) +#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK BITFIELD(5, 5) /* Used by PRM_SRAM_COUNT */ #define OMAP4430_VSETUPCNT_VALUE_SHIFT 8 -#define OMAP4430_VSETUPCNT_VALUE_MASK (0xff << 8) +#define OMAP4430_VSETUPCNT_VALUE_MASK BITFIELD(8, 15) /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ #define OMAP4430_VSTEPMAX_SHIFT 0 -#define OMAP4430_VSTEPMAX_MASK (0xff << 0) +#define OMAP4430_VSTEPMAX_MASK BITFIELD(0, 7) /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ #define OMAP4430_VSTEPMIN_SHIFT 0 -#define OMAP4430_VSTEPMIN_MASK (0xff << 0) +#define OMAP4430_VSTEPMIN_MASK BITFIELD(0, 7) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_WAKE_MODEM_SHIFT 0 -#define OMAP4430_WAKE_MODEM_MASK (1 << 0) +#define OMAP4430_WAKE_MODEM_MASK BITFIELD(0, 0) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DISPC_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_DISPC_MPU_MASK BITFIELD(0, 0) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK BITFIELD(3, 3) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_DMIC_WKDEP */ #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_ABE_DMIC_WKDEP */ #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_ABE_DMIC_WKDEP */ #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_DMIC_WKDEP */ #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_DMTIMER10_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_DMTIMER11_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_DMTIMER11_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_DMTIMER2_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_DMTIMER3_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_DMTIMER3_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_DMTIMER4_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_DMTIMER4_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_DMTIMER9_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_DMTIMER9_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK BITFIELD(0, 0) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5 -#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK (1 << 5) +#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK BITFIELD(5, 5) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4 -#define OMAP4430_WKUPDEP_DSI1_MPU_MASK (1 << 4) +#define OMAP4430_WKUPDEP_DSI1_MPU_MASK BITFIELD(4, 4) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK BITFIELD(7, 7) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK BITFIELD(6, 6) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9 -#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK (1 << 9) +#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK BITFIELD(9, 9) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8 -#define OMAP4430_WKUPDEP_DSI2_MPU_MASK (1 << 8) +#define OMAP4430_WKUPDEP_DSI2_MPU_MASK BITFIELD(8, 8) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11 -#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK (1 << 11) +#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK BITFIELD(11, 11) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10 -#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK (1 << 10) +#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK BITFIELD(10, 10) /* Used by PM_WKUP_GPIO1_WKDEP */ #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_WKUP_GPIO1_WKDEP */ #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_GPIO1_WKDEP */ #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_GPIO2_WKDEP */ #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_GPIO2_WKDEP */ #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_GPIO2_WKDEP */ #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_GPIO3_WKDEP */ #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_GPIO3_WKDEP */ #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_GPIO4_WKDEP */ #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_GPIO4_WKDEP */ #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_GPIO5_WKDEP */ #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_GPIO5_WKDEP */ #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_GPIO6_WKDEP */ #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_GPIO6_WKDEP */ #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 -#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) +#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK BITFIELD(19, 19) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13 -#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK (1 << 13) +#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK BITFIELD(13, 13) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 -#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) +#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK BITFIELD(12, 12) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14 -#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK (1 << 14) +#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK BITFIELD(14, 14) /* Used by PM_L4PER_HECC1_WKDEP */ #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HECC1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_HECC1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_HECC2_WKDEP */ #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HECC2_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_HECC2_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_HSI_WKDEP */ #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L3INIT_HSI_WKDEP */ #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_HSI_WKDEP */ #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_I2C1_WKDEP */ #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_I2C1_WKDEP */ #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_I2C1_WKDEP */ #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_I2C2_WKDEP */ #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_I2C2_WKDEP */ #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_I2C2_WKDEP */ #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_I2C3_WKDEP */ #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_I2C3_WKDEP */ #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_I2C3_WKDEP */ #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_I2C4_WKDEP */ #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_I2C4_WKDEP */ #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_I2C4_WKDEP */ #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_I2C5_WKDEP */ #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_I2C5_WKDEP */ #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_KEYBOARD_WKDEP */ #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_MCASP_WKDEP */ #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_ABE_MCASP_WKDEP */ #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_ABE_MCASP_WKDEP */ #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_MCASP_WKDEP */ #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MCASP2_WKDEP */ #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_MCASP2_WKDEP */ #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_MCASP2_WKDEP */ #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCASP2_WKDEP */ #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MCASP3_WKDEP */ #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_MCASP3_WKDEP */ #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_MCASP3_WKDEP */ #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCASP3_WKDEP */ #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_MCBSP1_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_MCBSP1_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK BITFIELD(3, 3) /* Used by PM_ABE_MCBSP1_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_MCBSP2_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_MCBSP2_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK BITFIELD(3, 3) /* Used by PM_ABE_MCBSP2_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_MCBSP3_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_MCBSP3_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK BITFIELD(3, 3) /* Used by PM_ABE_MCBSP3_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MCBSP4_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCBSP4_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MCBSP4_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MCSPI1_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_MCSPI1_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCSPI1_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MCSPI1_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MCSPI2_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_MCSPI2_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCSPI2_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MCSPI3_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCSPI3_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MCSPI4_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCSPI4_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L3INIT_MMC1_WKDEP */ #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_MMC1_WKDEP */ #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MMC1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_MMC1_WKDEP */ #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L3INIT_MMC1_WKDEP */ #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L3INIT_MMC2_WKDEP */ #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_MMC2_WKDEP */ #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC2_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MMC2_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_MMC2_WKDEP */ #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L3INIT_MMC2_WKDEP */ #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L3INIT_MMC6_WKDEP */ #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_MMC6_WKDEP */ #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC6_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MMC6_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_MMC6_WKDEP */ #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MMCSD3_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_MMCSD3_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MMCSD3_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MMCSD4_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_MMCSD4_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MMCSD4_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MMCSD5_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_MMCSD5_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MMCSD5_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L3INIT_PCIESS_WKDEP */ #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_PCIESS_WKDEP */ #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_PDM_WKDEP */ #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_ABE_PDM_WKDEP */ #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_ABE_PDM_WKDEP */ #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_PDM_WKDEP */ #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_WKUP_RTC_WKDEP */ #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_RTC_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_RTC_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_SATA_WKDEP */ #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SATA_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_SATA_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_SATA_WKDEP */ #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SATA_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_SATA_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_SLIMBUS_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_ABE_SLIMBUS_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_ABE_SLIMBUS_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_SLIMBUS_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ALWON_SR_CORE_WKDEP */ #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_ALWON_SR_CORE_WKDEP */ #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK BITFIELD(0, 0) /* Used by PM_ALWON_SR_IVA_WKDEP */ #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_ALWON_SR_IVA_WKDEP */ #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK BITFIELD(0, 0) /* Used by PM_ALWON_SR_MPU_WKDEP */ #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_TIMER12_WKDEP */ #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_TIMER1_WKDEP */ #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_TIMER5_WKDEP */ #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_TIMER5_WKDEP */ #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_TIMER6_WKDEP */ #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_TIMER6_WKDEP */ #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_TIMER7_WKDEP */ #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_TIMER7_WKDEP */ #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_TIMER8_WKDEP */ #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_TIMER8_WKDEP */ #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_UART1_WKDEP */ #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_UART1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_UART1_WKDEP */ #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART1_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_UART1_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_UART2_WKDEP */ #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART2_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_UART2_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_UART2_WKDEP */ #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART2_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_UART2_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_UART3_WKDEP */ #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_UART3_WKDEP */ #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART3_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_UART3_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_UART3_WKDEP */ #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART3_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_UART3_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_UART3_WKDEP */ #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_UART3_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_UART3_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_UART4_WKDEP */ #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART4_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_UART4_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_UART4_WKDEP */ #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART4_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_UART4_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L3INIT_UNIPRO1_WKDEP */ #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_UNIPRO1_WKDEP */ #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_USB_HOST_WKDEP */ #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_USB_HOST_WKDEP */ #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_USB_OTG_WKDEP */ #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_USB_OTG_WKDEP */ #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_USB_TLL_WKDEP */ #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_USB_TLL_WKDEP */ #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_USIM_WKDEP */ #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USIM_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_USIM_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_USIM_WKDEP */ #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_USIM_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_USIM_SDMA_MASK BITFIELD(3, 3) /* Used by PM_WKUP_WDT2_WKDEP */ #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_WKUP_WDT2_WKDEP */ #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_WDT2_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_WDT2_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_WDT3_WKDEP */ #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_WDT3_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_WDT3_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_HSI_WKDEP */ #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8 -#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK (1 << 8) +#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK BITFIELD(8, 8) /* Used by PM_L3INIT_XHPI_WKDEP */ #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK BITFIELD(1, 1) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_WUCLK_CTRL_SHIFT 8 -#define OMAP4430_WUCLK_CTRL_MASK (1 << 8) +#define OMAP4430_WUCLK_CTRL_MASK BITFIELD(8, 8) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_WUCLK_STATUS_SHIFT 9 -#define OMAP4430_WUCLK_STATUS_MASK (1 << 9) - -/* Used by REVISION_PRM */ -#define OMAP4430_X_MAJOR_SHIFT 8 -#define OMAP4430_X_MAJOR_MASK (0x7 << 8) - -/* Used by REVISION_PRM */ -#define OMAP4430_Y_MINOR_SHIFT 0 -#define OMAP4430_Y_MINOR_MASK (0x3f << 0) +#define OMAP4430_WUCLK_STATUS_MASK BITFIELD(9, 9) #endif diff --git a/trunk/arch/arm/mach-omap2/prm.h b/trunk/arch/arm/mach-omap2/prm.h index 7be040b2fdab..588873b9303a 100644 --- a/trunk/arch/arm/mach-omap2/prm.h +++ b/trunk/arch/arm/mach-omap2/prm.h @@ -5,7 +5,7 @@ * OMAP2/3 Power/Reset Management (PRM) register definitions * * Copyright (C) 2007-2009 Texas Instruments, Inc. - * Copyright (C) 2010 Nokia Corporation + * Copyright (C) 2009 Nokia Corporation * * Written by Paul Walmsley * @@ -246,15 +246,6 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) return prm_rmw_mod_reg_bits(bits, 0x0, module, idx); } -/* These omap2_ PRM functions apply to both OMAP2 and 3 */ -int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); -int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); -int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift); - -int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift); -int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift); -int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); - #endif /* @@ -407,11 +398,4 @@ int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); #define OMAP_POWERSTATE_MASK (0x3 << 0) -/* - * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP - * submodule to exit hardreset - */ -#define MAX_MODULE_HARDRESET_WAIT 10000 - - #endif diff --git a/trunk/arch/arm/mach-omap2/prm2xxx_3xxx.c b/trunk/arch/arm/mach-omap2/prm2xxx_3xxx.c deleted file mode 100644 index 421771eee450..000000000000 --- a/trunk/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * OMAP2/3 PRM module functions - * - * Copyright (C) 2010 Texas Instruments, Inc. - * Copyright (C) 2010 Nokia Corporation - * Benoît Cousson - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include "prm.h" -#include "prm-regbits-24xx.h" -#include "prm-regbits-34xx.h" - -/** - * omap2_prm_is_hardreset_asserted - read the HW reset line state of - * submodules contained in the hwmod module - * @prm_mod: PRM submodule base (e.g. CORE_MOD) - * @shift: register bit shift corresponding to the reset line to check - * - * Returns 1 if the (sub)module hardreset line is currently asserted, - * 0 if the (sub)module hardreset line is not currently asserted, or - * -EINVAL if called while running on a non-OMAP2/3 chip. - */ -int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) -{ - if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) - return -EINVAL; - - return prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, - (1 << shift)); -} - -/** - * omap2_prm_assert_hardreset - assert the HW reset line of a submodule - * @prm_mod: PRM submodule base (e.g. CORE_MOD) - * @shift: register bit shift corresponding to the reset line to assert - * - * Some IPs like dsp or iva contain processors that require an HW - * reset line to be asserted / deasserted in order to fully enable the - * IP. These modules may have multiple hard-reset lines that reset - * different 'submodules' inside the IP block. This function will - * place the submodule into reset. Returns 0 upon success or -EINVAL - * upon an argument error. - */ -int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) -{ - u32 mask; - - if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) - return -EINVAL; - - mask = 1 << shift; - prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); - - return 0; -} - -/** - * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait - * @prm_mod: PRM submodule base (e.g. CORE_MOD) - * @shift: register bit shift corresponding to the reset line to deassert - * - * Some IPs like dsp or iva contain processors that require an HW - * reset line to be asserted / deasserted in order to fully enable the - * IP. These modules may have multiple hard-reset lines that reset - * different 'submodules' inside the IP block. This function will - * take the submodule out of reset and wait until the PRCM indicates - * that the reset has completed before returning. Returns 0 upon success or - * -EINVAL upon an argument error, -EEXIST if the submodule was already out - * of reset, or -EBUSY if the submodule did not exit reset promptly. - */ -int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift) -{ - u32 mask; - int c; - - if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) - return -EINVAL; - - mask = 1 << shift; - - /* Check the current status to avoid de-asserting the line twice */ - if (prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0) - return -EEXIST; - - /* Clear the reset status by writing 1 to the status bit */ - prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST); - /* de-assert the reset control line */ - prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL); - /* wait the status to be set */ - omap_test_timeout(prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, - mask), - MAX_MODULE_HARDRESET_WAIT, c); - - return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; -} - diff --git a/trunk/arch/arm/mach-omap2/prm44xx.c b/trunk/arch/arm/mach-omap2/prm44xx.c deleted file mode 100644 index a1ff918d9bed..000000000000 --- a/trunk/arch/arm/mach-omap2/prm44xx.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * OMAP4 PRM module functions - * - * Copyright (C) 2010 Texas Instruments, Inc. - * Copyright (C) 2010 Nokia Corporation - * Benoît Cousson - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include "prm.h" -#include "prm-regbits-44xx.h" - -/* - * Address offset (in bytes) between the reset control and the reset - * status registers: 4 bytes on OMAP4 - */ -#define OMAP4_RST_CTRL_ST_OFFSET 4 - -/** - * omap4_prm_is_hardreset_asserted - read the HW reset line state of - * submodules contained in the hwmod module - * @rstctrl_reg: RM_RSTCTRL register address for this module - * @shift: register bit shift corresponding to the reset line to check - * - * Returns 1 if the (sub)module hardreset line is currently asserted, - * 0 if the (sub)module hardreset line is not currently asserted, or - * -EINVAL upon parameter error. - */ -int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift) -{ - if (!cpu_is_omap44xx() || !rstctrl_reg) - return -EINVAL; - - return omap4_prm_read_bits_shift(rstctrl_reg, (1 << shift)); -} - -/** - * omap4_prm_assert_hardreset - assert the HW reset line of a submodule - * @rstctrl_reg: RM_RSTCTRL register address for this module - * @shift: register bit shift corresponding to the reset line to assert - * - * Some IPs like dsp, ipu or iva contain processors that require an HW - * reset line to be asserted / deasserted in order to fully enable the - * IP. These modules may have multiple hard-reset lines that reset - * different 'submodules' inside the IP block. This function will - * place the submodule into reset. Returns 0 upon success or -EINVAL - * upon an argument error. - */ -int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift) -{ - u32 mask; - - if (!cpu_is_omap44xx() || !rstctrl_reg) - return -EINVAL; - - mask = 1 << shift; - omap4_prm_rmw_reg_bits(mask, mask, rstctrl_reg); - - return 0; -} - -/** - * omap4_prm_deassert_hardreset - deassert a submodule hardreset line and wait - * @rstctrl_reg: RM_RSTCTRL register address for this module - * @shift: register bit shift corresponding to the reset line to deassert - * - * Some IPs like dsp, ipu or iva contain processors that require an HW - * reset line to be asserted / deasserted in order to fully enable the - * IP. These modules may have multiple hard-reset lines that reset - * different 'submodules' inside the IP block. This function will - * take the submodule out of reset and wait until the PRCM indicates - * that the reset has completed before returning. Returns 0 upon success or - * -EINVAL upon an argument error, -EEXIST if the submodule was already out - * of reset, or -EBUSY if the submodule did not exit reset promptly. - */ -int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift) -{ - u32 mask; - void __iomem *rstst_reg; - int c; - - if (!cpu_is_omap44xx() || !rstctrl_reg) - return -EINVAL; - - rstst_reg = rstctrl_reg + OMAP4_RST_CTRL_ST_OFFSET; - - mask = 1 << shift; - - /* Check the current status to avoid de-asserting the line twice */ - if (omap4_prm_read_bits_shift(rstctrl_reg, mask) == 0) - return -EEXIST; - - /* Clear the reset status by writing 1 to the status bit */ - omap4_prm_rmw_reg_bits(0xffffffff, mask, rstst_reg); - /* de-assert the reset control line */ - omap4_prm_rmw_reg_bits(mask, 0, rstctrl_reg); - /* wait the status to be set */ - omap_test_timeout(omap4_prm_read_bits_shift(rstst_reg, mask), - MAX_MODULE_HARDRESET_WAIT, c); - - return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; -} - diff --git a/trunk/arch/arm/mach-omap2/prm44xx.h b/trunk/arch/arm/mach-omap2/prm44xx.h index 59839dbabd84..fe8ef26431e5 100644 --- a/trunk/arch/arm/mach-omap2/prm44xx.h +++ b/trunk/arch/arm/mach-omap2/prm44xx.h @@ -44,12 +44,14 @@ #define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030) #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038 #define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038) -#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) +#define OMAP4_PRM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 +#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) /* PRM.CKGEN_PRM register offsets */ #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000 #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000) +#define OMAP4_CM_DPLL_SYS_REF_CLKSEL_OFFSET 0x0004 +#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004) #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008 #define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008) #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c @@ -684,8 +686,8 @@ #define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8) #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc #define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc) -#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0 -#define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) +#define OMAP4_PRM_LDO_BANDGAP_CTRL_OFFSET 0x00e0 +#define OMAP4430_PRM_LDO_BANDGAP_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4 #define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4) #define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8 @@ -696,8 +698,6 @@ #define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0) #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4 #define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4) -#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 -#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8) /* * PRCM_MPU @@ -715,8 +715,6 @@ /* PRCM_MPU.DEVICE_PRM register offsets */ #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 #define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000) -#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 -#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004) /* PRCM_MPU.CPU0 register offsets */ #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 diff --git a/trunk/arch/arm/mach-omap2/sram34xx.S b/trunk/arch/arm/mach-omap2/sram34xx.S index 3637274af5be..de99ba2a57ab 100644 --- a/trunk/arch/arm/mach-omap2/sram34xx.S +++ b/trunk/arch/arm/mach-omap2/sram34xx.S @@ -129,11 +129,8 @@ ENTRY(omap3_sram_configure_core_dpll) ldr r4, [sp, #80] str r4, omap_sdrc_mr_1_val skip_cs1_params: - mrc p15, 0, r8, c1, c0, 0 @ read ctrl register - bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction - mcr p15, 0, r10, c1, c0, 0 @ write ctrl register dsb @ flush buffered writes to interconnect - isb @ prevent speculative exec past here + cmp r3, #1 @ if increasing SDRC clk rate, bleq configure_sdrc @ program the SDRC regs early (for RFR) cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state @@ -151,7 +148,6 @@ skip_cs1_params: beq return_to_sdram @ return to SDRAM code, otherwise, bl configure_sdrc @ reprogram SDRC regs now return_to_sdram: - mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register isb @ prevent speculative exec past here mov r0, #0 @ return value ldmfd sp!, {r1-r12, pc} @ restore regs and return diff --git a/trunk/arch/arm/mach-omap2/timer-gp.c b/trunk/arch/arm/mach-omap2/timer-gp.c index e13c29eecf2b..74fbed8491f2 100644 --- a/trunk/arch/arm/mach-omap2/timer-gp.c +++ b/trunk/arch/arm/mach-omap2/timer-gp.c @@ -40,8 +40,6 @@ #include #include -#include "timer-gp.h" - /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12 @@ -230,10 +228,8 @@ static void __init omap2_gp_clocksource_init(void) static void __init omap2_gp_timer_init(void) { #ifdef CONFIG_LOCAL_TIMERS - if (cpu_is_omap44xx()) { - twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256); - BUG_ON(!twd_base); - } + twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256); + BUG_ON(!twd_base); #endif omap_dm_timer_init(); diff --git a/trunk/arch/arm/plat-omap/Kconfig b/trunk/arch/arm/plat-omap/Kconfig index d98c5c0e164b..e39a417a368d 100644 --- a/trunk/arch/arm/plat-omap/Kconfig +++ b/trunk/arch/arm/plat-omap/Kconfig @@ -19,7 +19,7 @@ config ARCH_OMAP2PLUS bool "TI OMAP2/3/4" select COMMON_CLKDEV help - "Systems based on OMAP2, OMAP3 or OMAP4" + "Systems based on omap24xx, omap34xx or omap44xx" endchoice diff --git a/trunk/arch/arm/plat-omap/common.c b/trunk/arch/arm/plat-omap/common.c index 7d668b3b5363..3008e7104487 100644 --- a/trunk/arch/arm/plat-omap/common.c +++ b/trunk/arch/arm/plat-omap/common.c @@ -336,8 +336,7 @@ void __init omap3_map_io(void) static struct omap_globals omap4_globals = { .class = OMAP443X_CLASS, .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), - .ctrl = OMAP443X_SCM_BASE, - .ctrl_pad = OMAP443X_CTRL_BASE, + .ctrl = OMAP443X_CTRL_BASE, .prm = OMAP4430_PRM_BASE, .cm = OMAP4430_CM_BASE, .cm2 = OMAP4430_CM2_BASE, diff --git a/trunk/arch/arm/plat-omap/cpu-omap.c b/trunk/arch/arm/plat-omap/cpu-omap.c index 11c54ec8d47f..6d3d33360056 100644 --- a/trunk/arch/arm/plat-omap/cpu-omap.c +++ b/trunk/arch/arm/plat-omap/cpu-omap.c @@ -40,7 +40,7 @@ static struct clk *mpu_clk; /* TODO: Add support for SDRAM timing changes */ -static int omap_verify_speed(struct cpufreq_policy *policy) +int omap_verify_speed(struct cpufreq_policy *policy) { if (freq_table) return cpufreq_frequency_table_verify(policy, freq_table); @@ -58,7 +58,7 @@ static int omap_verify_speed(struct cpufreq_policy *policy) return 0; } -static unsigned int omap_getspeed(unsigned int cpu) +unsigned int omap_getspeed(unsigned int cpu) { unsigned long rate; diff --git a/trunk/arch/arm/plat-omap/dmtimer.c b/trunk/arch/arm/plat-omap/dmtimer.c index 1d706cf63ca0..44bafdab2dce 100644 --- a/trunk/arch/arm/plat-omap/dmtimer.c +++ b/trunk/arch/arm/plat-omap/dmtimer.c @@ -581,7 +581,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) * When the functional clock disappears, too quick writes seem * to cause an abort. XXX Is this still necessary? */ - __delay(300000); + __delay(150000); return ret; } diff --git a/trunk/arch/arm/plat-omap/fb.c b/trunk/arch/arm/plat-omap/fb.c index 725df5c1569d..0054b9501a53 100644 --- a/trunk/arch/arm/plat-omap/fb.c +++ b/trunk/arch/arm/plat-omap/fb.c @@ -36,8 +36,6 @@ #include #include -#include "fb.h" - #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) static struct omapfb_platform_data omapfb_config; diff --git a/trunk/arch/arm/plat-omap/fb.h b/trunk/arch/arm/plat-omap/fb.h deleted file mode 100644 index d765d0bd8520..000000000000 --- a/trunk/arch/arm/plat-omap/fb.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __PLAT_OMAP_FB_H__ -#define __PLAT_OMAP_FB_H__ - -extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart, - unsigned long sram_vstart, - unsigned long sram_size, - unsigned long pstart_avail, - unsigned long size_avail); - -#endif /* __PLAT_OMAP_FB_H__ */ diff --git a/trunk/arch/arm/plat-omap/gpio.c b/trunk/arch/arm/plat-omap/gpio.c index c05c653d1674..11c5b0eefb85 100644 --- a/trunk/arch/arm/plat-omap/gpio.c +++ b/trunk/arch/arm/plat-omap/gpio.c @@ -2084,7 +2084,7 @@ void omap2_gpio_prepare_for_idle(int power_state) for (i = min; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; - u32 l1 = 0, l2 = 0; + u32 l1, l2; int j; for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) @@ -2152,7 +2152,7 @@ void omap2_gpio_resume_after_idle(void) min = 1; for (i = min; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; - u32 l = 0, gen, gen0, gen1; + u32 l, gen, gen0, gen1; int j; for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) diff --git a/trunk/arch/arm/plat-omap/include/plat/common.h b/trunk/arch/arm/plat-omap/include/plat/common.h index 2d8f98d7ae50..c45dbb975e09 100644 --- a/trunk/arch/arm/plat-omap/include/plat/common.h +++ b/trunk/arch/arm/plat-omap/include/plat/common.h @@ -47,7 +47,6 @@ struct omap_globals { unsigned long sdrc; /* SDRAM Controller */ unsigned long sms; /* SDRAM Memory Scheduler */ unsigned long ctrl; /* System Control Module */ - unsigned long ctrl_pad; /* PAD Control Module */ unsigned long prm; /* Power and Reset Management */ unsigned long cm; /* Clock Management */ unsigned long cm2; diff --git a/trunk/arch/arm/plat-omap/include/plat/control.h b/trunk/arch/arm/plat-omap/include/plat/control.h index 19c9b2a82046..131bf405c2f6 100644 --- a/trunk/arch/arm/plat-omap/include/plat/control.h +++ b/trunk/arch/arm/plat-omap/include/plat/control.h @@ -17,10 +17,6 @@ #define __ASM_ARCH_CONTROL_H #include -#include -#include -#include -#include #ifndef __ASSEMBLY__ #define OMAP242X_CTRL_REGADDR(reg) \ @@ -208,6 +204,12 @@ #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 +/* 44xx control status register offset */ +#define OMAP44XX_CONTROL_STATUS 0x2c4 + +/* 44xx-only CONTROL_GENERAL register offsets */ +#define OMAP44XX_CONTROL_MMC1 0x628 +#define OMAP44XX_CONTROL_PBIAS_LITE 0x600 /* * REVISIT: This list of registers is not comprehensive - there are more * that should be added. @@ -253,6 +255,23 @@ #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) #define OMAP2_PBIASLITEVMODE0 (1 << 0) +/* CONTROL_PBIAS_LITE bits for OMAP4 */ +#define OMAP4_MMC1_PWRDNZ (1 << 26) +#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25) +#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24) +#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23) +#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22) +#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21) +#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20) + +#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31) +#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30) +#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29) +#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28) +#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27) +#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26) +#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25) + /* CONTROL_PROG_IO1 bits */ #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) @@ -335,11 +354,9 @@ extern void __iomem *omap_ctrl_base_get(void); extern u8 omap_ctrl_readb(u16 offset); extern u16 omap_ctrl_readw(u16 offset); extern u32 omap_ctrl_readl(u16 offset); -extern u32 omap4_ctrl_pad_readl(u16 offset); extern void omap_ctrl_writeb(u8 val, u16 offset); extern void omap_ctrl_writew(u16 val, u16 offset); extern void omap_ctrl_writel(u32 val, u16 offset); -extern void omap4_ctrl_pad_writel(u32 val, u16 offset); extern void omap3_save_scratchpad_contents(void); extern void omap3_clear_scratchpad_contents(void); @@ -354,11 +371,9 @@ extern void omap3_control_restore_context(void); #define omap_ctrl_readb(x) 0 #define omap_ctrl_readw(x) 0 #define omap_ctrl_readl(x) 0 -#define omap4_ctrl_pad_readl(x) 0 #define omap_ctrl_writeb(x, y) WARN_ON(1) #define omap_ctrl_writew(x, y) WARN_ON(1) #define omap_ctrl_writel(x, y) WARN_ON(1) -#define omap4_ctrl_pad_writel(x, y) WARN_ON(1) #endif #endif /* __ASSEMBLY__ */ diff --git a/trunk/arch/arm/plat-omap/include/plat/cpu.h b/trunk/arch/arm/plat-omap/include/plat/cpu.h index 9b38e4bddf57..2e2ae530fced 100644 --- a/trunk/arch/arm/plat-omap/include/plat/cpu.h +++ b/trunk/arch/arm/plat-omap/include/plat/cpu.h @@ -391,7 +391,6 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP443X_CLASS 0x44300044 #define OMAP4430_REV_ES1_0 0x44300044 -#define OMAP4430_REV_ES2_0 0x44301044 /* * omap_chip bits @@ -418,12 +417,10 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP4430ES1 (1 << 8) #define CHIP_IS_OMAP3630ES1_1 (1 << 9) #define CHIP_IS_OMAP3630ES1_2 (1 << 10) -#define CHIP_IS_OMAP4430ES2 (1 << 11) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) -#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ - CHIP_IS_OMAP4430ES2) +#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1) /* * "GE" here represents "greater than or equal to" in terms of ES diff --git a/trunk/arch/arm/plat-omap/include/plat/dmtimer.h b/trunk/arch/arm/plat-omap/include/plat/dmtimer.h index dfa3aff9761b..20f1054c0a80 100644 --- a/trunk/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/trunk/arch/arm/plat-omap/include/plat/dmtimer.h @@ -45,8 +45,6 @@ #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 struct omap_dm_timer; -extern struct omap_dm_timer *gptimer_wakeup; -extern struct sys_timer omap_timer; struct clk; int omap_dm_timer_init(void); diff --git a/trunk/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h b/trunk/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h deleted file mode 100644 index 872de0bf1e6b..000000000000 --- a/trunk/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * arch/arm/plat-omap/include/plat/gpmc-smsc911x.h - * - * Copyright (C) 2009 Li-Pro.Net - * Stephan Linz - * - * Modified from arch/arm/plat-omap/include/plat/gpmc-smc91x.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_OMAP_GPMC_SMSC911X_H__ - -struct omap_smsc911x_platform_data { - int cs; - int gpio_irq; - int gpio_reset; - u32 flags; -}; - -#if defined(CONFIG_SMSC911X) || \ - defined(CONFIG_SMSC911X_MODULE) - -extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d); - -#else - -static inline void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d) -{ -} - -#endif -#endif diff --git a/trunk/arch/arm/plat-omap/include/plat/i2c.h b/trunk/arch/arm/plat-omap/include/plat/i2c.h index 36a0befd6168..87f6bf2ea4fa 100644 --- a/trunk/arch/arm/plat-omap/include/plat/i2c.h +++ b/trunk/arch/arm/plat-omap/include/plat/i2c.h @@ -18,8 +18,6 @@ * 02110-1301 USA * */ -#ifndef __ASM__ARCH_OMAP_I2C_H -#define __ASM__ARCH_OMAP_I2C_H #include @@ -38,5 +36,3 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, void __init omap1_i2c_mux_pins(int bus_id); void __init omap2_i2c_mux_pins(int bus_id); - -#endif /* __ASM__ARCH_OMAP_I2C_H */ diff --git a/trunk/arch/arm/plat-omap/include/plat/mmc.h b/trunk/arch/arm/plat-omap/include/plat/mmc.h index c5f35f87deaa..9b89ec601ee2 100644 --- a/trunk/arch/arm/plat-omap/include/plat/mmc.h +++ b/trunk/arch/arm/plat-omap/include/plat/mmc.h @@ -73,12 +73,10 @@ struct omap_mmc_platform_data { struct omap_mmc_slot_data { - /* - * 4/8 wires and any additional host capabilities - * need to OR'd all capabilities (ref. linux/mmc/host.h) + /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC; + * 8 wire signaling is also optional, and is used with HSMMC */ - u8 wires; /* Used for the MMC driver on omap1 and 2420 */ - u32 caps; /* Used for the MMC driver on 2430 and later */ + u8 wires; /* * nomux means "standard" muxing is wrong on this board, and diff --git a/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h b/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h index c1835afc238d..cab4a681a121 100644 --- a/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -14,16 +14,19 @@ * * These headers and macros are used to define OMAP on-chip module * data and their integration with other OMAP modules and Linux. - * Copious documentation and references can also be found in the - * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this - * writing). + * + * References: + * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) + * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) + * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) + * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) + * - Open Core Protocol Specification 2.2 * * To do: * - add interconnect error log structures * - add pinmuxing * - init_conn_id_bit (CONNID_BIT_VECTOR) * - implement default hwmod SMS/SDRC flags? - * - remove unused fields * */ #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H @@ -32,7 +35,6 @@ #include #include #include -#include #include struct omap_device; @@ -94,7 +96,7 @@ struct omap_hwmod_irq_info { /** * struct omap_hwmod_dma_info - DMA channels used by the hwmod * @name: name of the DMA channel (module local name) - * @dma_req: DMA request ID + * @dma_ch: DMA channel ID * * @name should be something short, e.g., "tx" or "rx". It is for use * by platform_get_resource_byname(). It is defined locally to the @@ -102,20 +104,7 @@ struct omap_hwmod_irq_info { */ struct omap_hwmod_dma_info { const char *name; - u16 dma_req; -}; - -/** - * struct omap_hwmod_rst_info - IPs reset lines use by hwmod - * @name: name of the reset line (module local name) - * @rst_shift: Offset of the reset bit - * - * @name should be something short, e.g., "cpu0" or "rst". It is defined - * locally to the hwmod. - */ -struct omap_hwmod_rst_info { - const char *name; - u8 rst_shift; + u16 dma_ch; }; /** @@ -248,9 +237,8 @@ struct omap_hwmod_ocp_if { #define SYSC_HAS_CLOCKACTIVITY (1 << 4) #define SYSC_HAS_SIDLEMODE (1 << 5) #define SYSC_HAS_MIDLEMODE (1 << 6) -#define SYSS_HAS_RESET_STATUS (1 << 7) +#define SYSS_MISSING (1 << 7) #define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */ -#define SYSC_HAS_RESET_STATUS (1 << 9) /* omap_hwmod_sysconfig.clockact flags */ #define CLOCKACT_TEST_BOTH 0x0 @@ -339,12 +327,10 @@ struct omap_hwmod_omap2_prcm { /** * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data * @clkctrl_reg: PRCM address of the clock control register - * @rstctrl_reg: adress of the XXX_RSTCTRL register located in the PRM * @submodule_wkdep_bit: bit shift of the WKDEP range */ struct omap_hwmod_omap4_prcm { void __iomem *clkctrl_reg; - void __iomem *rstctrl_reg; u8 submodule_wkdep_bit; }; @@ -366,10 +352,6 @@ struct omap_hwmod_omap4_prcm { * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup * HWMOD_NO_IDLEST : this module does not have idle status - this is the case * only for few initiator modules on OMAP2 & 3. - * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset. - * This is needed for devices like DSS that require optional clocks enabled - * in order to complete the reset. Optional clocks will be disabled - * again after the reset. */ #define HWMOD_SWSUP_SIDLE (1 << 0) #define HWMOD_SWSUP_MSTANDBY (1 << 1) @@ -378,7 +360,6 @@ struct omap_hwmod_omap4_prcm { #define HWMOD_NO_OCP_AUTOIDLE (1 << 4) #define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) #define HWMOD_NO_IDLEST (1 << 6) -#define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7) /* * omap_hwmod._int_flags definitions @@ -429,7 +410,7 @@ struct omap_hwmod_class { * @class: struct omap_hwmod_class * to the class of this hwmod * @od: struct omap_device currently associated with this hwmod (internal use) * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) - * @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt) + * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt) * @prcm: PRCM data pertaining to this hwmod * @main_clk: main clock: OMAP clock name * @_clk: pointer to the main struct clk (filled in at runtime) @@ -443,7 +424,7 @@ struct omap_hwmod_class { * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6) * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift * @mpu_irqs_cnt: number of @mpu_irqs - * @sdma_reqs_cnt: number of @sdma_reqs + * @sdma_chs_cnt: number of @sdma_chs * @opt_clks_cnt: number of @opt_clks * @master_cnt: number of @master entries * @slaves_cnt: number of @slave entries @@ -452,7 +433,6 @@ struct omap_hwmod_class { * @_state: internal-use hwmod state * @flags: hwmod flags (documented below) * @omap_chip: OMAP chips this hwmod is present on - * @_mutex: mutex serializing operations on this hwmod * @node: list node for hwmod list (internal use) * * @main_clk refers to this module's "main clock," which for our @@ -468,8 +448,7 @@ struct omap_hwmod { struct omap_hwmod_class *class; struct omap_device *od; struct omap_hwmod_irq_info *mpu_irqs; - struct omap_hwmod_dma_info *sdma_reqs; - struct omap_hwmod_rst_info *rst_lines; + struct omap_hwmod_dma_info *sdma_chs; union { struct omap_hwmod_omap2_prcm omap2; struct omap_hwmod_omap4_prcm omap4; @@ -482,7 +461,6 @@ struct omap_hwmod { void *dev_attr; u32 _sysc_cache; void __iomem *_mpu_rt_va; - struct mutex _mutex; struct list_head node; u16 flags; u8 _mpu_port_index; @@ -490,8 +468,7 @@ struct omap_hwmod { u8 msuspendmux_shift; u8 response_lat; u8 mpu_irqs_cnt; - u8 sdma_reqs_cnt; - u8 rst_lines_cnt; + u8 sdma_chs_cnt; u8 opt_clks_cnt; u8 masters_cnt; u8 slaves_cnt; @@ -515,10 +492,6 @@ int omap_hwmod_idle(struct omap_hwmod *oh); int _omap_hwmod_idle(struct omap_hwmod *oh); int omap_hwmod_shutdown(struct omap_hwmod *oh); -int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name); -int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name); -int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name); - int omap_hwmod_enable_clocks(struct omap_hwmod *oh); int omap_hwmod_disable_clocks(struct omap_hwmod *oh); diff --git a/trunk/arch/arm/plat-omap/include/plat/powerdomain.h b/trunk/arch/arm/plat-omap/include/plat/powerdomain.h index 9ca420dcd2f8..fb6ec74fe39e 100644 --- a/trunk/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/trunk/arch/arm/plat-omap/include/plat/powerdomain.h @@ -32,7 +32,6 @@ /* Powerdomain allowable state bitfields */ #define PWRSTS_ON (1 << PWRDM_POWER_ON) -#define PWRSTS_OFF (1 << PWRDM_POWER_OFF) #define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ (1 << PWRDM_POWER_ON)) @@ -162,6 +161,5 @@ int pwrdm_state_switch(struct powerdomain *pwrdm); int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); int pwrdm_pre_transition(void); int pwrdm_post_transition(void); -int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); #endif diff --git a/trunk/arch/arm/plat-omap/include/plat/prcm.h b/trunk/arch/arm/plat-omap/include/plat/prcm.h index ab77442e42ab..9fbd91419cd1 100644 --- a/trunk/arch/arm/plat-omap/include/plat/prcm.h +++ b/trunk/arch/arm/plat-omap/include/plat/prcm.h @@ -38,8 +38,6 @@ u32 prm_read_mod_reg(s16 module, u16 idx); void prm_write_mod_reg(u32 val, s16 module, u16 idx); u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); -u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask); -u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg); u32 cm_read_mod_reg(s16 module, u16 idx); void cm_write_mod_reg(u32 val, s16 module, u16 idx); u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); diff --git a/trunk/arch/arm/plat-omap/include/plat/sdrc.h b/trunk/arch/arm/plat-omap/include/plat/sdrc.h index efd87c8dda69..7b76f50564ba 100644 --- a/trunk/arch/arm/plat-omap/include/plat/sdrc.h +++ b/trunk/arch/arm/plat-omap/include/plat/sdrc.h @@ -147,7 +147,6 @@ struct memory_timings { }; extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode); -struct omap_sdrc_params *rx51_get_sdram_timings(void); u32 omap2xxx_sdrc_dll_is_unlocked(void); u32 omap2xxx_sdrc_reprogram(u32 level, u32 force); diff --git a/trunk/arch/arm/plat-omap/include/plat/sram.h b/trunk/arch/arm/plat-omap/include/plat/sram.h index 5905100b29a1..16a1b458d53c 100644 --- a/trunk/arch/arm/plat-omap/include/plat/sram.h +++ b/trunk/arch/arm/plat-omap/include/plat/sram.h @@ -11,6 +11,7 @@ #ifndef __ARCH_ARM_OMAP_SRAM_H #define __ARCH_ARM_OMAP_SRAM_H +extern int __init omap_sram_init(void); extern void * omap_sram_push(void * start, unsigned long size); extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); diff --git a/trunk/arch/arm/mach-omap2/timer-gp.h b/trunk/arch/arm/plat-omap/include/plat/timer-gp.h similarity index 86% rename from trunk/arch/arm/mach-omap2/timer-gp.h rename to trunk/arch/arm/plat-omap/include/plat/timer-gp.h index 5c1072c6783b..c88d346b59d9 100644 --- a/trunk/arch/arm/mach-omap2/timer-gp.h +++ b/trunk/arch/arm/plat-omap/include/plat/timer-gp.h @@ -11,6 +11,7 @@ #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H -extern int __init omap2_gp_clockevent_set_gptimer(u8 id); +int __init omap2_gp_clockevent_set_gptimer(u8 id); #endif + diff --git a/trunk/arch/arm/plat-omap/include/plat/uncompress.h b/trunk/arch/arm/plat-omap/include/plat/uncompress.h index 2769395b4ea4..ddf723be48dc 100644 --- a/trunk/arch/arm/plat-omap/include/plat/uncompress.h +++ b/trunk/arch/arm/plat-omap/include/plat/uncompress.h @@ -139,12 +139,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id) DEBUG_LL_OMAP2(1, omap3evm); DEBUG_LL_OMAP3(1, omap_3430sdp); DEBUG_LL_OMAP3(1, omap_3630sdp); - DEBUG_LL_OMAP3(1, omap3530_lv_som); - DEBUG_LL_OMAP3(1, omap3_torpedo); /* omap3 based boards using UART3 */ DEBUG_LL_OMAP3(3, cm_t35); - DEBUG_LL_OMAP3(3, cm_t3517); DEBUG_LL_OMAP3(3, igep0020); DEBUG_LL_OMAP3(3, nokia_rx51); DEBUG_LL_OMAP3(3, omap3517evm); @@ -156,7 +153,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id) /* omap4 based boards using UART3 */ DEBUG_LL_OMAP4(3, omap_4430sdp); - DEBUG_LL_OMAP4(3, omap4_panda); /* zoom2/3 external uart */ DEBUG_LL_ZOOM(omap_zoom2); diff --git a/trunk/arch/arm/plat-omap/include/plat/usb.h b/trunk/arch/arm/plat-omap/include/plat/usb.h index 667456228a12..2a9427c8cc48 100644 --- a/trunk/arch/arm/plat-omap/include/plat/usb.h +++ b/trunk/arch/arm/plat-omap/include/plat/usb.h @@ -105,7 +105,7 @@ static inline void omap1_usb_init(struct omap_usb_config *pdata) #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE) void omap2_usbfs_init(struct omap_usb_config *pdata); #else -static inline void omap2_usbfs_init(struct omap_usb_config *pdata) +static inline omap2_usbfs_init(struct omap_usb_config *pdata) { } #endif diff --git a/trunk/arch/arm/plat-omap/mcbsp.c b/trunk/arch/arm/plat-omap/mcbsp.c index b2e046990d38..e31496e35b0f 100644 --- a/trunk/arch/arm/plat-omap/mcbsp.c +++ b/trunk/arch/arm/plat-omap/mcbsp.c @@ -33,7 +33,7 @@ struct omap_mcbsp **mcbsp_ptr; int omap_mcbsp_count, omap_mcbsp_cache_size; -static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) +void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) { if (cpu_class_is_omap1()) { ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val; @@ -47,7 +47,7 @@ static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) } } -static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) +int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) { if (cpu_class_is_omap1()) { return !from_cache ? __raw_readw(mcbsp->io_base + reg) : @@ -62,12 +62,12 @@ static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) } #ifdef CONFIG_ARCH_OMAP3 -static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) +void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) { __raw_writel(val, mcbsp->st_data->io_base_st + reg); } -static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) +int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) { return __raw_readl(mcbsp->st_data->io_base_st + reg); } @@ -878,7 +878,7 @@ EXPORT_SYMBOL(omap_mcbsp_free); void omap_mcbsp_start(unsigned int id, int tx, int rx) { struct omap_mcbsp *mcbsp; - int enable_srg = 0; + int idle; u16 w; if (!omap_mcbsp_check_valid_id(id)) { @@ -893,13 +893,10 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7; mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7; - /* Only enable SRG, if McBSP is master */ - w = MCBSP_READ_CACHE(mcbsp, PCR0); - if (w & (FSXM | FSRM | CLKXM | CLKRM)) - enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | - MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); + idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | + MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); - if (enable_srg) { + if (idle) { /* Start the sample generator */ w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); @@ -922,7 +919,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) */ udelay(500); - if (enable_srg) { + if (idle) { /* Start frame sync */ w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); @@ -1648,7 +1645,7 @@ static const struct attribute_group sidetone_attr_group = { .attrs = (struct attribute **)sidetone_attrs, }; -static int __devinit omap_st_add(struct omap_mcbsp *mcbsp) +int __devinit omap_st_add(struct omap_mcbsp *mcbsp) { struct omap_mcbsp_platform_data *pdata = mcbsp->pdata; struct omap_mcbsp_st_data *st_data; diff --git a/trunk/arch/arm/plat-omap/omap_device.c b/trunk/arch/arm/plat-omap/omap_device.c index abe933cd8f09..8215b1bf40f8 100644 --- a/trunk/arch/arm/plat-omap/omap_device.c +++ b/trunk/arch/arm/plat-omap/omap_device.c @@ -82,7 +82,6 @@ #include #include #include -#include #include #include @@ -238,44 +237,6 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev) return container_of(pdev, struct omap_device, pdev); } -/** - * _add_optional_clock_alias - Add clock alias for hwmod optional clocks - * @od: struct omap_device *od - * - * For every optional clock present per hwmod per omap_device, this function - * adds an entry in the clocks list of the form - * if an entry is already present in it with the form - * - * The function is called from inside omap_device_build_ss(), after - * omap_device_register. - * - * This allows drivers to get a pointer to its optional clocks based on its role - * by calling clk_get(, ). - * - * No return value. - */ -static void _add_optional_clock_alias(struct omap_device *od, - struct omap_hwmod *oh) -{ - int i; - - for (i = 0; i < oh->opt_clks_cnt; i++) { - struct omap_hwmod_opt_clk *oc; - int r; - - oc = &oh->opt_clks[i]; - - if (!oc->_clk) - continue; - - r = clk_add_alias(oc->role, dev_name(&od->pdev.dev), - (char *)oc->clk, &od->pdev.dev); - if (r) - pr_err("omap_device: %s: clk_add_alias for %s failed\n", - dev_name(&od->pdev.dev), oc->role); - } -} - /* Public functions for use by core code */ @@ -290,11 +251,12 @@ static void _add_optional_clock_alias(struct omap_device *od, */ int omap_device_count_resources(struct omap_device *od) { + struct omap_hwmod *oh; int c = 0; int i; - for (i = 0; i < od->hwmods_cnt; i++) - c += omap_hwmod_count_resources(od->hwmods[i]); + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + c += omap_hwmod_count_resources(oh); pr_debug("omap_device: %s: counted %d total resources across %d " "hwmods\n", od->pdev.name, c, od->hwmods_cnt); @@ -321,11 +283,12 @@ int omap_device_count_resources(struct omap_device *od) */ int omap_device_fill_resources(struct omap_device *od, struct resource *res) { + struct omap_hwmod *oh; int c = 0; int i, r; - for (i = 0; i < od->hwmods_cnt; i++) { - r = omap_hwmod_fill_resources(od->hwmods[i], res); + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) { + r = omap_hwmod_fill_resources(oh, res); res += r; c += r; } @@ -450,10 +413,8 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, else ret = omap_device_register(od); - for (i = 0; i < oh_cnt; i++) { + for (i = 0; i < oh_cnt; i++) hwmods[i]->od = od; - _add_optional_clock_alias(od, hwmods[i]); - } if (ret) goto odbs_exit4; @@ -598,6 +559,7 @@ int omap_device_shutdown(struct platform_device *pdev) { int ret, i; struct omap_device *od; + struct omap_hwmod *oh; od = _find_by_pdev(pdev); @@ -610,8 +572,8 @@ int omap_device_shutdown(struct platform_device *pdev) ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT); - for (i = 0; i < od->hwmods_cnt; i++) - omap_hwmod_shutdown(od->hwmods[i]); + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + omap_hwmod_shutdown(oh); od->_state = OMAP_DEVICE_STATE_SHUTDOWN; @@ -711,10 +673,11 @@ void __iomem *omap_device_get_rt_va(struct omap_device *od) */ int omap_device_enable_hwmods(struct omap_device *od) { + struct omap_hwmod *oh; int i; - for (i = 0; i < od->hwmods_cnt; i++) - omap_hwmod_enable(od->hwmods[i]); + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + omap_hwmod_enable(oh); /* XXX pass along return value here? */ return 0; @@ -728,10 +691,11 @@ int omap_device_enable_hwmods(struct omap_device *od) */ int omap_device_idle_hwmods(struct omap_device *od) { + struct omap_hwmod *oh; int i; - for (i = 0; i < od->hwmods_cnt; i++) - omap_hwmod_idle(od->hwmods[i]); + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + omap_hwmod_idle(oh); /* XXX pass along return value here? */ return 0; @@ -746,10 +710,11 @@ int omap_device_idle_hwmods(struct omap_device *od) */ int omap_device_disable_clocks(struct omap_device *od) { + struct omap_hwmod *oh; int i; - for (i = 0; i < od->hwmods_cnt; i++) - omap_hwmod_disable_clocks(od->hwmods[i]); + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + omap_hwmod_disable_clocks(oh); /* XXX pass along return value here? */ return 0; @@ -764,10 +729,11 @@ int omap_device_disable_clocks(struct omap_device *od) */ int omap_device_enable_clocks(struct omap_device *od) { + struct omap_hwmod *oh; int i; - for (i = 0; i < od->hwmods_cnt; i++) - omap_hwmod_enable_clocks(od->hwmods[i]); + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + omap_hwmod_enable_clocks(oh); /* XXX pass along return value here? */ return 0; diff --git a/trunk/arch/arm/plat-omap/sram.c b/trunk/arch/arm/plat-omap/sram.c index dba5704b77db..226b2e858d6c 100644 --- a/trunk/arch/arm/plat-omap/sram.c +++ b/trunk/arch/arm/plat-omap/sram.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include @@ -32,8 +31,6 @@ #include #include -#include "sram.h" -#include "fb.h" #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) # include "../mach-omap2/prm.h" @@ -56,7 +53,7 @@ #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) #define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) -#if defined(CONFIG_ARCH_OMAP2PLUS) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) #define SRAM_BOOTLOADER_SZ 0x00 #else #define SRAM_BOOTLOADER_SZ 0x80 @@ -82,6 +79,12 @@ static unsigned long omap_sram_base; static unsigned long omap_sram_size; static unsigned long omap_sram_ceil; +extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart, + unsigned long sram_vstart, + unsigned long sram_size, + unsigned long pstart_avail, + unsigned long size_avail); + /* * Depending on the target RAMFS firewall setup, the public usable amount of * SRAM varies. The default accessible size for all device types is 2k. A GP @@ -90,7 +93,16 @@ static unsigned long omap_sram_ceil; */ static int is_sram_locked(void) { - if (OMAP2_DEVICE_TYPE_GP == omap_type()) { + int type = 0; + + if (cpu_is_omap44xx()) + /* Not yet supported */ + return 0; + + if (cpu_is_omap242x()) + type = omap_rev() & OMAP2_DEVICETYPE_MASK; + + if (type == GP_DEVICE) { /* RAMFW: R/W access to all initiators for all qualifier sets */ if (cpu_is_omap242x()) { __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ @@ -115,7 +127,7 @@ static int is_sram_locked(void) * to secure SRAM will hang the system. Also the SRAM is not * yet mapped at this point. */ -static void __init omap_detect_sram(void) +void __init omap_detect_sram(void) { unsigned long reserved; @@ -201,7 +213,7 @@ static struct map_desc omap_sram_io_desc[] __initdata = { /* * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early. */ -static void __init omap_map_sram(void) +void __init omap_map_sram(void) { unsigned long base; @@ -333,7 +345,7 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass) #endif #ifdef CONFIG_ARCH_OMAP2420 -static int __init omap242x_sram_init(void) +int __init omap242x_sram_init(void) { _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init, omap242x_sram_ddr_init_sz); @@ -354,7 +366,7 @@ static inline int omap242x_sram_init(void) #endif #ifdef CONFIG_ARCH_OMAP2430 -static int __init omap243x_sram_init(void) +int __init omap243x_sram_init(void) { _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init, omap243x_sram_ddr_init_sz); @@ -410,7 +422,7 @@ void omap3_sram_restore_context(void) } #endif /* CONFIG_PM */ -static int __init omap34xx_sram_init(void) +int __init omap34xx_sram_init(void) { _omap3_sram_configure_core_dpll = omap_sram_push(omap3_sram_configure_core_dpll, @@ -426,7 +438,7 @@ static inline int omap34xx_sram_init(void) #endif #ifdef CONFIG_ARCH_OMAP4 -static int __init omap44xx_sram_init(void) +int __init omap44xx_sram_init(void) { printk(KERN_ERR "FIXME: %s not implemented\n", __func__); diff --git a/trunk/arch/arm/plat-omap/sram.h b/trunk/arch/arm/plat-omap/sram.h deleted file mode 100644 index 29b43ef97f20..000000000000 --- a/trunk/arch/arm/plat-omap/sram.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __PLAT_OMAP_SRAM_H__ -#define __PLAT_OMAP_SRAM_H__ - -extern int __init omap_sram_init(void); - -#endif /* __PLAT_OMAP_SRAM_H__ */ diff --git a/trunk/drivers/mmc/host/omap_hsmmc.c b/trunk/drivers/mmc/host/omap_hsmmc.c index 53f8fa599cf5..4526d2791f29 100644 --- a/trunk/drivers/mmc/host/omap_hsmmc.c +++ b/trunk/drivers/mmc/host/omap_hsmmc.c @@ -2116,9 +2116,23 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; - mmc->caps |= mmc_slot(host).caps; - if (mmc->caps & MMC_CAP_8_BIT_DATA) + switch (mmc_slot(host).wires) { + case 8: + mmc->caps |= MMC_CAP_8_BIT_DATA; + /* Fall through */ + case 4: mmc->caps |= MMC_CAP_4_BIT_DATA; + break; + case 1: + /* Nothing to crib here */ + case 0: + /* Assuming nothing was given by board, Core use's 1-Bit */ + break; + default: + /* Completely unexpected.. Core goes with 1-Bit Width */ + dev_crit(mmc_dev(host->mmc), "Invalid width %d\n used!" + "using 1 instead\n", mmc_slot(host).wires); + } if (mmc_slot(host).nonremovable) mmc->caps |= MMC_CAP_NONREMOVABLE;