From 0b6db96c0f7b9b3555eb195c762d295325ff4481 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 27 Sep 2006 18:37:30 +0900 Subject: [PATCH] --- yaml --- r: 36327 b: refs/heads/master c: 33573c0e3243aaa38b6ad96942de85a1b713c2ff h: refs/heads/master i: 36325: 38fa77142c353538649e06241cd90b29c26cb55c 36323: 00546f757b1179918225ba9c6fa9340b91c1dff9 36319: ff5e420846d20a034e2fe06e922d50b3fd0caee2 v: v3 --- [refs] | 2 +- trunk/arch/sh/mm/cache-sh4.c | 20 +++++++++----------- 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/[refs] b/[refs] index 8118c4bcef1b..38af4efa9b2a 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f3c2575818fab45f8609e4aef2e43ab02b3a142e +refs/heads/master: 33573c0e3243aaa38b6ad96942de85a1b713c2ff diff --git a/trunk/arch/sh/mm/cache-sh4.c b/trunk/arch/sh/mm/cache-sh4.c index aa4f62f0e374..e48cc22724d9 100644 --- a/trunk/arch/sh/mm/cache-sh4.c +++ b/trunk/arch/sh/mm/cache-sh4.c @@ -221,22 +221,20 @@ void flush_cache_sigtramp(unsigned long addr) static inline void flush_cache_4096(unsigned long start, unsigned long phys) { + unsigned long flags, exec_offset = 0; + /* * All types of SH-4 require PC to be in P2 to operate on the I-cache. * Some types of SH-4 require PC to be in P2 to operate on the D-cache. */ if ((cpu_data->flags & CPU_HAS_P2_FLUSH_BUG) || - (start < CACHE_OC_ADDRESS_ARRAY)) { - unsigned long flags; - - local_irq_save(flags); - __flush_cache_4096(start | SH_CACHE_ASSOC, - P1SEGADDR(phys), 0x20000000); - local_irq_restore(flags); - } else { - __flush_cache_4096(start | SH_CACHE_ASSOC, - P1SEGADDR(phys), 0); - } + (start < CACHE_OC_ADDRESS_ARRAY)) + exec_offset = 0x20000000; + + local_irq_save(flags); + __flush_cache_4096(start | SH_CACHE_ASSOC, + P1SEGADDR(phys), exec_offset); + local_irq_restore(flags); } /*