From 0ba5870de0ce94b28c30919cc2b92b3c10561ce7 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Thu, 13 Oct 2011 14:57:31 +0800 Subject: [PATCH] --- yaml --- r: 270858 b: refs/heads/master c: edf413f689e930011bf39ec726f704af99d7263b h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/sound/soc/codecs/sta32x.c | 28 +++++++++++++--------------- 2 files changed, 14 insertions(+), 16 deletions(-) diff --git a/[refs] b/[refs] index e08af972ceaf..4217a8136729 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f0bbc2b55f47f93286bb1b9ddbdb8ffed3572064 +refs/heads/master: edf413f689e930011bf39ec726f704af99d7263b diff --git a/trunk/sound/soc/codecs/sta32x.c b/trunk/sound/soc/codecs/sta32x.c index 754b3ff9afa5..bb82408ab8e1 100644 --- a/trunk/sound/soc/codecs/sta32x.c +++ b/trunk/sound/soc/codecs/sta32x.c @@ -756,21 +756,19 @@ static int sta32x_probe(struct snd_soc_codec *codec) return ret; } - /* preserve reset values of reserved register bits */ - snd_soc_cache_write(codec, STA32X_CONFC, - codec->hw_read(codec, STA32X_CONFC)); - snd_soc_cache_write(codec, STA32X_CONFE, - codec->hw_read(codec, STA32X_CONFE)); - snd_soc_cache_write(codec, STA32X_CONFF, - codec->hw_read(codec, STA32X_CONFF)); - snd_soc_cache_write(codec, STA32X_MMUTE, - codec->hw_read(codec, STA32X_MMUTE)); - snd_soc_cache_write(codec, STA32X_AUTO1, - codec->hw_read(codec, STA32X_AUTO1)); - snd_soc_cache_write(codec, STA32X_AUTO3, - codec->hw_read(codec, STA32X_AUTO3)); - snd_soc_cache_write(codec, STA32X_C3CFG, - codec->hw_read(codec, STA32X_C3CFG)); + /* Chip documentation explicitly requires that the reset values + * of reserved register bits are left untouched. + * Write the register default value to cache for reserved registers, + * so the write to the these registers are suppressed by the cache + * restore code when it skips writes of default registers. + */ + snd_soc_cache_write(codec, STA32X_CONFC, 0xc2); + snd_soc_cache_write(codec, STA32X_CONFE, 0xc2); + snd_soc_cache_write(codec, STA32X_CONFF, 0x5c); + snd_soc_cache_write(codec, STA32X_MMUTE, 0x10); + snd_soc_cache_write(codec, STA32X_AUTO1, 0x60); + snd_soc_cache_write(codec, STA32X_AUTO3, 0x00); + snd_soc_cache_write(codec, STA32X_C3CFG, 0x40); /* FIXME enable thermal warning adjustment and recovery */ snd_soc_update_bits(codec, STA32X_CONFA,