diff --git a/[refs] b/[refs] index a9f11e6e6d9e..c75e87e24230 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 5260562754c0aa4b95eebb1f851eaccce7286365 +refs/heads/master: a5f42a6bc51454137b918f67310168c27d1dd1de diff --git a/trunk/Documentation/filesystems/nfs/00-INDEX b/trunk/Documentation/filesystems/nfs/00-INDEX index 3225a5662114..2f68cd688769 100644 --- a/trunk/Documentation/filesystems/nfs/00-INDEX +++ b/trunk/Documentation/filesystems/nfs/00-INDEX @@ -14,5 +14,3 @@ nfsroot.txt - short guide on setting up a diskless box with NFS root filesystem. rpc-cache.txt - introduction to the caching mechanisms in the sunrpc layer. -idmapper.txt - - information for configuring request-keys to be used by idmapper diff --git a/trunk/Documentation/filesystems/nfs/idmapper.txt b/trunk/Documentation/filesystems/nfs/idmapper.txt deleted file mode 100644 index c3852041a21f..000000000000 --- a/trunk/Documentation/filesystems/nfs/idmapper.txt +++ /dev/null @@ -1,67 +0,0 @@ - -========= -ID Mapper -========= -Id mapper is used by NFS to translate user and group ids into names, and to -translate user and group names into ids. Part of this translation involves -performing an upcall to userspace to request the information. Id mapper will -user request-key to perform this upcall and cache the result. The program -/usr/sbin/nfs.upcall should be called by request-key, and will perform the -translation and initialize a key with the resulting information. - - NFS_USE_NEW_IDMAPPER must be selected when configuring the kernel to use this - feature. - -=========== -Configuring -=========== -The file /etc/request-key.conf will need to be modified so /sbin/request-key can -direct the upcall. The following line should be added: - -#OP TYPE DESCRIPTION CALLOUT INFO PROGRAM ARG1 ARG2 ARG3 ... -#====== ======= =============== =============== =============================== -create id_resolver * * /usr/sbin/nfs.upcall %k %d 600 - -This will direct all id_resolver requests to the program /usr/sbin/nfs.upcall. -The last parameter, 600, defines how many seconds into the future the key will -expire. This parameter is optional for /usr/sbin/nfs.upcall. When the timeout -is not specified, nfs.upcall will default to 600 seconds. - -id mapper uses for key descriptions: - uid: Find the UID for the given user - gid: Find the GID for the given group - user: Find the user name for the given UID - group: Find the group name for the given GID - -You can handle any of these individually, rather than using the generic upcall -program. If you would like to use your own program for a uid lookup then you -would edit your request-key.conf so it look similar to this: - -#OP TYPE DESCRIPTION CALLOUT INFO PROGRAM ARG1 ARG2 ARG3 ... -#====== ======= =============== =============== =============================== -create id_resolver uid:* * /some/other/program %k %d 600 -create id_resolver * * /usr/sbin/nfs.upcall %k %d 600 - -Notice that the new line was added above the line for the generic program. -request-key will find the first matching line and corresponding program. In -this case, /some/other/program will handle all uid lookups and -/usr/sbin/nfs.upcall will handle gid, user, and group lookups. - -See for more information about the -request-key function. - - -========== -nfs.upcall -========== -nfs.upcall is designed to be called by request-key, and should not be run "by -hand". This program takes two arguments, a serialized key and a key -description. The serialized key is first converted into a key_serial_t, and -then passed as an argument to keyctl_instantiate (both are part of keyutils.h). - -The actual lookups are performed by functions found in nfsidmap.h. nfs.upcall -determines the correct function to call by looking at the first part of the -description string. For example, a uid lookup description will appear as -"uid:user@domain". - -nfs.upcall will return 0 if the key was instantiated, and non-zero otherwise. diff --git a/trunk/Documentation/filesystems/nfs/nfsroot.txt b/trunk/Documentation/filesystems/nfs/nfsroot.txt index 90c71c6f0d00..f2430a7974e1 100644 --- a/trunk/Documentation/filesystems/nfs/nfsroot.txt +++ b/trunk/Documentation/filesystems/nfs/nfsroot.txt @@ -159,28 +159,6 @@ ip=:::::: Default: any -nfsrootdebug - - This parameter enables debugging messages to appear in the kernel - log at boot time so that administrators can verify that the correct - NFS mount options, server address, and root path are passed to the - NFS client. - - -rdinit= - - To specify which file contains the program that starts system - initialization, administrators can use this command line parameter. - The default value of this parameter is "/init". If the specified - file exists and the kernel can execute it, root filesystem related - kernel command line parameters, including `nfsroot=', are ignored. - - A description of the process of mounting the root file system can be - found in: - - Documentation/early-userspace/README - - 3.) Boot Loader diff --git a/trunk/Documentation/kernel-parameters.txt b/trunk/Documentation/kernel-parameters.txt index 4bc2f3c3da5b..b660085dcc69 100644 --- a/trunk/Documentation/kernel-parameters.txt +++ b/trunk/Documentation/kernel-parameters.txt @@ -1541,15 +1541,12 @@ and is between 256 and 4096 characters. It is defined in the file 1 to enable accounting Default value is 0. - nfsaddrs= [NFS] Deprecated. Use ip= instead. + nfsaddrs= [NFS] See Documentation/filesystems/nfs/nfsroot.txt. nfsroot= [NFS] nfs root filesystem for disk-less boxes. See Documentation/filesystems/nfs/nfsroot.txt. - nfsrootdebug [NFS] enable nfsroot debugging messages. - See Documentation/filesystems/nfs/nfsroot.txt. - nfs.callback_tcpport= [NFS] set the TCP port on which the NFSv4 callback channel should listen. diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index f401b92a99f5..b64e465ac49c 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -831,7 +831,7 @@ config ARCH_OMAP select GENERIC_CLOCKEVENTS select ARCH_HAS_HOLES_MEMORYMODEL help - Support for TI's OMAP platform (OMAP1/2/3/4). + Support for TI's OMAP platform (OMAP1 and OMAP2). config PLAT_SPEAR bool "ST SPEAr" diff --git a/trunk/arch/arm/configs/n8x0_defconfig b/trunk/arch/arm/configs/n8x0_defconfig new file mode 100644 index 000000000000..56aebb69411d --- /dev/null +++ b/trunk/arch/arm/configs/n8x0_defconfig @@ -0,0 +1,94 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_OMAP=y +CONFIG_ARCH_OMAP2=y +CONFIG_OMAP_RESET_CLOCKS=y +# CONFIG_OMAP_MUX is not set +# CONFIG_OMAP_MCBSP is not set +CONFIG_OMAP_MBOX_FWK=y +CONFIG_OMAP_32K_TIMER=y +CONFIG_ARCH_OMAP2420=y +CONFIG_MACH_NOKIA_N8X0=y +CONFIG_AEABI=y +CONFIG_LEDS=y +CONFIG_ZBOOT_ROM_TEXT=0x10C08000 +CONFIG_ZBOOT_ROM_BSS=0x10200000 +CONFIG_CMDLINE="root=/dev/mmcblk0p2 console=ttyS2,115200n8 debug earlyprintk rootwait" +CONFIG_FPE_NWFPE=y +CONFIG_VFP=y +CONFIG_PM=y +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_IPV6 is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_ONENAND=y +CONFIG_MTD_ONENAND_OMAP2=y +CONFIG_MTD_ONENAND_OTP=y +CONFIG_BLK_DEV_RAM=y +# CONFIG_MISC_DEVICES is not set +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_OMAP=y +CONFIG_SPI=y +CONFIG_SPI_OMAP24XX=y +# CONFIG_HWMON is not set +CONFIG_MENELAUS=y +CONFIG_REGULATOR=y +# CONFIG_VGA_CONSOLE is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_SUSPEND=y +# CONFIG_USB_OTG_WHITELIST is not set +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_OTG=y +CONFIG_USB_GADGET_MUSB_HDRC=y +# CONFIG_MUSB_PIO_ONLY is not set +CONFIG_USB_MUSB_DEBUG=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DEBUG=y +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_ETH=m +CONFIG_USB_ETH_EEM=y +CONFIG_MMC=y +CONFIG_MMC_OMAP=y +CONFIG_EXT3_FS=y +CONFIG_INOTIFY=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_LZO=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_INFO=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +CONFIG_CRC_CCITT=y diff --git a/trunk/arch/arm/configs/omap2plus_defconfig b/trunk/arch/arm/configs/omap3_defconfig similarity index 90% rename from trunk/arch/arm/configs/omap2plus_defconfig rename to trunk/arch/arm/configs/omap3_defconfig index ccedde1371c3..5db9a6be2054 100644 --- a/trunk/arch/arm/configs/omap2plus_defconfig +++ b/trunk/arch/arm/configs/omap3_defconfig @@ -53,18 +53,18 @@ CONFIG_MACH_SBC3530=y CONFIG_MACH_OMAP_3630SDP=y CONFIG_MACH_OMAP_4430SDP=y CONFIG_ARM_THUMBEE=y -CONFIG_ARM_L1_CACHE_SHIFT=5 -CONFIG_ARM_ERRATA_411920=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y -CONFIG_SMP=y -# CONFIG_LOCAL_TIMERS is not set CONFIG_AEABI=y CONFIG_LEDS=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200" +CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyS2,115200" CONFIG_KEXEC=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_FPE_NWFPE=y CONFIG_VFP=y CONFIG_NEON=y @@ -87,23 +87,23 @@ CONFIG_IP_PNP_RARP=y # CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_NETFILTER=y -CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=y CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m +CONFIG_BT_BNEP=y CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m -CONFIG_BT_HCIUART=m +CONFIG_BT_HIDP=y +CONFIG_BT_HCIUART=y CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBPA10X=m -CONFIG_CFG80211=m -CONFIG_MAC80211=m +CONFIG_BT_HCIBCM203X=y +CONFIG_BT_HCIBPA10X=y +CONFIG_CFG80211=y +CONFIG_MAC80211=y CONFIG_MAC80211_RC_PID=y CONFIG_MAC80211_RC_DEFAULT_PID=y CONFIG_MAC80211_LEDS=y @@ -137,11 +137,9 @@ CONFIG_SMSC_PHY=y CONFIG_NET_ETHERNET=y CONFIG_SMC91X=y CONFIG_SMSC911X=y -CONFIG_KS8851=y -CONFIG_KS8851_MLL=y -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_USB=m -CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS=y +CONFIG_LIBERTAS_USB=y +CONFIG_LIBERTAS_SDIO=y CONFIG_LIBERTAS_DEBUG=y CONFIG_USB_USBNET=y CONFIG_USB_ALI_M5632=y @@ -203,8 +201,8 @@ CONFIG_FONTS=y CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_LOGO=y -CONFIG_SOUND=m -CONFIG_SND=m +CONFIG_SOUND=y +CONFIG_SND=y CONFIG_SND_MIXER_OSS=y CONFIG_SND_PCM_OSS=y CONFIG_SND_VERBOSE_PRINTK=y @@ -220,9 +218,9 @@ CONFIG_USB_DEVICEFS=y CONFIG_USB_SUSPEND=y # CONFIG_USB_OTG_WHITELIST is not set CONFIG_USB_MON=y -# CONFIG_USB_MUSB_HDRC is not set -# CONFIG_USB_MUSB_OTG is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_OTG=y +CONFIG_USB_GADGET_MUSB_HDRC=y CONFIG_USB_MUSB_DEBUG=y CONFIG_USB_WDM=y CONFIG_USB_STORAGE=y @@ -278,11 +276,12 @@ CONFIG_DEBUG_KERNEL=y CONFIG_SCHEDSTATS=y CONFIG_TIMER_STATS=y CONFIG_PROVE_LOCKING=y -# CONFIG_LOCK_STAT is not set +CONFIG_LOCK_STAT=y CONFIG_DEBUG_SPINLOCK_SLEEP=y # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO=y # CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_DEBUG_LL=y CONFIG_SECURITY=y CONFIG_CRYPTO_MICHAEL_MIC=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/trunk/arch/arm/configs/omap_4430sdp_defconfig b/trunk/arch/arm/configs/omap_4430sdp_defconfig new file mode 100644 index 000000000000..14c1e18c648f --- /dev/null +++ b/trunk/arch/arm/configs/omap_4430sdp_defconfig @@ -0,0 +1,125 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_ELF_CORE is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_OMAP=y +CONFIG_ARCH_OMAP4=y +# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set +# CONFIG_ARCH_OMAP2 is not set +# CONFIG_ARCH_OMAP3 is not set +# CONFIG_OMAP_MUX is not set +CONFIG_OMAP_32K_TIMER=y +CONFIG_OMAP_DM_TIMER=y +CONFIG_MACH_OMAP_4430SDP=y +# CONFIG_ARM_THUMB is not set +CONFIG_PL310_ERRATA_588369=y +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +# CONFIG_LOCAL_TIMERS is not set +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS2,115200n8 initrd=0x81600000,20M ramdisk_size=20480" +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_FW_LOADER is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_MISC_DEVICES is not set +CONFIG_NETDEVICES=y +CONFIG_NET_ETHERNET=y +CONFIG_KS8851=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_OMAP=y +CONFIG_SPI=y +CONFIG_SPI_OMAP24XX=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_OMAP_WATCHDOG=y +CONFIG_TWL4030_CORE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_TWL4030=y +# CONFIG_VGA_CONSOLE is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_OMAP_HS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_TWL4030=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_INOTIFY=y +CONFIG_QUOTA=y +CONFIG_QFMT_V2=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DETECT_SOFTLOCKUP is not set +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRC_CCITT=y +CONFIG_CRC_T10DIF=y +CONFIG_LIBCRC32C=y diff --git a/trunk/arch/arm/configs/omap_generic_2420_defconfig b/trunk/arch/arm/configs/omap_generic_2420_defconfig new file mode 100644 index 000000000000..ac08e51180dd --- /dev/null +++ b/trunk/arch/arm/configs/omap_generic_2420_defconfig @@ -0,0 +1,37 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_OMAP=y +CONFIG_ARCH_OMAP2=y +# CONFIG_OMAP_MUX is not set +CONFIG_MACH_OMAP_GENERIC=y +CONFIG_ARCH_OMAP2420=y +CONFIG_LEDS=y +CONFIG_ZBOOT_ROM_TEXT=0x10C08000 +CONFIG_ZBOOT_ROM_BSS=0x10200000 +CONFIG_FPE_NWFPE=y +CONFIG_BLK_DEV_RAM=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y +CONFIG_VIDEO_OUTPUT_CONTROL=m +# CONFIG_VGA_CONSOLE is not set +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_INOTIFY=y +CONFIG_ROMFS_FS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_LL=y +CONFIG_CRC_CCITT=y diff --git a/trunk/arch/arm/mach-omap1/Makefile b/trunk/arch/arm/mach-omap1/Makefile index 9a304d854e33..facfaeb1ae5c 100644 --- a/trunk/arch/arm/mach-omap1/Makefile +++ b/trunk/arch/arm/mach-omap1/Makefile @@ -12,7 +12,7 @@ obj-$(CONFIG_OMAP_MPU_TIMER) += time.o obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o # Power Management -obj-$(CONFIG_PM) += pm.o sleep.o pm_bus.o +obj-$(CONFIG_PM) += pm.o sleep.o # DSP obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o diff --git a/trunk/arch/arm/mach-omap1/board-ams-delta.c b/trunk/arch/arm/mach-omap1/board-ams-delta.c index 1d4163b9f0b7..73c86392fcd3 100644 --- a/trunk/arch/arm/mach-omap1/board-ams-delta.c +++ b/trunk/arch/arm/mach-omap1/board-ams-delta.c @@ -16,12 +16,9 @@ #include #include #include -#include #include #include -#include - #include #include #include @@ -35,7 +32,6 @@ #include #include #include -#include #include @@ -217,56 +213,10 @@ static struct platform_device ams_delta_led_device = { .id = -1 }; -static struct i2c_board_info ams_delta_camera_board_info[] = { - { - I2C_BOARD_INFO("ov6650", 0x60), - }, -}; - -#ifdef CONFIG_LEDS_TRIGGERS -DEFINE_LED_TRIGGER(ams_delta_camera_led_trigger); - -static int ams_delta_camera_power(struct device *dev, int power) -{ - /* - * turn on camera LED - */ - if (power) - led_trigger_event(ams_delta_camera_led_trigger, LED_FULL); - else - led_trigger_event(ams_delta_camera_led_trigger, LED_OFF); - return 0; -} -#else -#define ams_delta_camera_power NULL -#endif - -static struct soc_camera_link __initdata ams_delta_iclink = { - .bus_id = 0, /* OMAP1 SoC camera bus */ - .i2c_adapter_id = 1, - .board_info = &ams_delta_camera_board_info[0], - .module_name = "ov6650", - .power = ams_delta_camera_power, -}; - -static struct platform_device ams_delta_camera_device = { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { - .platform_data = &ams_delta_iclink, - }, -}; - -static struct omap1_cam_platform_data ams_delta_camera_platform_data = { - .camexclk_khz = 12000, /* default 12MHz clock, no extra DPLL */ - .lclk_khz_max = 1334, /* results in 5fps CIF, 10fps QCIF */ -}; - static struct platform_device *ams_delta_devices[] __initdata = { &ams_delta_kp_device, &ams_delta_lcd_device, &ams_delta_led_device, - &ams_delta_camera_device, }; static void __init ams_delta_init(void) @@ -275,20 +225,6 @@ static void __init ams_delta_init(void) omap_cfg_reg(UART1_TX); omap_cfg_reg(UART1_RTS); - /* parallel camera interface */ - omap_cfg_reg(H19_1610_CAM_EXCLK); - omap_cfg_reg(J15_1610_CAM_LCLK); - omap_cfg_reg(L18_1610_CAM_VS); - omap_cfg_reg(L15_1610_CAM_HS); - omap_cfg_reg(L19_1610_CAM_D0); - omap_cfg_reg(K14_1610_CAM_D1); - omap_cfg_reg(K15_1610_CAM_D2); - omap_cfg_reg(K19_1610_CAM_D3); - omap_cfg_reg(K18_1610_CAM_D4); - omap_cfg_reg(J14_1610_CAM_D5); - omap_cfg_reg(J19_1610_CAM_D6); - omap_cfg_reg(J18_1610_CAM_D7); - iotable_init(ams_delta_io_desc, ARRAY_SIZE(ams_delta_io_desc)); omap_board_config = ams_delta_config; @@ -300,11 +236,6 @@ static void __init ams_delta_init(void) ams_delta_latch2_write(~0, 0); omap1_usb_init(&ams_delta_usb_config); - omap1_set_camera_info(&ams_delta_camera_platform_data); -#ifdef CONFIG_LEDS_TRIGGERS - led_trigger_register_simple("ams_delta_camera", - &ams_delta_camera_led_trigger); -#endif platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); #ifdef CONFIG_AMS_DELTA_FIQ diff --git a/trunk/arch/arm/mach-omap1/board-h2-mmc.c b/trunk/arch/arm/mach-omap1/board-h2-mmc.c index f2fc43d8382b..b30c4990744d 100644 --- a/trunk/arch/arm/mach-omap1/board-h2-mmc.c +++ b/trunk/arch/arm/mach-omap1/board-h2-mmc.c @@ -58,7 +58,8 @@ static struct omap_mmc_platform_data mmc1_data = { .dma_mask = 0xffffffff, .slots[0] = { .set_power = mmc_set_power, - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | + MMC_VDD_32_33 | MMC_VDD_33_34, .name = "mmcblk", }, }; diff --git a/trunk/arch/arm/mach-omap1/board-h3-mmc.c b/trunk/arch/arm/mach-omap1/board-h3-mmc.c index 2098525e7cc5..54b0f063e263 100644 --- a/trunk/arch/arm/mach-omap1/board-h3-mmc.c +++ b/trunk/arch/arm/mach-omap1/board-h3-mmc.c @@ -40,7 +40,8 @@ static struct omap_mmc_platform_data mmc1_data = { .dma_mask = 0xffffffff, .slots[0] = { .set_power = mmc_set_power, - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | + MMC_VDD_32_33 | MMC_VDD_33_34, .name = "mmcblk", }, }; diff --git a/trunk/arch/arm/mach-omap1/board-htcherald.c b/trunk/arch/arm/mach-omap1/board-htcherald.c index 071af3e47789..86afb2952225 100644 --- a/trunk/arch/arm/mach-omap1/board-htcherald.c +++ b/trunk/arch/arm/mach-omap1/board-htcherald.c @@ -30,13 +30,6 @@ #include #include #include -#include -#include -#include -#include -#include -#include -#include #include #include @@ -46,7 +39,6 @@ #include #include #include -#include #include @@ -60,123 +52,13 @@ #define OMAP_LCDC_CTRL_LCD_EN (1 << 0) #define OMAP_LCDC_STAT_DONE (1 << 0) -/* GPIO definitions for the power button and keyboard slide switch */ -#define HTCHERALD_GPIO_POWER 139 -#define HTCHERALD_GPIO_SLIDE 174 -#define HTCHERALD_GIRQ_BTNS 141 - -/* GPIO definitions for the touchscreen */ -#define HTCHERALD_GPIO_TS 76 - -/* HTCPLD definitions */ - -/* - * CPLD Logic - * - * Chip 3 - 0x03 - * - * Function 7 6 5 4 3 2 1 0 - * ------------------------------------ - * DPAD light x x x x x x x 1 - * SoundDev x x x x 1 x x x - * Screen white 1 x x x x x x x - * MMC power on x x x x x 1 x x - * Happy times (n) 0 x x x x 1 x x - * - * Chip 4 - 0x04 - * - * Function 7 6 5 4 3 2 1 0 - * ------------------------------------ - * Keyboard light x x x x x x x 1 - * LCD Bright (4) x x x x x 1 1 x - * LCD Bright (3) x x x x x 0 1 x - * LCD Bright (2) x x x x x 1 0 x - * LCD Bright (1) x x x x x 0 0 x - * LCD Off x x x x 0 x x x - * LCD image (fb) 1 x x x x x x x - * LCD image (white) 0 x x x x x x x - * Caps lock LED x x 1 x x x x x - * - * Chip 5 - 0x05 - * - * Function 7 6 5 4 3 2 1 0 - * ------------------------------------ - * Red (solid) x x x x x 1 x x - * Red (flash) x x x x x x 1 x - * Green (GSM flash) x x x x 1 x x x - * Green (GSM solid) x x x 1 x x x x - * Green (wifi flash) x x 1 x x x x x - * Blue (bt flash) x 1 x x x x x x - * DPAD Int Enable 1 x x x x x x 0 - * - * (Combinations of the above can be made for different colors.) - * The direction pad interrupt enable must be set each time the - * interrupt is handled. - * - * Chip 6 - 0x06 - * - * Function 7 6 5 4 3 2 1 0 - * ------------------------------------ - * Vibrator x x x x 1 x x x - * Alt LED x x x 1 x x x x - * Screen white 1 x x x x x x x - * Screen white x x 1 x x x x x - * Screen white x 0 x x x x x x - * Enable kbd dpad x x x x x x 0 x - * Happy Times 0 1 0 x x x 0 x - */ - -/* - * HTCPLD GPIO lines start 16 after OMAP_MAX_GPIO_LINES to account - * for the 16 MPUIO lines. - */ -#define HTCPLD_GPIO_START_OFFSET (OMAP_MAX_GPIO_LINES + 16) -#define HTCPLD_IRQ(chip, offset) (OMAP_IRQ_END + 8 * (chip) + (offset)) -#define HTCPLD_BASE(chip, offset) \ - (HTCPLD_GPIO_START_OFFSET + 8 * (chip) + (offset)) - -#define HTCPLD_GPIO_LED_DPAD HTCPLD_BASE(0, 0) -#define HTCPLD_GPIO_LED_KBD HTCPLD_BASE(1, 0) -#define HTCPLD_GPIO_LED_CAPS HTCPLD_BASE(1, 5) -#define HTCPLD_GPIO_LED_RED_FLASH HTCPLD_BASE(2, 1) -#define HTCPLD_GPIO_LED_RED_SOLID HTCPLD_BASE(2, 2) -#define HTCPLD_GPIO_LED_GREEN_FLASH HTCPLD_BASE(2, 3) -#define HTCPLD_GPIO_LED_GREEN_SOLID HTCPLD_BASE(2, 4) -#define HTCPLD_GPIO_LED_WIFI HTCPLD_BASE(2, 5) -#define HTCPLD_GPIO_LED_BT HTCPLD_BASE(2, 6) -#define HTCPLD_GPIO_LED_VIBRATE HTCPLD_BASE(3, 3) -#define HTCPLD_GPIO_LED_ALT HTCPLD_BASE(3, 4) - -#define HTCPLD_GPIO_RIGHT_KBD HTCPLD_BASE(6, 7) -#define HTCPLD_GPIO_UP_KBD HTCPLD_BASE(6, 6) -#define HTCPLD_GPIO_LEFT_KBD HTCPLD_BASE(6, 5) -#define HTCPLD_GPIO_DOWN_KBD HTCPLD_BASE(6, 4) - -#define HTCPLD_GPIO_RIGHT_DPAD HTCPLD_BASE(7, 7) -#define HTCPLD_GPIO_UP_DPAD HTCPLD_BASE(7, 6) -#define HTCPLD_GPIO_LEFT_DPAD HTCPLD_BASE(7, 5) -#define HTCPLD_GPIO_DOWN_DPAD HTCPLD_BASE(7, 4) -#define HTCPLD_GPIO_ENTER_DPAD HTCPLD_BASE(7, 3) +static struct omap_lcd_config htcherald_lcd_config __initdata = { + .ctrl_name = "internal", +}; -/* - * The htcpld chip requires a gpio write to a specific line - * to re-enable interrupts after one has occurred. - */ -#define HTCPLD_GPIO_INT_RESET_HI HTCPLD_BASE(2, 7) -#define HTCPLD_GPIO_INT_RESET_LO HTCPLD_BASE(2, 0) - -/* Chip 5 */ -#define HTCPLD_IRQ_RIGHT_KBD HTCPLD_IRQ(0, 7) -#define HTCPLD_IRQ_UP_KBD HTCPLD_IRQ(0, 6) -#define HTCPLD_IRQ_LEFT_KBD HTCPLD_IRQ(0, 5) -#define HTCPLD_IRQ_DOWN_KBD HTCPLD_IRQ(0, 4) - -/* Chip 6 */ -#define HTCPLD_IRQ_RIGHT_DPAD HTCPLD_IRQ(1, 7) -#define HTCPLD_IRQ_UP_DPAD HTCPLD_IRQ(1, 6) -#define HTCPLD_IRQ_LEFT_DPAD HTCPLD_IRQ(1, 5) -#define HTCPLD_IRQ_DOWN_DPAD HTCPLD_IRQ(1, 4) -#define HTCPLD_IRQ_ENTER_DPAD HTCPLD_IRQ(1, 3) +static struct omap_board_config_kernel htcherald_config[] __initdata = { + { OMAP_TAG_LCD, &htcherald_lcd_config }, +}; /* Keyboard definition */ @@ -258,129 +140,6 @@ static struct platform_device kp_device = { .resource = kp_resources, }; -/* GPIO buttons for keyboard slide and power button */ -static struct gpio_keys_button herald_gpio_keys_table[] = { - {BTN_0, HTCHERALD_GPIO_POWER, 1, "POWER", EV_KEY, 1, 20}, - {SW_LID, HTCHERALD_GPIO_SLIDE, 0, "SLIDE", EV_SW, 1, 20}, - - {KEY_LEFT, HTCPLD_GPIO_LEFT_KBD, 1, "LEFT", EV_KEY, 1, 20}, - {KEY_RIGHT, HTCPLD_GPIO_RIGHT_KBD, 1, "RIGHT", EV_KEY, 1, 20}, - {KEY_UP, HTCPLD_GPIO_UP_KBD, 1, "UP", EV_KEY, 1, 20}, - {KEY_DOWN, HTCPLD_GPIO_DOWN_KBD, 1, "DOWN", EV_KEY, 1, 20}, - - {KEY_LEFT, HTCPLD_GPIO_LEFT_DPAD, 1, "DLEFT", EV_KEY, 1, 20}, - {KEY_RIGHT, HTCPLD_GPIO_RIGHT_DPAD, 1, "DRIGHT", EV_KEY, 1, 20}, - {KEY_UP, HTCPLD_GPIO_UP_DPAD, 1, "DUP", EV_KEY, 1, 20}, - {KEY_DOWN, HTCPLD_GPIO_DOWN_DPAD, 1, "DDOWN", EV_KEY, 1, 20}, - {KEY_ENTER, HTCPLD_GPIO_ENTER_DPAD, 1, "DENTER", EV_KEY, 1, 20}, -}; - -static struct gpio_keys_platform_data herald_gpio_keys_data = { - .buttons = herald_gpio_keys_table, - .nbuttons = ARRAY_SIZE(herald_gpio_keys_table), - .rep = 1, -}; - -static struct platform_device herald_gpiokeys_device = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &herald_gpio_keys_data, - }, -}; - -/* LEDs for the Herald. These connect to the HTCPLD GPIO device. */ -static struct gpio_led gpio_leds[] = { - {"dpad", NULL, HTCPLD_GPIO_LED_DPAD, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"kbd", NULL, HTCPLD_GPIO_LED_KBD, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"vibrate", NULL, HTCPLD_GPIO_LED_VIBRATE, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"green_solid", NULL, HTCPLD_GPIO_LED_GREEN_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"green_flash", NULL, HTCPLD_GPIO_LED_GREEN_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"red_solid", "mmc0", HTCPLD_GPIO_LED_RED_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"red_flash", NULL, HTCPLD_GPIO_LED_RED_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"wifi", NULL, HTCPLD_GPIO_LED_WIFI, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"bt", NULL, HTCPLD_GPIO_LED_BT, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"caps", NULL, HTCPLD_GPIO_LED_CAPS, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"alt", NULL, HTCPLD_GPIO_LED_ALT, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, -}; - -static struct gpio_led_platform_data gpio_leds_data = { - .leds = gpio_leds, - .num_leds = ARRAY_SIZE(gpio_leds), -}; - -static struct platform_device gpio_leds_device = { - .name = "leds-gpio", - .id = 0, - .dev = { - .platform_data = &gpio_leds_data, - }, -}; - -/* HTC PLD chips */ - -static struct resource htcpld_resources[] = { - [0] = { - .start = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS), - .end = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS), - .flags = IORESOURCE_IRQ, - }, -}; - -struct htcpld_chip_platform_data htcpld_chips[] = { - [0] = { - .addr = 0x03, - .reset = 0x04, - .num_gpios = 8, - .gpio_out_base = HTCPLD_BASE(0, 0), - .gpio_in_base = HTCPLD_BASE(4, 0), - }, - [1] = { - .addr = 0x04, - .reset = 0x8e, - .num_gpios = 8, - .gpio_out_base = HTCPLD_BASE(1, 0), - .gpio_in_base = HTCPLD_BASE(5, 0), - }, - [2] = { - .addr = 0x05, - .reset = 0x80, - .num_gpios = 8, - .gpio_out_base = HTCPLD_BASE(2, 0), - .gpio_in_base = HTCPLD_BASE(6, 0), - .irq_base = HTCPLD_IRQ(0, 0), - .num_irqs = 8, - }, - [3] = { - .addr = 0x06, - .reset = 0x40, - .num_gpios = 8, - .gpio_out_base = HTCPLD_BASE(3, 0), - .gpio_in_base = HTCPLD_BASE(7, 0), - .irq_base = HTCPLD_IRQ(1, 0), - .num_irqs = 8, - }, -}; - -struct htcpld_core_platform_data htcpld_pfdata = { - .int_reset_gpio_hi = HTCPLD_GPIO_INT_RESET_HI, - .int_reset_gpio_lo = HTCPLD_GPIO_INT_RESET_LO, - .i2c_adapter_id = 1, - - .chip = htcpld_chips, - .num_chip = ARRAY_SIZE(htcpld_chips), -}; - -static struct platform_device htcpld_device = { - .name = "i2c-htcpld", - .id = -1, - .resource = htcpld_resources, - .num_resources = ARRAY_SIZE(htcpld_resources), - .dev = { - .platform_data = &htcpld_pfdata, - }, -}; - /* USB Device */ static struct omap_usb_config htcherald_usb_config __initdata = { .otg = 0, @@ -391,71 +150,14 @@ static struct omap_usb_config htcherald_usb_config __initdata = { }; /* LCD Device resources */ -static struct omap_lcd_config htcherald_lcd_config __initdata = { - .ctrl_name = "internal", -}; - -static struct omap_board_config_kernel htcherald_config[] __initdata = { - { OMAP_TAG_LCD, &htcherald_lcd_config }, -}; - static struct platform_device lcd_device = { .name = "lcd_htcherald", .id = -1, }; -/* MMC Card */ -#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) -static struct omap_mmc_platform_data htc_mmc1_data = { - .nr_slots = 1, - .switch_slot = NULL, - .slots[0] = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .name = "mmcblk", - .nomux = 1, - .wires = 4, - .switch_pin = -1, - }, -}; - -static struct omap_mmc_platform_data *htc_mmc_data[1]; -#endif - - -/* Platform devices for the Herald */ static struct platform_device *devices[] __initdata = { &kp_device, &lcd_device, - &htcpld_device, - &gpio_leds_device, - &herald_gpiokeys_device, -}; - -/* - * Touchscreen - */ -static const struct ads7846_platform_data htcherald_ts_platform_data = { - .model = 7846, - .keep_vref_on = 1, - .x_plate_ohms = 496, - .gpio_pendown = HTCHERALD_GPIO_TS, - .pressure_max = 100000, - .pressure_min = 5000, - .x_min = 528, - .x_max = 3760, - .y_min = 624, - .y_max = 3760, -}; - -static struct spi_board_info __initdata htcherald_spi_board_info[] = { - { - .modalias = "ads7846", - .platform_data = &htcherald_ts_platform_data, - .irq = OMAP_GPIO_IRQ(HTCHERALD_GPIO_TS), - .max_speed_hz = 2500000, - .bus_num = 2, - .chip_select = 1, - } }; /* @@ -576,7 +278,6 @@ static void __init htcherald_init(void) { printk(KERN_INFO "HTC Herald init.\n"); - /* Do board initialization before we register all the devices */ omap_gpio_init(); omap_board_config = htcherald_config; @@ -587,16 +288,6 @@ static void __init htcherald_init(void) htcherald_usb_enable(); omap1_usb_init(&htcherald_usb_config); - - spi_register_board_info(htcherald_spi_board_info, - ARRAY_SIZE(htcherald_spi_board_info)); - - omap_register_i2c_bus(1, 100, NULL, 0); - -#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) - htc_mmc_data[0] = &htc_mmc1_data; - omap1_init_mmc(htc_mmc_data, 1); -#endif } static void __init htcherald_init_irq(void) diff --git a/trunk/arch/arm/mach-omap1/board-sx1-mmc.c b/trunk/arch/arm/mach-omap1/board-sx1-mmc.c index e8ddd86e3fda..5b33ae8141bc 100644 --- a/trunk/arch/arm/mach-omap1/board-sx1-mmc.c +++ b/trunk/arch/arm/mach-omap1/board-sx1-mmc.c @@ -44,7 +44,8 @@ static struct omap_mmc_platform_data mmc1_data = { .nr_slots = 1, .slots[0] = { .set_power = mmc_set_power, - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | + MMC_VDD_32_33 | MMC_VDD_33_34, .name = "mmcblk", }, }; diff --git a/trunk/arch/arm/mach-omap1/devices.c b/trunk/arch/arm/mach-omap1/devices.c index ea0d80a89da7..b583121b04b9 100644 --- a/trunk/arch/arm/mach-omap1/devices.c +++ b/trunk/arch/arm/mach-omap1/devices.c @@ -9,7 +9,6 @@ * (at your option) any later version. */ -#include #include #include #include @@ -193,48 +192,6 @@ static inline void omap_init_spi100k(void) } #endif - -#define OMAP1_CAMERA_BASE 0xfffb6800 -#define OMAP1_CAMERA_IOSIZE 0x1c - -static struct resource omap1_camera_resources[] = { - [0] = { - .start = OMAP1_CAMERA_BASE, - .end = OMAP1_CAMERA_BASE + OMAP1_CAMERA_IOSIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_CAMERA, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 omap1_camera_dma_mask = DMA_BIT_MASK(32); - -static struct platform_device omap1_camera_device = { - .name = "omap1-camera", - .id = 0, /* This is used to put cameras on this interface */ - .dev = { - .dma_mask = &omap1_camera_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(omap1_camera_resources), - .resource = omap1_camera_resources, -}; - -void __init omap1_camera_init(void *info) -{ - struct platform_device *dev = &omap1_camera_device; - int ret; - - dev->dev.platform_data = info; - - ret = platform_device_register(dev); - if (ret) - dev_err(&dev->dev, "unable to register device: %d\n", ret); -} - - /*-------------------------------------------------------------------------*/ static inline void omap_init_sti(void) {} @@ -301,30 +258,3 @@ static int __init omap1_init_devices(void) } arch_initcall(omap1_init_devices); -#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) - -static struct resource wdt_resources[] = { - { - .start = 0xfffeb000, - .end = 0xfffeb07F, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device omap_wdt_device = { - .name = "omap_wdt", - .id = -1, - .num_resources = ARRAY_SIZE(wdt_resources), - .resource = wdt_resources, -}; - -static int __init omap_init_wdt(void) -{ - if (!cpu_is_omap16xx()) - return; - - platform_device_register(&omap_wdt_device); - return 0; -} -subsys_initcall(omap_init_wdt); -#endif diff --git a/trunk/arch/arm/mach-omap1/include/mach/camera.h b/trunk/arch/arm/mach-omap1/include/mach/camera.h deleted file mode 100644 index fd54b452eb22..000000000000 --- a/trunk/arch/arm/mach-omap1/include/mach/camera.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __ASM_ARCH_CAMERA_H_ -#define __ASM_ARCH_CAMERA_H_ - -void omap1_camera_init(void *); - -static inline void omap1_set_camera_info(struct omap1_cam_platform_data *info) -{ - omap1_camera_init(info); -} - -#endif /* __ASM_ARCH_CAMERA_H_ */ diff --git a/trunk/arch/arm/mach-omap1/pm_bus.c b/trunk/arch/arm/mach-omap1/pm_bus.c deleted file mode 100644 index 8b66392be745..000000000000 --- a/trunk/arch/arm/mach-omap1/pm_bus.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Runtime PM support code for OMAP1 - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * Copyright (C) 2010 Texas Instruments, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#ifdef CONFIG_PM_RUNTIME -static int omap1_pm_runtime_suspend(struct device *dev) -{ - struct clk *iclk, *fclk; - int ret = 0; - - dev_dbg(dev, "%s\n", __func__); - - ret = pm_generic_runtime_suspend(dev); - - fclk = clk_get(dev, "fck"); - if (!IS_ERR(fclk)) { - clk_disable(fclk); - clk_put(fclk); - } - - iclk = clk_get(dev, "ick"); - if (!IS_ERR(iclk)) { - clk_disable(iclk); - clk_put(iclk); - } - - return 0; -}; - -static int omap1_pm_runtime_resume(struct device *dev) -{ - int ret = 0; - struct clk *iclk, *fclk; - - dev_dbg(dev, "%s\n", __func__); - - iclk = clk_get(dev, "ick"); - if (!IS_ERR(iclk)) { - clk_enable(iclk); - clk_put(iclk); - } - - fclk = clk_get(dev, "fck"); - if (!IS_ERR(fclk)) { - clk_enable(fclk); - clk_put(fclk); - } - - return pm_generic_runtime_resume(dev); -}; - -static int __init omap1_pm_runtime_init(void) -{ - const struct dev_pm_ops *pm; - struct dev_pm_ops *omap_pm; - - pm = platform_bus_get_pm_ops(); - if (!pm) { - pr_err("%s: unable to get dev_pm_ops from platform_bus\n", - __func__); - return -ENODEV; - } - - omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL); - if (!omap_pm) { - pr_err("%s: unable to alloc memory for new dev_pm_ops\n", - __func__); - return -ENOMEM; - } - - omap_pm->runtime_suspend = omap1_pm_runtime_suspend; - omap_pm->runtime_resume = omap1_pm_runtime_resume; - - platform_bus_set_pm_ops(omap_pm); - - return 0; -} -core_initcall(omap1_pm_runtime_init); -#endif /* CONFIG_PM_RUNTIME */ diff --git a/trunk/arch/arm/mach-omap2/Kconfig b/trunk/arch/arm/mach-omap2/Kconfig index ab784bfde908..b48bacf0a7aa 100644 --- a/trunk/arch/arm/mach-omap2/Kconfig +++ b/trunk/arch/arm/mach-omap2/Kconfig @@ -11,8 +11,9 @@ config ARCH_OMAP2PLUS_TYPICAL select PM_RUNTIME select VFP select NEON if ARCH_OMAP3 || ARCH_OMAP4 - select SERIAL_OMAP - select SERIAL_OMAP_CONSOLE + select SERIAL_8250 + select SERIAL_CORE_CONSOLE + select SERIAL_8250_CONSOLE select I2C select I2C_OMAP select MFD @@ -34,7 +35,7 @@ config ARCH_OMAP3 default y select CPU_V7 select USB_ARCH_HAS_EHCI - select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4 + select ARM_L1_CACHE_SHIFT_6 config ARCH_OMAP4 bool "TI OMAP4" @@ -42,8 +43,6 @@ config ARCH_OMAP4 depends on ARCH_OMAP2PLUS select CPU_V7 select ARM_GIC - select PL310_ERRATA_588369 - select ARM_ERRATA_720789 comment "OMAP Core Type" depends on ARCH_OMAP2 @@ -100,20 +99,20 @@ config MACH_OMAP2_TUSB6010 config MACH_OMAP_H4 bool "OMAP 2420 H4 board" - depends on ARCH_OMAP2420 + depends on ARCH_OMAP2 default y select OMAP_PACKAGE_ZAF select OMAP_DEBUG_DEVICES config MACH_OMAP_APOLLON bool "OMAP 2420 Apollon board" - depends on ARCH_OMAP2420 + depends on ARCH_OMAP2 default y select OMAP_PACKAGE_ZAC config MACH_OMAP_2430SDP bool "OMAP 2430 SDP board" - depends on ARCH_OMAP2430 + depends on ARCH_OMAP2 default y select OMAP_PACKAGE_ZAC @@ -136,26 +135,6 @@ config MACH_OMAP_LDP default y select OMAP_PACKAGE_CBB -config MACH_OMAP3530_LV_SOM - bool "OMAP3 Logic 3530 LV SOM board" - depends on ARCH_OMAP3 - select OMAP_PACKAGE_CBB - default y - help - Support for the LogicPD OMAP3530 SOM Development kit - for full description please see the products webpage at - http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit - -config MACH_OMAP3_TORPEDO - bool "OMAP3 Logic 35x Torpedo board" - depends on ARCH_OMAP3 - select OMAP_PACKAGE_CBB - default y - help - Support for the LogicPD OMAP35x Torpedo Development kit - for full description please see the products webpage at - http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit - config MACH_OVERO bool "Gumstix Overo board" depends on ARCH_OMAP3 @@ -221,18 +200,12 @@ config MACH_OMAP_ZOOM2 depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CBB - select SERIAL_8250 - select SERIAL_CORE_CONSOLE - select SERIAL_8250_CONSOLE config MACH_OMAP_ZOOM3 bool "OMAP3630 Zoom3 board" depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CBP - select SERIAL_8250 - select SERIAL_CORE_CONSOLE - select SERIAL_8250_CONSOLE config MACH_CM_T35 bool "CompuLab CM-T35 module" @@ -241,25 +214,12 @@ config MACH_CM_T35 select OMAP_PACKAGE_CUS select OMAP_MUX -config MACH_CM_T3517 - bool "CompuLab CM-T3517 module" - depends on ARCH_OMAP3 - default y - select OMAP_PACKAGE_CBB - select OMAP_MUX - config MACH_IGEP0020 bool "IGEP v2 board" depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CBB -config MACH_IGEP0030 - bool "IGEP OMAP3 module" - depends on ARCH_OMAP3 - default y - select OMAP_PACKAGE_CBB - config MACH_SBC3530 bool "OMAP3 SBC STALKER board" depends on ARCH_OMAP3 diff --git a/trunk/arch/arm/mach-omap2/Makefile b/trunk/arch/arm/mach-omap2/Makefile index 7352412e4917..88d3a1e920f5 100644 --- a/trunk/arch/arm/mach-omap2/Makefile +++ b/trunk/arch/arm/mach-omap2/Makefile @@ -3,10 +3,9 @@ # # Common support -obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \ - common.o +obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o -omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o +omap-2-3-common = irq.o sdrc.o hwmod-common = omap_hwmod.o \ omap_hwmod_common_data.o prcm-common = prcm.o powerdomain.o @@ -16,7 +15,7 @@ clock-common = clock.o clock_common_data.o \ obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) -obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) prm44xx.o $(hwmod-common) +obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) $(hwmod-common) obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o @@ -50,18 +49,14 @@ obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o # Power Management ifeq ($(CONFIG_PM),y) obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o -obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o -obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o pm_bus.o -obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o +obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o +obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o +obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a -ifeq ($(CONFIG_PM_VERBOSE),y) -CFLAGS_pm_bus.o += -DDEBUG -endif - endif # PRCM @@ -92,7 +87,6 @@ obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o obj-$(CONFIG_ARCH_OMAP2420) += omap_hwmod_2420_data.o obj-$(CONFIG_ARCH_OMAP2430) += omap_hwmod_2430_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o # EMU peripherals obj-$(CONFIG_OMAP3_EMU) += emu.o @@ -121,10 +115,6 @@ obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o \ obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \ board-flash.o \ hsmmc.o -obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o \ - hsmmc.o -obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o \ - hsmmc.o obj-$(CONFIG_MACH_OVERO) += board-overo.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o \ @@ -156,11 +146,8 @@ obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \ hsmmc.o obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \ hsmmc.o -obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \ hsmmc.o -obj-$(CONFIG_MACH_IGEP0030) += board-igep0030.o \ - hsmmc.o obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \ @@ -187,6 +174,3 @@ obj-y += $(nand-m) $(nand-y) smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o obj-y += $(smc91x-m) $(smc91x-y) - -smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o -obj-y += $(smsc911x-m) $(smsc911x-y) diff --git a/trunk/arch/arm/mach-omap2/board-2430sdp.c b/trunk/arch/arm/mach-omap2/board-2430sdp.c index b527f8d187ad..b857ce484510 100644 --- a/trunk/arch/arm/mach-omap2/board-2430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-2430sdp.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -191,7 +190,7 @@ static int __init omap2430_i2c_init(void) static struct omap2_hsmmc_info mmc[] __initdata = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .ext_clock = 1, diff --git a/trunk/arch/arm/mach-omap2/board-3430sdp.c b/trunk/arch/arm/mach-omap2/board-3430sdp.c index 4e3742c512b8..a5b095cf2adc 100644 --- a/trunk/arch/arm/mach-omap2/board-3430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-3430sdp.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include @@ -39,14 +38,15 @@ #include #include +#include #include -#include "board-flash.h" +#include + #include "mux.h" #include "sdram-qimonda-hyb18m512160af-6.h" #include "hsmmc.h" #include "pm.h" -#include "control.h" #define CONFIG_DISABLE_HFCLK 1 @@ -76,7 +76,7 @@ static struct cpuidle_params omap3_cpuidle_params_table[] = { {1, 10000, 30000, 300000}, }; -static uint32_t board_keymap[] = { +static int board_keymap[] = { KEY(0, 0, KEY_LEFT), KEY(0, 1, KEY_RIGHT), KEY(0, 2, KEY_A), @@ -353,12 +353,12 @@ static struct omap2_hsmmc_info mmc[] = { /* 8 bits (default) requires S6.3 == ON, * so the SIM card isn't used; else 4 bits. */ - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_wp = 4, }, { .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_wp = 7, }, {} /* Terminator */ diff --git a/trunk/arch/arm/mach-omap2/board-3630sdp.c b/trunk/arch/arm/mach-omap2/board-3630sdp.c index bbcf580fa097..fd27ac0860b0 100644 --- a/trunk/arch/arm/mach-omap2/board-3630sdp.c +++ b/trunk/arch/arm/mach-omap2/board-3630sdp.c @@ -21,8 +21,8 @@ #include #include +#include -#include "board-flash.h" #include "mux.h" #include "sdram-hynix-h8mbx00u0mer-0em.h" @@ -208,6 +208,7 @@ static struct flash_partitions sdp_flash_partitions[] = { static void __init omap_sdp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); + omap_serial_init(); zoom_peripherals_init(); board_smc91x_init(); board_flash_init(sdp_flash_partitions, chip_sel_sdp); diff --git a/trunk/arch/arm/mach-omap2/board-4430sdp.c b/trunk/arch/arm/mach-omap2/board-4430sdp.c index 69a4ae971e41..0b6a65f3a10a 100644 --- a/trunk/arch/arm/mach-omap2/board-4430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-4430sdp.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include @@ -32,18 +31,15 @@ #include #include +#include +#include #include #include - #include "hsmmc.h" -#include "timer-gp.h" -#include "control.h" #define ETH_KS8851_IRQ 34 #define ETH_KS8851_POWER_ON 48 #define ETH_KS8851_QUART 138 -#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 -#define OMAP4_SFH7741_ENABLE_GPIO 188 static struct gpio_led sdp4430_gpio_leds[] = { { @@ -81,47 +77,11 @@ static struct gpio_led sdp4430_gpio_leds[] = { }; -static struct gpio_keys_button sdp4430_gpio_keys[] = { - { - .desc = "Proximity Sensor", - .type = EV_SW, - .code = SW_FRONT_PROXIMITY, - .gpio = OMAP4_SFH7741_SENSOR_OUTPUT_GPIO, - .active_low = 0, - } -}; - static struct gpio_led_platform_data sdp4430_led_data = { .leds = sdp4430_gpio_leds, .num_leds = ARRAY_SIZE(sdp4430_gpio_leds), }; -static int omap_prox_activate(struct device *dev) -{ - gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1); - return 0; -} - -static void omap_prox_deactivate(struct device *dev) -{ - gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 0); -} - -static struct gpio_keys_platform_data sdp4430_gpio_keys_data = { - .buttons = sdp4430_gpio_keys, - .nbuttons = ARRAY_SIZE(sdp4430_gpio_keys), - .enable = omap_prox_activate, - .disable = omap_prox_deactivate, -}; - -static struct platform_device sdp4430_gpio_keys_device = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &sdp4430_gpio_keys_data, - }, -}; - static struct platform_device sdp4430_leds_gpio = { .name = "leds-gpio", .id = -1, @@ -201,7 +161,6 @@ static struct platform_device sdp4430_lcd_device = { static struct platform_device *sdp4430_devices[] __initdata = { &sdp4430_lcd_device, - &sdp4430_gpio_keys_device, &sdp4430_leds_gpio, }; @@ -234,16 +193,15 @@ static struct omap_musb_board_data musb_board_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_wp = -EINVAL, }, { .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .nonremovable = true, - .ocr_mask = MMC_VDD_29_30, }, {} /* Terminator */ }; @@ -277,14 +235,8 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev) static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) { - struct omap_mmc_platform_data *pdata; + struct omap_mmc_platform_data *pdata = dev->platform_data; - /* dev can be null if CONFIG_MMC_OMAP_HS is not set */ - if (!dev) { - pr_err("Failed %s\n", __func__); - return; - } - pdata = dev->platform_data; pdata->init = omap4_twl6030_hsmmc_late_init; } @@ -460,11 +412,6 @@ static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = { I2C_BOARD_INFO("tmp105", 0x48), }, }; -static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = { - { - I2C_BOARD_INFO("hmc5843", 0x1e), - }, -}; static int __init omap4_i2c_init(void) { /* @@ -476,36 +423,14 @@ static int __init omap4_i2c_init(void) omap_register_i2c_bus(2, 400, NULL, 0); omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); - omap_register_i2c_bus(4, 400, sdp4430_i2c_4_boardinfo, - ARRAY_SIZE(sdp4430_i2c_4_boardinfo)); + omap_register_i2c_bus(4, 400, NULL, 0); return 0; } - -static void __init omap_sfh7741prox_init(void) -{ - int error; - - error = gpio_request(OMAP4_SFH7741_ENABLE_GPIO, "sfh7741"); - if (error < 0) { - pr_err("%s:failed to request GPIO %d, error %d\n", - __func__, OMAP4_SFH7741_ENABLE_GPIO, error); - return; - } - - error = gpio_direction_output(OMAP4_SFH7741_ENABLE_GPIO , 0); - if (error < 0) { - pr_err("%s: GPIO configuration failed: GPIO %d,error %d\n", - __func__, OMAP4_SFH7741_ENABLE_GPIO, error); - gpio_free(OMAP4_SFH7741_ENABLE_GPIO); - } -} - static void __init omap_4430sdp_init(void) { int status; omap4_i2c_init(); - omap_sfh7741prox_init(); platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); diff --git a/trunk/arch/arm/mach-omap2/board-am3517evm.c b/trunk/arch/arm/mach-omap2/board-am3517evm.c index 07399505312b..e1f8dda62799 100644 --- a/trunk/arch/arm/mach-omap2/board-am3517evm.c +++ b/trunk/arch/arm/mach-omap2/board-am3517evm.c @@ -33,11 +33,11 @@ #include #include +#include #include #include #include "mux.h" -#include "control.h" #define AM35XX_EVM_MDIO_FREQUENCY (1000000) @@ -125,7 +125,7 @@ static void am3517_disable_ethernet_int(void) regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); } -static void am3517_evm_ethernet_init(struct emac_platform_data *pdata) +void am3517_evm_ethernet_init(struct emac_platform_data *pdata) { unsigned int regval; @@ -160,6 +160,7 @@ static void am3517_evm_ethernet_init(struct emac_platform_data *pdata) static struct i2c_board_info __initdata am3517evm_i2c1_boardinfo[] = { { I2C_BOARD_INFO("s35390a", 0x30), + .type = "s35390a", }, }; @@ -367,7 +368,7 @@ static struct omap_dss_board_info am3517_evm_dss_data = { .default_device = &am3517_evm_lcd_device, }; -static struct platform_device am3517_evm_dss_device = { +struct platform_device am3517_evm_dss_device = { .name = "omapdss", .id = -1, .dev = { diff --git a/trunk/arch/arm/mach-omap2/board-apollon.c b/trunk/arch/arm/mach-omap2/board-apollon.c index 2c6db1aaeb29..68f07f5f441a 100644 --- a/trunk/arch/arm/mach-omap2/board-apollon.c +++ b/trunk/arch/arm/mach-omap2/board-apollon.c @@ -39,9 +39,9 @@ #include #include #include +#include #include "mux.h" -#include "control.h" /* LED & Switch macros */ #define LED0_GPIO13 13 diff --git a/trunk/arch/arm/mach-omap2/board-cm-t35.c b/trunk/arch/arm/mach-omap2/board-cm-t35.c index 63f764e2af3f..934d9380c372 100644 --- a/trunk/arch/arm/mach-omap2/board-cm-t35.c +++ b/trunk/arch/arm/mach-omap2/board-cm-t35.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include @@ -238,6 +237,8 @@ static inline void cm_t35_init_nand(void) {} defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) #include +#include + static struct omap2_mcspi_device_config ads7846_mcspi_config = { .turbo_mode = 0, .single_channel = 1, /* 0: slave, 1: master */ @@ -557,7 +558,7 @@ static struct twl4030_usb_data cm_t35_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static uint32_t cm_t35_keymap[] = { +static int cm_t35_keymap[] = { KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT), KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN), KEY(2, 0, KEY_RIGHT), KEY(2, 1, KEY_C), KEY(2, 2, KEY_D), @@ -578,14 +579,14 @@ static struct twl4030_keypad_data cm_t35_kp_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, { .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .transceiver = 1, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, diff --git a/trunk/arch/arm/mach-omap2/board-cm-t3517.c b/trunk/arch/arm/mach-omap2/board-cm-t3517.c deleted file mode 100644 index 1dd303e9a267..000000000000 --- a/trunk/arch/arm/mach-omap2/board-cm-t3517.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/board-cm-t3517.c - * - * Support for the CompuLab CM-T3517 modules - * - * Copyright (C) 2010 CompuLab, Ltd. - * Author: Igor Grinberg - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include "mux.h" -#include "control.h" - -#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) -static struct gpio_led cm_t3517_leds[] = { - [0] = { - .gpio = 186, - .name = "cm-t3517:green", - .default_trigger = "heartbeat", - .active_low = 0, - }, -}; - -static struct gpio_led_platform_data cm_t3517_led_pdata = { - .num_leds = ARRAY_SIZE(cm_t3517_leds), - .leds = cm_t3517_leds, -}; - -static struct platform_device cm_t3517_led_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &cm_t3517_led_pdata, - }, -}; - -static void __init cm_t3517_init_leds(void) -{ - platform_device_register(&cm_t3517_led_device); -} -#else -static inline void cm_t3517_init_leds(void) {} -#endif - -#if defined(CONFIG_CAN_TI_HECC) || defined(CONFIG_CAN_TI_HECC_MODULE) -static struct resource cm_t3517_hecc_resources[] = { - { - .start = AM35XX_IPSS_HECC_BASE, - .end = AM35XX_IPSS_HECC_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_35XX_HECC0_IRQ, - .end = INT_35XX_HECC0_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct ti_hecc_platform_data cm_t3517_hecc_pdata = { - .scc_hecc_offset = AM35XX_HECC_SCC_HECC_OFFSET, - .scc_ram_offset = AM35XX_HECC_SCC_RAM_OFFSET, - .hecc_ram_offset = AM35XX_HECC_RAM_OFFSET, - .mbx_offset = AM35XX_HECC_MBOX_OFFSET, - .int_line = AM35XX_HECC_INT_LINE, - .version = AM35XX_HECC_VERSION, -}; - -static struct platform_device cm_t3517_hecc_device = { - .name = "ti_hecc", - .id = 1, - .num_resources = ARRAY_SIZE(cm_t3517_hecc_resources), - .resource = cm_t3517_hecc_resources, - .dev = { - .platform_data = &cm_t3517_hecc_pdata, - }, -}; - -static void cm_t3517_init_hecc(void) -{ - platform_device_register(&cm_t3517_hecc_device); -} -#else -static inline void cm_t3517_init_hecc(void) {} -#endif - -#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE) -#define RTC_IO_GPIO (153) -#define RTC_WR_GPIO (154) -#define RTC_RD_GPIO (160) -#define RTC_CS_GPIO (163) - -struct v3020_platform_data cm_t3517_v3020_pdata = { - .use_gpio = 1, - .gpio_cs = RTC_CS_GPIO, - .gpio_wr = RTC_WR_GPIO, - .gpio_rd = RTC_RD_GPIO, - .gpio_io = RTC_IO_GPIO, -}; - -static struct platform_device cm_t3517_rtc_device = { - .name = "v3020", - .id = -1, - .dev = { - .platform_data = &cm_t3517_v3020_pdata, - } -}; - -static void __init cm_t3517_init_rtc(void) -{ - platform_device_register(&cm_t3517_rtc_device); -} -#else -static inline void cm_t3517_init_rtc(void) {} -#endif - -#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE) -#define HSUSB1_RESET_GPIO (146) -#define HSUSB2_RESET_GPIO (147) -#define USB_HUB_RESET_GPIO (152) - -static struct ehci_hcd_omap_platform_data cm_t3517_ehci_pdata __initdata = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, - - .phy_reset = true, - .reset_gpio_port[0] = HSUSB1_RESET_GPIO, - .reset_gpio_port[1] = HSUSB2_RESET_GPIO, - .reset_gpio_port[2] = -EINVAL, -}; - -static int cm_t3517_init_usbh(void) -{ - int err; - - err = gpio_request(USB_HUB_RESET_GPIO, "usb hub rst"); - if (err) { - pr_err("CM-T3517: usb hub rst gpio request failed: %d\n", err); - } else { - gpio_direction_output(USB_HUB_RESET_GPIO, 0); - udelay(10); - gpio_set_value(USB_HUB_RESET_GPIO, 1); - msleep(1); - } - - usb_ehci_init(&cm_t3517_ehci_pdata); - - return 0; -} -#else -static inline int cm_t3517_init_usbh(void) -{ - return 0; -} -#endif - -#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) -#define NAND_BLOCK_SIZE SZ_128K - -static struct mtd_partition cm_t3517_nand_partitions[] = { - { - .name = "xloader", - .offset = 0, /* Offset = 0x00000 */ - .size = 4 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE - }, - { - .name = "uboot", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ - .size = 15 * NAND_BLOCK_SIZE, - }, - { - .name = "uboot environment", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ - .size = 2 * NAND_BLOCK_SIZE, - }, - { - .name = "linux", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ - .size = 32 * NAND_BLOCK_SIZE, - }, - { - .name = "rootfs", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */ - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct omap_nand_platform_data cm_t3517_nand_data = { - .parts = cm_t3517_nand_partitions, - .nr_parts = ARRAY_SIZE(cm_t3517_nand_partitions), - .dma_channel = -1, /* disable DMA in OMAP NAND driver */ - .cs = 0, -}; - -static void __init cm_t3517_init_nand(void) -{ - if (gpmc_nand_init(&cm_t3517_nand_data) < 0) - pr_err("CM-T3517: NAND initialization failed\n"); -} -#else -static inline void cm_t3517_init_nand(void) {} -#endif - -static struct omap_board_config_kernel cm_t3517_config[] __initdata = { -}; - -static void __init cm_t3517_init_irq(void) -{ - omap_board_config = cm_t3517_config; - omap_board_config_size = ARRAY_SIZE(cm_t3517_config); - - omap2_init_common_hw(NULL, NULL); - omap_init_irq(); - omap_gpio_init(); -} - -static struct omap_board_mux board_mux[] __initdata = { - /* GPIO186 - Green LED */ - OMAP3_MUX(SYS_CLKOUT2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), - /* RTC GPIOs: IO, WR#, RD#, CS# */ - OMAP3_MUX(MCBSP4_DR, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), - OMAP3_MUX(MCBSP4_DX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), - OMAP3_MUX(MCBSP_CLKS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), - OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), - /* HSUSB1 RESET */ - OMAP3_MUX(UART2_TX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), - /* HSUSB2 RESET */ - OMAP3_MUX(UART2_RX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), - /* CM-T3517 USB HUB nRESET */ - OMAP3_MUX(MCBSP4_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), - - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; - -static void __init cm_t3517_init(void) -{ - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap_serial_init(); - cm_t3517_init_leds(); - cm_t3517_init_nand(); - cm_t3517_init_rtc(); - cm_t3517_init_usbh(); - cm_t3517_init_hecc(); -} - -MACHINE_START(CM_T3517, "Compulab CM-T3517") - .boot_params = 0x80000100, - .map_io = omap3_map_io, - .reserve = omap_reserve, - .init_irq = cm_t3517_init_irq, - .init_machine = cm_t3517_init, - .timer = &omap_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-omap2/board-devkit8000.c b/trunk/arch/arm/mach-omap2/board-devkit8000.c index 067f4379c87f..2205c20a4cdb 100644 --- a/trunk/arch/arm/mach-omap2/board-devkit8000.c +++ b/trunk/arch/arm/mach-omap2/board-devkit8000.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include @@ -45,6 +44,7 @@ #include #include #include +#include #include #include @@ -58,7 +58,6 @@ #include "mux.h" #include "hsmmc.h" -#include "timer-gp.h" #define NAND_BLOCK_SIZE SZ_128K @@ -106,7 +105,7 @@ static struct omap_nand_platform_data devkit8000_nand_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_wp = 29, }, {} /* Terminator */ @@ -199,7 +198,7 @@ static struct platform_device devkit8000_dss_device = { static struct regulator_consumer_supply devkit8000_vdda_dac_supply = REGULATOR_SUPPLY("vdda_dac", "omapdss"); -static uint32_t board_keymap[] = { +static int board_keymap[] = { KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3), diff --git a/trunk/arch/arm/mach-omap2/board-flash.c b/trunk/arch/arm/mach-omap2/board-flash.c index fd38c05bb47f..ac834aa7abf6 100644 --- a/trunk/arch/arm/mach-omap2/board-flash.c +++ b/trunk/arch/arm/mach-omap2/board-flash.c @@ -21,8 +21,7 @@ #include #include #include - -#include "board-flash.h" +#include #define REG_FPGA_REV 0x10 #define REG_FPGA_DIP_SWITCH_INPUT2 0x60 diff --git a/trunk/arch/arm/mach-omap2/board-generic.c b/trunk/arch/arm/mach-omap2/board-generic.c index b1c2c9a11c38..69064b1c6a75 100644 --- a/trunk/arch/arm/mach-omap2/board-generic.c +++ b/trunk/arch/arm/mach-omap2/board-generic.c @@ -48,22 +48,10 @@ static void __init omap_generic_init(void) static void __init omap_generic_map_io(void) { - if (cpu_is_omap242x()) { - omap2_set_globals_242x(); - omap242x_map_common_io(); - } else if (cpu_is_omap243x()) { - omap2_set_globals_243x(); - omap243x_map_common_io(); - } else if (cpu_is_omap34xx()) { - omap2_set_globals_3xxx(); - omap34xx_map_common_io(); - } else if (cpu_is_omap44xx()) { - omap2_set_globals_443x(); - omap44xx_map_common_io(); - } + omap2_set_globals_242x(); /* should be 242x, 243x, or 343x */ + omap242x_map_common_io(); } -/* XXX This machine entry name should be updated */ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") /* Maintainer: Paul Mundt */ .boot_params = 0x80000100, diff --git a/trunk/arch/arm/mach-omap2/board-h4.c b/trunk/arch/arm/mach-omap2/board-h4.c index 929993b4bf26..cc39fc866524 100644 --- a/trunk/arch/arm/mach-omap2/board-h4.c +++ b/trunk/arch/arm/mach-omap2/board-h4.c @@ -31,6 +31,7 @@ #include #include +#include #include #include #include @@ -41,7 +42,6 @@ #include #include "mux.h" -#include "control.h" #define H4_FLASH_CS 0 #define H4_SMC91X_CS 1 diff --git a/trunk/arch/arm/mach-omap2/board-igep0020.c b/trunk/arch/arm/mach-omap2/board-igep0020.c index 5e035a58b809..b62a68ba069b 100644 --- a/trunk/arch/arm/mach-omap2/board-igep0020.c +++ b/trunk/arch/arm/mach-omap2/board-igep0020.c @@ -20,7 +20,6 @@ #include #include -#include #include #include @@ -39,61 +38,12 @@ #define IGEP2_SMSC911X_CS 5 #define IGEP2_SMSC911X_GPIO 176 #define IGEP2_GPIO_USBH_NRESET 24 -#define IGEP2_GPIO_LED0_GREEN 26 -#define IGEP2_GPIO_LED0_RED 27 -#define IGEP2_GPIO_LED1_RED 28 -#define IGEP2_GPIO_DVI_PUP 170 - -#define IGEP2_RB_GPIO_WIFI_NPD 94 -#define IGEP2_RB_GPIO_WIFI_NRESET 95 -#define IGEP2_RB_GPIO_BT_NRESET 137 -#define IGEP2_RC_GPIO_WIFI_NPD 138 -#define IGEP2_RC_GPIO_WIFI_NRESET 139 -#define IGEP2_RC_GPIO_BT_NRESET 137 - -/* - * IGEP2 Hardware Revision Table - * - * -------------------------------------------------------------------------- - * | Id. | Hw Rev. | HW0 (28) | WIFI_NPD | WIFI_NRESET | BT_NRESET | - * -------------------------------------------------------------------------- - * | 0 | B | high | gpio94 | gpio95 | - | - * | 0 | B/C (B-compatible) | high | gpio94 | gpio95 | gpio137 | - * | 1 | C | low | gpio138 | gpio139 | gpio137 | - * -------------------------------------------------------------------------- - */ - -#define IGEP2_BOARD_HWREV_B 0 -#define IGEP2_BOARD_HWREV_C 1 - -static u8 hwrev; - -static void __init igep2_get_revision(void) -{ - u8 ret; - - omap_mux_init_gpio(IGEP2_GPIO_LED1_RED, OMAP_PIN_INPUT); - - if ((gpio_request(IGEP2_GPIO_LED1_RED, "GPIO_HW0_REV") == 0) && - (gpio_direction_input(IGEP2_GPIO_LED1_RED) == 0)) { - ret = gpio_get_value(IGEP2_GPIO_LED1_RED); - if (ret == 0) { - pr_info("IGEP2: Hardware Revision C (B-NON compatible)\n"); - hwrev = IGEP2_BOARD_HWREV_C; - } else if (ret == 1) { - pr_info("IGEP2: Hardware Revision B/C (B compatible)\n"); - hwrev = IGEP2_BOARD_HWREV_B; - } else { - pr_err("IGEP2: Unknown Hardware Revision\n"); - hwrev = -1; - } - } else { - pr_warning("IGEP2: Could not obtain gpio GPIO_HW0_REV\n"); - pr_err("IGEP2: Unknown Hardware Revision\n"); - } - - gpio_free(IGEP2_GPIO_LED1_RED); -} +#define IGEP2_GPIO_LED0_GREEN 26 +#define IGEP2_GPIO_LED0_RED 27 +#define IGEP2_GPIO_LED1_RED 28 +#define IGEP2_GPIO_DVI_PUP 170 +#define IGEP2_GPIO_WIFI_NPD 94 +#define IGEP2_GPIO_WIFI_NRESET 95 #if defined(CONFIG_MTD_ONENAND_OMAP2) || \ defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) @@ -157,7 +107,7 @@ static struct platform_device igep2_onenand_device = { }, }; -static void __init igep2_flash_init(void) +void __init igep2_flash_init(void) { u8 cs = 0; u8 onenandcs = GPMC_CS_NUM + 1; @@ -191,7 +141,7 @@ static void __init igep2_flash_init(void) } #else -static void __init igep2_flash_init(void) {} +void __init igep2_flash_init(void) {} #endif #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) @@ -261,6 +211,10 @@ static struct regulator_consumer_supply igep2_vmmc1_supply = { .supply = "vmmc", }; +static struct regulator_consumer_supply igep2_vmmc2_supply = { + .supply = "vmmc", +}; + /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ static struct regulator_init_data igep2_vmmc1 = { .constraints = { @@ -276,95 +230,37 @@ static struct regulator_init_data igep2_vmmc1 = { .consumer_supplies = &igep2_vmmc1_supply, }; +/* VMMC2 for OMAP VDD_MMC2 (i/o) and MMC2 WIFI */ +static struct regulator_init_data igep2_vmmc2 = { + .constraints = { + .min_uV = 1850000, + .max_uV = 3150000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &igep2_vmmc2_supply, +}; + static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, -#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) { .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, -#endif {} /* Terminator */ }; -#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) -#include - -static struct gpio_led igep2_gpio_leds[] = { - [0] = { - .name = "gpio-led:red:d0", - .gpio = IGEP2_GPIO_LED0_RED, - .default_trigger = "default-off" - }, - [1] = { - .name = "gpio-led:green:d0", - .gpio = IGEP2_GPIO_LED0_GREEN, - .default_trigger = "default-off", - }, - [2] = { - .name = "gpio-led:red:d1", - .gpio = IGEP2_GPIO_LED1_RED, - .default_trigger = "default-off", - }, - [3] = { - .name = "gpio-led:green:d1", - .default_trigger = "heartbeat", - .gpio = -EINVAL, /* gets replaced */ - }, -}; - -static struct gpio_led_platform_data igep2_led_pdata = { - .leds = igep2_gpio_leds, - .num_leds = ARRAY_SIZE(igep2_gpio_leds), -}; - -static struct platform_device igep2_led_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &igep2_led_pdata, - }, -}; - -static void __init igep2_leds_init(void) -{ - platform_device_register(&igep2_led_device); -} - -#else -static inline void igep2_leds_init(void) -{ - if ((gpio_request(IGEP2_GPIO_LED0_RED, "gpio-led:red:d0") == 0) && - (gpio_direction_output(IGEP2_GPIO_LED0_RED, 1) == 0)) { - gpio_export(IGEP2_GPIO_LED0_RED, 0); - gpio_set_value(IGEP2_GPIO_LED0_RED, 0); - } else - pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n"); - - if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "gpio-led:green:d0") == 0) && - (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 1) == 0)) { - gpio_export(IGEP2_GPIO_LED0_GREEN, 0); - gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0); - } else - pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n"); - - if ((gpio_request(IGEP2_GPIO_LED1_RED, "gpio-led:red:d1") == 0) && - (gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) { - gpio_export(IGEP2_GPIO_LED1_RED, 0); - gpio_set_value(IGEP2_GPIO_LED1_RED, 0); - } else - pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n"); - -} -#endif - static int igep2_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { @@ -372,48 +268,20 @@ static int igep2_twl_gpio_setup(struct device *dev, mmc[0].gpio_cd = gpio + 0; omap2_hsmmc_init(mmc); - /* - * link regulators to MMC adapters ... we "know" the + /* link regulators to MMC adapters ... we "know" the * regulators will be set up only *after* we return. - */ + */ igep2_vmmc1_supply.dev = mmc[0].dev; - - /* - * REVISIT: need ehci-omap hooks for external VBUS - * power switch and overcurrent detect - */ - if ((gpio_request(gpio + 1, "GPIO_EHCI_NOC") < 0) || - (gpio_direction_input(gpio + 1) < 0)) - pr_err("IGEP2: Could not obtain gpio for EHCI NOC"); - - /* - * TWL4030_GPIO_MAX + 0 == ledA, GPIO_USBH_CPEN - * (out, active low) - */ - if ((gpio_request(gpio + TWL4030_GPIO_MAX, "GPIO_USBH_CPEN") < 0) || - (gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0) < 0)) - pr_err("IGEP2: Could not obtain gpio for USBH_CPEN"); - - /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ -#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE) - if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0) - && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) { - gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0); - gpio_set_value(gpio + TWL4030_GPIO_MAX + 1, 0); - } else - pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_GREEN\n"); -#else - igep2_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1; -#endif + igep2_vmmc2_supply.dev = mmc[1].dev; return 0; }; -static struct twl4030_gpio_platform_data igep2_twl4030_gpio_pdata = { +static struct twl4030_gpio_platform_data igep2_gpio_data = { .gpio_base = OMAP_MAX_GPIO_LINES, .irq_base = TWL4030_GPIO_IRQ_BASE, .irq_end = TWL4030_GPIO_IRQ_END, - .use_leds = true, + .use_leds = false, .setup = igep2_twl_gpio_setup, }; @@ -487,6 +355,47 @@ static void __init igep2_display_init(void) pr_err("IGEP v2: Could not obtain gpio GPIO_DVI_PUP\n"); } +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +#include + +static struct gpio_led igep2_gpio_leds[] = { + { + .name = "led0:red", + .gpio = IGEP2_GPIO_LED0_RED, + }, + { + .name = "led0:green", + .default_trigger = "heartbeat", + .gpio = IGEP2_GPIO_LED0_GREEN, + }, + { + .name = "led1:red", + .gpio = IGEP2_GPIO_LED1_RED, + }, +}; + +static struct gpio_led_platform_data igep2_led_pdata = { + .leds = igep2_gpio_leds, + .num_leds = ARRAY_SIZE(igep2_gpio_leds), +}; + +static struct platform_device igep2_led_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &igep2_led_pdata, + }, +}; + +static void __init igep2_init_led(void) +{ + platform_device_register(&igep2_led_device); +} + +#else +static inline void igep2_init_led(void) {} +#endif + static struct platform_device *igep2_devices[] __initdata = { &igep2_dss_device, }; @@ -516,13 +425,14 @@ static struct twl4030_platform_data igep2_twldata = { /* platform_data for children goes here */ .usb = &igep2_usb_data, .codec = &igep2_codec_data, - .gpio = &igep2_twl4030_gpio_pdata, + .gpio = &igep2_gpio_data, .vmmc1 = &igep2_vmmc1, + .vmmc2 = &igep2_vmmc2, .vpll2 = &igep2_vpll2, }; -static struct i2c_board_info __initdata igep2_i2c1_boardinfo[] = { +static struct i2c_board_info __initdata igep2_i2c_boardinfo[] = { { I2C_BOARD_INFO("twl4030", 0x48), .flags = I2C_CLIENT_WAKE, @@ -531,29 +441,14 @@ static struct i2c_board_info __initdata igep2_i2c1_boardinfo[] = { }, }; -static struct i2c_board_info __initdata igep2_i2c3_boardinfo[] = { - { - I2C_BOARD_INFO("eeprom", 0x50), - }, -}; - -static void __init igep2_i2c_init(void) +static int __init igep2_i2c_init(void) { - int ret; - - ret = omap_register_i2c_bus(1, 2600, igep2_i2c1_boardinfo, - ARRAY_SIZE(igep2_i2c1_boardinfo)); - if (ret) - pr_warning("IGEP2: Could not register I2C1 bus (%d)\n", ret); - - /* - * Bus 3 is attached to the DVI port where devices like the pico DLP - * projector don't work reliably with 400kHz - */ - ret = omap_register_i2c_bus(3, 100, igep2_i2c3_boardinfo, - ARRAY_SIZE(igep2_i2c3_boardinfo)); - if (ret) - pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret); + omap_register_i2c_bus(1, 2600, igep2_i2c_boardinfo, + ARRAY_SIZE(igep2_i2c_boardinfo)); + /* Bus 3 is attached to the DVI port where devices like the pico DLP + * projector don't work reliably with 400kHz */ + omap_register_i2c_bus(3, 100, NULL, 0); + return 0; } static struct omap_musb_board_data musb_board_data = { @@ -581,57 +476,9 @@ static struct omap_board_mux board_mux[] __initdata = { #define board_mux NULL #endif -#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) - -static void __init igep2_wlan_bt_init(void) -{ - unsigned npd, wreset, btreset; - - /* GPIO's for WLAN-BT combo depends on hardware revision */ - if (hwrev == IGEP2_BOARD_HWREV_B) { - npd = IGEP2_RB_GPIO_WIFI_NPD; - wreset = IGEP2_RB_GPIO_WIFI_NRESET; - btreset = IGEP2_RB_GPIO_BT_NRESET; - } else if (hwrev == IGEP2_BOARD_HWREV_C) { - npd = IGEP2_RC_GPIO_WIFI_NPD; - wreset = IGEP2_RC_GPIO_WIFI_NRESET; - btreset = IGEP2_RC_GPIO_BT_NRESET; - } else - return; - - /* Set GPIO's for WLAN-BT combo module */ - if ((gpio_request(npd, "GPIO_WIFI_NPD") == 0) && - (gpio_direction_output(npd, 1) == 0)) { - gpio_export(npd, 0); - } else - pr_warning("IGEP2: Could not obtain gpio GPIO_WIFI_NPD\n"); - - if ((gpio_request(wreset, "GPIO_WIFI_NRESET") == 0) && - (gpio_direction_output(wreset, 1) == 0)) { - gpio_export(wreset, 0); - gpio_set_value(wreset, 0); - udelay(10); - gpio_set_value(wreset, 1); - } else - pr_warning("IGEP2: Could not obtain gpio GPIO_WIFI_NRESET\n"); - - if ((gpio_request(btreset, "GPIO_BT_NRESET") == 0) && - (gpio_direction_output(btreset, 1) == 0)) { - gpio_export(btreset, 0); - } else - pr_warning("IGEP2: Could not obtain gpio GPIO_BT_NRESET\n"); -} -#else -static inline void __init igep2_wlan_bt_init(void) { } -#endif - static void __init igep2_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - - /* Get IGEP2 hardware revision */ - igep2_get_revision(); - /* Register I2C busses and drivers */ igep2_i2c_init(); platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices)); omap_serial_init(); @@ -639,16 +486,50 @@ static void __init igep2_init(void) usb_ehci_init(&ehci_pdata); igep2_flash_init(); - igep2_leds_init(); + igep2_init_led(); igep2_display_init(); igep2_init_smsc911x(); - /* - * WLAN-BT combo module from MuRata wich has a Marvell WLAN - * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface. - */ - igep2_wlan_bt_init(); + /* GPIO userspace leds */ +#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE) + if ((gpio_request(IGEP2_GPIO_LED0_RED, "led0:red") == 0) && + (gpio_direction_output(IGEP2_GPIO_LED0_RED, 1) == 0)) { + gpio_export(IGEP2_GPIO_LED0_RED, 0); + gpio_set_value(IGEP2_GPIO_LED0_RED, 0); + } else + pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n"); + + if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "led0:green") == 0) && + (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 1) == 0)) { + gpio_export(IGEP2_GPIO_LED0_GREEN, 0); + gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0); + } else + pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n"); + + if ((gpio_request(IGEP2_GPIO_LED1_RED, "led1:red") == 0) && + (gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) { + gpio_export(IGEP2_GPIO_LED1_RED, 0); + gpio_set_value(IGEP2_GPIO_LED1_RED, 0); + } else + pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n"); +#endif + + /* GPIO W-LAN + Bluetooth combo module */ + if ((gpio_request(IGEP2_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) && + (gpio_direction_output(IGEP2_GPIO_WIFI_NPD, 1) == 0)) { + gpio_export(IGEP2_GPIO_WIFI_NPD, 0); +/* gpio_set_value(IGEP2_GPIO_WIFI_NPD, 0); */ + } else + pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NPD\n"); + if ((gpio_request(IGEP2_GPIO_WIFI_NRESET, "GPIO_WIFI_NRESET") == 0) && + (gpio_direction_output(IGEP2_GPIO_WIFI_NRESET, 1) == 0)) { + gpio_export(IGEP2_GPIO_WIFI_NRESET, 0); + gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 0); + udelay(10); + gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 1); + } else + pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NRESET\n"); } MACHINE_START(IGEP0020, "IGEP v2 board") diff --git a/trunk/arch/arm/mach-omap2/board-igep0030.c b/trunk/arch/arm/mach-omap2/board-igep0030.c deleted file mode 100644 index 22b0b253e16b..000000000000 --- a/trunk/arch/arm/mach-omap2/board-igep0030.c +++ /dev/null @@ -1,400 +0,0 @@ -/* - * Copyright (C) 2010 - ISEE 2007 SL - * - * Modified from mach-omap2/board-generic.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include - -#include "mux.h" -#include "hsmmc.h" -#include "sdram-numonyx-m65kxxxxam.h" - -#define IGEP3_GPIO_LED0_GREEN 54 -#define IGEP3_GPIO_LED0_RED 53 -#define IGEP3_GPIO_LED1_RED 16 - -#define IGEP3_GPIO_WIFI_NPD 138 -#define IGEP3_GPIO_WIFI_NRESET 139 -#define IGEP3_GPIO_BT_NRESET 137 - -#define IGEP3_GPIO_USBH_NRESET 115 - - -#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ - defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) - -#define ONENAND_MAP 0x20000000 - -/* - * x2 Flash built-in COMBO POP MEMORY - * Since the device is equipped with two DataRAMs, and two-plane NAND - * Flash memory array, these two component enables simultaneous program - * of 4KiB. Plane1 has only even blocks such as block0, block2, block4 - * while Plane2 has only odd blocks such as block1, block3, block5. - * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048) - */ - -static struct mtd_partition igep3_onenand_partitions[] = { - { - .name = "X-Loader", - .offset = 0, - .size = 2 * (64*(2*2048)) - }, - { - .name = "U-Boot", - .offset = MTDPART_OFS_APPEND, - .size = 6 * (64*(2*2048)), - }, - { - .name = "Environment", - .offset = MTDPART_OFS_APPEND, - .size = 2 * (64*(2*2048)), - }, - { - .name = "Kernel", - .offset = MTDPART_OFS_APPEND, - .size = 12 * (64*(2*2048)), - }, - { - .name = "File System", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct omap_onenand_platform_data igep3_onenand_pdata = { - .parts = igep3_onenand_partitions, - .nr_parts = ARRAY_SIZE(igep3_onenand_partitions), - .onenand_setup = NULL, - .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ -}; - -static struct platform_device igep3_onenand_device = { - .name = "omap2-onenand", - .id = -1, - .dev = { - .platform_data = &igep3_onenand_pdata, - }, -}; - -void __init igep3_flash_init(void) -{ - u8 cs = 0; - u8 onenandcs = GPMC_CS_NUM + 1; - - for (cs = 0; cs < GPMC_CS_NUM; cs++) { - u32 ret; - ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); - - /* Check if NAND/oneNAND is configured */ - if ((ret & 0xC00) == 0x800) - /* NAND found */ - pr_err("IGEP3: Unsupported NAND found\n"); - else { - ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); - - if ((ret & 0x3F) == (ONENAND_MAP >> 24)) - /* OneNAND found */ - onenandcs = cs; - } - } - - if (onenandcs > GPMC_CS_NUM) { - pr_err("IGEP3: Unable to find configuration in GPMC\n"); - return; - } - - igep3_onenand_pdata.cs = onenandcs; - - if (platform_device_register(&igep3_onenand_device) < 0) - pr_err("IGEP3: Unable to register OneNAND device\n"); -} - -#else -void __init igep3_flash_init(void) {} -#endif - -static struct regulator_consumer_supply igep3_vmmc1_supply = { - .supply = "vmmc", -}; - -/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ -static struct regulator_init_data igep3_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &igep3_vmmc1_supply, -}; - -static struct omap2_hsmmc_info mmc[] = { - [0] = { - .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, - .gpio_cd = -EINVAL, - .gpio_wp = -EINVAL, - }, -#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) - [1] = { - .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA, - .gpio_cd = -EINVAL, - .gpio_wp = -EINVAL, - }, -#endif - {} /* Terminator */ -}; - -#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) -#include - -static struct gpio_led igep3_gpio_leds[] = { - [0] = { - .name = "gpio-led:red:d0", - .gpio = IGEP3_GPIO_LED0_RED, - .default_trigger = "default-off" - }, - [1] = { - .name = "gpio-led:green:d0", - .gpio = IGEP3_GPIO_LED0_GREEN, - .default_trigger = "default-off", - }, - [2] = { - .name = "gpio-led:red:d1", - .gpio = IGEP3_GPIO_LED1_RED, - .default_trigger = "default-off", - }, - [3] = { - .name = "gpio-led:green:d1", - .default_trigger = "heartbeat", - .gpio = -EINVAL, /* gets replaced */ - }, -}; - -static struct gpio_led_platform_data igep3_led_pdata = { - .leds = igep3_gpio_leds, - .num_leds = ARRAY_SIZE(igep3_gpio_leds), -}; - -static struct platform_device igep3_led_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &igep3_led_pdata, - }, -}; - -static void __init igep3_leds_init(void) -{ - platform_device_register(&igep3_led_device); -} - -#else -static inline void igep3_leds_init(void) -{ - if ((gpio_request(IGEP3_GPIO_LED0_RED, "gpio-led:red:d0") == 0) && - (gpio_direction_output(IGEP3_GPIO_LED0_RED, 1) == 0)) { - gpio_export(IGEP3_GPIO_LED0_RED, 0); - gpio_set_value(IGEP3_GPIO_LED0_RED, 1); - } else - pr_warning("IGEP3: Could not obtain gpio GPIO_LED0_RED\n"); - - if ((gpio_request(IGEP3_GPIO_LED0_GREEN, "gpio-led:green:d0") == 0) && - (gpio_direction_output(IGEP3_GPIO_LED0_GREEN, 1) == 0)) { - gpio_export(IGEP3_GPIO_LED0_GREEN, 0); - gpio_set_value(IGEP3_GPIO_LED0_GREEN, 1); - } else - pr_warning("IGEP3: Could not obtain gpio GPIO_LED0_GREEN\n"); - - if ((gpio_request(IGEP3_GPIO_LED1_RED, "gpio-led:red:d1") == 0) && - (gpio_direction_output(IGEP3_GPIO_LED1_RED, 1) == 0)) { - gpio_export(IGEP3_GPIO_LED1_RED, 0); - gpio_set_value(IGEP3_GPIO_LED1_RED, 1); - } else - pr_warning("IGEP3: Could not obtain gpio GPIO_LED1_RED\n"); -} -#endif - -static int igep3_twl4030_gpio_setup(struct device *dev, - unsigned gpio, unsigned ngpio) -{ - /* gpio + 0 is "mmc0_cd" (input/IRQ) */ - mmc[0].gpio_cd = gpio + 0; - omap2_hsmmc_init(mmc); - - /* - * link regulators to MMC adapters ... we "know" the - * regulators will be set up only *after* we return. - */ - igep3_vmmc1_supply.dev = mmc[0].dev; - - /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ -#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE) - if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0) - && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) { - gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0); - gpio_set_value(gpio + TWL4030_GPIO_MAX + 1, 0); - } else - pr_warning("IGEP3: Could not obtain gpio GPIO_LED1_GREEN\n"); -#else - igep3_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1; -#endif - - return 0; -}; - -static struct twl4030_gpio_platform_data igep3_twl4030_gpio_pdata = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, - .use_leds = true, - .setup = igep3_twl4030_gpio_setup, -}; - -static struct twl4030_usb_data igep3_twl4030_usb_data = { - .usb_mode = T2_USB_MODE_ULPI, -}; - -static void __init igep3_init_irq(void) -{ - omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); - omap_init_irq(); - omap_gpio_init(); -} - -static struct twl4030_platform_data igep3_twl4030_pdata = { - .irq_base = TWL4030_IRQ_BASE, - .irq_end = TWL4030_IRQ_END, - - /* platform_data for children goes here */ - .usb = &igep3_twl4030_usb_data, - .gpio = &igep3_twl4030_gpio_pdata, - .vmmc1 = &igep3_vmmc1, -}; - -static struct i2c_board_info __initdata igep3_i2c_boardinfo[] = { - { - I2C_BOARD_INFO("twl4030", 0x48), - .flags = I2C_CLIENT_WAKE, - .irq = INT_34XX_SYS_NIRQ, - .platform_data = &igep3_twl4030_pdata, - }, -}; - -static int __init igep3_i2c_init(void) -{ - omap_register_i2c_bus(1, 2600, igep3_i2c_boardinfo, - ARRAY_SIZE(igep3_i2c_boardinfo)); - - return 0; -} - -static struct omap_musb_board_data musb_board_data = { - .interface_type = MUSB_INTERFACE_ULPI, - .mode = MUSB_OTG, - .power = 100, -}; - -#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) - -static void __init igep3_wifi_bt_init(void) -{ - /* Configure MUX values for W-LAN + Bluetooth GPIO's */ - omap_mux_init_gpio(IGEP3_GPIO_WIFI_NPD, OMAP_PIN_OUTPUT); - omap_mux_init_gpio(IGEP3_GPIO_WIFI_NRESET, OMAP_PIN_OUTPUT); - omap_mux_init_gpio(IGEP3_GPIO_BT_NRESET, OMAP_PIN_OUTPUT); - - /* Set GPIO's for W-LAN + Bluetooth combo module */ - if ((gpio_request(IGEP3_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) && - (gpio_direction_output(IGEP3_GPIO_WIFI_NPD, 1) == 0)) { - gpio_export(IGEP3_GPIO_WIFI_NPD, 0); - } else - pr_warning("IGEP3: Could not obtain gpio GPIO_WIFI_NPD\n"); - - if ((gpio_request(IGEP3_GPIO_WIFI_NRESET, "GPIO_WIFI_NRESET") == 0) && - (gpio_direction_output(IGEP3_GPIO_WIFI_NRESET, 1) == 0)) { - gpio_export(IGEP3_GPIO_WIFI_NRESET, 0); - gpio_set_value(IGEP3_GPIO_WIFI_NRESET, 0); - udelay(10); - gpio_set_value(IGEP3_GPIO_WIFI_NRESET, 1); - } else - pr_warning("IGEP3: Could not obtain gpio GPIO_WIFI_NRESET\n"); - - if ((gpio_request(IGEP3_GPIO_BT_NRESET, "GPIO_BT_NRESET") == 0) && - (gpio_direction_output(IGEP3_GPIO_BT_NRESET, 1) == 0)) { - gpio_export(IGEP3_GPIO_BT_NRESET, 0); - } else - pr_warning("IGEP3: Could not obtain gpio GPIO_BT_NRESET\n"); -} -#else -void __init igep3_wifi_bt_init(void) {} -#endif - -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - -static void __init igep3_init(void) -{ - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - - /* Register I2C busses and drivers */ - igep3_i2c_init(); - - omap_serial_init(); - usb_musb_init(&musb_board_data); - - igep3_flash_init(); - igep3_leds_init(); - - /* - * WLAN-BT combo module from MuRata wich has a Marvell WLAN - * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface. - */ - igep3_wifi_bt_init(); - -} - -MACHINE_START(IGEP0030, "IGEP OMAP3 module") - .boot_params = 0x80000100, - .map_io = omap3_map_io, - .init_irq = igep3_init_irq, - .init_machine = igep3_init, - .timer = &omap_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-omap2/board-ldp.c b/trunk/arch/arm/mach-omap2/board-ldp.c index 001fd9713f39..f28fd77bceb3 100644 --- a/trunk/arch/arm/mach-omap2/board-ldp.c +++ b/trunk/arch/arm/mach-omap2/board-ldp.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include @@ -42,12 +41,11 @@ #include #include +#include #include -#include "board-flash.h" #include "mux.h" #include "hsmmc.h" -#include "control.h" #define LDP_SMSC911X_CS 1 #define LDP_SMSC911X_GPIO 152 @@ -84,7 +82,7 @@ static struct platform_device ldp_smsc911x_device = { }, }; -static uint32_t board_keymap[] = { +static int board_keymap[] = { KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3), @@ -364,7 +362,7 @@ static int __init omap_i2c_init(void) static struct omap2_hsmmc_info mmc[] __initdata = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, diff --git a/trunk/arch/arm/mach-omap2/board-n8x0.c b/trunk/arch/arm/mach-omap2/board-n8x0.c index e823c7042ab3..3f7966873507 100644 --- a/trunk/arch/arm/mach-omap2/board-n8x0.c +++ b/trunk/arch/arm/mach-omap2/board-n8x0.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include @@ -384,6 +383,15 @@ static void n8x0_mmc_callback(void *data, u8 card_mask) omap_mmc_notify_cover_event(mmc_device, index, *openp); } +void n8x0_mmc_slot1_cover_handler(void *arg, int closed_state) +{ + if (mmc_device == NULL) + return; + + slot1_cover_open = !closed_state; + omap_mmc_notify_cover_event(mmc_device, 0, closed_state); +} + static int n8x0_mmc_late_init(struct device *dev) { int r, bit, *openp; @@ -503,7 +511,7 @@ static struct omap_mmc_platform_data mmc1_data = { static struct omap_mmc_platform_data *mmc_data[OMAP24XX_NR_MMC]; -static void __init n8x0_mmc_init(void) +void __init n8x0_mmc_init(void) { int err; @@ -552,6 +560,11 @@ static void __init n8x0_mmc_init(void) void __init n8x0_mmc_init(void) { } + +void n8x0_mmc_slot1_cover_handler(void *arg, int state) +{ +} + #endif /* CONFIG_MMC_OMAP */ #ifdef CONFIG_MENELAUS @@ -601,35 +614,29 @@ static int n8x0_menelaus_late_init(struct device *dev) return 0; } -#else -static int n8x0_menelaus_late_init(struct device *dev) -{ - return 0; -} -#endif - -static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = { - .late_init = n8x0_menelaus_late_init, -}; - -static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = { +static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] = { { I2C_BOARD_INFO("menelaus", 0x72), .irq = INT_24XX_SYS_NIRQ, - .platform_data = &n8x0_menelaus_platform_data, }, }; -static struct aic3x_pdata n810_aic33_data __initdata = { - .gpio_reset = 118, +static struct menelaus_platform_data n8x0_menelaus_platform_data = { + .late_init = n8x0_menelaus_late_init, }; -static struct i2c_board_info n810_i2c_board_info_2[] __initdata = { - { - I2C_BOARD_INFO("tlv320aic3x", 0x18), - .platform_data = &n810_aic33_data, - }, -}; +static void __init n8x0_menelaus_init(void) +{ + n8x0_i2c_board_info_1[0].platform_data = &n8x0_menelaus_platform_data; + omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, + ARRAY_SIZE(n8x0_i2c_board_info_1)); +} + +#else +static inline void __init n8x0_menelaus_init(void) +{ +} +#endif static void __init n8x0_map_io(void) { @@ -646,11 +653,6 @@ static void __init n8x0_init_irq(void) #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { - /* I2S codec port pins for McBSP block */ - OMAP2420_MUX(EAC_AC_SCLK, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), - OMAP2420_MUX(EAC_AC_FS, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), - OMAP2420_MUX(EAC_AC_DIN, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), - OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else @@ -663,14 +665,9 @@ static void __init n8x0_init_machine(void) /* FIXME: add n810 spi devices */ spi_register_board_info(n800_spi_board_info, ARRAY_SIZE(n800_spi_board_info)); - omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, - ARRAY_SIZE(n8x0_i2c_board_info_1)); - omap_register_i2c_bus(2, 400, NULL, 0); - if (machine_is_nokia_n810()) - i2c_register_board_info(2, n810_i2c_board_info_2, - ARRAY_SIZE(n810_i2c_board_info_2)); omap_serial_init(); + n8x0_menelaus_init(); n8x0_onenand_init(); n8x0_mmc_init(); n8x0_usb_init(); diff --git a/trunk/arch/arm/mach-omap2/board-omap3beagle.c b/trunk/arch/arm/mach-omap2/board-omap3beagle.c index 14f42240ae79..9d9f5b881ee8 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3beagle.c +++ b/trunk/arch/arm/mach-omap2/board-omap3beagle.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include @@ -44,100 +43,13 @@ #include #include #include +#include #include "mux.h" #include "hsmmc.h" -#include "timer-gp.h" #define NAND_BLOCK_SIZE SZ_128K -/* - * OMAP3 Beagle revision - * Run time detection of Beagle revision is done by reading GPIO. - * GPIO ID - - * AXBX = GPIO173, GPIO172, GPIO171: 1 1 1 - * C1_3 = GPIO173, GPIO172, GPIO171: 1 1 0 - * C4 = GPIO173, GPIO172, GPIO171: 1 0 1 - * XM = GPIO173, GPIO172, GPIO171: 0 0 0 - */ -enum { - OMAP3BEAGLE_BOARD_UNKN = 0, - OMAP3BEAGLE_BOARD_AXBX, - OMAP3BEAGLE_BOARD_C1_3, - OMAP3BEAGLE_BOARD_C4, - OMAP3BEAGLE_BOARD_XM, -}; - -static u8 omap3_beagle_version; - -static u8 omap3_beagle_get_rev(void) -{ - return omap3_beagle_version; -} - -static void __init omap3_beagle_init_rev(void) -{ - int ret; - u16 beagle_rev = 0; - - omap_mux_init_gpio(171, OMAP_PIN_INPUT_PULLUP); - omap_mux_init_gpio(172, OMAP_PIN_INPUT_PULLUP); - omap_mux_init_gpio(173, OMAP_PIN_INPUT_PULLUP); - - ret = gpio_request(171, "rev_id_0"); - if (ret < 0) - goto fail0; - - ret = gpio_request(172, "rev_id_1"); - if (ret < 0) - goto fail1; - - ret = gpio_request(173, "rev_id_2"); - if (ret < 0) - goto fail2; - - gpio_direction_input(171); - gpio_direction_input(172); - gpio_direction_input(173); - - beagle_rev = gpio_get_value(171) | (gpio_get_value(172) << 1) - | (gpio_get_value(173) << 2); - - switch (beagle_rev) { - case 7: - printk(KERN_INFO "OMAP3 Beagle Rev: Ax/Bx\n"); - omap3_beagle_version = OMAP3BEAGLE_BOARD_AXBX; - break; - case 6: - printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n"); - omap3_beagle_version = OMAP3BEAGLE_BOARD_C1_3; - break; - case 5: - printk(KERN_INFO "OMAP3 Beagle Rev: C4\n"); - omap3_beagle_version = OMAP3BEAGLE_BOARD_C4; - break; - case 0: - printk(KERN_INFO "OMAP3 Beagle Rev: xM\n"); - omap3_beagle_version = OMAP3BEAGLE_BOARD_XM; - break; - default: - printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev); - omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN; - } - - return; - -fail2: - gpio_free(172); -fail1: - gpio_free(171); -fail0: - printk(KERN_ERR "Unable to get revision detection GPIO pins\n"); - omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN; - - return; -} - static struct mtd_partition omap3beagle_nand_partitions[] = { /* All the partition sizes are listed in terms of NAND block size */ { @@ -254,7 +166,7 @@ static void __init beagle_display_init(void) static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_wp = 29, }, {} /* Terminator */ @@ -273,10 +185,7 @@ static struct gpio_led gpio_leds[]; static int beagle_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { - if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) { - mmc[0].gpio_wp = -EINVAL; - } else if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C1_3) || - (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C4)) { + if (system_rev >= 0x20 && system_rev <= 0x34301000) { omap_mux_init_gpio(23, OMAP_PIN_INPUT); mmc[0].gpio_wp = 23; } else { @@ -413,19 +322,13 @@ static struct i2c_board_info __initdata beagle_i2c_boardinfo[] = { }, }; -static struct i2c_board_info __initdata beagle_i2c_eeprom[] = { - { - I2C_BOARD_INFO("eeprom", 0x50), - }, -}; - static int __init omap3_beagle_i2c_init(void) { omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo, ARRAY_SIZE(beagle_i2c_boardinfo)); /* Bus 3 is attached to the DVI port where devices like the pico DLP * projector don't work reliably with 400kHz */ - omap_register_i2c_bus(3, 100, beagle_i2c_eeprom, ARRAY_SIZE(beagle_i2c_eeprom)); + omap_register_i2c_bus(3, 100, NULL, 0); return 0; } @@ -561,7 +464,6 @@ static struct omap_musb_board_data musb_board_data = { static void __init omap3_beagle_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap3_beagle_init_rev(); omap3_beagle_i2c_init(); platform_add_devices(omap3_beagle_devices, ARRAY_SIZE(omap3_beagle_devices)); diff --git a/trunk/arch/arm/mach-omap2/board-omap3evm.c b/trunk/arch/arm/mach-omap2/board-omap3evm.c index b04365c6bb10..8936e4fba334 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3evm.c +++ b/trunk/arch/arm/mach-omap2/board-omap3evm.c @@ -31,7 +31,6 @@ #include #include -#include #include #include @@ -371,7 +370,7 @@ static struct regulator_init_data omap3evm_vsim = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = 63, }, @@ -447,7 +446,7 @@ static struct twl4030_usb_data omap3evm_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static uint32_t board_keymap[] = { +static int board_keymap[] = { KEY(0, 0, KEY_LEFT), KEY(0, 1, KEY_DOWN), KEY(0, 2, KEY_ENTER), @@ -585,7 +584,7 @@ static int ads7846_get_pendown_state(void) return !gpio_get_value(OMAP3_EVM_TS_GPIO); } -static struct ads7846_platform_data ads7846_config = { +struct ads7846_platform_data ads7846_config = { .x_max = 0x0fff, .y_max = 0x0fff, .x_plate_ohms = 180, @@ -604,7 +603,7 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = { .single_channel = 1, /* 0: slave, 1: master */ }; -static struct spi_board_info omap3evm_spi_board_info[] = { +struct spi_board_info omap3evm_spi_board_info[] = { [0] = { .modalias = "ads7846", .bus_num = 1, diff --git a/trunk/arch/arm/mach-omap2/board-omap3logic.c b/trunk/arch/arm/mach-omap2/board-omap3logic.c deleted file mode 100644 index 5f7d2c1e7ef5..000000000000 --- a/trunk/arch/arm/mach-omap2/board-omap3logic.c +++ /dev/null @@ -1,241 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/board-omap3logic.c - * - * Copyright (C) 2010 Li-Pro.Net - * Stephan Linz - * - * Copyright (C) 2010 Logic Product Development, Inc. - * Peter Barada - * - * Modified from Beagle, EVM, and RX51 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include -#include -#include -#include - -#include "mux.h" -#include "hsmmc.h" -#include "timer-gp.h" -#include "control.h" - -#include -#include -#include -#include -#include -#include - -#define OMAP3LOGIC_SMSC911X_CS 1 - -#define OMAP3530_LV_SOM_MMC_GPIO_CD 110 -#define OMAP3530_LV_SOM_MMC_GPIO_WP 126 -#define OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ 152 - -#define OMAP3_TORPEDO_MMC_GPIO_CD 127 -#define OMAP3_TORPEDO_SMSC911X_GPIO_IRQ 129 - -static struct regulator_consumer_supply omap3logic_vmmc1_supply = { - .supply = "vmmc", -}; - -/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ -static struct regulator_init_data omap3logic_vmmc1 = { - .constraints = { - .name = "VMMC1", - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &omap3logic_vmmc1_supply, -}; - -static struct twl4030_gpio_platform_data omap3logic_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, - .use_leds = true, - .pullups = BIT(1), - .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) - | BIT(13) | BIT(15) | BIT(16) | BIT(17), -}; - -static struct twl4030_platform_data omap3logic_twldata = { - .irq_base = TWL4030_IRQ_BASE, - .irq_end = TWL4030_IRQ_END, - - /* platform_data for children goes here */ - .gpio = &omap3logic_gpio_data, - .vmmc1 = &omap3logic_vmmc1, -}; - -static struct i2c_board_info __initdata omap3logic_i2c_boardinfo[] = { - { - I2C_BOARD_INFO("twl4030", 0x48), - .flags = I2C_CLIENT_WAKE, - .irq = INT_34XX_SYS_NIRQ, - .platform_data = &omap3logic_twldata, - }, -}; - -static int __init omap3logic_i2c_init(void) -{ - omap_register_i2c_bus(1, 2600, omap3logic_i2c_boardinfo, - ARRAY_SIZE(omap3logic_i2c_boardinfo)); - return 0; -} - -static struct omap2_hsmmc_info __initdata board_mmc_info[] = { - { - .name = "external", - .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, - .gpio_cd = -EINVAL, - .gpio_wp = -EINVAL, - }, - {} /* Terminator */ -}; - -static void __init board_mmc_init(void) -{ - if (machine_is_omap3530_lv_som()) { - /* OMAP3530 LV SOM board */ - board_mmc_info[0].gpio_cd = OMAP3530_LV_SOM_MMC_GPIO_CD; - board_mmc_info[0].gpio_wp = OMAP3530_LV_SOM_MMC_GPIO_WP; - omap_mux_init_signal("gpio_110", OMAP_PIN_OUTPUT); - omap_mux_init_signal("gpio_126", OMAP_PIN_OUTPUT); - } else if (machine_is_omap3_torpedo()) { - /* OMAP3 Torpedo board */ - board_mmc_info[0].gpio_cd = OMAP3_TORPEDO_MMC_GPIO_CD; - omap_mux_init_signal("gpio_127", OMAP_PIN_OUTPUT); - } else { - /* unsupported board */ - printk(KERN_ERR "%s(): unknown machine type\n", __func__); - return; - } - - omap2_hsmmc_init(board_mmc_info); - /* link regulators to MMC adapters */ - omap3logic_vmmc1_supply.dev = board_mmc_info[0].dev; -} - -static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = { - .cs = OMAP3LOGIC_SMSC911X_CS, - .gpio_irq = -EINVAL, - .gpio_reset = -EINVAL, - .flags = IORESOURCE_IRQ_LOWLEVEL, -}; - -/* TODO/FIXME (comment by Peter Barada, LogicPD): - * Fix the PBIAS voltage for Torpedo MMC1 pins that - * are used for other needs (IRQs, etc). */ -static void omap3torpedo_fix_pbias_voltage(void) -{ - u16 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; - u32 reg; - - if (machine_is_omap3_torpedo()) - { - /* Set the bias for the pin */ - reg = omap_ctrl_readl(control_pbias_offset); - - reg &= ~OMAP343X_PBIASLITEPWRDNZ1; - omap_ctrl_writel(reg, control_pbias_offset); - - /* 100ms delay required for PBIAS configuration */ - msleep(100); - - reg |= OMAP343X_PBIASLITEVMODE1; - reg |= OMAP343X_PBIASLITEPWRDNZ1; - omap_ctrl_writel(reg | 0x300, control_pbias_offset); - } -} - -static inline void __init board_smsc911x_init(void) -{ - if (machine_is_omap3530_lv_som()) { - /* OMAP3530 LV SOM board */ - board_smsc911x_data.gpio_irq = - OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ; - omap_mux_init_signal("gpio_152", OMAP_PIN_INPUT); - } else if (machine_is_omap3_torpedo()) { - /* OMAP3 Torpedo board */ - board_smsc911x_data.gpio_irq = OMAP3_TORPEDO_SMSC911X_GPIO_IRQ; - omap_mux_init_signal("gpio_129", OMAP_PIN_INPUT); - } else { - /* unsupported board */ - printk(KERN_ERR "%s(): unknown machine type\n", __func__); - return; - } - - gpmc_smsc911x_init(&board_smsc911x_data); -} - -static void __init omap3logic_init_irq(void) -{ - omap2_init_common_hw(NULL, NULL); - omap_init_irq(); - omap_gpio_init(); -} - -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - -static void __init omap3logic_init(void) -{ - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap3torpedo_fix_pbias_voltage(); - omap3logic_i2c_init(); - omap_serial_init(); - board_mmc_init(); - board_smsc911x_init(); - - /* Ensure SDRC pins are mux'd for self-refresh */ - omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); - omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); -} - -MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board") - .boot_params = 0x80000100, - .map_io = omap3_map_io, - .init_irq = omap3logic_init_irq, - .init_machine = omap3logic_init, - .timer = &omap_timer, -MACHINE_END - -MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board") - .boot_params = 0x80000100, - .map_io = omap3_map_io, - .init_irq = omap3logic_init_irq, - .init_machine = omap3logic_init, - .timer = &omap_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-omap2/board-omap3pandora.c b/trunk/arch/arm/mach-omap2/board-omap3pandora.c index 89ed1be2d62e..41d6f549070c 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3pandora.c +++ b/trunk/arch/arm/mach-omap2/board-omap3pandora.c @@ -32,9 +32,7 @@ #include #include #include -#include #include -#include #include #include @@ -278,14 +276,14 @@ static void pandora_wl1251_init_card(struct mmc_card *card) static struct omap2_hsmmc_info omap3pandora_mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = 126, .ext_clock = 0, }, { .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = 127, .ext_clock = 1, @@ -293,7 +291,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = { }, { .mmc = 3, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .init_card = pandora_wl1251_init_card, @@ -346,9 +344,6 @@ static struct regulator_consumer_supply pandora_vmmc1_supply = static struct regulator_consumer_supply pandora_vmmc2_supply = REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); -static struct regulator_consumer_supply pandora_vmmc3_supply = - REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.2"); - static struct regulator_consumer_supply pandora_vdda_dac_supply = REGULATOR_SUPPLY("vdda_dac", "omapdss"); @@ -493,33 +488,6 @@ static struct regulator_init_data pandora_vsim = { .consumer_supplies = &pandora_adac_supply, }; -/* Fixed regulator internal to Wifi module */ -static struct regulator_init_data pandora_vmmc3 = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &pandora_vmmc3_supply, -}; - -static struct fixed_voltage_config pandora_vwlan = { - .supply_name = "vwlan", - .microvolts = 1800000, /* 1.8V */ - .gpio = PANDORA_WIFI_NRESET_GPIO, - .startup_delay = 50000, /* 50ms */ - .enable_high = 1, - .enabled_at_boot = 0, - .init_data = &pandora_vmmc3, -}; - -static struct platform_device pandora_vwlan_device = { - .name = "reg-fixed-voltage", - .id = 1, - .dev = { - .platform_data = &pandora_vwlan, - }, -}; - static struct twl4030_usb_data omap3pandora_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; @@ -533,8 +501,6 @@ static struct twl4030_codec_data omap3pandora_codec_data = { .audio = &omap3pandora_audio_data, }; -static struct twl4030_bci_platform_data pandora_bci_data; - static struct twl4030_platform_data omap3pandora_twldata = { .irq_base = TWL4030_IRQ_BASE, .irq_end = TWL4030_IRQ_END, @@ -550,7 +516,6 @@ static struct twl4030_platform_data omap3pandora_twldata = { .vaux4 = &pandora_vaux4, .vsim = &pandora_vsim, .keypad = &pandora_kp_data, - .bci = &pandora_bci_data, }; static struct i2c_board_info __initdata omap3pandora_i2c_boardinfo[] = { @@ -679,8 +644,19 @@ static void pandora_wl1251_init(void) if (pandora_wl1251_pdata.irq < 0) goto fail_irq; + ret = gpio_request(PANDORA_WIFI_NRESET_GPIO, "wl1251 nreset"); + if (ret < 0) + goto fail_irq; + + /* start powered so that it probes with MMC subsystem */ + ret = gpio_direction_output(PANDORA_WIFI_NRESET_GPIO, 1); + if (ret < 0) + goto fail_nreset; + return; +fail_nreset: + gpio_free(PANDORA_WIFI_NRESET_GPIO); fail_irq: gpio_free(PANDORA_WIFI_IRQ_GPIO); fail: @@ -692,7 +668,6 @@ static struct platform_device *omap3pandora_devices[] __initdata = { &pandora_keys_gpio, &pandora_dss_device, &pandora_wl1251_data, - &pandora_vwlan_device, }; static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { diff --git a/trunk/arch/arm/mach-omap2/board-omap3stalker.c b/trunk/arch/arm/mach-omap2/board-omap3stalker.c index f25272125413..bc5ac83bd4cf 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3stalker.c +++ b/trunk/arch/arm/mach-omap2/board-omap3stalker.c @@ -26,7 +26,6 @@ #include #include -#include #include #include @@ -39,6 +38,7 @@ #include #include #include +#include #include #include @@ -52,7 +52,6 @@ #include "sdram-micron-mt46h32m32lf-6.h" #include "mux.h" #include "hsmmc.h" -#include "timer-gp.h" #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) #define OMAP3STALKER_ETHR_START 0x2c000000 @@ -276,7 +275,7 @@ static struct regulator_init_data omap3stalker_vsim = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = 23, }, @@ -390,7 +389,7 @@ static struct twl4030_usb_data omap3stalker_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static uint32_t board_keymap[] = { +static int board_keymap[] = { KEY(0, 0, KEY_LEFT), KEY(0, 1, KEY_DOWN), KEY(0, 2, KEY_ENTER), @@ -565,7 +564,7 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = { .single_channel = 1, /* 0: slave, 1: master */ }; -static struct spi_board_info omap3stalker_spi_board_info[] = { +struct spi_board_info omap3stalker_spi_board_info[] = { [0] = { .modalias = "ads7846", .bus_num = 1, diff --git a/trunk/arch/arm/mach-omap2/board-omap3touchbook.c b/trunk/arch/arm/mach-omap2/board-omap3touchbook.c index 41104bb8774c..0e99ce584dbf 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/trunk/arch/arm/mach-omap2/board-omap3touchbook.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include @@ -48,10 +47,10 @@ #include #include #include +#include #include "mux.h" #include "hsmmc.h" -#include "timer-gp.h" #include @@ -62,7 +61,7 @@ #define TB_BL_PWM_TIMER 9 #define TB_KILL_POWER_GPIO 168 -static unsigned long touchbook_revision; +unsigned long touchbook_revision; static struct mtd_partition omap3touchbook_nand_partitions[] = { /* All the partition sizes are listed in terms of NAND block size */ @@ -109,7 +108,7 @@ static struct omap_nand_platform_data omap3touchbook_nand_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_wp = 29, }, {} /* Terminator */ diff --git a/trunk/arch/arm/mach-omap2/board-omap4panda.c b/trunk/arch/arm/mach-omap2/board-omap4panda.c index 702f2a63f2c1..db69bcadf4c7 100644 --- a/trunk/arch/arm/mach-omap2/board-omap4panda.c +++ b/trunk/arch/arm/mach-omap2/board-omap4panda.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -34,45 +33,12 @@ #include #include +#include +#include #include #include -#include "timer-gp.h" - #include "hsmmc.h" -#include "control.h" - -#define GPIO_HUB_POWER 1 -#define GPIO_HUB_NRESET 62 - -static struct gpio_led gpio_leds[] = { - { - .name = "pandaboard::status1", - .default_trigger = "heartbeat", - .gpio = 7, - }, - { - .name = "pandaboard::status2", - .default_trigger = "mmc0", - .gpio = 8, - }, -}; -static struct gpio_led_platform_data gpio_led_info = { - .leds = gpio_leds, - .num_leds = ARRAY_SIZE(gpio_leds), -}; - -static struct platform_device leds_gpio = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &gpio_led_info, - }, -}; - -static struct platform_device *panda_devices[] __initdata = { - &leds_gpio, -}; static void __init omap4_panda_init_irq(void) { @@ -81,56 +47,6 @@ static void __init omap4_panda_init_irq(void) omap_gpio_init(); } -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .phy_reset = false, - .reset_gpio_port[0] = -EINVAL, - .reset_gpio_port[1] = -EINVAL, - .reset_gpio_port[2] = -EINVAL -}; - -static void __init omap4_ehci_init(void) -{ - int ret; - - - /* disable the power to the usb hub prior to init */ - ret = gpio_request(GPIO_HUB_POWER, "hub_power"); - if (ret) { - pr_err("Cannot request GPIO %d\n", GPIO_HUB_POWER); - goto error1; - } - gpio_export(GPIO_HUB_POWER, 0); - gpio_direction_output(GPIO_HUB_POWER, 0); - gpio_set_value(GPIO_HUB_POWER, 0); - - /* reset phy+hub */ - ret = gpio_request(GPIO_HUB_NRESET, "hub_nreset"); - if (ret) { - pr_err("Cannot request GPIO %d\n", GPIO_HUB_NRESET); - goto error2; - } - gpio_export(GPIO_HUB_NRESET, 0); - gpio_direction_output(GPIO_HUB_NRESET, 0); - gpio_set_value(GPIO_HUB_NRESET, 0); - gpio_set_value(GPIO_HUB_NRESET, 1); - - usb_ehci_init(&ehci_pdata); - - /* enable power to hub */ - gpio_set_value(GPIO_HUB_POWER, 1); - return; - -error2: - gpio_free(GPIO_HUB_POWER); -error1: - pr_err("Unable to initialize EHCI power/reset\n"); - return; - -} - static struct omap_musb_board_data musb_board_data = { .interface_type = MUSB_INTERFACE_UTMI, .mode = MUSB_PERIPHERAL, @@ -140,7 +56,7 @@ static struct omap_musb_board_data musb_board_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_wp = -EINVAL, }, {} /* Terminator */ @@ -151,6 +67,10 @@ static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = { .supply = "vmmc", .dev_name = "mmci-omap-hs.0", }, + { + .supply = "vmmc", + .dev_name = "mmci-omap-hs.1", + }, }; static int omap4_twl6030_hsmmc_late_init(struct device *dev) @@ -169,14 +89,7 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev) static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) { - struct omap_mmc_platform_data *pdata; - - /* dev can be null if CONFIG_MMC_OMAP_HS is not set */ - if (!dev) { - pr_err("Failed omap4_twl6030_hsmmc_set_late_init\n"); - return; - } - pdata = dev->platform_data; + struct omap_mmc_platform_data *pdata = dev->platform_data; pdata->init = omap4_twl6030_hsmmc_late_init; } @@ -243,7 +156,7 @@ static struct regulator_init_data omap4_panda_vmmc = { | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, + .num_consumer_supplies = 2, .consumer_supplies = omap4_panda_vmmc_supply, }; @@ -361,13 +274,13 @@ static int __init omap4_panda_i2c_init(void) } static void __init omap4_panda_init(void) { + int status; + omap4_panda_i2c_init(); - platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); /* OMAP4 Panda uses internal transceiver so register nop transceiver */ usb_nop_xceiv_register(); - omap4_ehci_init(); /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ if (!cpu_is_omap44xx()) usb_musb_init(&musb_board_data); diff --git a/trunk/arch/arm/mach-omap2/board-overo.c b/trunk/arch/arm/mach-omap2/board-overo.c index 7053bc0b46db..5e528ca015a1 100644 --- a/trunk/arch/arm/mach-omap2/board-overo.c +++ b/trunk/arch/arm/mach-omap2/board-overo.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include @@ -304,13 +303,13 @@ static void __init overo_flash_init(void) static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, { .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .transceiver = true, diff --git a/trunk/arch/arm/mach-omap2/board-rx51-peripherals.c b/trunk/arch/arm/mach-omap2/board-rx51-peripherals.c index 41285297eafc..63d786bccb67 100644 --- a/trunk/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/trunk/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -33,8 +33,6 @@ #include #include -#include - #include #include @@ -187,7 +185,7 @@ static void __init rx51_add_gpio_keys(void) } #endif /* CONFIG_KEYBOARD_GPIO || CONFIG_KEYBOARD_GPIO_MODULE */ -static uint32_t board_keymap[] = { +static int board_keymap[] = { /* * Note that KEY(x, 8, KEY_XXX) entries represent "entrire row * connected to the ground" matrix state. @@ -305,7 +303,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .cover_only = true, .gpio_cd = 160, .gpio_wp = -EINVAL, @@ -314,8 +312,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "internal", .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, - /* See also rx51_mmc2_remux */ + .wires = 8, /* See also rx51_mmc2_remux */ .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .nonremovable = true, diff --git a/trunk/arch/arm/mach-omap2/board-rx51-sdram.c b/trunk/arch/arm/mach-omap2/board-rx51-sdram.c index a43b2c5c838b..f392844195d2 100644 --- a/trunk/arch/arm/mach-omap2/board-rx51-sdram.c +++ b/trunk/arch/arm/mach-omap2/board-rx51-sdram.c @@ -43,7 +43,7 @@ struct sdram_timings { u32 tWTR; }; -static struct omap_sdrc_params rx51_sdrc_params[4]; +struct omap_sdrc_params rx51_sdrc_params[4]; static const struct sdram_timings rx51_timings[] = { { diff --git a/trunk/arch/arm/mach-omap2/board-rx51-video.c b/trunk/arch/arm/mach-omap2/board-rx51-video.c index 85503fed4e13..5a1005ba9815 100644 --- a/trunk/arch/arm/mach-omap2/board-rx51-video.c +++ b/trunk/arch/arm/mach-omap2/board-rx51-video.c @@ -20,8 +20,6 @@ #include #include -#include - #include "mux.h" #define RX51_LCD_RESET_GPIO 90 diff --git a/trunk/arch/arm/mach-omap2/board-zoom-debugboard.c b/trunk/arch/arm/mach-omap2/board-zoom-debugboard.c index 007ebdc6c993..1d7f827b0408 100644 --- a/trunk/arch/arm/mach-omap2/board-zoom-debugboard.c +++ b/trunk/arch/arm/mach-omap2/board-zoom-debugboard.c @@ -16,8 +16,6 @@ #include -#include - #define ZOOM_SMSC911X_CS 7 #define ZOOM_SMSC911X_GPIO 158 #define ZOOM_QUADUART_CS 3 diff --git a/trunk/arch/arm/mach-omap2/board-zoom-peripherals.c b/trunk/arch/arm/mach-omap2/board-zoom-peripherals.c index 86c9b2102952..bc8232845d7a 100644 --- a/trunk/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/trunk/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include @@ -36,7 +35,7 @@ #define OMAP_ZOOM_WLAN_IRQ_GPIO (162) /* Zoom2 has Qwerty keyboard*/ -static uint32_t board_keymap[] = { +static int board_keymap[] = { KEY(0, 0, KEY_E), KEY(0, 1, KEY_R), KEY(0, 2, KEY_T), @@ -200,14 +199,14 @@ static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .gpio_wp = -EINVAL, .power_saving = true, }, { .name = "internal", .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .wires = 8, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .nonremovable = true, @@ -349,5 +348,4 @@ void __init zoom_peripherals_init(void) platform_device_register(&omap_vwlan_device); usb_musb_init(&musb_board_data); enable_board_wakeup_source(); - omap_serial_init(); } diff --git a/trunk/arch/arm/mach-omap2/board-zoom2.c b/trunk/arch/arm/mach-omap2/board-zoom2.c index 2992a9f3a585..4ccbc32386a0 100644 --- a/trunk/arch/arm/mach-omap2/board-zoom2.c +++ b/trunk/arch/arm/mach-omap2/board-zoom2.c @@ -24,7 +24,6 @@ #include -#include "board-flash.h" #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" diff --git a/trunk/arch/arm/mach-omap2/board-zoom3.c b/trunk/arch/arm/mach-omap2/board-zoom3.c index 5adde12c0395..b2bb3ff971ac 100644 --- a/trunk/arch/arm/mach-omap2/board-zoom3.c +++ b/trunk/arch/arm/mach-omap2/board-zoom3.c @@ -22,7 +22,6 @@ #include #include -#include "board-flash.h" #include "mux.h" #include "sdram-hynix-h8mbx00u0mer-0em.h" diff --git a/trunk/arch/arm/mach-omap2/clock.c b/trunk/arch/arm/mach-omap2/clock.c index b5babf5440e4..605f531783a8 100644 --- a/trunk/arch/arm/mach-omap2/clock.c +++ b/trunk/arch/arm/mach-omap2/clock.c @@ -395,7 +395,7 @@ void omap2_clk_disable_unused(struct clk *clk) if ((regval32 & (1 << clk->enable_bit)) == v) return; - pr_debug("Disabling unused clock \"%s\"\n", clk->name); + printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name); if (cpu_is_omap34xx()) { omap2_clk_enable(clk); omap2_clk_disable(clk); diff --git a/trunk/arch/arm/mach-omap2/clock2420_data.c b/trunk/arch/arm/mach-omap2/clock2420_data.c index 21f856252ad8..5f2066a6ba74 100644 --- a/trunk/arch/arm/mach-omap2/clock2420_data.c +++ b/trunk/arch/arm/mach-omap2/clock2420_data.c @@ -27,7 +27,6 @@ #include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" #include "sdrc.h" -#include "control.h" #define OMAP_CM_REGADDR OMAP2420_CM_REGADDR @@ -90,12 +89,6 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ .clkdm_name = "wkup_clkdm", }; -/* Optional external clock input for McBSP CLKS */ -static struct clk mcbsp_clks = { - .name = "mcbsp_clks", - .ops = &clkops_null, -}; - /* * Analog domain root source clocks */ @@ -1142,34 +1135,14 @@ static struct clk mcbsp1_ick = { .recalc = &followparent_recalc, }; -static const struct clksel_rate common_mcbsp_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel mcbsp_fck_clksel[] = { - { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, - { .parent = NULL } -}; - static struct clk mcbsp1_fck = { .name = "mcbsp1_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, - .clksel = mcbsp_fck_clksel, - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; static struct clk mcbsp2_ick = { @@ -1186,14 +1159,10 @@ static struct clk mcbsp2_fck = { .name = "mcbsp2_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, - .clksel = mcbsp_fck_clksel, - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; static struct clk mcspi1_ick = { @@ -1752,9 +1721,6 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "osc_ck", &osc_ck, CK_242X), CLK(NULL, "sys_ck", &sys_ck, CK_242X), CLK(NULL, "alt_ck", &alt_ck, CK_242X), - CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_242X), - CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_242X), - CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), /* internal analog sources */ CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), @@ -1762,8 +1728,6 @@ static struct omap_clk omap2420_clks[] = { /* internal prcm root sources */ CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), CLK(NULL, "core_ck", &core_ck, CK_242X), - CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_242X), - CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_242X), CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), diff --git a/trunk/arch/arm/mach-omap2/clock2430_data.c b/trunk/arch/arm/mach-omap2/clock2430_data.c index e32afcbdfb88..701a1716019e 100644 --- a/trunk/arch/arm/mach-omap2/clock2430_data.c +++ b/trunk/arch/arm/mach-omap2/clock2430_data.c @@ -27,7 +27,6 @@ #include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" #include "sdrc.h" -#include "control.h" #define OMAP_CM_REGADDR OMAP2430_CM_REGADDR @@ -90,12 +89,6 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ .clkdm_name = "wkup_clkdm", }; -/* Optional external clock input for McBSP CLKS */ -static struct clk mcbsp_clks = { - .name = "mcbsp_clks", - .ops = &clkops_null, -}; - /* * Analog domain root source clocks */ @@ -1130,34 +1123,14 @@ static struct clk mcbsp1_ick = { .recalc = &followparent_recalc, }; -static const struct clksel_rate common_mcbsp_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel mcbsp_fck_clksel[] = { - { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, - { .parent = NULL } -}; - static struct clk mcbsp1_fck = { .name = "mcbsp1_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, - .clksel = mcbsp_fck_clksel, - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; static struct clk mcbsp2_ick = { @@ -1174,14 +1147,10 @@ static struct clk mcbsp2_fck = { .name = "mcbsp2_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, - .clksel = mcbsp_fck_clksel, - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; static struct clk mcbsp3_ick = { @@ -1198,14 +1167,10 @@ static struct clk mcbsp3_fck = { .name = "mcbsp3_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, - .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), - .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, - .clksel = mcbsp_fck_clksel, - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; static struct clk mcbsp4_ick = { @@ -1222,14 +1187,10 @@ static struct clk mcbsp4_fck = { .name = "mcbsp4_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, - .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), - .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, - .clksel = mcbsp_fck_clksel, - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; static struct clk mcbsp5_ick = { @@ -1246,14 +1207,10 @@ static struct clk mcbsp5_fck = { .name = "mcbsp5_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, - .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), - .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, - .clksel = mcbsp_fck_clksel, - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; static struct clk mcspi1_ick = { @@ -1851,12 +1808,6 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "osc_ck", &osc_ck, CK_243X), CLK(NULL, "sys_ck", &sys_ck, CK_243X), CLK(NULL, "alt_ck", &alt_ck, CK_243X), - CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_243X), - CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_243X), - CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_243X), - CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_243X), - CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_243X), - CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), /* internal analog sources */ CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), CLK(NULL, "apll96_ck", &apll96_ck, CK_243X), @@ -1864,11 +1815,6 @@ static struct omap_clk omap2430_clks[] = { /* internal prcm root sources */ CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), CLK(NULL, "core_ck", &core_ck, CK_243X), - CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_243X), - CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_243X), - CLK("omap-mcbsp.3", "prcm_fck", &func_96m_ck, CK_243X), - CLK("omap-mcbsp.4", "prcm_fck", &func_96m_ck, CK_243X), - CLK("omap-mcbsp.5", "prcm_fck", &func_96m_ck, CK_243X), CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), diff --git a/trunk/arch/arm/mach-omap2/clock3xxx_data.c b/trunk/arch/arm/mach-omap2/clock3xxx_data.c index d85ecd5aebfd..c73906d17458 100644 --- a/trunk/arch/arm/mach-omap2/clock3xxx_data.c +++ b/trunk/arch/arm/mach-omap2/clock3xxx_data.c @@ -20,6 +20,7 @@ #include #include +#include #include #include "clock.h" @@ -32,7 +33,6 @@ #include "cm-regbits-34xx.h" #include "prm.h" #include "prm-regbits-34xx.h" -#include "control.h" /* * clocks @@ -2465,16 +2465,6 @@ static struct clk uart3_fck = { .recalc = &followparent_recalc, }; -static struct clk uart4_fck = { - .name = "uart4_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_48m_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3630_EN_UART4_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - static struct clk gpt2_fck = { .name = "gpt2_fck", .ops = &clkops_omap2_dflt_wait, @@ -2725,16 +2715,6 @@ static struct clk uart3_ick = { .recalc = &followparent_recalc, }; -static struct clk uart4_ick = { - .name = "uart4_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3630_EN_UART4_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - static struct clk gpt9_ick = { .name = "gpt9_ick", .ops = &clkops_omap2_dflt_wait, @@ -3208,11 +3188,6 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), - CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_3XXX), - CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_3XXX), - CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_3XXX), - CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_3XXX), - CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_3XXX), CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), @@ -3278,8 +3253,6 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX), CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX), CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX), - CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), - CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX), CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), @@ -3373,13 +3346,9 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), - CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck, CK_3XXX), - CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck, CK_3XXX), - CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck, CK_3XXX), CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), - CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX), CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), @@ -3403,7 +3372,6 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX), CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX), CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX), - CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX), CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX), CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX), CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX), diff --git a/trunk/arch/arm/mach-omap2/clock44xx_data.c b/trunk/arch/arm/mach-omap2/clock44xx_data.c index 1599836ba3d9..e10db7a90cb2 100644 --- a/trunk/arch/arm/mach-omap2/clock44xx_data.c +++ b/trunk/arch/arm/mach-omap2/clock44xx_data.c @@ -17,15 +17,13 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * - * XXX Some of the ES1 clocks have been removed/changed; once support - * is added for discriminating clocks by ES level, these should be added back - * in. */ #include #include #include + +#include #include #include "clock.h" @@ -34,7 +32,6 @@ #include "cm-regbits-44xx.h" #include "prm.h" #include "prm-regbits-44xx.h" -#include "control.h" /* Root clocks */ @@ -178,27 +175,21 @@ static struct clk sys_clkin_ck = { .recalc = &omap2_clksel_recalc, }; -static struct clk tie_low_clock_ck = { - .name = "tie_low_clock_ck", - .rate = 0, - .ops = &clkops_null, -}; - static struct clk utmi_phy_clkout_ck = { .name = "utmi_phy_clkout_ck", - .rate = 60000000, + .rate = 12000000, .ops = &clkops_null, }; static struct clk xclk60mhsp1_ck = { .name = "xclk60mhsp1_ck", - .rate = 60000000, + .rate = 12000000, .ops = &clkops_null, }; static struct clk xclk60mhsp2_ck = { .name = "xclk60mhsp2_ck", - .rate = 60000000, + .rate = 12000000, .ops = &clkops_null, }; @@ -210,23 +201,39 @@ static struct clk xclk60motg_ck = { /* Module clocks and DPLL outputs */ -static const struct clksel abe_dpll_bypass_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, +static const struct clksel_rate div2_1to2_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_4430 }, + { .div = 2, .val = 1, .flags = RATE_IN_4430 }, + { .div = 0 }, +}; + +static const struct clksel dpll_sys_ref_clk_div[] = { + { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, { .parent = NULL }, }; -static struct clk abe_dpll_bypass_clk_mux_ck = { - .name = "abe_dpll_bypass_clk_mux_ck", +static struct clk dpll_sys_ref_clk = { + .name = "dpll_sys_ref_clk", .parent = &sys_clkin_ck, + .clksel = dpll_sys_ref_clk_div, + .clksel_reg = OMAP4430_CM_DPLL_SYS_REF_CLKSEL, + .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, .ops = &clkops_null, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static const struct clksel abe_dpll_refclk_mux_sel[] = { + { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, + { .parent = NULL }, }; static struct clk abe_dpll_refclk_mux_ck = { .name = "abe_dpll_refclk_mux_ck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, + .parent = &dpll_sys_ref_clk, + .clksel = abe_dpll_refclk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL, .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, @@ -237,7 +244,7 @@ static struct clk abe_dpll_refclk_mux_ck = { /* DPLL_ABE */ static struct dpll_data dpll_abe_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, - .clk_bypass = &abe_dpll_bypass_clk_mux_ck, + .clk_bypass = &sys_clkin_ck, .clk_ref = &abe_dpll_refclk_mux_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), @@ -303,12 +310,6 @@ static struct clk abe_clk = { .set_rate = &omap2_clksel_set_rate, }; -static const struct clksel_rate div2_1to2_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - static const struct clksel aess_fclk_div[] = { { .parent = &abe_clk, .rates = div2_1to2_rates }, { .parent = NULL }, @@ -379,14 +380,14 @@ static struct clk dpll_abe_m3_ck = { }; static const struct clksel core_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; static struct clk core_hsd_byp_clk_mux_ck = { .name = "core_hsd_byp_clk_mux_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .clksel = core_hsd_byp_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, @@ -399,7 +400,7 @@ static struct clk core_hsd_byp_clk_mux_ck = { static struct dpll_data dpll_core_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, .clk_bypass = &core_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, + .clk_ref = &dpll_sys_ref_clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, @@ -417,7 +418,7 @@ static struct dpll_data dpll_core_dd = { static struct clk dpll_core_ck = { .name = "dpll_core_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_core_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_null, @@ -595,14 +596,14 @@ static struct clk dpll_core_m7_ck = { }; static const struct clksel iva_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, { .parent = NULL }, }; static struct clk iva_hsd_byp_clk_mux_ck = { .name = "iva_hsd_byp_clk_mux_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .ops = &clkops_null, .recalc = &followparent_recalc, }; @@ -611,7 +612,7 @@ static struct clk iva_hsd_byp_clk_mux_ck = { static struct dpll_data dpll_iva_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, .clk_bypass = &iva_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, + .clk_ref = &dpll_sys_ref_clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, @@ -629,7 +630,7 @@ static struct dpll_data dpll_iva_dd = { static struct clk dpll_iva_ck = { .name = "dpll_iva_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_iva_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -671,7 +672,7 @@ static struct clk dpll_iva_m5_ck = { static struct dpll_data dpll_mpu_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, .clk_bypass = &div_mpu_hs_clk, - .clk_ref = &sys_clkin_ck, + .clk_ref = &dpll_sys_ref_clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, @@ -689,7 +690,7 @@ static struct dpll_data dpll_mpu_dd = { static struct clk dpll_mpu_ck = { .name = "dpll_mpu_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_mpu_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -723,14 +724,14 @@ static struct clk per_hs_clk_div_ck = { }; static const struct clksel per_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; static struct clk per_hsd_byp_clk_mux_ck = { .name = "per_hsd_byp_clk_mux_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .clksel = per_hsd_byp_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER, @@ -743,7 +744,7 @@ static struct clk per_hsd_byp_clk_mux_ck = { static struct dpll_data dpll_per_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, .clk_bypass = &per_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, + .clk_ref = &dpll_sys_ref_clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, @@ -761,7 +762,7 @@ static struct dpll_data dpll_per_dd = { static struct clk dpll_per_ck = { .name = "dpll_per_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_per_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -857,8 +858,8 @@ static struct clk dpll_per_m7_ck = { /* DPLL_UNIPRO */ static struct dpll_data dpll_unipro_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, + .clk_bypass = &dpll_sys_ref_clk, + .clk_ref = &dpll_sys_ref_clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO, @@ -876,7 +877,7 @@ static struct dpll_data dpll_unipro_dd = { static struct clk dpll_unipro_ck = { .name = "dpll_unipro_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_unipro_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -913,8 +914,7 @@ static struct clk usb_hs_clk_div_ck = { static struct dpll_data dpll_usb_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, .clk_bypass = &usb_hs_clk_div_ck, - .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL, - .clk_ref = &sys_clkin_ck, + .clk_ref = &dpll_sys_ref_clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, @@ -927,12 +927,13 @@ static struct dpll_data dpll_usb_dd = { .max_multiplier = OMAP4430_MAX_DPLL_MULT, .max_divider = OMAP4430_MAX_DPLL_DIV, .min_divider = 1, + .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL }; static struct clk dpll_usb_ck = { .name = "dpll_usb_ck", - .parent = &sys_clkin_ck, + .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_usb_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -1221,7 +1222,7 @@ static struct clk per_abe_24m_fclk = { static const struct clksel pmd_stm_clock_mux_sel[] = { { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, - { .parent = &tie_low_clock_ck, .rates = div_1_2_rates }, + { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates }, { .parent = NULL }, }; @@ -1239,15 +1240,10 @@ static struct clk pmd_trace_clk_mux_ck = { .recalc = &followparent_recalc, }; -static const struct clksel syc_clk_div_div[] = { - { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; - static struct clk syc_clk_div_ck = { .name = "syc_clk_div_ck", .parent = &sys_clkin_ck, - .clksel = syc_clk_div_div, + .clksel = dpll_sys_ref_clk_div, .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL, .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, .ops = &clkops_null, @@ -1288,13 +1284,13 @@ static struct clk aess_fck = { .recalc = &followparent_recalc, }; -static struct clk bandgap_fclk = { - .name = "bandgap_fclk", +static struct clk cust_efuse_fck = { + .name = "cust_efuse_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, + .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_cefuse_clkdm", + .parent = &sys_clkin_ck, .recalc = &followparent_recalc, }; @@ -1348,56 +1344,6 @@ static struct clk dmic_fck = { .clkdm_name = "abe_clkdm", }; -static struct clk dsp_fck = { - .name = "dsp_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "tesla_clkdm", - .parent = &dpll_iva_m4_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dss_sys_clk = { - .name = "dss_sys_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, - .clkdm_name = "l3_dss_clkdm", - .parent = &syc_clk_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dss_tv_clk = { - .name = "dss_tv_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, - .clkdm_name = "l3_dss_clkdm", - .parent = &extalt_clkin_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dss_dss_clk = { - .name = "dss_dss_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, - .clkdm_name = "l3_dss_clkdm", - .parent = &dpll_per_m5_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dss_48mhz_clk = { - .name = "dss_48mhz_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, - .clkdm_name = "l3_dss_clkdm", - .parent = &func_48mc_fclk, - .recalc = &followparent_recalc, -}; - static struct clk dss_fck = { .name = "dss_fck", .ops = &clkops_omap2_dflt, @@ -1408,18 +1354,18 @@ static struct clk dss_fck = { .recalc = &followparent_recalc, }; -static struct clk efuse_ctrl_cust_fck = { - .name = "efuse_ctrl_cust_fck", +static struct clk ducati_ick = { + .name = "ducati_ick", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_cefuse_clkdm", - .parent = &sys_clkin_ck, + .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .clkdm_name = "ducati_clkdm", + .parent = &ducati_clk_mux_ck, .recalc = &followparent_recalc, }; -static struct clk emif1_fck = { - .name = "emif1_fck", +static struct clk emif1_ick = { + .name = "emif1_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1429,8 +1375,8 @@ static struct clk emif1_fck = { .recalc = &followparent_recalc, }; -static struct clk emif2_fck = { - .name = "emif2_fck", +static struct clk emif2_ick = { + .name = "emif2_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1461,24 +1407,42 @@ static struct clk fdif_fck = { .clkdm_name = "iss_clkdm", }; -static struct clk fpka_fck = { - .name = "fpka_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, +static const struct clksel per_sgx_fclk_div[] = { + { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, + { .parent = NULL }, +}; + +static struct clk per_sgx_fclk = { + .name = "per_sgx_fclk", + .parent = &dpll_per_m2x2_ck, + .clksel = per_sgx_fclk_div, + .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_PER_192M_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static const struct clksel sgx_clk_mux_sel[] = { + { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates }, + { .parent = &per_sgx_fclk, .rates = div_1_1_rates }, + { .parent = NULL }, }; -static struct clk gpio1_dbclk = { - .name = "gpio1_dbclk", +/* Merged sgx_clk_mux into gfx */ +static struct clk gfx_fck = { + .name = "gfx_fck", + .parent = &dpll_core_m7_ck, + .clksel = sgx_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l3_gfx_clkdm", }; static struct clk gpio1_ick = { @@ -1491,16 +1455,6 @@ static struct clk gpio1_ick = { .recalc = &followparent_recalc, }; -static struct clk gpio2_dbclk = { - .name = "gpio2_dbclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - static struct clk gpio2_ick = { .name = "gpio2_ick", .ops = &clkops_omap2_dflt, @@ -1511,16 +1465,6 @@ static struct clk gpio2_ick = { .recalc = &followparent_recalc, }; -static struct clk gpio3_dbclk = { - .name = "gpio3_dbclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - static struct clk gpio3_ick = { .name = "gpio3_ick", .ops = &clkops_omap2_dflt, @@ -1531,16 +1475,6 @@ static struct clk gpio3_ick = { .recalc = &followparent_recalc, }; -static struct clk gpio4_dbclk = { - .name = "gpio4_dbclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - static struct clk gpio4_ick = { .name = "gpio4_ick", .ops = &clkops_omap2_dflt, @@ -1551,16 +1485,6 @@ static struct clk gpio4_ick = { .recalc = &followparent_recalc, }; -static struct clk gpio5_dbclk = { - .name = "gpio5_dbclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - static struct clk gpio5_ick = { .name = "gpio5_ick", .ops = &clkops_omap2_dflt, @@ -1571,16 +1495,6 @@ static struct clk gpio5_ick = { .recalc = &followparent_recalc, }; -static struct clk gpio6_dbclk = { - .name = "gpio6_dbclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - static struct clk gpio6_ick = { .name = "gpio6_ick", .ops = &clkops_omap2_dflt, @@ -1601,114 +1515,278 @@ static struct clk gpmc_ick = { .recalc = &followparent_recalc, }; -static const struct clksel sgx_clk_mux_sel[] = { - { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates }, +static const struct clksel dmt1_clk_mux_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; -/* Merged sgx_clk_mux into gpu */ -static struct clk gpu_fck = { - .name = "gpu_fck", - .parent = &dpll_core_m7_ck, - .clksel = sgx_clk_mux_sel, +/* + * Merged dmt1_clk_mux into gptimer1 + * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention + */ +static struct clk gpt1_fck = { + .name = "gpt1_fck", + .parent = &sys_clkin_ck, + .clksel = dmt1_clk_mux_sel, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, + .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, .ops = &clkops_omap2_dflt, .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, + .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_gfx_clkdm", + .clkdm_name = "l4_wkup_clkdm", }; -static struct clk hdq1w_fck = { - .name = "hdq1w_fck", +/* + * Merged cm2_dm10_mux into gptimer10 + * gptimer10 renamed temporarily into gpt10 to match OMAP3 convention + */ +static struct clk gpt10_fck = { + .name = "gpt10_fck", + .parent = &sys_clkin_ck, + .clksel = dmt1_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", - .parent = &func_12m_fclk, - .recalc = &followparent_recalc, -}; - -static const struct clksel hsi_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, }; -/* Merged hsi_fclk into hsi */ -static struct clk hsi_fck = { - .name = "hsi_fck", - .parent = &dpll_per_m2x2_ck, - .clksel = hsi_fclk_div, - .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, +/* + * Merged cm2_dm11_mux into gptimer11 + * gptimer11 renamed temporarily into gpt11 to match OMAP3 convention + */ +static struct clk gpt11_fck = { + .name = "gpt11_fck", + .parent = &sys_clkin_ck, + .clksel = dmt1_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, .ops = &clkops_omap2_dflt, .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", -}; - -static struct clk i2c1_fck = { - .name = "i2c1_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, }; -static struct clk i2c2_fck = { - .name = "i2c2_fck", +/* + * Merged cm2_dm2_mux into gptimer2 + * gptimer2 renamed temporarily into gpt2 to match OMAP3 convention + */ +static struct clk gpt2_fck = { + .name = "gpt2_fck", + .parent = &sys_clkin_ck, + .clksel = dmt1_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, }; -static struct clk i2c3_fck = { - .name = "i2c3_fck", +/* + * Merged cm2_dm3_mux into gptimer3 + * gptimer3 renamed temporarily into gpt3 to match OMAP3 convention + */ +static struct clk gpt3_fck = { + .name = "gpt3_fck", + .parent = &sys_clkin_ck, + .clksel = dmt1_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, }; -static struct clk i2c4_fck = { - .name = "i2c4_fck", +/* + * Merged cm2_dm4_mux into gptimer4 + * gptimer4 renamed temporarily into gpt4 to match OMAP3 convention + */ +static struct clk gpt4_fck = { + .name = "gpt4_fck", + .parent = &sys_clkin_ck, + .clksel = dmt1_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, +}; + +static const struct clksel timer5_sync_mux_sel[] = { + { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +/* + * Merged timer5_sync_mux into gptimer5 + * gptimer5 renamed temporarily into gpt5 to match OMAP3 convention + */ +static struct clk gpt5_fck = { + .name = "gpt5_fck", + .parent = &syc_clk_div_ck, + .clksel = timer5_sync_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", +}; + +/* + * Merged timer6_sync_mux into gptimer6 + * gptimer6 renamed temporarily into gpt6 to match OMAP3 convention + */ +static struct clk gpt6_fck = { + .name = "gpt6_fck", + .parent = &syc_clk_div_ck, + .clksel = timer5_sync_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", +}; + +/* + * Merged timer7_sync_mux into gptimer7 + * gptimer7 renamed temporarily into gpt7 to match OMAP3 convention + */ +static struct clk gpt7_fck = { + .name = "gpt7_fck", + .parent = &syc_clk_div_ck, + .clksel = timer5_sync_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", +}; + +/* + * Merged timer8_sync_mux into gptimer8 + * gptimer8 renamed temporarily into gpt8 to match OMAP3 convention + */ +static struct clk gpt8_fck = { + .name = "gpt8_fck", + .parent = &syc_clk_div_ck, + .clksel = timer5_sync_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", +}; + +/* + * Merged cm2_dm9_mux into gptimer9 + * gptimer9 renamed temporarily into gpt9 to match OMAP3 convention + */ +static struct clk gpt9_fck = { + .name = "gpt9_fck", + .parent = &sys_clkin_ck, + .clksel = dmt1_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", +}; + +static struct clk hdq1w_fck = { + .name = "hdq1w_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", + .parent = &func_12m_fclk, .recalc = &followparent_recalc, }; -static struct clk ipu_fck = { - .name = "ipu_fck", +/* Merged hsi_fclk into hsi */ +static struct clk hsi_ick = { + .name = "hsi_ick", + .parent = &dpll_per_m2x2_ck, + .clksel = per_sgx_fclk_div, + .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "ducati_clkdm", - .parent = &ducati_clk_mux_ck, + .clkdm_name = "l3_init_clkdm", +}; + +static struct clk i2c1_fck = { + .name = "i2c1_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", + .parent = &func_96m_fclk, .recalc = &followparent_recalc, }; -static struct clk iss_ctrlclk = { - .name = "iss_ctrlclk", +static struct clk i2c2_fck = { + .name = "i2c2_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, - .clkdm_name = "iss_clkdm", + .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", + .parent = &func_96m_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk i2c3_fck = { + .name = "i2c3_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", + .parent = &func_96m_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk i2c4_fck = { + .name = "i2c4_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", .parent = &func_96m_fclk, .recalc = &followparent_recalc, }; @@ -1723,8 +1801,8 @@ static struct clk iss_fck = { .recalc = &followparent_recalc, }; -static struct clk iva_fck = { - .name = "iva_fck", +static struct clk ivahd_ick = { + .name = "ivahd_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1733,8 +1811,8 @@ static struct clk iva_fck = { .recalc = &followparent_recalc, }; -static struct clk kbd_fck = { - .name = "kbd_fck", +static struct clk keyboard_fck = { + .name = "keyboard_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -1743,8 +1821,8 @@ static struct clk kbd_fck = { .recalc = &followparent_recalc, }; -static struct clk l3_instr_ick = { - .name = "l3_instr_ick", +static struct clk l3_instr_interconnect_ick = { + .name = "l3_instr_interconnect_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1753,8 +1831,8 @@ static struct clk l3_instr_ick = { .recalc = &followparent_recalc, }; -static struct clk l3_main_3_ick = { - .name = "l3_main_3_ick", +static struct clk l3_interconnect_3_ick = { + .name = "l3_interconnect_3_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1927,16 +2005,6 @@ static struct clk mcbsp4_fck = { .clkdm_name = "l4_per_clkdm", }; -static struct clk mcpdm_fck = { - .name = "mcpdm_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &pad_clks_ck, - .recalc = &followparent_recalc, -}; - static struct clk mcspi1_fck = { .name = "mcspi1_fck", .ops = &clkops_omap2_dflt, @@ -2037,33 +2105,33 @@ static struct clk mmc5_fck = { .recalc = &followparent_recalc, }; -static struct clk ocp2scp_usb_phy_phy_48m = { - .name = "ocp2scp_usb_phy_phy_48m", +static struct clk ocp_wp1_ick = { + .name = "ocp_wp1_ick", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &func_48m_fclk, + .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .clkdm_name = "l3_instr_clkdm", + .parent = &l3_div_ck, .recalc = &followparent_recalc, }; -static struct clk ocp2scp_usb_phy_ick = { - .name = "ocp2scp_usb_phy_ick", +static struct clk pdm_fck = { + .name = "pdm_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &l4_div_ck, + .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", + .parent = &pad_clks_ck, .recalc = &followparent_recalc, }; -static struct clk ocp_wp_noc_ick = { - .name = "ocp_wp_noc_ick", +static struct clk pkaeip29_fck = { + .name = "pkaeip29_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_instr_clkdm", - .parent = &l3_div_ck, + .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_secure_clkdm", + .parent = &l4_div_ck, .recalc = &followparent_recalc, }; @@ -2077,8 +2145,8 @@ static struct clk rng_ick = { .recalc = &followparent_recalc, }; -static struct clk sha2md5_fck = { - .name = "sha2md5_fck", +static struct clk sha2md51_fck = { + .name = "sha2md51_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2087,8 +2155,8 @@ static struct clk sha2md5_fck = { .recalc = &followparent_recalc, }; -static struct clk sl2if_ick = { - .name = "sl2if_ick", +static struct clk sl2_ick = { + .name = "sl2_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -2097,334 +2165,123 @@ static struct clk sl2if_ick = { .recalc = &followparent_recalc, }; -static struct clk slimbus1_fclk_1 = { - .name = "slimbus1_fclk_1", +static struct clk slimbus1_fck = { + .name = "slimbus1_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "abe_clkdm", - .parent = &func_24m_clk, + .parent = &ocp_abe_iclk, .recalc = &followparent_recalc, }; -static struct clk slimbus1_fclk_0 = { - .name = "slimbus1_fclk_0", +static struct clk slimbus2_fck = { + .name = "slimbus2_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT, - .clkdm_name = "abe_clkdm", - .parent = &abe_24m_fclk, + .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", + .parent = &l4_div_ck, .recalc = &followparent_recalc, }; -static struct clk slimbus1_fclk_2 = { - .name = "slimbus1_fclk_2", +static struct clk sr_core_fck = { + .name = "sr_core_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT, - .clkdm_name = "abe_clkdm", - .parent = &pad_clks_ck, + .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_ao_clkdm", + .parent = &l4_wkup_clk_mux_ck, .recalc = &followparent_recalc, }; -static struct clk slimbus1_slimbus_clk = { - .name = "slimbus1_slimbus_clk", +static struct clk sr_iva_fck = { + .name = "sr_iva_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, - .clkdm_name = "abe_clkdm", - .parent = &slimbus_clk, + .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_ao_clkdm", + .parent = &l4_wkup_clk_mux_ck, .recalc = &followparent_recalc, }; -static struct clk slimbus1_fck = { - .name = "slimbus1_fck", +static struct clk sr_mpu_fck = { + .name = "sr_mpu_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &ocp_abe_iclk, + .clkdm_name = "l4_ao_clkdm", + .parent = &l4_wkup_clk_mux_ck, .recalc = &followparent_recalc, }; -static struct clk slimbus2_fclk_1 = { - .name = "slimbus2_fclk_1", +static struct clk tesla_ick = { + .name = "tesla_ick", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &per_abe_24m_fclk, + .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .clkdm_name = "tesla_clkdm", + .parent = &dpll_iva_m4_ck, .recalc = &followparent_recalc, }; -static struct clk slimbus2_fclk_0 = { - .name = "slimbus2_fclk_0", +static struct clk uart1_fck = { + .name = "uart1_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, + .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", - .parent = &func_24mc_fclk, + .parent = &func_48m_fclk, .recalc = &followparent_recalc, }; -static struct clk slimbus2_slimbus_clk = { - .name = "slimbus2_slimbus_clk", +static struct clk uart2_fck = { + .name = "uart2_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, + .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", - .parent = &pad_slimbus_core_clks_ck, + .parent = &func_48m_fclk, .recalc = &followparent_recalc, }; -static struct clk slimbus2_fck = { - .name = "slimbus2_fck", +static struct clk uart3_fck = { + .name = "uart3_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, + .parent = &func_48m_fclk, .recalc = &followparent_recalc, }; -static struct clk smartreflex_core_fck = { - .name = "smartreflex_core_fck", +static struct clk uart4_fck = { + .name = "uart4_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, + .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_ao_clkdm", - .parent = &l4_wkup_clk_mux_ck, + .clkdm_name = "l4_per_clkdm", + .parent = &func_48m_fclk, .recalc = &followparent_recalc, }; -static struct clk smartreflex_iva_fck = { - .name = "smartreflex_iva_fck", +static struct clk unipro1_fck = { + .name = "unipro1_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, + .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_ao_clkdm", - .parent = &l4_wkup_clk_mux_ck, + .clkdm_name = "l3_init_clkdm", + .parent = &func_96m_fclk, .recalc = &followparent_recalc, }; -static struct clk smartreflex_mpu_fck = { - .name = "smartreflex_mpu_fck", +static struct clk usb_host_fck = { + .name = "usb_host_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_ao_clkdm", - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -/* Merged dmt1_clk_mux into timer1 */ -static struct clk timer1_fck = { - .name = "timer1_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_wkup_clkdm", -}; - -/* Merged cm2_dm10_mux into timer10 */ -static struct clk timer10_fck = { - .name = "timer10_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* Merged cm2_dm11_mux into timer11 */ -static struct clk timer11_fck = { - .name = "timer11_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* Merged cm2_dm2_mux into timer2 */ -static struct clk timer2_fck = { - .name = "timer2_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* Merged cm2_dm3_mux into timer3 */ -static struct clk timer3_fck = { - .name = "timer3_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* Merged cm2_dm4_mux into timer4 */ -static struct clk timer4_fck = { - .name = "timer4_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -static const struct clksel timer5_sync_mux_sel[] = { - { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -/* Merged timer5_sync_mux into timer5 */ -static struct clk timer5_fck = { - .name = "timer5_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* Merged timer6_sync_mux into timer6 */ -static struct clk timer6_fck = { - .name = "timer6_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* Merged timer7_sync_mux into timer7 */ -static struct clk timer7_fck = { - .name = "timer7_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* Merged timer8_sync_mux into timer8 */ -static struct clk timer8_fck = { - .name = "timer8_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* Merged cm2_dm9_mux into timer9 */ -static struct clk timer9_fck = { - .name = "timer9_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -static struct clk uart1_fck = { - .name = "uart1_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk uart2_fck = { - .name = "uart2_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk uart3_fck = { - .name = "uart3_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk uart4_fck = { - .name = "uart4_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, + .clkdm_name = "l3_init_clkdm", + .parent = &init_60m_fclk, .recalc = &followparent_recalc, }; @@ -2438,138 +2295,75 @@ static struct clk usb_host_fs_fck = { .recalc = &followparent_recalc, }; -static struct clk usb_host_hs_utmi_p3_clk = { - .name = "usb_host_hs_utmi_p3_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_hsic60m_p1_clk = { - .name = "usb_host_hs_hsic60m_p1_clk", +static struct clk usb_otg_ick = { + .name = "usb_otg_ick", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_hsic60m_p2_clk = { - .name = "usb_host_hs_hsic60m_p2_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static const struct clksel utmi_p1_gfclk_sel[] = { - { .parent = &init_60m_fclk, .rates = div_1_0_rates }, - { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk utmi_p1_gfclk = { - .name = "utmi_p1_gfclk", - .parent = &init_60m_fclk, - .clksel = utmi_p1_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk usb_host_hs_utmi_p1_clk = { - .name = "usb_host_hs_utmi_p1_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, + .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_init_clkdm", - .parent = &utmi_p1_gfclk, + .parent = &l3_div_ck, .recalc = &followparent_recalc, }; -static const struct clksel utmi_p2_gfclk_sel[] = { - { .parent = &init_60m_fclk, .rates = div_1_0_rates }, - { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk utmi_p2_gfclk = { - .name = "utmi_p2_gfclk", - .parent = &init_60m_fclk, - .clksel = utmi_p2_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk usb_host_hs_utmi_p2_clk = { - .name = "usb_host_hs_utmi_p2_clk", +static struct clk usb_tll_ick = { + .name = "usb_tll_ick", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, + .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_init_clkdm", - .parent = &utmi_p2_gfclk, + .parent = &l4_div_ck, .recalc = &followparent_recalc, }; -static struct clk usb_host_hs_hsic480m_p1_clk = { - .name = "usb_host_hs_hsic480m_p1_clk", +static struct clk usbphyocp2scp_ick = { + .name = "usbphyocp2scp_ick", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, + .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_init_clkdm", - .parent = &dpll_usb_m2_ck, + .parent = &l4_div_ck, .recalc = &followparent_recalc, }; -static struct clk usb_host_hs_hsic480m_p2_clk = { - .name = "usb_host_hs_hsic480m_p2_clk", +static struct clk usim_fck = { + .name = "usim_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &dpll_usb_m2_ck, + .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_wkup_clkdm", + .parent = &sys_32k_ck, .recalc = &followparent_recalc, }; -static struct clk usb_host_hs_func48mclk = { - .name = "usb_host_hs_func48mclk", +static struct clk wdt2_fck = { + .name = "wdt2_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &func_48mc_fclk, + .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_wkup_clkdm", + .parent = &sys_32k_ck, .recalc = &followparent_recalc, }; -static struct clk usb_host_hs_fck = { - .name = "usb_host_hs_fck", +static struct clk wdt3_fck = { + .name = "wdt3_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, + .clkdm_name = "abe_clkdm", + .parent = &sys_32k_ck, .recalc = &followparent_recalc, }; +/* Remaining optional clocks */ static const struct clksel otg_60m_gfclk_sel[] = { { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates }, { .parent = &xclk60motg_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; -static struct clk otg_60m_gfclk = { - .name = "otg_60m_gfclk", +static struct clk otg_60m_gfclk_ck = { + .name = "otg_60m_gfclk_ck", .parent = &utmi_phy_clkout_ck, .clksel = otg_60m_gfclk_sel, .init = &omap2_init_clksel_parent, @@ -2579,74 +2373,38 @@ static struct clk otg_60m_gfclk = { .recalc = &omap2_clksel_recalc, }; -static struct clk usb_otg_hs_xclk = { - .name = "usb_otg_hs_xclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &otg_60m_gfclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_otg_hs_ick = { - .name = "usb_otg_hs_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usb_phy_cm_clk32k = { - .name = "usb_phy_cm_clk32k", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT, - .clkdm_name = "l4_ao_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usb_tll_hs_usb_ch2_clk = { - .name = "usb_tll_hs_usb_ch2_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, +static const struct clksel stm_clk_div_div[] = { + { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, + { .parent = NULL }, }; -static struct clk usb_tll_hs_usb_ch0_clk = { - .name = "usb_tll_hs_usb_ch0_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, +static struct clk stm_clk_div_ck = { + .name = "stm_clk_div_ck", + .parent = &pmd_stm_clock_mux_ck, + .clksel = stm_clk_div_div, + .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, }; -static struct clk usb_tll_hs_usb_ch1_clk = { - .name = "usb_tll_hs_usb_ch1_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, +static const struct clksel trace_clk_div_div[] = { + { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, + { .parent = NULL }, }; -static struct clk usb_tll_hs_ick = { - .name = "usb_tll_hs_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, +static struct clk trace_clk_div_ck = { + .name = "trace_clk_div_ck", + .parent = &pmd_trace_clk_mux_ck, + .clksel = trace_clk_div_div, + .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, }; static const struct clksel_rate div2_14to18_rates[] = { @@ -2660,8 +2418,8 @@ static const struct clksel usim_fclk_div[] = { { .parent = NULL }, }; -static struct clk usim_ck = { - .name = "usim_ck", +static struct clk usim_fclk = { + .name = "usim_fclk", .parent = &dpll_per_m4_ck, .clksel = usim_fclk_div, .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, @@ -2672,79 +2430,38 @@ static struct clk usim_ck = { .set_rate = &omap2_clksel_set_rate, }; -static struct clk usim_fclk = { - .name = "usim_fclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT, - .clkdm_name = "l4_wkup_clkdm", - .parent = &usim_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usim_fck = { - .name = "usim_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk wd_timer2_fck = { - .name = "wd_timer2_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk wd_timer3_fck = { - .name = "wd_timer3_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -/* Remaining optional clocks */ -static const struct clksel stm_clk_div_div[] = { - { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, +static const struct clksel utmi_p1_gfclk_sel[] = { + { .parent = &init_60m_fclk, .rates = div_1_0_rates }, + { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; -static struct clk stm_clk_div_ck = { - .name = "stm_clk_div_ck", - .parent = &pmd_stm_clock_mux_ck, - .clksel = stm_clk_div_div, - .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK, +static struct clk utmi_p1_gfclk_ck = { + .name = "utmi_p1_gfclk_ck", + .parent = &init_60m_fclk, + .clksel = utmi_p1_gfclk_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, .ops = &clkops_null, .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, }; -static const struct clksel trace_clk_div_div[] = { - { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, +static const struct clksel utmi_p2_gfclk_sel[] = { + { .parent = &init_60m_fclk, .rates = div_1_0_rates }, + { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; -static struct clk trace_clk_div_ck = { - .name = "trace_clk_div_ck", - .parent = &pmd_trace_clk_mux_ck, - .clksel = trace_clk_div_div, - .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, +static struct clk utmi_p2_gfclk_ck = { + .name = "utmi_p2_gfclk_ck", + .parent = &init_60m_fclk, + .clksel = utmi_p2_gfclk_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, .ops = &clkops_null, .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, }; /* @@ -2766,12 +2483,11 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), - CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), - CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), + CLK(NULL, "dpll_sys_ref_clk", &dpll_sys_ref_clk, CK_443X), CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), @@ -2841,48 +2557,46 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), CLK(NULL, "aess_fck", &aess_fck, CK_443X), - CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), + CLK(NULL, "cust_efuse_fck", &cust_efuse_fck, CK_443X), CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), - CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), - CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), - CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), - CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), - CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), CLK(NULL, "dss_fck", &dss_fck, CK_443X), - CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), - CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), - CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), + CLK(NULL, "ducati_ick", &ducati_ick, CK_443X), + CLK(NULL, "emif1_ick", &emif1_ick, CK_443X), + CLK(NULL, "emif2_ick", &emif2_ick, CK_443X), CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), - CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), - CLK(NULL, "gpio1_dbck", &gpio1_dbclk, CK_443X), + CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X), + CLK(NULL, "gfx_fck", &gfx_fck, CK_443X), CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), - CLK(NULL, "gpio2_dbck", &gpio2_dbclk, CK_443X), CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), - CLK(NULL, "gpio3_dbck", &gpio3_dbclk, CK_443X), CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), - CLK(NULL, "gpio4_dbck", &gpio4_dbclk, CK_443X), CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), - CLK(NULL, "gpio5_dbck", &gpio5_dbclk, CK_443X), CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), - CLK(NULL, "gpio6_dbck", &gpio6_dbclk, CK_443X), CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), - CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_443X), + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_443X), + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_443X), + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_443X), + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_443X), + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_443X), + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_443X), + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_443X), + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_443X), + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_443X), + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_443X), CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), - CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), + CLK(NULL, "hsi_ick", &hsi_ick, CK_443X), CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X), CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X), CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X), CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X), - CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), - CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), CLK(NULL, "iss_fck", &iss_fck, CK_443X), - CLK(NULL, "iva_fck", &iva_fck, CK_443X), - CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), - CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), - CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), + CLK(NULL, "ivahd_ick", &ivahd_ick, CK_443X), + CLK(NULL, "keyboard_fck", &keyboard_fck, CK_443X), + CLK(NULL, "l3_instr_interconnect_ick", &l3_instr_interconnect_ick, CK_443X), + CLK(NULL, "l3_interconnect_3_ick", &l3_interconnect_3_ick, CK_443X), CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), @@ -2893,7 +2607,6 @@ static struct omap_clk omap44xx_clks[] = { CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), - CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), @@ -2903,66 +2616,43 @@ static struct omap_clk omap44xx_clks[] = { CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), - CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), - CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), - CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), + CLK(NULL, "ocp_wp1_ick", &ocp_wp1_ick, CK_443X), + CLK(NULL, "pdm_fck", &pdm_fck, CK_443X), + CLK(NULL, "pkaeip29_fck", &pkaeip29_fck, CK_443X), CLK("omap_rng", "ick", &rng_ick, CK_443X), - CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), - CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), - CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), - CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), - CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), - CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), + CLK(NULL, "sha2md51_fck", &sha2md51_fck, CK_443X), + CLK(NULL, "sl2_ick", &sl2_ick, CK_443X), CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), - CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), - CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), - CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), - CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), - CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), - CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), - CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X), - CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X), - CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X), - CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X), - CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X), - CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X), - CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X), - CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X), - CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X), - CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X), - CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X), + CLK(NULL, "sr_core_fck", &sr_core_fck, CK_443X), + CLK(NULL, "sr_iva_fck", &sr_iva_fck, CK_443X), + CLK(NULL, "sr_mpu_fck", &sr_mpu_fck, CK_443X), + CLK(NULL, "tesla_ick", &tesla_ick, CK_443X), CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), + CLK(NULL, "unipro1_fck", &unipro1_fck, CK_443X), + CLK(NULL, "usb_host_fck", &usb_host_fck, CK_443X), CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), - CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), - CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), - CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), - CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), - CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), - CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), - CLK("musb_hdrc", "ick", &usb_otg_hs_ick, CK_443X), - CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), - CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), - CLK(NULL, "usim_ck", &usim_ck, CK_443X), - CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), + CLK("musb_hdrc", "ick", &usb_otg_ick, CK_443X), + CLK(NULL, "usb_tll_ick", &usb_tll_ick, CK_443X), + CLK(NULL, "usbphyocp2scp_ick", &usbphyocp2scp_ick, CK_443X), CLK(NULL, "usim_fck", &usim_fck, CK_443X), - CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), - CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), + CLK("omap_wdt", "fck", &wdt2_fck, CK_443X), + CLK(NULL, "wdt3_fck", &wdt3_fck, CK_443X), + CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X), CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), + CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), + CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X), + CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X), + CLK(NULL, "gpio1_dbck", &dummy_ck, CK_443X), + CLK(NULL, "gpio2_dbck", &dummy_ck, CK_443X), + CLK(NULL, "gpio3_dbck", &dummy_ck, CK_443X), + CLK(NULL, "gpio4_dbck", &dummy_ck, CK_443X), + CLK(NULL, "gpio5_dbck", &dummy_ck, CK_443X), + CLK(NULL, "gpio6_dbck", &dummy_ck, CK_443X), CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), @@ -2979,19 +2669,19 @@ static struct omap_clk omap44xx_clks[] = { CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X), CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X), CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X), CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), diff --git a/trunk/arch/arm/mach-omap2/clockdomain.c b/trunk/arch/arm/mach-omap2/clockdomain.c index 6fb61b1a0d46..5d80cb897489 100644 --- a/trunk/arch/arm/mach-omap2/clockdomain.c +++ b/trunk/arch/arm/mach-omap2/clockdomain.c @@ -258,6 +258,97 @@ static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable) } +/** + * _init_wkdep_usecount - initialize wkdep usecounts to match hardware + * @clkdm: clockdomain to initialize wkdep usecounts + * + * Initialize the wakeup dependency usecount variables for clockdomain @clkdm. + * If a wakeup dependency is present in the hardware, the usecount will be + * set to 1; otherwise, it will be set to 0. Software should clear all + * software wakeup dependencies prior to calling this function if it wishes + * to ensure that all usecounts start at 0. No return value. + */ +static void _init_wkdep_usecount(struct clockdomain *clkdm) +{ + u32 v; + struct clkdm_dep *cd; + + if (!clkdm->wkdep_srcs) + return; + + for (cd = clkdm->wkdep_srcs; cd->clkdm_name; cd++) { + if (!omap_chip_is(cd->omap_chip)) + continue; + + if (!cd->clkdm && cd->clkdm_name) + cd->clkdm = _clkdm_lookup(cd->clkdm_name); + + if (!cd->clkdm) { + WARN(!cd->clkdm, "clockdomain: %s: wkdep clkdm %s not " + "found\n", clkdm->name, cd->clkdm_name); + continue; + } + + v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs, + PM_WKDEP, + (1 << cd->clkdm->dep_bit)); + + if (v) + pr_debug("clockdomain: %s: wakeup dependency already " + "set to wake up when %s wakes\n", + clkdm->name, cd->clkdm->name); + + atomic_set(&cd->wkdep_usecount, (v) ? 1 : 0); + } +} + +/** + * _init_sleepdep_usecount - initialize sleepdep usecounts to match hardware + * @clkdm: clockdomain to initialize sleepdep usecounts + * + * Initialize the sleep dependency usecount variables for clockdomain @clkdm. + * If a sleep dependency is present in the hardware, the usecount will be + * set to 1; otherwise, it will be set to 0. Software should clear all + * software sleep dependencies prior to calling this function if it wishes + * to ensure that all usecounts start at 0. No return value. + */ +static void _init_sleepdep_usecount(struct clockdomain *clkdm) +{ + u32 v; + struct clkdm_dep *cd; + + if (!cpu_is_omap34xx()) + return; + + if (!clkdm->sleepdep_srcs) + return; + + for (cd = clkdm->sleepdep_srcs; cd->clkdm_name; cd++) { + if (!omap_chip_is(cd->omap_chip)) + continue; + + if (!cd->clkdm && cd->clkdm_name) + cd->clkdm = _clkdm_lookup(cd->clkdm_name); + + if (!cd->clkdm) { + WARN(!cd->clkdm, "clockdomain: %s: sleepdep clkdm %s " + "not found\n", clkdm->name, cd->clkdm_name); + continue; + } + + v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs, + OMAP3430_CM_SLEEPDEP, + (1 << cd->clkdm->dep_bit)); + + if (v) + pr_debug("clockdomain: %s: sleep dependency already " + "set to prevent from idling until %s " + "idles\n", clkdm->name, cd->clkdm->name); + + atomic_set(&cd->sleepdep_usecount, (v) ? 1 : 0); + } +}; + /* Public functions */ /** @@ -288,17 +379,12 @@ void clkdm_init(struct clockdomain **clkdms, _autodep_lookup(autodep); /* - * Put all clockdomains into software-supervised mode; PM code - * should later enable hardware-supervised mode as appropriate + * Ensure that the *dep_usecount registers reflect the current + * state of the PRCM. */ list_for_each_entry(clkdm, &clkdm_list, node) { - if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) - omap2_clkdm_wakeup(clkdm); - else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO) - omap2_clkdm_deny_idle(clkdm); - - clkdm_clear_all_wkdeps(clkdm); - clkdm_clear_all_sleepdeps(clkdm); + _init_wkdep_usecount(clkdm); + _init_sleepdep_usecount(clkdm); } } @@ -506,9 +592,6 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) if (!omap_chip_is(cd->omap_chip)) continue; - if (!cd->clkdm && cd->clkdm_name) - cd->clkdm = _clkdm_lookup(cd->clkdm_name); - /* PRM accesses are slow, so minimize them */ mask |= 1 << cd->clkdm->dep_bit; atomic_set(&cd->wkdep_usecount, 0); @@ -669,9 +752,6 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) if (!omap_chip_is(cd->omap_chip)) continue; - if (!cd->clkdm && cd->clkdm_name) - cd->clkdm = _clkdm_lookup(cd->clkdm_name); - /* PRM accesses are slow, so minimize them */ mask |= 1 << cd->clkdm->dep_bit; atomic_set(&cd->sleepdep_usecount, 0); diff --git a/trunk/arch/arm/mach-omap2/cm-regbits-34xx.h b/trunk/arch/arm/mach-omap2/cm-regbits-34xx.h index 4f959a7d881c..fe82b79d5f3b 100644 --- a/trunk/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/trunk/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -649,8 +649,6 @@ #define OMAP3430_ST_MCBSP2_MASK (1 << 0) /* CM_AUTOIDLE_PER */ -#define OMAP3630_AUTO_UART4_MASK (1 << 18) -#define OMAP3630_AUTO_UART4_SHIFT 18 #define OMAP3430_AUTO_GPIO6_MASK (1 << 17) #define OMAP3430_AUTO_GPIO6_SHIFT 17 #define OMAP3430_AUTO_GPIO5_MASK (1 << 16) diff --git a/trunk/arch/arm/mach-omap2/cm-regbits-44xx.h b/trunk/arch/arm/mach-omap2/cm-regbits-44xx.h index 0b72be433776..ac8458e43252 100644 --- a/trunk/arch/arm/mach-omap2/cm-regbits-44xx.h +++ b/trunk/arch/arm/mach-omap2/cm-regbits-44xx.h @@ -1,8 +1,8 @@ /* * OMAP44xx Clock Management register bits * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * Copyright (C) 2009-2010 Nokia Corporation + * Copyright (C) 2009 Texas Instruments, Inc. + * Copyright (C) 2009 Nokia Corporation * * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) @@ -25,459 +25,453 @@ #include "cm.h" -/* - * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, - * CM_TESLA_DYNAMICDEP - */ +/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_ABE_DYNDEP_SHIFT 3 -#define OMAP4430_ABE_DYNDEP_MASK (1 << 3) +#define OMAP4430_ABE_DYNDEP_MASK BITFIELD(3, 3) /* - * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, - * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, + * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, + * CM_TESLA_STATICDEP */ #define OMAP4430_ABE_STATDEP_SHIFT 3 -#define OMAP4430_ABE_STATDEP_MASK (1 << 3) +#define OMAP4430_ABE_STATDEP_MASK BITFIELD(3, 3) -/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ +/* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 -#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) +#define OMAP4430_ALWONCORE_DYNDEP_MASK BITFIELD(16, 16) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 -#define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16) +#define OMAP4430_ALWONCORE_STATDEP_MASK BITFIELD(16, 16) /* - * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, - * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY, - * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, - * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB + * Used by CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB, + * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, + * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU */ #define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 -#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) +#define OMAP4430_AUTO_DPLL_MODE_MASK BITFIELD(0, 2) -/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ +/* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 -#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) +#define OMAP4430_CEFUSE_DYNDEP_MASK BITFIELD(17, 17) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_CEFUSE_STATDEP_SHIFT 17 -#define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17) +#define OMAP4430_CEFUSE_STATDEP_MASK BITFIELD(17, 17) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) +#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK BITFIELD(13, 13) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12) +#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK BITFIELD(12, 12) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK BITFIELD(9, 9) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11) +#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK BITFIELD(11, 11) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK BITFIELD(8, 8) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) +#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK BITFIELD(11, 11) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) +#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK BITFIELD(12, 12) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) +#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK BITFIELD(13, 13) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9) - -/* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12) +#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK BITFIELD(9, 9) /* Used by CM_EMU_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK BITFIELD(9, 9) /* Used by CM_CEFUSE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK BITFIELD(9, 9) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK BITFIELD(9, 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK BITFIELD(9, 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) +#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK BITFIELD(10, 10) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) +#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK BITFIELD(11, 11) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) +#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK BITFIELD(12, 12) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) +#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK BITFIELD(13, 13) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 -#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) +#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK BITFIELD(14, 14) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10) +#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK BITFIELD(10, 10) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK BITFIELD(9, 9) /* Used by CM_DUCATI_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK BITFIELD(8, 8) + +/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ +#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK BITFIELD(10, 10) /* Used by CM_EMU_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK BITFIELD(8, 8) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) +#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK BITFIELD(10, 10) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 -#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) +#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK BITFIELD(15, 15) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) +#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK BITFIELD(10, 10) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) +#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK BITFIELD(11, 11) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 -#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) +#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK BITFIELD(20, 20) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 -#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) +#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK BITFIELD(26, 26) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 -#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) +#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK BITFIELD(21, 21) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 -#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) +#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK BITFIELD(27, 27) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT 31 +#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK BITFIELD(31, 31) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) +#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK BITFIELD(13, 13) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) +#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK BITFIELD(12, 12) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 -#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) +#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK BITFIELD(28, 28) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 -#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) +#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK BITFIELD(29, 29) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) +#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK BITFIELD(11, 11) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 -#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) +#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK BITFIELD(16, 16) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK BITFIELD(17, 17) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK BITFIELD(18, 18) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK BITFIELD(19, 19) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK BITFIELD(8, 8) /* Used by CM_IVAHD_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK BITFIELD(8, 8) -/* Used by CM_D2D_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) +/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ +#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT 14 +#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK BITFIELD(14, 14) /* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK BITFIELD(8, 8) /* Used by CM_D2D_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK BITFIELD(8, 8) /* Used by CM_SDMA_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK BITFIELD(8, 8) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK BITFIELD(8, 8) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK BITFIELD(8, 8) /* Used by CM_GFX_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L3INSTR_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L4SEC_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK BITFIELD(8, 8) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK BITFIELD(8, 8) /* Used by CM_CEFUSE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK BITFIELD(8, 8) /* Used by CM_D2D_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK BITFIELD(9, 9) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK BITFIELD(9, 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L4SEC_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK BITFIELD(9, 9) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) +#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK BITFIELD(12, 12) /* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK BITFIELD(8, 8) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK BITFIELD(9, 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 -#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) +#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK BITFIELD(16, 16) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 -#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) +#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK BITFIELD(17, 17) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 -#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) +#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK BITFIELD(18, 18) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 -#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) +#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK BITFIELD(19, 19) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 -#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) +#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK BITFIELD(25, 25) + +/* Used by CM_EMU_CLKSTCTRL */ +#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK BITFIELD(10, 10) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 -#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) +#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK BITFIELD(20, 20) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 -#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21) +#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK BITFIELD(21, 21) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 -#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) +#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK BITFIELD(22, 22) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 -#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) +#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK BITFIELD(24, 24) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) +#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK BITFIELD(10, 10) /* Used by CM_GFX_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK BITFIELD(9, 9) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11) +#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK BITFIELD(11, 11) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10) +#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK BITFIELD(10, 10) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9) +#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK BITFIELD(9, 9) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK BITFIELD(8, 8) /* Used by CM_TESLA_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) +#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 -#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) +#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK BITFIELD(22, 22) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 -#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) +#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK BITFIELD(23, 23) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 -#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 -#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) +#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK BITFIELD(24, 24) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 -#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) +#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK BITFIELD(15, 15) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) +#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK BITFIELD(10, 10) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 -#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) +#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK BITFIELD(30, 30) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 -#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) +#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK BITFIELD(25, 25) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) +#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK BITFIELD(11, 11) /* - * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, - * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, - * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, + * Used by CM_WKUP_TIMER1_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, - * CM_WKUP_TIMER1_CLKCTRL + * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, + * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, + * CM1_ABE_TIMER8_CLKCTRL */ #define OMAP4430_CLKSEL_SHIFT 24 -#define OMAP4430_CLKSEL_MASK (1 << 24) +#define OMAP4430_CLKSEL_MASK BITFIELD(24, 24) /* * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, - * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ + * CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, + * CM_CLKSEL_USB_60MHZ */ #define OMAP4430_CLKSEL_0_0_SHIFT 0 -#define OMAP4430_CLKSEL_0_0_MASK (1 << 0) +#define OMAP4430_CLKSEL_0_0_MASK BITFIELD(0, 0) /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ #define OMAP4430_CLKSEL_0_1_SHIFT 0 -#define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0) +#define OMAP4430_CLKSEL_0_1_MASK BITFIELD(0, 1) /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ #define OMAP4430_CLKSEL_24_25_SHIFT 24 -#define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24) +#define OMAP4430_CLKSEL_24_25_MASK BITFIELD(24, 25) /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ #define OMAP4430_CLKSEL_60M_SHIFT 24 -#define OMAP4430_CLKSEL_60M_MASK (1 << 24) +#define OMAP4430_CLKSEL_60M_MASK BITFIELD(24, 24) /* Used by CM1_ABE_AESS_CLKCTRL */ #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) +#define OMAP4430_CLKSEL_AESS_FCLK_MASK BITFIELD(24, 24) -/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ +/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_CORE_SHIFT 0 -#define OMAP4430_CLKSEL_CORE_MASK (1 << 0) +#define OMAP4430_CLKSEL_CORE_MASK BITFIELD(0, 0) -/* - * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE, - * CM_SHADOW_FREQ_CONFIG2 - */ +/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ #define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 -#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) +#define OMAP4430_CLKSEL_CORE_1_1_MASK BITFIELD(1, 1) /* Used by CM_WKUP_USIM_CLKCTRL */ #define OMAP4430_CLKSEL_DIV_SHIFT 24 -#define OMAP4430_CLKSEL_DIV_MASK (1 << 24) +#define OMAP4430_CLKSEL_DIV_MASK BITFIELD(24, 24) /* Used by CM_CAM_FDIF_CLKCTRL */ #define OMAP4430_CLKSEL_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) +#define OMAP4430_CLKSEL_FCLK_MASK BITFIELD(24, 25) /* Used by CM_L4PER_MCBSP4_CLKCTRL */ #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25) +#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK BITFIELD(25, 25) /* * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL, @@ -485,869 +479,836 @@ * CM1_ABE_MCBSP3_CLKCTRL */ #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) +#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK BITFIELD(26, 27) -/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ +/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_L3_SHIFT 4 -#define OMAP4430_CLKSEL_L3_MASK (1 << 4) +#define OMAP4430_CLKSEL_L3_MASK BITFIELD(4, 4) -/* - * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE, - * CM_SHADOW_FREQ_CONFIG2 - */ +/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 -#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) +#define OMAP4430_CLKSEL_L3_SHADOW_MASK BITFIELD(2, 2) -/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ +/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_L4_SHIFT 8 -#define OMAP4430_CLKSEL_L4_MASK (1 << 8) +#define OMAP4430_CLKSEL_L4_MASK BITFIELD(8, 8) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_CLKSEL_OPP_SHIFT 0 -#define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0) +#define OMAP4430_CLKSEL_OPP_MASK BITFIELD(0, 1) + +/* Used by CM_GFX_GFX_CLKCTRL */ +#define OMAP4430_CLKSEL_PER_192M_SHIFT 25 +#define OMAP4430_CLKSEL_PER_192M_MASK BITFIELD(25, 26) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 -#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27) +#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK BITFIELD(27, 29) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 -#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) +#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK BITFIELD(24, 26) /* Used by CM_GFX_GFX_CLKCTRL */ #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) +#define OMAP4430_CLKSEL_SGX_FCLK_MASK BITFIELD(24, 24) /* * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL */ #define OMAP4430_CLKSEL_SOURCE_SHIFT 24 -#define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) +#define OMAP4430_CLKSEL_SOURCE_MASK BITFIELD(24, 25) /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 -#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) +#define OMAP4430_CLKSEL_SOURCE_24_24_MASK BITFIELD(24, 24) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 -#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) +#define OMAP4430_CLKSEL_UTMI_P1_MASK BITFIELD(24, 24) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 -#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) +#define OMAP4430_CLKSEL_UTMI_P2_MASK BITFIELD(25, 25) /* - * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL, - * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL, - * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL, - * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL, - * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL, - * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE, - * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL, - * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL, - * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL, - * CM_WKUP_CLKSTCTRL + * Used by CM_WKUP_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_D2D_CLKSTCTRL, + * CM_DUCATI_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL, + * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, + * CM_SDMA_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL, + * CM_L3INIT_CLKSTCTRL, CM_CAM_CLKSTCTRL, CM_CEFUSE_CLKSTCTRL, + * CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3_1_CLKSTCTRL_RESTORE, + * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL_RESTORE, + * CM_L4PER_CLKSTCTRL_RESTORE, CM_MEMIF_CLKSTCTRL_RESTORE, CM_ALWON_CLKSTCTRL, + * CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL, + * CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKTRCTRL_SHIFT 0 -#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) +#define OMAP4430_CLKTRCTRL_MASK BITFIELD(0, 1) /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 -#define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) +#define OMAP4430_CORE_DPLL_EMU_DIV_MASK BITFIELD(0, 6) /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 -#define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_CUSTOM_SHIFT 6 -#define OMAP4430_CUSTOM_MASK (0x3 << 6) +#define OMAP4430_CORE_DPLL_EMU_MULT_MASK BITFIELD(8, 18) -/* - * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP_RESTORE - */ +/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ #define OMAP4430_D2D_DYNDEP_SHIFT 18 -#define OMAP4430_D2D_DYNDEP_MASK (1 << 18) +#define OMAP4430_D2D_DYNDEP_MASK BITFIELD(18, 18) /* Used by CM_MPU_STATICDEP */ #define OMAP4430_D2D_STATDEP_SHIFT 18 -#define OMAP4430_D2D_STATDEP_MASK (1 << 18) +#define OMAP4430_D2D_STATDEP_MASK BITFIELD(18, 18) /* - * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, - * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY, - * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU, - * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, - * CM_SSC_DELTAMSTEP_DPLL_USB + * Used by CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, + * CM_SSC_DELTAMSTEP_DPLL_USB, CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, + * CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, + * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, + * CM_SSC_DELTAMSTEP_DPLL_MPU */ #define OMAP4430_DELTAMSTEP_SHIFT 0 -#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) +#define OMAP4430_DELTAMSTEP_MASK BITFIELD(0, 19) -/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ +/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_DLL_OVERRIDE_SHIFT 2 -#define OMAP4430_DLL_OVERRIDE_MASK (1 << 2) +#define OMAP4430_DLL_OVERRIDE_MASK BITFIELD(2, 2) /* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */ #define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0 -#define OMAP4430_DLL_OVERRIDE_0_0_MASK (1 << 0) +#define OMAP4430_DLL_OVERRIDE_0_0_MASK BITFIELD(0, 0) -/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ +/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_DLL_RESET_SHIFT 3 -#define OMAP4430_DLL_RESET_MASK (1 << 3) +#define OMAP4430_DLL_RESET_MASK BITFIELD(3, 3) /* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, - * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, - * CM_CLKSEL_DPLL_USB + * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB, + * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, + * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU */ #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 -#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) +#define OMAP4430_DPLL_BYP_CLKSEL_MASK BITFIELD(23, 23) /* Used by CM_CLKDCOLDO_DPLL_USB */ #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) +#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK BITFIELD(8, 8) -/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */ +/* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */ #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 -#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) +#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK BITFIELD(20, 20) /* - * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, - * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER + * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, + * CM_DIV_M3_DPLL_CORE */ #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 -#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) +#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK BITFIELD(0, 4) /* - * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, - * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER + * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, + * CM_DIV_M3_DPLL_CORE */ #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 -#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) +#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK BITFIELD(5, 5) /* - * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, - * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER + * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, + * CM_DIV_M3_DPLL_CORE */ #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) +#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK BITFIELD(8, 8) -/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ +/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 -#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) +#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BITFIELD(10, 10) /* - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, - * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO + * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, + * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, + * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU */ #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 -#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) +#define OMAP4430_DPLL_CLKOUT_DIV_MASK BITFIELD(0, 4) /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 -#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) +#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK BITFIELD(0, 6) /* - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, - * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO + * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, + * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, + * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU */ #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) +#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK BITFIELD(5, 5) /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) +#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK BITFIELD(7, 7) /* - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, - * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB + * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE, + * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, + * CM_DIV_M2_DPLL_MPU */ #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) +#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BITFIELD(8, 8) -/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ +/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 -#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) +#define OMAP4430_DPLL_CORE_DPLL_EN_MASK BITFIELD(8, 10) -/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ +/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 -#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) +#define OMAP4430_DPLL_CORE_M2_DIV_MASK BITFIELD(11, 15) -/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ +/* Used by CM_SHADOW_FREQ_CONFIG2 */ #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 -#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) +#define OMAP4430_DPLL_CORE_M5_DIV_MASK BITFIELD(3, 7) + +/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ +#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT 1 +#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK BITFIELD(1, 1) /* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, - * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO + * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, + * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, + * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU */ #define OMAP4430_DPLL_DIV_SHIFT 0 -#define OMAP4430_DPLL_DIV_MASK (0x7f << 0) +#define OMAP4430_DPLL_DIV_MASK BITFIELD(0, 6) /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_DIV_0_7_SHIFT 0 -#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) +#define OMAP4430_DPLL_DIV_0_7_MASK BITFIELD(0, 7) /* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER + * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK BITFIELD(8, 8) /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 -#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) +#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK BITFIELD(3, 3) /* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, - * CM_CLKMODE_DPLL_USB + * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ #define OMAP4430_DPLL_EN_SHIFT 0 -#define OMAP4430_DPLL_EN_MASK (0x7 << 0) +#define OMAP4430_DPLL_EN_MASK BITFIELD(0, 2) /* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO + * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ #define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 -#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) +#define OMAP4430_DPLL_LPMODE_EN_MASK BITFIELD(10, 10) /* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, - * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO + * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, + * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, + * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU */ #define OMAP4430_DPLL_MULT_SHIFT 8 -#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) +#define OMAP4430_DPLL_MULT_MASK BITFIELD(8, 18) /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_MULT_USB_SHIFT 8 -#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) +#define OMAP4430_DPLL_MULT_USB_MASK BITFIELD(8, 19) /* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO + * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ #define OMAP4430_DPLL_REGM4XEN_SHIFT 11 -#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) +#define OMAP4430_DPLL_REGM4XEN_MASK BITFIELD(11, 11) /* Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_SD_DIV_SHIFT 24 -#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) +#define OMAP4430_DPLL_SD_DIV_MASK BITFIELD(24, 31) /* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, - * CM_CLKMODE_DPLL_USB + * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ #define OMAP4430_DPLL_SSC_ACK_SHIFT 13 -#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) +#define OMAP4430_DPLL_SSC_ACK_MASK BITFIELD(13, 13) /* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, - * CM_CLKMODE_DPLL_USB + * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 -#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) +#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK BITFIELD(14, 14) /* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, - * CM_CLKMODE_DPLL_USB + * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ #define OMAP4430_DPLL_SSC_EN_SHIFT 12 -#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) +#define OMAP4430_DPLL_SSC_EN_MASK BITFIELD(12, 12) -/* - * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE - */ +/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ #define OMAP4430_DSS_DYNDEP_SHIFT 8 -#define OMAP4430_DSS_DYNDEP_MASK (1 << 8) +#define OMAP4430_DSS_DYNDEP_MASK BITFIELD(8, 8) /* - * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE + * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, + * CM_MPU_STATICDEP */ #define OMAP4430_DSS_STATDEP_SHIFT 8 -#define OMAP4430_DSS_STATDEP_MASK (1 << 8) +#define OMAP4430_DSS_STATDEP_MASK BITFIELD(8, 8) -/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ +/* Used by CM_L3_2_DYNAMICDEP */ #define OMAP4430_DUCATI_DYNDEP_SHIFT 0 -#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) +#define OMAP4430_DUCATI_DYNDEP_MASK BITFIELD(0, 0) -/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */ +/* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */ #define OMAP4430_DUCATI_STATDEP_SHIFT 0 -#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) +#define OMAP4430_DUCATI_STATDEP_MASK BITFIELD(0, 0) -/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ +/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_FREQ_UPDATE_SHIFT 0 -#define OMAP4430_FREQ_UPDATE_MASK (1 << 0) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_FUNC_SHIFT 16 -#define OMAP4430_FUNC_MASK (0xfff << 16) +#define OMAP4430_FREQ_UPDATE_MASK BITFIELD(0, 0) -/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ +/* Used by CM_L3_2_DYNAMICDEP */ #define OMAP4430_GFX_DYNDEP_SHIFT 10 -#define OMAP4430_GFX_DYNDEP_MASK (1 << 10) +#define OMAP4430_GFX_DYNDEP_MASK BITFIELD(10, 10) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_GFX_STATDEP_SHIFT 10 -#define OMAP4430_GFX_STATDEP_MASK (1 << 10) +#define OMAP4430_GFX_STATDEP_MASK BITFIELD(10, 10) -/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ +/* Used by CM_SHADOW_FREQ_CONFIG2 */ #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 -#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) +#define OMAP4430_GPMC_FREQ_UPDATE_MASK BITFIELD(0, 0) /* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER + * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA */ #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) +#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK BITFIELD(0, 4) /* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER + * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA */ #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK BITFIELD(5, 5) /* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER + * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA */ #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK BITFIELD(8, 8) /* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER + * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA */ #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) +#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK BITFIELD(12, 12) /* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER + * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA */ #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) +#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK BITFIELD(0, 4) /* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER + * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA */ #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK BITFIELD(5, 5) /* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER + * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA */ #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK BITFIELD(8, 8) /* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER + * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA */ #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) +#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK BITFIELD(12, 12) /* - * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER + * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY */ #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) +#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK BITFIELD(0, 4) /* - * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER + * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY */ #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK BITFIELD(5, 5) /* - * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER + * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY */ #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK BITFIELD(8, 8) /* - * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER + * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY */ #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) +#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK BITFIELD(12, 12) /* - * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_PER + * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_CORE */ #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) +#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK BITFIELD(0, 4) /* - * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_PER + * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_CORE */ #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK BITFIELD(5, 5) /* - * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_PER + * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_CORE */ #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK BITFIELD(8, 8) /* - * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_PER + * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_CORE */ #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) - -/* - * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, - * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, - * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, - * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, - * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, - * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, - * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, - * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, - * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE, - * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, - * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, - * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, - * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, +#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK BITFIELD(12, 12) + +/* + * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, + * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, + * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, + * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, + * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, + * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, + * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, + * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, + * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, + * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, + * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, + * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, + * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, + * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, + * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, + * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, + * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, + * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, + * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, + * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, + * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, + * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, + * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, + * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, + * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, + * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, + * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, + * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, + * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, + * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, - * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, - * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, - * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE, - * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, - * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, - * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, - * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, - * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, - * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, - * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, - * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, - * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, - * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, - * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, - * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, - * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, - * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, - * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, - * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, - * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, - * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, - * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, - * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, - * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, - * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, - * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, - * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, - * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, - * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, - * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL + * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, + * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, + * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, + * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, + * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, + * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE, + * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, + * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE, + * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, + * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL, + * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, + * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL, + * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, + * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL, + * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL, + * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, + * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL */ #define OMAP4430_IDLEST_SHIFT 16 -#define OMAP4430_IDLEST_MASK (0x3 << 16) +#define OMAP4430_IDLEST_MASK BITFIELD(16, 17) -/* - * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, - * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE - */ +/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ #define OMAP4430_ISS_DYNDEP_SHIFT 9 -#define OMAP4430_ISS_DYNDEP_MASK (1 << 9) +#define OMAP4430_ISS_DYNDEP_MASK BITFIELD(9, 9) /* - * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, + * CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_ISS_STATDEP_SHIFT 9 -#define OMAP4430_ISS_STATDEP_MASK (1 << 9) +#define OMAP4430_ISS_STATDEP_MASK BITFIELD(9, 9) -/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */ +/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_IVAHD_DYNDEP_SHIFT 2 -#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) +#define OMAP4430_IVAHD_DYNDEP_MASK BITFIELD(2, 2) /* - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, - * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, - * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, + * CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP, + * CM_TESLA_STATICDEP */ #define OMAP4430_IVAHD_STATDEP_SHIFT 2 -#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) +#define OMAP4430_IVAHD_STATDEP_MASK BITFIELD(2, 2) -/* - * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE - */ +/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ #define OMAP4430_L3INIT_DYNDEP_SHIFT 7 -#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) +#define OMAP4430_L3INIT_DYNDEP_MASK BITFIELD(7, 7) /* - * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, - * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, - * CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L3INIT_STATDEP_SHIFT 7 -#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) +#define OMAP4430_L3INIT_STATDEP_MASK BITFIELD(7, 7) /* - * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP, - * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP + * Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, + * CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_L3_1_DYNDEP_SHIFT 5 -#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) +#define OMAP4430_L3_1_DYNDEP_MASK BITFIELD(5, 5) /* - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, - * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, - * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, + * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, + * CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L3_1_STATDEP_SHIFT 5 -#define OMAP4430_L3_1_STATDEP_MASK (1 << 5) +#define OMAP4430_L3_1_STATDEP_MASK BITFIELD(5, 5) /* - * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, - * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, - * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, - * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP + * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, + * CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_SDMA_DYNAMICDEP, + * CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, + * CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP */ #define OMAP4430_L3_2_DYNDEP_SHIFT 6 -#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) +#define OMAP4430_L3_2_DYNDEP_MASK BITFIELD(6, 6) /* - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, - * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, - * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, + * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, + * CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L3_2_STATDEP_SHIFT 6 -#define OMAP4430_L3_2_STATDEP_MASK (1 << 6) +#define OMAP4430_L3_2_STATDEP_MASK BITFIELD(6, 6) -/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */ +/* Used by CM_L3_1_DYNAMICDEP */ #define OMAP4430_L4CFG_DYNDEP_SHIFT 12 -#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) +#define OMAP4430_L4CFG_DYNDEP_MASK BITFIELD(12, 12) /* - * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, - * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, + * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, + * CM_TESLA_STATICDEP */ #define OMAP4430_L4CFG_STATDEP_SHIFT 12 -#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) +#define OMAP4430_L4CFG_STATDEP_MASK BITFIELD(12, 12) -/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ +/* Used by CM_L3_2_DYNAMICDEP */ #define OMAP4430_L4PER_DYNDEP_SHIFT 13 -#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) +#define OMAP4430_L4PER_DYNDEP_MASK BITFIELD(13, 13) /* - * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, - * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, + * CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, + * CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L4PER_STATDEP_SHIFT 13 -#define OMAP4430_L4PER_STATDEP_MASK (1 << 13) +#define OMAP4430_L4PER_STATDEP_MASK BITFIELD(13, 13) -/* - * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, - * CM_L4PER_DYNAMICDEP_RESTORE - */ +/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ #define OMAP4430_L4SEC_DYNDEP_SHIFT 14 -#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) +#define OMAP4430_L4SEC_DYNDEP_MASK BITFIELD(14, 14) /* - * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE + * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */ #define OMAP4430_L4SEC_STATDEP_SHIFT 14 -#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) +#define OMAP4430_L4SEC_STATDEP_MASK BITFIELD(14, 14) -/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ +/* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 -#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) +#define OMAP4430_L4WKUP_DYNDEP_MASK BITFIELD(15, 15) /* - * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 -#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) +#define OMAP4430_L4WKUP_STATDEP_MASK BITFIELD(15, 15) /* - * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP, - * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP + * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, + * CM_MPU_DYNAMICDEP */ #define OMAP4430_MEMIF_DYNDEP_SHIFT 4 -#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) +#define OMAP4430_MEMIF_DYNDEP_MASK BITFIELD(4, 4) /* - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, - * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, - * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, + * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, + * CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_MEMIF_STATDEP_SHIFT 4 -#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) +#define OMAP4430_MEMIF_STATDEP_MASK BITFIELD(4, 4) /* - * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, - * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, - * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, - * CM_SSC_MODFREQDIV_DPLL_USB + * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, + * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, + * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, + * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, + * CM_SSC_MODFREQDIV_DPLL_MPU */ #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 -#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) +#define OMAP4430_MODFREQDIV_EXPONENT_MASK BITFIELD(8, 10) /* - * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, - * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, - * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, - * CM_SSC_MODFREQDIV_DPLL_USB + * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, + * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, + * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, + * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, + * CM_SSC_MODFREQDIV_DPLL_MPU */ #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 -#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) - -/* - * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, - * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, - * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, - * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, - * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, - * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, - * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, - * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, - * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE, - * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, - * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, - * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, - * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, +#define OMAP4430_MODFREQDIV_MANTISSA_MASK BITFIELD(0, 6) + +/* + * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, + * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, + * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, + * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, + * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, + * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, + * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, + * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, + * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, + * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, + * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, + * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, + * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, + * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, + * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, + * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, + * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, + * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, + * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, + * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, + * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, + * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, + * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, + * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, + * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, + * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, + * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, + * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, + * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, + * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, - * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, - * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, - * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE, - * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, - * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, - * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, - * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, - * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, - * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, - * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, - * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, - * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, - * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, - * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, - * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, - * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, - * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, - * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, - * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, - * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, - * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, - * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, - * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, - * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, - * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, - * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, - * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, - * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, - * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, - * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL + * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, + * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, + * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, + * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, + * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, + * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE, + * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, + * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE, + * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, + * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL, + * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, + * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL, + * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, + * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL, + * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL, + * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, + * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL */ #define OMAP4430_MODULEMODE_SHIFT 0 -#define OMAP4430_MODULEMODE_MASK (0x3 << 0) +#define OMAP4430_MODULEMODE_MASK BITFIELD(0, 1) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) +#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK BITFIELD(9, 9) /* Used by CM_WKUP_BANDGAP_CLKCTRL */ #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 -#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK BITFIELD(8, 8) -/* Used by CM_ALWON_USBPHY_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 -#define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8) +/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ +#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 9 +#define OMAP4430_OPTFCLKEN_CLK32K_MASK BITFIELD(9, 9) /* Used by CM_CAM_ISS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK BITFIELD(8, 8) /* - * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, - * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, - * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL + * Used by CM_WKUP_GPIO1_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, + * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, + * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, + * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, + * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_DBCLK_MASK BITFIELD(8, 8) /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK BITFIELD(8, 8) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8) - -/* Used by CM_WKUP_USIM_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_DSSCLK_MASK BITFIELD(8, 8) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 -#define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_FCLK0_MASK BITFIELD(8, 8) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 -#define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9) +#define OMAP4430_OPTFCLKEN_FCLK1_MASK BITFIELD(9, 9) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 -#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) +#define OMAP4430_OPTFCLKEN_FCLK2_MASK BITFIELD(10, 10) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 -#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) +#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK BITFIELD(15, 15) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 -#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) +#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK BITFIELD(13, 13) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 -#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) +#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK BITFIELD(14, 14) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 -#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) +#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK BITFIELD(11, 11) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 -#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) +#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK BITFIELD(12, 12) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK BITFIELD(8, 8) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9) +#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK BITFIELD(9, 9) /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 -#define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_PHY_48M_MASK BITFIELD(8, 8) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10) +#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK BITFIELD(10, 10) /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11) +#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK BITFIELD(11, 11) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) +#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK BITFIELD(10, 10) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 -#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) +#define OMAP4430_OPTFCLKEN_TV_CLK_MASK BITFIELD(11, 11) /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) +#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK BITFIELD(9, 9) /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) +#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK BITFIELD(10, 10) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) +#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK BITFIELD(9, 9) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) +#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK BITFIELD(10, 10) /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8) +#define OMAP4430_OPTFCLKEN_XCLK_MASK BITFIELD(8, 8) -/* Used by CM_EMU_OVERRIDE_DPLL_CORE */ +/* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 -#define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19) +#define OMAP4430_OVERRIDE_ENABLE_MASK BITFIELD(19, 19) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 -#define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8) +#define OMAP4430_PAD_CLKS_GATE_MASK BITFIELD(8, 8) /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ #define OMAP4430_PERF_CURRENT_SHIFT 0 -#define OMAP4430_PERF_CURRENT_MASK (0xff << 0) +#define OMAP4430_PERF_CURRENT_MASK BITFIELD(0, 7) /* * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3, @@ -1355,173 +1316,159 @@ * CM_IVA_DVFS_PERF_TESLA */ #define OMAP4430_PERF_REQ_SHIFT 0 -#define OMAP4430_PERF_REQ_MASK (0xff << 0) +#define OMAP4430_PERF_REQ_MASK BITFIELD(0, 7) + +/* Used by CM_EMU_OVERRIDE_DPLL_PER */ +#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT 0 +#define OMAP4430_PER_DPLL_EMU_DIV_MASK BITFIELD(0, 6) + +/* Used by CM_EMU_OVERRIDE_DPLL_PER */ +#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT 8 +#define OMAP4430_PER_DPLL_EMU_MULT_MASK BITFIELD(8, 18) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE1_COMPLETED_SHIFT 0 -#define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0) +#define OMAP4430_PHASE1_COMPLETED_MASK BITFIELD(0, 0) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 -#define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1) +#define OMAP4430_PHASE2A_COMPLETED_MASK BITFIELD(1, 1) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 -#define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2) +#define OMAP4430_PHASE2B_COMPLETED_MASK BITFIELD(2, 2) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 -#define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20) +#define OMAP4430_PMD_STM_MUX_CTRL_MASK BITFIELD(20, 21) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 -#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) +#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK BITFIELD(22, 23) -/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */ +/* Used by CM_DYN_DEP_PRESCAL */ #define OMAP4430_PRESCAL_SHIFT 0 -#define OMAP4430_PRESCAL_MASK (0x3f << 0) +#define OMAP4430_PRESCAL_MASK BITFIELD(0, 5) -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_R_RTL_SHIFT 11 -#define OMAP4430_R_RTL_MASK (0x1f << 11) +/* Used by REVISION_CM2, REVISION_CM1 */ +#define OMAP4430_REV_SHIFT 0 +#define OMAP4430_REV_MASK BITFIELD(0, 7) /* - * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, - * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE + * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, + * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ #define OMAP4430_SAR_MODE_SHIFT 4 -#define OMAP4430_SAR_MODE_MASK (1 << 4) +#define OMAP4430_SAR_MODE_MASK BITFIELD(4, 4) /* Used by CM_SCALE_FCLK */ #define OMAP4430_SCALE_FCLK_SHIFT 0 -#define OMAP4430_SCALE_FCLK_MASK (1 << 0) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_SCHEME_SHIFT 30 -#define OMAP4430_SCHEME_MASK (0x3 << 30) +#define OMAP4430_SCALE_FCLK_MASK BITFIELD(0, 0) -/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ +/* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_SDMA_DYNDEP_SHIFT 11 -#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) +#define OMAP4430_SDMA_DYNDEP_MASK BITFIELD(11, 11) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_SDMA_STATDEP_SHIFT 11 -#define OMAP4430_SDMA_STATDEP_MASK (1 << 11) +#define OMAP4430_SDMA_STATDEP_MASK BITFIELD(11, 11) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 -#define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10) +#define OMAP4430_SLIMBUS_CLK_GATE_MASK BITFIELD(10, 10) /* - * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, - * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, - * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, - * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, + * Used by CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, + * CM_DUCATI_DUCATI_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, + * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, - * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, - * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, - * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL + * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, + * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, + * CM_CAM_ISS_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, + * CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, + * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL */ #define OMAP4430_STBYST_SHIFT 18 -#define OMAP4430_STBYST_MASK (1 << 18) +#define OMAP4430_STBYST_MASK BITFIELD(18, 18) /* - * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, - * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, - * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB + * Used by CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB, + * CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, + * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU */ #define OMAP4430_ST_DPLL_CLK_SHIFT 0 -#define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) +#define OMAP4430_ST_DPLL_CLK_MASK BITFIELD(0, 0) /* Used by CM_CLKDCOLDO_DPLL_USB */ #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) +#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK BITFIELD(9, 9) /* - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, - * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB + * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE, + * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, + * CM_DIV_M2_DPLL_MPU */ #define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) +#define OMAP4430_ST_DPLL_CLKOUT_MASK BITFIELD(9, 9) /* - * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, - * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER + * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, + * CM_DIV_M3_DPLL_CORE */ #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) +#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK BITFIELD(9, 9) -/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ +/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 -#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) +#define OMAP4430_ST_DPLL_CLKOUTX2_MASK BITFIELD(11, 11) /* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER + * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA */ #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK BITFIELD(9, 9) /* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER + * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA */ #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK BITFIELD(9, 9) /* - * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER + * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY */ #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK BITFIELD(9, 9) /* - * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_PER + * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_CORE */ #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) - -/* - * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, - * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, - * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB - */ -#define OMAP4430_ST_MN_BYPASS_SHIFT 8 -#define OMAP4430_ST_MN_BYPASS_MASK (1 << 8) +#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK BITFIELD(9, 9) /* Used by CM_SYS_CLKSEL */ #define OMAP4430_SYS_CLKSEL_SHIFT 0 -#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) +#define OMAP4430_SYS_CLKSEL_MASK BITFIELD(0, 2) -/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ +/* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_TESLA_DYNDEP_SHIFT 1 -#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) +#define OMAP4430_TESLA_DYNDEP_MASK BITFIELD(1, 1) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_TESLA_STATDEP_SHIFT 1 -#define OMAP4430_TESLA_STATDEP_MASK (1 << 1) +#define OMAP4430_TESLA_STATDEP_MASK BITFIELD(1, 1) /* - * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP, - * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, - * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, - * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP + * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, + * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, + * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_WINDOWSIZE_SHIFT 24 -#define OMAP4430_WINDOWSIZE_MASK (0xf << 24) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_X_MAJOR_SHIFT 8 -#define OMAP4430_X_MAJOR_MASK (0x7 << 8) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_Y_MINOR_SHIFT 0 -#define OMAP4430_Y_MINOR_MASK (0x3f << 0) +#define OMAP4430_WINDOWSIZE_MASK BITFIELD(24, 27) #endif diff --git a/trunk/arch/arm/mach-omap2/cm44xx.h b/trunk/arch/arm/mach-omap2/cm44xx.h index 3c35a87cb90c..336d94889e5b 100644 --- a/trunk/arch/arm/mach-omap2/cm44xx.h +++ b/trunk/arch/arm/mach-omap2/cm44xx.h @@ -195,42 +195,6 @@ #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088) -/* CM1.RESTORE_CM1 register offsets */ -#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000 -#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000) -#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004 -#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004) -#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008 -#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008) -#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c -#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c) -#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010 -#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010) -#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014 -#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014) -#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018 -#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018) -#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c -#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024 -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024) -#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028 -#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028) -#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c -#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c) -#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030 -#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030) -#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034 -#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034) -#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038 -#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0038) -#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c -#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x003c) -#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040 -#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0040) - /* CM2 */ /* CM2.OCP_SOCKET_CM2 register offsets */ @@ -288,6 +252,8 @@ #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068) #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c) +#define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET 0x0070 +#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070) #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 #define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080) #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 @@ -330,8 +296,6 @@ #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030) #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038) -#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0040) /* CM2.CORE_CM2 register offsets */ #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 @@ -614,54 +578,4 @@ #define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000) #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020) - -/* CM2.RESTORE_CM2 register offsets */ -#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000 -#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000) -#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004 -#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004) -#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008 -#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008) -#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c -#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c) -#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010 -#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010) -#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014 -#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014) -#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018 -#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018) -#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c -#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c) -#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020 -#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020) -#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024 -#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024) -#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028 -#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028) -#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c -#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c) -#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030 -#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030) -#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034 -#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034) -#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038 -#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038) -#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c -#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c) -#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040 -#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040) -#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044 -#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0044) -#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048 -#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0048) -#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c -#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x004c) -#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050 -#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0050) -#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054 -#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0054) -#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058 -#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0058) -#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c -#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x005c) #endif diff --git a/trunk/arch/arm/mach-omap2/cm4xxx.c b/trunk/arch/arm/mach-omap2/cm4xxx.c index f8a660a1a4a6..b101091e95d6 100644 --- a/trunk/arch/arm/mach-omap2/cm4xxx.c +++ b/trunk/arch/arm/mach-omap2/cm4xxx.c @@ -43,6 +43,7 @@ * using separate functional clock * 0x3 disabled: Module is disabled and cannot be accessed * + * TODO: Need to handle module accessible in idle state */ int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg) { @@ -51,11 +52,9 @@ int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg) if (!clkctrl_reg) return 0; - omap_test_timeout(( - ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) || - (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >> - OMAP4430_IDLEST_SHIFT) == 0x2)), - MAX_MODULE_READY_TIME, i); + omap_test_timeout(((__raw_readl(clkctrl_reg) & + OMAP4430_IDLEST_MASK) == 0), + MAX_MODULE_READY_TIME, i); return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; } diff --git a/trunk/arch/arm/mach-omap2/common.c b/trunk/arch/arm/mach-omap2/common.c deleted file mode 100644 index 778929f7e92d..000000000000 --- a/trunk/arch/arm/mach-omap2/common.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/common.c - * - * Code common to all OMAP2+ machines. - * - * Copyright (C) 2009 Texas Instruments - * Copyright (C) 2010 Nokia Corporation - * Tony Lindgren - * Added OMAP4 support - Santosh Shilimkar - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include "sdrc.h" -#include "control.h" - -/* Global address base setup code */ - -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - -static void __init __omap2_set_globals(struct omap_globals *omap2_globals) -{ - omap2_set_globals_tap(omap2_globals); - omap2_set_globals_sdrc(omap2_globals); - omap2_set_globals_control(omap2_globals); - omap2_set_globals_prcm(omap2_globals); -} - -#endif - -#if defined(CONFIG_ARCH_OMAP2420) - -static struct omap_globals omap242x_globals = { - .class = OMAP242X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(0x48014000), - .sdrc = OMAP2420_SDRC_BASE, - .sms = OMAP2420_SMS_BASE, - .ctrl = OMAP242X_CTRL_BASE, - .prm = OMAP2420_PRM_BASE, - .cm = OMAP2420_CM_BASE, - .uart1_phys = OMAP2_UART1_BASE, - .uart2_phys = OMAP2_UART2_BASE, - .uart3_phys = OMAP2_UART3_BASE, -}; - -void __init omap2_set_globals_242x(void) -{ - __omap2_set_globals(&omap242x_globals); -} -#endif - -#if defined(CONFIG_ARCH_OMAP2430) - -static struct omap_globals omap243x_globals = { - .class = OMAP243X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(0x4900a000), - .sdrc = OMAP243X_SDRC_BASE, - .sms = OMAP243X_SMS_BASE, - .ctrl = OMAP243X_CTRL_BASE, - .prm = OMAP2430_PRM_BASE, - .cm = OMAP2430_CM_BASE, - .uart1_phys = OMAP2_UART1_BASE, - .uart2_phys = OMAP2_UART2_BASE, - .uart3_phys = OMAP2_UART3_BASE, -}; - -void __init omap2_set_globals_243x(void) -{ - __omap2_set_globals(&omap243x_globals); -} -#endif - -#if defined(CONFIG_ARCH_OMAP3) - -static struct omap_globals omap3_globals = { - .class = OMAP343X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(0x4830A000), - .sdrc = OMAP343X_SDRC_BASE, - .sms = OMAP343X_SMS_BASE, - .ctrl = OMAP343X_CTRL_BASE, - .prm = OMAP3430_PRM_BASE, - .cm = OMAP3430_CM_BASE, - .uart1_phys = OMAP3_UART1_BASE, - .uart2_phys = OMAP3_UART2_BASE, - .uart3_phys = OMAP3_UART3_BASE, - .uart4_phys = OMAP3_UART4_BASE, /* Only on 3630 */ -}; - -void __init omap2_set_globals_3xxx(void) -{ - __omap2_set_globals(&omap3_globals); -} - -void __init omap3_map_io(void) -{ - omap2_set_globals_3xxx(); - omap34xx_map_common_io(); -} -#endif - -#if defined(CONFIG_ARCH_OMAP4) -static struct omap_globals omap4_globals = { - .class = OMAP443X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), - .ctrl = OMAP443X_SCM_BASE, - .ctrl_pad = OMAP443X_CTRL_BASE, - .prm = OMAP4430_PRM_BASE, - .cm = OMAP4430_CM_BASE, - .cm2 = OMAP4430_CM2_BASE, - .uart1_phys = OMAP4_UART1_BASE, - .uart2_phys = OMAP4_UART2_BASE, - .uart3_phys = OMAP4_UART3_BASE, - .uart4_phys = OMAP4_UART4_BASE, -}; - -void __init omap2_set_globals_443x(void) -{ - omap2_set_globals_tap(&omap4_globals); - omap2_set_globals_control(&omap4_globals); - omap2_set_globals_prcm(&omap4_globals); -} -#endif - diff --git a/trunk/arch/arm/mach-omap2/control.c b/trunk/arch/arm/mach-omap2/control.c index 1fa3294b6048..a8d20eef2306 100644 --- a/trunk/arch/arm/mach-omap2/control.c +++ b/trunk/arch/arm/mach-omap2/control.c @@ -16,18 +16,15 @@ #include #include +#include #include - #include "cm-regbits-34xx.h" #include "prm-regbits-34xx.h" #include "cm.h" #include "prm.h" #include "sdrc.h" -#include "pm.h" -#include "control.h" static void __iomem *omap2_ctrl_base; -static void __iomem *omap4_ctrl_pad_base; #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) struct omap3_scratchpad { @@ -140,7 +137,6 @@ static struct omap3_control_regs control_context; #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) -#define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) void __init omap2_set_globals_control(struct omap_globals *omap2_globals) { @@ -149,12 +145,6 @@ void __init omap2_set_globals_control(struct omap_globals *omap2_globals) omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K); WARN_ON(!omap2_ctrl_base); } - - /* Static mapping, never released */ - if (omap2_globals->ctrl_pad) { - omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K); - WARN_ON(!omap4_ctrl_pad_base); - } } void __iomem *omap_ctrl_base_get(void) @@ -192,23 +182,6 @@ void omap_ctrl_writel(u32 val, u16 offset) __raw_writel(val, OMAP_CTRL_REGADDR(offset)); } -/* - * On OMAP4 control pad are not addressable from control - * core base. So the common omap_ctrl_read/write APIs breaks - * Hence export separate APIs to manage the omap4 pad control - * registers. This APIs will work only for OMAP4 - */ - -u32 omap4_ctrl_pad_readl(u16 offset) -{ - return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset)); -} - -void omap4_ctrl_pad_writel(u32 val, u16 offset) -{ - __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset)); -} - #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) /* * Clears the scratchpad contents in case of cold boot- @@ -217,7 +190,7 @@ void omap4_ctrl_pad_writel(u32 val, u16 offset) void omap3_clear_scratchpad_contents(void) { u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; - void __iomem *v_addr; + u32 *v_addr; u32 offset = 0; v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & @@ -233,7 +206,7 @@ void omap3_clear_scratchpad_contents(void) /* Populate the scratchpad structure with restore structure */ void omap3_save_scratchpad_contents(void) { - void __iomem *scratchpad_address; + void * __iomem scratchpad_address; u32 arm_context_addr; struct omap3_scratchpad scratchpad_contents; struct omap3_scratchpad_prcm_block prcm_block_contents; diff --git a/trunk/arch/arm/mach-omap2/cpuidle34xx.c b/trunk/arch/arm/mach-omap2/cpuidle34xx.c index 0d50b45d041c..3d3d035db9af 100644 --- a/trunk/arch/arm/mach-omap2/cpuidle34xx.c +++ b/trunk/arch/arm/mach-omap2/cpuidle34xx.c @@ -29,10 +29,10 @@ #include #include #include +#include #include #include "pm.h" -#include "control.h" #ifdef CONFIG_CPU_IDLE @@ -60,8 +60,7 @@ struct omap3_processor_cx { struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; struct omap3_processor_cx current_cx_state; -struct powerdomain *mpu_pd, *core_pd, *per_pd; -struct powerdomain *cam_pd; +struct powerdomain *mpu_pd, *core_pd; /* * The latencies/thresholds for various C states have @@ -234,60 +233,14 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev, struct cpuidle_state *state) { struct cpuidle_state *new_state = next_valid_state(dev, state); - u32 core_next_state, per_next_state = 0, per_saved_state = 0; - u32 cam_state; - struct omap3_processor_cx *cx; - int ret; if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { BUG_ON(!dev->safe_state); new_state = dev->safe_state; - goto select_state; } - cx = cpuidle_get_statedata(state); - core_next_state = cx->core_state; - - /* - * FIXME: we currently manage device-specific idle states - * for PER and CORE in combination with CPU-specific - * idle states. This is wrong, and device-specific - * idle managment needs to be separated out into - * its own code. - */ - - /* - * Prevent idle completely if CAM is active. - * CAM does not have wakeup capability in OMAP3. - */ - cam_state = pwrdm_read_pwrst(cam_pd); - if (cam_state == PWRDM_POWER_ON) { - new_state = dev->safe_state; - goto select_state; - } - - /* - * Prevent PER off if CORE is not in retention or off as this - * would disable PER wakeups completely. - */ - per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd); - if ((per_next_state == PWRDM_POWER_OFF) && - (core_next_state > PWRDM_POWER_RET)) - per_next_state = PWRDM_POWER_RET; - - /* Are we changing PER target state? */ - if (per_next_state != per_saved_state) - pwrdm_set_next_pwrst(per_pd, per_next_state); - -select_state: dev->last_state = new_state; - ret = omap3_enter_idle(dev, new_state); - - /* Restore original PER state if it was modified */ - if (per_next_state != per_saved_state) - pwrdm_set_next_pwrst(per_pd, per_saved_state); - - return ret; + return omap3_enter_idle(dev, new_state); } DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); @@ -375,8 +328,7 @@ void omap_init_power_states(void) cpuidle_params_table[OMAP3_STATE_C2].threshold; omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON; omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; - omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID | - CPUIDLE_FLAG_CHECK_BM; + omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; /* C3 . MPU CSWR + Core inactive */ omap3_power_states[OMAP3_STATE_C3].valid = @@ -474,8 +426,6 @@ int __init omap3_idle_init(void) mpu_pd = pwrdm_lookup("mpu_pwrdm"); core_pd = pwrdm_lookup("core_pwrdm"); - per_pd = pwrdm_lookup("per_pwrdm"); - cam_pd = pwrdm_lookup("cam_pwrdm"); omap_init_power_states(); cpuidle_register_driver(&omap3_idle_driver); diff --git a/trunk/arch/arm/mach-omap2/devices.c b/trunk/arch/arm/mach-omap2/devices.c index 5a0c148e23bc..c5cf1ba08a6f 100644 --- a/trunk/arch/arm/mach-omap2/devices.c +++ b/trunk/arch/arm/mach-omap2/devices.c @@ -9,12 +9,12 @@ * (at your option) any later version. */ +#include #include #include #include #include #include -#include #include #include @@ -22,17 +22,15 @@ #include #include +#include #include #include #include #include #include #include -#include -#include #include "mux.h" -#include "control.h" #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) @@ -540,7 +538,7 @@ static inline void omap_init_sham(void) { } #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE) -#ifdef CONFIG_ARCH_OMAP2 +#ifdef CONFIG_ARCH_OMAP24XX static struct resource omap2_aes_resources[] = { { .start = OMAP24XX_SEC_AES_BASE, @@ -562,7 +560,7 @@ static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources); #define omap2_aes_resources_sz 0 #endif -#ifdef CONFIG_ARCH_OMAP3 +#ifdef CONFIG_ARCH_OMAP34XX static struct resource omap3_aes_resources[] = { { .start = OMAP34XX_SEC_AES_BASE, @@ -734,7 +732,7 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, omap_mux_init_signal("sdmmc_dat0", 0); omap_mux_init_signal("sdmmc_dat_dir0", 0); omap_mux_init_signal("sdmmc_cmd_dir", 0); - if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { + if (mmc_controller->slots[0].wires == 4) { omap_mux_init_signal("sdmmc_dat1", 0); omap_mux_init_signal("sdmmc_dat2", 0); omap_mux_init_signal("sdmmc_dat3", 0); @@ -762,8 +760,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc1_dat0", OMAP_PIN_INPUT_PULLUP); - if (mmc_controller->slots[0].caps & - (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { + if (mmc_controller->slots[0].wires == 4 || + mmc_controller->slots[0].wires == 8) { omap_mux_init_signal("sdmmc1_dat1", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc1_dat2", @@ -771,8 +769,7 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, omap_mux_init_signal("sdmmc1_dat3", OMAP_PIN_INPUT_PULLUP); } - if (mmc_controller->slots[0].caps & - MMC_CAP_8_BIT_DATA) { + if (mmc_controller->slots[0].wires == 8) { omap_mux_init_signal("sdmmc1_dat4", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc1_dat5", @@ -796,8 +793,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed * in the board-*.c files */ - if (mmc_controller->slots[0].caps & - (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { + if (mmc_controller->slots[0].wires == 4 || + mmc_controller->slots[0].wires == 8) { omap_mux_init_signal("sdmmc2_dat1", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc2_dat2", @@ -805,8 +802,7 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, omap_mux_init_signal("sdmmc2_dat3", OMAP_PIN_INPUT_PULLUP); } - if (mmc_controller->slots[0].caps & - MMC_CAP_8_BIT_DATA) { + if (mmc_controller->slots[0].wires == 8) { omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", @@ -857,13 +853,13 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, case 3: if (!cpu_is_omap44xx()) return; - base = OMAP4_MMC4_BASE; + base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET; irq = OMAP44XX_IRQ_MMC4; break; case 4: if (!cpu_is_omap44xx()) return; - base = OMAP4_MMC5_BASE; + base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET; irq = OMAP44XX_IRQ_MMC5; break; default: @@ -874,8 +870,10 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, size = OMAP2420_MMC_SIZE; name = "mmci-omap"; } else if (cpu_is_omap44xx()) { - if (i < 3) + if (i < 3) { + base += OMAP4_MMC_REG_OFFSET; irq += OMAP44XX_IRQ_GIC_START; + } size = OMAP4_HSMMC_SIZE; name = "mmci-omap-hs"; } else { @@ -951,72 +949,11 @@ static inline void omap_init_vout(void) {} /*-------------------------------------------------------------------------*/ -/* - * Inorder to avoid any assumptions from bootloader regarding WDT - * settings, WDT module is reset during init. This enables the watchdog - * timer. Hence it is required to disable the watchdog after the WDT reset - * during init. Otherwise the system would reboot as per the default - * watchdog timer registers settings. - */ -#define OMAP_WDT_WPS (0x34) -#define OMAP_WDT_SPR (0x48) - -static int omap2_disable_wdt(struct omap_hwmod *oh, void *unused) -{ - void __iomem *base; - int ret; - - if (!oh) { - pr_err("%s: Could not look up wdtimer_hwmod\n", __func__); - return -EINVAL; - } - - base = omap_hwmod_get_mpu_rt_va(oh); - if (!base) { - pr_err("%s: Could not get the base address for %s\n", - oh->name, __func__); - return -EINVAL; - } - - /* Enable the clocks before accessing the WDT registers */ - ret = omap_hwmod_enable(oh); - if (ret) { - pr_err("%s: Could not enable clocks for %s\n", - oh->name, __func__); - return ret; - } - - /* sequence required to disable watchdog */ - __raw_writel(0xAAAA, base + OMAP_WDT_SPR); - while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) - cpu_relax(); - - __raw_writel(0x5555, base + OMAP_WDT_SPR); - while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) - cpu_relax(); - - ret = omap_hwmod_idle(oh); - if (ret) - pr_err("%s: Could not disable clocks for %s\n", - oh->name, __func__); - - return ret; -} - -static void __init omap_disable_wdt(void) -{ - if (cpu_class_is_omap2()) - omap_hwmod_for_each_by_class("wd_timer", - omap2_disable_wdt, NULL); - return; -} - static int __init omap2_init_devices(void) { /* please keep these calls, and their implementations above, * in alphabetical order so they're easier to sort through. */ - omap_disable_wdt(); omap_hsmmc_reset(); omap_init_audio(); omap_init_camera(); @@ -1032,39 +969,3 @@ static int __init omap2_init_devices(void) return 0; } arch_initcall(omap2_init_devices); - -#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) -struct omap_device_pm_latency omap_wdt_latency[] = { - [0] = { - .deactivate_func = omap_device_idle_hwmods, - .activate_func = omap_device_enable_hwmods, - .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, - }, -}; - -static int __init omap_init_wdt(void) -{ - int id = -1; - struct omap_device *od; - struct omap_hwmod *oh; - char *oh_name = "wd_timer2"; - char *dev_name = "omap_wdt"; - - if (!cpu_class_is_omap2()) - return 0; - - oh = omap_hwmod_lookup(oh_name); - if (!oh) { - pr_err("Could not look up wd_timer%d hwmod\n", id); - return -EINVAL; - } - - od = omap_device_build(dev_name, id, oh, NULL, 0, - omap_wdt_latency, - ARRAY_SIZE(omap_wdt_latency), 0); - WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n", - dev_name, oh->name); - return 0; -} -subsys_initcall(omap_init_wdt); -#endif diff --git a/trunk/arch/arm/mach-omap2/gpmc-smsc911x.c b/trunk/arch/arm/mach-omap2/gpmc-smsc911x.c deleted file mode 100644 index 703f150dd01d..000000000000 --- a/trunk/arch/arm/mach-omap2/gpmc-smsc911x.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/gpmc-smsc911x.c - * - * Copyright (C) 2009 Li-Pro.Net - * Stephan Linz - * - * Modified from linux/arch/arm/mach-omap2/gpmc-smc91x.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -static struct omap_smsc911x_platform_data *gpmc_cfg; - -static struct resource gpmc_smsc911x_resources[] = { - [0] = { - .flags = IORESOURCE_MEM, - }, - [1] = { - .flags = IORESOURCE_IRQ, - }, -}; - -static struct smsc911x_platform_config gpmc_smsc911x_config = { - .phy_interface = PHY_INTERFACE_MODE_MII, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .flags = SMSC911X_USE_16BIT, -}; - -static struct platform_device gpmc_smsc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(gpmc_smsc911x_resources), - .resource = gpmc_smsc911x_resources, - .dev = { - .platform_data = &gpmc_smsc911x_config, - }, -}; - -/* - * Initialize smsc911x device connected to the GPMC. Note that we - * assume that pin multiplexing is done in the board-*.c file, - * or in the bootloader. - */ -void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data) -{ - unsigned long cs_mem_base; - int ret; - - gpmc_cfg = board_data; - - if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) { - printk(KERN_ERR "Failed to request GPMC mem for smsc911x\n"); - return; - } - - gpmc_smsc911x_resources[0].start = cs_mem_base + 0x0; - gpmc_smsc911x_resources[0].end = cs_mem_base + 0xff; - - if (gpio_request(gpmc_cfg->gpio_irq, "smsc911x irq") < 0) { - printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n", - gpmc_cfg->gpio_irq); - goto free1; - } - - gpio_direction_input(gpmc_cfg->gpio_irq); - gpmc_smsc911x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq); - gpmc_smsc911x_resources[1].flags |= - (gpmc_cfg->flags & IRQF_TRIGGER_MASK); - - if (gpio_is_valid(gpmc_cfg->gpio_reset)) { - ret = gpio_request(gpmc_cfg->gpio_reset, "smsc911x reset"); - if (ret) { - printk(KERN_ERR "Failed to request GPIO%d for smsc911x reset\n", - gpmc_cfg->gpio_reset); - goto free2; - } - - gpio_direction_output(gpmc_cfg->gpio_reset, 1); - gpio_set_value(gpmc_cfg->gpio_reset, 0); - msleep(100); - gpio_set_value(gpmc_cfg->gpio_reset, 1); - } - - if (platform_device_register(&gpmc_smsc911x_device) < 0) { - printk(KERN_ERR "Unable to register smsc911x device\n"); - gpio_free(gpmc_cfg->gpio_reset); - goto free2; - } - - return; - -free2: - gpio_free(gpmc_cfg->gpio_irq); -free1: - gpmc_cs_free(gpmc_cfg->cs); - - printk(KERN_ERR "Could not initialize smsc911x\n"); -} diff --git a/trunk/arch/arm/mach-omap2/hsmmc.c b/trunk/arch/arm/mach-omap2/hsmmc.c index 34272e4863fd..c8f647b6205e 100644 --- a/trunk/arch/arm/mach-omap2/hsmmc.c +++ b/trunk/arch/arm/mach-omap2/hsmmc.c @@ -14,11 +14,11 @@ #include #include #include +#include #include #include #include "hsmmc.h" -#include "control.h" #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) @@ -135,11 +135,10 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, * * FIXME handle VMMC1A as needed ... */ - reg = omap4_ctrl_pad_readl(control_pbias_offset); - reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | - OMAP4_MMC1_PWRDNZ_MASK | - OMAP4_USBC1_ICUSB_PWRDNZ_MASK); - omap4_ctrl_pad_writel(reg, control_pbias_offset); + reg = omap_ctrl_readl(control_pbias_offset); + reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | + OMAP4_USBC1_ICUSB_PWRDNZ); + omap_ctrl_writel(reg, control_pbias_offset); } static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, @@ -148,33 +147,30 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, u32 reg; if (power_on) { - reg = omap4_ctrl_pad_readl(control_pbias_offset); - reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK; + reg = omap_ctrl_readl(control_pbias_offset); + reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ; if ((1 << vdd) <= MMC_VDD_165_195) - reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK; + reg &= ~OMAP4_MMC1_PBIASLITE_VMODE; else - reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK; - reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | - OMAP4_MMC1_PWRDNZ_MASK | - OMAP4_USBC1_ICUSB_PWRDNZ_MASK); - omap4_ctrl_pad_writel(reg, control_pbias_offset); + reg |= OMAP4_MMC1_PBIASLITE_VMODE; + reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | + OMAP4_USBC1_ICUSB_PWRDNZ); + omap_ctrl_writel(reg, control_pbias_offset); /* 4 microsec delay for comparator to generate an error*/ udelay(4); - reg = omap4_ctrl_pad_readl(control_pbias_offset); - if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) { + reg = omap_ctrl_readl(control_pbias_offset); + if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR) { pr_err("Pbias Voltage is not same as LDO\n"); /* Caution : On VMODE_ERROR Power Down MMC IO */ - reg &= ~(OMAP4_MMC1_PWRDNZ_MASK | - OMAP4_USBC1_ICUSB_PWRDNZ_MASK); - omap4_ctrl_pad_writel(reg, control_pbias_offset); + reg &= ~(OMAP4_MMC1_PWRDNZ | OMAP4_USBC1_ICUSB_PWRDNZ); + omap_ctrl_writel(reg, control_pbias_offset); } } else { - reg = omap4_ctrl_pad_readl(control_pbias_offset); - reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | - OMAP4_MMC1_PWRDNZ_MASK | - OMAP4_MMC1_PBIASLITE_VMODE_MASK | - OMAP4_USBC1_ICUSB_PWRDNZ_MASK); - omap4_ctrl_pad_writel(reg, control_pbias_offset); + reg = omap_ctrl_readl(control_pbias_offset); + reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | + OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ | + OMAP4_USBC1_ICUSB_PWRDNZ); + omap_ctrl_writel(reg, control_pbias_offset); } } @@ -222,18 +218,17 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; } } else { - control_pbias_offset = - OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; - control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; - reg = omap4_ctrl_pad_readl(control_mmc1); - reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | - OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); - reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | - OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); - reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| - OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | - OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); - omap4_ctrl_pad_writel(reg, control_mmc1); + control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE; + control_mmc1 = OMAP44XX_CONTROL_MMC1; + reg = omap_ctrl_readl(control_mmc1); + reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 | + OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1); + reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 | + OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3); + reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL | + OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL | + OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL); + omap_ctrl_writel(reg, control_mmc1); } for (c = controllers; c->mmc; c++) { @@ -263,13 +258,9 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) "mmc%islot%i", c->mmc, 1); mmc->slots[0].name = hc->name; mmc->nr_slots = 1; - mmc->slots[0].caps = c->caps; + mmc->slots[0].wires = c->wires; mmc->slots[0].internal_clock = !c->ext_clock; mmc->dma_mask = 0xffffffff; - if (cpu_is_omap44xx()) - mmc->reg_offset = OMAP4_MMC_REG_OFFSET; - else - mmc->reg_offset = 0; mmc->get_context_loss_count = hsmmc_get_context_loss; @@ -307,9 +298,6 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) else mmc->slots[0].features |= HSMMC_HAS_PBIAS; - if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) - mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; - switch (c->mmc) { case 1: if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { @@ -328,20 +316,16 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) } /* Omap3630 HSMMC1 supports only 4-bit */ - if (cpu_is_omap3630() && - (c->caps & MMC_CAP_8_BIT_DATA)) { - c->caps &= ~MMC_CAP_8_BIT_DATA; - c->caps |= MMC_CAP_4_BIT_DATA; - mmc->slots[0].caps = c->caps; + if (cpu_is_omap3630() && c->wires > 4) { + c->wires = 4; + mmc->slots[0].wires = c->wires; } break; case 2: if (c->ext_clock) c->transceiver = 1; - if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { - c->caps &= ~MMC_CAP_8_BIT_DATA; - c->caps |= MMC_CAP_4_BIT_DATA; - } + if (c->transceiver && c->wires > 4) + c->wires = 4; /* FALLTHROUGH */ case 3: if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { diff --git a/trunk/arch/arm/mach-omap2/hsmmc.h b/trunk/arch/arm/mach-omap2/hsmmc.h index f119348827d4..0f8a2e6ee284 100644 --- a/trunk/arch/arm/mach-omap2/hsmmc.h +++ b/trunk/arch/arm/mach-omap2/hsmmc.h @@ -10,8 +10,7 @@ struct mmc_card; struct omap2_hsmmc_info { u8 mmc; /* controller 1/2/3 */ - u32 caps; /* 4/8 wires and any additional host - * capabilities OR'd (ref. linux/mmc/host.h) */ + u8 wires; /* 1/4/8 wires */ bool transceiver; /* MMC-2 option */ bool ext_clock; /* use external pin for input clock */ bool cover_only; /* No card detect - just cover switch */ diff --git a/trunk/arch/arm/mach-omap2/id.c b/trunk/arch/arm/mach-omap2/id.c index 5f9086c65e48..9a879f959509 100644 --- a/trunk/arch/arm/mach-omap2/id.c +++ b/trunk/arch/arm/mach-omap2/id.c @@ -22,12 +22,11 @@ #include #include +#include #include #include -#include "control.h" - static struct omap_chip_id omap_chip; static unsigned int omap_revision; @@ -61,7 +60,7 @@ int omap_type(void) } else if (cpu_is_omap34xx()) { val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); } else if (cpu_is_omap44xx()) { - val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); + val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS); } else { pr_err("Cannot detect omap type!\n"); goto out; @@ -299,6 +298,7 @@ static void __init omap4_check_revision(void) u32 idcode; u16 hawkeye; u8 rev; + char *rev_name = "ES1.0"; /* * The IC rev detection is done with hawkeye and rev. @@ -309,39 +309,14 @@ static void __init omap4_check_revision(void) hawkeye = (idcode >> 12) & 0xffff; rev = (idcode >> 28) & 0xff; - /* - * Few initial ES2.0 samples IDCODE is same as ES1.0 - * Use ARM register to detect the correct ES version - */ - if (!rev) { - idcode = read_cpuid(CPUID_ID); - rev = (idcode & 0xf) - 1; - } - - switch (hawkeye) { - case 0xb852: - switch (rev) { - case 0: - omap_revision = OMAP4430_REV_ES1_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES1; - break; - case 1: - omap_revision = OMAP4430_REV_ES2_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES2; - break; - default: - omap_revision = OMAP4430_REV_ES2_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES2; - } - break; - default: - /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP4430_REV_ES2_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES2; + if ((hawkeye == 0xb852) && (rev == 0x0)) { + omap_revision = OMAP4430_REV_ES1_0; + omap_chip.oc |= CHIP_IS_OMAP4430ES1; + pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); + return; } - pr_info("OMAP%04x ES%d.0\n", - omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1); + pr_err("Unknown OMAP4 CPU id\n"); } #define OMAP3_SHOW_FEATURE(feat) \ @@ -386,54 +361,30 @@ static void __init omap3_cpuinfo(void) strcpy(cpu_name, "OMAP3503"); } - if (cpu_is_omap3630()) { - switch (rev) { - case OMAP_REVBITS_00: - strcpy(cpu_rev, "1.0"); - break; - case OMAP_REVBITS_01: - strcpy(cpu_rev, "1.1"); - break; - case OMAP_REVBITS_02: - /* FALLTHROUGH */ - default: - /* Use the latest known revision as default */ - strcpy(cpu_rev, "1.2"); - } - } else if (cpu_is_omap3505() || cpu_is_omap3517()) { - switch (rev) { - case OMAP_REVBITS_00: - strcpy(cpu_rev, "1.0"); - break; - case OMAP_REVBITS_01: - /* FALLTHROUGH */ - default: - /* Use the latest known revision as default */ - strcpy(cpu_rev, "1.1"); - } - } else { - switch (rev) { - case OMAP_REVBITS_00: - strcpy(cpu_rev, "1.0"); - break; - case OMAP_REVBITS_01: - strcpy(cpu_rev, "2.0"); - break; - case OMAP_REVBITS_02: - strcpy(cpu_rev, "2.1"); - break; - case OMAP_REVBITS_03: - strcpy(cpu_rev, "3.0"); - break; - case OMAP_REVBITS_04: - strcpy(cpu_rev, "3.1"); - break; - case OMAP_REVBITS_05: - /* FALLTHROUGH */ - default: - /* Use the latest known revision as default */ - strcpy(cpu_rev, "3.1.2"); - } + switch (rev) { + case OMAP_REVBITS_00: + strcpy(cpu_rev, "1.0"); + break; + case OMAP_REVBITS_01: + strcpy(cpu_rev, "1.1"); + break; + case OMAP_REVBITS_02: + strcpy(cpu_rev, "1.2"); + break; + case OMAP_REVBITS_10: + strcpy(cpu_rev, "2.0"); + break; + case OMAP_REVBITS_20: + strcpy(cpu_rev, "2.1"); + break; + case OMAP_REVBITS_30: + strcpy(cpu_rev, "3.0"); + break; + case OMAP_REVBITS_40: + /* FALLTHROUGH */ + default: + /* Use the latest known revision as default */ + strcpy(cpu_rev, "3.1"); } /* Print verbose information */ diff --git a/trunk/arch/arm/mach-omap2/board-flash.h b/trunk/arch/arm/mach-omap2/include/mach/board-flash.h similarity index 88% rename from trunk/arch/arm/mach-omap2/board-flash.h rename to trunk/arch/arm/mach-omap2/include/mach/board-flash.h index 69befe00dd2f..b2242ae2bb6f 100644 --- a/trunk/arch/arm/mach-omap2/board-flash.h +++ b/trunk/arch/arm/mach-omap2/include/mach/board-flash.h @@ -26,5 +26,3 @@ struct flash_partitions { extern void board_flash_init(struct flash_partitions [], char chip_sel[][GPMC_CS_NUM]); -extern void board_nand_init(struct mtd_partition *nand_parts, - u8 nr_parts, u8 cs); diff --git a/trunk/arch/arm/mach-omap2/include/mach/board-rx51.h b/trunk/arch/arm/mach-omap2/include/mach/board-rx51.h deleted file mode 100644 index b76f49e7eed5..000000000000 --- a/trunk/arch/arm/mach-omap2/include/mach/board-rx51.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Defines for rx51 boards - */ - -#ifndef _OMAP_BOARD_RX51_H -#define _OMAP_BOARD_RX51_H - -extern void __init rx51_peripherals_init(void); -extern void __init rx51_video_mem_init(void); - -#endif diff --git a/trunk/arch/arm/mach-omap2/include/mach/board-zoom.h b/trunk/arch/arm/mach-omap2/include/mach/board-zoom.h index f93ca3928c3b..80591fda8f8f 100644 --- a/trunk/arch/arm/mach-omap2/include/mach/board-zoom.h +++ b/trunk/arch/arm/mach-omap2/include/mach/board-zoom.h @@ -1,8 +1,12 @@ /* * Defines for zoom boards */ +#include +#include + #define ZOOM_NAND_CS 0 +extern void __init board_nand_init(struct mtd_partition *, u8 nr_parts, u8 cs); extern int __init zoom_debugboard_init(void); extern void __init zoom_peripherals_init(void); diff --git a/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h deleted file mode 100644 index 2f7ac70a20d8..000000000000 --- a/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h +++ /dev/null @@ -1,391 +0,0 @@ -/* - * OMAP44xx CTRL_MODULE_CORE registers and bitfields - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * - * Benoit Cousson (b-cousson@ti.com) - * Santosh Shilimkar (santosh.shilimkar@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H - - -/* Base address */ -#define OMAP4_CTRL_MODULE_CORE 0x4a002000 - -/* Registers offset */ -#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000 -#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004 -#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200 -#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268 -#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 -#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300 -#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314 -#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318 -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320 -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324 -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328 -#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c -#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330 -#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334 -#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c -#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340 -#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350 -#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400 -#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408 -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430 -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434 -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438 -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440 -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444 -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448 -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450 -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc - -/* Registers shifts and masks */ - -/* IP_REVISION */ -#define OMAP4_IP_REV_SCHEME_SHIFT 30 -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) -#define OMAP4_IP_REV_FUNC_SHIFT 16 -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) -#define OMAP4_IP_REV_RTL_SHIFT 11 -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) -#define OMAP4_IP_REV_MAJOR_SHIFT 8 -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) -#define OMAP4_IP_REV_CUSTOM_SHIFT 6 -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) -#define OMAP4_IP_REV_MINOR_SHIFT 0 -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) - -/* IP_HWINFO */ -#define OMAP4_IP_HWINFO_SHIFT 0 -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) - -/* IP_SYSCONFIG */ -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) - -/* STD_FUSE_DIE_ID_0 */ -#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0 -#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0) - -/* ID_CODE */ -#define OMAP4_STD_FUSE_IDCODE_SHIFT 0 -#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0) - -/* STD_FUSE_DIE_ID_1 */ -#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0 -#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0) - -/* STD_FUSE_DIE_ID_2 */ -#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0 -#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0) - -/* STD_FUSE_DIE_ID_3 */ -#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0 -#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0) - -/* STD_FUSE_PROD_ID_0 */ -#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0 -#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0) - -/* STD_FUSE_PROD_ID_1 */ -#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0 -#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0) - -/* STD_FUSE_USB_CONF */ -#define OMAP4_USB_PROD_ID_SHIFT 16 -#define OMAP4_USB_PROD_ID_MASK (0xffff << 16) -#define OMAP4_USB_VENDOR_ID_SHIFT 0 -#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0) - -/* STD_FUSE_OPP_VDD_WKUP */ -#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0 -#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0) - -/* STD_FUSE_OPP_BGAP */ -#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0 -#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0) - -/* STD_FUSE_OPP_DPLL_0 */ -#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0 -#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0) - -/* STD_FUSE_OPP_DPLL_1 */ -#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0 -#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0) - -/* STATUS */ -#define OMAP4_ATTILA_CONF_SHIFT 11 -#define OMAP4_ATTILA_CONF_MASK (0x3 << 11) -#define OMAP4_DEVICE_TYPE_SHIFT 8 -#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8) -#define OMAP4_SYS_BOOT_SHIFT 0 -#define OMAP4_SYS_BOOT_MASK (0xff << 0) - -/* DEV_CONF */ -#define OMAP4_DEV_CONF_SHIFT 1 -#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1) -#define OMAP4_USBPHY_PD_SHIFT 0 -#define OMAP4_USBPHY_PD_MASK (1 << 0) - -/* LDOVBB_IVA_VOLTAGE_CTRL */ -#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26 -#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26) -#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21 -#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21) -#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16 -#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16) -#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10 -#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10) -#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5 -#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5) -#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0 -#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0) - -/* LDOVBB_MPU_VOLTAGE_CTRL */ -#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26 -#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26) -#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21 -#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21) -#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16 -#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16) -#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10 -#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10) -#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5 -#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5) -#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0 -#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0) - -/* LDOSRAM_IVA_VOLTAGE_CTRL */ -#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26 -#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26) -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21 -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21) -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16 -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16) -#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10 -#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10) -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5 -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5) -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0 -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0) - -/* LDOSRAM_MPU_VOLTAGE_CTRL */ -#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26 -#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26) -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21 -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21) -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16 -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16) -#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10 -#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10) -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5 -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5) -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0 -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0) - -/* LDOSRAM_CORE_VOLTAGE_CTRL */ -#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26 -#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26) -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21 -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21) -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16 -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16) -#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10 -#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10) -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5 -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5) -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0 -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0) - -/* TEMP_SENSOR */ -#define OMAP4_BGAP_TEMPSOFF_SHIFT 12 -#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12) -#define OMAP4_BGAP_TSHUT_SHIFT 11 -#define OMAP4_BGAP_TSHUT_MASK (1 << 11) -#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10 -#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10) -#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9 -#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9) -#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8 -#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8) -#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0 -#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0) - -/* DPLL_NWELL_TRIM_0 */ -#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29 -#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) -#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24 -#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24) -#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23 -#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) -#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18 -#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18) -#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17 -#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) -#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12 -#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12) -#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11 -#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) -#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6 -#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6) -#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5 -#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) -#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0 -#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0) - -/* DPLL_NWELL_TRIM_1 */ -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29 -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24 -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24) -#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23 -#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) -#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18 -#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18) -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17 -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) -#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12 -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12) -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11 -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) -#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6 -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6) -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5 -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) -#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0 -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0) - -/* USBOTGHS_CONTROL */ -#define OMAP4_DISCHRGVBUS_SHIFT 8 -#define OMAP4_DISCHRGVBUS_MASK (1 << 8) -#define OMAP4_CHRGVBUS_SHIFT 7 -#define OMAP4_CHRGVBUS_MASK (1 << 7) -#define OMAP4_DRVVBUS_SHIFT 6 -#define OMAP4_DRVVBUS_MASK (1 << 6) -#define OMAP4_IDPULLUP_SHIFT 5 -#define OMAP4_IDPULLUP_MASK (1 << 5) -#define OMAP4_IDDIG_SHIFT 4 -#define OMAP4_IDDIG_MASK (1 << 4) -#define OMAP4_SESSEND_SHIFT 3 -#define OMAP4_SESSEND_MASK (1 << 3) -#define OMAP4_VBUSVALID_SHIFT 2 -#define OMAP4_VBUSVALID_MASK (1 << 2) -#define OMAP4_BVALID_SHIFT 1 -#define OMAP4_BVALID_MASK (1 << 1) -#define OMAP4_AVALID_SHIFT 0 -#define OMAP4_AVALID_MASK (1 << 0) - -/* DSS_CONTROL */ -#define OMAP4_DSS_MUX6_SELECT_SHIFT 0 -#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0) - -/* HWOBS_CONTROL */ -#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3 -#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3) -#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2 -#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2) -#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1 -#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1) -#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0 -#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0) - -/* DEBOBS_FINAL_MUX_SEL */ -#define OMAP4_SELECT_SHIFT 0 -#define OMAP4_SELECT_MASK (0xffffffff << 0) - -/* DEBOBS_MMR_MPU */ -#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0 -#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0) - -/* CONF_SDMA_REQ_SEL0 */ -#define OMAP4_MULT_SHIFT 0 -#define OMAP4_MULT_MASK (0x7f << 0) - -/* CONF_CLK_SEL0 */ -#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0 -#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0) - -/* CONF_CLK_SEL1 */ -#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0 -#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0) - -/* CONF_CLK_SEL2 */ -#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0 -#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0) - -/* CONF_DPLL_FREQLOCK_SEL */ -#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0 -#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0) - -/* CONF_DPLL_TINITZ_SEL */ -#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0 -#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0) - -/* CONF_DPLL_PHASELOCK_SEL */ -#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0 -#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0) - -/* CONF_DEBUG_SEL_TST_0 */ -#define OMAP4_MODE_SHIFT 0 -#define OMAP4_MODE_MASK (0xf << 0) - -#endif diff --git a/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h deleted file mode 100644 index c88420de1151..000000000000 --- a/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h +++ /dev/null @@ -1,1409 +0,0 @@ -/* - * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * - * Benoit Cousson (b-cousson@ti.com) - * Santosh Shilimkar (santosh.shilimkar@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H - - -/* Base address */ -#define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000 - -/* Registers offset */ -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000 -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004 -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010 -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8 -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0 -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4 -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8 -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660 -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664 -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c - -/* Registers shifts and masks */ - -/* IP_REVISION */ -#define OMAP4_IP_REV_SCHEME_SHIFT 30 -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) -#define OMAP4_IP_REV_FUNC_SHIFT 16 -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) -#define OMAP4_IP_REV_RTL_SHIFT 11 -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) -#define OMAP4_IP_REV_MAJOR_SHIFT 8 -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) -#define OMAP4_IP_REV_CUSTOM_SHIFT 6 -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) -#define OMAP4_IP_REV_MINOR_SHIFT 0 -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) - -/* IP_HWINFO */ -#define OMAP4_IP_HWINFO_SHIFT 0 -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) - -/* IP_SYSCONFIG */ -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) - -/* PADCONF_WAKEUPEVENT_0 */ -#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_1 */ -#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_2 */ -#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_3 */ -#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_4 */ -#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_5 */ -#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_6 */ -#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* CONTROL_PADCONF_GLOBAL */ -#define OMAP4_FORCE_OFFMODE_EN_SHIFT 31 -#define OMAP4_FORCE_OFFMODE_EN_MASK (1 << 31) - -/* CONTROL_PADCONF_MODE */ -#define OMAP4_VDDS_DV_BANK0_SHIFT 31 -#define OMAP4_VDDS_DV_BANK0_MASK (1 << 31) -#define OMAP4_VDDS_DV_BANK1_SHIFT 30 -#define OMAP4_VDDS_DV_BANK1_MASK (1 << 30) -#define OMAP4_VDDS_DV_BANK3_SHIFT 29 -#define OMAP4_VDDS_DV_BANK3_MASK (1 << 29) -#define OMAP4_VDDS_DV_BANK4_SHIFT 28 -#define OMAP4_VDDS_DV_BANK4_MASK (1 << 28) -#define OMAP4_VDDS_DV_BANK5_SHIFT 27 -#define OMAP4_VDDS_DV_BANK5_MASK (1 << 27) -#define OMAP4_VDDS_DV_BANK6_SHIFT 26 -#define OMAP4_VDDS_DV_BANK6_MASK (1 << 26) -#define OMAP4_VDDS_DV_C2C_SHIFT 25 -#define OMAP4_VDDS_DV_C2C_MASK (1 << 25) -#define OMAP4_VDDS_DV_CAM_SHIFT 24 -#define OMAP4_VDDS_DV_CAM_MASK (1 << 24) -#define OMAP4_VDDS_DV_GPMC_SHIFT 23 -#define OMAP4_VDDS_DV_GPMC_MASK (1 << 23) -#define OMAP4_VDDS_DV_SDMMC2_SHIFT 22 -#define OMAP4_VDDS_DV_SDMMC2_MASK (1 << 22) - -/* CONTROL_SMART1IO_PADCONF_0 */ -#define OMAP4_ABE_DR0_SC_SHIFT 30 -#define OMAP4_ABE_DR0_SC_MASK (0x3 << 30) -#define OMAP4_CAM_DR0_SC_SHIFT 28 -#define OMAP4_CAM_DR0_SC_MASK (0x3 << 28) -#define OMAP4_FREF_DR2_SC_SHIFT 26 -#define OMAP4_FREF_DR2_SC_MASK (0x3 << 26) -#define OMAP4_FREF_DR3_SC_SHIFT 24 -#define OMAP4_FREF_DR3_SC_MASK (0x3 << 24) -#define OMAP4_GPIO_DR8_SC_SHIFT 22 -#define OMAP4_GPIO_DR8_SC_MASK (0x3 << 22) -#define OMAP4_GPIO_DR9_SC_SHIFT 20 -#define OMAP4_GPIO_DR9_SC_MASK (0x3 << 20) -#define OMAP4_GPMC_DR2_SC_SHIFT 18 -#define OMAP4_GPMC_DR2_SC_MASK (0x3 << 18) -#define OMAP4_GPMC_DR3_SC_SHIFT 16 -#define OMAP4_GPMC_DR3_SC_MASK (0x3 << 16) -#define OMAP4_GPMC_DR6_SC_SHIFT 14 -#define OMAP4_GPMC_DR6_SC_MASK (0x3 << 14) -#define OMAP4_HDMI_DR0_SC_SHIFT 12 -#define OMAP4_HDMI_DR0_SC_MASK (0x3 << 12) -#define OMAP4_MCSPI1_DR0_SC_SHIFT 10 -#define OMAP4_MCSPI1_DR0_SC_MASK (0x3 << 10) -#define OMAP4_UART1_DR0_SC_SHIFT 8 -#define OMAP4_UART1_DR0_SC_MASK (0x3 << 8) -#define OMAP4_UART3_DR0_SC_SHIFT 6 -#define OMAP4_UART3_DR0_SC_MASK (0x3 << 6) -#define OMAP4_UART3_DR1_SC_SHIFT 4 -#define OMAP4_UART3_DR1_SC_MASK (0x3 << 4) -#define OMAP4_UNIPRO_DR0_SC_SHIFT 2 -#define OMAP4_UNIPRO_DR0_SC_MASK (0x3 << 2) -#define OMAP4_UNIPRO_DR1_SC_SHIFT 0 -#define OMAP4_UNIPRO_DR1_SC_MASK (0x3 << 0) - -/* CONTROL_SMART1IO_PADCONF_1 */ -#define OMAP4_ABE_DR0_LB_SHIFT 30 -#define OMAP4_ABE_DR0_LB_MASK (0x3 << 30) -#define OMAP4_CAM_DR0_LB_SHIFT 28 -#define OMAP4_CAM_DR0_LB_MASK (0x3 << 28) -#define OMAP4_FREF_DR2_LB_SHIFT 26 -#define OMAP4_FREF_DR2_LB_MASK (0x3 << 26) -#define OMAP4_FREF_DR3_LB_SHIFT 24 -#define OMAP4_FREF_DR3_LB_MASK (0x3 << 24) -#define OMAP4_GPIO_DR8_LB_SHIFT 22 -#define OMAP4_GPIO_DR8_LB_MASK (0x3 << 22) -#define OMAP4_GPIO_DR9_LB_SHIFT 20 -#define OMAP4_GPIO_DR9_LB_MASK (0x3 << 20) -#define OMAP4_GPMC_DR2_LB_SHIFT 18 -#define OMAP4_GPMC_DR2_LB_MASK (0x3 << 18) -#define OMAP4_GPMC_DR3_LB_SHIFT 16 -#define OMAP4_GPMC_DR3_LB_MASK (0x3 << 16) -#define OMAP4_GPMC_DR6_LB_SHIFT 14 -#define OMAP4_GPMC_DR6_LB_MASK (0x3 << 14) -#define OMAP4_HDMI_DR0_LB_SHIFT 12 -#define OMAP4_HDMI_DR0_LB_MASK (0x3 << 12) -#define OMAP4_MCSPI1_DR0_LB_SHIFT 10 -#define OMAP4_MCSPI1_DR0_LB_MASK (0x3 << 10) -#define OMAP4_UART1_DR0_LB_SHIFT 8 -#define OMAP4_UART1_DR0_LB_MASK (0x3 << 8) -#define OMAP4_UART3_DR0_LB_SHIFT 6 -#define OMAP4_UART3_DR0_LB_MASK (0x3 << 6) -#define OMAP4_UART3_DR1_LB_SHIFT 4 -#define OMAP4_UART3_DR1_LB_MASK (0x3 << 4) -#define OMAP4_UNIPRO_DR0_LB_SHIFT 2 -#define OMAP4_UNIPRO_DR0_LB_MASK (0x3 << 2) -#define OMAP4_UNIPRO_DR1_LB_SHIFT 0 -#define OMAP4_UNIPRO_DR1_LB_MASK (0x3 << 0) - -/* CONTROL_SMART2IO_PADCONF_0 */ -#define OMAP4_C2C_DR0_LB_SHIFT 31 -#define OMAP4_C2C_DR0_LB_MASK (1 << 31) -#define OMAP4_DPM_DR1_LB_SHIFT 30 -#define OMAP4_DPM_DR1_LB_MASK (1 << 30) -#define OMAP4_DPM_DR2_LB_SHIFT 29 -#define OMAP4_DPM_DR2_LB_MASK (1 << 29) -#define OMAP4_DPM_DR3_LB_SHIFT 28 -#define OMAP4_DPM_DR3_LB_MASK (1 << 28) -#define OMAP4_GPIO_DR0_LB_SHIFT 27 -#define OMAP4_GPIO_DR0_LB_MASK (1 << 27) -#define OMAP4_GPIO_DR1_LB_SHIFT 26 -#define OMAP4_GPIO_DR1_LB_MASK (1 << 26) -#define OMAP4_GPIO_DR10_LB_SHIFT 25 -#define OMAP4_GPIO_DR10_LB_MASK (1 << 25) -#define OMAP4_GPIO_DR2_LB_SHIFT 24 -#define OMAP4_GPIO_DR2_LB_MASK (1 << 24) -#define OMAP4_GPMC_DR0_LB_SHIFT 23 -#define OMAP4_GPMC_DR0_LB_MASK (1 << 23) -#define OMAP4_GPMC_DR1_LB_SHIFT 22 -#define OMAP4_GPMC_DR1_LB_MASK (1 << 22) -#define OMAP4_GPMC_DR4_LB_SHIFT 21 -#define OMAP4_GPMC_DR4_LB_MASK (1 << 21) -#define OMAP4_GPMC_DR5_LB_SHIFT 20 -#define OMAP4_GPMC_DR5_LB_MASK (1 << 20) -#define OMAP4_GPMC_DR7_LB_SHIFT 19 -#define OMAP4_GPMC_DR7_LB_MASK (1 << 19) -#define OMAP4_HSI2_DR0_LB_SHIFT 18 -#define OMAP4_HSI2_DR0_LB_MASK (1 << 18) -#define OMAP4_HSI2_DR1_LB_SHIFT 17 -#define OMAP4_HSI2_DR1_LB_MASK (1 << 17) -#define OMAP4_HSI2_DR2_LB_SHIFT 16 -#define OMAP4_HSI2_DR2_LB_MASK (1 << 16) -#define OMAP4_KPD_DR0_LB_SHIFT 15 -#define OMAP4_KPD_DR0_LB_MASK (1 << 15) -#define OMAP4_KPD_DR1_LB_SHIFT 14 -#define OMAP4_KPD_DR1_LB_MASK (1 << 14) -#define OMAP4_PDM_DR0_LB_SHIFT 13 -#define OMAP4_PDM_DR0_LB_MASK (1 << 13) -#define OMAP4_SDMMC2_DR0_LB_SHIFT 12 -#define OMAP4_SDMMC2_DR0_LB_MASK (1 << 12) -#define OMAP4_SDMMC3_DR0_LB_SHIFT 11 -#define OMAP4_SDMMC3_DR0_LB_MASK (1 << 11) -#define OMAP4_SDMMC4_DR0_LB_SHIFT 10 -#define OMAP4_SDMMC4_DR0_LB_MASK (1 << 10) -#define OMAP4_SDMMC4_DR1_LB_SHIFT 9 -#define OMAP4_SDMMC4_DR1_LB_MASK (1 << 9) -#define OMAP4_SPI3_DR0_LB_SHIFT 8 -#define OMAP4_SPI3_DR0_LB_MASK (1 << 8) -#define OMAP4_SPI3_DR1_LB_SHIFT 7 -#define OMAP4_SPI3_DR1_LB_MASK (1 << 7) -#define OMAP4_UART3_DR2_LB_SHIFT 6 -#define OMAP4_UART3_DR2_LB_MASK (1 << 6) -#define OMAP4_UART3_DR3_LB_SHIFT 5 -#define OMAP4_UART3_DR3_LB_MASK (1 << 5) -#define OMAP4_UART3_DR4_LB_SHIFT 4 -#define OMAP4_UART3_DR4_LB_MASK (1 << 4) -#define OMAP4_UART3_DR5_LB_SHIFT 3 -#define OMAP4_UART3_DR5_LB_MASK (1 << 3) -#define OMAP4_USBA0_DR1_LB_SHIFT 2 -#define OMAP4_USBA0_DR1_LB_MASK (1 << 2) -#define OMAP4_USBA_DR2_LB_SHIFT 1 -#define OMAP4_USBA_DR2_LB_MASK (1 << 1) - -/* CONTROL_SMART2IO_PADCONF_1 */ -#define OMAP4_USBB1_DR0_LB_SHIFT 31 -#define OMAP4_USBB1_DR0_LB_MASK (1 << 31) -#define OMAP4_USBB2_DR0_LB_SHIFT 30 -#define OMAP4_USBB2_DR0_LB_MASK (1 << 30) -#define OMAP4_USBA0_DR0_LB_SHIFT 29 -#define OMAP4_USBA0_DR0_LB_MASK (1 << 29) - -/* CONTROL_SMART3IO_PADCONF_0 */ -#define OMAP4_DMIC_DR0_MB_SHIFT 30 -#define OMAP4_DMIC_DR0_MB_MASK (0x3 << 30) -#define OMAP4_GPIO_DR3_MB_SHIFT 28 -#define OMAP4_GPIO_DR3_MB_MASK (0x3 << 28) -#define OMAP4_GPIO_DR4_MB_SHIFT 26 -#define OMAP4_GPIO_DR4_MB_MASK (0x3 << 26) -#define OMAP4_GPIO_DR5_MB_SHIFT 24 -#define OMAP4_GPIO_DR5_MB_MASK (0x3 << 24) -#define OMAP4_GPIO_DR6_MB_SHIFT 22 -#define OMAP4_GPIO_DR6_MB_MASK (0x3 << 22) -#define OMAP4_HSI_DR1_MB_SHIFT 20 -#define OMAP4_HSI_DR1_MB_MASK (0x3 << 20) -#define OMAP4_HSI_DR2_MB_SHIFT 18 -#define OMAP4_HSI_DR2_MB_MASK (0x3 << 18) -#define OMAP4_HSI_DR3_MB_SHIFT 16 -#define OMAP4_HSI_DR3_MB_MASK (0x3 << 16) -#define OMAP4_MCBSP2_DR0_MB_SHIFT 14 -#define OMAP4_MCBSP2_DR0_MB_MASK (0x3 << 14) -#define OMAP4_MCSPI4_DR0_MB_SHIFT 12 -#define OMAP4_MCSPI4_DR0_MB_MASK (0x3 << 12) -#define OMAP4_MCSPI4_DR1_MB_SHIFT 10 -#define OMAP4_MCSPI4_DR1_MB_MASK (0x3 << 10) -#define OMAP4_SDMMC3_DR0_MB_SHIFT 8 -#define OMAP4_SDMMC3_DR0_MB_MASK (0x3 << 8) -#define OMAP4_SPI2_DR0_MB_SHIFT 0 -#define OMAP4_SPI2_DR0_MB_MASK (0x3 << 0) - -/* CONTROL_SMART3IO_PADCONF_1 */ -#define OMAP4_SPI2_DR1_MB_SHIFT 30 -#define OMAP4_SPI2_DR1_MB_MASK (0x3 << 30) -#define OMAP4_SPI2_DR2_MB_SHIFT 28 -#define OMAP4_SPI2_DR2_MB_MASK (0x3 << 28) -#define OMAP4_UART2_DR0_MB_SHIFT 26 -#define OMAP4_UART2_DR0_MB_MASK (0x3 << 26) -#define OMAP4_UART2_DR1_MB_SHIFT 24 -#define OMAP4_UART2_DR1_MB_MASK (0x3 << 24) -#define OMAP4_UART4_DR0_MB_SHIFT 22 -#define OMAP4_UART4_DR0_MB_MASK (0x3 << 22) -#define OMAP4_HSI_DR0_MB_SHIFT 20 -#define OMAP4_HSI_DR0_MB_MASK (0x3 << 20) - -/* CONTROL_SMART3IO_PADCONF_2 */ -#define OMAP4_DMIC_DR0_LB_SHIFT 31 -#define OMAP4_DMIC_DR0_LB_MASK (1 << 31) -#define OMAP4_GPIO_DR3_LB_SHIFT 30 -#define OMAP4_GPIO_DR3_LB_MASK (1 << 30) -#define OMAP4_GPIO_DR4_LB_SHIFT 29 -#define OMAP4_GPIO_DR4_LB_MASK (1 << 29) -#define OMAP4_GPIO_DR5_LB_SHIFT 28 -#define OMAP4_GPIO_DR5_LB_MASK (1 << 28) -#define OMAP4_GPIO_DR6_LB_SHIFT 27 -#define OMAP4_GPIO_DR6_LB_MASK (1 << 27) -#define OMAP4_HSI_DR1_LB_SHIFT 26 -#define OMAP4_HSI_DR1_LB_MASK (1 << 26) -#define OMAP4_HSI_DR2_LB_SHIFT 25 -#define OMAP4_HSI_DR2_LB_MASK (1 << 25) -#define OMAP4_HSI_DR3_LB_SHIFT 24 -#define OMAP4_HSI_DR3_LB_MASK (1 << 24) -#define OMAP4_MCBSP2_DR0_LB_SHIFT 23 -#define OMAP4_MCBSP2_DR0_LB_MASK (1 << 23) -#define OMAP4_MCSPI4_DR0_LB_SHIFT 22 -#define OMAP4_MCSPI4_DR0_LB_MASK (1 << 22) -#define OMAP4_MCSPI4_DR1_LB_SHIFT 21 -#define OMAP4_MCSPI4_DR1_LB_MASK (1 << 21) -#define OMAP4_SLIMBUS2_DR0_LB_SHIFT 18 -#define OMAP4_SLIMBUS2_DR0_LB_MASK (1 << 18) -#define OMAP4_SPI2_DR0_LB_SHIFT 16 -#define OMAP4_SPI2_DR0_LB_MASK (1 << 16) -#define OMAP4_SPI2_DR1_LB_SHIFT 15 -#define OMAP4_SPI2_DR1_LB_MASK (1 << 15) -#define OMAP4_SPI2_DR2_LB_SHIFT 14 -#define OMAP4_SPI2_DR2_LB_MASK (1 << 14) -#define OMAP4_UART2_DR0_LB_SHIFT 13 -#define OMAP4_UART2_DR0_LB_MASK (1 << 13) -#define OMAP4_UART2_DR1_LB_SHIFT 12 -#define OMAP4_UART2_DR1_LB_MASK (1 << 12) -#define OMAP4_UART4_DR0_LB_SHIFT 11 -#define OMAP4_UART4_DR0_LB_MASK (1 << 11) -#define OMAP4_HSI_DR0_LB_SHIFT 10 -#define OMAP4_HSI_DR0_LB_MASK (1 << 10) - -/* CONTROL_USBB_HSIC */ -#define OMAP4_USBB2_DR1_SR_SHIFT 30 -#define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30) -#define OMAP4_USBB2_DR1_I_SHIFT 27 -#define OMAP4_USBB2_DR1_I_MASK (0x7 << 27) -#define OMAP4_USBB1_DR1_SR_SHIFT 25 -#define OMAP4_USBB1_DR1_SR_MASK (0x3 << 25) -#define OMAP4_USBB1_DR1_I_SHIFT 22 -#define OMAP4_USBB1_DR1_I_MASK (0x7 << 22) -#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT 20 -#define OMAP4_USBB1_HSIC_DATA_WD_MASK (0x3 << 20) -#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT 18 -#define OMAP4_USBB1_HSIC_STROBE_WD_MASK (0x3 << 18) -#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT 16 -#define OMAP4_USBB2_HSIC_DATA_WD_MASK (0x3 << 16) -#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT 14 -#define OMAP4_USBB2_HSIC_STROBE_WD_MASK (0x3 << 14) -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 13 -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 13) -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT 11 -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 11) -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 10 -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 10) -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT 8 -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 8) -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 7 -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 7) -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT 5 -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 5) -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 4 -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 4) -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT 2 -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 2) - -/* CONTROL_SLIMBUS */ -#define OMAP4_SLIMBUS1_DR0_MB_SHIFT 30 -#define OMAP4_SLIMBUS1_DR0_MB_MASK (0x3 << 30) -#define OMAP4_SLIMBUS1_DR1_MB_SHIFT 28 -#define OMAP4_SLIMBUS1_DR1_MB_MASK (0x3 << 28) -#define OMAP4_SLIMBUS2_DR0_MB_SHIFT 26 -#define OMAP4_SLIMBUS2_DR0_MB_MASK (0x3 << 26) -#define OMAP4_SLIMBUS2_DR1_MB_SHIFT 24 -#define OMAP4_SLIMBUS2_DR1_MB_MASK (0x3 << 24) -#define OMAP4_SLIMBUS2_DR2_MB_SHIFT 22 -#define OMAP4_SLIMBUS2_DR2_MB_MASK (0x3 << 22) -#define OMAP4_SLIMBUS2_DR3_MB_SHIFT 20 -#define OMAP4_SLIMBUS2_DR3_MB_MASK (0x3 << 20) -#define OMAP4_SLIMBUS1_DR0_LB_SHIFT 19 -#define OMAP4_SLIMBUS1_DR0_LB_MASK (1 << 19) -#define OMAP4_SLIMBUS2_DR1_LB_SHIFT 18 -#define OMAP4_SLIMBUS2_DR1_LB_MASK (1 << 18) - -/* CONTROL_PBIASLITE */ -#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT 31 -#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK (1 << 31) -#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT 30 -#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 30) -#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT 29 -#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK (1 << 29) -#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT 28 -#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK (1 << 28) -#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT 27 -#define OMAP4_USIM_PBIASLITE_VMODE_MASK (1 << 27) -#define OMAP4_MMC1_PWRDNZ_SHIFT 26 -#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26) -#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT 25 -#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK (1 << 25) -#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT 24 -#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 24) -#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT 23 -#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23) -#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT 22 -#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22) -#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT 21 -#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21) -#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT 20 -#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK (1 << 20) - -/* CONTROL_I2C_0 */ -#define OMAP4_I2C4_SDA_GLFENB_SHIFT 31 -#define OMAP4_I2C4_SDA_GLFENB_MASK (1 << 31) -#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT 29 -#define OMAP4_I2C4_SDA_LOAD_BITS_MASK (0x3 << 29) -#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT 28 -#define OMAP4_I2C4_SDA_PULLUPRESX_MASK (1 << 28) -#define OMAP4_I2C3_SDA_GLFENB_SHIFT 27 -#define OMAP4_I2C3_SDA_GLFENB_MASK (1 << 27) -#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT 25 -#define OMAP4_I2C3_SDA_LOAD_BITS_MASK (0x3 << 25) -#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT 24 -#define OMAP4_I2C3_SDA_PULLUPRESX_MASK (1 << 24) -#define OMAP4_I2C2_SDA_GLFENB_SHIFT 23 -#define OMAP4_I2C2_SDA_GLFENB_MASK (1 << 23) -#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT 21 -#define OMAP4_I2C2_SDA_LOAD_BITS_MASK (0x3 << 21) -#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT 20 -#define OMAP4_I2C2_SDA_PULLUPRESX_MASK (1 << 20) -#define OMAP4_I2C1_SDA_GLFENB_SHIFT 19 -#define OMAP4_I2C1_SDA_GLFENB_MASK (1 << 19) -#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT 17 -#define OMAP4_I2C1_SDA_LOAD_BITS_MASK (0x3 << 17) -#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT 16 -#define OMAP4_I2C1_SDA_PULLUPRESX_MASK (1 << 16) -#define OMAP4_I2C4_SCL_GLFENB_SHIFT 15 -#define OMAP4_I2C4_SCL_GLFENB_MASK (1 << 15) -#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT 13 -#define OMAP4_I2C4_SCL_LOAD_BITS_MASK (0x3 << 13) -#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT 12 -#define OMAP4_I2C4_SCL_PULLUPRESX_MASK (1 << 12) -#define OMAP4_I2C3_SCL_GLFENB_SHIFT 11 -#define OMAP4_I2C3_SCL_GLFENB_MASK (1 << 11) -#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT 9 -#define OMAP4_I2C3_SCL_LOAD_BITS_MASK (0x3 << 9) -#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT 8 -#define OMAP4_I2C3_SCL_PULLUPRESX_MASK (1 << 8) -#define OMAP4_I2C2_SCL_GLFENB_SHIFT 7 -#define OMAP4_I2C2_SCL_GLFENB_MASK (1 << 7) -#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT 5 -#define OMAP4_I2C2_SCL_LOAD_BITS_MASK (0x3 << 5) -#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT 4 -#define OMAP4_I2C2_SCL_PULLUPRESX_MASK (1 << 4) -#define OMAP4_I2C1_SCL_GLFENB_SHIFT 3 -#define OMAP4_I2C1_SCL_GLFENB_MASK (1 << 3) -#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT 1 -#define OMAP4_I2C1_SCL_LOAD_BITS_MASK (0x3 << 1) -#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT 0 -#define OMAP4_I2C1_SCL_PULLUPRESX_MASK (1 << 0) - -/* CONTROL_CAMERA_RX */ -#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT 31 -#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK (1 << 31) -#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29 -#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29) -#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24 -#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24) -#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT 22 -#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK (0x3 << 22) -#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21 -#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21) -#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19 -#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19) -#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18 -#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18) -#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16 -#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16) - -/* CONTROL_AVDAC */ -#define OMAP4_AVDAC_ACEN_SHIFT 31 -#define OMAP4_AVDAC_ACEN_MASK (1 << 31) -#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT 30 -#define OMAP4_AVDAC_TVOUTBYPASS_MASK (1 << 30) -#define OMAP4_AVDAC_INPUTINV_SHIFT 29 -#define OMAP4_AVDAC_INPUTINV_MASK (1 << 29) -#define OMAP4_AVDAC_CTL_SHIFT 13 -#define OMAP4_AVDAC_CTL_MASK (0xffff << 13) -#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT 12 -#define OMAP4_AVDAC_CTL_WR_ACK_MASK (1 << 12) - -/* CONTROL_HDMI_TX_PHY */ -#define OMAP4_HDMITXPHY_PADORDER_SHIFT 31 -#define OMAP4_HDMITXPHY_PADORDER_MASK (1 << 31) -#define OMAP4_HDMITXPHY_TXVALID_SHIFT 30 -#define OMAP4_HDMITXPHY_TXVALID_MASK (1 << 30) -#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT 29 -#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK (1 << 29) -#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT 28 -#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK (1 << 28) - -/* CONTROL_MMC2 */ -#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT 31 -#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK (1 << 31) - -/* CONTROL_DSIPHY */ -#define OMAP4_DSI2_LANEENABLE_SHIFT 29 -#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) -#define OMAP4_DSI1_LANEENABLE_SHIFT 24 -#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) -#define OMAP4_DSI1_PIPD_SHIFT 19 -#define OMAP4_DSI1_PIPD_MASK (0x1f << 19) -#define OMAP4_DSI2_PIPD_SHIFT 14 -#define OMAP4_DSI2_PIPD_MASK (0x1f << 14) - -/* CONTROL_MCBSPLP */ -#define OMAP4_ALBCTRLRX_FSX_SHIFT 31 -#define OMAP4_ALBCTRLRX_FSX_MASK (1 << 31) -#define OMAP4_ALBCTRLRX_CLKX_SHIFT 30 -#define OMAP4_ALBCTRLRX_CLKX_MASK (1 << 30) -#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT 29 -#define OMAP4_ABE_MCBSP1_DR_EN_MASK (1 << 29) - -/* CONTROL_USB2PHYCORE */ -#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT 31 -#define OMAP4_USB2PHY_AUTORESUME_EN_MASK (1 << 31) -#define OMAP4_USB2PHY_DISCHGDET_SHIFT 30 -#define OMAP4_USB2PHY_DISCHGDET_MASK (1 << 30) -#define OMAP4_USB2PHY_GPIOMODE_SHIFT 29 -#define OMAP4_USB2PHY_GPIOMODE_MASK (1 << 29) -#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT 28 -#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK (1 << 28) -#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT 27 -#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK (1 << 27) -#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT 26 -#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK (1 << 26) -#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT 25 -#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK (1 << 25) -#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT 24 -#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK (1 << 24) -#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT 21 -#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK (0x7 << 21) -#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT 20 -#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK (1 << 20) -#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT 19 -#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK (1 << 19) -#define OMAP4_USB2PHY_DATADET_SHIFT 18 -#define OMAP4_USB2PHY_DATADET_MASK (1 << 18) -#define OMAP4_USB2PHY_SINKONDP_SHIFT 17 -#define OMAP4_USB2PHY_SINKONDP_MASK (1 << 17) -#define OMAP4_USB2PHY_SRCONDM_SHIFT 16 -#define OMAP4_USB2PHY_SRCONDM_MASK (1 << 16) -#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT 15 -#define OMAP4_USB2PHY_RESTARTCHGDET_MASK (1 << 15) -#define OMAP4_USB2PHY_CHGDETDONE_SHIFT 14 -#define OMAP4_USB2PHY_CHGDETDONE_MASK (1 << 14) -#define OMAP4_USB2PHY_CHGDETECTED_SHIFT 13 -#define OMAP4_USB2PHY_CHGDETECTED_MASK (1 << 13) -#define OMAP4_USB2PHY_MCPCPUEN_SHIFT 12 -#define OMAP4_USB2PHY_MCPCPUEN_MASK (1 << 12) -#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT 11 -#define OMAP4_USB2PHY_MCPCMODEEN_MASK (1 << 11) -#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT 10 -#define OMAP4_USB2PHY_RESETDONEMCLK_MASK (1 << 10) -#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT 9 -#define OMAP4_USB2PHY_UTMIRESETDONE_MASK (1 << 9) -#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT 8 -#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK (1 << 8) -#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT 7 -#define OMAP4_USB2PHY_DATAPOLARITYN_MASK (1 << 7) -#define OMAP4_USBDPLL_FREQLOCK_SHIFT 6 -#define OMAP4_USBDPLL_FREQLOCK_MASK (1 << 6) -#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT 5 -#define OMAP4_USB2PHY_RESETDONETCLK_MASK (1 << 5) - -/* CONTROL_I2C_1 */ -#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT 31 -#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK (1 << 31) -#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT 29 -#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK (0x3 << 29) -#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT 28 -#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28) -#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT 27 -#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK (1 << 27) -#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT 25 -#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK (0x3 << 25) -#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT 24 -#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24) -#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT 23 -#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK (1 << 23) -#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT 22 -#define OMAP4_HDMI_DDC_SDA_NMODE_MASK (1 << 22) -#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT 21 -#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK (1 << 21) -#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT 20 -#define OMAP4_HDMI_DDC_SCL_NMODE_MASK (1 << 20) - -/* CONTROL_MMC1 */ -#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT 31 -#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31) -#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT 30 -#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30) -#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT 29 -#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29) -#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT 28 -#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28) -#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT 27 -#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27) -#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT 26 -#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26) -#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT 25 -#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25) -#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT 24 -#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK (1 << 24) -#define OMAP4_USB_FD_CDEN_SHIFT 23 -#define OMAP4_USB_FD_CDEN_MASK (1 << 23) -#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT 22 -#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK (1 << 22) -#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT 21 -#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK (1 << 21) - -/* CONTROL_HSI */ -#define OMAP4_HSI1_CALLOOP_SEL_SHIFT 31 -#define OMAP4_HSI1_CALLOOP_SEL_MASK (1 << 31) -#define OMAP4_HSI1_CALMUX_SEL_SHIFT 30 -#define OMAP4_HSI1_CALMUX_SEL_MASK (1 << 30) -#define OMAP4_HSI2_CALLOOP_SEL_SHIFT 29 -#define OMAP4_HSI2_CALLOOP_SEL_MASK (1 << 29) -#define OMAP4_HSI2_CALMUX_SEL_SHIFT 28 -#define OMAP4_HSI2_CALMUX_SEL_MASK (1 << 28) - -/* CONTROL_USB */ -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT 31 -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK (1 << 31) -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT 30 -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK (1 << 30) - -/* CONTROL_HDQ */ -#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT 31 -#define OMAP4_HDQ_SIO_PWRDNZ_MASK (1 << 31) - -/* CONTROL_LPDDR2IO1_0 */ -#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT 30 -#define OMAP4_LPDDR2IO1_GR4_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO1_GR4_I_SHIFT 27 -#define OMAP4_LPDDR2IO1_GR4_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT 25 -#define OMAP4_LPDDR2IO1_GR4_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT 22 -#define OMAP4_LPDDR2IO1_GR3_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO1_GR3_I_SHIFT 19 -#define OMAP4_LPDDR2IO1_GR3_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT 17 -#define OMAP4_LPDDR2IO1_GR3_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT 14 -#define OMAP4_LPDDR2IO1_GR2_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO1_GR2_I_SHIFT 11 -#define OMAP4_LPDDR2IO1_GR2_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT 9 -#define OMAP4_LPDDR2IO1_GR2_WD_MASK (0x3 << 9) -#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT 6 -#define OMAP4_LPDDR2IO1_GR1_SR_MASK (0x3 << 6) -#define OMAP4_LPDDR2IO1_GR1_I_SHIFT 3 -#define OMAP4_LPDDR2IO1_GR1_I_MASK (0x7 << 3) -#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT 1 -#define OMAP4_LPDDR2IO1_GR1_WD_MASK (0x3 << 1) - -/* CONTROL_LPDDR2IO1_1 */ -#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT 30 -#define OMAP4_LPDDR2IO1_GR8_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO1_GR8_I_SHIFT 27 -#define OMAP4_LPDDR2IO1_GR8_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT 25 -#define OMAP4_LPDDR2IO1_GR8_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT 22 -#define OMAP4_LPDDR2IO1_GR7_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO1_GR7_I_SHIFT 19 -#define OMAP4_LPDDR2IO1_GR7_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT 17 -#define OMAP4_LPDDR2IO1_GR7_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT 14 -#define OMAP4_LPDDR2IO1_GR6_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO1_GR6_I_SHIFT 11 -#define OMAP4_LPDDR2IO1_GR6_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT 9 -#define OMAP4_LPDDR2IO1_GR6_WD_MASK (0x3 << 9) -#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT 6 -#define OMAP4_LPDDR2IO1_GR5_SR_MASK (0x3 << 6) -#define OMAP4_LPDDR2IO1_GR5_I_SHIFT 3 -#define OMAP4_LPDDR2IO1_GR5_I_MASK (0x7 << 3) -#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT 1 -#define OMAP4_LPDDR2IO1_GR5_WD_MASK (0x3 << 1) - -/* CONTROL_LPDDR2IO1_2 */ -#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT 30 -#define OMAP4_LPDDR2IO1_GR11_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO1_GR11_I_SHIFT 27 -#define OMAP4_LPDDR2IO1_GR11_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT 25 -#define OMAP4_LPDDR2IO1_GR11_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT 22 -#define OMAP4_LPDDR2IO1_GR10_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO1_GR10_I_SHIFT 19 -#define OMAP4_LPDDR2IO1_GR10_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT 17 -#define OMAP4_LPDDR2IO1_GR10_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT 14 -#define OMAP4_LPDDR2IO1_GR9_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO1_GR9_I_SHIFT 11 -#define OMAP4_LPDDR2IO1_GR9_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT 9 -#define OMAP4_LPDDR2IO1_GR9_WD_MASK (0x3 << 9) - -/* CONTROL_LPDDR2IO1_3 */ -#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT 31 -#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK (1 << 31) -#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT 30 -#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK (1 << 30) -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT 29 -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK (1 << 29) -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT 28 -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK (1 << 28) -#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT 27 -#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK (1 << 27) -#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT 26 -#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK (1 << 26) -#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT 25 -#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK (1 << 25) -#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT 24 -#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK (1 << 24) -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT 23 -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK (1 << 23) -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT 22 -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK (1 << 22) -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT 21 -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK (1 << 21) -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT 20 -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK (1 << 20) -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT 19 -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK (1 << 19) -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT 18 -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK (1 << 18) -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT 17 -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK (1 << 17) -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT 16 -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK (1 << 16) -#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT 15 -#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK (1 << 15) -#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT 14 -#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK (1 << 14) -#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT 13 -#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13) -#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12 -#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12) - -/* CONTROL_LPDDR2IO2_0 */ -#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30 -#define OMAP4_LPDDR2IO2_GR4_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO2_GR4_I_SHIFT 27 -#define OMAP4_LPDDR2IO2_GR4_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT 25 -#define OMAP4_LPDDR2IO2_GR4_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT 22 -#define OMAP4_LPDDR2IO2_GR3_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO2_GR3_I_SHIFT 19 -#define OMAP4_LPDDR2IO2_GR3_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT 17 -#define OMAP4_LPDDR2IO2_GR3_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT 14 -#define OMAP4_LPDDR2IO2_GR2_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO2_GR2_I_SHIFT 11 -#define OMAP4_LPDDR2IO2_GR2_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT 9 -#define OMAP4_LPDDR2IO2_GR2_WD_MASK (0x3 << 9) -#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT 6 -#define OMAP4_LPDDR2IO2_GR1_SR_MASK (0x3 << 6) -#define OMAP4_LPDDR2IO2_GR1_I_SHIFT 3 -#define OMAP4_LPDDR2IO2_GR1_I_MASK (0x7 << 3) -#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT 1 -#define OMAP4_LPDDR2IO2_GR1_WD_MASK (0x3 << 1) - -/* CONTROL_LPDDR2IO2_1 */ -#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT 30 -#define OMAP4_LPDDR2IO2_GR8_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO2_GR8_I_SHIFT 27 -#define OMAP4_LPDDR2IO2_GR8_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT 25 -#define OMAP4_LPDDR2IO2_GR8_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT 22 -#define OMAP4_LPDDR2IO2_GR7_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO2_GR7_I_SHIFT 19 -#define OMAP4_LPDDR2IO2_GR7_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT 17 -#define OMAP4_LPDDR2IO2_GR7_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT 14 -#define OMAP4_LPDDR2IO2_GR6_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO2_GR6_I_SHIFT 11 -#define OMAP4_LPDDR2IO2_GR6_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT 9 -#define OMAP4_LPDDR2IO2_GR6_WD_MASK (0x3 << 9) -#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT 6 -#define OMAP4_LPDDR2IO2_GR5_SR_MASK (0x3 << 6) -#define OMAP4_LPDDR2IO2_GR5_I_SHIFT 3 -#define OMAP4_LPDDR2IO2_GR5_I_MASK (0x7 << 3) -#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT 1 -#define OMAP4_LPDDR2IO2_GR5_WD_MASK (0x3 << 1) - -/* CONTROL_LPDDR2IO2_2 */ -#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT 30 -#define OMAP4_LPDDR2IO2_GR11_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO2_GR11_I_SHIFT 27 -#define OMAP4_LPDDR2IO2_GR11_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT 25 -#define OMAP4_LPDDR2IO2_GR11_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT 22 -#define OMAP4_LPDDR2IO2_GR10_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO2_GR10_I_SHIFT 19 -#define OMAP4_LPDDR2IO2_GR10_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT 17 -#define OMAP4_LPDDR2IO2_GR10_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT 14 -#define OMAP4_LPDDR2IO2_GR9_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO2_GR9_I_SHIFT 11 -#define OMAP4_LPDDR2IO2_GR9_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT 9 -#define OMAP4_LPDDR2IO2_GR9_WD_MASK (0x3 << 9) - -/* CONTROL_LPDDR2IO2_3 */ -#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT 31 -#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK (1 << 31) -#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT 30 -#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK (1 << 30) -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT 29 -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK (1 << 29) -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT 28 -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK (1 << 28) -#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT 27 -#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK (1 << 27) -#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT 26 -#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK (1 << 26) -#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT 25 -#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK (1 << 25) -#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT 24 -#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK (1 << 24) -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT 23 -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK (1 << 23) -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT 22 -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK (1 << 22) -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT 21 -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK (1 << 21) -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT 20 -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK (1 << 20) -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT 19 -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK (1 << 19) -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT 18 -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK (1 << 18) -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT 17 -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK (1 << 17) -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT 16 -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK (1 << 16) -#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT 15 -#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK (1 << 15) -#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT 14 -#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK (1 << 14) -#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT 13 -#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK (1 << 13) -#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT 12 -#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK (1 << 12) - -/* CONTROL_BUS_HOLD */ -#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT 31 -#define OMAP4_ABE_DMIC_DIN3_EN_MASK (1 << 31) -#define OMAP4_MCSPI1_CS3_EN_SHIFT 30 -#define OMAP4_MCSPI1_CS3_EN_MASK (1 << 30) - -/* CONTROL_C2C */ -#define OMAP4_MIRROR_MODE_EN_SHIFT 31 -#define OMAP4_MIRROR_MODE_EN_MASK (1 << 31) -#define OMAP4_C2C_SPARE_SHIFT 24 -#define OMAP4_C2C_SPARE_MASK (0x7f << 24) - -/* CORE_CONTROL_SPARE_RW */ -#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT 0 -#define OMAP4_CORE_CONTROL_SPARE_RW_MASK (0xffffffff << 0) - -/* CORE_CONTROL_SPARE_R */ -#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT 0 -#define OMAP4_CORE_CONTROL_SPARE_R_MASK (0xffffffff << 0) - -/* CORE_CONTROL_SPARE_R_C0 */ -#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT 31 -#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK (1 << 31) -#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT 30 -#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK (1 << 30) -#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT 29 -#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK (1 << 29) -#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT 28 -#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK (1 << 28) -#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT 27 -#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK (1 << 27) -#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT 26 -#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK (1 << 26) -#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT 25 -#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK (1 << 25) -#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT 24 -#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK (1 << 24) - -/* CONTROL_EFUSE_1 */ -#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT 24 -#define OMAP4_AVDAC_TRIM_BYTE3_MASK (0x7f << 24) -#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT 16 -#define OMAP4_AVDAC_TRIM_BYTE2_MASK (0xff << 16) -#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT 8 -#define OMAP4_AVDAC_TRIM_BYTE1_MASK (0xff << 8) -#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT 0 -#define OMAP4_AVDAC_TRIM_BYTE0_MASK (0xff << 0) - -/* CONTROL_EFUSE_2 */ -#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT 31 -#define OMAP4_EFUSE_SMART2TEST_P0_MASK (1 << 31) -#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT 30 -#define OMAP4_EFUSE_SMART2TEST_P1_MASK (1 << 30) -#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT 29 -#define OMAP4_EFUSE_SMART2TEST_P2_MASK (1 << 29) -#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT 28 -#define OMAP4_EFUSE_SMART2TEST_P3_MASK (1 << 28) -#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT 27 -#define OMAP4_EFUSE_SMART2TEST_N0_MASK (1 << 27) -#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT 26 -#define OMAP4_EFUSE_SMART2TEST_N1_MASK (1 << 26) -#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT 25 -#define OMAP4_EFUSE_SMART2TEST_N2_MASK (1 << 25) -#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT 24 -#define OMAP4_EFUSE_SMART2TEST_N3_MASK (1 << 24) -#define OMAP4_LPDDR2_PTV_N1_SHIFT 23 -#define OMAP4_LPDDR2_PTV_N1_MASK (1 << 23) -#define OMAP4_LPDDR2_PTV_N2_SHIFT 22 -#define OMAP4_LPDDR2_PTV_N2_MASK (1 << 22) -#define OMAP4_LPDDR2_PTV_N3_SHIFT 21 -#define OMAP4_LPDDR2_PTV_N3_MASK (1 << 21) -#define OMAP4_LPDDR2_PTV_N4_SHIFT 20 -#define OMAP4_LPDDR2_PTV_N4_MASK (1 << 20) -#define OMAP4_LPDDR2_PTV_N5_SHIFT 19 -#define OMAP4_LPDDR2_PTV_N5_MASK (1 << 19) -#define OMAP4_LPDDR2_PTV_P1_SHIFT 18 -#define OMAP4_LPDDR2_PTV_P1_MASK (1 << 18) -#define OMAP4_LPDDR2_PTV_P2_SHIFT 17 -#define OMAP4_LPDDR2_PTV_P2_MASK (1 << 17) -#define OMAP4_LPDDR2_PTV_P3_SHIFT 16 -#define OMAP4_LPDDR2_PTV_P3_MASK (1 << 16) -#define OMAP4_LPDDR2_PTV_P4_SHIFT 15 -#define OMAP4_LPDDR2_PTV_P4_MASK (1 << 15) -#define OMAP4_LPDDR2_PTV_P5_SHIFT 14 -#define OMAP4_LPDDR2_PTV_P5_MASK (1 << 14) - -/* CONTROL_EFUSE_3 */ -#define OMAP4_STD_FUSE_SPARE_1_SHIFT 24 -#define OMAP4_STD_FUSE_SPARE_1_MASK (0xff << 24) -#define OMAP4_STD_FUSE_SPARE_2_SHIFT 16 -#define OMAP4_STD_FUSE_SPARE_2_MASK (0xff << 16) -#define OMAP4_STD_FUSE_SPARE_3_SHIFT 8 -#define OMAP4_STD_FUSE_SPARE_3_MASK (0xff << 8) -#define OMAP4_STD_FUSE_SPARE_4_SHIFT 0 -#define OMAP4_STD_FUSE_SPARE_4_MASK (0xff << 0) - -/* CONTROL_EFUSE_4 */ -#define OMAP4_STD_FUSE_SPARE_5_SHIFT 24 -#define OMAP4_STD_FUSE_SPARE_5_MASK (0xff << 24) -#define OMAP4_STD_FUSE_SPARE_6_SHIFT 16 -#define OMAP4_STD_FUSE_SPARE_6_MASK (0xff << 16) -#define OMAP4_STD_FUSE_SPARE_7_SHIFT 8 -#define OMAP4_STD_FUSE_SPARE_7_MASK (0xff << 8) -#define OMAP4_STD_FUSE_SPARE_8_SHIFT 0 -#define OMAP4_STD_FUSE_SPARE_8_MASK (0xff << 0) - -#endif diff --git a/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h deleted file mode 100644 index 17c9b37042c0..000000000000 --- a/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * - * Benoit Cousson (b-cousson@ti.com) - * Santosh Shilimkar (santosh.shilimkar@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H - - -/* Base address */ -#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000 - -/* Registers offset */ -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000 -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004 -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010 -#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614 -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618 -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c - -/* Registers shifts and masks */ - -/* IP_REVISION */ -#define OMAP4_IP_REV_SCHEME_SHIFT 30 -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) -#define OMAP4_IP_REV_FUNC_SHIFT 16 -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) -#define OMAP4_IP_REV_RTL_SHIFT 11 -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) -#define OMAP4_IP_REV_MAJOR_SHIFT 8 -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) -#define OMAP4_IP_REV_CUSTOM_SHIFT 6 -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) -#define OMAP4_IP_REV_MINOR_SHIFT 0 -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) - -/* IP_HWINFO */ -#define OMAP4_IP_HWINFO_SHIFT 0 -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) - -/* IP_SYSCONFIG */ -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) - -/* PADCONF_WAKEUPEVENT_0 */ -#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* CONTROL_SMART1NOPMIO_PADCONF_0 */ -#define OMAP4_FREF_DR0_SC_SHIFT 30 -#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30) -#define OMAP4_FREF_DR1_SC_SHIFT 28 -#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28) -#define OMAP4_FREF_DR4_SC_SHIFT 26 -#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26) -#define OMAP4_FREF_DR5_SC_SHIFT 24 -#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24) -#define OMAP4_FREF_DR6_SC_SHIFT 22 -#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22) -#define OMAP4_FREF_DR7_SC_SHIFT 20 -#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20) -#define OMAP4_GPIO_DR7_SC_SHIFT 18 -#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18) -#define OMAP4_DPM_DR0_SC_SHIFT 14 -#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14) -#define OMAP4_SIM_DR0_SC_SHIFT 12 -#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12) - -/* CONTROL_SMART1NOPMIO_PADCONF_1 */ -#define OMAP4_FREF_DR0_LB_SHIFT 30 -#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30) -#define OMAP4_FREF_DR1_LB_SHIFT 28 -#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28) -#define OMAP4_FREF_DR4_LB_SHIFT 26 -#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26) -#define OMAP4_FREF_DR5_LB_SHIFT 24 -#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24) -#define OMAP4_FREF_DR6_LB_SHIFT 22 -#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22) -#define OMAP4_FREF_DR7_LB_SHIFT 20 -#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20) -#define OMAP4_GPIO_DR7_LB_SHIFT 18 -#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18) -#define OMAP4_DPM_DR0_LB_SHIFT 14 -#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14) -#define OMAP4_SIM_DR0_LB_SHIFT 12 -#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12) - -/* CONTROL_PADCONF_MODE */ -#define OMAP4_VDDS_DV_FREF_SHIFT 31 -#define OMAP4_VDDS_DV_FREF_MASK (1 << 31) -#define OMAP4_VDDS_DV_BANK2_SHIFT 30 -#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30) - -/* CONTROL_XTAL_OSCILLATOR */ -#define OMAP4_OSCILLATOR_BOOST_SHIFT 31 -#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31) -#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30 -#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30) - -/* CONTROL_USIMIO */ -#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31 -#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31) -#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29 -#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29) -#define OMAP4_USIM_PWRDNZ_SHIFT 28 -#define OMAP4_USIM_PWRDNZ_MASK (1 << 28) - -/* CONTROL_I2C_2 */ -#define OMAP4_SR_SDA_GLFENB_SHIFT 31 -#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31) -#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29 -#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29) -#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28 -#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28) -#define OMAP4_SR_SCL_GLFENB_SHIFT 27 -#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27) -#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25 -#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25) -#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24 -#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24) - -/* CONTROL_JTAG */ -#define OMAP4_JTAG_NTRST_EN_SHIFT 31 -#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31) -#define OMAP4_JTAG_TCK_EN_SHIFT 30 -#define OMAP4_JTAG_TCK_EN_MASK (1 << 30) -#define OMAP4_JTAG_RTCK_EN_SHIFT 29 -#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29) -#define OMAP4_JTAG_TDI_EN_SHIFT 28 -#define OMAP4_JTAG_TDI_EN_MASK (1 << 28) -#define OMAP4_JTAG_TDO_EN_SHIFT 27 -#define OMAP4_JTAG_TDO_EN_MASK (1 << 27) - -/* CONTROL_SYS */ -#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31 -#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31) - -/* WKUP_CONTROL_SPARE_RW */ -#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0 -#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0) - -/* WKUP_CONTROL_SPARE_R */ -#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0 -#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0) - -/* WKUP_CONTROL_SPARE_R_C0 */ -#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31 -#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31) -#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30 -#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30) -#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29 -#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29) -#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28 -#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28) -#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27 -#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27) -#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26 -#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26) -#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25 -#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25) -#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24 -#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24) - -#endif diff --git a/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h deleted file mode 100644 index a0af9baec3f7..000000000000 --- a/trunk/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * OMAP44xx CTRL_MODULE_WKUP registers and bitfields - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * - * Benoit Cousson (b-cousson@ti.com) - * Santosh Shilimkar (santosh.shilimkar@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H - - -/* Base address */ -#define OMAP4_CTRL_MODULE_WKUP 0x4a30c000 - -/* Registers offset */ -#define OMAP4_CTRL_MODULE_WKUP_IP_REVISION 0x0000 -#define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO 0x0004 -#define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG 0x0010 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0 0x0460 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1 0x0464 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2 0x0468 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3 0x046c -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4 0x0470 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5 0x0474 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6 0x0478 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7 0x047c -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8 0x0480 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9 0x0484 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10 0x0488 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11 0x048c -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12 0x0490 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13 0x0494 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14 0x0498 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15 0x049c -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16 0x04a0 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17 0x04a4 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18 0x04a8 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19 0x04ac -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20 0x04b0 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21 0x04b4 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22 0x04b8 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23 0x04bc -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24 0x04c0 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25 0x04c4 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26 0x04c8 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27 0x04cc -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28 0x04d0 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29 0x04d4 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30 0x04d8 -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31 0x04dc - -/* Registers shifts and masks */ - -/* IP_REVISION */ -#define OMAP4_IP_REV_SCHEME_SHIFT 30 -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) -#define OMAP4_IP_REV_FUNC_SHIFT 16 -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) -#define OMAP4_IP_REV_RTL_SHIFT 11 -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) -#define OMAP4_IP_REV_MAJOR_SHIFT 8 -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) -#define OMAP4_IP_REV_CUSTOM_SHIFT 6 -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) -#define OMAP4_IP_REV_MINOR_SHIFT 0 -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) - -/* IP_HWINFO */ -#define OMAP4_IP_HWINFO_SHIFT 0 -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) - -/* IP_SYSCONFIG */ -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) - -/* CONF_DEBUG_SEL_TST_0 */ -#define OMAP4_WKUP_MODE_SHIFT 0 -#define OMAP4_WKUP_MODE_MASK (1 << 0) - -#endif diff --git a/trunk/arch/arm/mach-omap2/io.c b/trunk/arch/arm/mach-omap2/io.c index 40562ddd3ee4..b9ea70bce563 100644 --- a/trunk/arch/arm/mach-omap2/io.c +++ b/trunk/arch/arm/mach-omap2/io.c @@ -36,7 +36,6 @@ #include "clock2xxx.h" #include "clock3xxx.h" #include "clock44xx.h" -#include "io.h" #include #include @@ -324,9 +323,6 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, omap2430_hwmod_init(); else if (cpu_is_omap34xx()) omap3xxx_hwmod_init(); - else if (cpu_is_omap44xx()) - omap44xx_hwmod_init(); - /* The OPP tables have to be registered before a clk init */ omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); @@ -346,7 +342,9 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, #ifndef CONFIG_PM_RUNTIME skip_setup_idle = 1; #endif - omap_hwmod_late_init(skip_setup_idle); + if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */ + omap_hwmod_late_init(skip_setup_idle); + if (cpu_is_omap24xx() || cpu_is_omap34xx()) { omap2_sdrc_init(sdrc_cs0, sdrc_cs1); _omap2_init_reprogram_sdrc(); diff --git a/trunk/arch/arm/mach-omap2/io.h b/trunk/arch/arm/mach-omap2/io.h deleted file mode 100644 index fd230c6cded5..000000000000 --- a/trunk/arch/arm/mach-omap2/io.h +++ /dev/null @@ -1,7 +0,0 @@ - -#ifndef __MACH_OMAP2_IO_H__ -#define __MACH_OMAP2_IO_H__ - -extern int __init omap_sram_init(void); - -#endif /* __MACH_OMAP2_IO_H__ */ diff --git a/trunk/arch/arm/mach-omap2/irq.c b/trunk/arch/arm/mach-omap2/irq.c index 32eeabe9d2ab..26aeef560aa3 100644 --- a/trunk/arch/arm/mach-omap2/irq.c +++ b/trunk/arch/arm/mach-omap2/irq.c @@ -47,6 +47,7 @@ static struct omap_irq_bank { } __attribute__ ((aligned(4))) irq_banks[] = { { /* MPU INTC */ + .base_reg = 0, .nr_irqs = 96, }, }; diff --git a/trunk/arch/arm/mach-omap2/mailbox.c b/trunk/arch/arm/mach-omap2/mailbox.c index 40ddecab93a9..42dbfa46e656 100644 --- a/trunk/arch/arm/mach-omap2/mailbox.c +++ b/trunk/arch/arm/mach-omap2/mailbox.c @@ -181,7 +181,7 @@ static int omap2_mbox_fifo_full(struct omap_mbox *mbox) static void omap2_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { - struct omap_mbox2_priv *p = mbox->priv; + struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; l = mbox_read_reg(p->irqenable); @@ -192,7 +192,7 @@ static void omap2_mbox_enable_irq(struct omap_mbox *mbox, static void omap2_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { - struct omap_mbox2_priv *p = mbox->priv; + struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; l = mbox_read_reg(p->irqdisable); l &= ~bit; @@ -202,7 +202,7 @@ static void omap2_mbox_disable_irq(struct omap_mbox *mbox, static void omap2_mbox_ack_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { - struct omap_mbox2_priv *p = mbox->priv; + struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; mbox_write_reg(bit, p->irqstatus); @@ -214,7 +214,7 @@ static void omap2_mbox_ack_irq(struct omap_mbox *mbox, static int omap2_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { - struct omap_mbox2_priv *p = mbox->priv; + struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; u32 enable = mbox_read_reg(p->irqenable); u32 status = mbox_read_reg(p->irqstatus); diff --git a/trunk/arch/arm/mach-omap2/mcbsp.c b/trunk/arch/arm/mach-omap2/mcbsp.c index f9c9df5b5ff1..467aae245781 100644 --- a/trunk/arch/arm/mach-omap2/mcbsp.c +++ b/trunk/arch/arm/mach-omap2/mcbsp.c @@ -23,86 +23,29 @@ #include #include -#include "control.h" +#include "mux.h" - -/* McBSP internal signal muxing functions */ - -void omap2_mcbsp1_mux_clkr_src(u8 mux) +static void omap2_mcbsp2_mux_setup(void) { - u32 v; - - v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); - if (mux == CLKR_SRC_CLKR) - v &= ~OMAP2_MCBSP1_CLKR_MASK; - else if (mux == CLKR_SRC_CLKX) - v |= OMAP2_MCBSP1_CLKR_MASK; - omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); + omap_mux_init_signal("eac_ac_sclk.mcbsp2_clkx", OMAP_PULL_ENA); + omap_mux_init_signal("eac_ac_fs.mcbsp2_fsx", OMAP_PULL_ENA); + omap_mux_init_signal("eac_ac_din.mcbsp2_dr", OMAP_PULL_ENA); + omap_mux_init_signal("eac_ac_dout.mcbsp2_dx", OMAP_PULL_ENA); + omap_mux_init_gpio(117, OMAP_PULL_ENA); + /* + * TODO: Need to add MUX settings for OMAP 2430 SDP + */ } -EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src); -void omap2_mcbsp1_mux_fsr_src(u8 mux) +static void omap2_mcbsp_request(unsigned int id) { - u32 v; - - v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); - if (mux == FSR_SRC_FSR) - v &= ~OMAP2_MCBSP1_FSR_MASK; - else if (mux == FSR_SRC_FSX) - v |= OMAP2_MCBSP1_FSR_MASK; - omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); + if (cpu_is_omap2420() && (id == OMAP_MCBSP2)) + omap2_mcbsp2_mux_setup(); } -EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src); - -/* McBSP CLKS source switching function */ -int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id) -{ - struct omap_mcbsp *mcbsp; - struct clk *fck_src; - char *fck_src_name; - int r; - - if (!omap_mcbsp_check_valid_id(id)) { - pr_err("%s: Invalid id (%d)\n", __func__, id + 1); - return -EINVAL; - } - mcbsp = id_to_mcbsp_ptr(id); - - if (fck_src_id == MCBSP_CLKS_PAD_SRC) - fck_src_name = "pad_fck"; - else if (fck_src_id == MCBSP_CLKS_PRCM_SRC) - fck_src_name = "prcm_fck"; - else - return -EINVAL; - - fck_src = clk_get(mcbsp->dev, fck_src_name); - if (IS_ERR_OR_NULL(fck_src)) { - pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks", - fck_src_name); - return -EINVAL; - } - - clk_disable(mcbsp->fclk); - - r = clk_set_parent(mcbsp->fclk, fck_src); - if (IS_ERR_VALUE(r)) { - pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n", - "clks", fck_src_name); - clk_put(fck_src); - return -EINVAL; - } - - clk_enable(mcbsp->fclk); - - clk_put(fck_src); - - return 0; -} -EXPORT_SYMBOL(omap2_mcbsp_set_clks_src); - - -/* Platform data */ +static struct omap_mcbsp_ops omap2_mcbsp_ops = { + .request = omap2_mcbsp_request, +}; #ifdef CONFIG_ARCH_OMAP2420 static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { @@ -112,6 +55,7 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, + .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP24XX_MCBSP2_BASE, @@ -119,6 +63,7 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, + .ops = &omap2_mcbsp_ops, }, }; #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) @@ -137,6 +82,7 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, + .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP24XX_MCBSP2_BASE, @@ -144,6 +90,7 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, + .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP2430_MCBSP3_BASE, @@ -151,6 +98,7 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, .rx_irq = INT_24XX_MCBSP3_IRQ_RX, .tx_irq = INT_24XX_MCBSP3_IRQ_TX, + .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP2430_MCBSP4_BASE, @@ -158,6 +106,7 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, .rx_irq = INT_24XX_MCBSP4_IRQ_RX, .tx_irq = INT_24XX_MCBSP4_IRQ_TX, + .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP2430_MCBSP5_BASE, @@ -165,6 +114,7 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, .rx_irq = INT_24XX_MCBSP5_IRQ_RX, .tx_irq = INT_24XX_MCBSP5_IRQ_TX, + .ops = &omap2_mcbsp_ops, }, }; #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) @@ -183,6 +133,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, + .ops = &omap2_mcbsp_ops, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { @@ -192,6 +143,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, + .ops = &omap2_mcbsp_ops, .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ }, { @@ -201,6 +153,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, .rx_irq = INT_24XX_MCBSP3_IRQ_RX, .tx_irq = INT_24XX_MCBSP3_IRQ_TX, + .ops = &omap2_mcbsp_ops, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { @@ -209,6 +162,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, .rx_irq = INT_24XX_MCBSP4_IRQ_RX, .tx_irq = INT_24XX_MCBSP4_IRQ_TX, + .ops = &omap2_mcbsp_ops, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { @@ -217,6 +171,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, .rx_irq = INT_24XX_MCBSP5_IRQ_RX, .tx_irq = INT_24XX_MCBSP5_IRQ_TX, + .ops = &omap2_mcbsp_ops, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, }; @@ -234,24 +189,28 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, .tx_irq = OMAP44XX_IRQ_MCBSP1, + .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP2_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, .tx_irq = OMAP44XX_IRQ_MCBSP2, + .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP3_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, .tx_irq = OMAP44XX_IRQ_MCBSP3, + .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP4_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, .tx_irq = OMAP44XX_IRQ_MCBSP4, + .ops = &omap2_mcbsp_ops, }, }; #define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) diff --git a/trunk/arch/arm/mach-omap2/mux.c b/trunk/arch/arm/mach-omap2/mux.c index 074536ae401f..ab403b2ed26b 100644 --- a/trunk/arch/arm/mach-omap2/mux.c +++ b/trunk/arch/arm/mach-omap2/mux.c @@ -23,11 +23,12 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * */ -#include +#include #include #include -#include #include +#include +#include #include #include #include @@ -35,7 +36,8 @@ #include -#include "control.h" +#include + #include "mux.h" #define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */ @@ -85,7 +87,7 @@ static char *omap_mux_options; int __init omap_mux_init_gpio(int gpio, int val) { struct omap_mux_entry *e; - struct omap_mux *gpio_mux = NULL; + struct omap_mux *gpio_mux; u16 old_mode; u16 mux_mode; int found = 0; @@ -125,16 +127,17 @@ int __init omap_mux_init_gpio(int gpio, int val) return 0; } -int __init omap_mux_init_signal(const char *muxname, int val) +int __init omap_mux_init_signal(char *muxname, int val) { struct omap_mux_entry *e; - const char *mode_name; - int found = 0, mode0_len = 0; + char *m0_name = NULL, *mode_name = NULL; + int found = 0; mode_name = strchr(muxname, '.'); if (mode_name) { - mode0_len = strlen(muxname) - strlen(mode_name); + *mode_name = '\0'; mode_name++; + m0_name = muxname; } else { mode_name = muxname; } @@ -144,11 +147,9 @@ int __init omap_mux_init_signal(const char *muxname, int val) char *m0_entry = m->muxnames[0]; int i; - /* First check for full name in mode0.muxmode format */ - if (mode0_len && strncmp(muxname, m0_entry, mode0_len)) + if (m0_name && strcmp(m0_name, m0_entry)) continue; - /* Then check for muxmode only */ for (i = 0; i < OMAP_MUX_NR_MODES; i++) { char *mode_cur = m->muxnames[i]; diff --git a/trunk/arch/arm/mach-omap2/mux.h b/trunk/arch/arm/mach-omap2/mux.h index 350c04f27383..a8e040c2c7e9 100644 --- a/trunk/arch/arm/mach-omap2/mux.h +++ b/trunk/arch/arm/mach-omap2/mux.h @@ -120,7 +120,7 @@ int omap_mux_init_gpio(int gpio, int val); * @muxname: Mux name in mode0_name.signal_name format * @val: Options for the mux register value */ -int omap_mux_init_signal(const char *muxname, int val); +int omap_mux_init_signal(char *muxname, int val); #else diff --git a/trunk/arch/arm/mach-omap2/mux2420.c b/trunk/arch/arm/mach-omap2/mux2420.c index 414af5434456..fdb04a7eb8aa 100644 --- a/trunk/arch/arm/mach-omap2/mux2420.c +++ b/trunk/arch/arm/mach-omap2/mux2420.c @@ -507,7 +507,7 @@ static struct omap_mux __initdata omap2420_muxmodes[] = { * Balls for 447-pin POP package */ #ifdef CONFIG_DEBUG_FS -static struct omap_ball __initdata omap2420_pop_ball[] = { +struct omap_ball __initdata omap2420_pop_ball[] = { _OMAP2420_BALLENTRY(CAM_D0, "y4", NULL), _OMAP2420_BALLENTRY(CAM_D1, "y3", NULL), _OMAP2420_BALLENTRY(CAM_D2, "u7", NULL), diff --git a/trunk/arch/arm/mach-omap2/mux2430.c b/trunk/arch/arm/mach-omap2/mux2430.c index 84d2c5a7ecd7..7dcaaa8af32a 100644 --- a/trunk/arch/arm/mach-omap2/mux2430.c +++ b/trunk/arch/arm/mach-omap2/mux2430.c @@ -586,7 +586,7 @@ static struct omap_mux __initdata omap2430_muxmodes[] = { * 447-pin s-PBGA Package, 0.00mm Ball Pitch (Bottom) */ #ifdef CONFIG_DEBUG_FS -static struct omap_ball __initdata omap2430_pop_ball[] = { +struct omap_ball __initdata omap2430_pop_ball[] = { _OMAP2430_BALLENTRY(CAM_D0, "t8", NULL), _OMAP2430_BALLENTRY(CAM_D1, "t4", NULL), _OMAP2430_BALLENTRY(CAM_D10, "r4", NULL), diff --git a/trunk/arch/arm/mach-omap2/mux34xx.c b/trunk/arch/arm/mach-omap2/mux34xx.c index 574e54ea3ab7..f64d7eea3451 100644 --- a/trunk/arch/arm/mach-omap2/mux34xx.c +++ b/trunk/arch/arm/mach-omap2/mux34xx.c @@ -931,7 +931,7 @@ struct omap_ball __initdata omap3_cbc_ball[] = { * Signals different on CUS package compared to superset */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS) -static struct omap_mux __initdata omap3_cus_subset[] = { +struct omap_mux __initdata omap3_cus_subset[] = { _OMAP3_MUXENTRY(CAM_D10, 109, "cam_d10", NULL, NULL, NULL, "gpio_109", NULL, NULL, "safe_mode"), @@ -1077,7 +1077,7 @@ static struct omap_mux __initdata omap3_cus_subset[] = { */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ && defined(CONFIG_OMAP_PACKAGE_CUS) -static struct omap_ball __initdata omap3_cus_ball[] = { +struct omap_ball __initdata omap3_cus_ball[] = { _OMAP3_BALLENTRY(CAM_D0, "ab18", NULL), _OMAP3_BALLENTRY(CAM_D1, "ac18", NULL), _OMAP3_BALLENTRY(CAM_D10, "f21", NULL), @@ -1269,7 +1269,7 @@ static struct omap_ball __initdata omap3_cus_ball[] = { * Signals different on CBB package comapared to superset */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB) -static struct omap_mux __initdata omap3_cbb_subset[] = { +struct omap_mux __initdata omap3_cbb_subset[] = { _OMAP3_MUXENTRY(CAM_D10, 109, "cam_d10", NULL, NULL, NULL, "gpio_109", NULL, NULL, "safe_mode"), @@ -1390,7 +1390,7 @@ static struct omap_mux __initdata omap3_cbb_subset[] = { */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ && defined(CONFIG_OMAP_PACKAGE_CBB) -static struct omap_ball __initdata omap3_cbb_ball[] = { +struct omap_ball __initdata omap3_cbb_ball[] = { _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL), _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL), _OMAP3_BALLENTRY(CAM_D10, "b25", NULL), @@ -1600,7 +1600,7 @@ static struct omap_ball __initdata omap3_cbb_ball[] = { * Signals different on 36XX CBP package comapared to 34XX CBC package */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP) -static struct omap_mux __initdata omap36xx_cbp_subset[] = { +struct omap_mux __initdata omap36xx_cbp_subset[] = { _OMAP3_MUXENTRY(CAM_D0, 99, "cam_d0", NULL, "csi2_dx2", NULL, "gpio_99", NULL, NULL, "safe_mode"), @@ -1818,7 +1818,7 @@ static struct omap_mux __initdata omap36xx_cbp_subset[] = { */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ && defined (CONFIG_OMAP_PACKAGE_CBP) -static struct omap_ball __initdata omap36xx_cbp_ball[] = { +struct omap_ball __initdata omap36xx_cbp_ball[] = { _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL), _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL), _OMAP3_BALLENTRY(CAM_D10, "b25", NULL), diff --git a/trunk/arch/arm/mach-omap2/omap4-common.c b/trunk/arch/arm/mach-omap2/omap4-common.c index 923f9f5f91ce..13dc9794dcc2 100644 --- a/trunk/arch/arm/mach-omap2/omap4-common.c +++ b/trunk/arch/arm/mach-omap2/omap4-common.c @@ -61,14 +61,10 @@ static int __init omap_l2_cache_init(void) omap_smc1(0x102, 0x1); /* - * 16-way associativity, parity disabled - * Way size - 32KB (es1.0) - * Way size - 64KB (es2.0 +) + * 32KB way size, 16-way associativity, + * parity disabled */ - if (omap_rev() == OMAP4430_REV_ES1_0) - l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); - else - l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff); + l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); return 0; } diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod.c b/trunk/arch/arm/mach-omap2/omap_hwmod.c index 5a30658444d0..cb911d7d1a3c 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod.c @@ -13,102 +13,10 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Introduction - * ------------ - * One way to view an OMAP SoC is as a collection of largely unrelated - * IP blocks connected by interconnects. The IP blocks include - * devices such as ARM processors, audio serial interfaces, UARTs, - * etc. Some of these devices, like the DSP, are created by TI; - * others, like the SGX, largely originate from external vendors. In - * TI's documentation, on-chip devices are referred to as "OMAP - * modules." Some of these IP blocks are identical across several - * OMAP versions. Others are revised frequently. - * - * These OMAP modules are tied together by various interconnects. - * Most of the address and data flow between modules is via OCP-based - * interconnects such as the L3 and L4 buses; but there are other - * interconnects that distribute the hardware clock tree, handle idle - * and reset signaling, supply power, and connect the modules to - * various pads or balls on the OMAP package. - * - * OMAP hwmod provides a consistent way to describe the on-chip - * hardware blocks and their integration into the rest of the chip. - * This description can be automatically generated from the TI - * hardware database. OMAP hwmod provides a standard, consistent API - * to reset, enable, idle, and disable these hardware blocks. And - * hwmod provides a way for other core code, such as the Linux device - * code or the OMAP power management and address space mapping code, - * to query the hardware database. - * - * Using hwmod - * ----------- - * Drivers won't call hwmod functions directly. That is done by the - * omap_device code, and in rare occasions, by custom integration code - * in arch/arm/ *omap*. The omap_device code includes functions to - * build a struct platform_device using omap_hwmod data, and that is - * currently how hwmod data is communicated to drivers and to the - * Linux driver model. Most drivers will call omap_hwmod functions only - * indirectly, via pm_runtime*() functions. - * - * From a layering perspective, here is where the OMAP hwmod code - * fits into the kernel software stack: - * - * +-------------------------------+ - * | Device driver code | - * | (e.g., drivers/) | - * +-------------------------------+ - * | Linux driver model | - * | (platform_device / | - * | platform_driver data/code) | - * +-------------------------------+ - * | OMAP core-driver integration | - * |(arch/arm/mach-omap2/devices.c)| - * +-------------------------------+ - * | omap_device code | - * | (../plat-omap/omap_device.c) | - * +-------------------------------+ - * ----> | omap_hwmod code/data | <----- - * | (../mach-omap2/omap_hwmod*) | - * +-------------------------------+ - * | OMAP clock/PRCM/register fns | - * | (__raw_{read,write}l, clk*) | - * +-------------------------------+ - * - * Device drivers should not contain any OMAP-specific code or data in - * them. They should only contain code to operate the IP block that - * the driver is responsible for. This is because these IP blocks can - * also appear in other SoCs, either from TI (such as DaVinci) or from - * other manufacturers; and drivers should be reusable across other - * platforms. - * - * The OMAP hwmod code also will attempt to reset and idle all on-chip - * devices upon boot. The goal here is for the kernel to be - * completely self-reliant and independent from bootloaders. This is - * to ensure a repeatable configuration, both to ensure consistent - * runtime behavior, and to make it easier for others to reproduce - * bugs. - * - * OMAP module activity states - * --------------------------- - * The hwmod code considers modules to be in one of several activity - * states. IP blocks start out in an UNKNOWN state, then once they - * are registered via the hwmod code, proceed to the REGISTERED state. - * Once their clock names are resolved to clock pointers, the module - * enters the CLKS_INITED state; and finally, once the module has been - * reset and the integration registers programmed, the INITIALIZED state - * is entered. The hwmod code will then place the module into either - * the IDLE state to save power, or in the case of a critical system - * module, the ENABLED state. - * - * OMAP core integration code can then call omap_hwmod*() functions - * directly to move the module between the IDLE, ENABLED, and DISABLED - * states, as needed. This is done during both the PM idle loop, and - * in the OMAP core integration code's implementation of the PM runtime - * functions. - * - * References - * ---------- - * This is a partial list. + * This code manages "OMAP modules" (on-chip devices) and their + * integration with Linux device driver and bus code. + * + * References: * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) @@ -142,13 +50,11 @@ #include #include #include -#include #include "cm.h" -#include "prm.h" -/* Maximum microseconds to wait for OMAP module to softreset */ -#define MAX_MODULE_SOFTRESET_WAIT 10000 +/* Maximum microseconds to wait for OMAP module to reset */ +#define MAX_MODULE_RESET_WAIT 10000 /* Name of the OMAP hwmod for the MPU */ #define MPU_INITIATOR_NAME "mpu" @@ -184,7 +90,7 @@ static int _update_sysc_cache(struct omap_hwmod *oh) /* XXX ensure module interface clock is up */ - oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); + oh->_sysc_cache = omap_hwmod_readl(oh, oh->class->sysc->sysc_offs); if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; @@ -211,7 +117,7 @@ static void _write_sysconfig(u32 v, struct omap_hwmod *oh) if (oh->_sysc_cache != v) { oh->_sysc_cache = v; - omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); + omap_hwmod_writel(v, oh, oh->class->sysc->sysc_offs); } } @@ -638,36 +544,6 @@ static int _disable_clocks(struct omap_hwmod *oh) return 0; } -static void _enable_optional_clocks(struct omap_hwmod *oh) -{ - struct omap_hwmod_opt_clk *oc; - int i; - - pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); - - for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) - if (oc->_clk) { - pr_debug("omap_hwmod: enable %s:%s\n", oc->role, - oc->_clk->name); - clk_enable(oc->_clk); - } -} - -static void _disable_optional_clocks(struct omap_hwmod *oh) -{ - struct omap_hwmod_opt_clk *oc; - int i; - - pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); - - for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) - if (oc->_clk) { - pr_debug("omap_hwmod: disable %s:%s\n", oc->role, - oc->_clk->name); - clk_disable(oc->_clk); - } -} - /** * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use * @oh: struct omap_hwmod * @@ -746,7 +622,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) } /** - * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG + * _sysc_enable - try to bring a module out of idle via OCP_SYSCONFIG * @oh: struct omap_hwmod * * * If module is marked as SWSUP_SIDLE, force the module out of slave @@ -754,7 +630,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) * as SWSUP_MSUSPEND, force the module out of master standby; * otherwise, configure it for smart-standby. No return value. */ -static void _enable_sysc(struct omap_hwmod *oh) +static void _sysc_enable(struct omap_hwmod *oh) { u8 idlemode, sf; u32 v; @@ -777,6 +653,14 @@ static void _enable_sysc(struct omap_hwmod *oh) _set_master_standbymode(oh, idlemode, &v); } + if (sf & SYSC_HAS_AUTOIDLE) { + idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? + 0 : 1; + _set_module_autoidle(oh, idlemode, &v); + } + + /* XXX OCP ENAWAKEUP bit? */ + /* * XXX The clock framework should handle this, by * calling into this code. But this must wait until the @@ -787,25 +671,10 @@ static void _enable_sysc(struct omap_hwmod *oh) _set_clockactivity(oh, oh->class->sysc->clockact, &v); _write_sysconfig(v, oh); - - /* If slave is in SMARTIDLE, also enable wakeup */ - if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) - _enable_wakeup(oh); - - /* - * Set the autoidle bit only after setting the smartidle bit - * Setting this will not have any impact on the other modules. - */ - if (sf & SYSC_HAS_AUTOIDLE) { - idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? - 0 : 1; - _set_module_autoidle(oh, idlemode, &v); - _write_sysconfig(v, oh); - } } /** - * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG + * _sysc_idle - try to put a module into idle via OCP_SYSCONFIG * @oh: struct omap_hwmod * * * If module is marked as SWSUP_SIDLE, force the module into slave @@ -813,7 +682,7 @@ static void _enable_sysc(struct omap_hwmod *oh) * as SWSUP_MSUSPEND, force the module into master standby; otherwise, * configure it for smart-standby. No return value. */ -static void _idle_sysc(struct omap_hwmod *oh) +static void _sysc_idle(struct omap_hwmod *oh) { u8 idlemode, sf; u32 v; @@ -840,13 +709,13 @@ static void _idle_sysc(struct omap_hwmod *oh) } /** - * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG + * _sysc_shutdown - force a module into idle via OCP_SYSCONFIG * @oh: struct omap_hwmod * * * Force the module into slave idle and master suspend. No return * value. */ -static void _shutdown_sysc(struct omap_hwmod *oh) +static void _sysc_shutdown(struct omap_hwmod *oh) { u32 v; u8 sf; @@ -898,10 +767,10 @@ static struct omap_hwmod *_lookup(const char *name) * @data: not used; pass NULL * * Called by omap_hwmod_late_init() (after omap2_clk_init()). - * Resolves all clock names embedded in the hwmod. Returns -EINVAL if - * the omap_hwmod has not yet been registered or if the clocks have - * already been initialized, 0 on success, or a non-zero error on - * failure. + * Resolves all clock names embedded in the hwmod. Must be called + * with omap_hwmod_mutex held. Returns -EINVAL if the omap_hwmod + * has not yet been registered or if the clocks have already been + * initialized, 0 on success, or a non-zero error on failure. */ static int _init_clocks(struct omap_hwmod *oh, void *data) { @@ -964,203 +833,57 @@ static int _wait_target_ready(struct omap_hwmod *oh) return ret; } -/** - * _lookup_hardreset - return the register bit shift for this hwmod/reset line - * @oh: struct omap_hwmod * - * @name: name of the reset line in the context of this hwmod - * - * Return the bit position of the reset line that match the - * input name. Return -ENOENT if not found. - */ -static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name) -{ - int i; - - for (i = 0; i < oh->rst_lines_cnt; i++) { - const char *rst_line = oh->rst_lines[i].name; - if (!strcmp(rst_line, name)) { - u8 shift = oh->rst_lines[i].rst_shift; - pr_debug("omap_hwmod: %s: _lookup_hardreset: %s: %d\n", - oh->name, rst_line, shift); - - return shift; - } - } - - return -ENOENT; -} - -/** - * _assert_hardreset - assert the HW reset line of submodules - * contained in the hwmod module. - * @oh: struct omap_hwmod * - * @name: name of the reset line to lookup and assert - * - * Some IP like dsp, ipu or iva contain processor that require - * an HW reset line to be assert / deassert in order to enable fully - * the IP. - */ -static int _assert_hardreset(struct omap_hwmod *oh, const char *name) -{ - u8 shift; - - if (!oh) - return -EINVAL; - - shift = _lookup_hardreset(oh, name); - if (IS_ERR_VALUE(shift)) - return shift; - - if (cpu_is_omap24xx() || cpu_is_omap34xx()) - return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, - shift); - else if (cpu_is_omap44xx()) - return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg, - shift); - else - return -EINVAL; -} - -/** - * _deassert_hardreset - deassert the HW reset line of submodules contained - * in the hwmod module. - * @oh: struct omap_hwmod * - * @name: name of the reset line to look up and deassert - * - * Some IP like dsp, ipu or iva contain processor that require - * an HW reset line to be assert / deassert in order to enable fully - * the IP. - */ -static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) -{ - u8 shift; - int r; - - if (!oh) - return -EINVAL; - - shift = _lookup_hardreset(oh, name); - if (IS_ERR_VALUE(shift)) - return shift; - - if (cpu_is_omap24xx() || cpu_is_omap34xx()) - r = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, - shift); - else if (cpu_is_omap44xx()) - r = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg, - shift); - else - return -EINVAL; - - if (r == -EBUSY) - pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); - - return r; -} - -/** - * _read_hardreset - read the HW reset line state of submodules - * contained in the hwmod module - * @oh: struct omap_hwmod * - * @name: name of the reset line to look up and read - * - * Return the state of the reset line. - */ -static int _read_hardreset(struct omap_hwmod *oh, const char *name) -{ - u8 shift; - - if (!oh) - return -EINVAL; - - shift = _lookup_hardreset(oh, name); - if (IS_ERR_VALUE(shift)) - return shift; - - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { - return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, - shift); - } else if (cpu_is_omap44xx()) { - return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg, - shift); - } else { - return -EINVAL; - } -} - /** * _reset - reset an omap_hwmod * @oh: struct omap_hwmod * * * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be - * enabled for this to work. Returns -EINVAL if the hwmod cannot be - * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if - * the module did not reset in time, or 0 upon success. - * - * In OMAP3 a specific SYSSTATUS register is used to get the reset status. - * Starting in OMAP4, some IPs does not have SYSSTATUS register and instead - * use the SYSCONFIG softreset bit to provide the status. - * - * Note that some IP like McBSP does have a reset control but no reset status. + * enabled for this to work. Must be called with omap_hwmod_mutex + * held. Returns -EINVAL if the hwmod cannot be reset this way or if + * the hwmod is in the wrong state, -ETIMEDOUT if the module did not + * reset in time, or 0 upon success. */ static int _reset(struct omap_hwmod *oh) { - u32 v; + u32 r, v; int c = 0; - int ret = 0; if (!oh->class->sysc || - !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) + !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET) || + (oh->class->sysc->sysc_flags & SYSS_MISSING)) return -EINVAL; /* clocks must be on for this operation */ if (oh->_state != _HWMOD_STATE_ENABLED) { - pr_warning("omap_hwmod: %s: reset can only be entered from " - "enabled state\n", oh->name); + WARN(1, "omap_hwmod: %s: reset can only be entered from " + "enabled state\n", oh->name); return -EINVAL; } - /* For some modules, all optionnal clocks need to be enabled as well */ - if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) - _enable_optional_clocks(oh); - pr_debug("omap_hwmod: %s: resetting\n", oh->name); v = oh->_sysc_cache; - ret = _set_softreset(oh, &v); - if (ret) - goto dis_opt_clks; + r = _set_softreset(oh, &v); + if (r) + return r; _write_sysconfig(v, oh); - if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) - omap_test_timeout((omap_hwmod_read(oh, - oh->class->sysc->syss_offs) - & SYSS_RESETDONE_MASK), - MAX_MODULE_SOFTRESET_WAIT, c); - else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) - omap_test_timeout(!(omap_hwmod_read(oh, - oh->class->sysc->sysc_offs) - & SYSC_TYPE2_SOFTRESET_MASK), - MAX_MODULE_SOFTRESET_WAIT, c); - - if (c == MAX_MODULE_SOFTRESET_WAIT) - pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", - oh->name, MAX_MODULE_SOFTRESET_WAIT); + omap_test_timeout((omap_hwmod_readl(oh, oh->class->sysc->syss_offs) & + SYSS_RESETDONE_MASK), + MAX_MODULE_RESET_WAIT, c); + + if (c == MAX_MODULE_RESET_WAIT) + WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n", + oh->name, MAX_MODULE_RESET_WAIT); else - pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); + pr_debug("omap_hwmod: %s: reset in %d usec\n", oh->name, c); /* * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from * _wait_target_ready() or _reset() */ - ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; - -dis_opt_clks: - if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) - _disable_optional_clocks(oh); - - return ret; + return (c == MAX_MODULE_RESET_WAIT) ? -ETIMEDOUT : 0; } /** @@ -1168,11 +891,9 @@ static int _reset(struct omap_hwmod *oh) * @oh: struct omap_hwmod * * * Enables an omap_hwmod @oh such that the MPU can access the hwmod's - * register target. (This function has a full name -- - * _omap_hwmod_enable() rather than simply _enable() -- because it is - * currently required by the pm34xx.c idle loop.) Returns -EINVAL if - * the hwmod is in the wrong state or passes along the return value of - * _wait_target_ready(). + * register target. Must be called with omap_hwmod_mutex held. + * Returns -EINVAL if the hwmod is in the wrong state or passes along + * the return value of _wait_target_ready(). */ int _omap_hwmod_enable(struct omap_hwmod *oh) { @@ -1188,15 +909,6 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: enabling\n", oh->name); - /* - * If an IP contains only one HW reset line, then de-assert it in order - * to allow to enable the clocks. Otherwise the PRCM will return - * Intransition status, and the init will failed. - */ - if ((oh->_state == _HWMOD_STATE_INITIALIZED || - oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) - _deassert_hardreset(oh, oh->rst_lines[0].name); - /* XXX mux balls */ _add_initiator_dep(oh, mpu_oh); @@ -1210,7 +922,7 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) if (oh->class->sysc) { if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) _update_sysc_cache(oh); - _enable_sysc(oh); + _sysc_enable(oh); } } else { pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", @@ -1221,14 +933,12 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) } /** - * _omap_hwmod_idle - idle an omap_hwmod + * _idle - idle an omap_hwmod * @oh: struct omap_hwmod * * * Idles an omap_hwmod @oh. This should be called once the hwmod has - * no further work. (This function has a full name -- - * _omap_hwmod_idle() rather than simply _idle() -- because it is - * currently required by the pm34xx.c idle loop.) Returns -EINVAL if - * the hwmod is in the wrong state or returns 0. + * no further work. Returns -EINVAL if the hwmod is in the wrong + * state or returns 0. */ int _omap_hwmod_idle(struct omap_hwmod *oh) { @@ -1241,7 +951,7 @@ int _omap_hwmod_idle(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: idling\n", oh->name); if (oh->class->sysc) - _idle_sysc(oh); + _sysc_idle(oh); _del_initiator_dep(oh, mpu_oh); _disable_clocks(oh); @@ -1271,21 +981,10 @@ static int _shutdown(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: disabling\n", oh->name); if (oh->class->sysc) - _shutdown_sysc(oh); - - /* - * If an IP contains only one HW reset line, then assert it - * before disabling the clocks and shutting down the IP. - */ - if (oh->rst_lines_cnt == 1) - _assert_hardreset(oh, oh->rst_lines[0].name); - - /* clocks and deps are already disabled in idle */ - if (oh->_state == _HWMOD_STATE_ENABLED) { - _del_initiator_dep(oh, mpu_oh); - /* XXX what about the other system initiators here? dma, dsp */ - _disable_clocks(oh); - } + _sysc_shutdown(oh); + _del_initiator_dep(oh, mpu_oh); + /* XXX what about the other system initiators here? DMA, tesla, d2d */ + _disable_clocks(oh); /* XXX Should this code also force-disable the optional clocks? */ /* XXX mux any associated balls to safe mode */ @@ -1301,10 +1000,11 @@ static int _shutdown(struct omap_hwmod *oh) * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1 * * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh - * OCP_SYSCONFIG register. @skip_setup_idle is intended to be used on - * a system that will not call omap_hwmod_enable() to enable devices - * (e.g., a system without PM runtime). Returns -EINVAL if the hwmod - * is in the wrong state or returns 0. + * OCP_SYSCONFIG register. Must be called with omap_hwmod_mutex held. + * @skip_setup_idle is intended to be used on a system that will not + * call omap_hwmod_enable() to enable devices (e.g., a system without + * PM runtime). Returns -EINVAL if the hwmod is in the wrong state or + * returns 0. */ static int _setup(struct omap_hwmod *oh, void *data) { @@ -1334,19 +1034,8 @@ static int _setup(struct omap_hwmod *oh, void *data) } } - mutex_init(&oh->_mutex); oh->_state = _HWMOD_STATE_INITIALIZED; - /* - * In the case of hwmod with hardreset that should not be - * de-assert at boot time, we have to keep the module - * initialized, because we cannot enable it properly with the - * reset asserted. Exit without warning because that behavior is - * expected. - */ - if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1) - return 0; - r = _omap_hwmod_enable(oh); if (r) { pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", @@ -1355,16 +1044,16 @@ static int _setup(struct omap_hwmod *oh, void *data) } if (!(oh->flags & HWMOD_INIT_NO_RESET)) { - _reset(oh); - /* - * OCP_SYSCONFIG bits need to be reprogrammed after a softreset. - * The _omap_hwmod_enable() function should be split to - * avoid the rewrite of the OCP_SYSCONFIG register. + * XXX Do the OCP_SYSCONFIG bits need to be + * reprogrammed after a reset? If not, then this can + * be removed. If they do, then probably the + * _omap_hwmod_enable() function should be split to avoid the + * rewrite of the OCP_SYSCONFIG register. */ if (oh->class->sysc) { _update_sysc_cache(oh); - _enable_sysc(oh); + _sysc_enable(oh); } } @@ -1378,20 +1067,14 @@ static int _setup(struct omap_hwmod *oh, void *data) /* Public functions */ -u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) +u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs) { - if (oh->flags & HWMOD_16BIT_REG) - return __raw_readw(oh->_mpu_rt_va + reg_offs); - else - return __raw_readl(oh->_mpu_rt_va + reg_offs); + return __raw_readl(oh->_mpu_rt_va + reg_offs); } -void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) +void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs) { - if (oh->flags & HWMOD_16BIT_REG) - __raw_writew(v, oh->_mpu_rt_va + reg_offs); - else - __raw_writel(v, oh->_mpu_rt_va + reg_offs); + __raw_writel(v, oh->_mpu_rt_va + reg_offs); } /** @@ -1626,7 +1309,7 @@ int omap_hwmod_unregister(struct omap_hwmod *oh) * omap_hwmod_enable - enable an omap_hwmod * @oh: struct omap_hwmod * * - * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). + * Enable an omap_hwomd @oh. Intended to be called by omap_device_enable(). * Returns -EINVAL on error or passes along the return value from _enable(). */ int omap_hwmod_enable(struct omap_hwmod *oh) @@ -1636,9 +1319,9 @@ int omap_hwmod_enable(struct omap_hwmod *oh) if (!oh) return -EINVAL; - mutex_lock(&oh->_mutex); + mutex_lock(&omap_hwmod_mutex); r = _omap_hwmod_enable(oh); - mutex_unlock(&oh->_mutex); + mutex_unlock(&omap_hwmod_mutex); return r; } @@ -1648,7 +1331,7 @@ int omap_hwmod_enable(struct omap_hwmod *oh) * omap_hwmod_idle - idle an omap_hwmod * @oh: struct omap_hwmod * * - * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). + * Idle an omap_hwomd @oh. Intended to be called by omap_device_idle(). * Returns -EINVAL on error or passes along the return value from _idle(). */ int omap_hwmod_idle(struct omap_hwmod *oh) @@ -1656,9 +1339,9 @@ int omap_hwmod_idle(struct omap_hwmod *oh) if (!oh) return -EINVAL; - mutex_lock(&oh->_mutex); + mutex_lock(&omap_hwmod_mutex); _omap_hwmod_idle(oh); - mutex_unlock(&oh->_mutex); + mutex_unlock(&omap_hwmod_mutex); return 0; } @@ -1667,7 +1350,7 @@ int omap_hwmod_idle(struct omap_hwmod *oh) * omap_hwmod_shutdown - shutdown an omap_hwmod * @oh: struct omap_hwmod * * - * Shutdown an omap_hwmod @oh. Intended to be called by + * Shutdown an omap_hwomd @oh. Intended to be called by * omap_device_shutdown(). Returns -EINVAL on error or passes along * the return value from _shutdown(). */ @@ -1676,9 +1359,9 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh) if (!oh) return -EINVAL; - mutex_lock(&oh->_mutex); + mutex_lock(&omap_hwmod_mutex); _shutdown(oh); - mutex_unlock(&oh->_mutex); + mutex_unlock(&omap_hwmod_mutex); return 0; } @@ -1691,9 +1374,9 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh) */ int omap_hwmod_enable_clocks(struct omap_hwmod *oh) { - mutex_lock(&oh->_mutex); + mutex_lock(&omap_hwmod_mutex); _enable_clocks(oh); - mutex_unlock(&oh->_mutex); + mutex_unlock(&omap_hwmod_mutex); return 0; } @@ -1706,9 +1389,9 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh) */ int omap_hwmod_disable_clocks(struct omap_hwmod *oh) { - mutex_lock(&oh->_mutex); + mutex_lock(&omap_hwmod_mutex); _disable_clocks(oh); - mutex_unlock(&oh->_mutex); + mutex_unlock(&omap_hwmod_mutex); return 0; } @@ -1738,7 +1421,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) * Forces posted writes to complete on the OCP thread handling * register writes */ - omap_hwmod_read(oh, oh->class->sysc->sysc_offs); + omap_hwmod_readl(oh, oh->class->sysc->sysc_offs); } /** @@ -1747,18 +1430,20 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) * * Under some conditions, a driver may wish to reset the entire device. * Called from omap_device code. Returns -EINVAL on error or passes along - * the return value from _reset(). + * the return value from _reset()/_enable(). */ int omap_hwmod_reset(struct omap_hwmod *oh) { int r; - if (!oh) + if (!oh || !(oh->_state & _HWMOD_STATE_ENABLED)) return -EINVAL; - mutex_lock(&oh->_mutex); + mutex_lock(&omap_hwmod_mutex); r = _reset(oh); - mutex_unlock(&oh->_mutex); + if (!r) + r = _omap_hwmod_enable(oh); + mutex_unlock(&omap_hwmod_mutex); return r; } @@ -1783,7 +1468,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh) { int ret, i; - ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt; + ret = oh->mpu_irqs_cnt + oh->sdma_chs_cnt; for (i = 0; i < oh->slaves_cnt; i++) ret += oh->slaves[i]->addr_cnt; @@ -1816,10 +1501,10 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) r++; } - for (i = 0; i < oh->sdma_reqs_cnt; i++) { - (res + r)->name = (oh->sdma_reqs + i)->name; - (res + r)->start = (oh->sdma_reqs + i)->dma_req; - (res + r)->end = (oh->sdma_reqs + i)->dma_req; + for (i = 0; i < oh->sdma_chs_cnt; i++) { + (res + r)->name = (oh->sdma_chs + i)->name; + (res + r)->start = (oh->sdma_chs + i)->dma_ch; + (res + r)->end = (oh->sdma_chs + i)->dma_ch; (res + r)->flags = IORESOURCE_DMA; r++; } @@ -1959,9 +1644,9 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) return -EINVAL; - mutex_lock(&oh->_mutex); + mutex_lock(&omap_hwmod_mutex); _enable_wakeup(oh); - mutex_unlock(&oh->_mutex); + mutex_unlock(&omap_hwmod_mutex); return 0; } @@ -1984,91 +1669,13 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) return -EINVAL; - mutex_lock(&oh->_mutex); + mutex_lock(&omap_hwmod_mutex); _disable_wakeup(oh); - mutex_unlock(&oh->_mutex); + mutex_unlock(&omap_hwmod_mutex); return 0; } -/** - * omap_hwmod_assert_hardreset - assert the HW reset line of submodules - * contained in the hwmod module. - * @oh: struct omap_hwmod * - * @name: name of the reset line to lookup and assert - * - * Some IP like dsp, ipu or iva contain processor that require - * an HW reset line to be assert / deassert in order to enable fully - * the IP. Returns -EINVAL if @oh is null or if the operation is not - * yet supported on this OMAP; otherwise, passes along the return value - * from _assert_hardreset(). - */ -int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) -{ - int ret; - - if (!oh) - return -EINVAL; - - mutex_lock(&oh->_mutex); - ret = _assert_hardreset(oh, name); - mutex_unlock(&oh->_mutex); - - return ret; -} - -/** - * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules - * contained in the hwmod module. - * @oh: struct omap_hwmod * - * @name: name of the reset line to look up and deassert - * - * Some IP like dsp, ipu or iva contain processor that require - * an HW reset line to be assert / deassert in order to enable fully - * the IP. Returns -EINVAL if @oh is null or if the operation is not - * yet supported on this OMAP; otherwise, passes along the return value - * from _deassert_hardreset(). - */ -int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) -{ - int ret; - - if (!oh) - return -EINVAL; - - mutex_lock(&oh->_mutex); - ret = _deassert_hardreset(oh, name); - mutex_unlock(&oh->_mutex); - - return ret; -} - -/** - * omap_hwmod_read_hardreset - read the HW reset line state of submodules - * contained in the hwmod module - * @oh: struct omap_hwmod * - * @name: name of the reset line to look up and read - * - * Return the current state of the hwmod @oh's reset line named @name: - * returns -EINVAL upon parameter error or if this operation - * is unsupported on the current OMAP; otherwise, passes along the return - * value from _read_hardreset(). - */ -int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) -{ - int ret; - - if (!oh) - return -EINVAL; - - mutex_lock(&oh->_mutex); - ret = _read_hardreset(oh, name); - mutex_unlock(&oh->_mutex); - - return ret; -} - - /** * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname * @classname: struct omap_hwmod_class name to search for diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_2420_data.c index adf6e3632a2b..3cc768e8bc04 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -15,12 +15,10 @@ #include #include #include -#include #include "omap_hwmod_common_data.h" #include "prm-regbits-24xx.h" -#include "cm-regbits-24xx.h" /* * OMAP2420 hardware module integration data @@ -35,7 +33,6 @@ static struct omap_hwmod omap2420_mpu_hwmod; static struct omap_hwmod omap2420_iva_hwmod; static struct omap_hwmod omap2420_l3_main_hwmod; static struct omap_hwmod omap2420_l4_core_hwmod; -static struct omap_hwmod omap2420_wd_timer2_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { @@ -74,9 +71,6 @@ static struct omap_hwmod omap2420_l3_main_hwmod = { }; static struct omap_hwmod omap2420_l4_wkup_hwmod; -static struct omap_hwmod omap2420_uart1_hwmod; -static struct omap_hwmod omap2420_uart2_hwmod; -static struct omap_hwmod omap2420_uart3_hwmod; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { @@ -85,60 +79,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* L4 CORE -> UART1 interface */ -static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = { - { - .pa_start = OMAP2_UART1_BASE, - .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, -}; - -static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_uart1_hwmod, - .clk = "uart1_ick", - .addr = omap2420_uart1_addr_space, - .addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART2 interface */ -static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = { - { - .pa_start = OMAP2_UART2_BASE, - .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, -}; - -static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_uart2_hwmod, - .clk = "uart2_ick", - .addr = omap2420_uart2_addr_space, - .addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 PER -> UART3 interface */ -static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = { - { - .pa_start = OMAP2_UART3_BASE, - .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, -}; - -static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_uart3_hwmod, - .clk = "uart3_ick", - .addr = omap2420_uart3_addr_space, - .addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { &omap2420_l3_main__l4_core, @@ -147,9 +87,6 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { /* Master interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { &omap2420_l4_core__l4_wkup, - &omap2_l4_core__uart1, - &omap2_l4_core__uart2, - &omap2_l4_core__uart3, }; /* L4 CORE */ @@ -228,206 +165,12 @@ static struct omap_hwmod omap2420_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { - { - .pa_start = 0x48022000, - .pa_end = 0x4802207f, - .flags = ADDR_TYPE_RT - }, -}; - -static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_wd_timer2_hwmod, - .clk = "mpu_wdt_ick", - .addr = omap2420_wd_timer2_addrs, - .addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* - * 'wd_timer' class - * 32-bit watchdog upward counter that generates a pulse on the reset pin on - * overflow condition - */ - -static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = { - .name = "wd_timer", - .sysc = &omap2420_wd_timer_sysc, -}; - -/* wd_timer2 */ -static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { - &omap2420_l4_wkup__wd_timer2, -}; - -static struct omap_hwmod omap2420_wd_timer2_hwmod = { - .name = "wd_timer2", - .class = &omap2420_wd_timer_hwmod_class, - .main_clk = "mpu_wdt_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, - }, - }, - .slaves = omap2420_wd_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -}; - -/* UART */ - -static struct omap_hwmod_class_sysconfig uart_sysc = { - .rev_offs = 0x50, - .sysc_offs = 0x54, - .syss_offs = 0x58, - .sysc_flags = (SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class uart_class = { - .name = "uart", - .sysc = &uart_sysc, -}; - -/* UART1 */ - -static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { - { .irq = INT_24XX_UART1_IRQ, }, -}; - -static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { - { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, - { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, -}; - -static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { - &omap2_l4_core__uart1, -}; - -static struct omap_hwmod omap2420_uart1_hwmod = { - .name = "uart1", - .mpu_irqs = uart1_mpu_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), - .sdma_reqs = uart1_sdma_reqs, - .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), - .main_clk = "uart1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, - }, - }, - .slaves = omap2420_uart1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), - .class = &uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -}; - -/* UART2 */ - -static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { - { .irq = INT_24XX_UART2_IRQ, }, -}; - -static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { - { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, - { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, -}; - -static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { - &omap2_l4_core__uart2, -}; - -static struct omap_hwmod omap2420_uart2_hwmod = { - .name = "uart2", - .mpu_irqs = uart2_mpu_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), - .sdma_reqs = uart2_sdma_reqs, - .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), - .main_clk = "uart2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, - }, - }, - .slaves = omap2420_uart2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), - .class = &uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -}; - -/* UART3 */ - -static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { - { .irq = INT_24XX_UART3_IRQ, }, -}; - -static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { - { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, - { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, -}; - -static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { - &omap2_l4_core__uart3, -}; - -static struct omap_hwmod omap2420_uart3_hwmod = { - .name = "uart3", - .mpu_irqs = uart3_mpu_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), - .sdma_reqs = uart3_sdma_reqs, - .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), - .main_clk = "uart3_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 2, - .module_bit = OMAP24XX_EN_UART3_SHIFT, - .idlest_reg_id = 2, - .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, - }, - }, - .slaves = omap2420_uart3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), - .class = &uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -}; - static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_l3_main_hwmod, &omap2420_l4_core_hwmod, &omap2420_l4_wkup_hwmod, &omap2420_mpu_hwmod, &omap2420_iva_hwmod, - &omap2420_wd_timer2_hwmod, - &omap2420_uart1_hwmod, - &omap2420_uart2_hwmod, - &omap2420_uart3_hwmod, NULL, }; diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 12d939e456cf..4526628ed287 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -15,12 +15,10 @@ #include #include #include -#include #include "omap_hwmod_common_data.h" #include "prm-regbits-24xx.h" -#include "cm-regbits-24xx.h" /* * OMAP2430 hardware module integration data @@ -35,7 +33,6 @@ static struct omap_hwmod omap2430_mpu_hwmod; static struct omap_hwmod omap2430_iva_hwmod; static struct omap_hwmod omap2430_l3_main_hwmod; static struct omap_hwmod omap2430_l4_core_hwmod; -static struct omap_hwmod omap2430_wd_timer2_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { @@ -74,9 +71,6 @@ static struct omap_hwmod omap2430_l3_main_hwmod = { }; static struct omap_hwmod omap2430_l4_wkup_hwmod; -static struct omap_hwmod omap2430_uart1_hwmod; -static struct omap_hwmod omap2430_uart2_hwmod; -static struct omap_hwmod omap2430_uart3_hwmod; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { @@ -85,60 +79,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* L4 CORE -> UART1 interface */ -static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = { - { - .pa_start = OMAP2_UART1_BASE, - .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, -}; - -static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_uart1_hwmod, - .clk = "uart1_ick", - .addr = omap2430_uart1_addr_space, - .addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART2 interface */ -static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = { - { - .pa_start = OMAP2_UART2_BASE, - .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, -}; - -static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_uart2_hwmod, - .clk = "uart2_ick", - .addr = omap2430_uart2_addr_space, - .addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 PER -> UART3 interface */ -static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = { - { - .pa_start = OMAP2_UART3_BASE, - .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, -}; - -static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_uart3_hwmod, - .clk = "uart3_ick", - .addr = omap2430_uart3_addr_space, - .addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { &omap2430_l3_main__l4_core, @@ -164,9 +104,6 @@ static struct omap_hwmod omap2430_l4_core_hwmod = { /* Slave interfaces on the L4_WKUP interconnect */ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { &omap2430_l4_core__l4_wkup, - &omap2_l4_core__uart1, - &omap2_l4_core__uart2, - &omap2_l4_core__uart3, }; /* Master interfaces on the L4_WKUP interconnect */ @@ -228,206 +165,12 @@ static struct omap_hwmod omap2430_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { - { - .pa_start = 0x49016000, - .pa_end = 0x4901607f, - .flags = ADDR_TYPE_RT - }, -}; - -static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_wd_timer2_hwmod, - .clk = "mpu_wdt_ick", - .addr = omap2430_wd_timer2_addrs, - .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* - * 'wd_timer' class - * 32-bit watchdog upward counter that generates a pulse on the reset pin on - * overflow condition - */ - -static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { - .rev_offs = 0x0, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { - .name = "wd_timer", - .sysc = &omap2430_wd_timer_sysc, -}; - -/* wd_timer2 */ -static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { - &omap2430_l4_wkup__wd_timer2, -}; - -static struct omap_hwmod omap2430_wd_timer2_hwmod = { - .name = "wd_timer2", - .class = &omap2430_wd_timer_hwmod_class, - .main_clk = "mpu_wdt_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, - }, - }, - .slaves = omap2430_wd_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -}; - -/* UART */ - -static struct omap_hwmod_class_sysconfig uart_sysc = { - .rev_offs = 0x50, - .sysc_offs = 0x54, - .syss_offs = 0x58, - .sysc_flags = (SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class uart_class = { - .name = "uart", - .sysc = &uart_sysc, -}; - -/* UART1 */ - -static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { - { .irq = INT_24XX_UART1_IRQ, }, -}; - -static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { - { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, - { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, -}; - -static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { - &omap2_l4_core__uart1, -}; - -static struct omap_hwmod omap2430_uart1_hwmod = { - .name = "uart1", - .mpu_irqs = uart1_mpu_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), - .sdma_reqs = uart1_sdma_reqs, - .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), - .main_clk = "uart1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, - }, - }, - .slaves = omap2430_uart1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), - .class = &uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -}; - -/* UART2 */ - -static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { - { .irq = INT_24XX_UART2_IRQ, }, -}; - -static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { - { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, - { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, -}; - -static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { - &omap2_l4_core__uart2, -}; - -static struct omap_hwmod omap2430_uart2_hwmod = { - .name = "uart2", - .mpu_irqs = uart2_mpu_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), - .sdma_reqs = uart2_sdma_reqs, - .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), - .main_clk = "uart2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, - }, - }, - .slaves = omap2430_uart2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), - .class = &uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -}; - -/* UART3 */ - -static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { - { .irq = INT_24XX_UART3_IRQ, }, -}; - -static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { - { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, - { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, -}; - -static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { - &omap2_l4_core__uart3, -}; - -static struct omap_hwmod omap2430_uart3_hwmod = { - .name = "uart3", - .mpu_irqs = uart3_mpu_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), - .sdma_reqs = uart3_sdma_reqs, - .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), - .main_clk = "uart3_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 2, - .module_bit = OMAP24XX_EN_UART3_SHIFT, - .idlest_reg_id = 2, - .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, - }, - }, - .slaves = omap2430_uart3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), - .class = &uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -}; - static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l3_main_hwmod, &omap2430_l4_core_hwmod, &omap2430_l4_wkup_hwmod, &omap2430_mpu_hwmod, &omap2430_iva_hwmod, - &omap2430_wd_timer2_hwmod, - &omap2430_uart1_hwmod, - &omap2430_uart2_hwmod, - &omap2430_uart3_hwmod, NULL, }; diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index cb97ecf0a3f6..5d8eb58ba5e3 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -17,12 +17,10 @@ #include #include #include -#include #include "omap_hwmod_common_data.h" #include "prm-regbits-34xx.h" -#include "cm-regbits-34xx.h" /* * OMAP3xxx hardware module integration data @@ -38,7 +36,6 @@ static struct omap_hwmod omap3xxx_iva_hwmod; static struct omap_hwmod omap3xxx_l3_main_hwmod; static struct omap_hwmod omap3xxx_l4_core_hwmod; static struct omap_hwmod omap3xxx_l4_per_hwmod; -static struct omap_hwmod omap3xxx_wd_timer2_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { @@ -85,10 +82,6 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = { }; static struct omap_hwmod omap3xxx_l4_wkup_hwmod; -static struct omap_hwmod omap3xxx_uart1_hwmod; -static struct omap_hwmod omap3xxx_uart2_hwmod; -static struct omap_hwmod omap3xxx_uart3_hwmod; -static struct omap_hwmod omap3xxx_uart4_hwmod; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { @@ -97,78 +90,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* L4 CORE -> UART1 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { - { - .pa_start = OMAP3_UART1_BASE, - .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, -}; - -static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_uart1_hwmod, - .clk = "uart1_ick", - .addr = omap3xxx_uart1_addr_space, - .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART2 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { - { - .pa_start = OMAP3_UART2_BASE, - .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, -}; - -static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_uart2_hwmod, - .clk = "uart2_ick", - .addr = omap3xxx_uart2_addr_space, - .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 PER -> UART3 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { - { - .pa_start = OMAP3_UART3_BASE, - .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, -}; - -static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_uart3_hwmod, - .clk = "uart3_ick", - .addr = omap3xxx_uart3_addr_space, - .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 PER -> UART4 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = { - { - .pa_start = OMAP3_UART4_BASE, - .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, -}; - -static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_uart4_hwmod, - .clk = "uart4_ick", - .addr = omap3xxx_uart4_addr_space, - .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { &omap3xxx_l3_main__l4_core, @@ -177,8 +98,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { /* Master interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { &omap3xxx_l4_core__l4_wkup, - &omap3_l4_core__uart1, - &omap3_l4_core__uart2, }; /* L4 CORE */ @@ -200,8 +119,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { /* Master interfaces on the L4_PER interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = { - &omap3_l4_per__uart3, - &omap3_l4_per__uart4, }; /* L4 PER */ @@ -280,235 +197,6 @@ static struct omap_hwmod omap3xxx_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { - { - .pa_start = 0x48314000, - .pa_end = 0x4831407f, - .flags = ADDR_TYPE_RT - }, -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_wd_timer2_hwmod, - .clk = "wdt2_ick", - .addr = omap3xxx_wd_timer2_addrs, - .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* - * 'wd_timer' class - * 32-bit watchdog upward counter that generates a pulse on the reset pin on - * overflow condition - */ - -static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { - .name = "wd_timer", - .sysc = &omap3xxx_wd_timer_sysc, -}; - -/* wd_timer2 */ -static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { - &omap3xxx_l4_wkup__wd_timer2, -}; - -static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { - .name = "wd_timer2", - .class = &omap3xxx_wd_timer_hwmod_class, - .main_clk = "wdt2_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_WDT2_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, - }, - }, - .slaves = omap3xxx_wd_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -/* UART common */ - -static struct omap_hwmod_class_sysconfig uart_sysc = { - .rev_offs = 0x50, - .sysc_offs = 0x54, - .syss_offs = 0x58, - .sysc_flags = (SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class uart_class = { - .name = "uart", - .sysc = &uart_sysc, -}; - -/* UART1 */ - -static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { - { .irq = INT_24XX_UART1_IRQ, }, -}; - -static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { - { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, - { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, -}; - -static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { - &omap3_l4_core__uart1, -}; - -static struct omap_hwmod omap3xxx_uart1_hwmod = { - .name = "uart1", - .mpu_irqs = uart1_mpu_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), - .sdma_reqs = uart1_sdma_reqs, - .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), - .main_clk = "uart1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_UART1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, - }, - }, - .slaves = omap3xxx_uart1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), - .class = &uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -/* UART2 */ - -static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { - { .irq = INT_24XX_UART2_IRQ, }, -}; - -static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { - { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, - { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, -}; - -static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { - &omap3_l4_core__uart2, -}; - -static struct omap_hwmod omap3xxx_uart2_hwmod = { - .name = "uart2", - .mpu_irqs = uart2_mpu_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), - .sdma_reqs = uart2_sdma_reqs, - .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), - .main_clk = "uart2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_UART2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, - }, - }, - .slaves = omap3xxx_uart2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), - .class = &uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -/* UART3 */ - -static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { - { .irq = INT_24XX_UART3_IRQ, }, -}; - -static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { - { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, - { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, -}; - -static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { - &omap3_l4_per__uart3, -}; - -static struct omap_hwmod omap3xxx_uart3_hwmod = { - .name = "uart3", - .mpu_irqs = uart3_mpu_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), - .sdma_reqs = uart3_sdma_reqs, - .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), - .main_clk = "uart3_fck", - .prcm = { - .omap2 = { - .module_offs = OMAP3430_PER_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_UART3_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, - }, - }, - .slaves = omap3xxx_uart3_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), - .class = &uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -/* UART4 */ - -static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { - { .irq = INT_36XX_UART4_IRQ, }, -}; - -static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { - { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, - { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, -}; - -static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { - &omap3_l4_per__uart4, -}; - -static struct omap_hwmod omap3xxx_uart4_hwmod = { - .name = "uart4", - .mpu_irqs = uart4_mpu_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs), - .sdma_reqs = uart4_sdma_reqs, - .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs), - .main_clk = "uart4_fck", - .prcm = { - .omap2 = { - .module_offs = OMAP3430_PER_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3630_EN_UART4_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, - }, - }, - .slaves = omap3xxx_uart4_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), - .class = &uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), -}; - static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, @@ -516,11 +204,6 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l4_wkup_hwmod, &omap3xxx_mpu_hwmod, &omap3xxx_iva_hwmod, - &omap3xxx_wd_timer2_hwmod, - &omap3xxx_uart1_hwmod, - &omap3xxx_uart2_hwmod, - &omap3xxx_uart3_hwmod, - &omap3xxx_uart4_hwmod, NULL, }; @@ -528,3 +211,5 @@ int __init omap3xxx_hwmod_init(void) { return omap_hwmod_init(omap3xxx_hwmods); } + + diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_44xx_data.c deleted file mode 100644 index 7274db4de487..000000000000 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ /dev/null @@ -1,850 +0,0 @@ -/* - * Hardware modules present on the OMAP44xx chips - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * Copyright (C) 2009-2010 Nokia Corporation - * - * Paul Walmsley - * Benoit Cousson - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -#include -#include - -#include "omap_hwmod_common_data.h" - -#include "cm.h" -#include "prm-regbits-44xx.h" - -/* Base offset for all OMAP4 interrupts external to MPUSS */ -#define OMAP44XX_IRQ_GIC_START 32 - -/* Base offset for all OMAP4 dma requests */ -#define OMAP44XX_DMA_REQ_START 1 - -/* Backward references (IPs with Bus Master capability) */ -static struct omap_hwmod omap44xx_dmm_hwmod; -static struct omap_hwmod omap44xx_emif_fw_hwmod; -static struct omap_hwmod omap44xx_l3_instr_hwmod; -static struct omap_hwmod omap44xx_l3_main_1_hwmod; -static struct omap_hwmod omap44xx_l3_main_2_hwmod; -static struct omap_hwmod omap44xx_l3_main_3_hwmod; -static struct omap_hwmod omap44xx_l4_abe_hwmod; -static struct omap_hwmod omap44xx_l4_cfg_hwmod; -static struct omap_hwmod omap44xx_l4_per_hwmod; -static struct omap_hwmod omap44xx_l4_wkup_hwmod; -static struct omap_hwmod omap44xx_mpu_hwmod; -static struct omap_hwmod omap44xx_mpu_private_hwmod; - -/* - * Interconnects omap_hwmod structures - * hwmods that compose the global OMAP interconnect - */ - -/* - * 'dmm' class - * instance(s): dmm - */ -static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { - .name = "dmm", -}; - -/* dmm interface data */ -/* l3_main_1 -> dmm */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_dmm_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mpu -> dmm */ -static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_dmm_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dmm slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { - &omap44xx_l3_main_1__dmm, - &omap44xx_mpu__dmm, -}; - -static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { - { .irq = 113 + OMAP44XX_IRQ_GIC_START }, -}; - -static struct omap_hwmod omap44xx_dmm_hwmod = { - .name = "dmm", - .class = &omap44xx_dmm_hwmod_class, - .slaves = omap44xx_dmm_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), - .mpu_irqs = omap44xx_dmm_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* - * 'emif_fw' class - * instance(s): emif_fw - */ -static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { - .name = "emif_fw", -}; - -/* emif_fw interface data */ -/* dmm -> emif_fw */ -static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { - .master = &omap44xx_dmm_hwmod, - .slave = &omap44xx_emif_fw_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> emif_fw */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_emif_fw_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* emif_fw slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = { - &omap44xx_dmm__emif_fw, - &omap44xx_l4_cfg__emif_fw, -}; - -static struct omap_hwmod omap44xx_emif_fw_hwmod = { - .name = "emif_fw", - .class = &omap44xx_emif_fw_hwmod_class, - .slaves = omap44xx_emif_fw_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* - * 'l3' class - * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 - */ -static struct omap_hwmod_class omap44xx_l3_hwmod_class = { - .name = "l3", -}; - -/* l3_instr interface data */ -/* l3_main_3 -> l3_instr */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { - .master = &omap44xx_l3_main_3_hwmod, - .slave = &omap44xx_l3_instr_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_instr slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { - &omap44xx_l3_main_3__l3_instr, -}; - -static struct omap_hwmod omap44xx_l3_instr_hwmod = { - .name = "l3_instr", - .class = &omap44xx_l3_hwmod_class, - .slaves = omap44xx_l3_instr_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* l3_main_2 -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mpu -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { - &omap44xx_l3_main_2__l3_main_1, - &omap44xx_l4_cfg__l3_main_1, - &omap44xx_mpu__l3_main_1, -}; - -static struct omap_hwmod omap44xx_l3_main_1_hwmod = { - .name = "l3_main_1", - .class = &omap44xx_l3_hwmod_class, - .slaves = omap44xx_l3_main_1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* l3_main_2 interface data */ -/* l3_main_1 -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { - &omap44xx_l3_main_1__l3_main_2, - &omap44xx_l4_cfg__l3_main_2, -}; - -static struct omap_hwmod omap44xx_l3_main_2_hwmod = { - .name = "l3_main_2", - .class = &omap44xx_l3_hwmod_class, - .slaves = omap44xx_l3_main_2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* l3_main_3 interface data */ -/* l3_main_1 -> l3_main_3 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l3_main_3_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_2 -> l3_main_3 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_l3_main_3_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> l3_main_3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l3_main_3_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = { - &omap44xx_l3_main_1__l3_main_3, - &omap44xx_l3_main_2__l3_main_3, - &omap44xx_l4_cfg__l3_main_3, -}; - -static struct omap_hwmod omap44xx_l3_main_3_hwmod = { - .name = "l3_main_3", - .class = &omap44xx_l3_hwmod_class, - .slaves = omap44xx_l3_main_3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* - * 'l4' class - * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup - */ -static struct omap_hwmod_class omap44xx_l4_hwmod_class = { - .name = "l4", -}; - -/* l4_abe interface data */ -/* l3_main_1 -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mpu -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_abe slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { - &omap44xx_l3_main_1__l4_abe, - &omap44xx_mpu__l4_abe, -}; - -static struct omap_hwmod omap44xx_l4_abe_hwmod = { - .name = "l4_abe", - .class = &omap44xx_l4_hwmod_class, - .slaves = omap44xx_l4_abe_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* l4_cfg interface data */ -/* l3_main_1 -> l4_cfg */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l4_cfg_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = { - &omap44xx_l3_main_1__l4_cfg, -}; - -static struct omap_hwmod omap44xx_l4_cfg_hwmod = { - .name = "l4_cfg", - .class = &omap44xx_l4_hwmod_class, - .slaves = omap44xx_l4_cfg_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* l4_per interface data */ -/* l3_main_2 -> l4_per */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_l4_per_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = { - &omap44xx_l3_main_2__l4_per, -}; - -static struct omap_hwmod omap44xx_l4_per_hwmod = { - .name = "l4_per", - .class = &omap44xx_l4_hwmod_class, - .slaves = omap44xx_l4_per_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* l4_wkup interface data */ -/* l4_cfg -> l4_wkup */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l4_wkup_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_wkup slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = { - &omap44xx_l4_cfg__l4_wkup, -}; - -static struct omap_hwmod omap44xx_l4_wkup_hwmod = { - .name = "l4_wkup", - .class = &omap44xx_l4_hwmod_class, - .slaves = omap44xx_l4_wkup_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* - * 'mpu_bus' class - * instance(s): mpu_private - */ -static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { - .name = "mpu_bus", -}; - -/* mpu_private interface data */ -/* mpu -> mpu_private */ -static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_mpu_private_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mpu_private slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = { - &omap44xx_mpu__mpu_private, -}; - -static struct omap_hwmod omap44xx_mpu_private_hwmod = { - .name = "mpu_private", - .class = &omap44xx_mpu_bus_hwmod_class, - .slaves = omap44xx_mpu_private_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* - * 'mpu' class - * mpu sub-system - */ - -static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { - .name = "mpu", -}; - -/* mpu */ -static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { - { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, - { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, - { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, -}; - -/* mpu master ports */ -static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { - &omap44xx_mpu__l3_main_1, - &omap44xx_mpu__l4_abe, - &omap44xx_mpu__dmm, -}; - -static struct omap_hwmod omap44xx_mpu_hwmod = { - .name = "mpu", - .class = &omap44xx_mpu_hwmod_class, - .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), - .mpu_irqs = omap44xx_mpu_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs), - .main_clk = "dpll_mpu_m2_ck", - .prcm = { - .omap4 = { - .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL, - }, - }, - .masters = omap44xx_mpu_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* - * 'wd_timer' class - * 32-bit watchdog upward counter that generates a pulse on the reset pin on - * overflow condition - */ - -static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | - SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -/* - * 'uart' class - * universal asynchronous receiver/transmitter (uart) - */ - -static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { - .rev_offs = 0x0050, - .sysc_offs = 0x0054, - .syss_offs = 0x0058, - .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { - .name = "wd_timer", - .sysc = &omap44xx_wd_timer_sysc, -}; - -/* wd_timer2 */ -static struct omap_hwmod omap44xx_wd_timer2_hwmod; -static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { - { .irq = 80 + OMAP44XX_IRQ_GIC_START }, -}; - -static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { - { - .pa_start = 0x4a314000, - .pa_end = 0x4a31407f, - .flags = ADDR_TYPE_RT - }, -}; - -static struct omap_hwmod_class omap44xx_uart_hwmod_class = { - .name = "uart", - .sysc = &omap44xx_uart_sysc, -}; - -/* uart1 */ -static struct omap_hwmod omap44xx_uart1_hwmod; -static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { - { .irq = 72 + OMAP44XX_IRQ_GIC_START }, -}; - -static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { - { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, -}; - -static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { - { - .pa_start = 0x4806a000, - .pa_end = 0x4806a0ff, - .flags = ADDR_TYPE_RT - }, -}; - -/* l4_per -> uart1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart1_addrs, - .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* uart1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = { - &omap44xx_l4_per__uart1, -}; - -static struct omap_hwmod omap44xx_uart1_hwmod = { - .name = "uart1", - .class = &omap44xx_uart_hwmod_class, - .mpu_irqs = omap44xx_uart1_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs), - .sdma_reqs = omap44xx_uart1_sdma_reqs, - .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs), - .main_clk = "uart1_fck", - .prcm = { - .omap4 = { - .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, - }, - }, - .slaves = omap44xx_uart1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* uart2 */ -static struct omap_hwmod omap44xx_uart2_hwmod; -static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { - { .irq = 73 + OMAP44XX_IRQ_GIC_START }, -}; - -static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { - { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, -}; - -static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { - { - .pa_start = 0x4806c000, - .pa_end = 0x4806c0ff, - .flags = ADDR_TYPE_RT - }, -}; - -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_wd_timer2_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_wd_timer2_addrs, - .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* wd_timer2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { - &omap44xx_l4_wkup__wd_timer2, -}; - -static struct omap_hwmod omap44xx_wd_timer2_hwmod = { - .name = "wd_timer2", - .class = &omap44xx_wd_timer_hwmod_class, - .mpu_irqs = omap44xx_wd_timer2_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs), - .main_clk = "wd_timer2_fck", - .prcm = { - .omap4 = { - .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, - }, - }, - .slaves = omap44xx_wd_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* wd_timer3 */ -static struct omap_hwmod omap44xx_wd_timer3_hwmod; -static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { - { .irq = 36 + OMAP44XX_IRQ_GIC_START }, -}; - -static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { - { - .pa_start = 0x40130000, - .pa_end = 0x4013007f, - .flags = ADDR_TYPE_RT - }, -}; - -/* l4_per -> uart2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart2_addrs, - .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* uart2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = { - &omap44xx_l4_per__uart2, -}; - -static struct omap_hwmod omap44xx_uart2_hwmod = { - .name = "uart2", - .class = &omap44xx_uart_hwmod_class, - .mpu_irqs = omap44xx_uart2_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs), - .sdma_reqs = omap44xx_uart2_sdma_reqs, - .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs), - .main_clk = "uart2_fck", - .prcm = { - .omap4 = { - .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, - }, - }, - .slaves = omap44xx_uart2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* uart3 */ -static struct omap_hwmod omap44xx_uart3_hwmod; -static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { - { .irq = 74 + OMAP44XX_IRQ_GIC_START }, -}; - -static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { - { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, -}; - -static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { - { - .pa_start = 0x48020000, - .pa_end = 0x480200ff, - .flags = ADDR_TYPE_RT - }, -}; - -/* l4_abe -> wd_timer3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_wd_timer3_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_wd_timer3_addrs, - .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs), - .user = OCP_USER_MPU, -}; - -/* l4_abe -> wd_timer3 (dma) */ -static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { - { - .pa_start = 0x49030000, - .pa_end = 0x4903007f, - .flags = ADDR_TYPE_RT - }, -}; - -/* l4_per -> uart3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart3_addrs, - .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* uart3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { - &omap44xx_l4_per__uart3, -}; - -static struct omap_hwmod omap44xx_uart3_hwmod = { - .name = "uart3", - .class = &omap44xx_uart_hwmod_class, - .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), - .mpu_irqs = omap44xx_uart3_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs), - .sdma_reqs = omap44xx_uart3_sdma_reqs, - .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs), - .main_clk = "uart3_fck", - .prcm = { - .omap4 = { - .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, - }, - }, - .slaves = omap44xx_uart3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* uart4 */ -static struct omap_hwmod omap44xx_uart4_hwmod; -static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { - { .irq = 70 + OMAP44XX_IRQ_GIC_START }, -}; - -static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { - { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, -}; - -static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { - { - .pa_start = 0x4806e000, - .pa_end = 0x4806e0ff, - .flags = ADDR_TYPE_RT - }, -}; - -static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_wd_timer3_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_wd_timer3_dma_addrs, - .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs), - .user = OCP_USER_SDMA, -}; - -/* wd_timer3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { - &omap44xx_l4_abe__wd_timer3, - &omap44xx_l4_abe__wd_timer3_dma, -}; - -static struct omap_hwmod omap44xx_wd_timer3_hwmod = { - .name = "wd_timer3", - .class = &omap44xx_wd_timer_hwmod_class, - .mpu_irqs = omap44xx_wd_timer3_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs), - .main_clk = "wd_timer3_fck", - .prcm = { - .omap4 = { - .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, - }, - }, - .slaves = omap44xx_wd_timer3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* l4_per -> uart4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart4_addrs, - .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* uart4 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = { - &omap44xx_l4_per__uart4, -}; - -static struct omap_hwmod omap44xx_uart4_hwmod = { - .name = "uart4", - .class = &omap44xx_uart_hwmod_class, - .mpu_irqs = omap44xx_uart4_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs), - .sdma_reqs = omap44xx_uart4_sdma_reqs, - .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs), - .main_clk = "uart4_fck", - .prcm = { - .omap4 = { - .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, - }, - }, - .slaves = omap44xx_uart4_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -static __initdata struct omap_hwmod *omap44xx_hwmods[] = { - /* dmm class */ - &omap44xx_dmm_hwmod, - /* emif_fw class */ - &omap44xx_emif_fw_hwmod, - /* l3 class */ - &omap44xx_l3_instr_hwmod, - &omap44xx_l3_main_1_hwmod, - &omap44xx_l3_main_2_hwmod, - &omap44xx_l3_main_3_hwmod, - /* l4 class */ - &omap44xx_l4_abe_hwmod, - &omap44xx_l4_cfg_hwmod, - &omap44xx_l4_per_hwmod, - &omap44xx_l4_wkup_hwmod, - /* mpu_bus class */ - &omap44xx_mpu_private_hwmod, - - /* mpu class */ - &omap44xx_mpu_hwmod, - /* wd_timer class */ - &omap44xx_wd_timer2_hwmod, - &omap44xx_wd_timer3_hwmod, - - /* uart class */ - &omap44xx_uart1_hwmod, - &omap44xx_uart2_hwmod, - &omap44xx_uart3_hwmod, - &omap44xx_uart4_hwmod, - NULL, -}; - -int __init omap44xx_hwmod_init(void) -{ - return omap_hwmod_init(omap44xx_hwmods); -} - diff --git a/trunk/arch/arm/mach-omap2/pm-debug.c b/trunk/arch/arm/mach-omap2/pm-debug.c index 5e81517a7af2..723b44e252fd 100644 --- a/trunk/arch/arm/mach-omap2/pm-debug.c +++ b/trunk/arch/arm/mach-omap2/pm-debug.c @@ -31,17 +31,12 @@ #include #include #include -#include #include "prm.h" #include "cm.h" #include "pm.h" int omap2_pm_debug; -u32 enable_off_mode; -u32 sleep_while_idle; -u32 wakeup_timer_seconds; -u32 wakeup_timer_milliseconds; #define DUMP_PRM_MOD_REG(mod, reg) \ regs[reg_count].name = #mod "." #reg; \ @@ -167,7 +162,7 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) static void pm_dbg_regset_store(u32 *ptr); -static struct dentry *pm_dbg_dir; +struct dentry *pm_dbg_dir; static int pm_dbg_init_done; @@ -354,23 +349,6 @@ void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) pwrdm->timer = t; } -void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds) -{ - u32 tick_rate, cycles; - - if (!seconds && !milliseconds) - return; - - tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); - cycles = tick_rate * seconds + tick_rate * milliseconds / 1000; - omap_dm_timer_stop(gptimer_wakeup); - omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); - - pr_info("PM: Resume timer in %u.%03u secs" - " (%d ticks at %d ticks/sec.)\n", - seconds, milliseconds, cycles, tick_rate); -} - static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user) { struct seq_file *s = (struct seq_file *)user; @@ -516,10 +494,8 @@ int pm_dbg_regset_init(int reg_set) static int pwrdm_suspend_get(void *data, u64 *val) { - int ret = -EINVAL; - - if (cpu_is_omap34xx()) - ret = omap3_pm_get_suspend_state((struct powerdomain *)data); + int ret; + ret = omap3_pm_get_suspend_state((struct powerdomain *)data); *val = ret; if (ret >= 0) @@ -529,10 +505,7 @@ static int pwrdm_suspend_get(void *data, u64 *val) static int pwrdm_suspend_set(void *data, u64 val) { - if (cpu_is_omap34xx()) - return omap3_pm_set_suspend_state( - (struct powerdomain *)data, (int)val); - return -EINVAL; + return omap3_pm_set_suspend_state((struct powerdomain *)data, (int)val); } DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get, @@ -580,10 +553,8 @@ static int option_set(void *data, u64 val) *option = val; - if (option == &enable_off_mode) { - if (cpu_is_omap34xx()) - omap3_pm_off_mode_enable(val); - } + if (option == &enable_off_mode) + omap3_pm_off_mode_enable(val); return 0; } @@ -638,9 +609,6 @@ static int __init pm_dbg_init(void) &sleep_while_idle, &pm_dbg_option_fops); (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d, &wakeup_timer_seconds, &pm_dbg_option_fops); - (void) debugfs_create_file("wakeup_timer_milliseconds", - S_IRUGO | S_IWUGO, d, &wakeup_timer_milliseconds, - &pm_dbg_option_fops); pm_dbg_init_done = 1; return 0; diff --git a/trunk/arch/arm/mach-omap2/pm.c b/trunk/arch/arm/mach-omap2/pm.c index 59ca03b0e691..68f9f2e95891 100644 --- a/trunk/arch/arm/mach-omap2/pm.c +++ b/trunk/arch/arm/mach-omap2/pm.c @@ -18,15 +18,11 @@ #include #include -#include -#include - static struct omap_device_pm_latency *pm_lats; static struct device *mpu_dev; -static struct device *iva_dev; -static struct device *l3_dev; static struct device *dsp_dev; +static struct device *l3_dev; struct device *omap2_get_mpuss_device(void) { @@ -34,10 +30,10 @@ struct device *omap2_get_mpuss_device(void) return mpu_dev; } -struct device *omap2_get_iva_device(void) +struct device *omap2_get_dsp_device(void) { - WARN_ON_ONCE(!iva_dev); - return iva_dev; + WARN_ON_ONCE(!dsp_dev); + return dsp_dev; } struct device *omap2_get_l3_device(void) @@ -46,13 +42,6 @@ struct device *omap2_get_l3_device(void) return l3_dev; } -struct device *omap4_get_dsp_device(void) -{ - WARN_ON_ONCE(!dsp_dev); - return dsp_dev; -} -EXPORT_SYMBOL(omap4_get_dsp_device); - /* static int _init_omap_device(struct omap_hwmod *oh, void *user) */ static int _init_omap_device(char *name, struct device **new_dev) { @@ -80,60 +69,8 @@ static int _init_omap_device(char *name, struct device **new_dev) static void omap2_init_processor_devices(void) { _init_omap_device("mpu", &mpu_dev); - _init_omap_device("iva", &iva_dev); - if (cpu_is_omap44xx()) { - _init_omap_device("l3_main_1", &l3_dev); - _init_omap_device("dsp", &dsp_dev); - } else { - _init_omap_device("l3_main", &l3_dev); - } -} - -/* - * This sets pwrdm state (other than mpu & core. Currently only ON & - * RET are supported. Function is assuming that clkdm doesn't have - * hw_sup mode enabled. - */ -int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state) -{ - u32 cur_state; - int sleep_switch = 0; - int ret = 0; - - if (pwrdm == NULL || IS_ERR(pwrdm)) - return -EINVAL; - - while (!(pwrdm->pwrsts & (1 << state))) { - if (state == PWRDM_POWER_OFF) - return ret; - state--; - } - - cur_state = pwrdm_read_next_pwrst(pwrdm); - if (cur_state == state) - return ret; - - if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { - omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); - sleep_switch = 1; - pwrdm_wait_transition(pwrdm); - } - - ret = pwrdm_set_next_pwrst(pwrdm, state); - if (ret) { - printk(KERN_ERR "Unable to set state of powerdomain: %s\n", - pwrdm->name); - goto err; - } - - if (sleep_switch) { - omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); - pwrdm_wait_transition(pwrdm); - pwrdm_state_switch(pwrdm); - } - -err: - return ret; + _init_omap_device("iva", &dsp_dev); + _init_omap_device("l3_main", &l3_dev); } static int __init omap2_common_pm_init(void) diff --git a/trunk/arch/arm/mach-omap2/pm.h b/trunk/arch/arm/mach-omap2/pm.h index 0d75bfd1fdbe..3de6ece23fc8 100644 --- a/trunk/arch/arm/mach-omap2/pm.h +++ b/trunk/arch/arm/mach-omap2/pm.h @@ -13,11 +13,14 @@ #include +extern u32 enable_off_mode; +extern u32 sleep_while_idle; + extern void *omap3_secure_ram_storage; extern void omap3_pm_off_mode_enable(int); extern void omap_sram_idle(void); extern int omap3_can_sleep(void); -extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state); +extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state); extern int omap3_idle_init(void); struct cpuidle_params { @@ -45,16 +48,10 @@ extern struct omap_dm_timer *gptimer_wakeup; #ifdef CONFIG_PM_DEBUG extern void omap2_pm_dump(int mode, int resume, unsigned int us); -extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds); extern int omap2_pm_debug; -extern u32 enable_off_mode; -extern u32 sleep_while_idle; #else #define omap2_pm_dump(mode, resume, us) do {} while (0); -#define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0); #define omap2_pm_debug 0 -#define enable_off_mode 0 -#define sleep_while_idle 0 #endif #if defined(CONFIG_CPU_IDLE) diff --git a/trunk/arch/arm/mach-omap2/pm24xx.c b/trunk/arch/arm/mach-omap2/pm24xx.c index a40457d81927..6aeedeacdad8 100644 --- a/trunk/arch/arm/mach-omap2/pm24xx.c +++ b/trunk/arch/arm/mach-omap2/pm24xx.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include @@ -47,7 +48,6 @@ #include "cm-regbits-24xx.h" #include "sdrc.h" #include "pm.h" -#include "control.h" #include #include @@ -245,8 +245,6 @@ static int omap2_can_sleep(void) { if (omap2_fclks_active()) return 0; - if (!omap_uart_can_sleep()) - return 0; if (osc_ck->usecount > 1) return 0; if (omap_dma_running()) diff --git a/trunk/arch/arm/mach-omap2/pm34xx.c b/trunk/arch/arm/mach-omap2/pm34xx.c index 75c0cd13ad8e..7b03426c72a3 100644 --- a/trunk/arch/arm/mach-omap2/pm34xx.c +++ b/trunk/arch/arm/mach-omap2/pm34xx.c @@ -32,11 +32,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include @@ -47,12 +49,16 @@ #include "prm.h" #include "pm.h" #include "sdrc.h" -#include "control.h" /* Scratchpad offsets */ -#define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4 -#define OMAP343X_TABLE_VALUE_OFFSET 0xc0 -#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8 +#define OMAP343X_TABLE_ADDRESS_OFFSET 0x31 +#define OMAP343X_TABLE_VALUE_OFFSET 0x30 +#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32 + +u32 enable_off_mode; +u32 sleep_while_idle; +u32 wakeup_timer_seconds; +u32 wakeup_timer_milliseconds; struct power_state { struct powerdomain *pwrdm; @@ -310,7 +316,7 @@ static void restore_control_register(u32 val) /* Function to restore the table entry that was modified for enabling MMU */ static void restore_table_entry(void) { - void __iomem *scratchpad_address; + u32 *scratchpad_address; u32 previous_value, control_reg_value; u32 *address; @@ -345,6 +351,7 @@ void omap_sram_idle(void) int core_next_state = PWRDM_POWER_ON; int core_prev_state, per_prev_state; u32 sdrc_pwr = 0; + int per_state_modified = 0; if (!_omap_sram_idle) return; @@ -378,9 +385,9 @@ void omap_sram_idle(void) /* Enable IO-PAD and IO-CHAIN wakeups */ per_next_state = pwrdm_read_next_pwrst(per_pwrdm); core_next_state = pwrdm_read_next_pwrst(core_pwrdm); - if (omap3_has_io_wakeup() && - (per_next_state < PWRDM_POWER_ON || - core_next_state < PWRDM_POWER_ON)) { + if (omap3_has_io_wakeup() && \ + (per_next_state < PWRDM_POWER_ON || + core_next_state < PWRDM_POWER_ON)) { prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); omap3_enable_io_chain(); } @@ -388,12 +395,20 @@ void omap_sram_idle(void) /* PER */ if (per_next_state < PWRDM_POWER_ON) { omap_uart_prepare_idle(2); - omap_uart_prepare_idle(3); omap2_gpio_prepare_for_idle(per_next_state); - if (per_next_state == PWRDM_POWER_OFF) + if (per_next_state == PWRDM_POWER_OFF) { + if (core_next_state == PWRDM_POWER_ON) { + per_next_state = PWRDM_POWER_RET; + pwrdm_set_next_pwrst(per_pwrdm, per_next_state); + per_state_modified = 1; + } else omap3_per_save_context(); + } } + if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON) + omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]); + /* CORE */ if (core_next_state < PWRDM_POWER_ON) { omap_uart_prepare_idle(0); @@ -460,7 +475,8 @@ void omap_sram_idle(void) if (per_prev_state == PWRDM_POWER_OFF) omap3_per_restore_context(); omap_uart_resume_idle(2); - omap_uart_resume_idle(3); + if (per_state_modified) + pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF); } /* Disable IO-PAD and IO-CHAIN wakeup */ @@ -485,6 +501,51 @@ int omap3_can_sleep(void) return 1; } +/* This sets pwrdm state (other than mpu & core. Currently only ON & + * RET are supported. Function is assuming that clkdm doesn't have + * hw_sup mode enabled. */ +int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) +{ + u32 cur_state; + int sleep_switch = 0; + int ret = 0; + + if (pwrdm == NULL || IS_ERR(pwrdm)) + return -EINVAL; + + while (!(pwrdm->pwrsts & (1 << state))) { + if (state == PWRDM_POWER_OFF) + return ret; + state--; + } + + cur_state = pwrdm_read_next_pwrst(pwrdm); + if (cur_state == state) + return ret; + + if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { + omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); + sleep_switch = 1; + pwrdm_wait_transition(pwrdm); + } + + ret = pwrdm_set_next_pwrst(pwrdm, state); + if (ret) { + printk(KERN_ERR "Unable to set state of powerdomain: %s\n", + pwrdm->name); + goto err; + } + + if (sleep_switch) { + omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); + pwrdm_wait_transition(pwrdm); + pwrdm_state_switch(pwrdm); + } + +err: + return ret; +} + static void omap3_pm_idle(void) { local_irq_disable(); @@ -506,6 +567,23 @@ static void omap3_pm_idle(void) #ifdef CONFIG_SUSPEND static suspend_state_t suspend_state; +static void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds) +{ + u32 tick_rate, cycles; + + if (!seconds && !milliseconds) + return; + + tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); + cycles = tick_rate * seconds + tick_rate * milliseconds / 1000; + omap_dm_timer_stop(gptimer_wakeup); + omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); + + pr_info("PM: Resume timer in %u.%03u secs" + " (%d ticks at %d ticks/sec.)\n", + seconds, milliseconds, cycles, tick_rate); +} + static int omap3_pm_prepare(void) { disable_hlt(); @@ -526,7 +604,7 @@ static int omap3_pm_suspend(void) pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); /* Set ones wanted by suspend */ list_for_each_entry(pwrst, &pwrst_list, node) { - if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) + if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) goto restore; if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) goto restore; @@ -547,7 +625,7 @@ static int omap3_pm_suspend(void) pwrst->pwrdm->name, pwrst->next_state); ret = -1; } - omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); + set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); } if (ret) printk(KERN_ERR "Could not enter target state in pm_suspend\n"); @@ -678,14 +756,6 @@ static void __init omap3_d2d_idle(void) static void __init prcm_setup_regs(void) { - u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ? - OMAP3630_AUTO_UART4_MASK : 0; - u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? - OMAP3630_EN_UART4_MASK : 0; - u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? - OMAP3630_GRPSEL_UART4_MASK : 0; - - /* XXX Reset all wkdeps. This should be done when initializing * powerdomains */ prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); @@ -772,7 +842,6 @@ static void __init prcm_setup_regs(void) CM_AUTOIDLE); cm_write_mod_reg( - omap3630_auto_uart4_mask | OMAP3430_AUTO_GPIO6_MASK | OMAP3430_AUTO_GPIO5_MASK | OMAP3430_AUTO_GPIO4_MASK | @@ -849,16 +918,14 @@ static void __init prcm_setup_regs(void) OMAP3430_DSS_MOD, PM_WKEN); /* Enable wakeups in PER */ - prm_write_mod_reg(omap3630_en_uart4_mask | - OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | + prm_write_mod_reg(OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | OMAP3430_EN_MCBSP4_MASK, OMAP3430_PER_MOD, PM_WKEN); /* and allow them to wake up MPU */ - prm_write_mod_reg(omap3630_grpsel_uart4_mask | - OMAP3430_GRPSEL_GPIO2_MASK | + prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK | OMAP3430_GRPSEL_GPIO3_MASK | OMAP3430_GRPSEL_GPIO4_MASK | OMAP3430_GRPSEL_GPIO5_MASK | @@ -907,7 +974,7 @@ void omap3_pm_off_mode_enable(int enable) list_for_each_entry(pwrst, &pwrst_list, node) { pwrst->next_state = state; - omap_set_pwrdm_state(pwrst->pwrdm, state); + set_pwrdm_state(pwrst->pwrdm, state); } } @@ -952,7 +1019,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) if (pwrdm_has_hdwr_sar(pwrdm)) pwrdm_enable_hdwr_sar(pwrdm); - return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); + return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); } /* @@ -962,6 +1029,9 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) */ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) { + clkdm_clear_all_wkdeps(clkdm); + clkdm_clear_all_sleepdeps(clkdm); + if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) omap2_clkdm_allow_idle(clkdm); else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && diff --git a/trunk/arch/arm/mach-omap2/pm_bus.c b/trunk/arch/arm/mach-omap2/pm_bus.c deleted file mode 100644 index 784989f8f2f5..000000000000 --- a/trunk/arch/arm/mach-omap2/pm_bus.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Runtime PM support code for OMAP - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * Copyright (C) 2010 Texas Instruments, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include -#include -#include -#include -#include -#include - -#include -#include - -#ifdef CONFIG_PM_RUNTIME -int omap_pm_runtime_suspend(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - int r, ret = 0; - - dev_dbg(dev, "%s\n", __func__); - - ret = pm_generic_runtime_suspend(dev); - - if (!ret && dev->parent == &omap_device_parent) { - r = omap_device_idle(pdev); - WARN_ON(r); - } - - return ret; -}; - -int omap_pm_runtime_resume(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - int r; - - dev_dbg(dev, "%s\n", __func__); - - if (dev->parent == &omap_device_parent) { - r = omap_device_enable(pdev); - WARN_ON(r); - } - - return pm_generic_runtime_resume(dev); -}; -#else -#define omap_pm_runtime_suspend NULL -#define omap_pm_runtime_resume NULL -#endif /* CONFIG_PM_RUNTIME */ - -static int __init omap_pm_runtime_init(void) -{ - const struct dev_pm_ops *pm; - struct dev_pm_ops *omap_pm; - - pm = platform_bus_get_pm_ops(); - if (!pm) { - pr_err("%s: unable to get dev_pm_ops from platform_bus\n", - __func__); - return -ENODEV; - } - - omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL); - if (!omap_pm) { - pr_err("%s: unable to alloc memory for new dev_pm_ops\n", - __func__); - return -ENOMEM; - } - - omap_pm->runtime_suspend = omap_pm_runtime_suspend; - omap_pm->runtime_resume = omap_pm_runtime_resume; - - platform_bus_set_pm_ops(omap_pm); - - return 0; -} -core_initcall(omap_pm_runtime_init); diff --git a/trunk/arch/arm/mach-omap2/powerdomains44xx.h b/trunk/arch/arm/mach-omap2/powerdomains44xx.h index 9c01b55d6102..c7219513472a 100644 --- a/trunk/arch/arm/mach-omap2/powerdomains44xx.h +++ b/trunk/arch/arm/mach-omap2/powerdomains44xx.h @@ -98,7 +98,7 @@ static struct powerdomain dss_44xx_pwrdm = { .prcm_offs = OMAP4430_PRM_DSS_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF, + .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 1, .pwrsts_mem_ret = { [0] = PWRDM_POWER_OFF, /* dss_mem */ diff --git a/trunk/arch/arm/mach-omap2/prcm-common.h b/trunk/arch/arm/mach-omap2/prcm-common.h index 298a22a754e2..995b7edbf18d 100644 --- a/trunk/arch/arm/mach-omap2/prcm-common.h +++ b/trunk/arch/arm/mach-omap2/prcm-common.h @@ -382,9 +382,6 @@ #define OMAP3430_EN_MPU_SHIFT 1 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ - -#define OMAP3630_EN_UART4_MASK (1 << 18) -#define OMAP3630_EN_UART4_SHIFT 18 #define OMAP3430_EN_GPIO6_MASK (1 << 17) #define OMAP3430_EN_GPIO6_SHIFT 17 #define OMAP3430_EN_GPIO5_MASK (1 << 16) @@ -425,8 +422,6 @@ #define OMAP3430_EN_MCBSP2_SHIFT 0 /* CM_IDLEST_PER, PM_WKST_PER shared bits */ -#define OMAP3630_ST_UART4_SHIFT 18 -#define OMAP3630_ST_UART4_MASK (1 << 18) #define OMAP3430_ST_GPIO6_SHIFT 17 #define OMAP3430_ST_GPIO6_MASK (1 << 17) #define OMAP3430_ST_GPIO5_SHIFT 16 diff --git a/trunk/arch/arm/mach-omap2/prcm.c b/trunk/arch/arm/mach-omap2/prcm.c index a51846e3a6fa..c20137497c92 100644 --- a/trunk/arch/arm/mach-omap2/prcm.c +++ b/trunk/arch/arm/mach-omap2/prcm.c @@ -26,14 +26,13 @@ #include #include #include +#include #include "clock.h" #include "clock2xxx.h" #include "cm.h" #include "prm.h" #include "prm-regbits-24xx.h" -#include "prm-regbits-44xx.h" -#include "control.h" static void __iomem *prm_base; static void __iomem *cm_base; @@ -119,7 +118,7 @@ struct omap3_prcm_regs { u32 wkup_pm_wken; }; -static struct omap3_prcm_regs prcm_context; +struct omap3_prcm_regs prcm_context; u32 omap_prcm_get_reset_sources(void) { @@ -162,8 +161,8 @@ void omap_prcm_arch_reset(char mode, const char *cmd) prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, OMAP2_RM_RSTCTRL); if (cpu_is_omap44xx()) - prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK, - prcm_offs, OMAP4_RM_RSTCTRL); + prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, + OMAP4_RM_RSTCTRL); } static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) @@ -216,30 +215,6 @@ u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) return v; } -/* Read a PRM register, AND it, and shift the result down to bit 0 */ -u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask) -{ - u32 v; - - v = __raw_readl(reg); - v &= mask; - v >>= __ffs(mask); - - return v; -} - -/* Read-modify-write a register in a PRM module. Caller must lock */ -u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg) -{ - u32 v; - - v = __raw_readl(reg); - v &= ~mask; - v |= bits; - __raw_writel(v, reg); - - return v; -} /* Read a register in a CM module */ u32 cm_read_mod_reg(s16 module, u16 idx) { diff --git a/trunk/arch/arm/mach-omap2/prm-regbits-34xx.h b/trunk/arch/arm/mach-omap2/prm-regbits-34xx.h index 9e63cb743a97..7fd6023edf96 100644 --- a/trunk/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/trunk/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -122,7 +122,6 @@ #define OMAP3430_MEMRETSTATE_MASK (1 << 8) /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */ -#define OMAP3630_GRPSEL_UART4_MASK (1 << 18) #define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17) #define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16) #define OMAP3430_GRPSEL_GPIO4_MASK (1 << 15) diff --git a/trunk/arch/arm/mach-omap2/prm-regbits-44xx.h b/trunk/arch/arm/mach-omap2/prm-regbits-44xx.h index 25b19b610177..597be4a2b9ff 100644 --- a/trunk/arch/arm/mach-omap2/prm-regbits-44xx.h +++ b/trunk/arch/arm/mach-omap2/prm-regbits-44xx.h @@ -1,8 +1,8 @@ /* * OMAP44xx Power Management register bits * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * Copyright (C) 2009-2010 Nokia Corporation + * Copyright (C) 2009 Texas Instruments, Inc. + * Copyright (C) 2009 Nokia Corporation * * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) @@ -30,611 +30,587 @@ * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1 -#define OMAP4430_ABBOFF_ACT_EXPORT_MASK (1 << 1) +#define OMAP4430_ABBOFF_ACT_EXPORT_MASK BITFIELD(1, 1) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2 -#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) +#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK BITFIELD(2, 2) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31 -#define OMAP4430_ABB_IVA_DONE_EN_MASK (1 << 31) +#define OMAP4430_ABB_IVA_DONE_EN_MASK BITFIELD(31, 31) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31 -#define OMAP4430_ABB_IVA_DONE_ST_MASK (1 << 31) +#define OMAP4430_ABB_IVA_DONE_ST_MASK BITFIELD(31, 31) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7 -#define OMAP4430_ABB_MPU_DONE_EN_MASK (1 << 7) +#define OMAP4430_ABB_MPU_DONE_EN_MASK BITFIELD(7, 7) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7 -#define OMAP4430_ABB_MPU_DONE_ST_MASK (1 << 7) +#define OMAP4430_ABB_MPU_DONE_ST_MASK BITFIELD(7, 7) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2 -#define OMAP4430_ACTIVE_FBB_SEL_MASK (1 << 2) +#define OMAP4430_ACTIVE_FBB_SEL_MASK BITFIELD(2, 2) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1 -#define OMAP4430_ACTIVE_RBB_SEL_MASK (1 << 1) +#define OMAP4430_ACTIVE_RBB_SEL_MASK BITFIELD(1, 1) /* Used by PM_ABE_PWRSTCTRL */ #define OMAP4430_AESSMEM_ONSTATE_SHIFT 16 -#define OMAP4430_AESSMEM_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_AESSMEM_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_ABE_PWRSTCTRL */ #define OMAP4430_AESSMEM_RETSTATE_SHIFT 8 -#define OMAP4430_AESSMEM_RETSTATE_MASK (1 << 8) +#define OMAP4430_AESSMEM_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_ABE_PWRSTST */ #define OMAP4430_AESSMEM_STATEST_SHIFT 4 -#define OMAP4430_AESSMEM_STATEST_MASK (0x3 << 4) +#define OMAP4430_AESSMEM_STATEST_MASK BITFIELD(4, 5) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_AIPOFF_SHIFT 8 -#define OMAP4430_AIPOFF_MASK (1 << 8) +#define OMAP4430_AIPOFF_MASK BITFIELD(8, 8) /* Used by PRM_VOLTCTRL */ #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0 -#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) +#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK BITFIELD(0, 1) /* Used by PRM_VOLTCTRL */ #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4 -#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK (0x3 << 4) +#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK BITFIELD(4, 5) /* Used by PRM_VOLTCTRL */ #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2 -#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_BYPS_RA_ERR_SHIFT 25 -#define OMAP4430_BYPS_RA_ERR_MASK (1 << 25) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_BYPS_SA_ERR_SHIFT 24 -#define OMAP4430_BYPS_SA_ERR_MASK (1 << 24) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT 26 -#define OMAP4430_BYPS_TIMEOUT_ERR_MASK (1 << 26) - -/* Used by PRM_RSTST */ -#define OMAP4430_C2C_RST_SHIFT 10 -#define OMAP4430_C2C_RST_MASK (1 << 10) +#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK BITFIELD(2, 3) /* Used by PM_CAM_PWRSTCTRL */ #define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_CAM_MEM_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_CAM_MEM_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_CAM_PWRSTST */ #define OMAP4430_CAM_MEM_STATEST_SHIFT 4 -#define OMAP4430_CAM_MEM_STATEST_MASK (0x3 << 4) +#define OMAP4430_CAM_MEM_STATEST_MASK BITFIELD(4, 5) /* Used by PRM_CLKREQCTRL */ #define OMAP4430_CLKREQ_COND_SHIFT 0 -#define OMAP4430_CLKREQ_COND_MASK (0x7 << 0) +#define OMAP4430_CLKREQ_COND_MASK BITFIELD(0, 2) /* Used by PRM_VC_VAL_SMPS_RA_CMD */ #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0 -#define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) +#define OMAP4430_CMDRA_VDD_CORE_L_MASK BITFIELD(0, 7) /* Used by PRM_VC_VAL_SMPS_RA_CMD */ #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8 -#define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) +#define OMAP4430_CMDRA_VDD_IVA_L_MASK BITFIELD(8, 15) /* Used by PRM_VC_VAL_SMPS_RA_CMD */ #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16 -#define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) +#define OMAP4430_CMDRA_VDD_MPU_L_MASK BITFIELD(16, 23) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_CMD_VDD_CORE_L_SHIFT 4 -#define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4) +#define OMAP4430_CMD_VDD_CORE_L_MASK BITFIELD(4, 4) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_CMD_VDD_IVA_L_SHIFT 12 -#define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12) +#define OMAP4430_CMD_VDD_IVA_L_MASK BITFIELD(12, 12) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_CMD_VDD_MPU_L_SHIFT 17 -#define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17) +#define OMAP4430_CMD_VDD_MPU_L_MASK BITFIELD(17, 17) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18 -#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) +#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK BITFIELD(18, 19) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9 -#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9) +#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK BITFIELD(9, 9) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6 -#define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6) +#define OMAP4430_CORE_OCMRAM_STATEST_MASK BITFIELD(6, 7) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8 -#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) +#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4 -#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) - -/* Used by REVISION_PRM */ -#define OMAP4430_CUSTOM_SHIFT 6 -#define OMAP4430_CUSTOM_MASK (0x3 << 6) +#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK BITFIELD(4, 5) /* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_DATA_SHIFT 16 -#define OMAP4430_DATA_MASK (0xff << 16) +#define OMAP4430_DATA_MASK BITFIELD(16, 23) /* Used by PRM_DEVICE_OFF_CTRL */ #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0 -#define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0) +#define OMAP4430_DEVICE_OFF_ENABLE_MASK BITFIELD(0, 0) /* Used by PRM_VC_CFG_I2C_MODE */ #define OMAP4430_DFILTEREN_SHIFT 6 -#define OMAP4430_DFILTEREN_MASK (1 << 6) +#define OMAP4430_DFILTEREN_MASK BITFIELD(6, 6) -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP - */ -#define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0 -#define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ +/* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4 -#define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4) +#define OMAP4430_DPLL_ABE_RECAL_EN_MASK BITFIELD(4, 4) -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ +/* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4 -#define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4) +#define OMAP4430_DPLL_ABE_RECAL_ST_MASK BITFIELD(4, 4) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0 -#define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0) +#define OMAP4430_DPLL_CORE_RECAL_EN_MASK BITFIELD(0, 0) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0 -#define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0) +#define OMAP4430_DPLL_CORE_RECAL_ST_MASK BITFIELD(0, 0) /* Used by PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6 -#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6) +#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK BITFIELD(6, 6) /* Used by PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6 -#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6) +#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK BITFIELD(6, 6) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2 -#define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2) +#define OMAP4430_DPLL_IVA_RECAL_EN_MASK BITFIELD(2, 2) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2 -#define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2) +#define OMAP4430_DPLL_IVA_RECAL_ST_MASK BITFIELD(2, 2) /* Used by PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1 -#define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1) +#define OMAP4430_DPLL_MPU_RECAL_EN_MASK BITFIELD(1, 1) /* Used by PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1 -#define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1) +#define OMAP4430_DPLL_MPU_RECAL_ST_MASK BITFIELD(1, 1) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3 -#define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3) +#define OMAP4430_DPLL_PER_RECAL_EN_MASK BITFIELD(3, 3) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3 -#define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3) +#define OMAP4430_DPLL_PER_RECAL_ST_MASK BITFIELD(3, 3) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7 -#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7) +#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK BITFIELD(7, 7) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7 -#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7) +#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK BITFIELD(7, 7) + +/* Used by PRM_IRQENABLE_MPU */ +#define OMAP4430_DPLL_USB_RECAL_EN_SHIFT 5 +#define OMAP4430_DPLL_USB_RECAL_EN_MASK BITFIELD(5, 5) + +/* Used by PRM_IRQSTATUS_MPU */ +#define OMAP4430_DPLL_USB_RECAL_ST_SHIFT 5 +#define OMAP4430_DPLL_USB_RECAL_ST_MASK BITFIELD(5, 5) /* Used by PM_DSS_PWRSTCTRL */ #define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_DSS_MEM_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_DSS_PWRSTCTRL */ #define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8 -#define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8) +#define OMAP4430_DSS_MEM_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_DSS_PWRSTST */ #define OMAP4430_DSS_MEM_STATEST_SHIFT 4 -#define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4) +#define OMAP4430_DSS_MEM_STATEST_MASK BITFIELD(4, 5) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20 -#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20) +#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK BITFIELD(20, 21) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10 -#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10) +#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK BITFIELD(10, 10) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8 -#define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8) +#define OMAP4430_DUCATI_L2RAM_STATEST_MASK BITFIELD(8, 9) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22 -#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22) +#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK BITFIELD(22, 23) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11 -#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11) +#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK BITFIELD(11, 11) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 -#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10) +#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK BITFIELD(10, 11) /* Used by RM_MPU_RSTST */ #define OMAP4430_EMULATION_RST_SHIFT 0 -#define OMAP4430_EMULATION_RST_MASK (1 << 0) +#define OMAP4430_EMULATION_RST_MASK BITFIELD(0, 0) /* Used by RM_DUCATI_RSTST */ #define OMAP4430_EMULATION_RST1ST_SHIFT 3 -#define OMAP4430_EMULATION_RST1ST_MASK (1 << 3) +#define OMAP4430_EMULATION_RST1ST_MASK BITFIELD(3, 3) /* Used by RM_DUCATI_RSTST */ #define OMAP4430_EMULATION_RST2ST_SHIFT 4 -#define OMAP4430_EMULATION_RST2ST_MASK (1 << 4) +#define OMAP4430_EMULATION_RST2ST_MASK BITFIELD(4, 4) /* Used by RM_IVAHD_RSTST */ #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3 -#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3) +#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK BITFIELD(3, 3) /* Used by RM_IVAHD_RSTST */ #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4 -#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4) +#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK BITFIELD(4, 4) /* Used by PM_EMU_PWRSTCTRL */ #define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_EMU_BANK_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_EMU_PWRSTST */ #define OMAP4430_EMU_BANK_STATEST_SHIFT 4 -#define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4) +#define OMAP4430_EMU_BANK_STATEST_MASK BITFIELD(4, 5) + +/* + * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, + * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP + */ +#define OMAP4430_ENABLE_RTA_EXPORT_SHIFT 0 +#define OMAP4430_ENABLE_RTA_EXPORT_MASK BITFIELD(0, 0) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ -#define OMAP4430_ENFUNC1_EXPORT_SHIFT 3 -#define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3) +#define OMAP4430_ENFUNC1_SHIFT 3 +#define OMAP4430_ENFUNC1_MASK BITFIELD(3, 3) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ -#define OMAP4430_ENFUNC3_EXPORT_SHIFT 5 -#define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5) +#define OMAP4430_ENFUNC3_SHIFT 5 +#define OMAP4430_ENFUNC3_MASK BITFIELD(5, 5) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_ENFUNC4_SHIFT 6 -#define OMAP4430_ENFUNC4_MASK (1 << 6) +#define OMAP4430_ENFUNC4_MASK BITFIELD(6, 6) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_ENFUNC5_SHIFT 7 -#define OMAP4430_ENFUNC5_MASK (1 << 7) +#define OMAP4430_ENFUNC5_MASK BITFIELD(7, 7) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_ERRORGAIN_SHIFT 16 -#define OMAP4430_ERRORGAIN_MASK (0xff << 16) +#define OMAP4430_ERRORGAIN_MASK BITFIELD(16, 23) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_ERROROFFSET_SHIFT 24 -#define OMAP4430_ERROROFFSET_MASK (0xff << 24) +#define OMAP4430_ERROROFFSET_MASK BITFIELD(24, 31) /* Used by PRM_RSTST */ #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 -#define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5) +#define OMAP4430_EXTERNAL_WARM_RST_MASK BITFIELD(5, 5) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_FORCEUPDATE_SHIFT 1 -#define OMAP4430_FORCEUPDATE_MASK (1 << 1) +#define OMAP4430_FORCEUPDATE_MASK BITFIELD(1, 1) /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ #define OMAP4430_FORCEUPDATEWAIT_SHIFT 8 -#define OMAP4430_FORCEUPDATEWAIT_MASK (0xffffff << 8) +#define OMAP4430_FORCEUPDATEWAIT_MASK BITFIELD(8, 31) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ #define OMAP4430_FORCEWKUP_EN_SHIFT 10 -#define OMAP4430_FORCEWKUP_EN_MASK (1 << 10) +#define OMAP4430_FORCEWKUP_EN_MASK BITFIELD(10, 10) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ #define OMAP4430_FORCEWKUP_ST_SHIFT 10 -#define OMAP4430_FORCEWKUP_ST_MASK (1 << 10) - -/* Used by REVISION_PRM */ -#define OMAP4430_FUNC_SHIFT 16 -#define OMAP4430_FUNC_MASK (0xfff << 16) +#define OMAP4430_FORCEWKUP_ST_MASK BITFIELD(10, 10) /* Used by PM_GFX_PWRSTCTRL */ #define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_GFX_MEM_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_GFX_MEM_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_GFX_PWRSTST */ #define OMAP4430_GFX_MEM_STATEST_SHIFT 4 -#define OMAP4430_GFX_MEM_STATEST_MASK (0x3 << 4) +#define OMAP4430_GFX_MEM_STATEST_MASK BITFIELD(4, 5) /* Used by PRM_RSTST */ #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 -#define OMAP4430_GLOBAL_COLD_RST_MASK (1 << 0) +#define OMAP4430_GLOBAL_COLD_RST_MASK BITFIELD(0, 0) /* Used by PRM_RSTST */ #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 -#define OMAP4430_GLOBAL_WARM_SW_RST_MASK (1 << 1) +#define OMAP4430_GLOBAL_WARM_SW_RST_MASK BITFIELD(1, 1) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_GLOBAL_WUEN_SHIFT 16 -#define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) +#define OMAP4430_GLOBAL_WUEN_MASK BITFIELD(16, 16) /* Used by PRM_VC_CFG_I2C_MODE */ #define OMAP4430_HSMCODE_SHIFT 0 -#define OMAP4430_HSMCODE_MASK (0x7 << 0) +#define OMAP4430_HSMCODE_MASK BITFIELD(0, 2) /* Used by PRM_VC_CFG_I2C_MODE */ #define OMAP4430_HSMODEEN_SHIFT 3 -#define OMAP4430_HSMODEEN_MASK (1 << 3) +#define OMAP4430_HSMODEEN_MASK BITFIELD(3, 3) /* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_HSSCLH_SHIFT 16 -#define OMAP4430_HSSCLH_MASK (0xff << 16) +#define OMAP4430_HSSCLH_MASK BITFIELD(16, 23) /* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_HSSCLL_SHIFT 24 -#define OMAP4430_HSSCLL_MASK (0xff << 24) +#define OMAP4430_HSSCLL_MASK BITFIELD(24, 31) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_HWA_MEM_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_HWA_MEM_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8 -#define OMAP4430_HWA_MEM_RETSTATE_MASK (1 << 8) +#define OMAP4430_HWA_MEM_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_IVAHD_PWRSTST */ #define OMAP4430_HWA_MEM_STATEST_SHIFT 4 -#define OMAP4430_HWA_MEM_STATEST_MASK (0x3 << 4) +#define OMAP4430_HWA_MEM_STATEST_MASK BITFIELD(4, 5) /* Used by RM_MPU_RSTST */ #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1 -#define OMAP4430_ICECRUSHER_MPU_RST_MASK (1 << 1) +#define OMAP4430_ICECRUSHER_MPU_RST_MASK BITFIELD(1, 1) /* Used by RM_DUCATI_RSTST */ #define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5 -#define OMAP4430_ICECRUSHER_RST1ST_MASK (1 << 5) +#define OMAP4430_ICECRUSHER_RST1ST_MASK BITFIELD(5, 5) /* Used by RM_DUCATI_RSTST */ #define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6 -#define OMAP4430_ICECRUSHER_RST2ST_MASK (1 << 6) +#define OMAP4430_ICECRUSHER_RST2ST_MASK BITFIELD(6, 6) /* Used by RM_IVAHD_RSTST */ #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5 -#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK (1 << 5) +#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK BITFIELD(5, 5) /* Used by RM_IVAHD_RSTST */ #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6 -#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK (1 << 6) +#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK BITFIELD(6, 6) /* Used by PRM_RSTST */ #define OMAP4430_ICEPICK_RST_SHIFT 9 -#define OMAP4430_ICEPICK_RST_MASK (1 << 9) +#define OMAP4430_ICEPICK_RST_MASK BITFIELD(9, 9) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_INITVDD_SHIFT 2 -#define OMAP4430_INITVDD_MASK (1 << 2) +#define OMAP4430_INITVDD_MASK BITFIELD(2, 2) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_INITVOLTAGE_SHIFT 8 -#define OMAP4430_INITVOLTAGE_MASK (0xff << 8) +#define OMAP4430_INITVOLTAGE_MASK BITFIELD(8, 15) /* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, - * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, - * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST + * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, + * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, + * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST */ #define OMAP4430_INTRANSITION_SHIFT 20 -#define OMAP4430_INTRANSITION_MASK (1 << 20) +#define OMAP4430_INTRANSITION_MASK BITFIELD(20, 20) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_IO_EN_SHIFT 9 -#define OMAP4430_IO_EN_MASK (1 << 9) +#define OMAP4430_IO_EN_MASK BITFIELD(9, 9) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_IO_ON_STATUS_SHIFT 5 -#define OMAP4430_IO_ON_STATUS_MASK (1 << 5) +#define OMAP4430_IO_ON_STATUS_MASK BITFIELD(5, 5) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_IO_ST_SHIFT 9 -#define OMAP4430_IO_ST_MASK (1 << 9) +#define OMAP4430_IO_ST_MASK BITFIELD(9, 9) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0 -#define OMAP4430_ISOCLK_OVERRIDE_MASK (1 << 0) +#define OMAP4430_ISOCLK_OVERRIDE_MASK BITFIELD(0, 0) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_ISOCLK_STATUS_SHIFT 1 -#define OMAP4430_ISOCLK_STATUS_MASK (1 << 1) +#define OMAP4430_ISOCLK_STATUS_MASK BITFIELD(1, 1) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_ISOOVR_EXTEND_SHIFT 4 -#define OMAP4430_ISOOVR_EXTEND_MASK (1 << 4) +#define OMAP4430_ISOOVR_EXTEND_MASK BITFIELD(4, 4) /* Used by PRM_IO_COUNT */ #define OMAP4430_ISO_2_ON_TIME_SHIFT 0 -#define OMAP4430_ISO_2_ON_TIME_MASK (0xff << 0) +#define OMAP4430_ISO_2_ON_TIME_MASK BITFIELD(0, 7) /* Used by PM_L3INIT_PWRSTCTRL */ #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16 -#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_L3INIT_PWRSTCTRL */ #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8 -#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK (1 << 8) +#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_L3INIT_PWRSTST */ #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4 -#define OMAP4430_L3INIT_BANK1_STATEST_MASK (0x3 << 4) - -/* - * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST, - * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST - */ -#define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 -#define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) +#define OMAP4430_L3INIT_BANK1_STATEST_MASK BITFIELD(4, 5) /* - * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, - * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, - * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL + * Used by PM_CORE_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, + * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, + * PM_IVAHD_PWRSTCTRL */ #define OMAP4430_LOGICRETSTATE_SHIFT 2 -#define OMAP4430_LOGICRETSTATE_MASK (1 << 2) +#define OMAP4430_LOGICRETSTATE_MASK BITFIELD(2, 2) /* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, - * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, - * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST + * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, + * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, + * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST */ #define OMAP4430_LOGICSTATEST_SHIFT 2 -#define OMAP4430_LOGICSTATEST_MASK (1 << 2) +#define OMAP4430_LOGICSTATEST_MASK BITFIELD(2, 2) /* - * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, - * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, - * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, - * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, - * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT, - * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT, - * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT, - * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, - * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT, - * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, + * Used by RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, + * RM_WKUP_L4WKUP_CONTEXT, RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, + * RM_WKUP_SYNCTIMER_CONTEXT, RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, + * RM_WKUP_USIM_CONTEXT, RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT, + * RM_EMU_DEBUGSS_CONTEXT, RM_D2D_SAD2D_CONTEXT, RM_D2D_SAD2D_FW_CONTEXT, + * RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, + * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_OCP_WP1_CONTEXT, + * RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, RM_L3_2_OCMC_RAM_CONTEXT, + * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, RM_MEMIF_DLL_CONTEXT, + * RM_MEMIF_DLL_H_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, + * RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, - * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT, - * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, - * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, - * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT, - * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT, - * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT, - * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, - * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT, - * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT, - * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT, - * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT, - * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT, - * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT, - * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, - * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT, - * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, - * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT, - * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT, - * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT, - * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT, - * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT + * RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, + * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, + * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, + * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, + * RM_ABE_WDT3_CONTEXT, RM_GFX_GFX_CONTEXT, RM_MPU_MPU_CONTEXT, + * RM_CEFUSE_CEFUSE_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, + * RM_ALWON_SR_CORE_CONTEXT, RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, + * RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, RM_L4PER_ADC_CONTEXT, + * RM_L4PER_DMTIMER10_CONTEXT, RM_L4PER_DMTIMER11_CONTEXT, + * RM_L4PER_DMTIMER2_CONTEXT, RM_L4PER_DMTIMER3_CONTEXT, + * RM_L4PER_DMTIMER4_CONTEXT, RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, + * RM_L4PER_HDQ1W_CONTEXT, RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, + * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, + * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, + * RM_L4PER_MCASP3_CONTEXT, RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, + * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, + * RM_L4PER_MGATE_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, + * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_MSPROHG_CONTEXT, + * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT, + * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT */ #define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0 -#define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) +#define OMAP4430_LOSTCONTEXT_DFF_MASK BITFIELD(0, 0) /* * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT, - * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, - * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, - * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT, - * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT, - * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, + * RM_D2D_SAD2D_FW_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT, * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, - * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, - * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, - * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, - * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, - * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, - * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, - * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, - * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, - * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT + * RM_L4CFG_MAILBOX_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, + * RM_MEMIF_EMIF_2_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, + * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_L3INIT_HSI_CONTEXT, + * RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_MMC6_CONTEXT, + * RM_L3INIT_USB_HOST_CONTEXT, RM_L3INIT_USB_HOST_FS_CONTEXT, + * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_USB_TLL_CONTEXT, RM_DSS_DSS_CONTEXT, + * RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, RM_L4PER_GPIO4_CONTEXT, + * RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, RM_L4PER_I2C1_CONTEXT, + * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, + * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4SEC_AES1_CONTEXT, + * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT, + * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT */ #define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1 -#define OMAP4430_LOSTCONTEXT_RFF_MASK (1 << 1) +#define OMAP4430_LOSTCONTEXT_RFF_MASK BITFIELD(1, 1) /* Used by RM_ABE_AESS_CONTEXT */ #define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8 -#define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) +#define OMAP4430_LOSTMEM_AESSMEM_MASK BITFIELD(8, 8) /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_CAM_MEM_MASK (1 << 8) +#define OMAP4430_LOSTMEM_CAM_MEM_MASK BITFIELD(8, 8) /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8) +#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK BITFIELD(8, 8) /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9 -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK (1 << 9) +#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK BITFIELD(9, 9) /* Used by RM_L3_2_OCMC_RAM_CONTEXT */ #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) +#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK BITFIELD(8, 8) /* * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, * RM_SDMA_SDMA_CONTEXT */ #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) +#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK BITFIELD(8, 8) /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_DSS_MEM_MASK (1 << 8) +#define OMAP4430_LOSTMEM_DSS_MEM_MASK BITFIELD(8, 8) /* Used by RM_DUCATI_DUCATI_CONTEXT */ #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9 -#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK (1 << 9) +#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK BITFIELD(9, 9) /* Used by RM_DUCATI_DUCATI_CONTEXT */ #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8 -#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK (1 << 8) +#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK BITFIELD(8, 8) /* Used by RM_EMU_DEBUGSS_CONTEXT */ #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_EMU_BANK_MASK (1 << 8) +#define OMAP4430_LOSTMEM_EMU_BANK_MASK BITFIELD(8, 8) /* Used by RM_GFX_GFX_CONTEXT */ #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_GFX_MEM_MASK (1 << 8) +#define OMAP4430_LOSTMEM_GFX_MEM_MASK BITFIELD(8, 8) /* Used by RM_IVAHD_IVAHD_CONTEXT */ #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10 -#define OMAP4430_LOSTMEM_HWA_MEM_MASK (1 << 10) +#define OMAP4430_LOSTMEM_HWA_MEM_MASK BITFIELD(10, 10) /* * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT, @@ -644,19 +620,19 @@ * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT */ #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8 -#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) +#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK BITFIELD(8, 8) /* Used by RM_MPU_MPU_CONTEXT */ #define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8 -#define OMAP4430_LOSTMEM_MPU_L1_MASK (1 << 8) +#define OMAP4430_LOSTMEM_MPU_L1_MASK BITFIELD(8, 8) /* Used by RM_MPU_MPU_CONTEXT */ #define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9 -#define OMAP4430_LOSTMEM_MPU_L2_MASK (1 << 9) +#define OMAP4430_LOSTMEM_MPU_L2_MASK BITFIELD(9, 9) /* Used by RM_MPU_MPU_CONTEXT */ #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10 -#define OMAP4430_LOSTMEM_MPU_RAM_MASK (1 << 10) +#define OMAP4430_LOSTMEM_MPU_RAM_MASK BITFIELD(10, 10) /* * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, @@ -664,14 +640,14 @@ * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT */ #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) +#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK BITFIELD(8, 8) /* * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT */ #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8 -#define OMAP4430_LOSTMEM_PERIHPMEM_MASK (1 << 8) +#define OMAP4430_LOSTMEM_PERIHPMEM_MASK BITFIELD(8, 8) /* * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT, @@ -679,237 +655,245 @@ * RM_L4SEC_CRYPTODMA_CONTEXT */ #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK (1 << 8) +#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK BITFIELD(8, 8) /* Used by RM_IVAHD_SL2_CONTEXT */ #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_SL2_MEM_MASK (1 << 8) +#define OMAP4430_LOSTMEM_SL2_MEM_MASK BITFIELD(8, 8) /* Used by RM_IVAHD_IVAHD_CONTEXT */ #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_TCM1_MEM_MASK (1 << 8) +#define OMAP4430_LOSTMEM_TCM1_MEM_MASK BITFIELD(8, 8) /* Used by RM_IVAHD_IVAHD_CONTEXT */ #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9 -#define OMAP4430_LOSTMEM_TCM2_MEM_MASK (1 << 9) +#define OMAP4430_LOSTMEM_TCM2_MEM_MASK BITFIELD(9, 9) /* Used by RM_TESLA_TESLA_CONTEXT */ #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10 -#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK (1 << 10) +#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK BITFIELD(10, 10) /* Used by RM_TESLA_TESLA_CONTEXT */ #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8 -#define OMAP4430_LOSTMEM_TESLA_L1_MASK (1 << 8) +#define OMAP4430_LOSTMEM_TESLA_L1_MASK BITFIELD(8, 8) /* Used by RM_TESLA_TESLA_CONTEXT */ #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9 -#define OMAP4430_LOSTMEM_TESLA_L2_MASK (1 << 9) +#define OMAP4430_LOSTMEM_TESLA_L2_MASK BITFIELD(9, 9) /* Used by RM_WKUP_SARRAM_CONTEXT */ #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_WKUP_BANK_MASK (1 << 8) +#define OMAP4430_LOSTMEM_WKUP_BANK_MASK BITFIELD(8, 8) /* - * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, - * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL, - * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL + * Used by PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, + * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, + * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL */ #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 -#define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) +#define OMAP4430_LOWPOWERSTATECHANGE_MASK BITFIELD(4, 4) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP4430_MEMORYCHANGE_SHIFT 3 +#define OMAP4430_MEMORYCHANGE_MASK BITFIELD(3, 3) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_MODEM_READY_SHIFT 1 -#define OMAP4430_MODEM_READY_MASK (1 << 1) +#define OMAP4430_MODEM_READY_MASK BITFIELD(1, 1) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9 -#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) +#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK BITFIELD(9, 9) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_MODEM_SLEEP_ST_SHIFT 16 -#define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16) +#define OMAP4430_MODEM_SLEEP_ST_MASK BITFIELD(16, 16) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8 -#define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8) +#define OMAP4430_MODEM_WAKE_IRQ_MASK BITFIELD(8, 8) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_L1_ONSTATE_SHIFT 16 -#define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_MPU_L1_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_L1_RETSTATE_SHIFT 8 -#define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8) +#define OMAP4430_MPU_L1_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_MPU_PWRSTST */ #define OMAP4430_MPU_L1_STATEST_SHIFT 4 -#define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4) +#define OMAP4430_MPU_L1_STATEST_MASK BITFIELD(4, 5) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_L2_ONSTATE_SHIFT 18 -#define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18) +#define OMAP4430_MPU_L2_ONSTATE_MASK BITFIELD(18, 19) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_L2_RETSTATE_SHIFT 9 -#define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9) +#define OMAP4430_MPU_L2_RETSTATE_MASK BITFIELD(9, 9) /* Used by PM_MPU_PWRSTST */ #define OMAP4430_MPU_L2_STATEST_SHIFT 6 -#define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6) +#define OMAP4430_MPU_L2_STATEST_MASK BITFIELD(6, 7) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20 -#define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20) +#define OMAP4430_MPU_RAM_ONSTATE_MASK BITFIELD(20, 21) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10 -#define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10) +#define OMAP4430_MPU_RAM_RETSTATE_MASK BITFIELD(10, 10) /* Used by PM_MPU_PWRSTST */ #define OMAP4430_MPU_RAM_STATEST_SHIFT 8 -#define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8) +#define OMAP4430_MPU_RAM_STATEST_MASK BITFIELD(8, 9) /* Used by PRM_RSTST */ #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 -#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2) +#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK BITFIELD(2, 2) /* Used by PRM_RSTST */ #define OMAP4430_MPU_WDT_RST_SHIFT 3 -#define OMAP4430_MPU_WDT_RST_MASK (1 << 3) +#define OMAP4430_MPU_WDT_RST_MASK BITFIELD(3, 3) /* Used by PM_L4PER_PWRSTCTRL */ #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18 -#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18) +#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK BITFIELD(18, 19) /* Used by PM_L4PER_PWRSTCTRL */ #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9 -#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9) +#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK BITFIELD(9, 9) /* Used by PM_L4PER_PWRSTST */ #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6 -#define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6) +#define OMAP4430_NONRETAINED_BANK_STATEST_MASK BITFIELD(6, 7) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24 -#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) +#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK BITFIELD(24, 25) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12 -#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) +#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK BITFIELD(12, 12) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12 -#define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) +#define OMAP4430_OCP_NRET_BANK_STATEST_MASK BITFIELD(12, 13) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ #define OMAP4430_OFF_SHIFT 0 -#define OMAP4430_OFF_MASK (0xff << 0) +#define OMAP4430_OFF_MASK BITFIELD(0, 7) + +/* Used by PRM_LDO_BANDGAP_CTRL */ +#define OMAP4430_OFF_ENABLE_SHIFT 0 +#define OMAP4430_OFF_ENABLE_MASK BITFIELD(0, 0) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ #define OMAP4430_ON_SHIFT 24 -#define OMAP4430_ON_MASK (0xff << 24) +#define OMAP4430_ON_MASK BITFIELD(24, 31) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ #define OMAP4430_ONLP_SHIFT 16 -#define OMAP4430_ONLP_MASK (0xff << 16) +#define OMAP4430_ONLP_MASK BITFIELD(16, 23) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ #define OMAP4430_OPP_CHANGE_SHIFT 2 -#define OMAP4430_OPP_CHANGE_MASK (1 << 2) +#define OMAP4430_OPP_CHANGE_MASK BITFIELD(2, 2) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ #define OMAP4430_OPP_SEL_SHIFT 0 -#define OMAP4430_OPP_SEL_MASK (0x3 << 0) +#define OMAP4430_OPP_SEL_MASK BITFIELD(0, 1) /* Used by PRM_SRAM_COUNT */ #define OMAP4430_PCHARGECNT_VALUE_SHIFT 0 -#define OMAP4430_PCHARGECNT_VALUE_MASK (0x3f << 0) +#define OMAP4430_PCHARGECNT_VALUE_MASK BITFIELD(0, 5) /* Used by PRM_PSCON_COUNT */ #define OMAP4430_PCHARGE_TIME_SHIFT 0 -#define OMAP4430_PCHARGE_TIME_MASK (0xff << 0) +#define OMAP4430_PCHARGE_TIME_MASK BITFIELD(0, 7) /* Used by PM_ABE_PWRSTCTRL */ #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20 -#define OMAP4430_PERIPHMEM_ONSTATE_MASK (0x3 << 20) +#define OMAP4430_PERIPHMEM_ONSTATE_MASK BITFIELD(20, 21) /* Used by PM_ABE_PWRSTCTRL */ #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10 -#define OMAP4430_PERIPHMEM_RETSTATE_MASK (1 << 10) +#define OMAP4430_PERIPHMEM_RETSTATE_MASK BITFIELD(10, 10) /* Used by PM_ABE_PWRSTST */ #define OMAP4430_PERIPHMEM_STATEST_SHIFT 8 -#define OMAP4430_PERIPHMEM_STATEST_MASK (0x3 << 8) +#define OMAP4430_PERIPHMEM_STATEST_MASK BITFIELD(8, 9) /* Used by PRM_PHASE1_CNDP */ #define OMAP4430_PHASE1_CNDP_SHIFT 0 -#define OMAP4430_PHASE1_CNDP_MASK (0xffffffff << 0) +#define OMAP4430_PHASE1_CNDP_MASK BITFIELD(0, 31) /* Used by PRM_PHASE2A_CNDP */ #define OMAP4430_PHASE2A_CNDP_SHIFT 0 -#define OMAP4430_PHASE2A_CNDP_MASK (0xffffffff << 0) +#define OMAP4430_PHASE2A_CNDP_MASK BITFIELD(0, 31) /* Used by PRM_PHASE2B_CNDP */ #define OMAP4430_PHASE2B_CNDP_SHIFT 0 -#define OMAP4430_PHASE2B_CNDP_MASK (0xffffffff << 0) +#define OMAP4430_PHASE2B_CNDP_MASK BITFIELD(0, 31) /* Used by PRM_PSCON_COUNT */ #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8 -#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) +#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK BITFIELD(8, 15) /* - * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, - * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL, - * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, - * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL + * Used by PM_EMU_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, + * PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, + * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, + * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL */ #define OMAP4430_POWERSTATE_SHIFT 0 -#define OMAP4430_POWERSTATE_MASK (0x3 << 0) +#define OMAP4430_POWERSTATE_MASK BITFIELD(0, 1) /* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, - * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, - * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST + * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, + * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, + * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST */ #define OMAP4430_POWERSTATEST_SHIFT 0 -#define OMAP4430_POWERSTATEST_MASK (0x3 << 0) +#define OMAP4430_POWERSTATEST_MASK BITFIELD(0, 1) /* Used by PRM_PWRREQCTRL */ #define OMAP4430_PWRREQ_COND_SHIFT 0 -#define OMAP4430_PWRREQ_COND_MASK (0x3 << 0) +#define OMAP4430_PWRREQ_COND_MASK BITFIELD(0, 1) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3 -#define OMAP4430_RACEN_VDD_CORE_L_MASK (1 << 3) +#define OMAP4430_RACEN_VDD_CORE_L_MASK BITFIELD(3, 3) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11 -#define OMAP4430_RACEN_VDD_IVA_L_MASK (1 << 11) +#define OMAP4430_RACEN_VDD_IVA_L_MASK BITFIELD(11, 11) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20 -#define OMAP4430_RACEN_VDD_MPU_L_MASK (1 << 20) +#define OMAP4430_RACEN_VDD_MPU_L_MASK BITFIELD(20, 20) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAC_VDD_CORE_L_SHIFT 2 -#define OMAP4430_RAC_VDD_CORE_L_MASK (1 << 2) +#define OMAP4430_RAC_VDD_CORE_L_MASK BITFIELD(2, 2) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAC_VDD_IVA_L_SHIFT 10 -#define OMAP4430_RAC_VDD_IVA_L_MASK (1 << 10) +#define OMAP4430_RAC_VDD_IVA_L_MASK BITFIELD(10, 10) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAC_VDD_MPU_L_SHIFT 19 -#define OMAP4430_RAC_VDD_MPU_L_MASK (1 << 19) +#define OMAP4430_RAC_VDD_MPU_L_MASK BITFIELD(19, 19) /* * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, @@ -917,7 +901,7 @@ * PRM_VOLTSETUP_MPU_RET_SLEEP */ #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 -#define OMAP4430_RAMP_DOWN_COUNT_MASK (0x3f << 16) +#define OMAP4430_RAMP_DOWN_COUNT_MASK BITFIELD(16, 21) /* * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, @@ -925,7 +909,7 @@ * PRM_VOLTSETUP_MPU_RET_SLEEP */ #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24 -#define OMAP4430_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) +#define OMAP4430_RAMP_DOWN_PRESCAL_MASK BITFIELD(24, 25) /* * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, @@ -933,7 +917,7 @@ * PRM_VOLTSETUP_MPU_RET_SLEEP */ #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 -#define OMAP4430_RAMP_UP_COUNT_MASK (0x3f << 0) +#define OMAP4430_RAMP_UP_COUNT_MASK BITFIELD(0, 5) /* * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, @@ -941,1381 +925,1281 @@ * PRM_VOLTSETUP_MPU_RET_SLEEP */ #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 -#define OMAP4430_RAMP_UP_PRESCAL_MASK (0x3 << 8) +#define OMAP4430_RAMP_UP_PRESCAL_MASK BITFIELD(8, 9) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAV_VDD_CORE_L_SHIFT 1 -#define OMAP4430_RAV_VDD_CORE_L_MASK (1 << 1) +#define OMAP4430_RAV_VDD_CORE_L_MASK BITFIELD(1, 1) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAV_VDD_IVA_L_SHIFT 9 -#define OMAP4430_RAV_VDD_IVA_L_MASK (1 << 9) +#define OMAP4430_RAV_VDD_IVA_L_MASK BITFIELD(9, 9) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAV_VDD_MPU_L_SHIFT 18 -#define OMAP4430_RAV_VDD_MPU_L_MASK (1 << 18) +#define OMAP4430_RAV_VDD_MPU_L_MASK BITFIELD(18, 18) /* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_REGADDR_SHIFT 8 -#define OMAP4430_REGADDR_MASK (0xff << 8) +#define OMAP4430_REGADDR_MASK BITFIELD(8, 15) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ #define OMAP4430_RET_SHIFT 8 -#define OMAP4430_RET_MASK (0xff << 8) +#define OMAP4430_RET_MASK BITFIELD(8, 15) /* Used by PM_L4PER_PWRSTCTRL */ #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_RETAINED_BANK_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_RETAINED_BANK_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_L4PER_PWRSTCTRL */ #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8 -#define OMAP4430_RETAINED_BANK_RETSTATE_MASK (1 << 8) +#define OMAP4430_RETAINED_BANK_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_L4PER_PWRSTST */ #define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4 -#define OMAP4430_RETAINED_BANK_STATEST_MASK (0x3 << 4) +#define OMAP4430_RETAINED_BANK_STATEST_MASK BITFIELD(4, 5) /* * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, * PRM_LDO_SRAM_MPU_CTRL */ #define OMAP4430_RETMODE_ENABLE_SHIFT 0 -#define OMAP4430_RETMODE_ENABLE_MASK (1 << 0) +#define OMAP4430_RETMODE_ENABLE_MASK BITFIELD(0, 0) -/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ +/* Used by REVISION_PRM */ +#define OMAP4430_REV_SHIFT 0 +#define OMAP4430_REV_MASK BITFIELD(0, 7) + +/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ #define OMAP4430_RST1_SHIFT 0 -#define OMAP4430_RST1_MASK (1 << 0) +#define OMAP4430_RST1_MASK BITFIELD(0, 0) -/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ +/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ #define OMAP4430_RST1ST_SHIFT 0 -#define OMAP4430_RST1ST_MASK (1 << 0) +#define OMAP4430_RST1ST_MASK BITFIELD(0, 0) -/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ +/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ #define OMAP4430_RST2_SHIFT 1 -#define OMAP4430_RST2_MASK (1 << 1) +#define OMAP4430_RST2_MASK BITFIELD(1, 1) -/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ +/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ #define OMAP4430_RST2ST_SHIFT 1 -#define OMAP4430_RST2ST_MASK (1 << 1) +#define OMAP4430_RST2ST_MASK BITFIELD(1, 1) /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ #define OMAP4430_RST3_SHIFT 2 -#define OMAP4430_RST3_MASK (1 << 2) +#define OMAP4430_RST3_MASK BITFIELD(2, 2) /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ #define OMAP4430_RST3ST_SHIFT 2 -#define OMAP4430_RST3ST_MASK (1 << 2) +#define OMAP4430_RST3ST_MASK BITFIELD(2, 2) /* Used by PRM_RSTTIME */ #define OMAP4430_RSTTIME1_SHIFT 0 -#define OMAP4430_RSTTIME1_MASK (0x3ff << 0) +#define OMAP4430_RSTTIME1_MASK BITFIELD(0, 9) /* Used by PRM_RSTTIME */ #define OMAP4430_RSTTIME2_SHIFT 10 -#define OMAP4430_RSTTIME2_MASK (0x1f << 10) +#define OMAP4430_RSTTIME2_MASK BITFIELD(10, 14) /* Used by PRM_RSTCTRL */ #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1 -#define OMAP4430_RST_GLOBAL_COLD_SW_MASK (1 << 1) +#define OMAP4430_RST_GLOBAL_COLD_SW_MASK BITFIELD(1, 1) /* Used by PRM_RSTCTRL */ #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0 -#define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) - -/* Used by REVISION_PRM */ -#define OMAP4430_R_RTL_SHIFT 11 -#define OMAP4430_R_RTL_MASK (0x1f << 11) +#define OMAP4430_RST_GLOBAL_WARM_SW_MASK BITFIELD(0, 0) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 -#define OMAP4430_SA_VDD_CORE_L_MASK (1 << 0) +#define OMAP4430_SA_VDD_CORE_L_MASK BITFIELD(0, 0) /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0 -#define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) +#define OMAP4430_SA_VDD_CORE_L_0_6_MASK BITFIELD(0, 6) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 -#define OMAP4430_SA_VDD_IVA_L_MASK (1 << 8) +#define OMAP4430_SA_VDD_IVA_L_MASK BITFIELD(8, 8) /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8 -#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) +#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK BITFIELD(8, 14) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 -#define OMAP4430_SA_VDD_MPU_L_MASK (1 << 16) +#define OMAP4430_SA_VDD_MPU_L_MASK BITFIELD(16, 16) /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16 -#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) - -/* Used by REVISION_PRM */ -#define OMAP4430_SCHEME_SHIFT 30 -#define OMAP4430_SCHEME_MASK (0x3 << 30) +#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK BITFIELD(16, 22) /* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_SCLH_SHIFT 0 -#define OMAP4430_SCLH_MASK (0xff << 0) +#define OMAP4430_SCLH_MASK BITFIELD(0, 7) /* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_SCLL_SHIFT 8 -#define OMAP4430_SCLL_MASK (0xff << 8) +#define OMAP4430_SCLL_MASK BITFIELD(8, 15) /* Used by PRM_RSTST */ #define OMAP4430_SECURE_WDT_RST_SHIFT 4 -#define OMAP4430_SECURE_WDT_RST_MASK (1 << 4) +#define OMAP4430_SECURE_WDT_RST_MASK BITFIELD(4, 4) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18 -#define OMAP4430_SL2_MEM_ONSTATE_MASK (0x3 << 18) +#define OMAP4430_SL2_MEM_ONSTATE_MASK BITFIELD(18, 19) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9 -#define OMAP4430_SL2_MEM_RETSTATE_MASK (1 << 9) +#define OMAP4430_SL2_MEM_RETSTATE_MASK BITFIELD(9, 9) /* Used by PM_IVAHD_PWRSTST */ #define OMAP4430_SL2_MEM_STATEST_SHIFT 6 -#define OMAP4430_SL2_MEM_STATEST_MASK (0x3 << 6) +#define OMAP4430_SL2_MEM_STATEST_MASK BITFIELD(6, 7) /* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_SLAVEADDR_SHIFT 0 -#define OMAP4430_SLAVEADDR_MASK (0x7f << 0) +#define OMAP4430_SLAVEADDR_MASK BITFIELD(0, 6) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_SLEEP_RBB_SEL_SHIFT 3 -#define OMAP4430_SLEEP_RBB_SEL_MASK (1 << 3) +#define OMAP4430_SLEEP_RBB_SEL_MASK BITFIELD(3, 3) /* Used by PRM_SRAM_COUNT */ #define OMAP4430_SLPCNT_VALUE_SHIFT 16 -#define OMAP4430_SLPCNT_VALUE_MASK (0xff << 16) +#define OMAP4430_SLPCNT_VALUE_MASK BITFIELD(16, 23) /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 -#define OMAP4430_SMPSWAITTIMEMAX_MASK (0xffff << 8) +#define OMAP4430_SMPSWAITTIMEMAX_MASK BITFIELD(8, 23) /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 -#define OMAP4430_SMPSWAITTIMEMIN_MASK (0xffff << 8) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_RA_ERR_CORE_SHIFT 1 -#define OMAP4430_SMPS_RA_ERR_CORE_MASK (1 << 1) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_RA_ERR_IVA_SHIFT 9 -#define OMAP4430_SMPS_RA_ERR_IVA_MASK (1 << 9) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_RA_ERR_MPU_SHIFT 17 -#define OMAP4430_SMPS_RA_ERR_MPU_MASK (1 << 17) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_SA_ERR_CORE_SHIFT 0 -#define OMAP4430_SMPS_SA_ERR_CORE_MASK (1 << 0) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_SA_ERR_IVA_SHIFT 8 -#define OMAP4430_SMPS_SA_ERR_IVA_MASK (1 << 8) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_SA_ERR_MPU_SHIFT 16 -#define OMAP4430_SMPS_SA_ERR_MPU_MASK (1 << 16) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 -#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT 10 -#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK (1 << 10) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT 18 -#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 18) +#define OMAP4430_SMPSWAITTIMEMIN_MASK BITFIELD(8, 23) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_SR2EN_SHIFT 0 -#define OMAP4430_SR2EN_MASK (1 << 0) +#define OMAP4430_SR2EN_MASK BITFIELD(0, 0) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ #define OMAP4430_SR2_IN_TRANSITION_SHIFT 6 -#define OMAP4430_SR2_IN_TRANSITION_MASK (1 << 6) +#define OMAP4430_SR2_IN_TRANSITION_MASK BITFIELD(6, 6) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ #define OMAP4430_SR2_STATUS_SHIFT 3 -#define OMAP4430_SR2_STATUS_MASK (0x3 << 3) +#define OMAP4430_SR2_STATUS_MASK BITFIELD(3, 4) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8 -#define OMAP4430_SR2_WTCNT_VALUE_MASK (0xff << 8) +#define OMAP4430_SR2_WTCNT_VALUE_MASK BITFIELD(8, 15) /* * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, * PRM_LDO_SRAM_MPU_CTRL */ #define OMAP4430_SRAMLDO_STATUS_SHIFT 8 -#define OMAP4430_SRAMLDO_STATUS_MASK (1 << 8) +#define OMAP4430_SRAMLDO_STATUS_MASK BITFIELD(8, 8) /* * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, * PRM_LDO_SRAM_MPU_CTRL */ #define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9 -#define OMAP4430_SRAM_IN_TRANSITION_MASK (1 << 9) +#define OMAP4430_SRAM_IN_TRANSITION_MASK BITFIELD(9, 9) /* Used by PRM_VC_CFG_I2C_MODE */ #define OMAP4430_SRMODEEN_SHIFT 4 -#define OMAP4430_SRMODEEN_MASK (1 << 4) +#define OMAP4430_SRMODEEN_MASK BITFIELD(4, 4) /* Used by PRM_VOLTSETUP_WARMRESET */ #define OMAP4430_STABLE_COUNT_SHIFT 0 -#define OMAP4430_STABLE_COUNT_MASK (0x3f << 0) +#define OMAP4430_STABLE_COUNT_MASK BITFIELD(0, 5) /* Used by PRM_VOLTSETUP_WARMRESET */ #define OMAP4430_STABLE_PRESCAL_SHIFT 8 -#define OMAP4430_STABLE_PRESCAL_MASK (0x3 << 8) - -/* Used by PRM_LDO_BANDGAP_SETUP */ -#define OMAP4430_STARTUP_COUNT_SHIFT 0 -#define OMAP4430_STARTUP_COUNT_MASK (0xff << 0) - -/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ -#define OMAP4430_STARTUP_COUNT_24_31_SHIFT 24 -#define OMAP4430_STARTUP_COUNT_24_31_MASK (0xff << 24) +#define OMAP4430_STABLE_PRESCAL_MASK BITFIELD(8, 9) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20 -#define OMAP4430_TCM1_MEM_ONSTATE_MASK (0x3 << 20) +#define OMAP4430_TCM1_MEM_ONSTATE_MASK BITFIELD(20, 21) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10 -#define OMAP4430_TCM1_MEM_RETSTATE_MASK (1 << 10) +#define OMAP4430_TCM1_MEM_RETSTATE_MASK BITFIELD(10, 10) /* Used by PM_IVAHD_PWRSTST */ #define OMAP4430_TCM1_MEM_STATEST_SHIFT 8 -#define OMAP4430_TCM1_MEM_STATEST_MASK (0x3 << 8) +#define OMAP4430_TCM1_MEM_STATEST_MASK BITFIELD(8, 9) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22 -#define OMAP4430_TCM2_MEM_ONSTATE_MASK (0x3 << 22) +#define OMAP4430_TCM2_MEM_ONSTATE_MASK BITFIELD(22, 23) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11 -#define OMAP4430_TCM2_MEM_RETSTATE_MASK (1 << 11) +#define OMAP4430_TCM2_MEM_RETSTATE_MASK BITFIELD(11, 11) /* Used by PM_IVAHD_PWRSTST */ #define OMAP4430_TCM2_MEM_STATEST_SHIFT 10 -#define OMAP4430_TCM2_MEM_STATEST_MASK (0x3 << 10) +#define OMAP4430_TCM2_MEM_STATEST_MASK BITFIELD(10, 11) /* Used by RM_TESLA_RSTST */ #define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2 -#define OMAP4430_TESLASS_EMU_RSTST_MASK (1 << 2) +#define OMAP4430_TESLASS_EMU_RSTST_MASK BITFIELD(2, 2) /* Used by RM_TESLA_RSTST */ #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3 -#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK (1 << 3) +#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK BITFIELD(3, 3) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20 -#define OMAP4430_TESLA_EDMA_ONSTATE_MASK (0x3 << 20) +#define OMAP4430_TESLA_EDMA_ONSTATE_MASK BITFIELD(20, 21) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10 -#define OMAP4430_TESLA_EDMA_RETSTATE_MASK (1 << 10) +#define OMAP4430_TESLA_EDMA_RETSTATE_MASK BITFIELD(10, 10) /* Used by PM_TESLA_PWRSTST */ #define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8 -#define OMAP4430_TESLA_EDMA_STATEST_MASK (0x3 << 8) +#define OMAP4430_TESLA_EDMA_STATEST_MASK BITFIELD(8, 9) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16 -#define OMAP4430_TESLA_L1_ONSTATE_MASK (0x3 << 16) +#define OMAP4430_TESLA_L1_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8 -#define OMAP4430_TESLA_L1_RETSTATE_MASK (1 << 8) +#define OMAP4430_TESLA_L1_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_TESLA_PWRSTST */ #define OMAP4430_TESLA_L1_STATEST_SHIFT 4 -#define OMAP4430_TESLA_L1_STATEST_MASK (0x3 << 4) +#define OMAP4430_TESLA_L1_STATEST_MASK BITFIELD(4, 5) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18 -#define OMAP4430_TESLA_L2_ONSTATE_MASK (0x3 << 18) +#define OMAP4430_TESLA_L2_ONSTATE_MASK BITFIELD(18, 19) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9 -#define OMAP4430_TESLA_L2_RETSTATE_MASK (1 << 9) +#define OMAP4430_TESLA_L2_RETSTATE_MASK BITFIELD(9, 9) /* Used by PM_TESLA_PWRSTST */ #define OMAP4430_TESLA_L2_STATEST_SHIFT 6 -#define OMAP4430_TESLA_L2_STATEST_MASK (0x3 << 6) +#define OMAP4430_TESLA_L2_STATEST_MASK BITFIELD(6, 7) /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_TIMEOUT_SHIFT 0 -#define OMAP4430_TIMEOUT_MASK (0xffff << 0) +#define OMAP4430_TIMEOUT_MASK BITFIELD(0, 15) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_TIMEOUTEN_SHIFT 3 -#define OMAP4430_TIMEOUTEN_MASK (1 << 3) +#define OMAP4430_TIMEOUTEN_MASK BITFIELD(3, 3) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_TRANSITION_EN_SHIFT 8 -#define OMAP4430_TRANSITION_EN_MASK (1 << 8) +#define OMAP4430_TRANSITION_EN_MASK BITFIELD(8, 8) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_TRANSITION_ST_SHIFT 8 -#define OMAP4430_TRANSITION_ST_MASK (1 << 8) +#define OMAP4430_TRANSITION_ST_MASK BITFIELD(8, 8) /* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_VALID_SHIFT 24 -#define OMAP4430_VALID_MASK (1 << 24) +#define OMAP4430_VALID_MASK BITFIELD(24, 24) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_BYPASSACK_EN_SHIFT 14 -#define OMAP4430_VC_BYPASSACK_EN_MASK (1 << 14) +#define OMAP4430_VC_BYPASSACK_EN_MASK BITFIELD(14, 14) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_BYPASSACK_ST_SHIFT 14 -#define OMAP4430_VC_BYPASSACK_ST_MASK (1 << 14) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_CORE_VPACK_EN_SHIFT 22 -#define OMAP4430_VC_CORE_VPACK_EN_MASK (1 << 22) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_CORE_VPACK_ST_SHIFT 22 -#define OMAP4430_VC_CORE_VPACK_ST_MASK (1 << 22) +#define OMAP4430_VC_BYPASSACK_ST_MASK BITFIELD(14, 14) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30 -#define OMAP4430_VC_IVA_VPACK_EN_MASK (1 << 30) +#define OMAP4430_VC_IVA_VPACK_EN_MASK BITFIELD(30, 30) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30 -#define OMAP4430_VC_IVA_VPACK_ST_MASK (1 << 30) +#define OMAP4430_VC_IVA_VPACK_ST_MASK BITFIELD(30, 30) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6 -#define OMAP4430_VC_MPU_VPACK_EN_MASK (1 << 6) +#define OMAP4430_VC_MPU_VPACK_EN_MASK BITFIELD(6, 6) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6 -#define OMAP4430_VC_MPU_VPACK_ST_MASK (1 << 6) +#define OMAP4430_VC_MPU_VPACK_ST_MASK BITFIELD(6, 6) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_RAERR_EN_SHIFT 12 -#define OMAP4430_VC_RAERR_EN_MASK (1 << 12) +#define OMAP4430_VC_RAERR_EN_MASK BITFIELD(12, 12) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_RAERR_ST_SHIFT 12 -#define OMAP4430_VC_RAERR_ST_MASK (1 << 12) +#define OMAP4430_VC_RAERR_ST_MASK BITFIELD(12, 12) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_SAERR_EN_SHIFT 11 -#define OMAP4430_VC_SAERR_EN_MASK (1 << 11) +#define OMAP4430_VC_SAERR_EN_MASK BITFIELD(11, 11) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_SAERR_ST_SHIFT 11 -#define OMAP4430_VC_SAERR_ST_MASK (1 << 11) +#define OMAP4430_VC_SAERR_ST_MASK BITFIELD(11, 11) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_TOERR_EN_SHIFT 13 -#define OMAP4430_VC_TOERR_EN_MASK (1 << 13) +#define OMAP4430_VC_TOERR_EN_MASK BITFIELD(13, 13) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_TOERR_ST_SHIFT 13 -#define OMAP4430_VC_TOERR_ST_MASK (1 << 13) +#define OMAP4430_VC_TOERR_ST_MASK BITFIELD(13, 13) /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_VDDMAX_SHIFT 24 -#define OMAP4430_VDDMAX_MASK (0xff << 24) +#define OMAP4430_VDDMAX_MASK BITFIELD(24, 31) /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_VDDMIN_SHIFT 16 -#define OMAP4430_VDDMIN_MASK (0xff << 16) +#define OMAP4430_VDDMIN_MASK BITFIELD(16, 23) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12 -#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK (1 << 12) +#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK BITFIELD(12, 12) /* Used by PRM_RSTST */ #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 -#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) +#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK BITFIELD(8, 8) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14 -#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK (1 << 14) +#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK BITFIELD(14, 14) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9 -#define OMAP4430_VDD_IVA_PRESENCE_MASK (1 << 9) +#define OMAP4430_VDD_IVA_PRESENCE_MASK BITFIELD(9, 9) /* Used by PRM_RSTST */ #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 -#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK (1 << 7) +#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK BITFIELD(7, 7) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13 -#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK (1 << 13) +#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK BITFIELD(13, 13) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8 -#define OMAP4430_VDD_MPU_PRESENCE_MASK (1 << 8) +#define OMAP4430_VDD_MPU_PRESENCE_MASK BITFIELD(8, 8) /* Used by PRM_RSTST */ #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 -#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_RA_ERR_CORE_SHIFT 4 -#define OMAP4430_VFSM_RA_ERR_CORE_MASK (1 << 4) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_RA_ERR_IVA_SHIFT 12 -#define OMAP4430_VFSM_RA_ERR_IVA_MASK (1 << 12) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_RA_ERR_MPU_SHIFT 20 -#define OMAP4430_VFSM_RA_ERR_MPU_MASK (1 << 20) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_SA_ERR_CORE_SHIFT 3 -#define OMAP4430_VFSM_SA_ERR_CORE_MASK (1 << 3) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_SA_ERR_IVA_SHIFT 11 -#define OMAP4430_VFSM_SA_ERR_IVA_MASK (1 << 11) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_SA_ERR_MPU_SHIFT 19 -#define OMAP4430_VFSM_SA_ERR_MPU_MASK (1 << 19) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 -#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT 13 -#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK (1 << 13) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT 21 -#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 21) +#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK BITFIELD(6, 6) /* Used by PRM_VC_VAL_SMPS_RA_VOL */ #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0 -#define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) +#define OMAP4430_VOLRA_VDD_CORE_L_MASK BITFIELD(0, 7) /* Used by PRM_VC_VAL_SMPS_RA_VOL */ #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8 -#define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) +#define OMAP4430_VOLRA_VDD_IVA_L_MASK BITFIELD(8, 15) /* Used by PRM_VC_VAL_SMPS_RA_VOL */ #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16 -#define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) +#define OMAP4430_VOLRA_VDD_MPU_L_MASK BITFIELD(16, 23) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_VPENABLE_SHIFT 0 -#define OMAP4430_VPENABLE_MASK (1 << 0) +#define OMAP4430_VPENABLE_MASK BITFIELD(0, 0) /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ #define OMAP4430_VPINIDLE_SHIFT 0 -#define OMAP4430_VPINIDLE_MASK (1 << 0) +#define OMAP4430_VPINIDLE_MASK BITFIELD(0, 0) /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ #define OMAP4430_VPVOLTAGE_SHIFT 0 -#define OMAP4430_VPVOLTAGE_MASK (0xff << 0) +#define OMAP4430_VPVOLTAGE_MASK BITFIELD(0, 7) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20 -#define OMAP4430_VP_CORE_EQVALUE_EN_MASK (1 << 20) +#define OMAP4430_VP_CORE_EQVALUE_EN_MASK BITFIELD(20, 20) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20 -#define OMAP4430_VP_CORE_EQVALUE_ST_MASK (1 << 20) +#define OMAP4430_VP_CORE_EQVALUE_ST_MASK BITFIELD(20, 20) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18 -#define OMAP4430_VP_CORE_MAXVDD_EN_MASK (1 << 18) +#define OMAP4430_VP_CORE_MAXVDD_EN_MASK BITFIELD(18, 18) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18 -#define OMAP4430_VP_CORE_MAXVDD_ST_MASK (1 << 18) +#define OMAP4430_VP_CORE_MAXVDD_ST_MASK BITFIELD(18, 18) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17 -#define OMAP4430_VP_CORE_MINVDD_EN_MASK (1 << 17) +#define OMAP4430_VP_CORE_MINVDD_EN_MASK BITFIELD(17, 17) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17 -#define OMAP4430_VP_CORE_MINVDD_ST_MASK (1 << 17) +#define OMAP4430_VP_CORE_MINVDD_ST_MASK BITFIELD(17, 17) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19 -#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) +#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK BITFIELD(19, 19) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19 -#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) +#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK BITFIELD(19, 19) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 -#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) +#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK BITFIELD(16, 16) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 -#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) +#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK BITFIELD(16, 16) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21 -#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK (1 << 21) +#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK BITFIELD(21, 21) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21 -#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) +#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK BITFIELD(21, 21) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28 -#define OMAP4430_VP_IVA_EQVALUE_EN_MASK (1 << 28) +#define OMAP4430_VP_IVA_EQVALUE_EN_MASK BITFIELD(28, 28) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28 -#define OMAP4430_VP_IVA_EQVALUE_ST_MASK (1 << 28) +#define OMAP4430_VP_IVA_EQVALUE_ST_MASK BITFIELD(28, 28) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26 -#define OMAP4430_VP_IVA_MAXVDD_EN_MASK (1 << 26) +#define OMAP4430_VP_IVA_MAXVDD_EN_MASK BITFIELD(26, 26) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26 -#define OMAP4430_VP_IVA_MAXVDD_ST_MASK (1 << 26) +#define OMAP4430_VP_IVA_MAXVDD_ST_MASK BITFIELD(26, 26) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25 -#define OMAP4430_VP_IVA_MINVDD_EN_MASK (1 << 25) +#define OMAP4430_VP_IVA_MINVDD_EN_MASK BITFIELD(25, 25) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25 -#define OMAP4430_VP_IVA_MINVDD_ST_MASK (1 << 25) +#define OMAP4430_VP_IVA_MINVDD_ST_MASK BITFIELD(25, 25) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27 -#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK (1 << 27) +#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK BITFIELD(27, 27) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27 -#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK (1 << 27) +#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK BITFIELD(27, 27) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24 -#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK (1 << 24) +#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK BITFIELD(24, 24) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24 -#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK (1 << 24) +#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK BITFIELD(24, 24) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29 -#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK (1 << 29) +#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK BITFIELD(29, 29) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29 -#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) +#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK BITFIELD(29, 29) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4 -#define OMAP4430_VP_MPU_EQVALUE_EN_MASK (1 << 4) +#define OMAP4430_VP_MPU_EQVALUE_EN_MASK BITFIELD(4, 4) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4 -#define OMAP4430_VP_MPU_EQVALUE_ST_MASK (1 << 4) +#define OMAP4430_VP_MPU_EQVALUE_ST_MASK BITFIELD(4, 4) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2 -#define OMAP4430_VP_MPU_MAXVDD_EN_MASK (1 << 2) +#define OMAP4430_VP_MPU_MAXVDD_EN_MASK BITFIELD(2, 2) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2 -#define OMAP4430_VP_MPU_MAXVDD_ST_MASK (1 << 2) +#define OMAP4430_VP_MPU_MAXVDD_ST_MASK BITFIELD(2, 2) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1 -#define OMAP4430_VP_MPU_MINVDD_EN_MASK (1 << 1) +#define OMAP4430_VP_MPU_MINVDD_EN_MASK BITFIELD(1, 1) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1 -#define OMAP4430_VP_MPU_MINVDD_ST_MASK (1 << 1) +#define OMAP4430_VP_MPU_MINVDD_ST_MASK BITFIELD(1, 1) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3 -#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) +#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK BITFIELD(3, 3) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3 -#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) +#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK BITFIELD(3, 3) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 -#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) +#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK BITFIELD(0, 0) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 -#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) +#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK BITFIELD(0, 0) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5 -#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK (1 << 5) +#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK BITFIELD(5, 5) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5 -#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) +#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK BITFIELD(5, 5) /* Used by PRM_SRAM_COUNT */ #define OMAP4430_VSETUPCNT_VALUE_SHIFT 8 -#define OMAP4430_VSETUPCNT_VALUE_MASK (0xff << 8) +#define OMAP4430_VSETUPCNT_VALUE_MASK BITFIELD(8, 15) /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ #define OMAP4430_VSTEPMAX_SHIFT 0 -#define OMAP4430_VSTEPMAX_MASK (0xff << 0) +#define OMAP4430_VSTEPMAX_MASK BITFIELD(0, 7) /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ #define OMAP4430_VSTEPMIN_SHIFT 0 -#define OMAP4430_VSTEPMIN_MASK (0xff << 0) +#define OMAP4430_VSTEPMIN_MASK BITFIELD(0, 7) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_WAKE_MODEM_SHIFT 0 -#define OMAP4430_WAKE_MODEM_MASK (1 << 0) +#define OMAP4430_WAKE_MODEM_MASK BITFIELD(0, 0) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DISPC_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_DISPC_MPU_MASK BITFIELD(0, 0) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK BITFIELD(3, 3) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_DMIC_WKDEP */ #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_ABE_DMIC_WKDEP */ #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_ABE_DMIC_WKDEP */ #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_DMIC_WKDEP */ #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_DMTIMER10_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_DMTIMER11_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_DMTIMER11_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_DMTIMER2_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_DMTIMER3_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_DMTIMER3_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_DMTIMER4_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_DMTIMER4_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_DMTIMER9_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_DMTIMER9_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK BITFIELD(0, 0) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5 -#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK (1 << 5) +#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK BITFIELD(5, 5) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4 -#define OMAP4430_WKUPDEP_DSI1_MPU_MASK (1 << 4) +#define OMAP4430_WKUPDEP_DSI1_MPU_MASK BITFIELD(4, 4) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK BITFIELD(7, 7) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK BITFIELD(6, 6) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9 -#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK (1 << 9) +#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK BITFIELD(9, 9) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8 -#define OMAP4430_WKUPDEP_DSI2_MPU_MASK (1 << 8) +#define OMAP4430_WKUPDEP_DSI2_MPU_MASK BITFIELD(8, 8) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11 -#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK (1 << 11) +#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK BITFIELD(11, 11) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10 -#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK (1 << 10) +#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK BITFIELD(10, 10) /* Used by PM_WKUP_GPIO1_WKDEP */ #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_WKUP_GPIO1_WKDEP */ #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_GPIO1_WKDEP */ #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_GPIO2_WKDEP */ #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_GPIO2_WKDEP */ #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_GPIO2_WKDEP */ #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_GPIO3_WKDEP */ #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_GPIO3_WKDEP */ #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_GPIO4_WKDEP */ #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_GPIO4_WKDEP */ #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_GPIO5_WKDEP */ #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_GPIO5_WKDEP */ #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_GPIO6_WKDEP */ #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_GPIO6_WKDEP */ #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 -#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) +#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK BITFIELD(19, 19) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13 -#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK (1 << 13) +#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK BITFIELD(13, 13) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 -#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) +#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK BITFIELD(12, 12) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14 -#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK (1 << 14) +#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK BITFIELD(14, 14) /* Used by PM_L4PER_HECC1_WKDEP */ #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HECC1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_HECC1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_HECC2_WKDEP */ #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HECC2_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_HECC2_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_HSI_WKDEP */ #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L3INIT_HSI_WKDEP */ #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_HSI_WKDEP */ #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_I2C1_WKDEP */ #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_I2C1_WKDEP */ #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_I2C1_WKDEP */ #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_I2C2_WKDEP */ #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_I2C2_WKDEP */ #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_I2C2_WKDEP */ #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_I2C3_WKDEP */ #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_I2C3_WKDEP */ #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_I2C3_WKDEP */ #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_I2C4_WKDEP */ #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_I2C4_WKDEP */ #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_I2C4_WKDEP */ #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_I2C5_WKDEP */ #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_I2C5_WKDEP */ #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_KEYBOARD_WKDEP */ #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_MCASP_WKDEP */ #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_ABE_MCASP_WKDEP */ #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_ABE_MCASP_WKDEP */ #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_MCASP_WKDEP */ #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MCASP2_WKDEP */ #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_MCASP2_WKDEP */ #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_MCASP2_WKDEP */ #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCASP2_WKDEP */ #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MCASP3_WKDEP */ #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_MCASP3_WKDEP */ #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_MCASP3_WKDEP */ #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCASP3_WKDEP */ #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_MCBSP1_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_MCBSP1_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK BITFIELD(3, 3) /* Used by PM_ABE_MCBSP1_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_MCBSP2_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_MCBSP2_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK BITFIELD(3, 3) /* Used by PM_ABE_MCBSP2_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_MCBSP3_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_MCBSP3_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK BITFIELD(3, 3) /* Used by PM_ABE_MCBSP3_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MCBSP4_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCBSP4_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MCBSP4_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MCSPI1_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_MCSPI1_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCSPI1_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MCSPI1_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MCSPI2_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_MCSPI2_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCSPI2_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MCSPI3_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCSPI3_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MCSPI4_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCSPI4_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L3INIT_MMC1_WKDEP */ #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_MMC1_WKDEP */ #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MMC1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_MMC1_WKDEP */ #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L3INIT_MMC1_WKDEP */ #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L3INIT_MMC2_WKDEP */ #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_MMC2_WKDEP */ #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC2_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MMC2_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_MMC2_WKDEP */ #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L3INIT_MMC2_WKDEP */ #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L3INIT_MMC6_WKDEP */ #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_MMC6_WKDEP */ #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC6_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MMC6_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_MMC6_WKDEP */ #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MMCSD3_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_MMCSD3_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MMCSD3_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MMCSD4_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_MMCSD4_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MMCSD4_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MMCSD5_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_MMCSD5_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MMCSD5_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L3INIT_PCIESS_WKDEP */ #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_PCIESS_WKDEP */ #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_PDM_WKDEP */ #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_ABE_PDM_WKDEP */ #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_ABE_PDM_WKDEP */ #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_PDM_WKDEP */ #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_WKUP_RTC_WKDEP */ #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_RTC_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_RTC_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_SATA_WKDEP */ #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SATA_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_SATA_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_SATA_WKDEP */ #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SATA_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_SATA_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_SLIMBUS_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_ABE_SLIMBUS_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_ABE_SLIMBUS_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_SLIMBUS_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK (1 << 7) +#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK (1 << 6) +#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ALWON_SR_CORE_WKDEP */ #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_ALWON_SR_CORE_WKDEP */ #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK BITFIELD(0, 0) /* Used by PM_ALWON_SR_IVA_WKDEP */ #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_ALWON_SR_IVA_WKDEP */ #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK BITFIELD(0, 0) /* Used by PM_ALWON_SR_MPU_WKDEP */ #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_TIMER12_WKDEP */ #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_TIMER1_WKDEP */ #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_TIMER5_WKDEP */ #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_TIMER5_WKDEP */ #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_TIMER6_WKDEP */ #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_TIMER6_WKDEP */ #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_TIMER7_WKDEP */ #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_TIMER7_WKDEP */ #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_TIMER8_WKDEP */ #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_TIMER8_WKDEP */ #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_UART1_WKDEP */ #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_UART1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_UART1_WKDEP */ #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART1_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_UART1_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_UART2_WKDEP */ #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART2_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_UART2_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_UART2_WKDEP */ #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART2_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_UART2_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_UART3_WKDEP */ #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_UART3_WKDEP */ #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART3_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_UART3_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_UART3_WKDEP */ #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART3_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_UART3_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_UART3_WKDEP */ #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_UART3_TESLA_MASK (1 << 2) +#define OMAP4430_WKUPDEP_UART3_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_UART4_WKDEP */ #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART4_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_UART4_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_UART4_WKDEP */ #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART4_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_UART4_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L3INIT_UNIPRO1_WKDEP */ #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_UNIPRO1_WKDEP */ #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_USB_HOST_WKDEP */ #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_USB_HOST_WKDEP */ #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_USB_OTG_WKDEP */ #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_USB_OTG_WKDEP */ #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_USB_TLL_WKDEP */ #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_USB_TLL_WKDEP */ #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_USIM_WKDEP */ #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USIM_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_USIM_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_USIM_WKDEP */ #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_USIM_SDMA_MASK (1 << 3) +#define OMAP4430_WKUPDEP_USIM_SDMA_MASK BITFIELD(3, 3) /* Used by PM_WKUP_WDT2_WKDEP */ #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_WKUP_WDT2_WKDEP */ #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_WDT2_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_WDT2_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_WDT3_WKDEP */ #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_WDT3_MPU_MASK (1 << 0) +#define OMAP4430_WKUPDEP_WDT3_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_HSI_WKDEP */ #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8 -#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK (1 << 8) +#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK BITFIELD(8, 8) /* Used by PM_L3INIT_XHPI_WKDEP */ #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK (1 << 1) +#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK BITFIELD(1, 1) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_WUCLK_CTRL_SHIFT 8 -#define OMAP4430_WUCLK_CTRL_MASK (1 << 8) +#define OMAP4430_WUCLK_CTRL_MASK BITFIELD(8, 8) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_WUCLK_STATUS_SHIFT 9 -#define OMAP4430_WUCLK_STATUS_MASK (1 << 9) - -/* Used by REVISION_PRM */ -#define OMAP4430_X_MAJOR_SHIFT 8 -#define OMAP4430_X_MAJOR_MASK (0x7 << 8) - -/* Used by REVISION_PRM */ -#define OMAP4430_Y_MINOR_SHIFT 0 -#define OMAP4430_Y_MINOR_MASK (0x3f << 0) +#define OMAP4430_WUCLK_STATUS_MASK BITFIELD(9, 9) #endif diff --git a/trunk/arch/arm/mach-omap2/prm.h b/trunk/arch/arm/mach-omap2/prm.h index 7be040b2fdab..588873b9303a 100644 --- a/trunk/arch/arm/mach-omap2/prm.h +++ b/trunk/arch/arm/mach-omap2/prm.h @@ -5,7 +5,7 @@ * OMAP2/3 Power/Reset Management (PRM) register definitions * * Copyright (C) 2007-2009 Texas Instruments, Inc. - * Copyright (C) 2010 Nokia Corporation + * Copyright (C) 2009 Nokia Corporation * * Written by Paul Walmsley * @@ -246,15 +246,6 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) return prm_rmw_mod_reg_bits(bits, 0x0, module, idx); } -/* These omap2_ PRM functions apply to both OMAP2 and 3 */ -int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); -int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); -int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift); - -int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift); -int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift); -int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); - #endif /* @@ -407,11 +398,4 @@ int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); #define OMAP_POWERSTATE_MASK (0x3 << 0) -/* - * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP - * submodule to exit hardreset - */ -#define MAX_MODULE_HARDRESET_WAIT 10000 - - #endif diff --git a/trunk/arch/arm/mach-omap2/prm2xxx_3xxx.c b/trunk/arch/arm/mach-omap2/prm2xxx_3xxx.c deleted file mode 100644 index 421771eee450..000000000000 --- a/trunk/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * OMAP2/3 PRM module functions - * - * Copyright (C) 2010 Texas Instruments, Inc. - * Copyright (C) 2010 Nokia Corporation - * Benoît Cousson - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include "prm.h" -#include "prm-regbits-24xx.h" -#include "prm-regbits-34xx.h" - -/** - * omap2_prm_is_hardreset_asserted - read the HW reset line state of - * submodules contained in the hwmod module - * @prm_mod: PRM submodule base (e.g. CORE_MOD) - * @shift: register bit shift corresponding to the reset line to check - * - * Returns 1 if the (sub)module hardreset line is currently asserted, - * 0 if the (sub)module hardreset line is not currently asserted, or - * -EINVAL if called while running on a non-OMAP2/3 chip. - */ -int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) -{ - if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) - return -EINVAL; - - return prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, - (1 << shift)); -} - -/** - * omap2_prm_assert_hardreset - assert the HW reset line of a submodule - * @prm_mod: PRM submodule base (e.g. CORE_MOD) - * @shift: register bit shift corresponding to the reset line to assert - * - * Some IPs like dsp or iva contain processors that require an HW - * reset line to be asserted / deasserted in order to fully enable the - * IP. These modules may have multiple hard-reset lines that reset - * different 'submodules' inside the IP block. This function will - * place the submodule into reset. Returns 0 upon success or -EINVAL - * upon an argument error. - */ -int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) -{ - u32 mask; - - if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) - return -EINVAL; - - mask = 1 << shift; - prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); - - return 0; -} - -/** - * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait - * @prm_mod: PRM submodule base (e.g. CORE_MOD) - * @shift: register bit shift corresponding to the reset line to deassert - * - * Some IPs like dsp or iva contain processors that require an HW - * reset line to be asserted / deasserted in order to fully enable the - * IP. These modules may have multiple hard-reset lines that reset - * different 'submodules' inside the IP block. This function will - * take the submodule out of reset and wait until the PRCM indicates - * that the reset has completed before returning. Returns 0 upon success or - * -EINVAL upon an argument error, -EEXIST if the submodule was already out - * of reset, or -EBUSY if the submodule did not exit reset promptly. - */ -int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift) -{ - u32 mask; - int c; - - if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) - return -EINVAL; - - mask = 1 << shift; - - /* Check the current status to avoid de-asserting the line twice */ - if (prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0) - return -EEXIST; - - /* Clear the reset status by writing 1 to the status bit */ - prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST); - /* de-assert the reset control line */ - prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL); - /* wait the status to be set */ - omap_test_timeout(prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, - mask), - MAX_MODULE_HARDRESET_WAIT, c); - - return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; -} - diff --git a/trunk/arch/arm/mach-omap2/prm44xx.c b/trunk/arch/arm/mach-omap2/prm44xx.c deleted file mode 100644 index a1ff918d9bed..000000000000 --- a/trunk/arch/arm/mach-omap2/prm44xx.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * OMAP4 PRM module functions - * - * Copyright (C) 2010 Texas Instruments, Inc. - * Copyright (C) 2010 Nokia Corporation - * Benoît Cousson - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include "prm.h" -#include "prm-regbits-44xx.h" - -/* - * Address offset (in bytes) between the reset control and the reset - * status registers: 4 bytes on OMAP4 - */ -#define OMAP4_RST_CTRL_ST_OFFSET 4 - -/** - * omap4_prm_is_hardreset_asserted - read the HW reset line state of - * submodules contained in the hwmod module - * @rstctrl_reg: RM_RSTCTRL register address for this module - * @shift: register bit shift corresponding to the reset line to check - * - * Returns 1 if the (sub)module hardreset line is currently asserted, - * 0 if the (sub)module hardreset line is not currently asserted, or - * -EINVAL upon parameter error. - */ -int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift) -{ - if (!cpu_is_omap44xx() || !rstctrl_reg) - return -EINVAL; - - return omap4_prm_read_bits_shift(rstctrl_reg, (1 << shift)); -} - -/** - * omap4_prm_assert_hardreset - assert the HW reset line of a submodule - * @rstctrl_reg: RM_RSTCTRL register address for this module - * @shift: register bit shift corresponding to the reset line to assert - * - * Some IPs like dsp, ipu or iva contain processors that require an HW - * reset line to be asserted / deasserted in order to fully enable the - * IP. These modules may have multiple hard-reset lines that reset - * different 'submodules' inside the IP block. This function will - * place the submodule into reset. Returns 0 upon success or -EINVAL - * upon an argument error. - */ -int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift) -{ - u32 mask; - - if (!cpu_is_omap44xx() || !rstctrl_reg) - return -EINVAL; - - mask = 1 << shift; - omap4_prm_rmw_reg_bits(mask, mask, rstctrl_reg); - - return 0; -} - -/** - * omap4_prm_deassert_hardreset - deassert a submodule hardreset line and wait - * @rstctrl_reg: RM_RSTCTRL register address for this module - * @shift: register bit shift corresponding to the reset line to deassert - * - * Some IPs like dsp, ipu or iva contain processors that require an HW - * reset line to be asserted / deasserted in order to fully enable the - * IP. These modules may have multiple hard-reset lines that reset - * different 'submodules' inside the IP block. This function will - * take the submodule out of reset and wait until the PRCM indicates - * that the reset has completed before returning. Returns 0 upon success or - * -EINVAL upon an argument error, -EEXIST if the submodule was already out - * of reset, or -EBUSY if the submodule did not exit reset promptly. - */ -int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift) -{ - u32 mask; - void __iomem *rstst_reg; - int c; - - if (!cpu_is_omap44xx() || !rstctrl_reg) - return -EINVAL; - - rstst_reg = rstctrl_reg + OMAP4_RST_CTRL_ST_OFFSET; - - mask = 1 << shift; - - /* Check the current status to avoid de-asserting the line twice */ - if (omap4_prm_read_bits_shift(rstctrl_reg, mask) == 0) - return -EEXIST; - - /* Clear the reset status by writing 1 to the status bit */ - omap4_prm_rmw_reg_bits(0xffffffff, mask, rstst_reg); - /* de-assert the reset control line */ - omap4_prm_rmw_reg_bits(mask, 0, rstctrl_reg); - /* wait the status to be set */ - omap_test_timeout(omap4_prm_read_bits_shift(rstst_reg, mask), - MAX_MODULE_HARDRESET_WAIT, c); - - return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; -} - diff --git a/trunk/arch/arm/mach-omap2/prm44xx.h b/trunk/arch/arm/mach-omap2/prm44xx.h index 59839dbabd84..fe8ef26431e5 100644 --- a/trunk/arch/arm/mach-omap2/prm44xx.h +++ b/trunk/arch/arm/mach-omap2/prm44xx.h @@ -44,12 +44,14 @@ #define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030) #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038 #define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038) -#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) +#define OMAP4_PRM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 +#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) /* PRM.CKGEN_PRM register offsets */ #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000 #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000) +#define OMAP4_CM_DPLL_SYS_REF_CLKSEL_OFFSET 0x0004 +#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004) #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008 #define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008) #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c @@ -684,8 +686,8 @@ #define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8) #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc #define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc) -#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0 -#define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) +#define OMAP4_PRM_LDO_BANDGAP_CTRL_OFFSET 0x00e0 +#define OMAP4430_PRM_LDO_BANDGAP_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4 #define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4) #define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8 @@ -696,8 +698,6 @@ #define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0) #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4 #define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4) -#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 -#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8) /* * PRCM_MPU @@ -715,8 +715,6 @@ /* PRCM_MPU.DEVICE_PRM register offsets */ #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 #define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000) -#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 -#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004) /* PRCM_MPU.CPU0 register offsets */ #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 diff --git a/trunk/arch/arm/mach-omap2/serial.c b/trunk/arch/arm/mach-omap2/serial.c index becf0e38ef7e..566e991ede81 100644 --- a/trunk/arch/arm/mach-omap2/serial.c +++ b/trunk/arch/arm/mach-omap2/serial.c @@ -19,31 +19,20 @@ */ #include #include +#include #include #include #include #include -#include -#include -#include -#include - -#ifdef CONFIG_SERIAL_OMAP -#include -#endif #include #include #include -#include -#include -#include +#include #include "prm.h" #include "pm.h" -#include "cm.h" #include "prm-regbits-34xx.h" -#include "control.h" #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 #define UART_OMAP_WER 0x17 /* Wake-up enable register */ @@ -59,8 +48,6 @@ */ #define DEFAULT_TIMEOUT 0 -#define MAX_UART_HWMOD_NAME_LEN 16 - struct omap_uart_state { int num; int can_sleep; @@ -71,21 +58,14 @@ struct omap_uart_state { void __iomem *wk_en; u32 wk_mask; u32 padconf; - u32 dma_enabled; struct clk *ick; struct clk *fck; int clocked; - int irq; - int regshift; - int irqflags; - void __iomem *membase; - resource_size_t mapbase; - + struct plat_serial8250_port *p; struct list_head node; - struct omap_hwmod *oh; - struct platform_device *pdev; + struct platform_device pdev; u32 errata; #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) @@ -103,47 +83,75 @@ struct omap_uart_state { }; static LIST_HEAD(uart_list); -static u8 num_uarts; -/* - * Since these idle/enable hooks are used in the idle path itself - * which has interrupts disabled, use the non-locking versions of - * the hwmod enable/disable functions. - */ -static int uart_idle_hwmod(struct omap_device *od) -{ - _omap_hwmod_idle(od->hwmods[0]); - - return 0; -} +static struct plat_serial8250_port serial_platform_data0[] = { + { + .irq = 72, + .flags = UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = OMAP24XX_BASE_BAUD * 16, + }, { + .flags = 0 + } +}; -static int uart_enable_hwmod(struct omap_device *od) -{ - _omap_hwmod_enable(od->hwmods[0]); +static struct plat_serial8250_port serial_platform_data1[] = { + { + .irq = 73, + .flags = UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = OMAP24XX_BASE_BAUD * 16, + }, { + .flags = 0 + } +}; - return 0; -} +static struct plat_serial8250_port serial_platform_data2[] = { + { + .irq = 74, + .flags = UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = OMAP24XX_BASE_BAUD * 16, + }, { + .flags = 0 + } +}; -static struct omap_device_pm_latency omap_uart_latency[] = { +static struct plat_serial8250_port serial_platform_data3[] = { { - .deactivate_func = uart_idle_hwmod, - .activate_func = uart_enable_hwmod, - .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, - }, + .irq = 70, + .flags = UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = OMAP24XX_BASE_BAUD * 16, + }, { + .flags = 0 + } }; +void __init omap2_set_globals_uart(struct omap_globals *omap2_globals) +{ + serial_platform_data0[0].mapbase = omap2_globals->uart1_phys; + serial_platform_data1[0].mapbase = omap2_globals->uart2_phys; + serial_platform_data2[0].mapbase = omap2_globals->uart3_phys; + serial_platform_data3[0].mapbase = omap2_globals->uart4_phys; +} + static inline unsigned int __serial_read_reg(struct uart_port *up, - int offset) + int offset) { offset <<= up->regshift; return (unsigned int)__raw_readb(up->membase + offset); } -static inline unsigned int serial_read_reg(struct omap_uart_state *uart, +static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, int offset) { - offset <<= uart->regshift; - return (unsigned int)__raw_readb(uart->membase + offset); + offset <<= up->regshift; + return (unsigned int)__raw_readb(up->membase + offset); } static inline void __serial_write_reg(struct uart_port *up, int offset, @@ -153,11 +161,11 @@ static inline void __serial_write_reg(struct uart_port *up, int offset, __raw_writeb(value, up->membase + offset); } -static inline void serial_write_reg(struct omap_uart_state *uart, int offset, +static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, int value) { - offset <<= uart->regshift; - __raw_writeb(value, uart->membase + offset); + offset <<= p->regshift; + __raw_writeb(value, p->membase + offset); } /* @@ -165,12 +173,14 @@ static inline void serial_write_reg(struct omap_uart_state *uart, int offset, * properly. Note that the TX watermark initialization may not be needed * once the 8250.c watermark handling code is merged. */ - static inline void __init omap_uart_reset(struct omap_uart_state *uart) { - serial_write_reg(uart, UART_OMAP_MDR1, 0x07); - serial_write_reg(uart, UART_OMAP_SCR, 0x08); - serial_write_reg(uart, UART_OMAP_MDR1, 0x00); + struct plat_serial8250_port *p = uart->p; + + serial_write_reg(p, UART_OMAP_MDR1, 0x07); + serial_write_reg(p, UART_OMAP_SCR, 0x08); + serial_write_reg(p, UART_OMAP_MDR1, 0x00); + serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0)); } #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) @@ -187,23 +197,24 @@ static inline void __init omap_uart_reset(struct omap_uart_state *uart) static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, u8 fcr_val) { + struct plat_serial8250_port *p = uart->p; u8 timeout = 255; - serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val); + serial_write_reg(p, UART_OMAP_MDR1, mdr1_val); udelay(2); - serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT | + serial_write_reg(p, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); /* * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and * TX_FIFO_E bit is 1. */ - while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) & + while (UART_LSR_THRE != (serial_read_reg(p, UART_LSR) & (UART_LSR_THRE | UART_LSR_DR))) { timeout--; if (!timeout) { /* Should *never* happen. we warn and carry on */ - dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n", - serial_read_reg(uart, UART_LSR)); + dev_crit(&uart->pdev.dev, "Errata i202: timedout %x\n", + serial_read_reg(p, UART_LSR)); break; } udelay(1); @@ -213,22 +224,23 @@ static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, static void omap_uart_save_context(struct omap_uart_state *uart) { u16 lcr = 0; + struct plat_serial8250_port *p = uart->p; if (!enable_off_mode) return; - lcr = serial_read_reg(uart, UART_LCR); - serial_write_reg(uart, UART_LCR, 0xBF); - uart->dll = serial_read_reg(uart, UART_DLL); - uart->dlh = serial_read_reg(uart, UART_DLM); - serial_write_reg(uart, UART_LCR, lcr); - uart->ier = serial_read_reg(uart, UART_IER); - uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC); - uart->scr = serial_read_reg(uart, UART_OMAP_SCR); - uart->wer = serial_read_reg(uart, UART_OMAP_WER); - serial_write_reg(uart, UART_LCR, 0x80); - uart->mcr = serial_read_reg(uart, UART_MCR); - serial_write_reg(uart, UART_LCR, lcr); + lcr = serial_read_reg(p, UART_LCR); + serial_write_reg(p, UART_LCR, 0xBF); + uart->dll = serial_read_reg(p, UART_DLL); + uart->dlh = serial_read_reg(p, UART_DLM); + serial_write_reg(p, UART_LCR, lcr); + uart->ier = serial_read_reg(p, UART_IER); + uart->sysc = serial_read_reg(p, UART_OMAP_SYSC); + uart->scr = serial_read_reg(p, UART_OMAP_SCR); + uart->wer = serial_read_reg(p, UART_OMAP_WER); + serial_write_reg(p, UART_LCR, 0x80); + uart->mcr = serial_read_reg(p, UART_MCR); + serial_write_reg(p, UART_LCR, lcr); uart->context_valid = 1; } @@ -236,6 +248,7 @@ static void omap_uart_save_context(struct omap_uart_state *uart) static void omap_uart_restore_context(struct omap_uart_state *uart) { u16 efr = 0; + struct plat_serial8250_port *p = uart->p; if (!enable_off_mode) return; @@ -248,30 +261,29 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) omap_uart_mdr1_errataset(uart, 0x07, 0xA0); else - serial_write_reg(uart, UART_OMAP_MDR1, 0x7); - serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ - efr = serial_read_reg(uart, UART_EFR); - serial_write_reg(uart, UART_EFR, UART_EFR_ECB); - serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ - serial_write_reg(uart, UART_IER, 0x0); - serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ - serial_write_reg(uart, UART_DLL, uart->dll); - serial_write_reg(uart, UART_DLM, uart->dlh); - serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ - serial_write_reg(uart, UART_IER, uart->ier); - serial_write_reg(uart, UART_LCR, 0x80); - serial_write_reg(uart, UART_MCR, uart->mcr); - serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ - serial_write_reg(uart, UART_EFR, efr); - serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8); - serial_write_reg(uart, UART_OMAP_SCR, uart->scr); - serial_write_reg(uart, UART_OMAP_WER, uart->wer); - serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc); + serial_write_reg(p, UART_OMAP_MDR1, 0x7); + serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ + efr = serial_read_reg(p, UART_EFR); + serial_write_reg(p, UART_EFR, UART_EFR_ECB); + serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ + serial_write_reg(p, UART_IER, 0x0); + serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ + serial_write_reg(p, UART_DLL, uart->dll); + serial_write_reg(p, UART_DLM, uart->dlh); + serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ + serial_write_reg(p, UART_IER, uart->ier); + serial_write_reg(p, UART_LCR, 0x80); + serial_write_reg(p, UART_MCR, uart->mcr); + serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ + serial_write_reg(p, UART_EFR, efr); + serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); + serial_write_reg(p, UART_OMAP_SCR, uart->scr); + serial_write_reg(p, UART_OMAP_WER, uart->wer); + serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) omap_uart_mdr1_errataset(uart, 0x00, 0xA1); else - /* UART 16x mode */ - serial_write_reg(uart, UART_OMAP_MDR1, 0x00); + serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ } #else static inline void omap_uart_save_context(struct omap_uart_state *uart) {} @@ -283,7 +295,8 @@ static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) if (uart->clocked) return; - omap_device_enable(uart->pdev); + clk_enable(uart->ick); + clk_enable(uart->fck); uart->clocked = 1; omap_uart_restore_context(uart); } @@ -297,7 +310,8 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) omap_uart_save_context(uart); uart->clocked = 0; - omap_device_idle(uart->pdev); + clk_disable(uart->ick); + clk_disable(uart->fck); } static void omap_uart_enable_wakeup(struct omap_uart_state *uart) @@ -335,24 +349,18 @@ static void omap_uart_disable_wakeup(struct omap_uart_state *uart) } static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, - int enable) + int enable) { - u8 idlemode; + struct plat_serial8250_port *p = uart->p; + u16 sysc; - if (enable) { - /** - * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests - * in Smartidle Mode When Configured for DMA Operations. - */ - if (uart->dma_enabled) - idlemode = HWMOD_IDLEMODE_FORCE; - else - idlemode = HWMOD_IDLEMODE_SMART; - } else { - idlemode = HWMOD_IDLEMODE_NO; - } + sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7; + if (enable) + sysc |= 0x2 << 3; + else + sysc |= 0x1 << 3; - omap_hwmod_set_slave_idlemode(uart->oh, idlemode); + serial_write_reg(p, UART_OMAP_SYSC, sysc); } static void omap_uart_block_sleep(struct omap_uart_state *uart) @@ -369,7 +377,7 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart) static void omap_uart_allow_sleep(struct omap_uart_state *uart) { - if (device_may_wakeup(&uart->pdev->dev)) + if (device_may_wakeup(&uart->pdev.dev)) omap_uart_enable_wakeup(uart); else omap_uart_disable_wakeup(uart); @@ -464,7 +472,6 @@ int omap_uart_can_sleep(void) * UART will not idle or sleep for its timeout period. * **/ -/* static int first_interrupt; */ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) { struct omap_uart_state *uart = dev_id; @@ -476,6 +483,7 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) static void omap_uart_idle_init(struct omap_uart_state *uart) { + struct plat_serial8250_port *p = uart->p; int ret; uart->can_sleep = 0; @@ -487,7 +495,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) omap_uart_smart_idle_enable(uart, 0); if (cpu_is_omap34xx()) { - u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD; + u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD; u32 wk_mask = 0; u32 padconf = 0; @@ -506,17 +514,19 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) wk_mask = OMAP3430_ST_UART3_MASK; padconf = 0x19e; break; - case 3: - wk_mask = OMAP3630_ST_UART4_MASK; - padconf = 0x0d2; - break; } uart->wk_mask = wk_mask; uart->padconf = padconf; } else if (cpu_is_omap24xx()) { u32 wk_mask = 0; - u32 wk_en = PM_WKEN1, wk_st = PM_WKST1; + if (cpu_is_omap2430()) { + uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1); + uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1); + } else if (cpu_is_omap2420()) { + uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1); + uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1); + } switch (uart->num) { case 0: wk_mask = OMAP24XX_ST_UART1_MASK; @@ -525,19 +535,10 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) wk_mask = OMAP24XX_ST_UART2_MASK; break; case 2: - wk_en = OMAP24XX_PM_WKEN2; - wk_st = OMAP24XX_PM_WKST2; wk_mask = OMAP24XX_ST_UART3_MASK; break; } uart->wk_mask = wk_mask; - if (cpu_is_omap2430()) { - uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en); - uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st); - } else if (cpu_is_omap2420()) { - uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en); - uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st); - } } else { uart->wk_en = NULL; uart->wk_st = NULL; @@ -545,9 +546,9 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) uart->padconf = 0; } - uart->irqflags |= IRQF_SHARED; - ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt, - IRQF_SHARED, "serial idle", (void *)uart); + p->irqflags |= IRQF_SHARED; + ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED, + "serial idle", (void *)uart); WARN_ON(ret); } @@ -557,17 +558,11 @@ void omap_uart_enable_irqs(int enable) struct omap_uart_state *uart; list_for_each_entry(uart, &uart_list, node) { - if (enable) { - pm_runtime_put_sync(&uart->pdev->dev); - ret = request_threaded_irq(uart->irq, NULL, - omap_uart_interrupt, - IRQF_SHARED, - "serial idle", - (void *)uart); - } else { - pm_runtime_get_noresume(&uart->pdev->dev); - free_irq(uart->irq, (void *)uart); - } + if (enable) + ret = request_irq(uart->p->irq, omap_uart_interrupt, + IRQF_SHARED, "serial idle", (void *)uart); + else + free_irq(uart->p->irq, (void *)uart); } } @@ -575,9 +570,10 @@ static ssize_t sleep_timeout_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct platform_device *pdev = to_platform_device(dev); - struct omap_device *odev = to_omap_device(pdev); - struct omap_uart_state *uart = odev->hwmods[0]->dev_attr; + struct platform_device *pdev = container_of(dev, + struct platform_device, dev); + struct omap_uart_state *uart = container_of(pdev, + struct omap_uart_state, pdev); return sprintf(buf, "%u\n", uart->timeout / HZ); } @@ -586,9 +582,10 @@ static ssize_t sleep_timeout_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) { - struct platform_device *pdev = to_platform_device(dev); - struct omap_device *odev = to_omap_device(pdev); - struct omap_uart_state *uart = odev->hwmods[0]->dev_attr; + struct platform_device *pdev = container_of(dev, + struct platform_device, dev); + struct omap_uart_state *uart = container_of(pdev, + struct omap_uart_state, pdev); unsigned int value; if (sscanf(buf, "%u", &value) != 1) { @@ -611,15 +608,48 @@ static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) #else static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} -static void omap_uart_block_sleep(struct omap_uart_state *uart) -{ - /* Needed to enable UART clocks when built without CONFIG_PM */ - omap_uart_enable_clocks(uart); -} #define DEV_CREATE_FILE(dev, attr) #endif /* CONFIG_PM */ -#ifndef CONFIG_SERIAL_OMAP +static struct omap_uart_state omap_uart[] = { + { + .pdev = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = serial_platform_data0, + }, + }, + }, { + .pdev = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev = { + .platform_data = serial_platform_data1, + }, + }, + }, { + .pdev = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, + .dev = { + .platform_data = serial_platform_data2, + }, + }, + }, +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) + { + .pdev = { + .name = "serial8250", + .id = 3, + .dev = { + .platform_data = serial_platform_data3, + }, + }, + }, +#endif +}; + /* * Override the default 8250 read handler: mem_serial_in() * Empty RX fifo read causes an abort on omap3630 and omap4 @@ -652,44 +682,71 @@ static void serial_out_override(struct uart_port *up, int offset, int value) } __serial_write_reg(up, offset, value); } -#endif - void __init omap_serial_early_init(void) { - int i = 0; + int i, nr_ports; + char name[16]; - do { - char oh_name[MAX_UART_HWMOD_NAME_LEN]; - struct omap_hwmod *oh; - struct omap_uart_state *uart; - - snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN, - "uart%d", i + 1); - oh = omap_hwmod_lookup(oh_name); - if (!oh) - break; + if (!(cpu_is_omap3630() || cpu_is_omap4430())) + nr_ports = 3; + else + nr_ports = ARRAY_SIZE(omap_uart); - uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL); - if (WARN_ON(!uart)) - return; + /* + * Make sure the serial ports are muxed on at this point. + * You have to mux them off in device drivers later on + * if not needed. + */ - uart->oh = oh; - uart->num = i++; - list_add_tail(&uart->node, &uart_list); - num_uarts++; + for (i = 0; i < nr_ports; i++) { + struct omap_uart_state *uart = &omap_uart[i]; + struct platform_device *pdev = &uart->pdev; + struct device *dev = &pdev->dev; + struct plat_serial8250_port *p = dev->platform_data; + /* Don't map zero-based physical address */ + if (p->mapbase == 0) { + dev_warn(dev, "no physical address for uart#%d," + " so skipping early_init...\n", i); + continue; + } /* - * NOTE: omap_hwmod_init() has not yet been called, - * so no hwmod functions will work yet. + * Module 4KB + L4 interconnect 4KB + * Static mapping, never released */ + p->membase = ioremap(p->mapbase, SZ_8K); + if (!p->membase) { + dev_err(dev, "ioremap failed for uart%i\n", i + 1); + continue; + } - /* - * During UART early init, device need to be probed - * to determine SoC specific init before omap_device - * is ready. Therefore, don't allow idle here - */ - uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET; - } while (1); + sprintf(name, "uart%d_ick", i + 1); + uart->ick = clk_get(NULL, name); + if (IS_ERR(uart->ick)) { + dev_err(dev, "Could not get uart%d_ick\n", i + 1); + uart->ick = NULL; + } + + sprintf(name, "uart%d_fck", i+1); + uart->fck = clk_get(NULL, name); + if (IS_ERR(uart->fck)) { + dev_err(dev, "Could not get uart%d_fck\n", i + 1); + uart->fck = NULL; + } + + /* FIXME: Remove this once the clkdev is ready */ + if (!cpu_is_omap44xx()) { + if (!uart->ick || !uart->fck) + continue; + } + + uart->num = i; + p->private_data = uart; + uart->p = p; + + if (cpu_is_omap44xx()) + p->irq += 32; + } } /** @@ -706,135 +763,53 @@ void __init omap_serial_early_init(void) void __init omap_serial_init_port(int port) { struct omap_uart_state *uart; - struct omap_hwmod *oh; - struct omap_device *od; - void *pdata = NULL; - u32 pdata_size = 0; - char *name; -#ifndef CONFIG_SERIAL_OMAP - struct plat_serial8250_port ports[2] = { - {}, - {.flags = 0}, - }; - struct plat_serial8250_port *p = &ports[0]; -#else - struct omap_uart_port_info omap_up; -#endif + struct platform_device *pdev; + struct device *dev; - if (WARN_ON(port < 0)) - return; - if (WARN_ON(port >= num_uarts)) + BUG_ON(port < 0); + BUG_ON(port >= ARRAY_SIZE(omap_uart)); + + uart = &omap_uart[port]; + pdev = &uart->pdev; + dev = &pdev->dev; + + /* Don't proceed if there's no clocks available */ + if (unlikely(!uart->ick || !uart->fck)) { + WARN(1, "%s: can't init uart%d, no clocks available\n", + kobject_name(&dev->kobj), port); return; + } - list_for_each_entry(uart, &uart_list, node) - if (port == uart->num) - break; + omap_uart_enable_clocks(uart); - oh = uart->oh; - uart->dma_enabled = 0; -#ifndef CONFIG_SERIAL_OMAP - name = "serial8250"; + omap_uart_reset(uart); + omap_uart_idle_init(uart); - /* - * !! 8250 driver does not use standard IORESOURCE* It - * has it's own custom pdata that can be taken from - * the hwmod resource data. But, this needs to be - * done after the build. - * - * ?? does it have to be done before the register ?? - * YES, because platform_device_data_add() copies - * pdata, it does not use a pointer. - */ - p->flags = UPF_BOOT_AUTOCONF; - p->iotype = UPIO_MEM; - p->regshift = 2; - p->uartclk = OMAP24XX_BASE_BAUD * 16; - p->irq = oh->mpu_irqs[0].irq; - p->mapbase = oh->slaves[0]->addr->pa_start; - p->membase = omap_hwmod_get_mpu_rt_va(oh); - p->irqflags = IRQF_SHARED; - p->private_data = uart; + list_add_tail(&uart->node, &uart_list); + + if (WARN_ON(platform_device_register(pdev))) + return; + + if ((cpu_is_omap34xx() && uart->padconf) || + (uart->wk_en && uart->wk_mask)) { + device_init_wakeup(dev, true); + DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout); + } /* * omap44xx: Never read empty UART fifo * omap3xxx: Never read empty UART fifo on UARTs * with IP rev >=0x52 */ - uart->regshift = p->regshift; - uart->membase = p->membase; if (cpu_is_omap44xx()) uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; - else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF) + else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) { - p->serial_in = serial_in_override; - p->serial_out = serial_out_override; - } - - pdata = &ports[0]; - pdata_size = 2 * sizeof(struct plat_serial8250_port); -#else - - name = DRIVER_NAME; - - omap_up.dma_enabled = uart->dma_enabled; - omap_up.uartclk = OMAP24XX_BASE_BAUD * 16; - omap_up.mapbase = oh->slaves[0]->addr->pa_start; - omap_up.membase = omap_hwmod_get_mpu_rt_va(oh); - omap_up.irqflags = IRQF_SHARED; - omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; - - pdata = &omap_up; - pdata_size = sizeof(struct omap_uart_port_info); -#endif - - if (WARN_ON(!oh)) - return; - - od = omap_device_build(name, uart->num, oh, pdata, pdata_size, - omap_uart_latency, - ARRAY_SIZE(omap_uart_latency), false); - WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n", - name, oh->name); - - uart->irq = oh->mpu_irqs[0].irq; - uart->regshift = 2; - uart->mapbase = oh->slaves[0]->addr->pa_start; - uart->membase = omap_hwmod_get_mpu_rt_va(oh); - uart->pdev = &od->pdev; - - oh->dev_attr = uart; - - /* - * Because of early UART probing, UART did not get idled - * on init. Now that omap_device is ready, ensure full idle - * before doing omap_device_enable(). - */ - omap_hwmod_idle(uart->oh); - - omap_device_enable(uart->pdev); - omap_uart_idle_init(uart); - omap_uart_reset(uart); - omap_hwmod_enable_wakeup(uart->oh); - omap_device_idle(uart->pdev); - - /* - * Need to block sleep long enough for interrupt driven - * driver to start. Console driver is in polling mode - * so device needs to be kept enabled while polling driver - * is in use. - */ - if (uart->timeout) - uart->timeout = (30 * HZ); - omap_uart_block_sleep(uart); - uart->timeout = DEFAULT_TIMEOUT; - - if ((cpu_is_omap34xx() && uart->padconf) || - (uart->wk_en && uart->wk_mask)) { - device_init_wakeup(&od->pdev.dev, true); - DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout); + uart->p->serial_in = serial_in_override; + uart->p->serial_out = serial_out_override; } /* Enable the MDR1 errata for OMAP3 */ @@ -851,8 +826,13 @@ void __init omap_serial_init_port(int port) */ void __init omap_serial_init(void) { - struct omap_uart_state *uart; + int i, nr_ports; + + if (!(cpu_is_omap3630() || cpu_is_omap4430())) + nr_ports = 3; + else + nr_ports = ARRAY_SIZE(omap_uart); - list_for_each_entry(uart, &uart_list, node) - omap_serial_init_port(uart->num); + for (i = 0; i < nr_ports; i++) + omap_serial_init_port(i); } diff --git a/trunk/arch/arm/mach-omap2/sleep34xx.S b/trunk/arch/arm/mach-omap2/sleep34xx.S index 2fb205a7f285..ba53191ae4c5 100644 --- a/trunk/arch/arm/mach-omap2/sleep34xx.S +++ b/trunk/arch/arm/mach-omap2/sleep34xx.S @@ -27,11 +27,11 @@ #include #include #include +#include #include "cm.h" #include "prm.h" #include "sdrc.h" -#include "control.h" #define SDRC_SCRATCHPAD_SEM_V 0xfa00291c diff --git a/trunk/arch/arm/mach-omap2/sram34xx.S b/trunk/arch/arm/mach-omap2/sram34xx.S index 3637274af5be..de99ba2a57ab 100644 --- a/trunk/arch/arm/mach-omap2/sram34xx.S +++ b/trunk/arch/arm/mach-omap2/sram34xx.S @@ -129,11 +129,8 @@ ENTRY(omap3_sram_configure_core_dpll) ldr r4, [sp, #80] str r4, omap_sdrc_mr_1_val skip_cs1_params: - mrc p15, 0, r8, c1, c0, 0 @ read ctrl register - bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction - mcr p15, 0, r10, c1, c0, 0 @ write ctrl register dsb @ flush buffered writes to interconnect - isb @ prevent speculative exec past here + cmp r3, #1 @ if increasing SDRC clk rate, bleq configure_sdrc @ program the SDRC regs early (for RFR) cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state @@ -151,7 +148,6 @@ skip_cs1_params: beq return_to_sdram @ return to SDRAM code, otherwise, bl configure_sdrc @ reprogram SDRC regs now return_to_sdram: - mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register isb @ prevent speculative exec past here mov r0, #0 @ return value ldmfd sp!, {r1-r12, pc} @ restore regs and return diff --git a/trunk/arch/arm/mach-omap2/timer-gp.c b/trunk/arch/arm/mach-omap2/timer-gp.c index e13c29eecf2b..74fbed8491f2 100644 --- a/trunk/arch/arm/mach-omap2/timer-gp.c +++ b/trunk/arch/arm/mach-omap2/timer-gp.c @@ -40,8 +40,6 @@ #include #include -#include "timer-gp.h" - /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12 @@ -230,10 +228,8 @@ static void __init omap2_gp_clocksource_init(void) static void __init omap2_gp_timer_init(void) { #ifdef CONFIG_LOCAL_TIMERS - if (cpu_is_omap44xx()) { - twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256); - BUG_ON(!twd_base); - } + twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256); + BUG_ON(!twd_base); #endif omap_dm_timer_init(); diff --git a/trunk/arch/arm/mach-omap2/usb-fs.c b/trunk/arch/arm/mach-omap2/usb-fs.c index 1481078763b8..a216d88b04b5 100644 --- a/trunk/arch/arm/mach-omap2/usb-fs.c +++ b/trunk/arch/arm/mach-omap2/usb-fs.c @@ -29,18 +29,18 @@ #include +#include #include #include -#include "control.h" -#include "mux.h" - #define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN #define INT_USB_IRQ_NISO INT_24XX_USB_IRQ_NISO #define INT_USB_IRQ_ISO INT_24XX_USB_IRQ_ISO #define INT_USB_IRQ_HGEN INT_24XX_USB_IRQ_HGEN #define INT_USB_IRQ_OTG INT_24XX_USB_IRQ_OTG +#include "mux.h" + #if defined(CONFIG_ARCH_OMAP2) #ifdef CONFIG_USB_GADGET_OMAP diff --git a/trunk/arch/arm/plat-omap/Kconfig b/trunk/arch/arm/plat-omap/Kconfig index 92c5bb7909f5..a92cb499313f 100644 --- a/trunk/arch/arm/plat-omap/Kconfig +++ b/trunk/arch/arm/plat-omap/Kconfig @@ -19,7 +19,7 @@ config ARCH_OMAP2PLUS bool "TI OMAP2/3/4" select COMMON_CLKDEV help - "Systems based on OMAP2, OMAP3 or OMAP4" + "Systems based on omap24xx, omap34xx or omap44xx" endchoice diff --git a/trunk/arch/arm/plat-omap/Makefile b/trunk/arch/arm/plat-omap/Makefile index a4a12859fdd5..9405831b746a 100644 --- a/trunk/arch/arm/plat-omap/Makefile +++ b/trunk/arch/arm/plat-omap/Makefile @@ -4,7 +4,7 @@ # Common support obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \ - usb.o fb.o io.o counter_32k.o + usb.o fb.o io.o obj-m := obj-n := obj- := @@ -31,4 +31,4 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y) # OMAP mailbox framework obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o -obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o +obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o \ No newline at end of file diff --git a/trunk/arch/arm/plat-omap/clock.c b/trunk/arch/arm/plat-omap/clock.c index fc62fb5fc20b..7190cbd92620 100644 --- a/trunk/arch/arm/plat-omap/clock.c +++ b/trunk/arch/arm/plat-omap/clock.c @@ -60,7 +60,7 @@ void clk_disable(struct clk *clk) spin_lock_irqsave(&clockfw_lock, flags); if (clk->usecount == 0) { - pr_err("Trying disable clock %s with 0 usecount\n", + printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", clk->name); WARN_ON(1); goto out; @@ -397,7 +397,6 @@ static int __init clk_disable_unused(void) struct clk *ck; unsigned long flags; - pr_info("clock: disabling unused clocks to save power\n"); list_for_each_entry(ck, &clocks, node) { if (ck->ops == &clkops_null) continue; @@ -419,7 +418,7 @@ late_initcall(clk_disable_unused); int __init clk_init(struct clk_functions * custom_clocks) { if (!custom_clocks) { - pr_err("No custom clock functions registered\n"); + printk(KERN_ERR "No custom clock functions registered\n"); BUG(); } diff --git a/trunk/arch/arm/plat-omap/common.c b/trunk/arch/arm/plat-omap/common.c index 221a675ebbae..3008e7104487 100644 --- a/trunk/arch/arm/plat-omap/common.c +++ b/trunk/arch/arm/plat-omap/common.c @@ -11,15 +11,38 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include #include #include +#include +#include +#include +#include +#include +#include +#include #include #include +#include +#include +#include +#include +#include + #include #include +#include +#include +#include +#include #include +#include + +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +# include "../mach-omap2/sdrc.h" +#endif #define NO_LENGTH_CHECK 0xffffffff @@ -65,3 +88,270 @@ void __init omap_reserve(void) omapfb_reserve_sdram_memblock(); omap_vram_reserve_sdram_memblock(); } + +/* + * 32KHz clocksource ... always available, on pretty most chips except + * OMAP 730 and 1510. Other timers could be used as clocksources, with + * higher resolution in free-running counter modes (e.g. 12 MHz xtal), + * but systems won't necessarily want to spend resources that way. + */ + +#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410 + +#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) + +#include + +/* + * offset_32k holds the init time counter value. It is then subtracted + * from every counter read to achieve a counter that counts time from the + * kernel boot (needed for sched_clock()). + */ +static u32 offset_32k __read_mostly; + +#ifdef CONFIG_ARCH_OMAP16XX +static cycle_t omap16xx_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k; +} +#else +#define omap16xx_32k_read NULL +#endif + +#ifdef CONFIG_ARCH_OMAP2420 +static cycle_t omap2420_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k; +} +#else +#define omap2420_32k_read NULL +#endif + +#ifdef CONFIG_ARCH_OMAP2430 +static cycle_t omap2430_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k; +} +#else +#define omap2430_32k_read NULL +#endif + +#ifdef CONFIG_ARCH_OMAP3 +static cycle_t omap34xx_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k; +} +#else +#define omap34xx_32k_read NULL +#endif + +#ifdef CONFIG_ARCH_OMAP4 +static cycle_t omap44xx_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k; +} +#else +#define omap44xx_32k_read NULL +#endif + +/* + * Kernel assumes that sched_clock can be called early but may not have + * things ready yet. + */ +static cycle_t omap_32k_read_dummy(struct clocksource *cs) +{ + return 0; +} + +static struct clocksource clocksource_32k = { + .name = "32k_counter", + .rating = 250, + .read = omap_32k_read_dummy, + .mask = CLOCKSOURCE_MASK(32), + .shift = 10, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +/* + * Returns current time from boot in nsecs. It's OK for this to wrap + * around for now, as it's just a relative time stamp. + */ +unsigned long long sched_clock(void) +{ + return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k), + clocksource_32k.mult, clocksource_32k.shift); +} + +/** + * read_persistent_clock - Return time from a persistent clock. + * + * Reads the time from a source which isn't disabled during PM, the + * 32k sync timer. Convert the cycles elapsed since last read into + * nsecs and adds to a monotonically increasing timespec. + */ +static struct timespec persistent_ts; +static cycles_t cycles, last_cycles; +void read_persistent_clock(struct timespec *ts) +{ + unsigned long long nsecs; + cycles_t delta; + struct timespec *tsp = &persistent_ts; + + last_cycles = cycles; + cycles = clocksource_32k.read(&clocksource_32k); + delta = cycles - last_cycles; + + nsecs = clocksource_cyc2ns(delta, + clocksource_32k.mult, clocksource_32k.shift); + + timespec_add_ns(tsp, nsecs); + *ts = *tsp; +} + +static int __init omap_init_clocksource_32k(void) +{ + static char err[] __initdata = KERN_ERR + "%s: can't register clocksource!\n"; + + if (cpu_is_omap16xx() || cpu_class_is_omap2()) { + struct clk *sync_32k_ick; + + if (cpu_is_omap16xx()) + clocksource_32k.read = omap16xx_32k_read; + else if (cpu_is_omap2420()) + clocksource_32k.read = omap2420_32k_read; + else if (cpu_is_omap2430()) + clocksource_32k.read = omap2430_32k_read; + else if (cpu_is_omap34xx()) + clocksource_32k.read = omap34xx_32k_read; + else if (cpu_is_omap44xx()) + clocksource_32k.read = omap44xx_32k_read; + else + return -ENODEV; + + sync_32k_ick = clk_get(NULL, "omap_32ksync_ick"); + if (sync_32k_ick) + clk_enable(sync_32k_ick); + + clocksource_32k.mult = clocksource_hz2mult(32768, + clocksource_32k.shift); + + offset_32k = clocksource_32k.read(&clocksource_32k); + + if (clocksource_register(&clocksource_32k)) + printk(err, clocksource_32k.name); + } + return 0; +} +arch_initcall(omap_init_clocksource_32k); + +#endif /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */ + +/* Global address base setup code */ + +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) + +static void __init __omap2_set_globals(struct omap_globals *omap2_globals) +{ + omap2_set_globals_tap(omap2_globals); + omap2_set_globals_sdrc(omap2_globals); + omap2_set_globals_control(omap2_globals); + omap2_set_globals_prcm(omap2_globals); + omap2_set_globals_uart(omap2_globals); +} + +#endif + +#if defined(CONFIG_ARCH_OMAP2420) + +static struct omap_globals omap242x_globals = { + .class = OMAP242X_CLASS, + .tap = OMAP2_L4_IO_ADDRESS(0x48014000), + .sdrc = OMAP2420_SDRC_BASE, + .sms = OMAP2420_SMS_BASE, + .ctrl = OMAP2420_CTRL_BASE, + .prm = OMAP2420_PRM_BASE, + .cm = OMAP2420_CM_BASE, + .uart1_phys = OMAP2_UART1_BASE, + .uart2_phys = OMAP2_UART2_BASE, + .uart3_phys = OMAP2_UART3_BASE, +}; + +void __init omap2_set_globals_242x(void) +{ + __omap2_set_globals(&omap242x_globals); +} +#endif + +#if defined(CONFIG_ARCH_OMAP2430) + +static struct omap_globals omap243x_globals = { + .class = OMAP243X_CLASS, + .tap = OMAP2_L4_IO_ADDRESS(0x4900a000), + .sdrc = OMAP243X_SDRC_BASE, + .sms = OMAP243X_SMS_BASE, + .ctrl = OMAP243X_CTRL_BASE, + .prm = OMAP2430_PRM_BASE, + .cm = OMAP2430_CM_BASE, + .uart1_phys = OMAP2_UART1_BASE, + .uart2_phys = OMAP2_UART2_BASE, + .uart3_phys = OMAP2_UART3_BASE, +}; + +void __init omap2_set_globals_243x(void) +{ + __omap2_set_globals(&omap243x_globals); +} +#endif + +#if defined(CONFIG_ARCH_OMAP3) + +static struct omap_globals omap3_globals = { + .class = OMAP343X_CLASS, + .tap = OMAP2_L4_IO_ADDRESS(0x4830A000), + .sdrc = OMAP343X_SDRC_BASE, + .sms = OMAP343X_SMS_BASE, + .ctrl = OMAP343X_CTRL_BASE, + .prm = OMAP3430_PRM_BASE, + .cm = OMAP3430_CM_BASE, + .uart1_phys = OMAP3_UART1_BASE, + .uart2_phys = OMAP3_UART2_BASE, + .uart3_phys = OMAP3_UART3_BASE, + .uart4_phys = OMAP3_UART4_BASE, /* Only on 3630 */ +}; + +void __init omap2_set_globals_3xxx(void) +{ + __omap2_set_globals(&omap3_globals); +} + +void __init omap3_map_io(void) +{ + omap2_set_globals_3xxx(); + omap34xx_map_common_io(); +} +#endif + +#if defined(CONFIG_ARCH_OMAP4) +static struct omap_globals omap4_globals = { + .class = OMAP443X_CLASS, + .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), + .ctrl = OMAP443X_CTRL_BASE, + .prm = OMAP4430_PRM_BASE, + .cm = OMAP4430_CM_BASE, + .cm2 = OMAP4430_CM2_BASE, + .uart1_phys = OMAP4_UART1_BASE, + .uart2_phys = OMAP4_UART2_BASE, + .uart3_phys = OMAP4_UART3_BASE, + .uart4_phys = OMAP4_UART4_BASE, +}; + +void __init omap2_set_globals_443x(void) +{ + omap2_set_globals_tap(&omap4_globals); + omap2_set_globals_control(&omap4_globals); + omap2_set_globals_prcm(&omap4_globals); + omap2_set_globals_uart(&omap4_globals); +} +#endif + diff --git a/trunk/arch/arm/plat-omap/counter_32k.c b/trunk/arch/arm/plat-omap/counter_32k.c deleted file mode 100644 index 155fe43a672b..000000000000 --- a/trunk/arch/arm/plat-omap/counter_32k.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * OMAP 32ksynctimer/counter_32k-related code - * - * Copyright (C) 2009 Texas Instruments - * Copyright (C) 2010 Nokia Corporation - * Tony Lindgren - * Added OMAP4 support - Santosh Shilimkar - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * NOTE: This timer is not the same timer as the old OMAP1 MPU timer. - */ -#include -#include -#include -#include - -#include -#include - -#include - - -/* - * 32KHz clocksource ... always available, on pretty most chips except - * OMAP 730 and 1510. Other timers could be used as clocksources, with - * higher resolution in free-running counter modes (e.g. 12 MHz xtal), - * but systems won't necessarily want to spend resources that way. - */ - -#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410 - -#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) - -#include - -/* - * offset_32k holds the init time counter value. It is then subtracted - * from every counter read to achieve a counter that counts time from the - * kernel boot (needed for sched_clock()). - */ -static u32 offset_32k __read_mostly; - -#ifdef CONFIG_ARCH_OMAP16XX -static cycle_t omap16xx_32k_read(struct clocksource *cs) -{ - return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k; -} -#else -#define omap16xx_32k_read NULL -#endif - -#ifdef CONFIG_ARCH_OMAP2420 -static cycle_t omap2420_32k_read(struct clocksource *cs) -{ - return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k; -} -#else -#define omap2420_32k_read NULL -#endif - -#ifdef CONFIG_ARCH_OMAP2430 -static cycle_t omap2430_32k_read(struct clocksource *cs) -{ - return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k; -} -#else -#define omap2430_32k_read NULL -#endif - -#ifdef CONFIG_ARCH_OMAP3 -static cycle_t omap34xx_32k_read(struct clocksource *cs) -{ - return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k; -} -#else -#define omap34xx_32k_read NULL -#endif - -#ifdef CONFIG_ARCH_OMAP4 -static cycle_t omap44xx_32k_read(struct clocksource *cs) -{ - return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k; -} -#else -#define omap44xx_32k_read NULL -#endif - -/* - * Kernel assumes that sched_clock can be called early but may not have - * things ready yet. - */ -static cycle_t omap_32k_read_dummy(struct clocksource *cs) -{ - return 0; -} - -static struct clocksource clocksource_32k = { - .name = "32k_counter", - .rating = 250, - .read = omap_32k_read_dummy, - .mask = CLOCKSOURCE_MASK(32), - .shift = 10, - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -/* - * Returns current time from boot in nsecs. It's OK for this to wrap - * around for now, as it's just a relative time stamp. - */ -unsigned long long sched_clock(void) -{ - return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k), - clocksource_32k.mult, clocksource_32k.shift); -} - -/** - * read_persistent_clock - Return time from a persistent clock. - * - * Reads the time from a source which isn't disabled during PM, the - * 32k sync timer. Convert the cycles elapsed since last read into - * nsecs and adds to a monotonically increasing timespec. - */ -static struct timespec persistent_ts; -static cycles_t cycles, last_cycles; -void read_persistent_clock(struct timespec *ts) -{ - unsigned long long nsecs; - cycles_t delta; - struct timespec *tsp = &persistent_ts; - - last_cycles = cycles; - cycles = clocksource_32k.read(&clocksource_32k); - delta = cycles - last_cycles; - - nsecs = clocksource_cyc2ns(delta, - clocksource_32k.mult, clocksource_32k.shift); - - timespec_add_ns(tsp, nsecs); - *ts = *tsp; -} - -static int __init omap_init_clocksource_32k(void) -{ - static char err[] __initdata = KERN_ERR - "%s: can't register clocksource!\n"; - - if (cpu_is_omap16xx() || cpu_class_is_omap2()) { - struct clk *sync_32k_ick; - - if (cpu_is_omap16xx()) - clocksource_32k.read = omap16xx_32k_read; - else if (cpu_is_omap2420()) - clocksource_32k.read = omap2420_32k_read; - else if (cpu_is_omap2430()) - clocksource_32k.read = omap2430_32k_read; - else if (cpu_is_omap34xx()) - clocksource_32k.read = omap34xx_32k_read; - else if (cpu_is_omap44xx()) - clocksource_32k.read = omap44xx_32k_read; - else - return -ENODEV; - - sync_32k_ick = clk_get(NULL, "omap_32ksync_ick"); - if (sync_32k_ick) - clk_enable(sync_32k_ick); - - clocksource_32k.mult = clocksource_hz2mult(32768, - clocksource_32k.shift); - - offset_32k = clocksource_32k.read(&clocksource_32k); - - if (clocksource_register(&clocksource_32k)) - printk(err, clocksource_32k.name); - } - return 0; -} -arch_initcall(omap_init_clocksource_32k); - -#endif /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */ - diff --git a/trunk/arch/arm/plat-omap/cpu-omap.c b/trunk/arch/arm/plat-omap/cpu-omap.c index 11c54ec8d47f..6d3d33360056 100644 --- a/trunk/arch/arm/plat-omap/cpu-omap.c +++ b/trunk/arch/arm/plat-omap/cpu-omap.c @@ -40,7 +40,7 @@ static struct clk *mpu_clk; /* TODO: Add support for SDRAM timing changes */ -static int omap_verify_speed(struct cpufreq_policy *policy) +int omap_verify_speed(struct cpufreq_policy *policy) { if (freq_table) return cpufreq_frequency_table_verify(policy, freq_table); @@ -58,7 +58,7 @@ static int omap_verify_speed(struct cpufreq_policy *policy) return 0; } -static unsigned int omap_getspeed(unsigned int cpu) +unsigned int omap_getspeed(unsigned int cpu) { unsigned long rate; diff --git a/trunk/arch/arm/plat-omap/devices.c b/trunk/arch/arm/plat-omap/devices.c index 1e2383eae638..d1920be7833b 100644 --- a/trunk/arch/arm/plat-omap/devices.c +++ b/trunk/arch/arm/plat-omap/devices.c @@ -21,6 +21,7 @@ #include #include +#include #include #include #include @@ -231,6 +232,46 @@ static void omap_init_uwire(void) static inline void omap_init_uwire(void) {} #endif +/*-------------------------------------------------------------------------*/ + +#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) + +static struct resource wdt_resources[] = { + { + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device omap_wdt_device = { + .name = "omap_wdt", + .id = -1, + .num_resources = ARRAY_SIZE(wdt_resources), + .resource = wdt_resources, +}; + +static void omap_init_wdt(void) +{ + if (cpu_is_omap16xx()) + wdt_resources[0].start = 0xfffeb000; + else if (cpu_is_omap2420()) + wdt_resources[0].start = 0x48022000; /* WDT2 */ + else if (cpu_is_omap2430()) + wdt_resources[0].start = 0x49016000; /* WDT2 */ + else if (cpu_is_omap343x()) + wdt_resources[0].start = 0x48314000; /* WDT2 */ + else if (cpu_is_omap44xx()) + wdt_resources[0].start = 0x4a314000; + else + return; + + wdt_resources[0].end = wdt_resources[0].start + 0x4f; + + (void) platform_device_register(&omap_wdt_device); +} +#else +static inline void omap_init_wdt(void) {} +#endif + /* * This gets called after board-specific INIT_MACHINE, and initializes most * on-chip peripherals accessible on this board (except for few like USB): @@ -259,6 +300,7 @@ static int __init omap_init_devices(void) omap_init_rng(); omap_init_mcpdm(); omap_init_uwire(); + omap_init_wdt(); return 0; } arch_initcall(omap_init_devices); diff --git a/trunk/arch/arm/plat-omap/dma.c b/trunk/arch/arm/plat-omap/dma.c index f5c5b8da9a87..ec7eddf9e525 100644 --- a/trunk/arch/arm/plat-omap/dma.c +++ b/trunk/arch/arm/plat-omap/dma.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include @@ -997,17 +996,11 @@ void omap_start_dma(int lch) l = dma_read(CCR(lch)); /* - * Errata: Inter Frame DMA buffering issue (All OMAP2420 and - * OMAP2430ES1.0): DMA will wrongly buffer elements if packing and - * bursting is enabled. This might result in data gets stalled in - * FIFO at the end of the block. - * Workaround: DMA channels must have BUFFERING_DISABLED bit set to - * guarantee no data will stay in the DMA FIFO in case inter frame - * buffering occurs. + * Errata: On ES2.0 BUFFERING disable must be set. + * This will always fail on ES1.0 */ - if (cpu_is_omap2420() || - (cpu_is_omap2430() && (omap_type() == OMAP2430_REV_ES1_0))) - l |= OMAP_DMA_CCR_BUFFERING_DISABLE; + if (cpu_is_omap24xx()) + l |= OMAP_DMA_CCR_EN; l |= OMAP_DMA_CCR_EN; dma_write(l, CCR(lch)); @@ -1025,39 +1018,8 @@ void omap_stop_dma(int lch) dma_write(0, CICR(lch)); l = dma_read(CCR(lch)); - /* OMAP3 Errata i541: sDMA FIFO draining does not finish */ - if (cpu_is_omap34xx() && (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) { - int i = 0; - u32 sys_cf; - - /* Configure No-Standby */ - l = dma_read(OCP_SYSCONFIG); - sys_cf = l; - l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK; - l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); - dma_write(l , OCP_SYSCONFIG); - - l = dma_read(CCR(lch)); - l &= ~OMAP_DMA_CCR_EN; - dma_write(l, CCR(lch)); - - /* Wait for sDMA FIFO drain */ - l = dma_read(CCR(lch)); - while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE | - OMAP_DMA_CCR_WR_ACTIVE))) { - udelay(5); - i++; - l = dma_read(CCR(lch)); - } - if (i >= 100) - printk(KERN_ERR "DMA drain did not complete on " - "lch %d\n", lch); - /* Restore OCP_SYSCONFIG */ - dma_write(sys_cf, OCP_SYSCONFIG); - } else { - l &= ~OMAP_DMA_CCR_EN; - dma_write(l, CCR(lch)); - } + l &= ~OMAP_DMA_CCR_EN; + dma_write(l, CCR(lch)); if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch = lch; diff --git a/trunk/arch/arm/plat-omap/dmtimer.c b/trunk/arch/arm/plat-omap/dmtimer.c index 1d706cf63ca0..44bafdab2dce 100644 --- a/trunk/arch/arm/plat-omap/dmtimer.c +++ b/trunk/arch/arm/plat-omap/dmtimer.c @@ -581,7 +581,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) * When the functional clock disappears, too quick writes seem * to cause an abort. XXX Is this still necessary? */ - __delay(300000); + __delay(150000); return ret; } diff --git a/trunk/arch/arm/plat-omap/fb.c b/trunk/arch/arm/plat-omap/fb.c index bb78c1532fae..71934817e172 100644 --- a/trunk/arch/arm/plat-omap/fb.c +++ b/trunk/arch/arm/plat-omap/fb.c @@ -36,8 +36,6 @@ #include #include -#include "fb.h" - #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) static struct omapfb_platform_data omapfb_config; diff --git a/trunk/arch/arm/plat-omap/fb.h b/trunk/arch/arm/plat-omap/fb.h deleted file mode 100644 index d765d0bd8520..000000000000 --- a/trunk/arch/arm/plat-omap/fb.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __PLAT_OMAP_FB_H__ -#define __PLAT_OMAP_FB_H__ - -extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart, - unsigned long sram_vstart, - unsigned long sram_size, - unsigned long pstart_avail, - unsigned long size_avail); - -#endif /* __PLAT_OMAP_FB_H__ */ diff --git a/trunk/arch/arm/plat-omap/gpio.c b/trunk/arch/arm/plat-omap/gpio.c index c05c653d1674..7951eefe1a0e 100644 --- a/trunk/arch/arm/plat-omap/gpio.c +++ b/trunk/arch/arm/plat-omap/gpio.c @@ -2084,10 +2084,9 @@ void omap2_gpio_prepare_for_idle(int power_state) for (i = min; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; - u32 l1 = 0, l2 = 0; - int j; + u32 l1, l2; - for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) + if (bank->dbck_enable_mask) clk_disable(bank->dbck); if (power_state > PWRDM_POWER_OFF) @@ -2152,10 +2151,9 @@ void omap2_gpio_resume_after_idle(void) min = 1; for (i = min; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; - u32 l = 0, gen, gen0, gen1; - int j; + u32 l, gen, gen0, gen1; - for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) + if (bank->dbck_enable_mask) clk_enable(bank->dbck); if (!workaround_enabled) diff --git a/trunk/arch/arm/plat-omap/include/plat/common.h b/trunk/arch/arm/plat-omap/include/plat/common.h index a9d69a09920d..9776b41ad76f 100644 --- a/trunk/arch/arm/plat-omap/include/plat/common.h +++ b/trunk/arch/arm/plat-omap/include/plat/common.h @@ -47,7 +47,6 @@ struct omap_globals { unsigned long sdrc; /* SDRAM Controller */ unsigned long sms; /* SDRAM Memory Scheduler */ unsigned long ctrl; /* System Control Module */ - unsigned long ctrl_pad; /* PAD Control Module */ unsigned long prm; /* Power and Reset Management */ unsigned long cm; /* Clock Management */ unsigned long cm2; @@ -67,6 +66,7 @@ void omap2_set_globals_tap(struct omap_globals *); void omap2_set_globals_sdrc(struct omap_globals *); void omap2_set_globals_control(struct omap_globals *); void omap2_set_globals_prcm(struct omap_globals *); +void omap2_set_globals_uart(struct omap_globals *); void omap3_map_io(void); @@ -91,8 +91,7 @@ void omap3_map_io(void); }) extern struct device *omap2_get_mpuss_device(void); -extern struct device *omap2_get_iva_device(void); +extern struct device *omap2_get_dsp_device(void); extern struct device *omap2_get_l3_device(void); -extern struct device *omap4_get_dsp_device(void); #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ diff --git a/trunk/arch/arm/mach-omap2/control.h b/trunk/arch/arm/plat-omap/include/plat/control.h similarity index 92% rename from trunk/arch/arm/mach-omap2/control.h rename to trunk/arch/arm/plat-omap/include/plat/control.h index b6c6b7c450b3..131bf405c2f6 100644 --- a/trunk/arch/arm/mach-omap2/control.h +++ b/trunk/arch/arm/plat-omap/include/plat/control.h @@ -1,10 +1,10 @@ /* - * arch/arm/mach-omap2/control.h + * arch/arm/plat-omap/include/mach/control.h * * OMAP2/3/4 System Control Module definitions * - * Copyright (C) 2007-2010 Texas Instruments, Inc. - * Copyright (C) 2007-2008, 2010 Nokia Corporation + * Copyright (C) 2007-2009 Texas Instruments, Inc. + * Copyright (C) 2007-2008 Nokia Corporation * * Written by Paul Walmsley * @@ -13,14 +13,10 @@ * the Free Software Foundation. */ -#ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H -#define __ARCH_ARM_MACH_OMAP2_CONTROL_H +#ifndef __ASM_ARCH_CONTROL_H +#define __ASM_ARCH_CONTROL_H #include -#include -#include -#include -#include #ifndef __ASSEMBLY__ #define OMAP242X_CTRL_REGADDR(reg) \ @@ -208,6 +204,12 @@ #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 +/* 44xx control status register offset */ +#define OMAP44XX_CONTROL_STATUS 0x2c4 + +/* 44xx-only CONTROL_GENERAL register offsets */ +#define OMAP44XX_CONTROL_MMC1 0x628 +#define OMAP44XX_CONTROL_PBIAS_LITE 0x600 /* * REVISIT: This list of registers is not comprehensive - there are more * that should be added. @@ -223,8 +225,6 @@ #define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ #define OMAP24XX_USBSTANDBYCTRL (1 << 15) #define OMAP2_MCBSP2_CLKS_MASK (1 << 6) -#define OMAP2_MCBSP1_FSR_MASK (1 << 4) -#define OMAP2_MCBSP1_CLKR_MASK (1 << 3) #define OMAP2_MCBSP1_CLKS_MASK (1 << 2) /* CONTROL_DEVCONF1 bits */ @@ -255,6 +255,23 @@ #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) #define OMAP2_PBIASLITEVMODE0 (1 << 0) +/* CONTROL_PBIAS_LITE bits for OMAP4 */ +#define OMAP4_MMC1_PWRDNZ (1 << 26) +#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25) +#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24) +#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23) +#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22) +#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21) +#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20) + +#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31) +#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30) +#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29) +#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28) +#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27) +#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26) +#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25) + /* CONTROL_PROG_IO1 bits */ #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) @@ -321,12 +338,12 @@ #define FEAT_L2CACHE_256KB 3 #define OMAP3_ISP_SHIFT 5 -#define OMAP3_ISP_MASK (1 << OMAP3_ISP_SHIFT) +#define OMAP3_ISP_MASK (1<< OMAP3_ISP_SHIFT) #define FEAT_ISP 0 #define FEAT_ISP_NONE 1 #define OMAP3_NEON_SHIFT 4 -#define OMAP3_NEON_MASK (1 << OMAP3_NEON_SHIFT) +#define OMAP3_NEON_MASK (1<< OMAP3_NEON_SHIFT) #define FEAT_NEON 0 #define FEAT_NEON_NONE 1 @@ -337,11 +354,9 @@ extern void __iomem *omap_ctrl_base_get(void); extern u8 omap_ctrl_readb(u16 offset); extern u16 omap_ctrl_readw(u16 offset); extern u32 omap_ctrl_readl(u16 offset); -extern u32 omap4_ctrl_pad_readl(u16 offset); extern void omap_ctrl_writeb(u8 val, u16 offset); extern void omap_ctrl_writew(u16 val, u16 offset); extern void omap_ctrl_writel(u32 val, u16 offset); -extern void omap4_ctrl_pad_writel(u32 val, u16 offset); extern void omap3_save_scratchpad_contents(void); extern void omap3_clear_scratchpad_contents(void); @@ -356,13 +371,11 @@ extern void omap3_control_restore_context(void); #define omap_ctrl_readb(x) 0 #define omap_ctrl_readw(x) 0 #define omap_ctrl_readl(x) 0 -#define omap4_ctrl_pad_readl(x) 0 #define omap_ctrl_writeb(x, y) WARN_ON(1) #define omap_ctrl_writew(x, y) WARN_ON(1) #define omap_ctrl_writel(x, y) WARN_ON(1) -#define omap4_ctrl_pad_writel(x, y) WARN_ON(1) #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */ +#endif /* __ASM_ARCH_CONTROL_H */ diff --git a/trunk/arch/arm/plat-omap/include/plat/cpu.h b/trunk/arch/arm/plat-omap/include/plat/cpu.h index 3fd8b4055727..2e2ae530fced 100644 --- a/trunk/arch/arm/plat-omap/include/plat/cpu.h +++ b/trunk/arch/arm/plat-omap/include/plat/cpu.h @@ -68,9 +68,10 @@ unsigned int omap_rev(void); #define OMAP_REVBITS_00 0x00 #define OMAP_REVBITS_01 0x01 #define OMAP_REVBITS_02 0x02 -#define OMAP_REVBITS_03 0x03 -#define OMAP_REVBITS_04 0x04 -#define OMAP_REVBITS_05 0x05 +#define OMAP_REVBITS_10 0x10 +#define OMAP_REVBITS_20 0x20 +#define OMAP_REVBITS_30 0x30 +#define OMAP_REVBITS_40 0x40 /* * Get the CPU revision for OMAP devices @@ -362,24 +363,23 @@ IS_OMAP_TYPE(3517, 0x3517) /* Various silicon revisions for omap2 */ #define OMAP242X_CLASS 0x24200024 -#define OMAP2420_REV_ES1_0 OMAP242X_CLASS -#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8)) +#define OMAP2420_REV_ES1_0 0x24200024 +#define OMAP2420_REV_ES2_0 0x24201024 #define OMAP243X_CLASS 0x24300024 -#define OMAP2430_REV_ES1_0 OMAP243X_CLASS +#define OMAP2430_REV_ES1_0 0x24300024 #define OMAP343X_CLASS 0x34300034 -#define OMAP3430_REV_ES1_0 OMAP343X_CLASS -#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8)) -#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8)) -#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8)) -#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8)) -#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8)) - -#define OMAP363X_CLASS 0x36300034 -#define OMAP3630_REV_ES1_0 OMAP363X_CLASS -#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8)) -#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8)) +#define OMAP3430_REV_ES1_0 0x34300034 +#define OMAP3430_REV_ES2_0 0x34301034 +#define OMAP3430_REV_ES2_1 0x34302034 +#define OMAP3430_REV_ES3_0 0x34303034 +#define OMAP3430_REV_ES3_1 0x34304034 +#define OMAP3430_REV_ES3_1_2 0x34305034 + +#define OMAP3630_REV_ES1_0 0x36300034 +#define OMAP3630_REV_ES1_1 0x36300134 +#define OMAP3630_REV_ES1_2 0x36300234 #define OMAP35XX_CLASS 0x35000034 #define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) @@ -390,8 +390,7 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8)) #define OMAP443X_CLASS 0x44300044 -#define OMAP4430_REV_ES1_0 OMAP443X_CLASS -#define OMAP4430_REV_ES2_0 0x44301044 +#define OMAP4430_REV_ES1_0 0x44300044 /* * omap_chip bits @@ -418,12 +417,10 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP4430ES1 (1 << 8) #define CHIP_IS_OMAP3630ES1_1 (1 << 9) #define CHIP_IS_OMAP3630ES1_2 (1 << 10) -#define CHIP_IS_OMAP4430ES2 (1 << 11) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) -#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ - CHIP_IS_OMAP4430ES2) +#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1) /* * "GE" here represents "greater than or equal to" in terms of ES diff --git a/trunk/arch/arm/plat-omap/include/plat/dma.h b/trunk/arch/arm/plat-omap/include/plat/dma.h index 0cce4ca83aa0..af3a03941add 100644 --- a/trunk/arch/arm/plat-omap/include/plat/dma.h +++ b/trunk/arch/arm/plat-omap/include/plat/dma.h @@ -319,8 +319,6 @@ #define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ #define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ -#define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */ -#define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */ /*----------------------------------------------------------------------------*/ #define OMAP1_DMA_TOUT_IRQ (1 << 0) @@ -337,10 +335,6 @@ #define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) #define OMAP_DMA_CCR_EN (1 << 7) -#define OMAP_DMA_CCR_RD_ACTIVE (1 << 9) -#define OMAP_DMA_CCR_WR_ACTIVE (1 << 10) -#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC (1 << 24) -#define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25) #define OMAP_DMA_DATA_TYPE_S8 0x00 #define OMAP_DMA_DATA_TYPE_S16 0x01 diff --git a/trunk/arch/arm/plat-omap/include/plat/dmtimer.h b/trunk/arch/arm/plat-omap/include/plat/dmtimer.h index dfa3aff9761b..20f1054c0a80 100644 --- a/trunk/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/trunk/arch/arm/plat-omap/include/plat/dmtimer.h @@ -45,8 +45,6 @@ #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 struct omap_dm_timer; -extern struct omap_dm_timer *gptimer_wakeup; -extern struct sys_timer omap_timer; struct clk; int omap_dm_timer_init(void); diff --git a/trunk/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h b/trunk/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h deleted file mode 100644 index 872de0bf1e6b..000000000000 --- a/trunk/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * arch/arm/plat-omap/include/plat/gpmc-smsc911x.h - * - * Copyright (C) 2009 Li-Pro.Net - * Stephan Linz - * - * Modified from arch/arm/plat-omap/include/plat/gpmc-smc91x.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_OMAP_GPMC_SMSC911X_H__ - -struct omap_smsc911x_platform_data { - int cs; - int gpio_irq; - int gpio_reset; - u32 flags; -}; - -#if defined(CONFIG_SMSC911X) || \ - defined(CONFIG_SMSC911X_MODULE) - -extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d); - -#else - -static inline void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d) -{ -} - -#endif -#endif diff --git a/trunk/arch/arm/plat-omap/include/plat/i2c.h b/trunk/arch/arm/plat-omap/include/plat/i2c.h index 36a0befd6168..87f6bf2ea4fa 100644 --- a/trunk/arch/arm/plat-omap/include/plat/i2c.h +++ b/trunk/arch/arm/plat-omap/include/plat/i2c.h @@ -18,8 +18,6 @@ * 02110-1301 USA * */ -#ifndef __ASM__ARCH_OMAP_I2C_H -#define __ASM__ARCH_OMAP_I2C_H #include @@ -38,5 +36,3 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, void __init omap1_i2c_mux_pins(int bus_id); void __init omap2_i2c_mux_pins(int bus_id); - -#endif /* __ASM__ARCH_OMAP_I2C_H */ diff --git a/trunk/arch/arm/plat-omap/include/plat/irqs.h b/trunk/arch/arm/plat-omap/include/plat/irqs.h index 65e20a686713..c01d9f08a198 100644 --- a/trunk/arch/arm/plat-omap/include/plat/irqs.h +++ b/trunk/arch/arm/plat-omap/include/plat/irqs.h @@ -345,8 +345,6 @@ #define INT_34XX_MMC3_IRQ 94 #define INT_34XX_GPT12_IRQ 95 -#define INT_36XX_UART4_IRQ 80 - #define INT_35XX_HECC0_IRQ 24 #define INT_35XX_HECC1_IRQ 28 #define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67 diff --git a/trunk/arch/arm/plat-omap/include/plat/mcbsp.h b/trunk/arch/arm/plat-omap/include/plat/mcbsp.h index b87d83ccd545..5b20103e68eb 100644 --- a/trunk/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/trunk/arch/arm/plat-omap/include/plat/mcbsp.h @@ -319,18 +319,6 @@ static struct platform_device omap_mcbsp##port_nr = { \ #define RFSREN 0x0002 #define RSYNCERREN 0x0001 -/* CLKR signal muxing options */ -#define CLKR_SRC_CLKR 0 -#define CLKR_SRC_CLKX 1 - -/* FSR signal muxing options */ -#define FSR_SRC_FSR 0 -#define FSR_SRC_FSX 1 - -/* McBSP functional clock sources */ -#define MCBSP_CLKS_PRCM_SRC 0 -#define MCBSP_CLKS_PAD_SRC 1 - /* we don't do multichannel for now */ struct omap_mcbsp_reg_cfg { u16 spcr2; @@ -417,7 +405,6 @@ struct omap_mcbsp_spi_cfg { struct omap_mcbsp_ops { void (*request)(unsigned int); void (*free)(unsigned int); - int (*set_clks_src)(u8, u8); }; struct omap_mcbsp_platform_data { @@ -484,9 +471,6 @@ struct omap_mcbsp { extern struct omap_mcbsp **mcbsp_ptr; extern int omap_mcbsp_count, omap_mcbsp_cache_size; -#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count) -#define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; - int omap_mcbsp_init(void); void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, int size); @@ -525,8 +509,6 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word); int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word); -/* McBSP functional clock source changing function */ -extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id); /* SPI specific API */ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg); @@ -535,10 +517,6 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf); int omap_mcbsp_pollwrite(unsigned int id, u16 buf); int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type); -/* McBSP signal muxing API */ -void omap2_mcbsp1_mux_clkr_src(u8 mux); -void omap2_mcbsp1_mux_fsr_src(u8 mux); - #ifdef CONFIG_ARCH_OMAP3 /* Sidetone specific API */ int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); diff --git a/trunk/arch/arm/plat-omap/include/plat/mmc.h b/trunk/arch/arm/plat-omap/include/plat/mmc.h index f57f36abb07e..9b89ec601ee2 100644 --- a/trunk/arch/arm/plat-omap/include/plat/mmc.h +++ b/trunk/arch/arm/plat-omap/include/plat/mmc.h @@ -71,17 +71,12 @@ struct omap_mmc_platform_data { u64 dma_mask; - /* Register offset deviation */ - u16 reg_offset; - struct omap_mmc_slot_data { - /* - * 4/8 wires and any additional host capabilities - * need to OR'd all capabilities (ref. linux/mmc/host.h) + /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC; + * 8 wire signaling is also optional, and is used with HSMMC */ - u8 wires; /* Used for the MMC driver on omap1 and 2420 */ - u32 caps; /* Used for the MMC driver on 2430 and later */ + u8 wires; /* * nomux means "standard" muxing is wrong on this board, and @@ -109,7 +104,6 @@ struct omap_mmc_platform_data { /* we can put the features above into this variable */ #define HSMMC_HAS_PBIAS (1 << 0) -#define HSMMC_HAS_UPDATED_RESET (1 << 1) unsigned features; int switch_pin; /* gpio (card detect) */ diff --git a/trunk/arch/arm/plat-omap/include/plat/omap-serial.h b/trunk/arch/arm/plat-omap/include/plat/omap-serial.h deleted file mode 100644 index c8dae02f0704..000000000000 --- a/trunk/arch/arm/plat-omap/include/plat/omap-serial.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Driver for OMAP-UART controller. - * Based on drivers/serial/8250.c - * - * Copyright (C) 2010 Texas Instruments. - * - * Authors: - * Govindraj R - * Thara Gopinath - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __OMAP_SERIAL_H__ -#define __OMAP_SERIAL_H__ - -#include -#include - -#include - -#define DRIVER_NAME "omap-hsuart" - -/* - * Use tty device name as ttyO, [O -> OMAP] - * in bootargs we specify as console=ttyO0 if uart1 - * is used as console uart. - */ -#define OMAP_SERIAL_NAME "ttyO" - -#define OMAP_MDR1_DISABLE 0x07 -#define OMAP_MDR1_MODE13X 0x03 -#define OMAP_MDR1_MODE16X 0x00 -#define OMAP_MODE13X_SPEED 230400 - -/* - * LCR = 0XBF: Switch to Configuration Mode B. - * In configuration mode b allow access - * to EFR,DLL,DLH. - * Reference OMAP TRM Chapter 17 - * Section: 1.4.3 Mode Selection - */ -#define OMAP_UART_LCR_CONF_MDB 0XBF - -/* WER = 0x7F - * Enable module level wakeup in WER reg - */ -#define OMAP_UART_WER_MOD_WKUP 0X7F - -/* Enable XON/XOFF flow control on output */ -#define OMAP_UART_SW_TX 0x04 - -/* Enable XON/XOFF flow control on input */ -#define OMAP_UART_SW_RX 0x04 - -#define OMAP_UART_SYSC_RESET 0X07 -#define OMAP_UART_TCR_TRIG 0X0F -#define OMAP_UART_SW_CLR 0XF0 -#define OMAP_UART_FIFO_CLR 0X06 - -#define OMAP_UART_DMA_CH_FREE -1 - -#define RX_TIMEOUT (3 * HZ) -#define OMAP_MAX_HSUART_PORTS 4 - -#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA - -struct omap_uart_port_info { - bool dma_enabled; /* To specify DMA Mode */ - unsigned int uartclk; /* UART clock rate */ - void __iomem *membase; /* ioremap cookie or NULL */ - resource_size_t mapbase; /* resource base */ - unsigned long irqflags; /* request_irq flags */ - upf_t flags; /* UPF_* flags */ -}; - -struct uart_omap_dma { - u8 uart_dma_tx; - u8 uart_dma_rx; - int rx_dma_channel; - int tx_dma_channel; - dma_addr_t rx_buf_dma_phys; - dma_addr_t tx_buf_dma_phys; - unsigned int uart_base; - /* - * Buffer for rx dma.It is not required for tx because the buffer - * comes from port structure. - */ - unsigned char *rx_buf; - unsigned int prev_rx_dma_pos; - int tx_buf_size; - int tx_dma_used; - int rx_dma_used; - spinlock_t tx_lock; - spinlock_t rx_lock; - /* timer to poll activity on rx dma */ - struct timer_list rx_timer; - int rx_buf_size; - int rx_timeout; -}; - -struct uart_omap_port { - struct uart_port port; - struct uart_omap_dma uart_dma; - struct platform_device *pdev; - - unsigned char ier; - unsigned char lcr; - unsigned char mcr; - unsigned char fcr; - unsigned char efr; - - int use_dma; - /* - * Some bits in registers are cleared on a read, so they must - * be saved whenever the register is read but the bits will not - * be immediately processed. - */ - unsigned int lsr_break_flag; - unsigned char msr_saved_flags; - char name[20]; - unsigned long port_activity; -}; - -#endif /* __OMAP_SERIAL_H__ */ diff --git a/trunk/arch/arm/plat-omap/include/plat/omap24xx.h b/trunk/arch/arm/plat-omap/include/plat/omap24xx.h index 92df9e27cc5c..7055672a8c68 100644 --- a/trunk/arch/arm/plat-omap/include/plat/omap24xx.h +++ b/trunk/arch/arm/plat-omap/include/plat/omap24xx.h @@ -40,7 +40,7 @@ #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) #define OMAP24XX_IVA_INTC_BASE 0x40000000 -#define OMAP242X_CTRL_BASE L4_24XX_BASE +#define OMAP2420_CTRL_BASE L4_24XX_BASE #define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) #define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000) #define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000) diff --git a/trunk/arch/arm/plat-omap/include/plat/omap_device.h b/trunk/arch/arm/plat-omap/include/plat/omap_device.h index 28e2d1a78433..25cd9ac3b095 100644 --- a/trunk/arch/arm/plat-omap/include/plat/omap_device.h +++ b/trunk/arch/arm/plat-omap/include/plat/omap_device.h @@ -36,8 +36,6 @@ #include -extern struct device omap_device_parent; - /* omap_device._state values */ #define OMAP_DEVICE_STATE_UNKNOWN 0 #define OMAP_DEVICE_STATE_ENABLED 1 @@ -64,6 +62,7 @@ extern struct device omap_device_parent; * */ struct omap_device { + u32 magic; struct platform_device pdev; struct omap_hwmod **hwmods; struct omap_device_pm_latency *pm_lats; @@ -83,6 +82,7 @@ int omap_device_shutdown(struct platform_device *pdev); /* Core code interface */ +bool omap_device_is_valid(struct omap_device *od); int omap_device_count_resources(struct omap_device *od); int omap_device_fill_resources(struct omap_device *od, struct resource *res); diff --git a/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h b/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h index 7eaa8edf3b14..a4e508dfaba2 100644 --- a/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -14,16 +14,19 @@ * * These headers and macros are used to define OMAP on-chip module * data and their integration with other OMAP modules and Linux. - * Copious documentation and references can also be found in the - * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this - * writing). + * + * References: + * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) + * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) + * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) + * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) + * - Open Core Protocol Specification 2.2 * * To do: * - add interconnect error log structures * - add pinmuxing * - init_conn_id_bit (CONNID_BIT_VECTOR) * - implement default hwmod SMS/SDRC flags? - * - remove unused fields * */ #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H @@ -32,7 +35,6 @@ #include #include #include -#include #include struct omap_device; @@ -94,7 +96,7 @@ struct omap_hwmod_irq_info { /** * struct omap_hwmod_dma_info - DMA channels used by the hwmod * @name: name of the DMA channel (module local name) - * @dma_req: DMA request ID + * @dma_ch: DMA channel ID * * @name should be something short, e.g., "tx" or "rx". It is for use * by platform_get_resource_byname(). It is defined locally to the @@ -102,20 +104,7 @@ struct omap_hwmod_irq_info { */ struct omap_hwmod_dma_info { const char *name; - u16 dma_req; -}; - -/** - * struct omap_hwmod_rst_info - IPs reset lines use by hwmod - * @name: name of the reset line (module local name) - * @rst_shift: Offset of the reset bit - * - * @name should be something short, e.g., "cpu0" or "rst". It is defined - * locally to the hwmod. - */ -struct omap_hwmod_rst_info { - const char *name; - u8 rst_shift; + u16 dma_ch; }; /** @@ -248,9 +237,8 @@ struct omap_hwmod_ocp_if { #define SYSC_HAS_CLOCKACTIVITY (1 << 4) #define SYSC_HAS_SIDLEMODE (1 << 5) #define SYSC_HAS_MIDLEMODE (1 << 6) -#define SYSS_HAS_RESET_STATUS (1 << 7) +#define SYSS_MISSING (1 << 7) #define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */ -#define SYSC_HAS_RESET_STATUS (1 << 9) /* omap_hwmod_sysconfig.clockact flags */ #define CLOCKACT_TEST_BOTH 0x0 @@ -339,12 +327,10 @@ struct omap_hwmod_omap2_prcm { /** * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data * @clkctrl_reg: PRCM address of the clock control register - * @rstctrl_reg: adress of the XXX_RSTCTRL register located in the PRM * @submodule_wkdep_bit: bit shift of the WKDEP range */ struct omap_hwmod_omap4_prcm { void __iomem *clkctrl_reg; - void __iomem *rstctrl_reg; u8 submodule_wkdep_bit; }; @@ -366,11 +352,6 @@ struct omap_hwmod_omap4_prcm { * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup * HWMOD_NO_IDLEST : this module does not have idle status - this is the case * only for few initiator modules on OMAP2 & 3. - * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset. - * This is needed for devices like DSS that require optional clocks enabled - * in order to complete the reset. Optional clocks will be disabled - * again after the reset. - * HWMOD_16BIT_REG: Module has 16bit registers */ #define HWMOD_SWSUP_SIDLE (1 << 0) #define HWMOD_SWSUP_MSTANDBY (1 << 1) @@ -379,8 +360,6 @@ struct omap_hwmod_omap4_prcm { #define HWMOD_NO_OCP_AUTOIDLE (1 << 4) #define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) #define HWMOD_NO_IDLEST (1 << 6) -#define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7) -#define HWMOD_16BIT_REG (1 << 8) /* * omap_hwmod._int_flags definitions @@ -431,7 +410,7 @@ struct omap_hwmod_class { * @class: struct omap_hwmod_class * to the class of this hwmod * @od: struct omap_device currently associated with this hwmod (internal use) * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) - * @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt) + * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt) * @prcm: PRCM data pertaining to this hwmod * @main_clk: main clock: OMAP clock name * @_clk: pointer to the main struct clk (filled in at runtime) @@ -445,7 +424,7 @@ struct omap_hwmod_class { * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6) * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift * @mpu_irqs_cnt: number of @mpu_irqs - * @sdma_reqs_cnt: number of @sdma_reqs + * @sdma_chs_cnt: number of @sdma_chs * @opt_clks_cnt: number of @opt_clks * @master_cnt: number of @master entries * @slaves_cnt: number of @slave entries @@ -454,7 +433,6 @@ struct omap_hwmod_class { * @_state: internal-use hwmod state * @flags: hwmod flags (documented below) * @omap_chip: OMAP chips this hwmod is present on - * @_mutex: mutex serializing operations on this hwmod * @node: list node for hwmod list (internal use) * * @main_clk refers to this module's "main clock," which for our @@ -470,8 +448,7 @@ struct omap_hwmod { struct omap_hwmod_class *class; struct omap_device *od; struct omap_hwmod_irq_info *mpu_irqs; - struct omap_hwmod_dma_info *sdma_reqs; - struct omap_hwmod_rst_info *rst_lines; + struct omap_hwmod_dma_info *sdma_chs; union { struct omap_hwmod_omap2_prcm omap2; struct omap_hwmod_omap4_prcm omap4; @@ -484,7 +461,6 @@ struct omap_hwmod { void *dev_attr; u32 _sysc_cache; void __iomem *_mpu_rt_va; - struct mutex _mutex; struct list_head node; u16 flags; u8 _mpu_port_index; @@ -492,8 +468,7 @@ struct omap_hwmod { u8 msuspendmux_shift; u8 response_lat; u8 mpu_irqs_cnt; - u8 sdma_reqs_cnt; - u8 rst_lines_cnt; + u8 sdma_chs_cnt; u8 opt_clks_cnt; u8 masters_cnt; u8 slaves_cnt; @@ -517,10 +492,6 @@ int omap_hwmod_idle(struct omap_hwmod *oh); int _omap_hwmod_idle(struct omap_hwmod *oh); int omap_hwmod_shutdown(struct omap_hwmod *oh); -int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name); -int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name); -int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name); - int omap_hwmod_enable_clocks(struct omap_hwmod *oh); int omap_hwmod_disable_clocks(struct omap_hwmod *oh); @@ -529,8 +500,8 @@ int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode); int omap_hwmod_reset(struct omap_hwmod *oh); void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); -void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs); -u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs); +void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs); +u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs); int omap_hwmod_count_resources(struct omap_hwmod *oh); int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); @@ -563,6 +534,5 @@ int omap_hwmod_for_each_by_class(const char *classname, extern int omap2420_hwmod_init(void); extern int omap2430_hwmod_init(void); extern int omap3xxx_hwmod_init(void); -extern int omap44xx_hwmod_init(void); #endif diff --git a/trunk/arch/arm/plat-omap/include/plat/powerdomain.h b/trunk/arch/arm/plat-omap/include/plat/powerdomain.h index 9ca420dcd2f8..fb6ec74fe39e 100644 --- a/trunk/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/trunk/arch/arm/plat-omap/include/plat/powerdomain.h @@ -32,7 +32,6 @@ /* Powerdomain allowable state bitfields */ #define PWRSTS_ON (1 << PWRDM_POWER_ON) -#define PWRSTS_OFF (1 << PWRDM_POWER_OFF) #define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ (1 << PWRDM_POWER_ON)) @@ -162,6 +161,5 @@ int pwrdm_state_switch(struct powerdomain *pwrdm); int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); int pwrdm_pre_transition(void); int pwrdm_post_transition(void); -int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); #endif diff --git a/trunk/arch/arm/plat-omap/include/plat/prcm.h b/trunk/arch/arm/plat-omap/include/plat/prcm.h index ab77442e42ab..9fbd91419cd1 100644 --- a/trunk/arch/arm/plat-omap/include/plat/prcm.h +++ b/trunk/arch/arm/plat-omap/include/plat/prcm.h @@ -38,8 +38,6 @@ u32 prm_read_mod_reg(s16 module, u16 idx); void prm_write_mod_reg(u32 val, s16 module, u16 idx); u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); -u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask); -u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg); u32 cm_read_mod_reg(s16 module, u16 idx); void cm_write_mod_reg(u32 val, s16 module, u16 idx); u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); diff --git a/trunk/arch/arm/plat-omap/include/plat/sdrc.h b/trunk/arch/arm/plat-omap/include/plat/sdrc.h index efd87c8dda69..7b76f50564ba 100644 --- a/trunk/arch/arm/plat-omap/include/plat/sdrc.h +++ b/trunk/arch/arm/plat-omap/include/plat/sdrc.h @@ -147,7 +147,6 @@ struct memory_timings { }; extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode); -struct omap_sdrc_params *rx51_get_sdram_timings(void); u32 omap2xxx_sdrc_dll_is_unlocked(void); u32 omap2xxx_sdrc_reprogram(u32 level, u32 force); diff --git a/trunk/arch/arm/plat-omap/include/plat/sram.h b/trunk/arch/arm/plat-omap/include/plat/sram.h index 5905100b29a1..16a1b458d53c 100644 --- a/trunk/arch/arm/plat-omap/include/plat/sram.h +++ b/trunk/arch/arm/plat-omap/include/plat/sram.h @@ -11,6 +11,7 @@ #ifndef __ARCH_ARM_OMAP_SRAM_H #define __ARCH_ARM_OMAP_SRAM_H +extern int __init omap_sram_init(void); extern void * omap_sram_push(void * start, unsigned long size); extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); diff --git a/trunk/arch/arm/mach-omap2/timer-gp.h b/trunk/arch/arm/plat-omap/include/plat/timer-gp.h similarity index 86% rename from trunk/arch/arm/mach-omap2/timer-gp.h rename to trunk/arch/arm/plat-omap/include/plat/timer-gp.h index 5c1072c6783b..c88d346b59d9 100644 --- a/trunk/arch/arm/mach-omap2/timer-gp.h +++ b/trunk/arch/arm/plat-omap/include/plat/timer-gp.h @@ -11,6 +11,7 @@ #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H -extern int __init omap2_gp_clockevent_set_gptimer(u8 id); +int __init omap2_gp_clockevent_set_gptimer(u8 id); #endif + diff --git a/trunk/arch/arm/plat-omap/include/plat/uncompress.h b/trunk/arch/arm/plat-omap/include/plat/uncompress.h index 9036e374e0ac..ddf723be48dc 100644 --- a/trunk/arch/arm/plat-omap/include/plat/uncompress.h +++ b/trunk/arch/arm/plat-omap/include/plat/uncompress.h @@ -139,14 +139,10 @@ static inline void __arch_decomp_setup(unsigned long arch_id) DEBUG_LL_OMAP2(1, omap3evm); DEBUG_LL_OMAP3(1, omap_3430sdp); DEBUG_LL_OMAP3(1, omap_3630sdp); - DEBUG_LL_OMAP3(1, omap3530_lv_som); - DEBUG_LL_OMAP3(1, omap3_torpedo); /* omap3 based boards using UART3 */ DEBUG_LL_OMAP3(3, cm_t35); - DEBUG_LL_OMAP3(3, cm_t3517); DEBUG_LL_OMAP3(3, igep0020); - DEBUG_LL_OMAP3(3, igep0030); DEBUG_LL_OMAP3(3, nokia_rx51); DEBUG_LL_OMAP3(3, omap3517evm); DEBUG_LL_OMAP3(3, omap3_beagle); @@ -157,7 +153,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id) /* omap4 based boards using UART3 */ DEBUG_LL_OMAP4(3, omap_4430sdp); - DEBUG_LL_OMAP4(3, omap4_panda); /* zoom2/3 external uart */ DEBUG_LL_ZOOM(omap_zoom2); diff --git a/trunk/arch/arm/plat-omap/include/plat/usb.h b/trunk/arch/arm/plat-omap/include/plat/usb.h index 59c7fe731f28..9feddacfe850 100644 --- a/trunk/arch/arm/plat-omap/include/plat/usb.h +++ b/trunk/arch/arm/plat-omap/include/plat/usb.h @@ -105,7 +105,7 @@ static inline void omap1_usb_init(struct omap_usb_config *pdata) #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE) void omap2_usbfs_init(struct omap_usb_config *pdata); #else -static inline void omap2_usbfs_init(struct omap_usb_config *pdata) +static inline omap2_usbfs_init(struct omap_usb_config *pdata) { } #endif diff --git a/trunk/arch/arm/plat-omap/mcbsp.c b/trunk/arch/arm/plat-omap/mcbsp.c index eac4b978e9fd..0c8612fd8312 100644 --- a/trunk/arch/arm/plat-omap/mcbsp.c +++ b/trunk/arch/arm/plat-omap/mcbsp.c @@ -33,7 +33,7 @@ struct omap_mcbsp **mcbsp_ptr; int omap_mcbsp_count, omap_mcbsp_cache_size; -static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) +void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) { if (cpu_class_is_omap1()) { ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val; @@ -47,7 +47,7 @@ static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) } } -static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) +int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) { if (cpu_class_is_omap1()) { return !from_cache ? __raw_readw(mcbsp->io_base + reg) : @@ -62,12 +62,12 @@ static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) } #ifdef CONFIG_ARCH_OMAP3 -static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) +void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) { __raw_writel(val, mcbsp->st_data->io_base_st + reg); } -static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) +int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) { return __raw_readl(mcbsp->st_data->io_base_st + reg); } @@ -80,6 +80,9 @@ static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) #define MCBSP_READ_CACHE(mcbsp, reg) \ omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1) +#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count) +#define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; + #define MCBSP_ST_READ(mcbsp, reg) \ omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg) #define MCBSP_ST_WRITE(mcbsp, reg, val) \ @@ -875,7 +878,7 @@ EXPORT_SYMBOL(omap_mcbsp_free); void omap_mcbsp_start(unsigned int id, int tx, int rx) { struct omap_mcbsp *mcbsp; - int enable_srg = 0; + int idle; u16 w; if (!omap_mcbsp_check_valid_id(id)) { @@ -890,13 +893,10 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7; mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7; - /* Only enable SRG, if McBSP is master */ - w = MCBSP_READ_CACHE(mcbsp, PCR0); - if (w & (FSXM | FSRM | CLKXM | CLKRM)) - enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | - MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); + idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | + MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); - if (enable_srg) { + if (idle) { /* Start the sample generator */ w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); @@ -919,7 +919,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) */ udelay(500); - if (enable_srg) { + if (idle) { /* Start frame sync */ w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); @@ -1645,7 +1645,7 @@ static const struct attribute_group sidetone_attr_group = { .attrs = (struct attribute **)sidetone_attrs, }; -static int __devinit omap_st_add(struct omap_mcbsp *mcbsp) +int __devinit omap_st_add(struct omap_mcbsp *mcbsp) { struct omap_mcbsp_platform_data *pdata = mcbsp->pdata; struct omap_mcbsp_st_data *st_data; diff --git a/trunk/arch/arm/plat-omap/omap_device.c b/trunk/arch/arm/plat-omap/omap_device.c index abe933cd8f09..d2b160942ccc 100644 --- a/trunk/arch/arm/plat-omap/omap_device.c +++ b/trunk/arch/arm/plat-omap/omap_device.c @@ -82,7 +82,6 @@ #include #include #include -#include #include #include @@ -91,6 +90,12 @@ #define USE_WAKEUP_LAT 0 #define IGNORE_WAKEUP_LAT 1 +/* + * OMAP_DEVICE_MAGIC: used to determine whether a struct omap_device + * obtained via container_of() is in fact a struct omap_device + */ +#define OMAP_DEVICE_MAGIC 0xf00dcafe + /* Private functions */ /** @@ -238,44 +243,6 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev) return container_of(pdev, struct omap_device, pdev); } -/** - * _add_optional_clock_alias - Add clock alias for hwmod optional clocks - * @od: struct omap_device *od - * - * For every optional clock present per hwmod per omap_device, this function - * adds an entry in the clocks list of the form - * if an entry is already present in it with the form - * - * The function is called from inside omap_device_build_ss(), after - * omap_device_register. - * - * This allows drivers to get a pointer to its optional clocks based on its role - * by calling clk_get(, ). - * - * No return value. - */ -static void _add_optional_clock_alias(struct omap_device *od, - struct omap_hwmod *oh) -{ - int i; - - for (i = 0; i < oh->opt_clks_cnt; i++) { - struct omap_hwmod_opt_clk *oc; - int r; - - oc = &oh->opt_clks[i]; - - if (!oc->_clk) - continue; - - r = clk_add_alias(oc->role, dev_name(&od->pdev.dev), - (char *)oc->clk, &od->pdev.dev); - if (r) - pr_err("omap_device: %s: clk_add_alias for %s failed\n", - dev_name(&od->pdev.dev), oc->role); - } -} - /* Public functions for use by core code */ @@ -290,11 +257,12 @@ static void _add_optional_clock_alias(struct omap_device *od, */ int omap_device_count_resources(struct omap_device *od) { + struct omap_hwmod *oh; int c = 0; int i; - for (i = 0; i < od->hwmods_cnt; i++) - c += omap_hwmod_count_resources(od->hwmods[i]); + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + c += omap_hwmod_count_resources(oh); pr_debug("omap_device: %s: counted %d total resources across %d " "hwmods\n", od->pdev.name, c, od->hwmods_cnt); @@ -321,11 +289,12 @@ int omap_device_count_resources(struct omap_device *od) */ int omap_device_fill_resources(struct omap_device *od, struct resource *res) { + struct omap_hwmod *oh; int c = 0; int i, r; - for (i = 0; i < od->hwmods_cnt; i++) { - r = omap_hwmod_fill_resources(od->hwmods[i], res); + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) { + r = omap_hwmod_fill_resources(oh, res); res += r; c += r; } @@ -445,15 +414,15 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, od->pm_lats = pm_lats; od->pm_lats_cnt = pm_lats_cnt; + od->magic = OMAP_DEVICE_MAGIC; + if (is_early_device) ret = omap_early_device_register(od); else ret = omap_device_register(od); - for (i = 0; i < oh_cnt; i++) { + for (i = 0; i < oh_cnt; i++) hwmods[i]->od = od; - _add_optional_clock_alias(od, hwmods[i]); - } if (ret) goto odbs_exit4; @@ -504,7 +473,6 @@ int omap_device_register(struct omap_device *od) { pr_debug("omap_device: %s: registering\n", od->pdev.name); - od->pdev.dev.parent = &omap_device_parent; return platform_device_register(&od->pdev); } @@ -598,6 +566,7 @@ int omap_device_shutdown(struct platform_device *pdev) { int ret, i; struct omap_device *od; + struct omap_hwmod *oh; od = _find_by_pdev(pdev); @@ -610,8 +579,8 @@ int omap_device_shutdown(struct platform_device *pdev) ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT); - for (i = 0; i < od->hwmods_cnt; i++) - omap_hwmod_shutdown(od->hwmods[i]); + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + omap_hwmod_shutdown(oh); od->_state = OMAP_DEVICE_STATE_SHUTDOWN; @@ -657,6 +626,18 @@ int omap_device_align_pm_lat(struct platform_device *pdev, return ret; } +/** + * omap_device_is_valid - Check if pointer is a valid omap_device + * @od: struct omap_device * + * + * Return whether struct omap_device pointer @od points to a valid + * omap_device. + */ +bool omap_device_is_valid(struct omap_device *od) +{ + return (od && od->magic == OMAP_DEVICE_MAGIC); +} + /** * omap_device_get_pwrdm - return the powerdomain * associated with @od * @od: struct omap_device * @@ -711,10 +692,11 @@ void __iomem *omap_device_get_rt_va(struct omap_device *od) */ int omap_device_enable_hwmods(struct omap_device *od) { + struct omap_hwmod *oh; int i; - for (i = 0; i < od->hwmods_cnt; i++) - omap_hwmod_enable(od->hwmods[i]); + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + omap_hwmod_enable(oh); /* XXX pass along return value here? */ return 0; @@ -728,10 +710,11 @@ int omap_device_enable_hwmods(struct omap_device *od) */ int omap_device_idle_hwmods(struct omap_device *od) { + struct omap_hwmod *oh; int i; - for (i = 0; i < od->hwmods_cnt; i++) - omap_hwmod_idle(od->hwmods[i]); + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + omap_hwmod_idle(oh); /* XXX pass along return value here? */ return 0; @@ -746,10 +729,11 @@ int omap_device_idle_hwmods(struct omap_device *od) */ int omap_device_disable_clocks(struct omap_device *od) { + struct omap_hwmod *oh; int i; - for (i = 0; i < od->hwmods_cnt; i++) - omap_hwmod_disable_clocks(od->hwmods[i]); + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + omap_hwmod_disable_clocks(oh); /* XXX pass along return value here? */ return 0; @@ -764,22 +748,12 @@ int omap_device_disable_clocks(struct omap_device *od) */ int omap_device_enable_clocks(struct omap_device *od) { + struct omap_hwmod *oh; int i; - for (i = 0; i < od->hwmods_cnt; i++) - omap_hwmod_enable_clocks(od->hwmods[i]); + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + omap_hwmod_enable_clocks(oh); /* XXX pass along return value here? */ return 0; } - -struct device omap_device_parent = { - .init_name = "omap", - .parent = &platform_bus, -}; - -static int __init omap_device_init(void) -{ - return device_register(&omap_device_parent); -} -core_initcall(omap_device_init); diff --git a/trunk/arch/arm/plat-omap/sram.c b/trunk/arch/arm/plat-omap/sram.c index e2c8eebe6b3a..10b3b4c63372 100644 --- a/trunk/arch/arm/plat-omap/sram.c +++ b/trunk/arch/arm/plat-omap/sram.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include @@ -31,8 +30,8 @@ #include #include -#include "sram.h" -#include "fb.h" +#include + #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) # include "../mach-omap2/prm.h" # include "../mach-omap2/cm.h" @@ -54,7 +53,7 @@ #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) #define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) -#if defined(CONFIG_ARCH_OMAP2PLUS) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) #define SRAM_BOOTLOADER_SZ 0x00 #else #define SRAM_BOOTLOADER_SZ 0x80 @@ -69,6 +68,7 @@ #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858) #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880) #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048) +#define OMAP34XX_VA_CONTROL_STAT OMAP2_L4_IO_ADDRESS(0x480022F0) #define GP_DEVICE 0x300 @@ -79,6 +79,12 @@ static unsigned long omap_sram_base; static unsigned long omap_sram_size; static unsigned long omap_sram_ceil; +extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart, + unsigned long sram_vstart, + unsigned long sram_size, + unsigned long pstart_avail, + unsigned long size_avail); + /* * Depending on the target RAMFS firewall setup, the public usable amount of * SRAM varies. The default accessible size for all device types is 2k. A GP @@ -87,7 +93,16 @@ static unsigned long omap_sram_ceil; */ static int is_sram_locked(void) { - if (OMAP2_DEVICE_TYPE_GP == omap_type()) { + int type = 0; + + if (cpu_is_omap44xx()) + /* Not yet supported */ + return 0; + + if (cpu_is_omap242x()) + type = omap_rev() & OMAP2_DEVICETYPE_MASK; + + if (type == GP_DEVICE) { /* RAMFW: R/W access to all initiators for all qualifier sets */ if (cpu_is_omap242x()) { __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ @@ -112,7 +127,7 @@ static int is_sram_locked(void) * to secure SRAM will hang the system. Also the SRAM is not * yet mapped at this point. */ -static void __init omap_detect_sram(void) +void __init omap_detect_sram(void) { unsigned long reserved; @@ -198,7 +213,7 @@ static struct map_desc omap_sram_io_desc[] __initdata = { /* * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early. */ -static void __init omap_map_sram(void) +void __init omap_map_sram(void) { unsigned long base; @@ -315,7 +330,7 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass) #endif #ifdef CONFIG_ARCH_OMAP2420 -static int __init omap242x_sram_init(void) +int __init omap242x_sram_init(void) { _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init, omap242x_sram_ddr_init_sz); @@ -336,7 +351,7 @@ static inline int omap242x_sram_init(void) #endif #ifdef CONFIG_ARCH_OMAP2430 -static int __init omap243x_sram_init(void) +int __init omap243x_sram_init(void) { _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init, omap243x_sram_ddr_init_sz); @@ -392,7 +407,7 @@ void omap3_sram_restore_context(void) } #endif /* CONFIG_PM */ -static int __init omap34xx_sram_init(void) +int __init omap34xx_sram_init(void) { _omap3_sram_configure_core_dpll = omap_sram_push(omap3_sram_configure_core_dpll, @@ -408,7 +423,7 @@ static inline int omap34xx_sram_init(void) #endif #ifdef CONFIG_ARCH_OMAP4 -static int __init omap44xx_sram_init(void) +int __init omap44xx_sram_init(void) { printk(KERN_ERR "FIXME: %s not implemented\n", __func__); diff --git a/trunk/arch/arm/plat-omap/sram.h b/trunk/arch/arm/plat-omap/sram.h deleted file mode 100644 index 29b43ef97f20..000000000000 --- a/trunk/arch/arm/plat-omap/sram.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __PLAT_OMAP_SRAM_H__ -#define __PLAT_OMAP_SRAM_H__ - -extern int __init omap_sram_init(void); - -#endif /* __PLAT_OMAP_SRAM_H__ */ diff --git a/trunk/arch/mn10300/kernel/vmlinux.lds.S b/trunk/arch/mn10300/kernel/vmlinux.lds.S index febbeee7f2f5..10549dcfb610 100644 --- a/trunk/arch/mn10300/kernel/vmlinux.lds.S +++ b/trunk/arch/mn10300/kernel/vmlinux.lds.S @@ -70,7 +70,7 @@ SECTIONS .exit.text : { EXIT_TEXT; } .exit.data : { EXIT_DATA; } - PERCPU(PAGE_SIZE) + PERCPU(32) . = ALIGN(PAGE_SIZE); __init_end = .; /* freed after init ends here */ diff --git a/trunk/drivers/hwmon/coretemp.c b/trunk/drivers/hwmon/coretemp.c index a23b17a78ace..f34fe836b5c9 100644 --- a/trunk/drivers/hwmon/coretemp.c +++ b/trunk/drivers/hwmon/coretemp.c @@ -490,7 +490,7 @@ static int __cpuinit coretemp_device_add(unsigned int cpu) return err; } -static void coretemp_device_remove(unsigned int cpu) +static void __cpuinit coretemp_device_remove(unsigned int cpu) { struct pdev_entry *p; unsigned int i; diff --git a/trunk/drivers/hwmon/pkgtemp.c b/trunk/drivers/hwmon/pkgtemp.c index f11903936c8b..db5352c20946 100644 --- a/trunk/drivers/hwmon/pkgtemp.c +++ b/trunk/drivers/hwmon/pkgtemp.c @@ -340,7 +340,7 @@ static int __cpuinit pkgtemp_device_add(unsigned int cpu) } #ifdef CONFIG_HOTPLUG_CPU -static void pkgtemp_device_remove(unsigned int cpu) +static void __cpuinit pkgtemp_device_remove(unsigned int cpu) { struct pdev_entry *p; unsigned int i; diff --git a/trunk/drivers/hwmon/via-cputemp.c b/trunk/drivers/hwmon/via-cputemp.c index ffb793af680b..497bd231e241 100644 --- a/trunk/drivers/hwmon/via-cputemp.c +++ b/trunk/drivers/hwmon/via-cputemp.c @@ -238,7 +238,7 @@ static int __cpuinit via_cputemp_device_add(unsigned int cpu) } #ifdef CONFIG_HOTPLUG_CPU -static void via_cputemp_device_remove(unsigned int cpu) +static void __cpuinit via_cputemp_device_remove(unsigned int cpu) { struct pdev_entry *p, *n; mutex_lock(&pdev_list_mutex); diff --git a/trunk/drivers/mmc/host/omap_hsmmc.c b/trunk/drivers/mmc/host/omap_hsmmc.c index 4693e62145a6..4526d2791f29 100644 --- a/trunk/drivers/mmc/host/omap_hsmmc.c +++ b/trunk/drivers/mmc/host/omap_hsmmc.c @@ -364,7 +364,6 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) { struct regulator *reg; int ret = 0; - int ocr_value = 0; switch (host->id) { case OMAP_MMC1_DEVID: @@ -397,17 +396,6 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) } } else { host->vcc = reg; - ocr_value = mmc_regulator_get_ocrmask(reg); - if (!mmc_slot(host).ocr_mask) { - mmc_slot(host).ocr_mask = ocr_value; - } else { - if (!(mmc_slot(host).ocr_mask & ocr_value)) { - pr_err("MMC%d ocrmask %x is not supported\n", - host->id, mmc_slot(host).ocr_mask); - mmc_slot(host).ocr_mask = 0; - return -EINVAL; - } - } mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg); /* Allow an aux regulator */ @@ -994,17 +982,6 @@ static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, OMAP_HSMMC_WRITE(host->base, SYSCTL, OMAP_HSMMC_READ(host->base, SYSCTL) | bit); - /* - * OMAP4 ES2 and greater has an updated reset logic. - * Monitor a 0->1 transition first - */ - if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { - while ((!(OMAP_HSMMC_READ(host, SYSCTL) & bit)) - && (i++ < limit)) - cpu_relax(); - } - i = 0; - while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && (i++ < limit)) cpu_relax(); @@ -2026,8 +2003,6 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) if (res == NULL || irq < 0) return -ENXIO; - res->start += pdata->reg_offset; - res->end += pdata->reg_offset; res = request_mem_region(res->start, res->end - res->start + 1, pdev->name); if (res == NULL) @@ -2141,9 +2116,23 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; - mmc->caps |= mmc_slot(host).caps; - if (mmc->caps & MMC_CAP_8_BIT_DATA) + switch (mmc_slot(host).wires) { + case 8: + mmc->caps |= MMC_CAP_8_BIT_DATA; + /* Fall through */ + case 4: mmc->caps |= MMC_CAP_4_BIT_DATA; + break; + case 1: + /* Nothing to crib here */ + case 0: + /* Assuming nothing was given by board, Core use's 1-Bit */ + break; + default: + /* Completely unexpected.. Core goes with 1-Bit Width */ + dev_crit(mmc_dev(host->mmc), "Invalid width %d\n used!" + "using 1 instead\n", mmc_slot(host).wires); + } if (mmc_slot(host).nonremovable) mmc->caps |= MMC_CAP_NONREMOVABLE; diff --git a/trunk/drivers/serial/Kconfig b/trunk/drivers/serial/Kconfig index aff9dcd051c6..927816484397 100644 --- a/trunk/drivers/serial/Kconfig +++ b/trunk/drivers/serial/Kconfig @@ -1410,33 +1410,6 @@ config SERIAL_OF_PLATFORM Currently, only 8250 compatible ports are supported, but others can easily be added. -config SERIAL_OMAP - tristate "OMAP serial port support" - depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4 - select SERIAL_CORE - help - If you have a machine based on an Texas Instruments OMAP CPU you - can enable its onboard serial ports by enabling this option. - - By enabling this option you take advantage of dma feature available - with the omap-serial driver. DMA support can be enabled from platform - data. - -config SERIAL_OMAP_CONSOLE - bool "Console on OMAP serial port" - depends on SERIAL_OMAP - select SERIAL_CORE_CONSOLE - help - Select this option if you would like to use omap serial port as - console. - - Even if you say Y here, the currently visible virtual console - (/dev/tty0) will still be used as the system console by default, but - you can alter that using a kernel command line option such as - "console=ttyOx". (Try "man bootparam" or see the documentation of - your boot loader about how to pass options to the kernel at - boot time.) - config SERIAL_OF_PLATFORM_NWPSERIAL tristate "NWP serial port driver" depends on PPC_OF && PPC_DCR diff --git a/trunk/drivers/serial/Makefile b/trunk/drivers/serial/Makefile index c5705765454f..1ca4fd599ffe 100644 --- a/trunk/drivers/serial/Makefile +++ b/trunk/drivers/serial/Makefile @@ -88,4 +88,3 @@ obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o obj-$(CONFIG_SERIAL_ALTERA_UART) += altera_uart.o obj-$(CONFIG_SERIAL_MRST_MAX3110) += mrst_max3110.o obj-$(CONFIG_SERIAL_MFD_HSU) += mfd.o -obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o diff --git a/trunk/drivers/serial/omap-serial.c b/trunk/drivers/serial/omap-serial.c deleted file mode 100644 index 14365f72b664..000000000000 --- a/trunk/drivers/serial/omap-serial.c +++ /dev/null @@ -1,1333 +0,0 @@ -/* - * Driver for OMAP-UART controller. - * Based on drivers/serial/8250.c - * - * Copyright (C) 2010 Texas Instruments. - * - * Authors: - * Govindraj R - * Thara Gopinath - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * Note: This driver is made seperate from 8250 driver as we cannot - * over load 8250 driver with omap platform specific configuration for - * features like DMA, it makes easier to implement features like DMA and - * hardware flow control and software flow control configuration with - * this driver as required for the omap-platform. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; - -/* Forward declaration of functions */ -static void uart_tx_dma_callback(int lch, u16 ch_status, void *data); -static void serial_omap_rx_timeout(unsigned long uart_no); -static int serial_omap_start_rxdma(struct uart_omap_port *up); - -static inline unsigned int serial_in(struct uart_omap_port *up, int offset) -{ - offset <<= up->port.regshift; - return readw(up->port.membase + offset); -} - -static inline void serial_out(struct uart_omap_port *up, int offset, int value) -{ - offset <<= up->port.regshift; - writew(value, up->port.membase + offset); -} - -static inline void serial_omap_clear_fifos(struct uart_omap_port *up) -{ - serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); - serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | - UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); - serial_out(up, UART_FCR, 0); -} - -/* - * serial_omap_get_divisor - calculate divisor value - * @port: uart port info - * @baud: baudrate for which divisor needs to be calculated. - * - * We have written our own function to get the divisor so as to support - * 13x mode. 3Mbps Baudrate as an different divisor. - * Reference OMAP TRM Chapter 17: - * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates - * referring to oversampling - divisor value - * baudrate 460,800 to 3,686,400 all have divisor 13 - * except 3,000,000 which has divisor value 16 - */ -static unsigned int -serial_omap_get_divisor(struct uart_port *port, unsigned int baud) -{ - unsigned int divisor; - - if (baud > OMAP_MODE13X_SPEED && baud != 3000000) - divisor = 13; - else - divisor = 16; - return port->uartclk/(baud * divisor); -} - -static void serial_omap_stop_rxdma(struct uart_omap_port *up) -{ - if (up->uart_dma.rx_dma_used) { - del_timer(&up->uart_dma.rx_timer); - omap_stop_dma(up->uart_dma.rx_dma_channel); - omap_free_dma(up->uart_dma.rx_dma_channel); - up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; - up->uart_dma.rx_dma_used = false; - } -} - -static void serial_omap_enable_ms(struct uart_port *port) -{ - struct uart_omap_port *up = (struct uart_omap_port *)port; - - dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->pdev->id); - up->ier |= UART_IER_MSI; - serial_out(up, UART_IER, up->ier); -} - -static void serial_omap_stop_tx(struct uart_port *port) -{ - struct uart_omap_port *up = (struct uart_omap_port *)port; - - if (up->use_dma && - up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) { - /* - * Check if dma is still active. If yes do nothing, - * return. Else stop dma - */ - if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel)) - return; - omap_stop_dma(up->uart_dma.tx_dma_channel); - omap_free_dma(up->uart_dma.tx_dma_channel); - up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; - } - - if (up->ier & UART_IER_THRI) { - up->ier &= ~UART_IER_THRI; - serial_out(up, UART_IER, up->ier); - } -} - -static void serial_omap_stop_rx(struct uart_port *port) -{ - struct uart_omap_port *up = (struct uart_omap_port *)port; - - if (up->use_dma) - serial_omap_stop_rxdma(up); - up->ier &= ~UART_IER_RLSI; - up->port.read_status_mask &= ~UART_LSR_DR; - serial_out(up, UART_IER, up->ier); -} - -static inline void receive_chars(struct uart_omap_port *up, int *status) -{ - struct tty_struct *tty = up->port.state->port.tty; - unsigned int flag; - unsigned char ch, lsr = *status; - int max_count = 256; - - do { - if (likely(lsr & UART_LSR_DR)) - ch = serial_in(up, UART_RX); - flag = TTY_NORMAL; - up->port.icount.rx++; - - if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { - /* - * For statistics only - */ - if (lsr & UART_LSR_BI) { - lsr &= ~(UART_LSR_FE | UART_LSR_PE); - up->port.icount.brk++; - /* - * We do the SysRQ and SAK checking - * here because otherwise the break - * may get masked by ignore_status_mask - * or read_status_mask. - */ - if (uart_handle_break(&up->port)) - goto ignore_char; - } else if (lsr & UART_LSR_PE) { - up->port.icount.parity++; - } else if (lsr & UART_LSR_FE) { - up->port.icount.frame++; - } - - if (lsr & UART_LSR_OE) - up->port.icount.overrun++; - - /* - * Mask off conditions which should be ignored. - */ - lsr &= up->port.read_status_mask; - -#ifdef CONFIG_SERIAL_OMAP_CONSOLE - if (up->port.line == up->port.cons->index) { - /* Recover the break flag from console xmit */ - lsr |= up->lsr_break_flag; - up->lsr_break_flag = 0; - } -#endif - if (lsr & UART_LSR_BI) - flag = TTY_BREAK; - else if (lsr & UART_LSR_PE) - flag = TTY_PARITY; - else if (lsr & UART_LSR_FE) - flag = TTY_FRAME; - } - - if (uart_handle_sysrq_char(&up->port, ch)) - goto ignore_char; - uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); -ignore_char: - lsr = serial_in(up, UART_LSR); - } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0)); - spin_unlock(&up->port.lock); - tty_flip_buffer_push(tty); - spin_lock(&up->port.lock); -} - -static void transmit_chars(struct uart_omap_port *up) -{ - struct circ_buf *xmit = &up->port.state->xmit; - int count; - - if (up->port.x_char) { - serial_out(up, UART_TX, up->port.x_char); - up->port.icount.tx++; - up->port.x_char = 0; - return; - } - if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { - serial_omap_stop_tx(&up->port); - return; - } - count = up->port.fifosize / 4; - do { - serial_out(up, UART_TX, xmit->buf[xmit->tail]); - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); - up->port.icount.tx++; - if (uart_circ_empty(xmit)) - break; - } while (--count > 0); - - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) - uart_write_wakeup(&up->port); - - if (uart_circ_empty(xmit)) - serial_omap_stop_tx(&up->port); -} - -static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) -{ - if (!(up->ier & UART_IER_THRI)) { - up->ier |= UART_IER_THRI; - serial_out(up, UART_IER, up->ier); - } -} - -static void serial_omap_start_tx(struct uart_port *port) -{ - struct uart_omap_port *up = (struct uart_omap_port *)port; - struct circ_buf *xmit; - unsigned int start; - int ret = 0; - - if (!up->use_dma) { - serial_omap_enable_ier_thri(up); - return; - } - - if (up->uart_dma.tx_dma_used) - return; - - xmit = &up->port.state->xmit; - - if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) { - ret = omap_request_dma(up->uart_dma.uart_dma_tx, - "UART Tx DMA", - (void *)uart_tx_dma_callback, up, - &(up->uart_dma.tx_dma_channel)); - - if (ret < 0) { - serial_omap_enable_ier_thri(up); - return; - } - } - spin_lock(&(up->uart_dma.tx_lock)); - up->uart_dma.tx_dma_used = true; - spin_unlock(&(up->uart_dma.tx_lock)); - - start = up->uart_dma.tx_buf_dma_phys + - (xmit->tail & (UART_XMIT_SIZE - 1)); - - up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit); - /* - * It is a circular buffer. See if the buffer has wounded back. - * If yes it will have to be transferred in two separate dma - * transfers - */ - if (start + up->uart_dma.tx_buf_size >= - up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - up->uart_dma.tx_buf_size = - (up->uart_dma.tx_buf_dma_phys + - UART_XMIT_SIZE) - start; - - omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0, - OMAP_DMA_AMODE_CONSTANT, - up->uart_dma.uart_base, 0, 0); - omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0, - OMAP_DMA_AMODE_POST_INC, start, 0, 0); - omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel, - OMAP_DMA_DATA_TYPE_S8, - up->uart_dma.tx_buf_size, 1, - OMAP_DMA_SYNC_ELEMENT, - up->uart_dma.uart_dma_tx, 0); - /* FIXME: Cache maintenance needed here? */ - omap_start_dma(up->uart_dma.tx_dma_channel); -} - -static unsigned int check_modem_status(struct uart_omap_port *up) -{ - unsigned int status; - - status = serial_in(up, UART_MSR); - status |= up->msr_saved_flags; - up->msr_saved_flags = 0; - if ((status & UART_MSR_ANY_DELTA) == 0) - return status; - - if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && - up->port.state != NULL) { - if (status & UART_MSR_TERI) - up->port.icount.rng++; - if (status & UART_MSR_DDSR) - up->port.icount.dsr++; - if (status & UART_MSR_DDCD) - uart_handle_dcd_change - (&up->port, status & UART_MSR_DCD); - if (status & UART_MSR_DCTS) - uart_handle_cts_change - (&up->port, status & UART_MSR_CTS); - wake_up_interruptible(&up->port.state->port.delta_msr_wait); - } - - return status; -} - -/** - * serial_omap_irq() - This handles the interrupt from one port - * @irq: uart port irq number - * @dev_id: uart port info - */ -static inline irqreturn_t serial_omap_irq(int irq, void *dev_id) -{ - struct uart_omap_port *up = dev_id; - unsigned int iir, lsr; - unsigned long flags; - - iir = serial_in(up, UART_IIR); - if (iir & UART_IIR_NO_INT) - return IRQ_NONE; - - spin_lock_irqsave(&up->port.lock, flags); - lsr = serial_in(up, UART_LSR); - if (iir & UART_IIR_RLSI) { - if (!up->use_dma) { - if (lsr & UART_LSR_DR) - receive_chars(up, &lsr); - } else { - up->ier &= ~(UART_IER_RDI | UART_IER_RLSI); - serial_out(up, UART_IER, up->ier); - if ((serial_omap_start_rxdma(up) != 0) && - (lsr & UART_LSR_DR)) - receive_chars(up, &lsr); - } - } - - check_modem_status(up); - if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI)) - transmit_chars(up); - - spin_unlock_irqrestore(&up->port.lock, flags); - up->port_activity = jiffies; - return IRQ_HANDLED; -} - -static unsigned int serial_omap_tx_empty(struct uart_port *port) -{ - struct uart_omap_port *up = (struct uart_omap_port *)port; - unsigned long flags = 0; - unsigned int ret = 0; - - dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->pdev->id); - spin_lock_irqsave(&up->port.lock, flags); - ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; - spin_unlock_irqrestore(&up->port.lock, flags); - - return ret; -} - -static unsigned int serial_omap_get_mctrl(struct uart_port *port) -{ - struct uart_omap_port *up = (struct uart_omap_port *)port; - unsigned char status; - unsigned int ret = 0; - - status = check_modem_status(up); - dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->pdev->id); - - if (status & UART_MSR_DCD) - ret |= TIOCM_CAR; - if (status & UART_MSR_RI) - ret |= TIOCM_RNG; - if (status & UART_MSR_DSR) - ret |= TIOCM_DSR; - if (status & UART_MSR_CTS) - ret |= TIOCM_CTS; - return ret; -} - -static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) -{ - struct uart_omap_port *up = (struct uart_omap_port *)port; - unsigned char mcr = 0; - - dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->pdev->id); - if (mctrl & TIOCM_RTS) - mcr |= UART_MCR_RTS; - if (mctrl & TIOCM_DTR) - mcr |= UART_MCR_DTR; - if (mctrl & TIOCM_OUT1) - mcr |= UART_MCR_OUT1; - if (mctrl & TIOCM_OUT2) - mcr |= UART_MCR_OUT2; - if (mctrl & TIOCM_LOOP) - mcr |= UART_MCR_LOOP; - - mcr |= up->mcr; - serial_out(up, UART_MCR, mcr); -} - -static void serial_omap_break_ctl(struct uart_port *port, int break_state) -{ - struct uart_omap_port *up = (struct uart_omap_port *)port; - unsigned long flags = 0; - - dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->pdev->id); - spin_lock_irqsave(&up->port.lock, flags); - if (break_state == -1) - up->lcr |= UART_LCR_SBC; - else - up->lcr &= ~UART_LCR_SBC; - serial_out(up, UART_LCR, up->lcr); - spin_unlock_irqrestore(&up->port.lock, flags); -} - -static int serial_omap_startup(struct uart_port *port) -{ - struct uart_omap_port *up = (struct uart_omap_port *)port; - unsigned long flags = 0; - int retval; - - /* - * Allocate the IRQ - */ - retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, - up->name, up); - if (retval) - return retval; - - dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->pdev->id); - - /* - * Clear the FIFO buffers and disable them. - * (they will be reenabled in set_termios()) - */ - serial_omap_clear_fifos(up); - /* For Hardware flow control */ - serial_out(up, UART_MCR, UART_MCR_RTS); - - /* - * Clear the interrupt registers. - */ - (void) serial_in(up, UART_LSR); - if (serial_in(up, UART_LSR) & UART_LSR_DR) - (void) serial_in(up, UART_RX); - (void) serial_in(up, UART_IIR); - (void) serial_in(up, UART_MSR); - - /* - * Now, initialize the UART - */ - serial_out(up, UART_LCR, UART_LCR_WLEN8); - spin_lock_irqsave(&up->port.lock, flags); - /* - * Most PC uarts need OUT2 raised to enable interrupts. - */ - up->port.mctrl |= TIOCM_OUT2; - serial_omap_set_mctrl(&up->port, up->port.mctrl); - spin_unlock_irqrestore(&up->port.lock, flags); - - up->msr_saved_flags = 0; - if (up->use_dma) { - free_page((unsigned long)up->port.state->xmit.buf); - up->port.state->xmit.buf = dma_alloc_coherent(NULL, - UART_XMIT_SIZE, - (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys), - 0); - init_timer(&(up->uart_dma.rx_timer)); - up->uart_dma.rx_timer.function = serial_omap_rx_timeout; - up->uart_dma.rx_timer.data = up->pdev->id; - /* Currently the buffer size is 4KB. Can increase it */ - up->uart_dma.rx_buf = dma_alloc_coherent(NULL, - up->uart_dma.rx_buf_size, - (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0); - } - /* - * Finally, enable interrupts. Note: Modem status interrupts - * are set via set_termios(), which will be occurring imminently - * anyway, so we don't enable them here. - */ - up->ier = UART_IER_RLSI | UART_IER_RDI; - serial_out(up, UART_IER, up->ier); - - up->port_activity = jiffies; - return 0; -} - -static void serial_omap_shutdown(struct uart_port *port) -{ - struct uart_omap_port *up = (struct uart_omap_port *)port; - unsigned long flags = 0; - - dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->pdev->id); - /* - * Disable interrupts from this port - */ - up->ier = 0; - serial_out(up, UART_IER, 0); - - spin_lock_irqsave(&up->port.lock, flags); - up->port.mctrl &= ~TIOCM_OUT2; - serial_omap_set_mctrl(&up->port, up->port.mctrl); - spin_unlock_irqrestore(&up->port.lock, flags); - - /* - * Disable break condition and FIFOs - */ - serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); - serial_omap_clear_fifos(up); - - /* - * Read data port to reset things, and then free the irq - */ - if (serial_in(up, UART_LSR) & UART_LSR_DR) - (void) serial_in(up, UART_RX); - if (up->use_dma) { - dma_free_coherent(up->port.dev, - UART_XMIT_SIZE, up->port.state->xmit.buf, - up->uart_dma.tx_buf_dma_phys); - up->port.state->xmit.buf = NULL; - serial_omap_stop_rx(port); - dma_free_coherent(up->port.dev, - up->uart_dma.rx_buf_size, up->uart_dma.rx_buf, - up->uart_dma.rx_buf_dma_phys); - up->uart_dma.rx_buf = NULL; - } - free_irq(up->port.irq, up); -} - -static inline void -serial_omap_configure_xonxoff - (struct uart_omap_port *up, struct ktermios *termios) -{ - unsigned char efr = 0; - - up->lcr = serial_in(up, UART_LCR); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); - up->efr = serial_in(up, UART_EFR); - serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB); - - serial_out(up, UART_XON1, termios->c_cc[VSTART]); - serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); - - /* clear SW control mode bits */ - efr = up->efr; - efr &= OMAP_UART_SW_CLR; - - /* - * IXON Flag: - * Enable XON/XOFF flow control on output. - * Transmit XON1, XOFF1 - */ - if (termios->c_iflag & IXON) - efr |= OMAP_UART_SW_TX; - - /* - * IXOFF Flag: - * Enable XON/XOFF flow control on input. - * Receiver compares XON1, XOFF1. - */ - if (termios->c_iflag & IXOFF) - efr |= OMAP_UART_SW_RX; - - serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); - serial_out(up, UART_LCR, UART_LCR_DLAB); - - up->mcr = serial_in(up, UART_MCR); - - /* - * IXANY Flag: - * Enable any character to restart output. - * Operation resumes after receiving any - * character after recognition of the XOFF character - */ - if (termios->c_iflag & IXANY) - up->mcr |= UART_MCR_XONANY; - - serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); - serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); - /* Enable special char function UARTi.EFR_REG[5] and - * load the new software flow control mode IXON or IXOFF - * and restore the UARTi.EFR_REG[4] ENHANCED_EN value. - */ - serial_out(up, UART_EFR, efr | UART_EFR_SCD); - serial_out(up, UART_LCR, UART_LCR_DLAB); - - serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR); - serial_out(up, UART_LCR, up->lcr); -} - -static void -serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, - struct ktermios *old) -{ - struct uart_omap_port *up = (struct uart_omap_port *)port; - unsigned char cval = 0; - unsigned char efr = 0; - unsigned long flags = 0; - unsigned int baud, quot; - - switch (termios->c_cflag & CSIZE) { - case CS5: - cval = UART_LCR_WLEN5; - break; - case CS6: - cval = UART_LCR_WLEN6; - break; - case CS7: - cval = UART_LCR_WLEN7; - break; - default: - case CS8: - cval = UART_LCR_WLEN8; - break; - } - - if (termios->c_cflag & CSTOPB) - cval |= UART_LCR_STOP; - if (termios->c_cflag & PARENB) - cval |= UART_LCR_PARITY; - if (!(termios->c_cflag & PARODD)) - cval |= UART_LCR_EPAR; - - /* - * Ask the core to calculate the divisor for us. - */ - - baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); - quot = serial_omap_get_divisor(port, baud); - - up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | - UART_FCR_ENABLE_FIFO; - if (up->use_dma) - up->fcr |= UART_FCR_DMA_SELECT; - - /* - * Ok, we're now changing the port state. Do it with - * interrupts disabled. - */ - spin_lock_irqsave(&up->port.lock, flags); - - /* - * Update the per-port timeout. - */ - uart_update_timeout(port, termios->c_cflag, baud); - - up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; - if (termios->c_iflag & INPCK) - up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; - if (termios->c_iflag & (BRKINT | PARMRK)) - up->port.read_status_mask |= UART_LSR_BI; - - /* - * Characters to ignore - */ - up->port.ignore_status_mask = 0; - if (termios->c_iflag & IGNPAR) - up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; - if (termios->c_iflag & IGNBRK) { - up->port.ignore_status_mask |= UART_LSR_BI; - /* - * If we're ignoring parity and break indicators, - * ignore overruns too (for real raw support). - */ - if (termios->c_iflag & IGNPAR) - up->port.ignore_status_mask |= UART_LSR_OE; - } - - /* - * ignore all characters if CREAD is not set - */ - if ((termios->c_cflag & CREAD) == 0) - up->port.ignore_status_mask |= UART_LSR_DR; - - /* - * Modem status interrupts - */ - up->ier &= ~UART_IER_MSI; - if (UART_ENABLE_MS(&up->port, termios->c_cflag)) - up->ier |= UART_IER_MSI; - serial_out(up, UART_IER, up->ier); - serial_out(up, UART_LCR, cval); /* reset DLAB */ - - /* FIFOs and DMA Settings */ - - /* FCR can be changed only when the - * baud clock is not running - * DLL_REG and DLH_REG set to 0. - */ - serial_out(up, UART_LCR, UART_LCR_DLAB); - serial_out(up, UART_DLL, 0); - serial_out(up, UART_DLM, 0); - serial_out(up, UART_LCR, 0); - - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); - - up->efr = serial_in(up, UART_EFR); - serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); - - serial_out(up, UART_LCR, UART_LCR_DLAB); - up->mcr = serial_in(up, UART_MCR); - serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); - /* FIFO ENABLE, DMA MODE */ - serial_out(up, UART_FCR, up->fcr); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); - - if (up->use_dma) { - serial_out(up, UART_TI752_TLR, 0); - serial_out(up, UART_OMAP_SCR, - (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8)); - } - - serial_out(up, UART_EFR, up->efr); - serial_out(up, UART_LCR, UART_LCR_DLAB); - serial_out(up, UART_MCR, up->mcr); - - /* Protocol, Baud Rate, and Interrupt Settings */ - - serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_DISABLE); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); - - up->efr = serial_in(up, UART_EFR); - serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); - - serial_out(up, UART_LCR, 0); - serial_out(up, UART_IER, 0); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); - - serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ - serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ - - serial_out(up, UART_LCR, 0); - serial_out(up, UART_IER, up->ier); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); - - serial_out(up, UART_EFR, up->efr); - serial_out(up, UART_LCR, cval); - - if (baud > 230400 && baud != 3000000) - serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_MODE13X); - else - serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_MODE16X); - - /* Hardware Flow Control Configuration */ - - if (termios->c_cflag & CRTSCTS) { - efr |= (UART_EFR_CTS | UART_EFR_RTS); - serial_out(up, UART_LCR, UART_LCR_DLAB); - - up->mcr = serial_in(up, UART_MCR); - serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); - - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); - up->efr = serial_in(up, UART_EFR); - serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); - - serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); - serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */ - serial_out(up, UART_LCR, UART_LCR_DLAB); - serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS); - serial_out(up, UART_LCR, cval); - } - - serial_omap_set_mctrl(&up->port, up->port.mctrl); - /* Software Flow Control Configuration */ - if (termios->c_iflag & (IXON | IXOFF)) - serial_omap_configure_xonxoff(up, termios); - - spin_unlock_irqrestore(&up->port.lock, flags); - dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->pdev->id); -} - -static void -serial_omap_pm(struct uart_port *port, unsigned int state, - unsigned int oldstate) -{ - struct uart_omap_port *up = (struct uart_omap_port *)port; - unsigned char efr; - - dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); - efr = serial_in(up, UART_EFR); - serial_out(up, UART_EFR, efr | UART_EFR_ECB); - serial_out(up, UART_LCR, 0); - - serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); - serial_out(up, UART_EFR, efr); - serial_out(up, UART_LCR, 0); - /* Enable module level wake up */ - serial_out(up, UART_OMAP_WER, - (state != 0) ? OMAP_UART_WER_MOD_WKUP : 0); -} - -static void serial_omap_release_port(struct uart_port *port) -{ - dev_dbg(port->dev, "serial_omap_release_port+\n"); -} - -static int serial_omap_request_port(struct uart_port *port) -{ - dev_dbg(port->dev, "serial_omap_request_port+\n"); - return 0; -} - -static void serial_omap_config_port(struct uart_port *port, int flags) -{ - struct uart_omap_port *up = (struct uart_omap_port *)port; - - dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", - up->pdev->id); - up->port.type = PORT_OMAP; -} - -static int -serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) -{ - /* we don't want the core code to modify any port params */ - dev_dbg(port->dev, "serial_omap_verify_port+\n"); - return -EINVAL; -} - -static const char * -serial_omap_type(struct uart_port *port) -{ - struct uart_omap_port *up = (struct uart_omap_port *)port; - - dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->pdev->id); - return up->name; -} - -#ifdef CONFIG_SERIAL_OMAP_CONSOLE - -static struct uart_omap_port *serial_omap_console_ports[4]; - -static struct uart_driver serial_omap_reg; - -#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) - -static inline void wait_for_xmitr(struct uart_omap_port *up) -{ - unsigned int status, tmout = 10000; - - /* Wait up to 10ms for the character(s) to be sent. */ - do { - status = serial_in(up, UART_LSR); - - if (status & UART_LSR_BI) - up->lsr_break_flag = UART_LSR_BI; - - if (--tmout == 0) - break; - udelay(1); - } while ((status & BOTH_EMPTY) != BOTH_EMPTY); - - /* Wait up to 1s for flow control if necessary */ - if (up->port.flags & UPF_CONS_FLOW) { - tmout = 1000000; - for (tmout = 1000000; tmout; tmout--) { - unsigned int msr = serial_in(up, UART_MSR); - - up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; - if (msr & UART_MSR_CTS) - break; - - udelay(1); - } - } -} - -static void serial_omap_console_putchar(struct uart_port *port, int ch) -{ - struct uart_omap_port *up = (struct uart_omap_port *)port; - - wait_for_xmitr(up); - serial_out(up, UART_TX, ch); -} - -static void -serial_omap_console_write(struct console *co, const char *s, - unsigned int count) -{ - struct uart_omap_port *up = serial_omap_console_ports[co->index]; - unsigned long flags; - unsigned int ier; - int locked = 1; - - local_irq_save(flags); - if (up->port.sysrq) - locked = 0; - else if (oops_in_progress) - locked = spin_trylock(&up->port.lock); - else - spin_lock(&up->port.lock); - - /* - * First save the IER then disable the interrupts - */ - ier = serial_in(up, UART_IER); - serial_out(up, UART_IER, 0); - - uart_console_write(&up->port, s, count, serial_omap_console_putchar); - - /* - * Finally, wait for transmitter to become empty - * and restore the IER - */ - wait_for_xmitr(up); - serial_out(up, UART_IER, ier); - /* - * The receive handling will happen properly because the - * receive ready bit will still be set; it is not cleared - * on read. However, modem control will not, we must - * call it if we have saved something in the saved flags - * while processing with interrupts off. - */ - if (up->msr_saved_flags) - check_modem_status(up); - - if (locked) - spin_unlock(&up->port.lock); - local_irq_restore(flags); -} - -static int __init -serial_omap_console_setup(struct console *co, char *options) -{ - struct uart_omap_port *up; - int baud = 115200; - int bits = 8; - int parity = 'n'; - int flow = 'n'; - - if (serial_omap_console_ports[co->index] == NULL) - return -ENODEV; - up = serial_omap_console_ports[co->index]; - - if (options) - uart_parse_options(options, &baud, &parity, &bits, &flow); - - return uart_set_options(&up->port, co, baud, parity, bits, flow); -} - -static struct console serial_omap_console = { - .name = OMAP_SERIAL_NAME, - .write = serial_omap_console_write, - .device = uart_console_device, - .setup = serial_omap_console_setup, - .flags = CON_PRINTBUFFER, - .index = -1, - .data = &serial_omap_reg, -}; - -static void serial_omap_add_console_port(struct uart_omap_port *up) -{ - serial_omap_console_ports[up->pdev->id] = up; -} - -#define OMAP_CONSOLE (&serial_omap_console) - -#else - -#define OMAP_CONSOLE NULL - -static inline void serial_omap_add_console_port(struct uart_omap_port *up) -{} - -#endif - -static struct uart_ops serial_omap_pops = { - .tx_empty = serial_omap_tx_empty, - .set_mctrl = serial_omap_set_mctrl, - .get_mctrl = serial_omap_get_mctrl, - .stop_tx = serial_omap_stop_tx, - .start_tx = serial_omap_start_tx, - .stop_rx = serial_omap_stop_rx, - .enable_ms = serial_omap_enable_ms, - .break_ctl = serial_omap_break_ctl, - .startup = serial_omap_startup, - .shutdown = serial_omap_shutdown, - .set_termios = serial_omap_set_termios, - .pm = serial_omap_pm, - .type = serial_omap_type, - .release_port = serial_omap_release_port, - .request_port = serial_omap_request_port, - .config_port = serial_omap_config_port, - .verify_port = serial_omap_verify_port, -}; - -static struct uart_driver serial_omap_reg = { - .owner = THIS_MODULE, - .driver_name = "OMAP-SERIAL", - .dev_name = OMAP_SERIAL_NAME, - .nr = OMAP_MAX_HSUART_PORTS, - .cons = OMAP_CONSOLE, -}; - -static int -serial_omap_suspend(struct platform_device *pdev, pm_message_t state) -{ - struct uart_omap_port *up = platform_get_drvdata(pdev); - - if (up) - uart_suspend_port(&serial_omap_reg, &up->port); - return 0; -} - -static int serial_omap_resume(struct platform_device *dev) -{ - struct uart_omap_port *up = platform_get_drvdata(dev); - - if (up) - uart_resume_port(&serial_omap_reg, &up->port); - return 0; -} - -static void serial_omap_rx_timeout(unsigned long uart_no) -{ - struct uart_omap_port *up = ui[uart_no]; - unsigned int curr_dma_pos, curr_transmitted_size; - int ret = 0; - - curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel); - if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) || - (curr_dma_pos == 0)) { - if (jiffies_to_msecs(jiffies - up->port_activity) < - RX_TIMEOUT) { - mod_timer(&up->uart_dma.rx_timer, jiffies + - usecs_to_jiffies(up->uart_dma.rx_timeout)); - } else { - serial_omap_stop_rxdma(up); - up->ier |= (UART_IER_RDI | UART_IER_RLSI); - serial_out(up, UART_IER, up->ier); - } - return; - } - - curr_transmitted_size = curr_dma_pos - - up->uart_dma.prev_rx_dma_pos; - up->port.icount.rx += curr_transmitted_size; - tty_insert_flip_string(up->port.state->port.tty, - up->uart_dma.rx_buf + - (up->uart_dma.prev_rx_dma_pos - - up->uart_dma.rx_buf_dma_phys), - curr_transmitted_size); - tty_flip_buffer_push(up->port.state->port.tty); - up->uart_dma.prev_rx_dma_pos = curr_dma_pos; - if (up->uart_dma.rx_buf_size + - up->uart_dma.rx_buf_dma_phys == curr_dma_pos) { - ret = serial_omap_start_rxdma(up); - if (ret < 0) { - serial_omap_stop_rxdma(up); - up->ier |= (UART_IER_RDI | UART_IER_RLSI); - serial_out(up, UART_IER, up->ier); - } - } else { - mod_timer(&up->uart_dma.rx_timer, jiffies + - usecs_to_jiffies(up->uart_dma.rx_timeout)); - } - up->port_activity = jiffies; -} - -static void uart_rx_dma_callback(int lch, u16 ch_status, void *data) -{ - return; -} - -static int serial_omap_start_rxdma(struct uart_omap_port *up) -{ - int ret = 0; - - if (up->uart_dma.rx_dma_channel == -1) { - ret = omap_request_dma(up->uart_dma.uart_dma_rx, - "UART Rx DMA", - (void *)uart_rx_dma_callback, up, - &(up->uart_dma.rx_dma_channel)); - if (ret < 0) - return ret; - - omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0, - OMAP_DMA_AMODE_CONSTANT, - up->uart_dma.uart_base, 0, 0); - omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0, - OMAP_DMA_AMODE_POST_INC, - up->uart_dma.rx_buf_dma_phys, 0, 0); - omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel, - OMAP_DMA_DATA_TYPE_S8, - up->uart_dma.rx_buf_size, 1, - OMAP_DMA_SYNC_ELEMENT, - up->uart_dma.uart_dma_rx, 0); - } - up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys; - /* FIXME: Cache maintenance needed here? */ - omap_start_dma(up->uart_dma.rx_dma_channel); - mod_timer(&up->uart_dma.rx_timer, jiffies + - usecs_to_jiffies(up->uart_dma.rx_timeout)); - up->uart_dma.rx_dma_used = true; - return ret; -} - -static void serial_omap_continue_tx(struct uart_omap_port *up) -{ - struct circ_buf *xmit = &up->port.state->xmit; - unsigned int start = up->uart_dma.tx_buf_dma_phys - + (xmit->tail & (UART_XMIT_SIZE - 1)); - - if (uart_circ_empty(xmit)) - return; - - up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit); - /* - * It is a circular buffer. See if the buffer has wounded back. - * If yes it will have to be transferred in two separate dma - * transfers - */ - if (start + up->uart_dma.tx_buf_size >= - up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - up->uart_dma.tx_buf_size = - (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start; - omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0, - OMAP_DMA_AMODE_CONSTANT, - up->uart_dma.uart_base, 0, 0); - omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0, - OMAP_DMA_AMODE_POST_INC, start, 0, 0); - omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel, - OMAP_DMA_DATA_TYPE_S8, - up->uart_dma.tx_buf_size, 1, - OMAP_DMA_SYNC_ELEMENT, - up->uart_dma.uart_dma_tx, 0); - /* FIXME: Cache maintenance needed here? */ - omap_start_dma(up->uart_dma.tx_dma_channel); -} - -static void uart_tx_dma_callback(int lch, u16 ch_status, void *data) -{ - struct uart_omap_port *up = (struct uart_omap_port *)data; - struct circ_buf *xmit = &up->port.state->xmit; - - xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \ - (UART_XMIT_SIZE - 1); - up->port.icount.tx += up->uart_dma.tx_buf_size; - - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) - uart_write_wakeup(&up->port); - - if (uart_circ_empty(xmit)) { - spin_lock(&(up->uart_dma.tx_lock)); - serial_omap_stop_tx(&up->port); - up->uart_dma.tx_dma_used = false; - spin_unlock(&(up->uart_dma.tx_lock)); - } else { - omap_stop_dma(up->uart_dma.tx_dma_channel); - serial_omap_continue_tx(up); - } - up->port_activity = jiffies; - return; -} - -static int serial_omap_probe(struct platform_device *pdev) -{ - struct uart_omap_port *up; - struct resource *mem, *irq, *dma_tx, *dma_rx; - struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; - int ret = -ENOSPC; - - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!mem) { - dev_err(&pdev->dev, "no mem resource?\n"); - return -ENODEV; - } - - irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!irq) { - dev_err(&pdev->dev, "no irq resource?\n"); - return -ENODEV; - } - - if (!request_mem_region(mem->start, (mem->end - mem->start) + 1, - pdev->dev.driver->name)) { - dev_err(&pdev->dev, "memory region already claimed\n"); - return -EBUSY; - } - - dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); - if (!dma_rx) { - ret = -EINVAL; - goto err; - } - - dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); - if (!dma_tx) { - ret = -EINVAL; - goto err; - } - - up = kzalloc(sizeof(*up), GFP_KERNEL); - if (up == NULL) { - ret = -ENOMEM; - goto do_release_region; - } - sprintf(up->name, "OMAP UART%d", pdev->id); - up->pdev = pdev; - up->port.dev = &pdev->dev; - up->port.type = PORT_OMAP; - up->port.iotype = UPIO_MEM; - up->port.irq = irq->start; - - up->port.regshift = 2; - up->port.fifosize = 64; - up->port.ops = &serial_omap_pops; - up->port.line = pdev->id; - - up->port.membase = omap_up_info->membase; - up->port.mapbase = omap_up_info->mapbase; - up->port.flags = omap_up_info->flags; - up->port.irqflags = omap_up_info->irqflags; - up->port.uartclk = omap_up_info->uartclk; - up->uart_dma.uart_base = mem->start; - - if (omap_up_info->dma_enabled) { - up->uart_dma.uart_dma_tx = dma_tx->start; - up->uart_dma.uart_dma_rx = dma_rx->start; - up->use_dma = 1; - up->uart_dma.rx_buf_size = 4096; - up->uart_dma.rx_timeout = 2; - spin_lock_init(&(up->uart_dma.tx_lock)); - spin_lock_init(&(up->uart_dma.rx_lock)); - up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; - up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; - } - - ui[pdev->id] = up; - serial_omap_add_console_port(up); - - ret = uart_add_one_port(&serial_omap_reg, &up->port); - if (ret != 0) - goto do_release_region; - - platform_set_drvdata(pdev, up); - return 0; -err: - dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", - pdev->id, __func__, ret); -do_release_region: - release_mem_region(mem->start, (mem->end - mem->start) + 1); - return ret; -} - -static int serial_omap_remove(struct platform_device *dev) -{ - struct uart_omap_port *up = platform_get_drvdata(dev); - - platform_set_drvdata(dev, NULL); - if (up) { - uart_remove_one_port(&serial_omap_reg, &up->port); - kfree(up); - } - return 0; -} - -static struct platform_driver serial_omap_driver = { - .probe = serial_omap_probe, - .remove = serial_omap_remove, - - .suspend = serial_omap_suspend, - .resume = serial_omap_resume, - .driver = { - .name = DRIVER_NAME, - }, -}; - -static int __init serial_omap_init(void) -{ - int ret; - - ret = uart_register_driver(&serial_omap_reg); - if (ret != 0) - return ret; - ret = platform_driver_register(&serial_omap_driver); - if (ret != 0) - uart_unregister_driver(&serial_omap_reg); - return ret; -} - -static void __exit serial_omap_exit(void) -{ - platform_driver_unregister(&serial_omap_driver); - uart_unregister_driver(&serial_omap_reg); -} - -module_init(serial_omap_init); -module_exit(serial_omap_exit); - -MODULE_DESCRIPTION("OMAP High Speed UART driver"); -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Texas Instruments Inc"); diff --git a/trunk/drivers/usb/gadget/omap_udc.c b/trunk/drivers/usb/gadget/omap_udc.c index cb5cd422f3f5..61d3ca6619bb 100644 --- a/trunk/drivers/usb/gadget/omap_udc.c +++ b/trunk/drivers/usb/gadget/omap_udc.c @@ -54,6 +54,7 @@ #include #include +#include #include "omap_udc.h" @@ -2308,12 +2309,21 @@ static char *trx_mode(unsigned m, int enabled) static int proc_otg_show(struct seq_file *s) { u32 tmp; - u32 trans = 0; - char *ctrl_name = "(UNKNOWN)"; + u32 trans; + char *ctrl_name; - /* XXX This needs major revision for OMAP2+ */ tmp = omap_readl(OTG_REV); - if (cpu_class_is_omap1()) { + if (cpu_is_omap24xx()) { + /* + * REVISIT: Not clear how this works on OMAP2. trans + * is ANDed to produce bits 7 and 8, which might make + * sense for USB_TRANSCEIVER_CTRL on OMAP1, + * but with CONTROL_DEVCONF, these bits have something to + * do with the frame adjustment counter and McBSP2. + */ + ctrl_name = "control_devconf"; + trans = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + } else { ctrl_name = "tranceiver_ctrl"; trans = omap_readw(USB_TRANSCEIVER_CTRL); } diff --git a/trunk/drivers/watchdog/omap_wdt.c b/trunk/drivers/watchdog/omap_wdt.c index 3dd4971160ef..81e3d6100894 100644 --- a/trunk/drivers/watchdog/omap_wdt.c +++ b/trunk/drivers/watchdog/omap_wdt.c @@ -38,11 +38,11 @@ #include #include #include +#include #include #include #include #include -#include #include #include @@ -61,6 +61,8 @@ struct omap_wdt_dev { void __iomem *base; /* physical */ struct device *dev; int omap_wdt_users; + struct clk *ick; + struct clk *fck; struct resource *mem; struct miscdevice omap_wdt_miscdev; }; @@ -144,7 +146,8 @@ static int omap_wdt_open(struct inode *inode, struct file *file) if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users))) return -EBUSY; - pm_runtime_get_sync(wdev->dev); + clk_enable(wdev->ick); /* Enable the interface clock */ + clk_enable(wdev->fck); /* Enable the functional clock */ /* initialize prescaler */ while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01) @@ -174,7 +177,8 @@ static int omap_wdt_release(struct inode *inode, struct file *file) omap_wdt_disable(wdev); - pm_runtime_put_sync(wdev->dev); + clk_disable(wdev->ick); + clk_disable(wdev->fck); #else printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n"); #endif @@ -289,7 +293,19 @@ static int __devinit omap_wdt_probe(struct platform_device *pdev) wdev->omap_wdt_users = 0; wdev->mem = mem; - wdev->dev = &pdev->dev; + + wdev->ick = clk_get(&pdev->dev, "ick"); + if (IS_ERR(wdev->ick)) { + ret = PTR_ERR(wdev->ick); + wdev->ick = NULL; + goto err_clk; + } + wdev->fck = clk_get(&pdev->dev, "fck"); + if (IS_ERR(wdev->fck)) { + ret = PTR_ERR(wdev->fck); + wdev->fck = NULL; + goto err_clk; + } wdev->base = ioremap(res->start, resource_size(res)); if (!wdev->base) { @@ -299,8 +315,8 @@ static int __devinit omap_wdt_probe(struct platform_device *pdev) platform_set_drvdata(pdev, wdev); - pm_runtime_enable(wdev->dev); - pm_runtime_get_sync(wdev->dev); + clk_enable(wdev->ick); + clk_enable(wdev->fck); omap_wdt_disable(wdev); omap_wdt_adjust_timeout(timer_margin); @@ -318,7 +334,11 @@ static int __devinit omap_wdt_probe(struct platform_device *pdev) __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF, timer_margin); - pm_runtime_put_sync(wdev->dev); + /* autogate OCP interface clock */ + __raw_writel(0x01, wdev->base + OMAP_WATCHDOG_SYS_CONFIG); + + clk_disable(wdev->ick); + clk_disable(wdev->fck); omap_wdt_dev = pdev; @@ -330,6 +350,12 @@ static int __devinit omap_wdt_probe(struct platform_device *pdev) err_ioremap: wdev->base = NULL; + +err_clk: + if (wdev->ick) + clk_put(wdev->ick); + if (wdev->fck) + clk_put(wdev->fck); kfree(wdev); err_kzalloc: @@ -361,6 +387,8 @@ static int __devexit omap_wdt_remove(struct platform_device *pdev) release_mem_region(res->start, resource_size(res)); platform_set_drvdata(pdev, NULL); + clk_put(wdev->ick); + clk_put(wdev->fck); iounmap(wdev->base); kfree(wdev); diff --git a/trunk/fs/lockd/clntlock.c b/trunk/fs/lockd/clntlock.c index d5bb86866e6c..64fd427c993c 100644 --- a/trunk/fs/lockd/clntlock.c +++ b/trunk/fs/lockd/clntlock.c @@ -42,7 +42,6 @@ struct nlm_wait { }; static LIST_HEAD(nlm_blocked); -static DEFINE_SPINLOCK(nlm_blocked_lock); /** * nlmclnt_init - Set up per-NFS mount point lockd data structures @@ -98,10 +97,7 @@ struct nlm_wait *nlmclnt_prepare_block(struct nlm_host *host, struct file_lock * block->b_lock = fl; init_waitqueue_head(&block->b_wait); block->b_status = nlm_lck_blocked; - - spin_lock(&nlm_blocked_lock); list_add(&block->b_list, &nlm_blocked); - spin_unlock(&nlm_blocked_lock); } return block; } @@ -110,9 +106,7 @@ void nlmclnt_finish_block(struct nlm_wait *block) { if (block == NULL) return; - spin_lock(&nlm_blocked_lock); list_del(&block->b_list); - spin_unlock(&nlm_blocked_lock); kfree(block); } @@ -160,7 +154,6 @@ __be32 nlmclnt_grant(const struct sockaddr *addr, const struct nlm_lock *lock) * Look up blocked request based on arguments. * Warning: must not use cookie to match it! */ - spin_lock(&nlm_blocked_lock); list_for_each_entry(block, &nlm_blocked, b_list) { struct file_lock *fl_blocked = block->b_lock; @@ -185,7 +178,6 @@ __be32 nlmclnt_grant(const struct sockaddr *addr, const struct nlm_lock *lock) wake_up(&block->b_wait); res = nlm_granted; } - spin_unlock(&nlm_blocked_lock); return res; } @@ -224,6 +216,10 @@ reclaimer(void *ptr) allow_signal(SIGKILL); down_write(&host->h_rwsem); + + /* This one ensures that our parent doesn't terminate while the + * reclaim is in progress */ + lock_kernel(); lockd_up(); /* note: this cannot fail as lockd is already running */ dprintk("lockd: reclaiming locks for host %s\n", host->h_name); @@ -264,17 +260,16 @@ reclaimer(void *ptr) dprintk("NLM: done reclaiming locks for host %s\n", host->h_name); /* Now, wake up all processes that sleep on a blocked lock */ - spin_lock(&nlm_blocked_lock); list_for_each_entry(block, &nlm_blocked, b_list) { if (block->b_host == host) { block->b_status = nlm_lck_denied_grace_period; wake_up(&block->b_wait); } } - spin_unlock(&nlm_blocked_lock); /* Release host handle after use */ nlm_release_host(host); lockd_down(); + unlock_kernel(); return 0; } diff --git a/trunk/fs/lockd/clntproc.c b/trunk/fs/lockd/clntproc.c index 47ea1e1925b8..7932c399fab4 100644 --- a/trunk/fs/lockd/clntproc.c +++ b/trunk/fs/lockd/clntproc.c @@ -166,6 +166,7 @@ int nlmclnt_proc(struct nlm_host *host, int cmd, struct file_lock *fl) /* Set up the argument struct */ nlmclnt_setlockargs(call, fl); + lock_kernel(); if (IS_SETLK(cmd) || IS_SETLKW(cmd)) { if (fl->fl_type != F_UNLCK) { call->a_args.block = IS_SETLKW(cmd) ? 1 : 0; @@ -176,8 +177,10 @@ int nlmclnt_proc(struct nlm_host *host, int cmd, struct file_lock *fl) status = nlmclnt_test(call, fl); else status = -EINVAL; + fl->fl_ops->fl_release_private(fl); fl->fl_ops = NULL; + unlock_kernel(); dprintk("lockd: clnt proc returns %d\n", status); return status; @@ -223,7 +226,9 @@ void nlm_release_call(struct nlm_rqst *call) static void nlmclnt_rpc_release(void *data) { + lock_kernel(); nlm_release_call(data); + unlock_kernel(); } static int nlm_wait_on_grace(wait_queue_head_t *queue) @@ -443,18 +448,14 @@ nlmclnt_test(struct nlm_rqst *req, struct file_lock *fl) static void nlmclnt_locks_copy_lock(struct file_lock *new, struct file_lock *fl) { - spin_lock(&fl->fl_u.nfs_fl.owner->host->h_lock); new->fl_u.nfs_fl.state = fl->fl_u.nfs_fl.state; new->fl_u.nfs_fl.owner = nlm_get_lockowner(fl->fl_u.nfs_fl.owner); list_add_tail(&new->fl_u.nfs_fl.list, &fl->fl_u.nfs_fl.owner->host->h_granted); - spin_unlock(&fl->fl_u.nfs_fl.owner->host->h_lock); } static void nlmclnt_locks_release_private(struct file_lock *fl) { - spin_lock(&fl->fl_u.nfs_fl.owner->host->h_lock); list_del(&fl->fl_u.nfs_fl.list); - spin_unlock(&fl->fl_u.nfs_fl.owner->host->h_lock); nlm_put_lockowner(fl->fl_u.nfs_fl.owner); } @@ -720,7 +721,9 @@ static void nlmclnt_unlock_callback(struct rpc_task *task, void *data) die: return; retry_rebind: + lock_kernel(); nlm_rebind_host(req->a_host); + unlock_kernel(); retry_unlock: rpc_restart_call(task); } @@ -798,7 +801,9 @@ static void nlmclnt_cancel_callback(struct rpc_task *task, void *data) /* Don't ever retry more than 3 times */ if (req->a_retries++ >= NLMCLNT_MAX_RETRIES) goto die; + lock_kernel(); nlm_rebind_host(req->a_host); + unlock_kernel(); rpc_restart_call(task); rpc_delay(task, 30 * HZ); } diff --git a/trunk/fs/nfs/Kconfig b/trunk/fs/nfs/Kconfig index 5c55c26af165..b950415d7c43 100644 --- a/trunk/fs/nfs/Kconfig +++ b/trunk/fs/nfs/Kconfig @@ -118,14 +118,3 @@ config NFS_USE_KERNEL_DNS select DNS_RESOLVER select KEYS default y - -config NFS_USE_NEW_IDMAPPER - bool "Use the new idmapper upcall routine" - depends on NFS_V4 && KEYS - help - Say Y here if you want NFS to use the new idmapper upcall functions. - You will need /sbin/request-key (usually provided by the keyutils - package). For details, read - . - - If you are unsure, say N. diff --git a/trunk/fs/nfs/client.c b/trunk/fs/nfs/client.c index a882785eba41..e7340729af89 100644 --- a/trunk/fs/nfs/client.c +++ b/trunk/fs/nfs/client.c @@ -635,8 +635,7 @@ static int nfs_create_rpc_client(struct nfs_client *clp, */ static void nfs_destroy_server(struct nfs_server *server) { - if (!(server->flags & NFS_MOUNT_LOCAL_FLOCK) || - !(server->flags & NFS_MOUNT_LOCAL_FCNTL)) + if (!(server->flags & NFS_MOUNT_NONLM)) nlmclnt_done(server->nlm_host); } @@ -658,8 +657,7 @@ static int nfs_start_lockd(struct nfs_server *server) if (nlm_init.nfs_version > 3) return 0; - if ((server->flags & NFS_MOUNT_LOCAL_FLOCK) && - (server->flags & NFS_MOUNT_LOCAL_FCNTL)) + if (server->flags & NFS_MOUNT_NONLM) return 0; switch (clp->cl_proto) { @@ -903,8 +901,8 @@ static void nfs_server_set_fsinfo(struct nfs_server *server, struct nfs_fsinfo * server->wtmult = nfs_block_bits(fsinfo->wtmult, NULL); server->dtsize = nfs_block_size(fsinfo->dtpref, NULL); - if (server->dtsize > PAGE_CACHE_SIZE * NFS_MAX_READDIR_PAGES) - server->dtsize = PAGE_CACHE_SIZE * NFS_MAX_READDIR_PAGES; + if (server->dtsize > PAGE_CACHE_SIZE) + server->dtsize = PAGE_CACHE_SIZE; if (server->dtsize > server->rsize) server->dtsize = server->rsize; @@ -915,8 +913,6 @@ static void nfs_server_set_fsinfo(struct nfs_server *server, struct nfs_fsinfo * server->maxfilesize = fsinfo->maxfilesize; - server->time_delta = fsinfo->time_delta; - /* We're airborne Set socket buffersize */ rpc_setbufsize(server->client, server->wsize + 100, server->rsize + 100); } @@ -1360,9 +1356,8 @@ static int nfs4_init_server(struct nfs_server *server, /* Initialise the client representation from the mount data */ server->flags = data->flags; - server->caps |= NFS_CAP_ATOMIC_OPEN|NFS_CAP_CHANGE_ATTR|NFS_CAP_POSIX_LOCK; - if (!(data->flags & NFS_MOUNT_NORDIRPLUS)) - server->caps |= NFS_CAP_READDIRPLUS; + server->caps |= NFS_CAP_ATOMIC_OPEN|NFS_CAP_CHANGE_ATTR| + NFS_CAP_POSIX_LOCK; server->options = data->options; /* Get a client record */ diff --git a/trunk/fs/nfs/dir.c b/trunk/fs/nfs/dir.c index 257e4052492e..e257172d438c 100644 --- a/trunk/fs/nfs/dir.c +++ b/trunk/fs/nfs/dir.c @@ -33,12 +33,11 @@ #include #include #include -#include +#include "nfs4_fs.h" #include "delegation.h" #include "iostat.h" #include "internal.h" -#include "fscache.h" /* #define NFS_DEBUG_VERBOSE 1 */ @@ -56,7 +55,6 @@ static int nfs_rename(struct inode *, struct dentry *, struct inode *, struct dentry *); static int nfs_fsync_dir(struct file *, int); static loff_t nfs_llseek_dir(struct file *, loff_t, int); -static int nfs_readdir_clear_array(struct page*, gfp_t); const struct file_operations nfs_dir_operations = { .llseek = nfs_llseek_dir, @@ -82,10 +80,6 @@ const struct inode_operations nfs_dir_inode_operations = { .setattr = nfs_setattr, }; -const struct address_space_operations nfs_dir_addr_space_ops = { - .releasepage = nfs_readdir_clear_array, -}; - #ifdef CONFIG_NFS_V3 const struct inode_operations nfs3_dir_inode_operations = { .create = nfs_create, @@ -110,9 +104,8 @@ const struct inode_operations nfs3_dir_inode_operations = { #ifdef CONFIG_NFS_V4 static struct dentry *nfs_atomic_lookup(struct inode *, struct dentry *, struct nameidata *); -static int nfs_open_create(struct inode *dir, struct dentry *dentry, int mode, struct nameidata *nd); const struct inode_operations nfs4_dir_inode_operations = { - .create = nfs_open_create, + .create = nfs_create, .lookup = nfs_atomic_lookup, .link = nfs_link, .unlink = nfs_unlink, @@ -157,197 +150,51 @@ nfs_opendir(struct inode *inode, struct file *filp) return res; } -struct nfs_cache_array_entry { - u64 cookie; - u64 ino; - struct qstr string; -}; - -struct nfs_cache_array { - unsigned int size; - int eof_index; - u64 last_cookie; - struct nfs_cache_array_entry array[0]; -}; - -#define MAX_READDIR_ARRAY ((PAGE_SIZE - sizeof(struct nfs_cache_array)) / sizeof(struct nfs_cache_array_entry)) - -typedef __be32 * (*decode_dirent_t)(struct xdr_stream *, struct nfs_entry *, struct nfs_server *, int); +typedef __be32 * (*decode_dirent_t)(__be32 *, struct nfs_entry *, int); typedef struct { struct file *file; struct page *page; unsigned long page_index; + __be32 *ptr; u64 *dir_cookie; loff_t current_index; + struct nfs_entry *entry; decode_dirent_t decode; - + int plus; unsigned long timestamp; unsigned long gencount; - unsigned int cache_entry_index; - unsigned int plus:1; - unsigned int eof:1; + int timestamp_valid; } nfs_readdir_descriptor_t; -/* - * The caller is responsible for calling nfs_readdir_release_array(page) - */ -static -struct nfs_cache_array *nfs_readdir_get_array(struct page *page) -{ - if (page == NULL) - return ERR_PTR(-EIO); - return (struct nfs_cache_array *)kmap(page); -} - -static -void nfs_readdir_release_array(struct page *page) -{ - kunmap(page); -} - -/* - * we are freeing strings created by nfs_add_to_readdir_array() - */ -static -int nfs_readdir_clear_array(struct page *page, gfp_t mask) -{ - struct nfs_cache_array *array = nfs_readdir_get_array(page); - int i; - for (i = 0; i < array->size; i++) - kfree(array->array[i].string.name); - nfs_readdir_release_array(page); - return 0; -} - -/* - * the caller is responsible for freeing qstr.name - * when called by nfs_readdir_add_to_array, the strings will be freed in - * nfs_clear_readdir_array() +/* Now we cache directories properly, by stuffing the dirent + * data directly in the page cache. + * + * Inode invalidation due to refresh etc. takes care of + * _everything_, no sloppy entry flushing logic, no extraneous + * copying, network direct to page cache, the way it was meant + * to be. + * + * NOTE: Dirent information verification is done always by the + * page-in of the RPC reply, nowhere else, this simplies + * things substantially. */ static -int nfs_readdir_make_qstr(struct qstr *string, const char *name, unsigned int len) -{ - string->len = len; - string->name = kmemdup(name, len, GFP_KERNEL); - if (string->name == NULL) - return -ENOMEM; - string->hash = full_name_hash(name, len); - return 0; -} - -static -int nfs_readdir_add_to_array(struct nfs_entry *entry, struct page *page) -{ - struct nfs_cache_array *array = nfs_readdir_get_array(page); - struct nfs_cache_array_entry *cache_entry; - int ret; - - if (IS_ERR(array)) - return PTR_ERR(array); - ret = -EIO; - if (array->size >= MAX_READDIR_ARRAY) - goto out; - - cache_entry = &array->array[array->size]; - cache_entry->cookie = entry->prev_cookie; - cache_entry->ino = entry->ino; - ret = nfs_readdir_make_qstr(&cache_entry->string, entry->name, entry->len); - if (ret) - goto out; - array->last_cookie = entry->cookie; - if (entry->eof == 1) - array->eof_index = array->size; - array->size++; -out: - nfs_readdir_release_array(page); - return ret; -} - -static -int nfs_readdir_search_for_pos(struct nfs_cache_array *array, nfs_readdir_descriptor_t *desc) -{ - loff_t diff = desc->file->f_pos - desc->current_index; - unsigned int index; - - if (diff < 0) - goto out_eof; - if (diff >= array->size) { - if (array->eof_index > 0) - goto out_eof; - desc->current_index += array->size; - return -EAGAIN; - } - - index = (unsigned int)diff; - *desc->dir_cookie = array->array[index].cookie; - desc->cache_entry_index = index; - if (index == array->eof_index) - desc->eof = 1; - return 0; -out_eof: - desc->eof = 1; - return -EBADCOOKIE; -} - -static -int nfs_readdir_search_for_cookie(struct nfs_cache_array *array, nfs_readdir_descriptor_t *desc) -{ - int i; - int status = -EAGAIN; - - for (i = 0; i < array->size; i++) { - if (i == array->eof_index) { - desc->eof = 1; - status = -EBADCOOKIE; - } - if (array->array[i].cookie == *desc->dir_cookie) { - desc->cache_entry_index = i; - status = 0; - break; - } - } - - return status; -} - -static -int nfs_readdir_search_array(nfs_readdir_descriptor_t *desc) -{ - struct nfs_cache_array *array; - int status = -EBADCOOKIE; - - if (desc->dir_cookie == NULL) - goto out; - - array = nfs_readdir_get_array(desc->page); - if (IS_ERR(array)) { - status = PTR_ERR(array); - goto out; - } - - if (*desc->dir_cookie == 0) - status = nfs_readdir_search_for_pos(array, desc); - else - status = nfs_readdir_search_for_cookie(array, desc); - - nfs_readdir_release_array(desc->page); -out: - return status; -} - -/* Fill a page with xdr information before transferring to the cache page */ -static -int nfs_readdir_xdr_filler(struct page **pages, nfs_readdir_descriptor_t *desc, - struct nfs_entry *entry, struct file *file, struct inode *inode) +int nfs_readdir_filler(nfs_readdir_descriptor_t *desc, struct page *page) { + struct file *file = desc->file; + struct inode *inode = file->f_path.dentry->d_inode; struct rpc_cred *cred = nfs_file_cred(file); unsigned long timestamp, gencount; int error; + dfprintk(DIRCACHE, "NFS: %s: reading cookie %Lu into page %lu\n", + __func__, (long long)desc->entry->cookie, + page->index); + again: timestamp = jiffies; gencount = nfs_inc_attr_generation_counter(); - error = NFS_PROTO(inode)->readdir(file->f_path.dentry, cred, entry->cookie, pages, + error = NFS_PROTO(inode)->readdir(file->f_path.dentry, cred, desc->entry->cookie, page, NFS_SERVER(inode)->dtsize, desc->plus); if (error < 0) { /* We requested READDIRPLUS, but the server doesn't grok it */ @@ -361,292 +208,190 @@ int nfs_readdir_xdr_filler(struct page **pages, nfs_readdir_descriptor_t *desc, } desc->timestamp = timestamp; desc->gencount = gencount; -error: - return error; + desc->timestamp_valid = 1; + SetPageUptodate(page); + /* Ensure consistent page alignment of the data. + * Note: assumes we have exclusive access to this mapping either + * through inode->i_mutex or some other mechanism. + */ + if (invalidate_inode_pages2_range(inode->i_mapping, page->index + 1, -1) < 0) { + /* Should never happen */ + nfs_zap_mapping(inode, inode->i_mapping); + } + unlock_page(page); + return 0; + error: + unlock_page(page); + return -EIO; } -/* Fill in an entry based on the xdr code stored in desc->page */ -static -int xdr_decode(nfs_readdir_descriptor_t *desc, struct nfs_entry *entry, struct xdr_stream *stream) +static inline +int dir_decode(nfs_readdir_descriptor_t *desc) { - __be32 *p = desc->decode(stream, entry, NFS_SERVER(desc->file->f_path.dentry->d_inode), desc->plus); + __be32 *p = desc->ptr; + p = desc->decode(p, desc->entry, desc->plus); if (IS_ERR(p)) return PTR_ERR(p); - - entry->fattr->time_start = desc->timestamp; - entry->fattr->gencount = desc->gencount; - return 0; -} - -static -int nfs_same_file(struct dentry *dentry, struct nfs_entry *entry) -{ - struct nfs_inode *node; - if (dentry->d_inode == NULL) - goto different; - node = NFS_I(dentry->d_inode); - if (node->fh.size != entry->fh->size) - goto different; - if (strncmp(node->fh.data, entry->fh->data, node->fh.size) != 0) - goto different; - return 1; -different: + desc->ptr = p; + if (desc->timestamp_valid) { + desc->entry->fattr->time_start = desc->timestamp; + desc->entry->fattr->gencount = desc->gencount; + } else + desc->entry->fattr->valid &= ~NFS_ATTR_FATTR; return 0; } -static -void nfs_prime_dcache(struct dentry *parent, struct nfs_entry *entry) +static inline +void dir_page_release(nfs_readdir_descriptor_t *desc) { - struct qstr filename = { - .len = entry->len, - .name = entry->name, - }; - struct dentry *dentry; - struct dentry *alias; - struct inode *dir = parent->d_inode; - struct inode *inode; - - if (filename.name[0] == '.') { - if (filename.len == 1) - return; - if (filename.len == 2 && filename.name[1] == '.') - return; - } - filename.hash = full_name_hash(filename.name, filename.len); - - dentry = d_lookup(parent, &filename); - if (dentry != NULL) { - if (nfs_same_file(dentry, entry)) { - nfs_refresh_inode(dentry->d_inode, entry->fattr); - goto out; - } else { - d_drop(dentry); - dput(dentry); - } - } - - dentry = d_alloc(parent, &filename); - if (dentry == NULL) - return; - - dentry->d_op = NFS_PROTO(dir)->dentry_ops; - inode = nfs_fhget(dentry->d_sb, entry->fh, entry->fattr); - if (IS_ERR(inode)) - goto out; - - alias = d_materialise_unique(dentry, inode); - if (IS_ERR(alias)) - goto out; - else if (alias) { - nfs_set_verifier(alias, nfs_save_change_attribute(dir)); - dput(alias); - } else - nfs_set_verifier(dentry, nfs_save_change_attribute(dir)); - -out: - dput(dentry); + kunmap(desc->page); + page_cache_release(desc->page); + desc->page = NULL; + desc->ptr = NULL; } -/* Perform conversion from xdr to cache array */ -static -void nfs_readdir_page_filler(nfs_readdir_descriptor_t *desc, struct nfs_entry *entry, - void *xdr_page, struct page *page, unsigned int buflen) +/* + * Given a pointer to a buffer that has already been filled by a call + * to readdir, find the next entry with cookie '*desc->dir_cookie'. + * + * If the end of the buffer has been reached, return -EAGAIN, if not, + * return the offset within the buffer of the next entry to be + * read. + */ +static inline +int find_dirent(nfs_readdir_descriptor_t *desc) { - struct xdr_stream stream; - struct xdr_buf buf; - __be32 *ptr = xdr_page; - int status; - struct nfs_cache_array *array; - - buf.head->iov_base = xdr_page; - buf.head->iov_len = buflen; - buf.tail->iov_len = 0; - buf.page_base = 0; - buf.page_len = 0; - buf.buflen = buf.head->iov_len; - buf.len = buf.head->iov_len; - - xdr_init_decode(&stream, &buf, ptr); - - - do { - status = xdr_decode(desc, entry, &stream); - if (status != 0) - break; + struct nfs_entry *entry = desc->entry; + int loop_count = 0, + status; - if (nfs_readdir_add_to_array(entry, page) == -1) + while((status = dir_decode(desc)) == 0) { + dfprintk(DIRCACHE, "NFS: %s: examining cookie %Lu\n", + __func__, (unsigned long long)entry->cookie); + if (entry->prev_cookie == *desc->dir_cookie) break; - if (desc->plus == 1) - nfs_prime_dcache(desc->file->f_path.dentry, entry); - } while (!entry->eof); - - if (status == -EBADCOOKIE && entry->eof) { - array = nfs_readdir_get_array(page); - array->eof_index = array->size - 1; - status = 0; - nfs_readdir_release_array(page); + if (loop_count++ > 200) { + loop_count = 0; + schedule(); + } } -} - -static -void nfs_readdir_free_pagearray(struct page **pages, unsigned int npages) -{ - unsigned int i; - for (i = 0; i < npages; i++) - put_page(pages[i]); -} - -static -void nfs_readdir_free_large_page(void *ptr, struct page **pages, - unsigned int npages) -{ - vm_unmap_ram(ptr, npages); - nfs_readdir_free_pagearray(pages, npages); + return status; } /* - * nfs_readdir_large_page will allocate pages that must be freed with a call - * to nfs_readdir_free_large_page + * Given a pointer to a buffer that has already been filled by a call + * to readdir, find the entry at offset 'desc->file->f_pos'. + * + * If the end of the buffer has been reached, return -EAGAIN, if not, + * return the offset within the buffer of the next entry to be + * read. */ -static -void *nfs_readdir_large_page(struct page **pages, unsigned int npages) -{ - void *ptr; - unsigned int i; - - for (i = 0; i < npages; i++) { - struct page *page = alloc_page(GFP_KERNEL); - if (page == NULL) - goto out_freepages; - pages[i] = page; - } - - ptr = vm_map_ram(pages, npages, 0, PAGE_KERNEL); - if (!IS_ERR_OR_NULL(ptr)) - return ptr; -out_freepages: - nfs_readdir_free_pagearray(pages, i); - return NULL; -} - -static -int nfs_readdir_xdr_to_array(nfs_readdir_descriptor_t *desc, struct page *page, struct inode *inode) +static inline +int find_dirent_index(nfs_readdir_descriptor_t *desc) { - struct page *pages[NFS_MAX_READDIR_PAGES]; - void *pages_ptr = NULL; - struct nfs_entry entry; - struct file *file = desc->file; - struct nfs_cache_array *array; - int status = 0; - unsigned int array_size = ARRAY_SIZE(pages); - - entry.prev_cookie = 0; - entry.cookie = *desc->dir_cookie; - entry.eof = 0; - entry.fh = nfs_alloc_fhandle(); - entry.fattr = nfs_alloc_fattr(); - if (entry.fh == NULL || entry.fattr == NULL) - goto out; + struct nfs_entry *entry = desc->entry; + int loop_count = 0, + status; - array = nfs_readdir_get_array(page); - memset(array, 0, sizeof(struct nfs_cache_array)); - array->eof_index = -1; + for(;;) { + status = dir_decode(desc); + if (status) + break; - pages_ptr = nfs_readdir_large_page(pages, array_size); - if (!pages_ptr) - goto out_release_array; - do { - status = nfs_readdir_xdr_filler(pages, desc, &entry, file, inode); + dfprintk(DIRCACHE, "NFS: found cookie %Lu at index %Ld\n", + (unsigned long long)entry->cookie, desc->current_index); - if (status < 0) + if (desc->file->f_pos == desc->current_index) { + *desc->dir_cookie = entry->cookie; break; - nfs_readdir_page_filler(desc, &entry, pages_ptr, page, array_size * PAGE_SIZE); - } while (array->eof_index < 0 && array->size < MAX_READDIR_ARRAY); - - nfs_readdir_free_large_page(pages_ptr, pages, array_size); -out_release_array: - nfs_readdir_release_array(page); -out: - nfs_free_fattr(entry.fattr); - nfs_free_fhandle(entry.fh); + } + desc->current_index++; + if (loop_count++ > 200) { + loop_count = 0; + schedule(); + } + } return status; } /* - * Now we cache directories properly, by converting xdr information - * to an array that can be used for lookups later. This results in - * fewer cache pages, since we can store more information on each page. - * We only need to convert from xdr once so future lookups are much simpler + * Find the given page, and call find_dirent() or find_dirent_index in + * order to try to return the next entry. */ -static -int nfs_readdir_filler(nfs_readdir_descriptor_t *desc, struct page* page) +static inline +int find_dirent_page(nfs_readdir_descriptor_t *desc) { struct inode *inode = desc->file->f_path.dentry->d_inode; + struct page *page; + int status; - if (nfs_readdir_xdr_to_array(desc, page, inode) < 0) - goto error; - SetPageUptodate(page); + dfprintk(DIRCACHE, "NFS: %s: searching page %ld for target %Lu\n", + __func__, desc->page_index, + (long long) *desc->dir_cookie); - if (invalidate_inode_pages2_range(inode->i_mapping, page->index + 1, -1) < 0) { - /* Should never happen */ - nfs_zap_mapping(inode, inode->i_mapping); + /* If we find the page in the page_cache, we cannot be sure + * how fresh the data is, so we will ignore readdir_plus attributes. + */ + desc->timestamp_valid = 0; + page = read_cache_page(inode->i_mapping, desc->page_index, + (filler_t *)nfs_readdir_filler, desc); + if (IS_ERR(page)) { + status = PTR_ERR(page); + goto out; } - unlock_page(page); - return 0; - error: - unlock_page(page); - return -EIO; -} -static -void cache_page_release(nfs_readdir_descriptor_t *desc) -{ - page_cache_release(desc->page); - desc->page = NULL; -} - -static -struct page *get_cache_page(nfs_readdir_descriptor_t *desc) -{ - struct page *page; - page = read_cache_page(desc->file->f_path.dentry->d_inode->i_mapping, - desc->page_index, (filler_t *)nfs_readdir_filler, desc); - if (IS_ERR(page)) - desc->eof = 1; - return page; + /* NOTE: Someone else may have changed the READDIRPLUS flag */ + desc->page = page; + desc->ptr = kmap(page); /* matching kunmap in nfs_do_filldir */ + if (*desc->dir_cookie != 0) + status = find_dirent(desc); + else + status = find_dirent_index(desc); + if (status < 0) + dir_page_release(desc); + out: + dfprintk(DIRCACHE, "NFS: %s: returns %d\n", __func__, status); + return status; } /* - * Returns 0 if desc->dir_cookie was found on page desc->page_index + * Recurse through the page cache pages, and return a + * filled nfs_entry structure of the next directory entry if possible. + * + * The target for the search is '*desc->dir_cookie' if non-0, + * 'desc->file->f_pos' otherwise */ -static -int find_cache_page(nfs_readdir_descriptor_t *desc) -{ - int res; - - desc->page = get_cache_page(desc); - if (IS_ERR(desc->page)) - return PTR_ERR(desc->page); - - res = nfs_readdir_search_array(desc); - if (res == 0) - return 0; - cache_page_release(desc); - return res; -} - -/* Search for desc->dir_cookie from the beginning of the page cache */ static inline int readdir_search_pagecache(nfs_readdir_descriptor_t *desc) { - int res = -EAGAIN; + int loop_count = 0; + int res; + + /* Always search-by-index from the beginning of the cache */ + if (*desc->dir_cookie == 0) { + dfprintk(DIRCACHE, "NFS: readdir_search_pagecache() searching for offset %Ld\n", + (long long)desc->file->f_pos); + desc->page_index = 0; + desc->entry->cookie = desc->entry->prev_cookie = 0; + desc->entry->eof = 0; + desc->current_index = 0; + } else + dfprintk(DIRCACHE, "NFS: readdir_search_pagecache() searching for cookie %Lu\n", + (unsigned long long)*desc->dir_cookie); - while (1) { - res = find_cache_page(desc); + for (;;) { + res = find_dirent_page(desc); if (res != -EAGAIN) break; - desc->page_index++; + /* Align to beginning of next page */ + desc->page_index ++; + if (loop_count++ > 200) { + loop_count = 0; + schedule(); + } } + + dfprintk(DIRCACHE, "NFS: %s: returns %d\n", __func__, res); return res; } @@ -655,6 +400,8 @@ static inline unsigned int dt_type(struct inode *inode) return (inode->i_mode >> 12) & 15; } +static struct dentry *nfs_readdir_lookup(nfs_readdir_descriptor_t *desc); + /* * Once we've found the start of the dirent within a page: fill 'er up... */ @@ -663,36 +410,49 @@ int nfs_do_filldir(nfs_readdir_descriptor_t *desc, void *dirent, filldir_t filldir) { struct file *file = desc->file; - int i = 0; - int res = 0; - struct nfs_cache_array *array = NULL; - unsigned int d_type = DT_UNKNOWN; - struct dentry *dentry = NULL; - - array = nfs_readdir_get_array(desc->page); + struct nfs_entry *entry = desc->entry; + struct dentry *dentry = NULL; + u64 fileid; + int loop_count = 0, + res; + + dfprintk(DIRCACHE, "NFS: nfs_do_filldir() filling starting @ cookie %Lu\n", + (unsigned long long)entry->cookie); + + for(;;) { + unsigned d_type = DT_UNKNOWN; + /* Note: entry->prev_cookie contains the cookie for + * retrieving the current dirent on the server */ + fileid = entry->ino; + + /* Get a dentry if we have one */ + if (dentry != NULL) + dput(dentry); + dentry = nfs_readdir_lookup(desc); - for (i = desc->cache_entry_index; i < array->size; i++) { - d_type = DT_UNKNOWN; + /* Use readdirplus info */ + if (dentry != NULL && dentry->d_inode != NULL) { + d_type = dt_type(dentry->d_inode); + fileid = NFS_FILEID(dentry->d_inode); + } - res = filldir(dirent, array->array[i].string.name, - array->array[i].string.len, file->f_pos, - nfs_compat_user_ino64(array->array[i].ino), d_type); + res = filldir(dirent, entry->name, entry->len, + file->f_pos, nfs_compat_user_ino64(fileid), + d_type); if (res < 0) break; file->f_pos++; - desc->cache_entry_index = i; - if (i < (array->size-1)) - *desc->dir_cookie = array->array[i+1].cookie; - else - *desc->dir_cookie = array->last_cookie; - if (i == array->eof_index) { - desc->eof = 1; + *desc->dir_cookie = entry->cookie; + if (dir_decode(desc) != 0) { + desc->page_index ++; break; } + if (loop_count++ > 200) { + loop_count = 0; + schedule(); + } } - - nfs_readdir_release_array(desc->page); - cache_page_release(desc); + dir_page_release(desc); if (dentry != NULL) dput(dentry); dfprintk(DIRCACHE, "NFS: nfs_do_filldir() filling ended @ cookie %Lu; returning = %d\n", @@ -716,9 +476,12 @@ static inline int uncached_readdir(nfs_readdir_descriptor_t *desc, void *dirent, filldir_t filldir) { + struct file *file = desc->file; + struct inode *inode = file->f_path.dentry->d_inode; + struct rpc_cred *cred = nfs_file_cred(file); struct page *page = NULL; int status; - struct inode *inode = desc->file->f_path.dentry->d_inode; + unsigned long timestamp, gencount; dfprintk(DIRCACHE, "NFS: uncached_readdir() searching for cookie %Lu\n", (unsigned long long)*desc->dir_cookie); @@ -728,22 +491,38 @@ int uncached_readdir(nfs_readdir_descriptor_t *desc, void *dirent, status = -ENOMEM; goto out; } - - if (nfs_readdir_xdr_to_array(desc, page, inode) == -1) { + timestamp = jiffies; + gencount = nfs_inc_attr_generation_counter(); + status = NFS_PROTO(inode)->readdir(file->f_path.dentry, cred, + *desc->dir_cookie, page, + NFS_SERVER(inode)->dtsize, + desc->plus); + desc->page = page; + desc->ptr = kmap(page); /* matching kunmap in nfs_do_filldir */ + if (status >= 0) { + desc->timestamp = timestamp; + desc->gencount = gencount; + desc->timestamp_valid = 1; + if ((status = dir_decode(desc)) == 0) + desc->entry->prev_cookie = *desc->dir_cookie; + } else status = -EIO; + if (status < 0) goto out_release; - } - desc->page_index = 0; - desc->page = page; status = nfs_do_filldir(desc, dirent, filldir); + /* Reset read descriptor so it searches the page cache from + * the start upon the next call to readdir_search_pagecache() */ + desc->page_index = 0; + desc->entry->cookie = desc->entry->prev_cookie = 0; + desc->entry->eof = 0; out: dfprintk(DIRCACHE, "NFS: %s: returns %d\n", __func__, status); return status; out_release: - cache_page_release(desc); + dir_page_release(desc); goto out; } @@ -757,6 +536,7 @@ static int nfs_readdir(struct file *filp, void *dirent, filldir_t filldir) struct inode *inode = dentry->d_inode; nfs_readdir_descriptor_t my_desc, *desc = &my_desc; + struct nfs_entry my_entry; int res = -ENOMEM; dfprintk(FILE, "NFS: readdir(%s/%s) starting at cookie %llu\n", @@ -777,17 +557,26 @@ static int nfs_readdir(struct file *filp, void *dirent, filldir_t filldir) desc->decode = NFS_PROTO(inode)->decode_dirent; desc->plus = NFS_USE_READDIRPLUS(inode); + my_entry.cookie = my_entry.prev_cookie = 0; + my_entry.eof = 0; + my_entry.fh = nfs_alloc_fhandle(); + my_entry.fattr = nfs_alloc_fattr(); + if (my_entry.fh == NULL || my_entry.fattr == NULL) + goto out_alloc_failed; + + desc->entry = &my_entry; + nfs_block_sillyrename(dentry); res = nfs_revalidate_mapping(inode, filp->f_mapping); if (res < 0) goto out; - while (desc->eof != 1) { + while(!desc->entry->eof) { res = readdir_search_pagecache(desc); if (res == -EBADCOOKIE) { /* This means either end of directory */ - if (*desc->dir_cookie && desc->eof == 0) { + if (*desc->dir_cookie && desc->entry->cookie != *desc->dir_cookie) { /* Or that the server has 'lost' a cookie */ res = uncached_readdir(desc, dirent, filldir); if (res >= 0) @@ -799,9 +588,8 @@ static int nfs_readdir(struct file *filp, void *dirent, filldir_t filldir) if (res == -ETOOSMALL && desc->plus) { clear_bit(NFS_INO_ADVISE_RDPLUS, &NFS_I(inode)->flags); nfs_zap_caches(inode); - desc->page_index = 0; desc->plus = 0; - desc->eof = 0; + desc->entry->eof = 0; continue; } if (res < 0) @@ -817,6 +605,9 @@ static int nfs_readdir(struct file *filp, void *dirent, filldir_t filldir) nfs_unblock_sillyrename(dentry); if (res > 0) res = 0; +out_alloc_failed: + nfs_free_fattr(my_entry.fattr); + nfs_free_fhandle(my_entry.fh); dfprintk(FILE, "NFS: readdir(%s/%s) returns %d\n", dentry->d_parent->d_name.name, dentry->d_name.name, res); @@ -1238,63 +1029,10 @@ static int is_atomic_open(struct nameidata *nd) return 1; } -static struct nfs_open_context *nameidata_to_nfs_open_context(struct dentry *dentry, struct nameidata *nd) -{ - struct path path = { - .mnt = nd->path.mnt, - .dentry = dentry, - }; - struct nfs_open_context *ctx; - struct rpc_cred *cred; - fmode_t fmode = nd->intent.open.flags & (FMODE_READ | FMODE_WRITE | FMODE_EXEC); - - cred = rpc_lookup_cred(); - if (IS_ERR(cred)) - return ERR_CAST(cred); - ctx = alloc_nfs_open_context(&path, cred, fmode); - put_rpccred(cred); - if (ctx == NULL) - return ERR_PTR(-ENOMEM); - return ctx; -} - -static int do_open(struct inode *inode, struct file *filp) -{ - nfs_fscache_set_inode_cookie(inode, filp); - return 0; -} - -static int nfs_intent_set_file(struct nameidata *nd, struct nfs_open_context *ctx) -{ - struct file *filp; - int ret = 0; - - /* If the open_intent is for execute, we have an extra check to make */ - if (ctx->mode & FMODE_EXEC) { - ret = nfs_may_open(ctx->path.dentry->d_inode, - ctx->cred, - nd->intent.open.flags); - if (ret < 0) - goto out; - } - filp = lookup_instantiate_filp(nd, ctx->path.dentry, do_open); - if (IS_ERR(filp)) - ret = PTR_ERR(filp); - else - nfs_file_set_open_context(filp, ctx); -out: - put_nfs_open_context(ctx); - return ret; -} - static struct dentry *nfs_atomic_lookup(struct inode *dir, struct dentry *dentry, struct nameidata *nd) { - struct nfs_open_context *ctx; - struct iattr attr; struct dentry *res = NULL; - struct inode *inode; - int open_flags; - int err; + int error; dfprintk(VFS, "NFS: atomic_lookup(%s/%ld), %s\n", dir->i_sb->s_id, dir->i_ino, dentry->d_name.name); @@ -1316,32 +1054,13 @@ static struct dentry *nfs_atomic_lookup(struct inode *dir, struct dentry *dentry goto out; } - ctx = nameidata_to_nfs_open_context(dentry, nd); - res = ERR_CAST(ctx); - if (IS_ERR(ctx)) - goto out; - - open_flags = nd->intent.open.flags; - if (nd->flags & LOOKUP_CREATE) { - attr.ia_mode = nd->intent.open.create_mode; - attr.ia_valid = ATTR_MODE; - if (!IS_POSIXACL(dir)) - attr.ia_mode &= ~current_umask(); - } else { - open_flags &= ~(O_EXCL | O_CREAT); - attr.ia_valid = 0; - } - /* Open the file on the server */ - nfs_block_sillyrename(dentry->d_parent); - inode = NFS_PROTO(dir)->open_context(dir, ctx, open_flags, &attr); - if (IS_ERR(inode)) { - nfs_unblock_sillyrename(dentry->d_parent); - put_nfs_open_context(ctx); - switch (PTR_ERR(inode)) { + res = nfs4_atomic_open(dir, dentry, nd); + if (IS_ERR(res)) { + error = PTR_ERR(res); + switch (error) { /* Make a negative dentry */ case -ENOENT: - d_add(dentry, NULL); res = NULL; goto out; /* This turned out not to be a regular file */ @@ -1353,25 +1072,11 @@ static struct dentry *nfs_atomic_lookup(struct inode *dir, struct dentry *dentry goto no_open; /* case -EINVAL: */ default: - res = ERR_CAST(inode); goto out; } - } - res = d_add_unique(dentry, inode); - nfs_unblock_sillyrename(dentry->d_parent); - if (res != NULL) { - dput(ctx->path.dentry); - ctx->path.dentry = dget(res); + } else if (res != NULL) dentry = res; - } - err = nfs_intent_set_file(nd, ctx); - if (err < 0) { - if (res != NULL) - dput(res); - return ERR_PTR(err); - } out: - nfs_set_verifier(dentry, nfs_save_change_attribute(dir)); return res; no_open: return nfs_lookup(dir, dentry, nd); @@ -1382,15 +1087,12 @@ static int nfs_open_revalidate(struct dentry *dentry, struct nameidata *nd) struct dentry *parent = NULL; struct inode *inode = dentry->d_inode; struct inode *dir; - struct nfs_open_context *ctx; int openflags, ret = 0; if (!is_atomic_open(nd) || d_mountpoint(dentry)) goto no_open; - parent = dget_parent(dentry); dir = parent->d_inode; - /* We can't create new files in nfs_open_revalidate(), so we * optimize away revalidation of negative dentries. */ @@ -1410,95 +1112,98 @@ static int nfs_open_revalidate(struct dentry *dentry, struct nameidata *nd) /* We can't create new files, or truncate existing ones here */ openflags &= ~(O_CREAT|O_EXCL|O_TRUNC); - ctx = nameidata_to_nfs_open_context(dentry, nd); - ret = PTR_ERR(ctx); - if (IS_ERR(ctx)) - goto out; /* * Note: we're not holding inode->i_mutex and so may be racing with * operations that change the directory. We therefore save the * change attribute *before* we do the RPC call. */ - inode = NFS_PROTO(dir)->open_context(dir, ctx, openflags, NULL); - if (IS_ERR(inode)) { - ret = PTR_ERR(inode); - switch (ret) { - case -EPERM: - case -EACCES: - case -EDQUOT: - case -ENOSPC: - case -EROFS: - goto out_put_ctx; - default: - goto out_drop; - } - } - iput(inode); - if (inode != dentry->d_inode) - goto out_drop; - - nfs_set_verifier(dentry, nfs_save_change_attribute(dir)); - ret = nfs_intent_set_file(nd, ctx); - if (ret >= 0) - ret = 1; + ret = nfs4_open_revalidate(dir, dentry, openflags, nd); out: dput(parent); + if (!ret) + d_drop(dentry); return ret; -out_drop: - d_drop(dentry); - ret = 0; -out_put_ctx: - put_nfs_open_context(ctx); - goto out; - no_open_dput: dput(parent); no_open: return nfs_lookup_revalidate(dentry, nd); } +#endif /* CONFIG_NFSV4 */ -static int nfs_open_create(struct inode *dir, struct dentry *dentry, int mode, - struct nameidata *nd) +static struct dentry *nfs_readdir_lookup(nfs_readdir_descriptor_t *desc) { - struct nfs_open_context *ctx = NULL; - struct iattr attr; - int error; - int open_flags = 0; - - dfprintk(VFS, "NFS: create(%s/%ld), %s\n", - dir->i_sb->s_id, dir->i_ino, dentry->d_name.name); + struct dentry *parent = desc->file->f_path.dentry; + struct inode *dir = parent->d_inode; + struct nfs_entry *entry = desc->entry; + struct dentry *dentry, *alias; + struct qstr name = { + .name = entry->name, + .len = entry->len, + }; + struct inode *inode; + unsigned long verf = nfs_save_change_attribute(dir); - attr.ia_mode = mode; - attr.ia_valid = ATTR_MODE; + switch (name.len) { + case 2: + if (name.name[0] == '.' && name.name[1] == '.') + return dget_parent(parent); + break; + case 1: + if (name.name[0] == '.') + return dget(parent); + } - if ((nd->flags & LOOKUP_CREATE) != 0) { - open_flags = nd->intent.open.flags; + spin_lock(&dir->i_lock); + if (NFS_I(dir)->cache_validity & NFS_INO_INVALID_DATA) { + spin_unlock(&dir->i_lock); + return NULL; + } + spin_unlock(&dir->i_lock); - ctx = nameidata_to_nfs_open_context(dentry, nd); - error = PTR_ERR(ctx); - if (IS_ERR(ctx)) - goto out_err_drop; + name.hash = full_name_hash(name.name, name.len); + dentry = d_lookup(parent, &name); + if (dentry != NULL) { + /* Is this a positive dentry that matches the readdir info? */ + if (dentry->d_inode != NULL && + (NFS_FILEID(dentry->d_inode) == entry->ino || + d_mountpoint(dentry))) { + if (!desc->plus || entry->fh->size == 0) + return dentry; + if (nfs_compare_fh(NFS_FH(dentry->d_inode), + entry->fh) == 0) + goto out_renew; + } + /* No, so d_drop to allow one to be created */ + d_drop(dentry); + dput(dentry); + } + if (!desc->plus || !(entry->fattr->valid & NFS_ATTR_FATTR)) + return NULL; + if (name.len > NFS_SERVER(dir)->namelen) + return NULL; + /* Note: caller is already holding the dir->i_mutex! */ + dentry = d_alloc(parent, &name); + if (dentry == NULL) + return NULL; + dentry->d_op = NFS_PROTO(dir)->dentry_ops; + inode = nfs_fhget(dentry->d_sb, entry->fh, entry->fattr); + if (IS_ERR(inode)) { + dput(dentry); + return NULL; } - error = NFS_PROTO(dir)->create(dir, dentry, &attr, open_flags, ctx); - if (error != 0) - goto out_put_ctx; - if (ctx != NULL) { - error = nfs_intent_set_file(nd, ctx); - if (error < 0) - goto out_err; + alias = d_materialise_unique(dentry, inode); + if (alias != NULL) { + dput(dentry); + if (IS_ERR(alias)) + return NULL; + dentry = alias; } - return 0; -out_put_ctx: - if (ctx != NULL) - put_nfs_open_context(ctx); -out_err_drop: - d_drop(dentry); -out_err: - return error; -} -#endif /* CONFIG_NFSV4 */ +out_renew: + nfs_set_verifier(dentry, verf); + return dentry; +} /* * Code common to create, mkdir, and mknod. @@ -1553,6 +1258,7 @@ static int nfs_create(struct inode *dir, struct dentry *dentry, int mode, { struct iattr attr; int error; + int open_flags = 0; dfprintk(VFS, "NFS: create(%s/%ld), %s\n", dir->i_sb->s_id, dir->i_ino, dentry->d_name.name); @@ -1560,7 +1266,10 @@ static int nfs_create(struct inode *dir, struct dentry *dentry, int mode, attr.ia_mode = mode; attr.ia_valid = ATTR_MODE; - error = NFS_PROTO(dir)->create(dir, dentry, &attr, 0, NULL); + if ((nd->flags & LOOKUP_CREATE) != 0) + open_flags = nd->intent.open.flags; + + error = NFS_PROTO(dir)->create(dir, dentry, &attr, open_flags, nd); if (error != 0) goto out_err; return 0; @@ -1642,6 +1351,76 @@ static int nfs_rmdir(struct inode *dir, struct dentry *dentry) return error; } +static int nfs_sillyrename(struct inode *dir, struct dentry *dentry) +{ + static unsigned int sillycounter; + const int fileidsize = sizeof(NFS_FILEID(dentry->d_inode))*2; + const int countersize = sizeof(sillycounter)*2; + const int slen = sizeof(".nfs")+fileidsize+countersize-1; + char silly[slen+1]; + struct qstr qsilly; + struct dentry *sdentry; + int error = -EIO; + + dfprintk(VFS, "NFS: silly-rename(%s/%s, ct=%d)\n", + dentry->d_parent->d_name.name, dentry->d_name.name, + atomic_read(&dentry->d_count)); + nfs_inc_stats(dir, NFSIOS_SILLYRENAME); + + /* + * We don't allow a dentry to be silly-renamed twice. + */ + error = -EBUSY; + if (dentry->d_flags & DCACHE_NFSFS_RENAMED) + goto out; + + sprintf(silly, ".nfs%*.*Lx", + fileidsize, fileidsize, + (unsigned long long)NFS_FILEID(dentry->d_inode)); + + /* Return delegation in anticipation of the rename */ + nfs_inode_return_delegation(dentry->d_inode); + + sdentry = NULL; + do { + char *suffix = silly + slen - countersize; + + dput(sdentry); + sillycounter++; + sprintf(suffix, "%*.*x", countersize, countersize, sillycounter); + + dfprintk(VFS, "NFS: trying to rename %s to %s\n", + dentry->d_name.name, silly); + + sdentry = lookup_one_len(silly, dentry->d_parent, slen); + /* + * N.B. Better to return EBUSY here ... it could be + * dangerous to delete the file while it's in use. + */ + if (IS_ERR(sdentry)) + goto out; + } while(sdentry->d_inode != NULL); /* need negative lookup */ + + qsilly.name = silly; + qsilly.len = strlen(silly); + if (dentry->d_inode) { + error = NFS_PROTO(dir)->rename(dir, &dentry->d_name, + dir, &qsilly); + nfs_mark_for_revalidate(dentry->d_inode); + } else + error = NFS_PROTO(dir)->rename(dir, &dentry->d_name, + dir, &qsilly); + if (!error) { + nfs_set_verifier(dentry, nfs_save_change_attribute(dir)); + d_move(dentry, sdentry); + error = nfs_async_unlink(dir, dentry); + /* If we return 0 we don't unlink */ + } + dput(sdentry); +out: + return error; +} + /* * Remove a file after making sure there are no pending writes, * and after checking that the file has only one user. @@ -1932,14 +1711,14 @@ static void nfs_access_free_list(struct list_head *head) int nfs_access_cache_shrinker(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) { LIST_HEAD(head); - struct nfs_inode *nfsi, *next; + struct nfs_inode *nfsi; struct nfs_access_entry *cache; if ((gfp_mask & GFP_KERNEL) != GFP_KERNEL) return (nr_to_scan == 0) ? 0 : -1; spin_lock(&nfs_access_lru_lock); - list_for_each_entry_safe(nfsi, next, &nfs_access_lru_list, access_cache_inode_lru) { + list_for_each_entry(nfsi, &nfs_access_lru_list, access_cache_inode_lru) { struct inode *inode; if (nr_to_scan-- == 0) diff --git a/trunk/fs/nfs/file.c b/trunk/fs/nfs/file.c index e18c31e08a28..05bf3c0dc751 100644 --- a/trunk/fs/nfs/file.c +++ b/trunk/fs/nfs/file.c @@ -551,7 +551,7 @@ static int nfs_vm_page_mkwrite(struct vm_area_struct *vma, struct vm_fault *vmf) struct file *filp = vma->vm_file; struct dentry *dentry = filp->f_path.dentry; unsigned pagelen; - int ret = VM_FAULT_NOPAGE; + int ret = -EINVAL; struct address_space *mapping; dfprintk(PAGECACHE, "NFS: vm_page_mkwrite(%s/%s(%ld), offset %lld)\n", @@ -567,20 +567,21 @@ static int nfs_vm_page_mkwrite(struct vm_area_struct *vma, struct vm_fault *vmf) if (mapping != dentry->d_inode->i_mapping) goto out_unlock; + ret = 0; pagelen = nfs_page_length(page); if (pagelen == 0) goto out_unlock; - ret = VM_FAULT_LOCKED; - if (nfs_flush_incompatible(filp, page) == 0 && - nfs_updatepage(filp, page, 0, pagelen) == 0) - goto out; + ret = nfs_flush_incompatible(filp, page); + if (ret != 0) + goto out_unlock; - ret = VM_FAULT_SIGBUS; + ret = nfs_updatepage(filp, page, 0, pagelen); out_unlock: + if (!ret) + return VM_FAULT_LOCKED; unlock_page(page); -out: - return ret; + return VM_FAULT_SIGBUS; } static const struct vm_operations_struct nfs_file_vm_ops = { @@ -683,8 +684,7 @@ static ssize_t nfs_file_splice_write(struct pipe_inode_info *pipe, return ret; } -static int -do_getlk(struct file *filp, int cmd, struct file_lock *fl, int is_local) +static int do_getlk(struct file *filp, int cmd, struct file_lock *fl) { struct inode *inode = filp->f_mapping->host; int status = 0; @@ -699,7 +699,7 @@ do_getlk(struct file *filp, int cmd, struct file_lock *fl, int is_local) if (nfs_have_delegation(inode, FMODE_READ)) goto out_noconflict; - if (is_local) + if (NFS_SERVER(inode)->flags & NFS_MOUNT_NONLM) goto out_noconflict; status = NFS_PROTO(inode)->lock(filp, cmd, fl); @@ -726,8 +726,7 @@ static int do_vfs_lock(struct file *file, struct file_lock *fl) return res; } -static int -do_unlk(struct file *filp, int cmd, struct file_lock *fl, int is_local) +static int do_unlk(struct file *filp, int cmd, struct file_lock *fl) { struct inode *inode = filp->f_mapping->host; int status; @@ -742,24 +741,15 @@ do_unlk(struct file *filp, int cmd, struct file_lock *fl, int is_local) * If we're signalled while cleaning up locks on process exit, we * still need to complete the unlock. */ - /* - * Use local locking if mounted with "-onolock" or with appropriate - * "-olocal_lock=" - */ - if (!is_local) + /* Use local locking if mounted with "-onolock" */ + if (!(NFS_SERVER(inode)->flags & NFS_MOUNT_NONLM)) status = NFS_PROTO(inode)->lock(filp, cmd, fl); else status = do_vfs_lock(filp, fl); return status; } -static int -is_time_granular(struct timespec *ts) { - return ((ts->tv_sec == 0) && (ts->tv_nsec <= 1000)); -} - -static int -do_setlk(struct file *filp, int cmd, struct file_lock *fl, int is_local) +static int do_setlk(struct file *filp, int cmd, struct file_lock *fl) { struct inode *inode = filp->f_mapping->host; int status; @@ -772,31 +762,20 @@ do_setlk(struct file *filp, int cmd, struct file_lock *fl, int is_local) if (status != 0) goto out; - /* - * Use local locking if mounted with "-onolock" or with appropriate - * "-olocal_lock=" - */ - if (!is_local) + /* Use local locking if mounted with "-onolock" */ + if (!(NFS_SERVER(inode)->flags & NFS_MOUNT_NONLM)) status = NFS_PROTO(inode)->lock(filp, cmd, fl); else status = do_vfs_lock(filp, fl); if (status < 0) goto out; - /* - * Revalidate the cache if the server has time stamps granular - * enough to detect subsecond changes. Otherwise, clear the - * cache to prevent missing any changes. - * + * Make sure we clear the cache whenever we try to get the lock. * This makes locking act as a cache coherency point. */ nfs_sync_mapping(filp->f_mapping); - if (!nfs_have_delegation(inode, FMODE_READ)) { - if (is_time_granular(&NFS_SERVER(inode)->time_delta)) - __nfs_revalidate_inode(NFS_SERVER(inode), inode); - else - nfs_zap_caches(inode); - } + if (!nfs_have_delegation(inode, FMODE_READ)) + nfs_zap_caches(inode); out: return status; } @@ -808,7 +787,6 @@ static int nfs_lock(struct file *filp, int cmd, struct file_lock *fl) { struct inode *inode = filp->f_mapping->host; int ret = -ENOLCK; - int is_local = 0; dprintk("NFS: lock(%s/%s, t=%x, fl=%x, r=%lld:%lld)\n", filp->f_path.dentry->d_parent->d_name.name, @@ -822,9 +800,6 @@ static int nfs_lock(struct file *filp, int cmd, struct file_lock *fl) if (__mandatory_lock(inode) && fl->fl_type != F_UNLCK) goto out_err; - if (NFS_SERVER(inode)->flags & NFS_MOUNT_LOCAL_FCNTL) - is_local = 1; - if (NFS_PROTO(inode)->lock_check_bounds != NULL) { ret = NFS_PROTO(inode)->lock_check_bounds(fl); if (ret < 0) @@ -832,11 +807,11 @@ static int nfs_lock(struct file *filp, int cmd, struct file_lock *fl) } if (IS_GETLK(cmd)) - ret = do_getlk(filp, cmd, fl, is_local); + ret = do_getlk(filp, cmd, fl); else if (fl->fl_type == F_UNLCK) - ret = do_unlk(filp, cmd, fl, is_local); + ret = do_unlk(filp, cmd, fl); else - ret = do_setlk(filp, cmd, fl, is_local); + ret = do_setlk(filp, cmd, fl); out_err: return ret; } @@ -846,9 +821,6 @@ static int nfs_lock(struct file *filp, int cmd, struct file_lock *fl) */ static int nfs_flock(struct file *filp, int cmd, struct file_lock *fl) { - struct inode *inode = filp->f_mapping->host; - int is_local = 0; - dprintk("NFS: flock(%s/%s, t=%x, fl=%x)\n", filp->f_path.dentry->d_parent->d_name.name, filp->f_path.dentry->d_name.name, @@ -857,17 +829,14 @@ static int nfs_flock(struct file *filp, int cmd, struct file_lock *fl) if (!(fl->fl_flags & FL_FLOCK)) return -ENOLCK; - if (NFS_SERVER(inode)->flags & NFS_MOUNT_LOCAL_FLOCK) - is_local = 1; - /* We're simulating flock() locks using posix locks on the server */ fl->fl_owner = (fl_owner_t)filp; fl->fl_start = 0; fl->fl_end = OFFSET_MAX; if (fl->fl_type == F_UNLCK) - return do_unlk(filp, cmd, fl, is_local); - return do_setlk(filp, cmd, fl, is_local); + return do_unlk(filp, cmd, fl); + return do_setlk(filp, cmd, fl); } /* diff --git a/trunk/fs/nfs/idmap.c b/trunk/fs/nfs/idmap.c index dec47ed8b6b9..21a84d45916f 100644 --- a/trunk/fs/nfs/idmap.c +++ b/trunk/fs/nfs/idmap.c @@ -34,212 +34,6 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifdef CONFIG_NFS_USE_NEW_IDMAPPER - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#define NFS_UINT_MAXLEN 11 - -const struct cred *id_resolver_cache; - -struct key_type key_type_id_resolver = { - .name = "id_resolver", - .instantiate = user_instantiate, - .match = user_match, - .revoke = user_revoke, - .destroy = user_destroy, - .describe = user_describe, - .read = user_read, -}; - -int nfs_idmap_init(void) -{ - struct cred *cred; - struct key *keyring; - int ret = 0; - - printk(KERN_NOTICE "Registering the %s key type\n", key_type_id_resolver.name); - - cred = prepare_kernel_cred(NULL); - if (!cred) - return -ENOMEM; - - keyring = key_alloc(&key_type_keyring, ".id_resolver", 0, 0, cred, - (KEY_POS_ALL & ~KEY_POS_SETATTR) | - KEY_USR_VIEW | KEY_USR_READ, - KEY_ALLOC_NOT_IN_QUOTA); - if (IS_ERR(keyring)) { - ret = PTR_ERR(keyring); - goto failed_put_cred; - } - - ret = key_instantiate_and_link(keyring, NULL, 0, NULL, NULL); - if (ret < 0) - goto failed_put_key; - - ret = register_key_type(&key_type_id_resolver); - if (ret < 0) - goto failed_put_key; - - cred->thread_keyring = keyring; - cred->jit_keyring = KEY_REQKEY_DEFL_THREAD_KEYRING; - id_resolver_cache = cred; - return 0; - -failed_put_key: - key_put(keyring); -failed_put_cred: - put_cred(cred); - return ret; -} - -void nfs_idmap_quit(void) -{ - key_revoke(id_resolver_cache->thread_keyring); - unregister_key_type(&key_type_id_resolver); - put_cred(id_resolver_cache); -} - -/* - * Assemble the description to pass to request_key() - * This function will allocate a new string and update dest to point - * at it. The caller is responsible for freeing dest. - * - * On error 0 is returned. Otherwise, the length of dest is returned. - */ -static ssize_t nfs_idmap_get_desc(const char *name, size_t namelen, - const char *type, size_t typelen, char **desc) -{ - char *cp; - size_t desclen = typelen + namelen + 2; - - *desc = kmalloc(desclen, GFP_KERNEL); - if (!desc) - return -ENOMEM; - - cp = *desc; - memcpy(cp, type, typelen); - cp += typelen; - *cp++ = ':'; - - memcpy(cp, name, namelen); - cp += namelen; - *cp = '\0'; - return desclen; -} - -static ssize_t nfs_idmap_request_key(const char *name, size_t namelen, - const char *type, void *data, size_t data_size) -{ - const struct cred *saved_cred; - struct key *rkey; - char *desc; - struct user_key_payload *payload; - ssize_t ret; - - ret = nfs_idmap_get_desc(name, namelen, type, strlen(type), &desc); - if (ret <= 0) - goto out; - - saved_cred = override_creds(id_resolver_cache); - rkey = request_key(&key_type_id_resolver, desc, ""); - revert_creds(saved_cred); - kfree(desc); - if (IS_ERR(rkey)) { - ret = PTR_ERR(rkey); - goto out; - } - - rcu_read_lock(); - rkey->perm |= KEY_USR_VIEW; - - ret = key_validate(rkey); - if (ret < 0) - goto out_up; - - payload = rcu_dereference(rkey->payload.data); - if (IS_ERR_OR_NULL(payload)) { - ret = PTR_ERR(payload); - goto out_up; - } - - ret = payload->datalen; - if (ret > 0 && ret <= data_size) - memcpy(data, payload->data, ret); - else - ret = -EINVAL; - -out_up: - rcu_read_unlock(); - key_put(rkey); -out: - return ret; -} - - -/* ID -> Name */ -static ssize_t nfs_idmap_lookup_name(__u32 id, const char *type, char *buf, size_t buflen) -{ - char id_str[NFS_UINT_MAXLEN]; - int id_len; - ssize_t ret; - - id_len = snprintf(id_str, sizeof(id_str), "%u", id); - ret = nfs_idmap_request_key(id_str, id_len, type, buf, buflen); - if (ret < 0) - return -EINVAL; - return ret; -} - -/* Name -> ID */ -static int nfs_idmap_lookup_id(const char *name, size_t namelen, - const char *type, __u32 *id) -{ - char id_str[NFS_UINT_MAXLEN]; - long id_long; - ssize_t data_size; - int ret = 0; - - data_size = nfs_idmap_request_key(name, namelen, type, id_str, NFS_UINT_MAXLEN); - if (data_size <= 0) { - ret = -EINVAL; - } else { - ret = strict_strtol(id_str, 10, &id_long); - *id = (__u32)id_long; - } - return ret; -} - -int nfs_map_name_to_uid(struct nfs_client *clp, const char *name, size_t namelen, __u32 *uid) -{ - return nfs_idmap_lookup_id(name, namelen, "uid", uid); -} - -int nfs_map_group_to_gid(struct nfs_client *clp, const char *name, size_t namelen, __u32 *gid) -{ - return nfs_idmap_lookup_id(name, namelen, "gid", gid); -} - -int nfs_map_uid_to_name(struct nfs_client *clp, __u32 uid, char *buf, size_t buflen) -{ - return nfs_idmap_lookup_name(uid, "user", buf, buflen); -} -int nfs_map_gid_to_group(struct nfs_client *clp, __u32 gid, char *buf, size_t buflen) -{ - return nfs_idmap_lookup_name(gid, "group", buf, buflen); -} - -#else /* CONFIG_NFS_USE_IDMAPPER not defined */ - #include #include #include @@ -709,17 +503,16 @@ int nfs_map_group_to_gid(struct nfs_client *clp, const char *name, size_t namele return nfs_idmap_id(idmap, &idmap->idmap_group_hash, name, namelen, uid); } -int nfs_map_uid_to_name(struct nfs_client *clp, __u32 uid, char *buf, size_t buflen) +int nfs_map_uid_to_name(struct nfs_client *clp, __u32 uid, char *buf) { struct idmap *idmap = clp->cl_idmap; return nfs_idmap_name(idmap, &idmap->idmap_user_hash, uid, buf); } -int nfs_map_gid_to_group(struct nfs_client *clp, __u32 uid, char *buf, size_t buflen) +int nfs_map_gid_to_group(struct nfs_client *clp, __u32 uid, char *buf) { struct idmap *idmap = clp->cl_idmap; return nfs_idmap_name(idmap, &idmap->idmap_group_hash, uid, buf); } -#endif /* CONFIG_NFS_USE_NEW_IDMAPPER */ diff --git a/trunk/fs/nfs/inode.c b/trunk/fs/nfs/inode.c index 6eec28656415..7d2d6c72aa78 100644 --- a/trunk/fs/nfs/inode.c +++ b/trunk/fs/nfs/inode.c @@ -234,6 +234,9 @@ nfs_init_locked(struct inode *inode, void *opaque) return 0; } +/* Don't use READDIRPLUS on directories that we believe are too large */ +#define NFS_LIMIT_READDIRPLUS (8*PAGE_SIZE) + /* * This is our front-end to iget that looks up inodes by file handle * instead of inode number. @@ -288,7 +291,8 @@ nfs_fhget(struct super_block *sb, struct nfs_fh *fh, struct nfs_fattr *fattr) } else if (S_ISDIR(inode->i_mode)) { inode->i_op = NFS_SB(sb)->nfs_client->rpc_ops->dir_inode_ops; inode->i_fop = &nfs_dir_operations; - if (nfs_server_capable(inode, NFS_CAP_READDIRPLUS)) + if (nfs_server_capable(inode, NFS_CAP_READDIRPLUS) + && fattr->size <= NFS_LIMIT_READDIRPLUS) set_bit(NFS_INO_ADVISE_RDPLUS, &NFS_I(inode)->flags); /* Deal with crossing mountpoints */ if ((fattr->valid & NFS_ATTR_FATTR_FSID) @@ -619,7 +623,7 @@ void nfs_close_context(struct nfs_open_context *ctx, int is_sync) nfs_revalidate_inode(server, inode); } -struct nfs_open_context *alloc_nfs_open_context(struct path *path, struct rpc_cred *cred, fmode_t f_mode) +static struct nfs_open_context *alloc_nfs_open_context(struct path *path, struct rpc_cred *cred) { struct nfs_open_context *ctx; @@ -629,13 +633,11 @@ struct nfs_open_context *alloc_nfs_open_context(struct path *path, struct rpc_cr path_get(&ctx->path); ctx->cred = get_rpccred(cred); ctx->state = NULL; - ctx->mode = f_mode; ctx->flags = 0; ctx->error = 0; ctx->dir_cookie = 0; nfs_init_lock_context(&ctx->lock_context); ctx->lock_context.open_context = ctx; - INIT_LIST_HEAD(&ctx->list); } return ctx; } @@ -651,15 +653,11 @@ static void __put_nfs_open_context(struct nfs_open_context *ctx, int is_sync) { struct inode *inode = ctx->path.dentry->d_inode; - if (!list_empty(&ctx->list)) { - if (!atomic_dec_and_lock(&ctx->lock_context.count, &inode->i_lock)) - return; - list_del(&ctx->list); - spin_unlock(&inode->i_lock); - } else if (!atomic_dec_and_test(&ctx->lock_context.count)) + if (!atomic_dec_and_lock(&ctx->lock_context.count, &inode->i_lock)) return; - if (inode != NULL) - NFS_PROTO(inode)->close_context(ctx, is_sync); + list_del(&ctx->list); + spin_unlock(&inode->i_lock); + NFS_PROTO(inode)->close_context(ctx, is_sync); if (ctx->cred != NULL) put_rpccred(ctx->cred); path_put(&ctx->path); @@ -675,7 +673,7 @@ void put_nfs_open_context(struct nfs_open_context *ctx) * Ensure that mmap has a recent RPC credential for use when writing out * shared pages */ -void nfs_file_set_open_context(struct file *filp, struct nfs_open_context *ctx) +static void nfs_file_set_open_context(struct file *filp, struct nfs_open_context *ctx) { struct inode *inode = filp->f_path.dentry->d_inode; struct nfs_inode *nfsi = NFS_I(inode); @@ -732,10 +730,11 @@ int nfs_open(struct inode *inode, struct file *filp) cred = rpc_lookup_cred(); if (IS_ERR(cred)) return PTR_ERR(cred); - ctx = alloc_nfs_open_context(&filp->f_path, cred, filp->f_mode); + ctx = alloc_nfs_open_context(&filp->f_path, cred); put_rpccred(cred); if (ctx == NULL) return -ENOMEM; + ctx->mode = filp->f_mode; nfs_file_set_open_context(filp, ctx); put_nfs_open_context(ctx); nfs_fscache_set_inode_cookie(inode, filp); @@ -1494,7 +1493,7 @@ static int nfsiod_start(void) { struct workqueue_struct *wq; dprintk("RPC: creating workqueue nfsiod\n"); - wq = alloc_workqueue("nfsiod", WQ_RESCUER, 0); + wq = create_singlethread_workqueue("nfsiod"); if (wq == NULL) return -ENOMEM; nfsiod_workqueue = wq; @@ -1522,10 +1521,6 @@ static int __init init_nfs_fs(void) { int err; - err = nfs_idmap_init(); - if (err < 0) - goto out9; - err = nfs_dns_resolver_init(); if (err < 0) goto out8; @@ -1590,8 +1585,6 @@ static int __init init_nfs_fs(void) out7: nfs_dns_resolver_destroy(); out8: - nfs_idmap_quit(); -out9: return err; } @@ -1604,7 +1597,6 @@ static void __exit exit_nfs_fs(void) nfs_destroy_nfspagecache(); nfs_fscache_unregister(); nfs_dns_resolver_destroy(); - nfs_idmap_quit(); #ifdef CONFIG_PROC_FS rpc_proc_unregister("nfs"); #endif diff --git a/trunk/fs/nfs/internal.h b/trunk/fs/nfs/internal.h index db08ff3ff454..c961bc92c107 100644 --- a/trunk/fs/nfs/internal.h +++ b/trunk/fs/nfs/internal.h @@ -62,12 +62,6 @@ struct nfs_clone_mount { */ #define NFS_UNSPEC_PORT (-1) -/* - * Maximum number of pages that readdir can use for creating - * a vmapped array of pages. - */ -#define NFS_MAX_READDIR_PAGES 8 - /* * In-kernel mount arguments */ @@ -187,15 +181,15 @@ extern void nfs_destroy_directcache(void); /* nfs2xdr.c */ extern int nfs_stat_to_errno(int); extern struct rpc_procinfo nfs_procedures[]; -extern __be32 *nfs_decode_dirent(struct xdr_stream *, struct nfs_entry *, struct nfs_server *, int); +extern __be32 * nfs_decode_dirent(__be32 *, struct nfs_entry *, int); /* nfs3xdr.c */ extern struct rpc_procinfo nfs3_procedures[]; -extern __be32 *nfs3_decode_dirent(struct xdr_stream *, struct nfs_entry *, struct nfs_server *, int); +extern __be32 *nfs3_decode_dirent(__be32 *, struct nfs_entry *, int); /* nfs4xdr.c */ #ifdef CONFIG_NFS_V4 -extern __be32 *nfs4_decode_dirent(struct xdr_stream *, struct nfs_entry *, struct nfs_server *, int); +extern __be32 *nfs4_decode_dirent(__be32 *p, struct nfs_entry *entry, int plus); #endif #ifdef CONFIG_NFS_V4_1 extern const u32 nfs41_maxread_overhead; diff --git a/trunk/fs/nfs/mount_clnt.c b/trunk/fs/nfs/mount_clnt.c index d610203d95c6..59047f8d7d72 100644 --- a/trunk/fs/nfs/mount_clnt.c +++ b/trunk/fs/nfs/mount_clnt.c @@ -436,7 +436,7 @@ static int decode_auth_flavors(struct xdr_stream *xdr, struct mountres *res) for (i = 0; i < entries; i++) { flavors[i] = ntohl(*p++); - dprintk("NFS: auth flavor[%u]: %d\n", i, flavors[i]); + dprintk("NFS:\tflavor %u: %d\n", i, flavors[i]); } *count = i; diff --git a/trunk/fs/nfs/nfs2xdr.c b/trunk/fs/nfs/nfs2xdr.c index e6bf45710cc7..db8846a0e82e 100644 --- a/trunk/fs/nfs/nfs2xdr.c +++ b/trunk/fs/nfs/nfs2xdr.c @@ -337,10 +337,10 @@ nfs_xdr_createargs(struct rpc_rqst *req, __be32 *p, struct nfs_createargs *args) static int nfs_xdr_renameargs(struct rpc_rqst *req, __be32 *p, struct nfs_renameargs *args) { - p = xdr_encode_fhandle(p, args->old_dir); - p = xdr_encode_array(p, args->old_name->name, args->old_name->len); - p = xdr_encode_fhandle(p, args->new_dir); - p = xdr_encode_array(p, args->new_name->name, args->new_name->len); + p = xdr_encode_fhandle(p, args->fromfh); + p = xdr_encode_array(p, args->fromname, args->fromlen); + p = xdr_encode_fhandle(p, args->tofh); + p = xdr_encode_array(p, args->toname, args->tolen); req->rq_slen = xdr_adjust_iovec(req->rq_svec, p); return 0; } @@ -423,7 +423,9 @@ nfs_xdr_readdirres(struct rpc_rqst *req, __be32 *p, void *dummy) struct page **page; size_t hdrlen; unsigned int pglen, recvd; + u32 len; int status, nr = 0; + __be32 *end, *entry, *kaddr; if ((status = ntohl(*p++))) return nfs_stat_to_errno(status); @@ -443,59 +445,80 @@ nfs_xdr_readdirres(struct rpc_rqst *req, __be32 *p, void *dummy) if (pglen > recvd) pglen = recvd; page = rcvbuf->pages; - return nr; -} + kaddr = p = kmap_atomic(*page, KM_USER0); + end = (__be32 *)((char *)p + pglen); + entry = p; + + /* Make sure the packet actually has a value_follows and EOF entry */ + if ((entry + 1) > end) + goto short_pkt; + + for (; *p++; nr++) { + if (p + 2 > end) + goto short_pkt; + p++; /* fileid */ + len = ntohl(*p++); + p += XDR_QUADLEN(len) + 1; /* name plus cookie */ + if (len > NFS2_MAXNAMLEN) { + dprintk("NFS: giant filename in readdir (len 0x%x)!\n", + len); + goto err_unmap; + } + if (p + 2 > end) + goto short_pkt; + entry = p; + } -static void print_overflow_msg(const char *func, const struct xdr_stream *xdr) -{ - dprintk("nfs: %s: prematurely hit end of receive buffer. " - "Remaining buffer length is %tu words.\n", - func, xdr->end - xdr->p); + /* + * Apparently some server sends responses that are a valid size, but + * contain no entries, and have value_follows==0 and EOF==0. For + * those, just set the EOF marker. + */ + if (!nr && entry[1] == 0) { + dprintk("NFS: readdir reply truncated!\n"); + entry[1] = 1; + } + out: + kunmap_atomic(kaddr, KM_USER0); + return nr; + short_pkt: + /* + * When we get a short packet there are 2 possibilities. We can + * return an error, or fix up the response to look like a valid + * response and return what we have so far. If there are no + * entries and the packet was short, then return -EIO. If there + * are valid entries in the response, return them and pretend that + * the call was successful, but incomplete. The caller can retry the + * readdir starting at the last cookie. + */ + entry[0] = entry[1] = 0; + if (!nr) + nr = -errno_NFSERR_IO; + goto out; +err_unmap: + nr = -errno_NFSERR_IO; + goto out; } __be32 * -nfs_decode_dirent(struct xdr_stream *xdr, struct nfs_entry *entry, struct nfs_server *server, int plus) +nfs_decode_dirent(__be32 *p, struct nfs_entry *entry, int plus) { - __be32 *p; - p = xdr_inline_decode(xdr, 4); - if (unlikely(!p)) - goto out_overflow; - if (!ntohl(*p++)) { - p = xdr_inline_decode(xdr, 4); - if (unlikely(!p)) - goto out_overflow; - if (!ntohl(*p++)) + if (!*p++) { + if (!*p) return ERR_PTR(-EAGAIN); entry->eof = 1; return ERR_PTR(-EBADCOOKIE); } - p = xdr_inline_decode(xdr, 8); - if (unlikely(!p)) - goto out_overflow; - entry->ino = ntohl(*p++); entry->len = ntohl(*p++); - - p = xdr_inline_decode(xdr, entry->len + 4); - if (unlikely(!p)) - goto out_overflow; entry->name = (const char *) p; p += XDR_QUADLEN(entry->len); entry->prev_cookie = entry->cookie; entry->cookie = ntohl(*p++); - - p = xdr_inline_peek(xdr, 8); - if (p != NULL) - entry->eof = !p[0] && p[1]; - else - entry->eof = 0; + entry->eof = !p[0] && p[1]; return p; - -out_overflow: - print_overflow_msg(__func__, xdr); - return ERR_PTR(-EIO); } /* @@ -573,6 +596,7 @@ nfs_xdr_readlinkres(struct rpc_rqst *req, __be32 *p, void *dummy) struct kvec *iov = rcvbuf->head; size_t hdrlen; u32 len, recvd; + char *kaddr; int status; if ((status = ntohl(*p++))) @@ -599,7 +623,10 @@ nfs_xdr_readlinkres(struct rpc_rqst *req, __be32 *p, void *dummy) return -EIO; } - xdr_terminate_string(rcvbuf, len); + /* NULL terminate the string we got */ + kaddr = (char *)kmap_atomic(rcvbuf->pages[0], KM_USER0); + kaddr[len+rcvbuf->page_base] = '\0'; + kunmap_atomic(kaddr, KM_USER0); return 0; } diff --git a/trunk/fs/nfs/nfs3proc.c b/trunk/fs/nfs/nfs3proc.c index ce939c062a52..fabb4f2849a1 100644 --- a/trunk/fs/nfs/nfs3proc.c +++ b/trunk/fs/nfs/nfs3proc.c @@ -313,7 +313,7 @@ static void nfs3_free_createdata(struct nfs3_createdata *data) */ static int nfs3_proc_create(struct inode *dir, struct dentry *dentry, struct iattr *sattr, - int flags, struct nfs_open_context *ctx) + int flags, struct nameidata *nd) { struct nfs3_createdata *data; mode_t mode = sattr->ia_mode; @@ -438,38 +438,19 @@ nfs3_proc_unlink_done(struct rpc_task *task, struct inode *dir) return 1; } -static void -nfs3_proc_rename_setup(struct rpc_message *msg, struct inode *dir) -{ - msg->rpc_proc = &nfs3_procedures[NFS3PROC_RENAME]; -} - -static int -nfs3_proc_rename_done(struct rpc_task *task, struct inode *old_dir, - struct inode *new_dir) -{ - struct nfs_renameres *res; - - if (nfs3_async_handle_jukebox(task, old_dir)) - return 0; - res = task->tk_msg.rpc_resp; - - nfs_post_op_update_inode(old_dir, res->old_fattr); - nfs_post_op_update_inode(new_dir, res->new_fattr); - return 1; -} - static int nfs3_proc_rename(struct inode *old_dir, struct qstr *old_name, struct inode *new_dir, struct qstr *new_name) { - struct nfs_renameargs arg = { - .old_dir = NFS_FH(old_dir), - .old_name = old_name, - .new_dir = NFS_FH(new_dir), - .new_name = new_name, + struct nfs3_renameargs arg = { + .fromfh = NFS_FH(old_dir), + .fromname = old_name->name, + .fromlen = old_name->len, + .tofh = NFS_FH(new_dir), + .toname = new_name->name, + .tolen = new_name->len }; - struct nfs_renameres res; + struct nfs3_renameres res; struct rpc_message msg = { .rpc_proc = &nfs3_procedures[NFS3PROC_RENAME], .rpc_argp = &arg, @@ -479,17 +460,17 @@ nfs3_proc_rename(struct inode *old_dir, struct qstr *old_name, dprintk("NFS call rename %s -> %s\n", old_name->name, new_name->name); - res.old_fattr = nfs_alloc_fattr(); - res.new_fattr = nfs_alloc_fattr(); - if (res.old_fattr == NULL || res.new_fattr == NULL) + res.fromattr = nfs_alloc_fattr(); + res.toattr = nfs_alloc_fattr(); + if (res.fromattr == NULL || res.toattr == NULL) goto out; status = rpc_call_sync(NFS_CLIENT(old_dir), &msg, 0); - nfs_post_op_update_inode(old_dir, res.old_fattr); - nfs_post_op_update_inode(new_dir, res.new_fattr); + nfs_post_op_update_inode(old_dir, res.fromattr); + nfs_post_op_update_inode(new_dir, res.toattr); out: - nfs_free_fattr(res.old_fattr); - nfs_free_fattr(res.new_fattr); + nfs_free_fattr(res.toattr); + nfs_free_fattr(res.fromattr); dprintk("NFS reply rename: %d\n", status); return status; } @@ -630,7 +611,7 @@ nfs3_proc_rmdir(struct inode *dir, struct qstr *name) */ static int nfs3_proc_readdir(struct dentry *dentry, struct rpc_cred *cred, - u64 cookie, struct page **pages, unsigned int count, int plus) + u64 cookie, struct page *page, unsigned int count, int plus) { struct inode *dir = dentry->d_inode; __be32 *verf = NFS_COOKIEVERF(dir); @@ -640,7 +621,7 @@ nfs3_proc_readdir(struct dentry *dentry, struct rpc_cred *cred, .verf = {verf[0], verf[1]}, .plus = plus, .count = count, - .pages = pages + .pages = &page }; struct nfs3_readdirres res = { .verf = verf, @@ -671,8 +652,7 @@ nfs3_proc_readdir(struct dentry *dentry, struct rpc_cred *cred, nfs_free_fattr(res.dir_attr); out: - dprintk("NFS reply readdir%s: %d\n", - plus? "plus" : "", status); + dprintk("NFS reply readdir: %d\n", status); return status; } @@ -742,7 +722,7 @@ nfs3_proc_statfs(struct nfs_server *server, struct nfs_fh *fhandle, dprintk("NFS call fsstat\n"); nfs_fattr_init(stat->fattr); status = rpc_call_sync(server->client, &msg, 0); - dprintk("NFS reply fsstat: %d\n", status); + dprintk("NFS reply statfs: %d\n", status); return status; } @@ -864,8 +844,6 @@ const struct nfs_rpc_ops nfs_v3_clientops = { .unlink_setup = nfs3_proc_unlink_setup, .unlink_done = nfs3_proc_unlink_done, .rename = nfs3_proc_rename, - .rename_setup = nfs3_proc_rename_setup, - .rename_done = nfs3_proc_rename_done, .link = nfs3_proc_link, .symlink = nfs3_proc_symlink, .mkdir = nfs3_proc_mkdir, diff --git a/trunk/fs/nfs/nfs3xdr.c b/trunk/fs/nfs/nfs3xdr.c index d9a5e832c257..9769704f8ce6 100644 --- a/trunk/fs/nfs/nfs3xdr.c +++ b/trunk/fs/nfs/nfs3xdr.c @@ -100,13 +100,6 @@ static const umode_t nfs_type2fmt[] = { [NF3FIFO] = S_IFIFO, }; -static void print_overflow_msg(const char *func, const struct xdr_stream *xdr) -{ - dprintk("nfs: %s: prematurely hit end of receive buffer. " - "Remaining buffer length is %tu words.\n", - func, xdr->end - xdr->p); -} - /* * Common NFS XDR functions as inlines */ @@ -126,29 +119,6 @@ xdr_decode_fhandle(__be32 *p, struct nfs_fh *fh) return NULL; } -static inline __be32 * -xdr_decode_fhandle_stream(struct xdr_stream *xdr, struct nfs_fh *fh) -{ - __be32 *p; - p = xdr_inline_decode(xdr, 4); - if (unlikely(!p)) - goto out_overflow; - fh->size = ntohl(*p++); - - if (fh->size <= NFS3_FHSIZE) { - p = xdr_inline_decode(xdr, fh->size); - if (unlikely(!p)) - goto out_overflow; - memcpy(fh->data, p, fh->size); - return p + XDR_QUADLEN(fh->size); - } - return NULL; - -out_overflow: - print_overflow_msg(__func__, xdr); - return ERR_PTR(-EIO); -} - /* * Encode/decode time. */ @@ -270,26 +240,6 @@ xdr_decode_post_op_attr(__be32 *p, struct nfs_fattr *fattr) return p; } -static inline __be32 * -xdr_decode_post_op_attr_stream(struct xdr_stream *xdr, struct nfs_fattr *fattr) -{ - __be32 *p; - - p = xdr_inline_decode(xdr, 4); - if (unlikely(!p)) - goto out_overflow; - if (ntohl(*p++)) { - p = xdr_inline_decode(xdr, 84); - if (unlikely(!p)) - goto out_overflow; - p = xdr_decode_fattr(p, fattr); - } - return p; -out_overflow: - print_overflow_msg(__func__, xdr); - return ERR_PTR(-EIO); -} - static inline __be32 * xdr_decode_pre_op_attr(__be32 *p, struct nfs_fattr *fattr) { @@ -492,12 +442,12 @@ nfs3_xdr_mknodargs(struct rpc_rqst *req, __be32 *p, struct nfs3_mknodargs *args) * Encode RENAME arguments */ static int -nfs3_xdr_renameargs(struct rpc_rqst *req, __be32 *p, struct nfs_renameargs *args) +nfs3_xdr_renameargs(struct rpc_rqst *req, __be32 *p, struct nfs3_renameargs *args) { - p = xdr_encode_fhandle(p, args->old_dir); - p = xdr_encode_array(p, args->old_name->name, args->old_name->len); - p = xdr_encode_fhandle(p, args->new_dir); - p = xdr_encode_array(p, args->new_name->name, args->new_name->len); + p = xdr_encode_fhandle(p, args->fromfh); + p = xdr_encode_array(p, args->fromname, args->fromlen); + p = xdr_encode_fhandle(p, args->tofh); + p = xdr_encode_array(p, args->toname, args->tolen); req->rq_slen = xdr_adjust_iovec(req->rq_svec, p); return 0; } @@ -554,8 +504,9 @@ nfs3_xdr_readdirres(struct rpc_rqst *req, __be32 *p, struct nfs3_readdirres *res struct kvec *iov = rcvbuf->head; struct page **page; size_t hdrlen; - u32 recvd, pglen; + u32 len, recvd, pglen; int status, nr = 0; + __be32 *entry, *end, *kaddr; status = ntohl(*p++); /* Decode post_op_attrs */ @@ -585,38 +536,99 @@ nfs3_xdr_readdirres(struct rpc_rqst *req, __be32 *p, struct nfs3_readdirres *res if (pglen > recvd) pglen = recvd; page = rcvbuf->pages; + kaddr = p = kmap_atomic(*page, KM_USER0); + end = (__be32 *)((char *)p + pglen); + entry = p; + + /* Make sure the packet actually has a value_follows and EOF entry */ + if ((entry + 1) > end) + goto short_pkt; + + for (; *p++; nr++) { + if (p + 3 > end) + goto short_pkt; + p += 2; /* inode # */ + len = ntohl(*p++); /* string length */ + p += XDR_QUADLEN(len) + 2; /* name + cookie */ + if (len > NFS3_MAXNAMLEN) { + dprintk("NFS: giant filename in readdir (len 0x%x)!\n", + len); + goto err_unmap; + } + if (res->plus) { + /* post_op_attr */ + if (p + 2 > end) + goto short_pkt; + if (*p++) { + p += 21; + if (p + 1 > end) + goto short_pkt; + } + /* post_op_fh3 */ + if (*p++) { + if (p + 1 > end) + goto short_pkt; + len = ntohl(*p++); + if (len > NFS3_FHSIZE) { + dprintk("NFS: giant filehandle in " + "readdir (len 0x%x)!\n", len); + goto err_unmap; + } + p += XDR_QUADLEN(len); + } + } + + if (p + 2 > end) + goto short_pkt; + entry = p; + } + + /* + * Apparently some server sends responses that are a valid size, but + * contain no entries, and have value_follows==0 and EOF==0. For + * those, just set the EOF marker. + */ + if (!nr && entry[1] == 0) { + dprintk("NFS: readdir reply truncated!\n"); + entry[1] = 1; + } + out: + kunmap_atomic(kaddr, KM_USER0); return nr; + short_pkt: + /* + * When we get a short packet there are 2 possibilities. We can + * return an error, or fix up the response to look like a valid + * response and return what we have so far. If there are no + * entries and the packet was short, then return -EIO. If there + * are valid entries in the response, return them and pretend that + * the call was successful, but incomplete. The caller can retry the + * readdir starting at the last cookie. + */ + entry[0] = entry[1] = 0; + if (!nr) + nr = -errno_NFSERR_IO; + goto out; +err_unmap: + nr = -errno_NFSERR_IO; + goto out; } __be32 * -nfs3_decode_dirent(struct xdr_stream *xdr, struct nfs_entry *entry, struct nfs_server *server, int plus) +nfs3_decode_dirent(__be32 *p, struct nfs_entry *entry, int plus) { - __be32 *p; struct nfs_entry old = *entry; - p = xdr_inline_decode(xdr, 4); - if (unlikely(!p)) - goto out_overflow; - if (!ntohl(*p++)) { - p = xdr_inline_decode(xdr, 4); - if (unlikely(!p)) - goto out_overflow; - if (!ntohl(*p++)) + if (!*p++) { + if (!*p) return ERR_PTR(-EAGAIN); entry->eof = 1; return ERR_PTR(-EBADCOOKIE); } - p = xdr_inline_decode(xdr, 12); - if (unlikely(!p)) - goto out_overflow; p = xdr_decode_hyper(p, &entry->ino); entry->len = ntohl(*p++); - - p = xdr_inline_decode(xdr, entry->len + 8); - if (unlikely(!p)) - goto out_overflow; entry->name = (const char *) p; p += XDR_QUADLEN(entry->len); entry->prev_cookie = entry->cookie; @@ -624,17 +636,10 @@ nfs3_decode_dirent(struct xdr_stream *xdr, struct nfs_entry *entry, struct nfs_s if (plus) { entry->fattr->valid = 0; - p = xdr_decode_post_op_attr_stream(xdr, entry->fattr); - if (IS_ERR(p)) - goto out_overflow_exit; + p = xdr_decode_post_op_attr(p, entry->fattr); /* In fact, a post_op_fh3: */ - p = xdr_inline_decode(xdr, 4); - if (unlikely(!p)) - goto out_overflow; if (*p++) { - p = xdr_decode_fhandle_stream(xdr, entry->fh); - if (IS_ERR(p)) - goto out_overflow_exit; + p = xdr_decode_fhandle(p, entry->fh); /* Ugh -- server reply was truncated */ if (p == NULL) { dprintk("NFS: FH truncated\n"); @@ -645,18 +650,8 @@ nfs3_decode_dirent(struct xdr_stream *xdr, struct nfs_entry *entry, struct nfs_s memset((u8*)(entry->fh), 0, sizeof(*entry->fh)); } - p = xdr_inline_peek(xdr, 8); - if (p != NULL) - entry->eof = !p[0] && p[1]; - else - entry->eof = 0; - + entry->eof = !p[0] && p[1]; return p; - -out_overflow: - print_overflow_msg(__func__, xdr); -out_overflow_exit: - return ERR_PTR(-EIO); } /* @@ -829,6 +824,7 @@ nfs3_xdr_readlinkres(struct rpc_rqst *req, __be32 *p, struct nfs_fattr *fattr) struct kvec *iov = rcvbuf->head; size_t hdrlen; u32 len, recvd; + char *kaddr; int status; status = ntohl(*p++); @@ -861,7 +857,10 @@ nfs3_xdr_readlinkres(struct rpc_rqst *req, __be32 *p, struct nfs_fattr *fattr) return -EIO; } - xdr_terminate_string(rcvbuf, len); + /* NULL terminate the string we got */ + kaddr = (char*)kmap_atomic(rcvbuf->pages[0], KM_USER0); + kaddr[len+rcvbuf->page_base] = '\0'; + kunmap_atomic(kaddr, KM_USER0); return 0; } @@ -971,14 +970,14 @@ nfs3_xdr_createres(struct rpc_rqst *req, __be32 *p, struct nfs3_diropres *res) * Decode RENAME reply */ static int -nfs3_xdr_renameres(struct rpc_rqst *req, __be32 *p, struct nfs_renameres *res) +nfs3_xdr_renameres(struct rpc_rqst *req, __be32 *p, struct nfs3_renameres *res) { int status; if ((status = ntohl(*p++)) != 0) status = nfs_stat_to_errno(status); - p = xdr_decode_wcc_data(p, res->old_fattr); - p = xdr_decode_wcc_data(p, res->new_fattr); + p = xdr_decode_wcc_data(p, res->fromattr); + p = xdr_decode_wcc_data(p, res->toattr); return status; } @@ -1044,9 +1043,8 @@ nfs3_xdr_fsinfores(struct rpc_rqst *req, __be32 *p, struct nfs_fsinfo *res) res->wtmult = ntohl(*p++); res->dtpref = ntohl(*p++); p = xdr_decode_hyper(p, &res->maxfilesize); - p = xdr_decode_time3(p, &res->time_delta); - /* ignore properties */ + /* ignore time_delta and properties */ res->lease_time = 0; return 0; } diff --git a/trunk/fs/nfs/nfs4_fs.h b/trunk/fs/nfs/nfs4_fs.h index 9fa496387fdf..311e15cc8af0 100644 --- a/trunk/fs/nfs/nfs4_fs.h +++ b/trunk/fs/nfs/nfs4_fs.h @@ -242,6 +242,8 @@ extern int nfs4_proc_renew(struct nfs_client *, struct rpc_cred *); extern int nfs4_init_clientid(struct nfs_client *, struct rpc_cred *); extern int nfs41_init_clientid(struct nfs_client *, struct rpc_cred *); extern int nfs4_do_close(struct path *path, struct nfs4_state *state, gfp_t gfp_mask, int wait); +extern struct dentry *nfs4_atomic_open(struct inode *, struct dentry *, struct nameidata *); +extern int nfs4_open_revalidate(struct inode *, struct dentry *, int, struct nameidata *); extern int nfs4_server_capabilities(struct nfs_server *server, struct nfs_fh *fhandle); extern int nfs4_proc_fs_locations(struct inode *dir, const struct qstr *name, struct nfs4_fs_locations *fs_locations, struct page *page); @@ -331,7 +333,7 @@ extern void nfs_free_seqid(struct nfs_seqid *seqid); extern const nfs4_stateid zero_stateid; /* nfs4xdr.c */ -extern __be32 *nfs4_decode_dirent(struct xdr_stream *, struct nfs_entry *, struct nfs_server *, int); +extern __be32 *nfs4_decode_dirent(__be32 *p, struct nfs_entry *entry, int plus); extern struct rpc_procinfo nfs4_procedures[]; struct nfs4_mount_data; diff --git a/trunk/fs/nfs/nfs4proc.c b/trunk/fs/nfs/nfs4proc.c index e87fe612ca18..089da5b5d20a 100644 --- a/trunk/fs/nfs/nfs4proc.c +++ b/trunk/fs/nfs/nfs4proc.c @@ -129,7 +129,7 @@ const u32 nfs4_fsinfo_bitmap[2] = { FATTR4_WORD0_MAXFILESIZE | FATTR4_WORD0_MAXREAD | FATTR4_WORD0_MAXWRITE | FATTR4_WORD0_LEASE_TIME, - FATTR4_WORD1_TIME_DELTA + 0 }; const u32 nfs4_fs_locations_bitmap[2] = { @@ -255,6 +255,9 @@ static int nfs4_handle_exception(const struct nfs_server *server, int errorcode, nfs4_state_mark_reclaim_nograce(clp, state); goto do_state_recovery; case -NFS4ERR_STALE_STATEID: + if (state == NULL) + break; + nfs4_state_mark_reclaim_reboot(clp, state); case -NFS4ERR_STALE_CLIENTID: case -NFS4ERR_EXPIRED: goto do_state_recovery; @@ -331,12 +334,10 @@ static void renew_lease(const struct nfs_server *server, unsigned long timestamp * Must be called while holding tbl->slot_tbl_lock */ static void -nfs4_free_slot(struct nfs4_slot_table *tbl, struct nfs4_slot *free_slot) +nfs4_free_slot(struct nfs4_slot_table *tbl, u8 free_slotid) { - int free_slotid = free_slot - tbl->slots; int slotid = free_slotid; - BUG_ON(slotid < 0 || slotid >= NFS4_MAX_SLOT_TABLE); /* clear used bit in bitmap */ __clear_bit(slotid, tbl->used_slots); @@ -378,7 +379,7 @@ static void nfs41_sequence_free_slot(struct nfs4_sequence_res *res) struct nfs4_slot_table *tbl; tbl = &res->sr_session->fc_slot_table; - if (!res->sr_slot) { + if (res->sr_slotid == NFS4_MAX_SLOT_TABLE) { /* just wake up the next guy waiting since * we may have not consumed a slot after all */ dprintk("%s: No slot\n", __func__); @@ -386,15 +387,17 @@ static void nfs41_sequence_free_slot(struct nfs4_sequence_res *res) } spin_lock(&tbl->slot_tbl_lock); - nfs4_free_slot(tbl, res->sr_slot); + nfs4_free_slot(tbl, res->sr_slotid); nfs41_check_drain_session_complete(res->sr_session); spin_unlock(&tbl->slot_tbl_lock); - res->sr_slot = NULL; + res->sr_slotid = NFS4_MAX_SLOT_TABLE; } static int nfs41_sequence_done(struct rpc_task *task, struct nfs4_sequence_res *res) { unsigned long timestamp; + struct nfs4_slot_table *tbl; + struct nfs4_slot *slot; struct nfs_client *clp; /* @@ -407,14 +410,17 @@ static int nfs41_sequence_done(struct rpc_task *task, struct nfs4_sequence_res * res->sr_status = NFS_OK; /* -ERESTARTSYS can result in skipping nfs41_sequence_setup */ - if (!res->sr_slot) + if (res->sr_slotid == NFS4_MAX_SLOT_TABLE) goto out; + tbl = &res->sr_session->fc_slot_table; + slot = tbl->slots + res->sr_slotid; + /* Check the SEQUENCE operation status */ switch (res->sr_status) { case 0: /* Update the slot's sequence and clientid lease timer */ - ++res->sr_slot->seq_nr; + ++slot->seq_nr; timestamp = res->sr_renewal_time; clp = res->sr_session->clp; do_renew_lease(clp, timestamp); @@ -427,14 +433,12 @@ static int nfs41_sequence_done(struct rpc_task *task, struct nfs4_sequence_res * * returned NFS4ERR_DELAY as per Section 2.10.6.2 * of RFC5661. */ - dprintk("%s: slot=%ld seq=%d: Operation in progress\n", - __func__, - res->sr_slot - res->sr_session->fc_slot_table.slots, - res->sr_slot->seq_nr); + dprintk("%s: slot=%d seq=%d: Operation in progress\n", + __func__, res->sr_slotid, slot->seq_nr); goto out_retry; default: /* Just update the slot sequence no. */ - ++res->sr_slot->seq_nr; + ++slot->seq_nr; } out: /* The session may be reset by one of the error handlers. */ @@ -501,9 +505,10 @@ static int nfs41_setup_sequence(struct nfs4_session *session, dprintk("--> %s\n", __func__); /* slot already allocated? */ - if (res->sr_slot != NULL) + if (res->sr_slotid != NFS4_MAX_SLOT_TABLE) return 0; + res->sr_slotid = NFS4_MAX_SLOT_TABLE; tbl = &session->fc_slot_table; spin_lock(&tbl->slot_tbl_lock); @@ -545,7 +550,7 @@ static int nfs41_setup_sequence(struct nfs4_session *session, dprintk("<-- %s slotid=%d seqid=%d\n", __func__, slotid, slot->seq_nr); res->sr_session = session; - res->sr_slot = slot; + res->sr_slotid = slotid; res->sr_renewal_time = jiffies; res->sr_status_flags = 0; /* @@ -571,9 +576,8 @@ int nfs4_setup_sequence(const struct nfs_server *server, goto out; } - dprintk("--> %s clp %p session %p sr_slot %ld\n", - __func__, session->clp, session, res->sr_slot ? - res->sr_slot - session->fc_slot_table.slots : -1); + dprintk("--> %s clp %p session %p sr_slotid %d\n", + __func__, session->clp, session, res->sr_slotid); ret = nfs41_setup_sequence(session, args, res, cache_reply, task); @@ -646,7 +650,7 @@ static int nfs4_call_sync_sequence(struct nfs_server *server, .callback_data = &data }; - res->sr_slot = NULL; + res->sr_slotid = NFS4_MAX_SLOT_TABLE; if (privileged) task_setup.callback_ops = &nfs41_call_priv_sync_ops; task = rpc_run_task(&task_setup); @@ -731,6 +735,7 @@ static void nfs4_init_opendata_res(struct nfs4_opendata *p) p->o_res.server = p->o_arg.server; nfs_fattr_init(&p->f_attr); nfs_fattr_init(&p->dir_attr); + p->o_res.seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE; } static struct nfs4_opendata *nfs4_opendata_alloc(struct path *path, @@ -1115,7 +1120,6 @@ static int nfs4_open_recover(struct nfs4_opendata *opendata, struct nfs4_state * clear_bit(NFS_DELEGATED_STATE, &state->flags); smp_rmb(); if (state->n_rdwr != 0) { - clear_bit(NFS_O_RDWR_STATE, &state->flags); ret = nfs4_open_recover_helper(opendata, FMODE_READ|FMODE_WRITE, &newstate); if (ret != 0) return ret; @@ -1123,7 +1127,6 @@ static int nfs4_open_recover(struct nfs4_opendata *opendata, struct nfs4_state * return -ESTALE; } if (state->n_wronly != 0) { - clear_bit(NFS_O_WRONLY_STATE, &state->flags); ret = nfs4_open_recover_helper(opendata, FMODE_WRITE, &newstate); if (ret != 0) return ret; @@ -1131,7 +1134,6 @@ static int nfs4_open_recover(struct nfs4_opendata *opendata, struct nfs4_state * return -ESTALE; } if (state->n_rdonly != 0) { - clear_bit(NFS_O_RDONLY_STATE, &state->flags); ret = nfs4_open_recover_helper(opendata, FMODE_READ, &newstate); if (ret != 0) return ret; @@ -1186,7 +1188,7 @@ static int nfs4_do_open_reclaim(struct nfs_open_context *ctx, struct nfs4_state int err; do { err = _nfs4_do_open_reclaim(ctx, state); - if (err != -NFS4ERR_DELAY) + if (err != -NFS4ERR_DELAY && err != -EKEYEXPIRED) break; nfs4_handle_exception(server, err, &exception); } while (exception.retry); @@ -1256,13 +1258,6 @@ int nfs4_open_delegation_recall(struct nfs_open_context *ctx, struct nfs4_state case -NFS4ERR_ADMIN_REVOKED: case -NFS4ERR_BAD_STATEID: nfs4_state_mark_reclaim_nograce(server->nfs_client, state); - case -EKEYEXPIRED: - /* - * User RPCSEC_GSS context has expired. - * We cannot recover this stateid now, so - * skip it and allow recovery thread to - * proceed. - */ case -ENOMEM: err = 0; goto out; @@ -1610,6 +1605,7 @@ static int nfs4_do_open_expired(struct nfs_open_context *ctx, struct nfs4_state goto out; case -NFS4ERR_GRACE: case -NFS4ERR_DELAY: + case -EKEYEXPIRED: nfs4_handle_exception(server, err, &exception); err = 0; } @@ -1979,6 +1975,7 @@ int nfs4_do_close(struct path *path, struct nfs4_state *state, gfp_t gfp_mask, i calldata->res.fattr = &calldata->fattr; calldata->res.seqid = calldata->arg.seqid; calldata->res.server = server; + calldata->res.seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE; path_get(path); calldata->path = *path; @@ -2001,17 +1998,120 @@ int nfs4_do_close(struct path *path, struct nfs4_state *state, gfp_t gfp_mask, i return status; } -static struct inode * -nfs4_atomic_open(struct inode *dir, struct nfs_open_context *ctx, int open_flags, struct iattr *attr) +static int nfs4_intent_set_file(struct nameidata *nd, struct path *path, struct nfs4_state *state, fmode_t fmode) +{ + struct file *filp; + int ret; + + /* If the open_intent is for execute, we have an extra check to make */ + if (fmode & FMODE_EXEC) { + ret = nfs_may_open(state->inode, + state->owner->so_cred, + nd->intent.open.flags); + if (ret < 0) + goto out_close; + } + filp = lookup_instantiate_filp(nd, path->dentry, NULL); + if (!IS_ERR(filp)) { + struct nfs_open_context *ctx; + ctx = nfs_file_open_context(filp); + ctx->state = state; + return 0; + } + ret = PTR_ERR(filp); +out_close: + nfs4_close_sync(path, state, fmode & (FMODE_READ|FMODE_WRITE)); + return ret; +} + +struct dentry * +nfs4_atomic_open(struct inode *dir, struct dentry *dentry, struct nameidata *nd) { + struct path path = { + .mnt = nd->path.mnt, + .dentry = dentry, + }; + struct dentry *parent; + struct iattr attr; + struct rpc_cred *cred; struct nfs4_state *state; + struct dentry *res; + int open_flags = nd->intent.open.flags; + fmode_t fmode = open_flags & (FMODE_READ | FMODE_WRITE | FMODE_EXEC); + + if (nd->flags & LOOKUP_CREATE) { + attr.ia_mode = nd->intent.open.create_mode; + attr.ia_valid = ATTR_MODE; + if (!IS_POSIXACL(dir)) + attr.ia_mode &= ~current_umask(); + } else { + open_flags &= ~O_EXCL; + attr.ia_valid = 0; + BUG_ON(open_flags & O_CREAT); + } + cred = rpc_lookup_cred(); + if (IS_ERR(cred)) + return (struct dentry *)cred; + parent = dentry->d_parent; /* Protect against concurrent sillydeletes */ - state = nfs4_do_open(dir, &ctx->path, ctx->mode, open_flags, attr, ctx->cred); - if (IS_ERR(state)) - return ERR_CAST(state); - ctx->state = state; - return igrab(state->inode); + nfs_block_sillyrename(parent); + state = nfs4_do_open(dir, &path, fmode, open_flags, &attr, cred); + put_rpccred(cred); + if (IS_ERR(state)) { + if (PTR_ERR(state) == -ENOENT) { + d_add(dentry, NULL); + nfs_set_verifier(dentry, nfs_save_change_attribute(dir)); + } + nfs_unblock_sillyrename(parent); + return (struct dentry *)state; + } + res = d_add_unique(dentry, igrab(state->inode)); + if (res != NULL) + path.dentry = res; + nfs_set_verifier(path.dentry, nfs_save_change_attribute(dir)); + nfs_unblock_sillyrename(parent); + nfs4_intent_set_file(nd, &path, state, fmode); + return res; +} + +int +nfs4_open_revalidate(struct inode *dir, struct dentry *dentry, int openflags, struct nameidata *nd) +{ + struct path path = { + .mnt = nd->path.mnt, + .dentry = dentry, + }; + struct rpc_cred *cred; + struct nfs4_state *state; + fmode_t fmode = openflags & (FMODE_READ | FMODE_WRITE); + + cred = rpc_lookup_cred(); + if (IS_ERR(cred)) + return PTR_ERR(cred); + state = nfs4_do_open(dir, &path, fmode, openflags, NULL, cred); + put_rpccred(cred); + if (IS_ERR(state)) { + switch (PTR_ERR(state)) { + case -EPERM: + case -EACCES: + case -EDQUOT: + case -ENOSPC: + case -EROFS: + return PTR_ERR(state); + default: + goto out_drop; + } + } + if (state->inode == dentry->d_inode) { + nfs_set_verifier(dentry, nfs_save_change_attribute(dir)); + nfs4_intent_set_file(nd, &path, state, fmode); + return 1; + } + nfs4_close_sync(&path, state, fmode); +out_drop: + d_drop(dentry); + return 0; } static void nfs4_close_context(struct nfs_open_context *ctx, int is_sync) @@ -2468,34 +2568,36 @@ static int nfs4_proc_readlink(struct inode *inode, struct page *page, static int nfs4_proc_create(struct inode *dir, struct dentry *dentry, struct iattr *sattr, - int flags, struct nfs_open_context *ctx) + int flags, struct nameidata *nd) { - struct path my_path = { + struct path path = { + .mnt = nd->path.mnt, .dentry = dentry, }; - struct path *path = &my_path; struct nfs4_state *state; - struct rpc_cred *cred = NULL; - fmode_t fmode = 0; + struct rpc_cred *cred; + fmode_t fmode = flags & (FMODE_READ | FMODE_WRITE); int status = 0; - if (ctx != NULL) { - cred = ctx->cred; - path = &ctx->path; - fmode = ctx->mode; + cred = rpc_lookup_cred(); + if (IS_ERR(cred)) { + status = PTR_ERR(cred); + goto out; } - state = nfs4_do_open(dir, path, fmode, flags, sattr, cred); + state = nfs4_do_open(dir, &path, fmode, flags, sattr, cred); d_drop(dentry); if (IS_ERR(state)) { status = PTR_ERR(state); - goto out; + goto out_putcred; } d_add(dentry, igrab(state->inode)); nfs_set_verifier(dentry, nfs_save_change_attribute(dir)); - if (ctx != NULL) - ctx->state = state; + if (status == 0 && (nd->flags & LOOKUP_OPEN) != 0) + status = nfs4_intent_set_file(nd, &path, state, fmode); else - nfs4_close_sync(path, state, fmode); + nfs4_close_sync(&path, state, fmode); +out_putcred: + put_rpccred(cred); out: return status; } @@ -2553,7 +2655,6 @@ static void nfs4_proc_unlink_setup(struct rpc_message *msg, struct inode *dir) args->bitmask = server->cache_consistency_bitmask; res->server = server; - res->seq_res.sr_slot = NULL; msg->rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_REMOVE]; } @@ -2570,46 +2671,18 @@ static int nfs4_proc_unlink_done(struct rpc_task *task, struct inode *dir) return 1; } -static void nfs4_proc_rename_setup(struct rpc_message *msg, struct inode *dir) -{ - struct nfs_server *server = NFS_SERVER(dir); - struct nfs_renameargs *arg = msg->rpc_argp; - struct nfs_renameres *res = msg->rpc_resp; - - msg->rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_RENAME]; - arg->bitmask = server->attr_bitmask; - res->server = server; -} - -static int nfs4_proc_rename_done(struct rpc_task *task, struct inode *old_dir, - struct inode *new_dir) -{ - struct nfs_renameres *res = task->tk_msg.rpc_resp; - - if (!nfs4_sequence_done(task, &res->seq_res)) - return 0; - if (nfs4_async_handle_error(task, res->server, NULL) == -EAGAIN) - return 0; - - update_changeattr(old_dir, &res->old_cinfo); - nfs_post_op_update_inode(old_dir, res->old_fattr); - update_changeattr(new_dir, &res->new_cinfo); - nfs_post_op_update_inode(new_dir, res->new_fattr); - return 1; -} - static int _nfs4_proc_rename(struct inode *old_dir, struct qstr *old_name, struct inode *new_dir, struct qstr *new_name) { struct nfs_server *server = NFS_SERVER(old_dir); - struct nfs_renameargs arg = { + struct nfs4_rename_arg arg = { .old_dir = NFS_FH(old_dir), .new_dir = NFS_FH(new_dir), .old_name = old_name, .new_name = new_name, .bitmask = server->attr_bitmask, }; - struct nfs_renameres res = { + struct nfs4_rename_res res = { .server = server, }; struct rpc_message msg = { @@ -2823,16 +2896,15 @@ static int nfs4_proc_mkdir(struct inode *dir, struct dentry *dentry, } static int _nfs4_proc_readdir(struct dentry *dentry, struct rpc_cred *cred, - u64 cookie, struct page **pages, unsigned int count, int plus) + u64 cookie, struct page *page, unsigned int count, int plus) { struct inode *dir = dentry->d_inode; struct nfs4_readdir_arg args = { .fh = NFS_FH(dir), - .pages = pages, + .pages = &page, .pgbase = 0, .count = count, .bitmask = NFS_SERVER(dentry->d_inode)->attr_bitmask, - .plus = plus, }; struct nfs4_readdir_res res; struct rpc_message msg = { @@ -2860,14 +2932,14 @@ static int _nfs4_proc_readdir(struct dentry *dentry, struct rpc_cred *cred, } static int nfs4_proc_readdir(struct dentry *dentry, struct rpc_cred *cred, - u64 cookie, struct page **pages, unsigned int count, int plus) + u64 cookie, struct page *page, unsigned int count, int plus) { struct nfs4_exception exception = { }; int err; do { err = nfs4_handle_exception(NFS_SERVER(dentry->d_inode), _nfs4_proc_readdir(dentry, cred, cookie, - pages, count, plus), + page, count, plus), &exception); } while (exception.retry); return err; @@ -3418,6 +3490,9 @@ nfs4_async_handle_error(struct rpc_task *task, const struct nfs_server *server, nfs4_state_mark_reclaim_nograce(clp, state); goto do_state_recovery; case -NFS4ERR_STALE_STATEID: + if (state == NULL) + break; + nfs4_state_mark_reclaim_reboot(clp, state); case -NFS4ERR_STALE_CLIENTID: case -NFS4ERR_EXPIRED: goto do_state_recovery; @@ -3551,6 +3626,7 @@ int nfs4_proc_setclientid_confirm(struct nfs_client *clp, case -NFS4ERR_RESOURCE: /* The IBM lawyers misread another document! */ case -NFS4ERR_DELAY: + case -EKEYEXPIRED: err = nfs4_delay(clp->cl_rpcclient, &timeout); } } while (err == 0); @@ -3645,6 +3721,7 @@ static int _nfs4_proc_delegreturn(struct inode *inode, struct rpc_cred *cred, co memcpy(&data->stateid, stateid, sizeof(data->stateid)); data->res.fattr = &data->fattr; data->res.server = server; + data->res.seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE; nfs_fattr_init(data->res.fattr); data->timestamp = jiffies; data->rpc_status = 0; @@ -3797,6 +3874,7 @@ static struct nfs4_unlockdata *nfs4_alloc_unlockdata(struct file_lock *fl, p->arg.fl = &p->fl; p->arg.seqid = seqid; p->res.seqid = seqid; + p->res.seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE; p->arg.stateid = &lsp->ls_stateid; p->lsp = lsp; atomic_inc(&lsp->ls_count); @@ -3976,6 +4054,7 @@ static struct nfs4_lockdata *nfs4_alloc_lockdata(struct file_lock *fl, p->arg.lock_owner.clientid = server->nfs_client->cl_clientid; p->arg.lock_owner.id = lsp->ls_id.id; p->res.lock_seqid = p->arg.lock_seqid; + p->res.seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE; p->lsp = lsp; p->server = server; atomic_inc(&lsp->ls_count); @@ -4162,7 +4241,7 @@ static int nfs4_lock_reclaim(struct nfs4_state *state, struct file_lock *request if (test_bit(NFS_DELEGATED_STATE, &state->flags) != 0) return 0; err = _nfs4_do_setlk(state, F_SETLK, request, NFS_LOCK_RECLAIM); - if (err != -NFS4ERR_DELAY) + if (err != -NFS4ERR_DELAY && err != -EKEYEXPIRED) break; nfs4_handle_exception(server, err, &exception); } while (exception.retry); @@ -4187,6 +4266,7 @@ static int nfs4_lock_expired(struct nfs4_state *state, struct file_lock *request goto out; case -NFS4ERR_GRACE: case -NFS4ERR_DELAY: + case -EKEYEXPIRED: nfs4_handle_exception(server, err, &exception); err = 0; } @@ -4332,21 +4412,13 @@ int nfs4_lock_delegation_recall(struct nfs4_state *state, struct file_lock *fl) nfs4_state_mark_reclaim_nograce(server->nfs_client, state); err = 0; goto out; - case -EKEYEXPIRED: - /* - * User RPCSEC_GSS context has expired. - * We cannot recover this stateid now, so - * skip it and allow recovery thread to - * proceed. - */ - err = 0; - goto out; case -ENOMEM: case -NFS4ERR_DENIED: /* kill_proc(fl->fl_pid, SIGLOST, 1); */ err = 0; goto out; case -NFS4ERR_DELAY: + case -EKEYEXPIRED: break; } err = nfs4_handle_exception(server, err, &exception); @@ -4575,6 +4647,7 @@ static void nfs4_get_lease_time_done(struct rpc_task *task, void *calldata) switch (task->tk_status) { case -NFS4ERR_DELAY: case -NFS4ERR_GRACE: + case -EKEYEXPIRED: dprintk("%s Retry: tk_status %d\n", __func__, task->tk_status); rpc_delay(task, NFS4_POLL_RETRY_MIN); task->tk_status = 0; @@ -4614,6 +4687,7 @@ int nfs4_proc_get_lease_time(struct nfs_client *clp, struct nfs_fsinfo *fsinfo) }; int status; + res.lr_seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE; dprintk("--> %s\n", __func__); task = rpc_run_task(&task_setup); @@ -5037,6 +5111,7 @@ static int nfs41_sequence_handle_errors(struct rpc_task *task, struct nfs_client { switch(task->tk_status) { case -NFS4ERR_DELAY: + case -EKEYEXPIRED: rpc_delay(task, NFS4_POLL_RETRY_MAX); return -EAGAIN; default: @@ -5105,11 +5180,12 @@ static struct rpc_task *_nfs41_proc_sequence(struct nfs_client *clp, struct rpc_ if (!atomic_inc_not_zero(&clp->cl_count)) return ERR_PTR(-EIO); - calldata = kzalloc(sizeof(*calldata), GFP_NOFS); + calldata = kmalloc(sizeof(*calldata), GFP_NOFS); if (calldata == NULL) { nfs_put_client(clp); return ERR_PTR(-ENOMEM); } + calldata->res.sr_slotid = NFS4_MAX_SLOT_TABLE; msg.rpc_argp = &calldata->args; msg.rpc_resp = &calldata->res; calldata->clp = clp; @@ -5178,6 +5254,7 @@ static int nfs41_reclaim_complete_handle_errors(struct rpc_task *task, struct nf case -NFS4ERR_WRONG_CRED: /* What to do here? */ break; case -NFS4ERR_DELAY: + case -EKEYEXPIRED: rpc_delay(task, NFS4_POLL_RETRY_MAX); return -EAGAIN; default: @@ -5240,6 +5317,7 @@ static int nfs41_proc_reclaim_complete(struct nfs_client *clp) goto out; calldata->clp = clp; calldata->arg.one_fs = 0; + calldata->res.seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE; msg.rpc_argp = &calldata->arg; msg.rpc_resp = &calldata->res; @@ -5365,8 +5443,6 @@ const struct nfs_rpc_ops nfs_v4_clientops = { .unlink_setup = nfs4_proc_unlink_setup, .unlink_done = nfs4_proc_unlink_done, .rename = nfs4_proc_rename, - .rename_setup = nfs4_proc_rename_setup, - .rename_done = nfs4_proc_rename_done, .link = nfs4_proc_link, .symlink = nfs4_proc_symlink, .mkdir = nfs4_proc_mkdir, @@ -5387,7 +5463,6 @@ const struct nfs_rpc_ops nfs_v4_clientops = { .lock = nfs4_proc_lock, .clear_acl_cache = nfs4_zap_acl_attr, .close_context = nfs4_close_context, - .open_context = nfs4_atomic_open, }; /* diff --git a/trunk/fs/nfs/nfs4state.c b/trunk/fs/nfs/nfs4state.c index aa0b02a610c4..96524c5dca6b 100644 --- a/trunk/fs/nfs/nfs4state.c +++ b/trunk/fs/nfs/nfs4state.c @@ -46,7 +46,6 @@ #include #include #include -#include #include #include @@ -1064,14 +1063,6 @@ static int nfs4_reclaim_open_state(struct nfs4_state_owner *sp, const struct nfs /* Mark the file as being 'closed' */ state->state = 0; break; - case -EKEYEXPIRED: - /* - * User RPCSEC_GSS context has expired. - * We cannot recover this stateid now, so - * skip it and allow recovery thread to - * proceed. - */ - break; case -NFS4ERR_ADMIN_REVOKED: case -NFS4ERR_STALE_STATEID: case -NFS4ERR_BAD_STATEID: @@ -1147,14 +1138,16 @@ static void nfs4_reclaim_complete(struct nfs_client *clp, (void)ops->reclaim_complete(clp); } -static int nfs4_state_clear_reclaim_reboot(struct nfs_client *clp) +static void nfs4_state_end_reclaim_reboot(struct nfs_client *clp) { struct nfs4_state_owner *sp; struct rb_node *pos; struct nfs4_state *state; if (!test_and_clear_bit(NFS4CLNT_RECLAIM_REBOOT, &clp->cl_state)) - return 0; + return; + + nfs4_reclaim_complete(clp, clp->cl_mvops->reboot_recovery_ops); for (pos = rb_first(&clp->cl_state_owners); pos != NULL; pos = rb_next(pos)) { sp = rb_entry(pos, struct nfs4_state_owner, so_client_node); @@ -1168,14 +1161,6 @@ static int nfs4_state_clear_reclaim_reboot(struct nfs_client *clp) } nfs_delegation_reap_unclaimed(clp); - return 1; -} - -static void nfs4_state_end_reclaim_reboot(struct nfs_client *clp) -{ - if (!nfs4_state_clear_reclaim_reboot(clp)) - return; - nfs4_reclaim_complete(clp, clp->cl_mvops->reboot_recovery_ops); } static void nfs_delegation_clear_all(struct nfs_client *clp) @@ -1190,14 +1175,6 @@ static void nfs4_state_start_reclaim_nograce(struct nfs_client *clp) nfs4_state_mark_reclaim_helper(clp, nfs4_state_mark_reclaim_nograce); } -static void nfs4_warn_keyexpired(const char *s) -{ - printk_ratelimited(KERN_WARNING "Error: state manager" - " encountered RPCSEC_GSS session" - " expired against NFSv4 server %s.\n", - s); -} - static int nfs4_recovery_handle_error(struct nfs_client *clp, int error) { switch (error) { @@ -1210,7 +1187,7 @@ static int nfs4_recovery_handle_error(struct nfs_client *clp, int error) case -NFS4ERR_STALE_CLIENTID: case -NFS4ERR_LEASE_MOVED: set_bit(NFS4CLNT_LEASE_EXPIRED, &clp->cl_state); - nfs4_state_clear_reclaim_reboot(clp); + nfs4_state_end_reclaim_reboot(clp); nfs4_state_start_reclaim_reboot(clp); break; case -NFS4ERR_EXPIRED: @@ -1227,10 +1204,6 @@ static int nfs4_recovery_handle_error(struct nfs_client *clp, int error) set_bit(NFS4CLNT_SESSION_RESET, &clp->cl_state); /* Zero session reset errors */ return 0; - case -EKEYEXPIRED: - /* Nothing we can do */ - nfs4_warn_keyexpired(clp->cl_hostname); - return 0; } return error; } @@ -1441,10 +1414,9 @@ static void nfs4_set_lease_expired(struct nfs_client *clp, int status) case -NFS4ERR_DELAY: case -NFS4ERR_CLID_INUSE: case -EAGAIN: + case -EKEYEXPIRED: break; - case -EKEYEXPIRED: - nfs4_warn_keyexpired(clp->cl_hostname); case -NFS4ERR_NOT_SAME: /* FixMe: implement recovery * in nfs4_exchange_id */ default: diff --git a/trunk/fs/nfs/nfs4xdr.c b/trunk/fs/nfs/nfs4xdr.c index bd2101d918c8..08ef91291132 100644 --- a/trunk/fs/nfs/nfs4xdr.c +++ b/trunk/fs/nfs/nfs4xdr.c @@ -816,7 +816,7 @@ static void encode_attrs(struct xdr_stream *xdr, const struct iattr *iap, const if (iap->ia_valid & ATTR_MODE) len += 4; if (iap->ia_valid & ATTR_UID) { - owner_namelen = nfs_map_uid_to_name(server->nfs_client, iap->ia_uid, owner_name, IDMAP_NAMESZ); + owner_namelen = nfs_map_uid_to_name(server->nfs_client, iap->ia_uid, owner_name); if (owner_namelen < 0) { dprintk("nfs: couldn't resolve uid %d to string\n", iap->ia_uid); @@ -828,7 +828,7 @@ static void encode_attrs(struct xdr_stream *xdr, const struct iattr *iap, const len += 4 + (XDR_QUADLEN(owner_namelen) << 2); } if (iap->ia_valid & ATTR_GID) { - owner_grouplen = nfs_map_gid_to_group(server->nfs_client, iap->ia_gid, owner_group, IDMAP_NAMESZ); + owner_grouplen = nfs_map_gid_to_group(server->nfs_client, iap->ia_gid, owner_group); if (owner_grouplen < 0) { dprintk("nfs: couldn't resolve gid %d to string\n", iap->ia_gid); @@ -1385,35 +1385,24 @@ static void encode_read(struct xdr_stream *xdr, const struct nfs_readargs *args, static void encode_readdir(struct xdr_stream *xdr, const struct nfs4_readdir_arg *readdir, struct rpc_rqst *req, struct compound_hdr *hdr) { - uint32_t attrs[2] = {0, 0}; - uint32_t dircount = readdir->count >> 1; + uint32_t attrs[2] = { + FATTR4_WORD0_RDATTR_ERROR|FATTR4_WORD0_FILEID, + FATTR4_WORD1_MOUNTED_ON_FILEID, + }; __be32 *p; - if (readdir->plus) { - attrs[0] |= FATTR4_WORD0_TYPE|FATTR4_WORD0_CHANGE|FATTR4_WORD0_SIZE| - FATTR4_WORD0_FSID|FATTR4_WORD0_FILEHANDLE; - attrs[1] |= FATTR4_WORD1_MODE|FATTR4_WORD1_NUMLINKS|FATTR4_WORD1_OWNER| - FATTR4_WORD1_OWNER_GROUP|FATTR4_WORD1_RAWDEV| - FATTR4_WORD1_SPACE_USED|FATTR4_WORD1_TIME_ACCESS| - FATTR4_WORD1_TIME_METADATA|FATTR4_WORD1_TIME_MODIFY; - dircount >>= 1; - } - attrs[0] |= FATTR4_WORD0_RDATTR_ERROR|FATTR4_WORD0_FILEID; - attrs[1] |= FATTR4_WORD1_MOUNTED_ON_FILEID; - /* Switch to mounted_on_fileid if the server supports it */ - if (readdir->bitmask[1] & FATTR4_WORD1_MOUNTED_ON_FILEID) - attrs[0] &= ~FATTR4_WORD0_FILEID; - else - attrs[1] &= ~FATTR4_WORD1_MOUNTED_ON_FILEID; - p = reserve_space(xdr, 12+NFS4_VERIFIER_SIZE+20); *p++ = cpu_to_be32(OP_READDIR); p = xdr_encode_hyper(p, readdir->cookie); p = xdr_encode_opaque_fixed(p, readdir->verifier.data, NFS4_VERIFIER_SIZE); - *p++ = cpu_to_be32(dircount); + *p++ = cpu_to_be32(readdir->count >> 1); /* We're not doing readdirplus */ *p++ = cpu_to_be32(readdir->count); *p++ = cpu_to_be32(2); - + /* Switch to mounted_on_fileid if the server supports it */ + if (readdir->bitmask[1] & FATTR4_WORD1_MOUNTED_ON_FILEID) + attrs[0] &= ~FATTR4_WORD0_FILEID; + else + attrs[1] &= ~FATTR4_WORD1_MOUNTED_ON_FILEID; *p++ = cpu_to_be32(attrs[0] & readdir->bitmask[0]); *p = cpu_to_be32(attrs[1] & readdir->bitmask[1]); hdr->nops++; @@ -1834,7 +1823,7 @@ static int nfs4_xdr_enc_remove(struct rpc_rqst *req, __be32 *p, const struct nfs /* * Encode RENAME request */ -static int nfs4_xdr_enc_rename(struct rpc_rqst *req, __be32 *p, const struct nfs_renameargs *args) +static int nfs4_xdr_enc_rename(struct rpc_rqst *req, __be32 *p, const struct nfs4_rename_arg *args) { struct xdr_stream xdr; struct compound_hdr hdr = { @@ -2687,10 +2676,7 @@ static inline int decode_attr_length(struct xdr_stream *xdr, uint32_t *attrlen, static int decode_attr_supported(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t *bitmask) { if (likely(bitmap[0] & FATTR4_WORD0_SUPPORTED_ATTRS)) { - int ret; - ret = decode_attr_bitmap(xdr, bitmask); - if (unlikely(ret < 0)) - return ret; + decode_attr_bitmap(xdr, bitmask); bitmap[0] &= ~FATTR4_WORD0_SUPPORTED_ATTRS; } else bitmask[0] = bitmask[1] = 0; @@ -2862,56 +2848,6 @@ static int decode_attr_lease_time(struct xdr_stream *xdr, uint32_t *bitmap, uint return -EIO; } -static int decode_attr_error(struct xdr_stream *xdr, uint32_t *bitmap) -{ - __be32 *p; - - if (unlikely(bitmap[0] & (FATTR4_WORD0_RDATTR_ERROR - 1U))) - return -EIO; - if (likely(bitmap[0] & FATTR4_WORD0_RDATTR_ERROR)) { - p = xdr_inline_decode(xdr, 4); - if (unlikely(!p)) - goto out_overflow; - bitmap[0] &= ~FATTR4_WORD0_RDATTR_ERROR; - } - return 0; -out_overflow: - print_overflow_msg(__func__, xdr); - return -EIO; -} - -static int decode_attr_filehandle(struct xdr_stream *xdr, uint32_t *bitmap, struct nfs_fh *fh) -{ - __be32 *p; - int len; - - if (fh != NULL) - memset(fh, 0, sizeof(*fh)); - - if (unlikely(bitmap[0] & (FATTR4_WORD0_FILEHANDLE - 1U))) - return -EIO; - if (likely(bitmap[0] & FATTR4_WORD0_FILEHANDLE)) { - p = xdr_inline_decode(xdr, 4); - if (unlikely(!p)) - goto out_overflow; - len = be32_to_cpup(p); - if (len > NFS4_FHSIZE) - return -EIO; - p = xdr_inline_decode(xdr, len); - if (unlikely(!p)) - goto out_overflow; - if (fh != NULL) { - memcpy(fh->data, p, len); - fh->size = len; - } - bitmap[0] &= ~FATTR4_WORD0_FILEHANDLE; - } - return 0; -out_overflow: - print_overflow_msg(__func__, xdr); - return -EIO; -} - static int decode_attr_aclsupport(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t *res) { __be32 *p; @@ -3585,24 +3521,6 @@ static int decode_attr_time_metadata(struct xdr_stream *xdr, uint32_t *bitmap, s return status; } -static int decode_attr_time_delta(struct xdr_stream *xdr, uint32_t *bitmap, - struct timespec *time) -{ - int status = 0; - - time->tv_sec = 0; - time->tv_nsec = 0; - if (unlikely(bitmap[1] & (FATTR4_WORD1_TIME_DELTA - 1U))) - return -EIO; - if (likely(bitmap[1] & FATTR4_WORD1_TIME_DELTA)) { - status = decode_attr_time(xdr, time); - bitmap[1] &= ~FATTR4_WORD1_TIME_DELTA; - } - dprintk("%s: time_delta=%ld %ld\n", __func__, (long)time->tv_sec, - (long)time->tv_nsec); - return status; -} - static int decode_attr_time_modify(struct xdr_stream *xdr, uint32_t *bitmap, struct timespec *time) { int status = 0; @@ -3826,14 +3744,29 @@ static int decode_pathconf(struct xdr_stream *xdr, struct nfs_pathconf *pathconf return status; } -static int decode_getfattr_attrs(struct xdr_stream *xdr, uint32_t *bitmap, - struct nfs_fattr *fattr, struct nfs_fh *fh, +static int decode_getfattr(struct xdr_stream *xdr, struct nfs_fattr *fattr, const struct nfs_server *server, int may_sleep) { + __be32 *savep; + uint32_t attrlen, + bitmap[2] = {0}, + type; int status; umode_t fmode = 0; uint64_t fileid; - uint32_t type; + + status = decode_op_hdr(xdr, OP_GETATTR); + if (status < 0) + goto xdr_error; + + status = decode_attr_bitmap(xdr, bitmap); + if (status < 0) + goto xdr_error; + + status = decode_attr_length(xdr, &attrlen, &savep); + if (status < 0) + goto xdr_error; + status = decode_attr_type(xdr, bitmap, &type); if (status < 0) @@ -3859,14 +3792,6 @@ static int decode_getfattr_attrs(struct xdr_stream *xdr, uint32_t *bitmap, goto xdr_error; fattr->valid |= status; - status = decode_attr_error(xdr, bitmap); - if (status < 0) - goto xdr_error; - - status = decode_attr_filehandle(xdr, bitmap, fh); - if (status < 0) - goto xdr_error; - status = decode_attr_fileid(xdr, bitmap, &fattr->fileid); if (status < 0) goto xdr_error; @@ -3937,46 +3862,12 @@ static int decode_getfattr_attrs(struct xdr_stream *xdr, uint32_t *bitmap, fattr->valid |= status; } -xdr_error: - dprintk("%s: xdr returned %d\n", __func__, -status); - return status; -} - -static int decode_getfattr_generic(struct xdr_stream *xdr, struct nfs_fattr *fattr, - struct nfs_fh *fh, const struct nfs_server *server, int may_sleep) -{ - __be32 *savep; - uint32_t attrlen, - bitmap[2] = {0}; - int status; - - status = decode_op_hdr(xdr, OP_GETATTR); - if (status < 0) - goto xdr_error; - - status = decode_attr_bitmap(xdr, bitmap); - if (status < 0) - goto xdr_error; - - status = decode_attr_length(xdr, &attrlen, &savep); - if (status < 0) - goto xdr_error; - - status = decode_getfattr_attrs(xdr, bitmap, fattr, fh, server, may_sleep); - if (status < 0) - goto xdr_error; - status = verify_attr_len(xdr, savep, attrlen); xdr_error: dprintk("%s: xdr returned %d\n", __func__, -status); return status; } -static int decode_getfattr(struct xdr_stream *xdr, struct nfs_fattr *fattr, - const struct nfs_server *server, int may_sleep) -{ - return decode_getfattr_generic(xdr, fattr, NULL, server, may_sleep); -} static int decode_fsinfo(struct xdr_stream *xdr, struct nfs_fsinfo *fsinfo) { @@ -4003,9 +3894,6 @@ static int decode_fsinfo(struct xdr_stream *xdr, struct nfs_fsinfo *fsinfo) if ((status = decode_attr_maxwrite(xdr, bitmap, &fsinfo->wtmax)) != 0) goto xdr_error; fsinfo->wtpref = fsinfo->wtmax; - status = decode_attr_time_delta(xdr, bitmap, &fsinfo->time_delta); - if (status != 0) - goto xdr_error; status = verify_attr_len(xdr, savep, attrlen); xdr_error: @@ -4062,13 +3950,13 @@ static int decode_lock_denied (struct xdr_stream *xdr, struct file_lock *fl) __be32 *p; uint32_t namelen, type; - p = xdr_inline_decode(xdr, 32); /* read 32 bytes */ + p = xdr_inline_decode(xdr, 32); if (unlikely(!p)) goto out_overflow; - p = xdr_decode_hyper(p, &offset); /* read 2 8-byte long words */ + p = xdr_decode_hyper(p, &offset); p = xdr_decode_hyper(p, &length); - type = be32_to_cpup(p++); /* 4 byte read */ - if (fl != NULL) { /* manipulate file lock */ + type = be32_to_cpup(p++); + if (fl != NULL) { fl->fl_start = (loff_t)offset; fl->fl_end = fl->fl_start + (loff_t)length - 1; if (length == ~(uint64_t)0) @@ -4078,9 +3966,9 @@ static int decode_lock_denied (struct xdr_stream *xdr, struct file_lock *fl) fl->fl_type = F_RDLCK; fl->fl_pid = 0; } - p = xdr_decode_hyper(p, &clientid); /* read 8 bytes */ - namelen = be32_to_cpup(p); /* read 4 bytes */ /* have read all 32 bytes now */ - p = xdr_inline_decode(xdr, namelen); /* variable size field */ + p = xdr_decode_hyper(p, &clientid); + namelen = be32_to_cpup(p); + p = xdr_inline_decode(xdr, namelen); if (likely(p)) return -NFS4ERR_DENIED; out_overflow: @@ -4312,9 +4200,12 @@ static int decode_read(struct xdr_stream *xdr, struct rpc_rqst *req, struct nfs_ static int decode_readdir(struct xdr_stream *xdr, struct rpc_rqst *req, struct nfs4_readdir_res *readdir) { struct xdr_buf *rcvbuf = &req->rq_rcv_buf; + struct page *page = *rcvbuf->pages; struct kvec *iov = rcvbuf->head; size_t hdrlen; u32 recvd, pglen = rcvbuf->page_len; + __be32 *end, *entry, *p, *kaddr; + unsigned int nr = 0; int status; status = decode_op_hdr(xdr, OP_READDIR); @@ -4334,8 +4225,71 @@ static int decode_readdir(struct xdr_stream *xdr, struct rpc_rqst *req, struct n pglen = recvd; xdr_read_pages(xdr, pglen); - + BUG_ON(pglen + readdir->pgbase > PAGE_CACHE_SIZE); + kaddr = p = kmap_atomic(page, KM_USER0); + end = p + ((pglen + readdir->pgbase) >> 2); + entry = p; + + /* Make sure the packet actually has a value_follows and EOF entry */ + if ((entry + 1) > end) + goto short_pkt; + + for (; *p++; nr++) { + u32 len, attrlen, xlen; + if (end - p < 3) + goto short_pkt; + dprintk("cookie = %Lu, ", *((unsigned long long *)p)); + p += 2; /* cookie */ + len = ntohl(*p++); /* filename length */ + if (len > NFS4_MAXNAMLEN) { + dprintk("NFS: giant filename in readdir (len 0x%x)\n", + len); + goto err_unmap; + } + xlen = XDR_QUADLEN(len); + if (end - p < xlen + 1) + goto short_pkt; + dprintk("filename = %*s\n", len, (char *)p); + p += xlen; + len = ntohl(*p++); /* bitmap length */ + if (end - p < len + 1) + goto short_pkt; + p += len; + attrlen = XDR_QUADLEN(ntohl(*p++)); + if (end - p < attrlen + 2) + goto short_pkt; + p += attrlen; /* attributes */ + entry = p; + } + /* + * Apparently some server sends responses that are a valid size, but + * contain no entries, and have value_follows==0 and EOF==0. For + * those, just set the EOF marker. + */ + if (!nr && entry[1] == 0) { + dprintk("NFS: readdir reply truncated!\n"); + entry[1] = 1; + } +out: + kunmap_atomic(kaddr, KM_USER0); return 0; +short_pkt: + /* + * When we get a short packet there are 2 possibilities. We can + * return an error, or fix up the response to look like a valid + * response and return what we have so far. If there are no + * entries and the packet was short, then return -EIO. If there + * are valid entries in the response, return them and pretend that + * the call was successful, but incomplete. The caller can retry the + * readdir starting at the last cookie. + */ + dprintk("%s: short packet at entry %d\n", __func__, nr); + entry[0] = entry[1] = 0; + if (nr) + goto out; +err_unmap: + kunmap_atomic(kaddr, KM_USER0); + return -errno_NFSERR_IO; } static int decode_readlink(struct xdr_stream *xdr, struct rpc_rqst *req) @@ -4345,6 +4299,7 @@ static int decode_readlink(struct xdr_stream *xdr, struct rpc_rqst *req) size_t hdrlen; u32 len, recvd; __be32 *p; + char *kaddr; int status; status = decode_op_hdr(xdr, OP_READLINK); @@ -4375,7 +4330,9 @@ static int decode_readlink(struct xdr_stream *xdr, struct rpc_rqst *req) * and and null-terminate the text (the VFS expects * null-termination). */ - xdr_terminate_string(rcvbuf, len); + kaddr = (char *)kmap_atomic(rcvbuf->pages[0], KM_USER0); + kaddr[len+rcvbuf->page_base] = '\0'; + kunmap_atomic(kaddr, KM_USER0); return 0; out_overflow: print_overflow_msg(__func__, xdr); @@ -4711,6 +4668,7 @@ static int decode_sequence(struct xdr_stream *xdr, struct rpc_rqst *rqstp) { #if defined(CONFIG_NFS_V4_1) + struct nfs4_slot *slot; struct nfs4_sessionid id; u32 dummy; int status; @@ -4742,14 +4700,15 @@ static int decode_sequence(struct xdr_stream *xdr, goto out_overflow; /* seqid */ + slot = &res->sr_session->fc_slot_table.slots[res->sr_slotid]; dummy = be32_to_cpup(p++); - if (dummy != res->sr_slot->seq_nr) { + if (dummy != slot->seq_nr) { dprintk("%s Invalid sequence number\n", __func__); goto out_err; } /* slot id */ dummy = be32_to_cpup(p++); - if (dummy != res->sr_slot - res->sr_session->fc_slot_table.slots) { + if (dummy != res->sr_slotid) { dprintk("%s Invalid slot id\n", __func__); goto out_err; } @@ -4914,7 +4873,7 @@ static int nfs4_xdr_dec_remove(struct rpc_rqst *rqstp, __be32 *p, struct nfs_rem /* * Decode RENAME response */ -static int nfs4_xdr_dec_rename(struct rpc_rqst *rqstp, __be32 *p, struct nfs_renameres *res) +static int nfs4_xdr_dec_rename(struct rpc_rqst *rqstp, __be32 *p, struct nfs4_rename_res *res) { struct xdr_stream xdr; struct compound_hdr hdr; @@ -5801,35 +5760,23 @@ static int nfs4_xdr_dec_reclaim_complete(struct rpc_rqst *rqstp, uint32_t *p, } #endif /* CONFIG_NFS_V4_1 */ -__be32 *nfs4_decode_dirent(struct xdr_stream *xdr, struct nfs_entry *entry, - struct nfs_server *server, int plus) +__be32 *nfs4_decode_dirent(__be32 *p, struct nfs_entry *entry, int plus) { uint32_t bitmap[2] = {0}; uint32_t len; - __be32 *p = xdr_inline_decode(xdr, 4); - if (unlikely(!p)) - goto out_overflow; - if (!ntohl(*p++)) { - p = xdr_inline_decode(xdr, 4); - if (unlikely(!p)) - goto out_overflow; - if (!ntohl(*p++)) + + if (!*p++) { + if (!*p) return ERR_PTR(-EAGAIN); entry->eof = 1; return ERR_PTR(-EBADCOOKIE); } - p = xdr_inline_decode(xdr, 12); - if (unlikely(!p)) - goto out_overflow; entry->prev_cookie = entry->cookie; p = xdr_decode_hyper(p, &entry->cookie); entry->len = ntohl(*p++); - - p = xdr_inline_decode(xdr, entry->len); - if (unlikely(!p)) - goto out_overflow; entry->name = (const char *) p; + p += XDR_QUADLEN(entry->len); /* * In case the server doesn't return an inode number, @@ -5837,33 +5784,32 @@ __be32 *nfs4_decode_dirent(struct xdr_stream *xdr, struct nfs_entry *entry, * since glibc seems to choke on it...) */ entry->ino = 1; - entry->fattr->valid = 0; - - if (decode_attr_bitmap(xdr, bitmap) < 0) - goto out_overflow; - if (decode_attr_length(xdr, &len, &p) < 0) - goto out_overflow; - - if (decode_getfattr_attrs(xdr, bitmap, entry->fattr, entry->fh, server, 1) < 0) - goto out_overflow; - if (entry->fattr->valid & NFS_ATTR_FATTR_FILEID) - entry->ino = entry->fattr->fileid; - - if (verify_attr_len(xdr, p, len) < 0) - goto out_overflow; - - p = xdr_inline_peek(xdr, 8); - if (p != NULL) - entry->eof = !p[0] && p[1]; - else - entry->eof = 0; + len = ntohl(*p++); /* bitmap length */ + if (len-- > 0) { + bitmap[0] = ntohl(*p++); + if (len-- > 0) { + bitmap[1] = ntohl(*p++); + p += len; + } + } + len = XDR_QUADLEN(ntohl(*p++)); /* attribute buffer length */ + if (len > 0) { + if (bitmap[0] & FATTR4_WORD0_RDATTR_ERROR) { + bitmap[0] &= ~FATTR4_WORD0_RDATTR_ERROR; + /* Ignore the return value of rdattr_error for now */ + p++; + len--; + } + if (bitmap[0] == 0 && bitmap[1] == FATTR4_WORD1_MOUNTED_ON_FILEID) + xdr_decode_hyper(p, &entry->ino); + else if (bitmap[0] == FATTR4_WORD0_FILEID) + xdr_decode_hyper(p, &entry->ino); + p += len; + } + entry->eof = !p[0] && p[1]; return p; - -out_overflow: - print_overflow_msg(__func__, xdr); - return ERR_PTR(-EIO); } /* diff --git a/trunk/fs/nfs/nfsroot.c b/trunk/fs/nfs/nfsroot.c index 460df3652889..df101d9f546a 100644 --- a/trunk/fs/nfs/nfsroot.c +++ b/trunk/fs/nfs/nfsroot.c @@ -3,10 +3,9 @@ * * Allow an NFS filesystem to be mounted as root. The way this works is: * (1) Use the IP autoconfig mechanism to set local IP addresses and routes. - * (2) Construct the device string and the options string using DHCP - * option 17 and/or kernel command line options. - * (3) When mount_root() sets up the root file system, pass these strings - * to the NFS client's regular mount interface via sys_mount(). + * (2) Handle RPC negotiation with the system which replied to RARP or + * was reported as a boot server by BOOTP or manually. + * (3) The actual mounting is done later, when init() is running. * * * Changes: @@ -66,243 +65,470 @@ * Hua Qin : Support for mounting root file system via * NFS over TCP. * Fabian Frederick: Option parser rebuilt (using parser lib) - * Chuck Lever : Use super.c's text-based mount option parsing - * Chuck Lever : Add "nfsrootdebug". - */ +*/ #include #include +#include +#include +#include #include +#include +#include #include #include +#include +#include +#include #include +#include #include #include +#include #include "internal.h" +/* Define this to allow debugging output */ +#undef NFSROOT_DEBUG #define NFSDBG_FACILITY NFSDBG_ROOT +/* Default port to use if server is not running a portmapper */ +#define NFS_MNT_PORT 627 + /* Default path we try to mount. "%s" gets replaced by our IP address */ #define NFS_ROOT "/tftpboot/%s" /* Parameters passed from the kernel command line */ -static char nfs_root_parms[256] __initdata = ""; - -/* Text-based mount options passed to super.c */ -static char nfs_root_options[256] __initdata = ""; +static char nfs_root_name[256] __initdata = ""; /* Address of NFS server */ -static __be32 servaddr __initdata = htonl(INADDR_NONE); +static __be32 servaddr __initdata = 0; /* Name of directory to mount */ -static char nfs_export_path[NFS_MAXPATHLEN + 1] __initdata = ""; - -/* server:export path string passed to super.c */ -static char nfs_root_device[NFS_MAXPATHLEN + 1] __initdata = ""; +static char nfs_export_path[NFS_MAXPATHLEN + 1] __initdata = { 0, }; + +/* NFS-related data */ +static struct nfs_mount_data nfs_data __initdata = { 0, };/* NFS mount info */ +static int nfs_port __initdata = 0; /* Port to connect to for NFS */ +static int mount_port __initdata = 0; /* Mount daemon port number */ + + +/*************************************************************************** + + Parsing of options + + ***************************************************************************/ + +enum { + /* Options that take integer arguments */ + Opt_port, Opt_rsize, Opt_wsize, Opt_timeo, Opt_retrans, Opt_acregmin, + Opt_acregmax, Opt_acdirmin, Opt_acdirmax, + /* Options that take no arguments */ + Opt_soft, Opt_hard, Opt_intr, + Opt_nointr, Opt_posix, Opt_noposix, Opt_cto, Opt_nocto, Opt_ac, + Opt_noac, Opt_lock, Opt_nolock, Opt_v2, Opt_v3, Opt_udp, Opt_tcp, + Opt_acl, Opt_noacl, + /* Error token */ + Opt_err +}; + +static const match_table_t tokens __initconst = { + {Opt_port, "port=%u"}, + {Opt_rsize, "rsize=%u"}, + {Opt_wsize, "wsize=%u"}, + {Opt_timeo, "timeo=%u"}, + {Opt_retrans, "retrans=%u"}, + {Opt_acregmin, "acregmin=%u"}, + {Opt_acregmax, "acregmax=%u"}, + {Opt_acdirmin, "acdirmin=%u"}, + {Opt_acdirmax, "acdirmax=%u"}, + {Opt_soft, "soft"}, + {Opt_hard, "hard"}, + {Opt_intr, "intr"}, + {Opt_nointr, "nointr"}, + {Opt_posix, "posix"}, + {Opt_noposix, "noposix"}, + {Opt_cto, "cto"}, + {Opt_nocto, "nocto"}, + {Opt_ac, "ac"}, + {Opt_noac, "noac"}, + {Opt_lock, "lock"}, + {Opt_nolock, "nolock"}, + {Opt_v2, "nfsvers=2"}, + {Opt_v2, "v2"}, + {Opt_v3, "nfsvers=3"}, + {Opt_v3, "v3"}, + {Opt_udp, "proto=udp"}, + {Opt_udp, "udp"}, + {Opt_tcp, "proto=tcp"}, + {Opt_tcp, "tcp"}, + {Opt_acl, "acl"}, + {Opt_noacl, "noacl"}, + {Opt_err, NULL} + +}; /* - * When the "nfsrootdebug" kernel command line option is specified, - * enable debugging messages for NFSROOT. + * Parse option string. */ -static int __init nfs_root_debug(char *__unused) + +static int __init root_nfs_parse(char *name, char *buf) { - nfs_debug |= NFSDBG_ROOT | NFSDBG_MOUNT; + + char *p; + substring_t args[MAX_OPT_ARGS]; + int option; + + if (!name) + return 1; + + /* Set the NFS remote path */ + p = strsep(&name, ","); + if (p[0] != '\0' && strcmp(p, "default") != 0) + strlcpy(buf, p, NFS_MAXPATHLEN); + + while ((p = strsep (&name, ",")) != NULL) { + int token; + if (!*p) + continue; + token = match_token(p, tokens, args); + + /* %u tokens only. Beware if you add new tokens! */ + if (token < Opt_soft && match_int(&args[0], &option)) + return 0; + switch (token) { + case Opt_port: + nfs_port = option; + break; + case Opt_rsize: + nfs_data.rsize = option; + break; + case Opt_wsize: + nfs_data.wsize = option; + break; + case Opt_timeo: + nfs_data.timeo = option; + break; + case Opt_retrans: + nfs_data.retrans = option; + break; + case Opt_acregmin: + nfs_data.acregmin = option; + break; + case Opt_acregmax: + nfs_data.acregmax = option; + break; + case Opt_acdirmin: + nfs_data.acdirmin = option; + break; + case Opt_acdirmax: + nfs_data.acdirmax = option; + break; + case Opt_soft: + nfs_data.flags |= NFS_MOUNT_SOFT; + break; + case Opt_hard: + nfs_data.flags &= ~NFS_MOUNT_SOFT; + break; + case Opt_intr: + case Opt_nointr: + break; + case Opt_posix: + nfs_data.flags |= NFS_MOUNT_POSIX; + break; + case Opt_noposix: + nfs_data.flags &= ~NFS_MOUNT_POSIX; + break; + case Opt_cto: + nfs_data.flags &= ~NFS_MOUNT_NOCTO; + break; + case Opt_nocto: + nfs_data.flags |= NFS_MOUNT_NOCTO; + break; + case Opt_ac: + nfs_data.flags &= ~NFS_MOUNT_NOAC; + break; + case Opt_noac: + nfs_data.flags |= NFS_MOUNT_NOAC; + break; + case Opt_lock: + nfs_data.flags &= ~NFS_MOUNT_NONLM; + break; + case Opt_nolock: + nfs_data.flags |= NFS_MOUNT_NONLM; + break; + case Opt_v2: + nfs_data.flags &= ~NFS_MOUNT_VER3; + break; + case Opt_v3: + nfs_data.flags |= NFS_MOUNT_VER3; + break; + case Opt_udp: + nfs_data.flags &= ~NFS_MOUNT_TCP; + break; + case Opt_tcp: + nfs_data.flags |= NFS_MOUNT_TCP; + break; + case Opt_acl: + nfs_data.flags &= ~NFS_MOUNT_NOACL; + break; + case Opt_noacl: + nfs_data.flags |= NFS_MOUNT_NOACL; + break; + default: + printk(KERN_WARNING "Root-NFS: unknown " + "option: %s\n", p); + return 0; + } + } + return 1; } -__setup("nfsrootdebug", nfs_root_debug); - /* - * Parse NFS server and directory information passed on the kernel - * command line. - * - * nfsroot=[:][,] - * - * If there is a "%s" token in the string, it is replaced - * by the ASCII-representation of the client's IP address. + * Prepare the NFS data structure and parse all options. */ -static int __init nfs_root_setup(char *line) +static int __init root_nfs_name(char *name) { - ROOT_DEV = Root_NFS; - - if (line[0] == '/' || line[0] == ',' || (line[0] >= '0' && line[0] <= '9')) { - strlcpy(nfs_root_parms, line, sizeof(nfs_root_parms)); - } else { - size_t n = strlen(line) + sizeof(NFS_ROOT) - 1; - if (n >= sizeof(nfs_root_parms)) - line[sizeof(nfs_root_parms) - sizeof(NFS_ROOT) - 2] = '\0'; - sprintf(nfs_root_parms, NFS_ROOT, line); + static char buf[NFS_MAXPATHLEN] __initdata; + char *cp; + + /* Set some default values */ + memset(&nfs_data, 0, sizeof(nfs_data)); + nfs_port = -1; + nfs_data.version = NFS_MOUNT_VERSION; + nfs_data.flags = NFS_MOUNT_NONLM; /* No lockd in nfs root yet */ + nfs_data.rsize = NFS_DEF_FILE_IO_SIZE; + nfs_data.wsize = NFS_DEF_FILE_IO_SIZE; + nfs_data.acregmin = NFS_DEF_ACREGMIN; + nfs_data.acregmax = NFS_DEF_ACREGMAX; + nfs_data.acdirmin = NFS_DEF_ACDIRMIN; + nfs_data.acdirmax = NFS_DEF_ACDIRMAX; + strcpy(buf, NFS_ROOT); + + /* Process options received from the remote server */ + root_nfs_parse(root_server_path, buf); + + /* Override them by options set on kernel command-line */ + root_nfs_parse(name, buf); + + cp = utsname()->nodename; + if (strlen(buf) + strlen(cp) > NFS_MAXPATHLEN) { + printk(KERN_ERR "Root-NFS: Pathname for remote directory too long.\n"); + return -1; } - - /* - * Extract the IP address of the NFS server containing our - * root file system, if one was specified. - * - * Note: root_nfs_parse_addr() removes the server-ip from - * nfs_root_parms, if it exists. - */ - root_server_addr = root_nfs_parse_addr(nfs_root_parms); + sprintf(nfs_export_path, buf, cp); return 1; } -__setup("nfsroot=", nfs_root_setup); -static int __init root_nfs_copy(char *dest, const char *src, - const size_t destlen) +/* + * Get NFS server address. + */ +static int __init root_nfs_addr(void) { - if (strlcpy(dest, src, destlen) > destlen) + if ((servaddr = root_server_addr) == htonl(INADDR_NONE)) { + printk(KERN_ERR "Root-NFS: No NFS server available, giving up.\n"); return -1; - return 0; -} + } -static int __init root_nfs_cat(char *dest, const char *src, - const size_t destlen) -{ - if (strlcat(dest, src, destlen) > destlen) - return -1; + snprintf(nfs_data.hostname, sizeof(nfs_data.hostname), + "%pI4", &servaddr); return 0; } /* - * Parse out root export path and mount options from - * passed-in string @incoming. - * - * Copy the export path into @exppath. + * Tell the user what's going on. */ -static int __init root_nfs_parse_options(char *incoming, char *exppath, - const size_t exppathlen) +#ifdef NFSROOT_DEBUG +static void __init root_nfs_print(void) { - char *p; + printk(KERN_NOTICE "Root-NFS: Mounting %s on server %s as root\n", + nfs_export_path, nfs_data.hostname); + printk(KERN_NOTICE "Root-NFS: rsize = %d, wsize = %d, timeo = %d, retrans = %d\n", + nfs_data.rsize, nfs_data.wsize, nfs_data.timeo, nfs_data.retrans); + printk(KERN_NOTICE "Root-NFS: acreg (min,max) = (%d,%d), acdir (min,max) = (%d,%d)\n", + nfs_data.acregmin, nfs_data.acregmax, + nfs_data.acdirmin, nfs_data.acdirmax); + printk(KERN_NOTICE "Root-NFS: nfsd port = %d, mountd port = %d, flags = %08x\n", + nfs_port, mount_port, nfs_data.flags); +} +#endif - /* - * Set the NFS remote path - */ - p = strsep(&incoming, ","); - if (*p != '\0' && strcmp(p, "default") != 0) - if (root_nfs_copy(exppath, p, exppathlen)) - return -1; - /* - * @incoming now points to the rest of the string; if it - * contains something, append it to our root options buffer - */ - if (incoming != NULL && *incoming != '\0') - if (root_nfs_cat(nfs_root_options, incoming, - sizeof(nfs_root_options))) - return -1; +static int __init root_nfs_init(void) +{ +#ifdef NFSROOT_DEBUG + nfs_debug |= NFSDBG_ROOT; +#endif /* - * Possibly prepare for more options to be appended + * Decode the root directory path name and NFS options from + * the kernel command line. This has to go here in order to + * be able to use the client IP address for the remote root + * directory (necessary for pure RARP booting). */ - if (nfs_root_options[0] != '\0' && - nfs_root_options[strlen(nfs_root_options)] != ',') - if (root_nfs_cat(nfs_root_options, ",", - sizeof(nfs_root_options))) - return -1; + if (root_nfs_name(nfs_root_name) < 0 || + root_nfs_addr() < 0) + return -1; + +#ifdef NFSROOT_DEBUG + root_nfs_print(); +#endif return 0; } + /* - * Decode the export directory path name and NFS options from - * the kernel command line. This has to be done late in order to - * use a dynamically acquired client IP address for the remote - * root directory path. - * - * Returns zero if successful; otherwise -1 is returned. + * Parse NFS server and directory information passed on the kernel + * command line. */ -static int __init root_nfs_data(char *cmdline) +static int __init nfs_root_setup(char *line) { - char addr_option[sizeof("nolock,addr=") + INET_ADDRSTRLEN + 1]; - int len, retval = -1; - char *tmp = NULL; - const size_t tmplen = sizeof(nfs_export_path); - - tmp = kzalloc(tmplen, GFP_KERNEL); - if (tmp == NULL) - goto out_nomem; - strcpy(tmp, NFS_ROOT); - - if (root_server_path[0] != '\0') { - dprintk("Root-NFS: DHCPv4 option 17: %s\n", - root_server_path); - if (root_nfs_parse_options(root_server_path, tmp, tmplen)) - goto out_optionstoolong; + ROOT_DEV = Root_NFS; + if (line[0] == '/' || line[0] == ',' || (line[0] >= '0' && line[0] <= '9')) { + strlcpy(nfs_root_name, line, sizeof(nfs_root_name)); + } else { + int n = strlen(line) + sizeof(NFS_ROOT) - 1; + if (n >= sizeof(nfs_root_name)) + line[sizeof(nfs_root_name) - sizeof(NFS_ROOT) - 2] = '\0'; + sprintf(nfs_root_name, NFS_ROOT, line); } + root_server_addr = root_nfs_parse_addr(nfs_root_name); + return 1; +} - if (cmdline[0] != '\0') { - dprintk("Root-NFS: nfsroot=%s\n", cmdline); - if (root_nfs_parse_options(cmdline, tmp, tmplen)) - goto out_optionstoolong; - } +__setup("nfsroot=", nfs_root_setup); - /* - * Append mandatory options for nfsroot so they override - * what has come before - */ - snprintf(addr_option, sizeof(addr_option), "nolock,addr=%pI4", - &servaddr); - if (root_nfs_cat(nfs_root_options, addr_option, - sizeof(nfs_root_options))) - goto out_optionstoolong; +/*************************************************************************** - /* - * Set up nfs_root_device. For NFS mounts, this looks like - * - * server:/path - * - * At this point, utsname()->nodename contains our local - * IP address or hostname, set by ipconfig. If "%s" exists - * in tmp, substitute the nodename, then shovel the whole - * mess into nfs_root_device. - */ - len = snprintf(nfs_export_path, sizeof(nfs_export_path), - tmp, utsname()->nodename); - if (len > (int)sizeof(nfs_export_path)) - goto out_devnametoolong; - len = snprintf(nfs_root_device, sizeof(nfs_root_device), - "%pI4:%s", &servaddr, nfs_export_path); - if (len > (int)sizeof(nfs_root_device)) - goto out_devnametoolong; + Routines to actually mount the root directory - retval = 0; + ***************************************************************************/ -out: - kfree(tmp); - return retval; -out_nomem: - printk(KERN_ERR "Root-NFS: could not allocate memory\n"); - goto out; -out_optionstoolong: - printk(KERN_ERR "Root-NFS: mount options string too long\n"); - goto out; -out_devnametoolong: - printk(KERN_ERR "Root-NFS: root device name too long.\n"); - goto out; +/* + * Construct sockaddr_in from address and port number. + */ +static inline void +set_sockaddr(struct sockaddr_in *sin, __be32 addr, __be16 port) +{ + sin->sin_family = AF_INET; + sin->sin_addr.s_addr = addr; + sin->sin_port = port; } -/** - * nfs_root_data - Return prepared 'data' for NFSROOT mount - * @root_device: OUT: address of string containing NFSROOT device - * @root_data: OUT: address of string containing NFSROOT mount options - * - * Returns zero and sets @root_device and @root_data if successful, - * otherwise -1 is returned. +/* + * Query server portmapper for the port of a daemon program. */ -int __init nfs_root_data(char **root_device, char **root_data) +static int __init root_nfs_getport(int program, int version, int proto) { - servaddr = root_server_addr; - if (servaddr == htonl(INADDR_NONE)) { - printk(KERN_ERR "Root-NFS: no NFS server address\n"); - return -1; + struct sockaddr_in sin; + + printk(KERN_NOTICE "Looking up port of RPC %d/%d on %pI4\n", + program, version, &servaddr); + set_sockaddr(&sin, servaddr, 0); + return rpcb_getport_sync(&sin, program, version, proto); +} + + +/* + * Use portmapper to find mountd and nfsd port numbers if not overriden + * by the user. Use defaults if portmapper is not available. + * XXX: Is there any nfs server with no portmapper? + */ +static int __init root_nfs_ports(void) +{ + int port; + int nfsd_ver, mountd_ver; + int nfsd_port, mountd_port; + int proto; + + if (nfs_data.flags & NFS_MOUNT_VER3) { + nfsd_ver = NFS3_VERSION; + mountd_ver = NFS_MNT3_VERSION; + nfsd_port = NFS_PORT; + mountd_port = NFS_MNT_PORT; + } else { + nfsd_ver = NFS2_VERSION; + mountd_ver = NFS_MNT_VERSION; + nfsd_port = NFS_PORT; + mountd_port = NFS_MNT_PORT; } - if (root_nfs_data(nfs_root_parms) < 0) - return -1; + proto = (nfs_data.flags & NFS_MOUNT_TCP) ? IPPROTO_TCP : IPPROTO_UDP; + + if (nfs_port < 0) { + if ((port = root_nfs_getport(NFS_PROGRAM, nfsd_ver, proto)) < 0) { + printk(KERN_ERR "Root-NFS: Unable to get nfsd port " + "number from server, using default\n"); + port = nfsd_port; + } + nfs_port = port; + dprintk("Root-NFS: Portmapper on server returned %d " + "as nfsd port\n", port); + } + + if ((port = root_nfs_getport(NFS_MNT_PROGRAM, mountd_ver, proto)) < 0) { + printk(KERN_ERR "Root-NFS: Unable to get mountd port " + "number from server, using default\n"); + port = mountd_port; + } + mount_port = port; + dprintk("Root-NFS: mountd port is %d\n", port); - *root_device = nfs_root_device; - *root_data = nfs_root_options; return 0; } + + +/* + * Get a file handle from the server for the directory which is to be + * mounted. + */ +static int __init root_nfs_get_handle(void) +{ + struct sockaddr_in sin; + unsigned int auth_flav_len = 0; + struct nfs_mount_request request = { + .sap = (struct sockaddr *)&sin, + .salen = sizeof(sin), + .dirpath = nfs_export_path, + .version = (nfs_data.flags & NFS_MOUNT_VER3) ? + NFS_MNT3_VERSION : NFS_MNT_VERSION, + .protocol = (nfs_data.flags & NFS_MOUNT_TCP) ? + XPRT_TRANSPORT_TCP : XPRT_TRANSPORT_UDP, + .auth_flav_len = &auth_flav_len, + }; + int status = -ENOMEM; + + request.fh = nfs_alloc_fhandle(); + if (!request.fh) + goto out; + set_sockaddr(&sin, servaddr, htons(mount_port)); + status = nfs_mount(&request); + if (status < 0) + printk(KERN_ERR "Root-NFS: Server returned error %d " + "while mounting %s\n", status, nfs_export_path); + else { + nfs_data.root.size = request.fh->size; + memcpy(&nfs_data.root.data, request.fh->data, request.fh->size); + } + nfs_free_fhandle(request.fh); +out: + return status; +} + +/* + * Get the NFS port numbers and file handle, and return the prepared 'data' + * argument for mount() if everything went OK. Return NULL otherwise. + */ +void * __init nfs_root_data(void) +{ + if (root_nfs_init() < 0 + || root_nfs_ports() < 0 + || root_nfs_get_handle() < 0) + return NULL; + set_sockaddr((struct sockaddr_in *) &nfs_data.addr, servaddr, htons(nfs_port)); + return (void*)&nfs_data; +} diff --git a/trunk/fs/nfs/proc.c b/trunk/fs/nfs/proc.c index 58e7f84fc1fd..611bec22f552 100644 --- a/trunk/fs/nfs/proc.c +++ b/trunk/fs/nfs/proc.c @@ -258,7 +258,7 @@ static void nfs_free_createdata(const struct nfs_createdata *data) static int nfs_proc_create(struct inode *dir, struct dentry *dentry, struct iattr *sattr, - int flags, struct nfs_open_context *ctx) + int flags, struct nameidata *nd) { struct nfs_createdata *data; struct rpc_message msg = { @@ -365,32 +365,17 @@ static int nfs_proc_unlink_done(struct rpc_task *task, struct inode *dir) return 1; } -static void -nfs_proc_rename_setup(struct rpc_message *msg, struct inode *dir) -{ - msg->rpc_proc = &nfs_procedures[NFSPROC_RENAME]; -} - -static int -nfs_proc_rename_done(struct rpc_task *task, struct inode *old_dir, - struct inode *new_dir) -{ - if (nfs_async_handle_expired_key(task)) - return 0; - nfs_mark_for_revalidate(old_dir); - nfs_mark_for_revalidate(new_dir); - return 1; -} - static int nfs_proc_rename(struct inode *old_dir, struct qstr *old_name, struct inode *new_dir, struct qstr *new_name) { struct nfs_renameargs arg = { - .old_dir = NFS_FH(old_dir), - .old_name = old_name, - .new_dir = NFS_FH(new_dir), - .new_name = new_name, + .fromfh = NFS_FH(old_dir), + .fromname = old_name->name, + .fromlen = old_name->len, + .tofh = NFS_FH(new_dir), + .toname = new_name->name, + .tolen = new_name->len }; struct rpc_message msg = { .rpc_proc = &nfs_procedures[NFSPROC_RENAME], @@ -534,14 +519,14 @@ nfs_proc_rmdir(struct inode *dir, struct qstr *name) */ static int nfs_proc_readdir(struct dentry *dentry, struct rpc_cred *cred, - u64 cookie, struct page **pages, unsigned int count, int plus) + u64 cookie, struct page *page, unsigned int count, int plus) { struct inode *dir = dentry->d_inode; struct nfs_readdirargs arg = { .fh = NFS_FH(dir), .cookie = cookie, .count = count, - .pages = pages, + .pages = &page, }; struct rpc_message msg = { .rpc_proc = &nfs_procedures[NFSPROC_READDIR], @@ -720,8 +705,6 @@ const struct nfs_rpc_ops nfs_v2_clientops = { .unlink_setup = nfs_proc_unlink_setup, .unlink_done = nfs_proc_unlink_done, .rename = nfs_proc_rename, - .rename_setup = nfs_proc_rename_setup, - .rename_done = nfs_proc_rename_done, .link = nfs_proc_link, .symlink = nfs_proc_symlink, .mkdir = nfs_proc_mkdir, diff --git a/trunk/fs/nfs/read.c b/trunk/fs/nfs/read.c index 79859c81a943..87adc2744246 100644 --- a/trunk/fs/nfs/read.c +++ b/trunk/fs/nfs/read.c @@ -46,6 +46,7 @@ struct nfs_read_data *nfs_readdata_alloc(unsigned int pagecount) memset(p, 0, sizeof(*p)); INIT_LIST_HEAD(&p->pages); p->npages = pagecount; + p->res.seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE; if (pagecount <= ARRAY_SIZE(p->page_array)) p->pagevec = p->page_array; else { diff --git a/trunk/fs/nfs/super.c b/trunk/fs/nfs/super.c index 3600ec700d58..f4cbf0c306c6 100644 --- a/trunk/fs/nfs/super.c +++ b/trunk/fs/nfs/super.c @@ -100,7 +100,6 @@ enum { Opt_addr, Opt_mountaddr, Opt_clientaddr, Opt_lookupcache, Opt_fscache_uniq, - Opt_local_lock, /* Special mount options */ Opt_userspace, Opt_deprecated, Opt_sloppy, @@ -172,7 +171,6 @@ static const match_table_t nfs_mount_option_tokens = { { Opt_lookupcache, "lookupcache=%s" }, { Opt_fscache_uniq, "fsc=%s" }, - { Opt_local_lock, "local_lock=%s" }, { Opt_err, NULL } }; @@ -238,22 +236,6 @@ static match_table_t nfs_lookupcache_tokens = { { Opt_lookupcache_err, NULL } }; -enum { - Opt_local_lock_all, Opt_local_lock_flock, Opt_local_lock_posix, - Opt_local_lock_none, - - Opt_local_lock_err -}; - -static match_table_t nfs_local_lock_tokens = { - { Opt_local_lock_all, "all" }, - { Opt_local_lock_flock, "flock" }, - { Opt_local_lock_posix, "posix" }, - { Opt_local_lock_none, "none" }, - - { Opt_local_lock_err, NULL } -}; - static void nfs_umount_begin(struct super_block *); static int nfs_statfs(struct dentry *, struct kstatfs *); @@ -640,7 +622,6 @@ static void nfs_show_mount_options(struct seq_file *m, struct nfs_server *nfss, const struct proc_nfs_info *nfs_infop; struct nfs_client *clp = nfss->nfs_client; u32 version = clp->rpc_ops->version; - int local_flock, local_fcntl; seq_printf(m, ",vers=%u", version); seq_printf(m, ",rsize=%u", nfss->rsize); @@ -689,18 +670,6 @@ static void nfs_show_mount_options(struct seq_file *m, struct nfs_server *nfss, else seq_printf(m, ",lookupcache=pos"); } - - local_flock = nfss->flags & NFS_MOUNT_LOCAL_FLOCK; - local_fcntl = nfss->flags & NFS_MOUNT_LOCAL_FCNTL; - - if (!local_flock && !local_fcntl) - seq_printf(m, ",local_lock=none"); - else if (local_flock && local_fcntl) - seq_printf(m, ",local_lock=all"); - else if (local_flock) - seq_printf(m, ",local_lock=flock"); - else - seq_printf(m, ",local_lock=posix"); } /* @@ -1048,13 +1017,9 @@ static int nfs_parse_mount_options(char *raw, break; case Opt_lock: mnt->flags &= ~NFS_MOUNT_NONLM; - mnt->flags &= ~(NFS_MOUNT_LOCAL_FLOCK | - NFS_MOUNT_LOCAL_FCNTL); break; case Opt_nolock: mnt->flags |= NFS_MOUNT_NONLM; - mnt->flags |= (NFS_MOUNT_LOCAL_FLOCK | - NFS_MOUNT_LOCAL_FCNTL); break; case Opt_v2: mnt->flags &= ~NFS_MOUNT_VER3; @@ -1455,34 +1420,6 @@ static int nfs_parse_mount_options(char *raw, mnt->fscache_uniq = string; mnt->options |= NFS_OPTION_FSCACHE; break; - case Opt_local_lock: - string = match_strdup(args); - if (string == NULL) - goto out_nomem; - token = match_token(string, nfs_local_lock_tokens, - args); - kfree(string); - switch (token) { - case Opt_local_lock_all: - mnt->flags |= (NFS_MOUNT_LOCAL_FLOCK | - NFS_MOUNT_LOCAL_FCNTL); - break; - case Opt_local_lock_flock: - mnt->flags |= NFS_MOUNT_LOCAL_FLOCK; - break; - case Opt_local_lock_posix: - mnt->flags |= NFS_MOUNT_LOCAL_FCNTL; - break; - case Opt_local_lock_none: - mnt->flags &= ~(NFS_MOUNT_LOCAL_FLOCK | - NFS_MOUNT_LOCAL_FCNTL); - break; - default: - dfprintk(MOUNT, "NFS: invalid " - "local_lock argument\n"); - return 0; - }; - break; /* * Special options @@ -1888,12 +1825,6 @@ static int nfs_validate_mount_data(void *options, if (!args->nfs_server.hostname) goto out_nomem; - if (!(data->flags & NFS_MOUNT_NONLM)) - args->flags &= ~(NFS_MOUNT_LOCAL_FLOCK| - NFS_MOUNT_LOCAL_FCNTL); - else - args->flags |= (NFS_MOUNT_LOCAL_FLOCK| - NFS_MOUNT_LOCAL_FCNTL); /* * The legacy version 6 binary mount data from userspace has a * field used only to transport selinux information into the @@ -2510,8 +2441,7 @@ static void nfs4_fill_super(struct super_block *sb) static void nfs4_validate_mount_flags(struct nfs_parsed_mount_data *args) { - args->flags &= ~(NFS_MOUNT_NONLM|NFS_MOUNT_NOACL|NFS_MOUNT_VER3| - NFS_MOUNT_LOCAL_FLOCK|NFS_MOUNT_LOCAL_FCNTL); + args->flags &= ~(NFS_MOUNT_NONLM|NFS_MOUNT_NOACL|NFS_MOUNT_VER3); } static int nfs4_validate_text_mount_data(void *options, diff --git a/trunk/fs/nfs/sysctl.c b/trunk/fs/nfs/sysctl.c index 978aaeb8a093..ad4d2e787b20 100644 --- a/trunk/fs/nfs/sysctl.c +++ b/trunk/fs/nfs/sysctl.c @@ -32,7 +32,6 @@ static ctl_table nfs_cb_sysctls[] = { .extra1 = (int *)&nfs_set_port_min, .extra2 = (int *)&nfs_set_port_max, }, -#ifndef CONFIG_NFS_USE_NEW_IDMAPPER { .procname = "idmap_cache_timeout", .data = &nfs_idmap_cache_timeout, @@ -40,7 +39,6 @@ static ctl_table nfs_cb_sysctls[] = { .mode = 0644, .proc_handler = proc_dointvec_jiffies, }, -#endif /* CONFIG_NFS_USE_NEW_IDMAPPER */ #endif { .procname = "nfs_mountpoint_timeout", diff --git a/trunk/fs/nfs/unlink.c b/trunk/fs/nfs/unlink.c index 9a16bad5d2ea..2f84adaad427 100644 --- a/trunk/fs/nfs/unlink.c +++ b/trunk/fs/nfs/unlink.c @@ -13,12 +13,9 @@ #include #include #include -#include #include "internal.h" #include "nfs4_fs.h" -#include "iostat.h" -#include "delegation.h" struct nfs_unlinkdata { struct hlist_node list; @@ -247,7 +244,7 @@ void nfs_unblock_sillyrename(struct dentry *dentry) * @dir: parent directory of dentry * @dentry: dentry to unlink */ -static int +int nfs_async_unlink(struct inode *dir, struct dentry *dentry) { struct nfs_unlinkdata *data; @@ -262,6 +259,7 @@ nfs_async_unlink(struct inode *dir, struct dentry *dentry) status = PTR_ERR(data->cred); goto out_free; } + data->res.seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE; data->res.dir_attr = &data->dir_attr; status = -EBUSY; @@ -305,256 +303,3 @@ nfs_complete_unlink(struct dentry *dentry, struct inode *inode) if (data != NULL && (NFS_STALE(inode) || !nfs_call_unlink(dentry, data))) nfs_free_unlinkdata(data); } - -/* Cancel a queued async unlink. Called when a sillyrename run fails. */ -static void -nfs_cancel_async_unlink(struct dentry *dentry) -{ - spin_lock(&dentry->d_lock); - if (dentry->d_flags & DCACHE_NFSFS_RENAMED) { - struct nfs_unlinkdata *data = dentry->d_fsdata; - - dentry->d_flags &= ~DCACHE_NFSFS_RENAMED; - spin_unlock(&dentry->d_lock); - nfs_free_unlinkdata(data); - return; - } - spin_unlock(&dentry->d_lock); -} - -struct nfs_renamedata { - struct nfs_renameargs args; - struct nfs_renameres res; - struct rpc_cred *cred; - struct inode *old_dir; - struct dentry *old_dentry; - struct nfs_fattr old_fattr; - struct inode *new_dir; - struct dentry *new_dentry; - struct nfs_fattr new_fattr; -}; - -/** - * nfs_async_rename_done - Sillyrename post-processing - * @task: rpc_task of the sillyrename - * @calldata: nfs_renamedata for the sillyrename - * - * Do the directory attribute updates and the d_move - */ -static void nfs_async_rename_done(struct rpc_task *task, void *calldata) -{ - struct nfs_renamedata *data = calldata; - struct inode *old_dir = data->old_dir; - struct inode *new_dir = data->new_dir; - - if (!NFS_PROTO(old_dir)->rename_done(task, old_dir, new_dir)) { - nfs_restart_rpc(task, NFS_SERVER(old_dir)->nfs_client); - return; - } - - if (task->tk_status != 0) { - nfs_cancel_async_unlink(data->old_dentry); - return; - } - - nfs_set_verifier(data->old_dentry, nfs_save_change_attribute(old_dir)); - d_move(data->old_dentry, data->new_dentry); -} - -/** - * nfs_async_rename_release - Release the sillyrename data. - * @calldata: the struct nfs_renamedata to be released - */ -static void nfs_async_rename_release(void *calldata) -{ - struct nfs_renamedata *data = calldata; - struct super_block *sb = data->old_dir->i_sb; - - if (data->old_dentry->d_inode) - nfs_mark_for_revalidate(data->old_dentry->d_inode); - - dput(data->old_dentry); - dput(data->new_dentry); - iput(data->old_dir); - iput(data->new_dir); - nfs_sb_deactive(sb); - put_rpccred(data->cred); - kfree(data); -} - -#if defined(CONFIG_NFS_V4_1) -static void nfs_rename_prepare(struct rpc_task *task, void *calldata) -{ - struct nfs_renamedata *data = calldata; - struct nfs_server *server = NFS_SERVER(data->old_dir); - - if (nfs4_setup_sequence(server, &data->args.seq_args, - &data->res.seq_res, 1, task)) - return; - rpc_call_start(task); -} -#endif /* CONFIG_NFS_V4_1 */ - -static const struct rpc_call_ops nfs_rename_ops = { - .rpc_call_done = nfs_async_rename_done, - .rpc_release = nfs_async_rename_release, -#if defined(CONFIG_NFS_V4_1) - .rpc_call_prepare = nfs_rename_prepare, -#endif /* CONFIG_NFS_V4_1 */ -}; - -/** - * nfs_async_rename - perform an asynchronous rename operation - * @old_dir: directory that currently holds the dentry to be renamed - * @new_dir: target directory for the rename - * @old_dentry: original dentry to be renamed - * @new_dentry: dentry to which the old_dentry should be renamed - * - * It's expected that valid references to the dentries and inodes are held - */ -static struct rpc_task * -nfs_async_rename(struct inode *old_dir, struct inode *new_dir, - struct dentry *old_dentry, struct dentry *new_dentry) -{ - struct nfs_renamedata *data; - struct rpc_message msg = { }; - struct rpc_task_setup task_setup_data = { - .rpc_message = &msg, - .callback_ops = &nfs_rename_ops, - .workqueue = nfsiod_workqueue, - .rpc_client = NFS_CLIENT(old_dir), - .flags = RPC_TASK_ASYNC, - }; - - data = kzalloc(sizeof(*data), GFP_KERNEL); - if (data == NULL) - return ERR_PTR(-ENOMEM); - task_setup_data.callback_data = data, - - data->cred = rpc_lookup_cred(); - if (IS_ERR(data->cred)) { - struct rpc_task *task = ERR_CAST(data->cred); - kfree(data); - return task; - } - - msg.rpc_argp = &data->args; - msg.rpc_resp = &data->res; - msg.rpc_cred = data->cred; - - /* set up nfs_renamedata */ - data->old_dir = old_dir; - atomic_inc(&old_dir->i_count); - data->new_dir = new_dir; - atomic_inc(&new_dir->i_count); - data->old_dentry = dget(old_dentry); - data->new_dentry = dget(new_dentry); - nfs_fattr_init(&data->old_fattr); - nfs_fattr_init(&data->new_fattr); - - /* set up nfs_renameargs */ - data->args.old_dir = NFS_FH(old_dir); - data->args.old_name = &old_dentry->d_name; - data->args.new_dir = NFS_FH(new_dir); - data->args.new_name = &new_dentry->d_name; - - /* set up nfs_renameres */ - data->res.old_fattr = &data->old_fattr; - data->res.new_fattr = &data->new_fattr; - - nfs_sb_active(old_dir->i_sb); - - NFS_PROTO(data->old_dir)->rename_setup(&msg, old_dir); - - return rpc_run_task(&task_setup_data); -} - -/** - * nfs_sillyrename - Perform a silly-rename of a dentry - * @dir: inode of directory that contains dentry - * @dentry: dentry to be sillyrenamed - * - * NFSv2/3 is stateless and the server doesn't know when the client is - * holding a file open. To prevent application problems when a file is - * unlinked while it's still open, the client performs a "silly-rename". - * That is, it renames the file to a hidden file in the same directory, - * and only performs the unlink once the last reference to it is put. - * - * The final cleanup is done during dentry_iput. - */ -int -nfs_sillyrename(struct inode *dir, struct dentry *dentry) -{ - static unsigned int sillycounter; - const int fileidsize = sizeof(NFS_FILEID(dentry->d_inode))*2; - const int countersize = sizeof(sillycounter)*2; - const int slen = sizeof(".nfs")+fileidsize+countersize-1; - char silly[slen+1]; - struct dentry *sdentry; - struct rpc_task *task; - int error = -EIO; - - dfprintk(VFS, "NFS: silly-rename(%s/%s, ct=%d)\n", - dentry->d_parent->d_name.name, dentry->d_name.name, - atomic_read(&dentry->d_count)); - nfs_inc_stats(dir, NFSIOS_SILLYRENAME); - - /* - * We don't allow a dentry to be silly-renamed twice. - */ - error = -EBUSY; - if (dentry->d_flags & DCACHE_NFSFS_RENAMED) - goto out; - - sprintf(silly, ".nfs%*.*Lx", - fileidsize, fileidsize, - (unsigned long long)NFS_FILEID(dentry->d_inode)); - - /* Return delegation in anticipation of the rename */ - nfs_inode_return_delegation(dentry->d_inode); - - sdentry = NULL; - do { - char *suffix = silly + slen - countersize; - - dput(sdentry); - sillycounter++; - sprintf(suffix, "%*.*x", countersize, countersize, sillycounter); - - dfprintk(VFS, "NFS: trying to rename %s to %s\n", - dentry->d_name.name, silly); - - sdentry = lookup_one_len(silly, dentry->d_parent, slen); - /* - * N.B. Better to return EBUSY here ... it could be - * dangerous to delete the file while it's in use. - */ - if (IS_ERR(sdentry)) - goto out; - } while (sdentry->d_inode != NULL); /* need negative lookup */ - - /* queue unlink first. Can't do this from rpc_release as it - * has to allocate memory - */ - error = nfs_async_unlink(dir, dentry); - if (error) - goto out_dput; - - /* run the rename task, undo unlink if it fails */ - task = nfs_async_rename(dir, dir, dentry, sdentry); - if (IS_ERR(task)) { - error = -EBUSY; - nfs_cancel_async_unlink(dentry); - goto out_dput; - } - - /* wait for the RPC task to complete, unless a SIGKILL intervenes */ - error = rpc_wait_for_completion_task(task); - if (error == 0) - error = task->tk_status; - rpc_put_task(task); -out_dput: - dput(sdentry); -out: - return error; -} diff --git a/trunk/fs/nfs/write.c b/trunk/fs/nfs/write.c index 605e292501f4..874972d9427c 100644 --- a/trunk/fs/nfs/write.c +++ b/trunk/fs/nfs/write.c @@ -55,6 +55,7 @@ struct nfs_write_data *nfs_commitdata_alloc(void) if (p) { memset(p, 0, sizeof(*p)); INIT_LIST_HEAD(&p->pages); + p->res.seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE; } return p; } @@ -74,6 +75,7 @@ struct nfs_write_data *nfs_writedata_alloc(unsigned int pagecount) memset(p, 0, sizeof(*p)); INIT_LIST_HEAD(&p->pages); p->npages = pagecount; + p->res.seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE; if (pagecount <= ARRAY_SIZE(p->page_array)) p->pagevec = p->page_array; else { @@ -1431,17 +1433,15 @@ static int nfs_commit_unstable_pages(struct inode *inode, struct writeback_contr int flags = FLUSH_SYNC; int ret = 0; - if (wbc->sync_mode == WB_SYNC_NONE) { - /* Don't commit yet if this is a non-blocking flush and there - * are a lot of outstanding writes for this mapping. - */ - if (nfsi->ncommit <= (nfsi->npages >> 1)) - goto out_mark_dirty; + /* Don't commit yet if this is a non-blocking flush and there are + * lots of outstanding writes for this mapping. + */ + if (wbc->sync_mode == WB_SYNC_NONE && + nfsi->ncommit <= (nfsi->npages >> 1)) + goto out_mark_dirty; - /* don't wait for the COMMIT response */ + if (wbc->nonblocking || wbc->for_background) flags = 0; - } - ret = nfs_commit_inode(inode, flags); if (ret >= 0) { if (wbc->sync_mode == WB_SYNC_NONE) { diff --git a/trunk/include/linux/nfs_fs.h b/trunk/include/linux/nfs_fs.h index a46e430d9622..d0edf7d823ae 100644 --- a/trunk/include/linux/nfs_fs.h +++ b/trunk/include/linux/nfs_fs.h @@ -360,13 +360,10 @@ extern void nfs_setattr_update_inode(struct inode *inode, struct iattr *attr); extern struct nfs_open_context *get_nfs_open_context(struct nfs_open_context *ctx); extern void put_nfs_open_context(struct nfs_open_context *ctx); extern struct nfs_open_context *nfs_find_open_context(struct inode *inode, struct rpc_cred *cred, fmode_t mode); -extern struct nfs_open_context *alloc_nfs_open_context(struct path *path, struct rpc_cred *cred, fmode_t f_mode); -extern void nfs_file_set_open_context(struct file *filp, struct nfs_open_context *ctx); extern struct nfs_lock_context *nfs_get_lock_context(struct nfs_open_context *ctx); extern void nfs_put_lock_context(struct nfs_lock_context *l_ctx); extern u64 nfs_compat_user_ino64(u64 fileid); extern void nfs_fattr_init(struct nfs_fattr *fattr); -extern unsigned long nfs_inc_attr_generation_counter(void); extern struct nfs_fattr *nfs_alloc_fattr(void); @@ -382,12 +379,9 @@ static inline void nfs_free_fhandle(const struct nfs_fh *fh) kfree(fh); } -/* - * linux/fs/nfs/nfsroot.c - */ -extern int nfs_root_data(char **root_device, char **root_data); /*__init*/ /* linux/net/ipv4/ipconfig.c: trims ip addr off front of name, too. */ extern __be32 root_nfs_parse_addr(char *name); /*__init*/ +extern unsigned long nfs_inc_attr_generation_counter(void); /* * linux/fs/nfs/file.c @@ -485,10 +479,10 @@ extern void nfs_release_automount_timer(void); /* * linux/fs/nfs/unlink.c */ +extern int nfs_async_unlink(struct inode *dir, struct dentry *dentry); extern void nfs_complete_unlink(struct dentry *dentry, struct inode *); extern void nfs_block_sillyrename(struct dentry *dentry); extern void nfs_unblock_sillyrename(struct dentry *dentry); -extern int nfs_sillyrename(struct inode *dir, struct dentry *dentry); /* * linux/fs/nfs/write.c @@ -590,6 +584,10 @@ nfs_fileid_to_ino_t(u64 fileid) return ino; } +/* NFS root */ + +extern void * nfs_root_data(void); + #define nfs_wait_event(clnt, wq, condition) \ ({ \ int __retval = wait_event_killable(wq, condition); \ diff --git a/trunk/include/linux/nfs_fs_sb.h b/trunk/include/linux/nfs_fs_sb.h index 5eef862ec187..c82ee7cd6288 100644 --- a/trunk/include/linux/nfs_fs_sb.h +++ b/trunk/include/linux/nfs_fs_sb.h @@ -124,7 +124,6 @@ struct nfs_server { struct nfs_fsid fsid; __u64 maxfilesize; /* maximum file size */ - struct timespec time_delta; /* smallest time granularity */ unsigned long mount_time; /* when this fs was mounted */ dev_t s_dev; /* superblock dev numbers */ diff --git a/trunk/include/linux/nfs_idmap.h b/trunk/include/linux/nfs_idmap.h index e8352dc5afb5..91a1c24e0cbf 100644 --- a/trunk/include/linux/nfs_idmap.h +++ b/trunk/include/linux/nfs_idmap.h @@ -66,40 +66,13 @@ struct idmap_msg { /* Forward declaration to make this header independent of others */ struct nfs_client; -#ifdef CONFIG_NFS_USE_NEW_IDMAPPER - -int nfs_idmap_init(void); -void nfs_idmap_quit(void); - -static inline int nfs_idmap_new(struct nfs_client *clp) -{ - return 0; -} - -static inline void nfs_idmap_delete(struct nfs_client *clp) -{ -} - -#else /* CONFIG_NFS_USE_NEW_IDMAPPER not set */ - -static inline int nfs_idmap_init(void) -{ - return 0; -} - -static inline void nfs_idmap_quit(void) -{ -} - int nfs_idmap_new(struct nfs_client *); void nfs_idmap_delete(struct nfs_client *); -#endif /* CONFIG_NFS_USE_NEW_IDMAPPER */ - int nfs_map_name_to_uid(struct nfs_client *, const char *, size_t, __u32 *); int nfs_map_group_to_gid(struct nfs_client *, const char *, size_t, __u32 *); -int nfs_map_uid_to_name(struct nfs_client *, __u32, char *, size_t); -int nfs_map_gid_to_group(struct nfs_client *, __u32, char *, size_t); +int nfs_map_uid_to_name(struct nfs_client *, __u32, char *); +int nfs_map_gid_to_group(struct nfs_client *, __u32, char *); extern unsigned int nfs_idmap_cache_timeout; #endif /* __KERNEL__ */ diff --git a/trunk/include/linux/nfs_mount.h b/trunk/include/linux/nfs_mount.h index 576bddd72e04..5d59ae861aa6 100644 --- a/trunk/include/linux/nfs_mount.h +++ b/trunk/include/linux/nfs_mount.h @@ -71,7 +71,4 @@ struct nfs_mount_data { #define NFS_MOUNT_NORESVPORT 0x40000 #define NFS_MOUNT_LEGACY_INTERFACE 0x80000 -#define NFS_MOUNT_LOCAL_FLOCK 0x100000 -#define NFS_MOUNT_LOCAL_FCNTL 0x200000 - #endif diff --git a/trunk/include/linux/nfs_xdr.h b/trunk/include/linux/nfs_xdr.h index da7a1300dc60..fc461926c412 100644 --- a/trunk/include/linux/nfs_xdr.h +++ b/trunk/include/linux/nfs_xdr.h @@ -112,7 +112,6 @@ struct nfs_fsinfo { __u32 wtmult; /* writes should be multiple of this */ __u32 dtpref; /* pref. readdir transfer size */ __u64 maxfilesize; - struct timespec time_delta; /* server time granularity */ __u32 lease_time; /* in seconds */ }; @@ -171,7 +170,7 @@ struct nfs4_sequence_args { struct nfs4_sequence_res { struct nfs4_session *sr_session; - struct nfs4_slot *sr_slot; /* slot used to send request */ + u8 sr_slotid; /* slot used to send request */ int sr_status; /* sequence operation status */ unsigned long sr_renewal_time; u32 sr_status_flags; @@ -400,27 +399,6 @@ struct nfs_removeres { struct nfs4_sequence_res seq_res; }; -/* - * Common arguments to the rename call - */ -struct nfs_renameargs { - const struct nfs_fh *old_dir; - const struct nfs_fh *new_dir; - const struct qstr *old_name; - const struct qstr *new_name; - const u32 *bitmask; - struct nfs4_sequence_args seq_args; -}; - -struct nfs_renameres { - const struct nfs_server *server; - struct nfs4_change_info old_cinfo; - struct nfs_fattr *old_fattr; - struct nfs4_change_info new_cinfo; - struct nfs_fattr *new_fattr; - struct nfs4_sequence_res seq_res; -}; - /* * Argument struct for decode_entry function */ @@ -456,6 +434,15 @@ struct nfs_createargs { struct iattr * sattr; }; +struct nfs_renameargs { + struct nfs_fh * fromfh; + const char * fromname; + unsigned int fromlen; + struct nfs_fh * tofh; + const char * toname; + unsigned int tolen; +}; + struct nfs_setattrargs { struct nfs_fh * fh; nfs4_stateid stateid; @@ -599,6 +586,15 @@ struct nfs3_mknodargs { dev_t rdev; }; +struct nfs3_renameargs { + struct nfs_fh * fromfh; + const char * fromname; + unsigned int fromlen; + struct nfs_fh * tofh; + const char * toname; + unsigned int tolen; +}; + struct nfs3_linkargs { struct nfs_fh * fromfh; struct nfs_fh * tofh; @@ -633,6 +629,11 @@ struct nfs3_readlinkargs { struct page ** pages; }; +struct nfs3_renameres { + struct nfs_fattr * fromattr; + struct nfs_fattr * toattr; +}; + struct nfs3_linkres { struct nfs_fattr * dir_attr; struct nfs_fattr * fattr; @@ -779,7 +780,6 @@ struct nfs4_readdir_arg { struct page ** pages; /* zero-copy data */ unsigned int pgbase; /* zero-copy data */ const u32 * bitmask; - int plus; struct nfs4_sequence_args seq_args; }; @@ -801,6 +801,24 @@ struct nfs4_readlink_res { struct nfs4_sequence_res seq_res; }; +struct nfs4_rename_arg { + const struct nfs_fh * old_dir; + const struct nfs_fh * new_dir; + const struct qstr * old_name; + const struct qstr * new_name; + const u32 * bitmask; + struct nfs4_sequence_args seq_args; +}; + +struct nfs4_rename_res { + const struct nfs_server * server; + struct nfs4_change_info old_cinfo; + struct nfs_fattr * old_fattr; + struct nfs4_change_info new_cinfo; + struct nfs_fattr * new_fattr; + struct nfs4_sequence_res seq_res; +}; + #define NFS4_SETCLIENTID_NAMELEN (127) struct nfs4_setclientid { const nfs4_verifier * sc_verifier; @@ -1014,21 +1032,19 @@ struct nfs_rpc_ops { int (*readlink)(struct inode *, struct page *, unsigned int, unsigned int); int (*create) (struct inode *, struct dentry *, - struct iattr *, int, struct nfs_open_context *); + struct iattr *, int, struct nameidata *); int (*remove) (struct inode *, struct qstr *); void (*unlink_setup) (struct rpc_message *, struct inode *dir); int (*unlink_done) (struct rpc_task *, struct inode *); int (*rename) (struct inode *, struct qstr *, struct inode *, struct qstr *); - void (*rename_setup) (struct rpc_message *msg, struct inode *dir); - int (*rename_done) (struct rpc_task *task, struct inode *old_dir, struct inode *new_dir); int (*link) (struct inode *, struct inode *, struct qstr *); int (*symlink) (struct inode *, struct dentry *, struct page *, unsigned int, struct iattr *); int (*mkdir) (struct inode *, struct dentry *, struct iattr *); int (*rmdir) (struct inode *, struct qstr *); int (*readdir) (struct dentry *, struct rpc_cred *, - u64, struct page **, unsigned int, int); + u64, struct page *, unsigned int, int); int (*mknod) (struct inode *, struct dentry *, struct iattr *, dev_t); int (*statfs) (struct nfs_server *, struct nfs_fh *, @@ -1038,7 +1054,7 @@ struct nfs_rpc_ops { int (*pathconf) (struct nfs_server *, struct nfs_fh *, struct nfs_pathconf *); int (*set_capabilities)(struct nfs_server *, struct nfs_fh *); - __be32 *(*decode_dirent)(struct xdr_stream *, struct nfs_entry *, struct nfs_server *, int plus); + __be32 *(*decode_dirent)(__be32 *, struct nfs_entry *, int plus); void (*read_setup) (struct nfs_read_data *, struct rpc_message *); int (*read_done) (struct rpc_task *, struct nfs_read_data *); void (*write_setup) (struct nfs_write_data *, struct rpc_message *); @@ -1049,10 +1065,6 @@ struct nfs_rpc_ops { int (*lock_check_bounds)(const struct file_lock *); void (*clear_acl_cache)(struct inode *); void (*close_context)(struct nfs_open_context *ctx, int); - struct inode * (*open_context) (struct inode *dir, - struct nfs_open_context *ctx, - int open_flags, - struct iattr *iattr); }; /* diff --git a/trunk/include/linux/serial_core.h b/trunk/include/linux/serial_core.h index 212eb4c67797..99e5994e6f84 100644 --- a/trunk/include/linux/serial_core.h +++ b/trunk/include/linux/serial_core.h @@ -196,9 +196,6 @@ /* High Speed UART for Medfield */ #define PORT_MFD 95 -/* TI OMAP-UART */ -#define PORT_OMAP 96 - #ifdef __KERNEL__ #include diff --git a/trunk/include/linux/sunrpc/clnt.h b/trunk/include/linux/sunrpc/clnt.h index c83df09a8e2b..85f38a63f098 100644 --- a/trunk/include/linux/sunrpc/clnt.h +++ b/trunk/include/linux/sunrpc/clnt.h @@ -137,6 +137,7 @@ int rpcb_register(u32, u32, int, unsigned short); int rpcb_v4_register(const u32 program, const u32 version, const struct sockaddr *address, const char *netid); +int rpcb_getport_sync(struct sockaddr_in *, u32, u32, int); void rpcb_getport_async(struct rpc_task *); void rpc_call_start(struct rpc_task *); diff --git a/trunk/include/linux/sunrpc/xdr.h b/trunk/include/linux/sunrpc/xdr.h index ab91d86565fd..35cf2e8cd7c6 100644 --- a/trunk/include/linux/sunrpc/xdr.h +++ b/trunk/include/linux/sunrpc/xdr.h @@ -108,7 +108,6 @@ void xdr_encode_pages(struct xdr_buf *, struct page **, unsigned int, unsigned int); void xdr_inline_pages(struct xdr_buf *, unsigned int, struct page **, unsigned int, unsigned int); -void xdr_terminate_string(struct xdr_buf *, const u32); static inline __be32 *xdr_encode_array(__be32 *p, const void *s, unsigned int len) { @@ -201,7 +200,6 @@ extern __be32 *xdr_reserve_space(struct xdr_stream *xdr, size_t nbytes); extern void xdr_write_pages(struct xdr_stream *xdr, struct page **pages, unsigned int base, unsigned int len); extern void xdr_init_decode(struct xdr_stream *xdr, struct xdr_buf *buf, __be32 *p); -extern __be32 *xdr_inline_peek(struct xdr_stream *xdr, size_t nbytes); extern __be32 *xdr_inline_decode(struct xdr_stream *xdr, size_t nbytes); extern void xdr_read_pages(struct xdr_stream *xdr, unsigned int len); extern void xdr_enter_page(struct xdr_stream *xdr, unsigned int len); diff --git a/trunk/init/do_mounts.c b/trunk/init/do_mounts.c index 62a47eafa8e9..42db0551c3aa 100644 --- a/trunk/init/do_mounts.c +++ b/trunk/init/do_mounts.c @@ -361,13 +361,13 @@ void __init mount_block_root(char *name, int flags) #ifdef CONFIG_ROOT_NFS static int __init mount_nfs_root(void) { - char *root_dev, *root_data; + void *data = nfs_root_data(); - if (nfs_root_data(&root_dev, &root_data) != 0) - return 0; - if (do_mount_root(root_dev, "nfs", root_mountflags, root_data) != 0) - return 0; - return 1; + create_dev("/dev/root", ROOT_DEV); + if (data && + do_mount_root("/dev/root", "nfs", root_mountflags, data) == 0) + return 1; + return 0; } #endif diff --git a/trunk/kernel/workqueue.c b/trunk/kernel/workqueue.c index e5ff2cbaadc2..30acdb74cc23 100644 --- a/trunk/kernel/workqueue.c +++ b/trunk/kernel/workqueue.c @@ -2791,9 +2791,7 @@ static int alloc_cwqs(struct workqueue_struct *wq) } } - /* just in case, make sure it's actually aligned - * - this is affected by PERCPU() alignment in vmlinux.lds.S - */ + /* just in case, make sure it's actually aligned */ BUG_ON(!IS_ALIGNED(wq->cpu_wq.v, align)); return wq->cpu_wq.v ? 0 : -ENOMEM; } diff --git a/trunk/net/sunrpc/auth.c b/trunk/net/sunrpc/auth.c index 68192e562749..e9eaaf7d43c1 100644 --- a/trunk/net/sunrpc/auth.c +++ b/trunk/net/sunrpc/auth.c @@ -595,7 +595,7 @@ rpcauth_unwrap_resp(struct rpc_task *task, kxdrproc_t decode, void *rqstp, int rpcauth_refreshcred(struct rpc_task *task) { - struct rpc_cred *cred; + struct rpc_cred *cred = task->tk_rqstp->rq_cred; int err; cred = task->tk_rqstp->rq_cred; diff --git a/trunk/net/sunrpc/clnt.c b/trunk/net/sunrpc/clnt.c index cbc5b8ccc8be..fa5549079d79 100644 --- a/trunk/net/sunrpc/clnt.c +++ b/trunk/net/sunrpc/clnt.c @@ -1675,7 +1675,7 @@ rpc_verify_header(struct rpc_task *task) rpcauth_invalcred(task); /* Ensure we obtain a new XID! */ xprt_release(task); - task->tk_action = call_reserve; + task->tk_action = call_refresh; goto out_retry; case RPC_AUTH_BADCRED: case RPC_AUTH_BADVERF: diff --git a/trunk/net/sunrpc/rpcb_clnt.c b/trunk/net/sunrpc/rpcb_clnt.c index 63ec116b4dd4..dac219a56ae1 100644 --- a/trunk/net/sunrpc/rpcb_clnt.c +++ b/trunk/net/sunrpc/rpcb_clnt.c @@ -211,9 +211,8 @@ static int rpcb_create_local(void) */ clnt4 = rpc_bind_new_program(clnt, &rpcb_program, RPCBVERS_4); if (IS_ERR(clnt4)) { - dprintk("RPC: failed to bind second program to " - "rpcbind v4 client (errno %ld).\n", - PTR_ERR(clnt4)); + dprintk("RPC: failed to create local rpcbind v4 " + "cleint (errno %ld).\n", PTR_ERR(clnt4)); clnt4 = NULL; } @@ -476,6 +475,57 @@ int rpcb_v4_register(const u32 program, const u32 version, return -EAFNOSUPPORT; } +/** + * rpcb_getport_sync - obtain the port for an RPC service on a given host + * @sin: address of remote peer + * @prog: RPC program number to bind + * @vers: RPC version number to bind + * @prot: transport protocol to use to make this request + * + * Return value is the requested advertised port number, + * or a negative errno value. + * + * Called from outside the RPC client in a synchronous task context. + * Uses default timeout parameters specified by underlying transport. + * + * XXX: Needs to support IPv6 + */ +int rpcb_getport_sync(struct sockaddr_in *sin, u32 prog, u32 vers, int prot) +{ + struct rpcbind_args map = { + .r_prog = prog, + .r_vers = vers, + .r_prot = prot, + .r_port = 0, + }; + struct rpc_message msg = { + .rpc_proc = &rpcb_procedures2[RPCBPROC_GETPORT], + .rpc_argp = &map, + .rpc_resp = &map, + }; + struct rpc_clnt *rpcb_clnt; + int status; + + dprintk("RPC: %s(%pI4, %u, %u, %d)\n", + __func__, &sin->sin_addr.s_addr, prog, vers, prot); + + rpcb_clnt = rpcb_create(NULL, (struct sockaddr *)sin, + sizeof(*sin), prot, RPCBVERS_2); + if (IS_ERR(rpcb_clnt)) + return PTR_ERR(rpcb_clnt); + + status = rpc_call_sync(rpcb_clnt, &msg, 0); + rpc_shutdown_client(rpcb_clnt); + + if (status >= 0) { + if (map.r_port != 0) + return map.r_port; + status = -EACCES; + } + return status; +} +EXPORT_SYMBOL_GPL(rpcb_getport_sync); + static struct rpc_task *rpcb_call_async(struct rpc_clnt *rpcb_clnt, struct rpcbind_args *map, struct rpc_procinfo *proc) { struct rpc_message msg = { diff --git a/trunk/net/sunrpc/sched.c b/trunk/net/sunrpc/sched.c index 243fc09b164e..aa5dbda6608c 100644 --- a/trunk/net/sunrpc/sched.c +++ b/trunk/net/sunrpc/sched.c @@ -908,7 +908,7 @@ static int rpciod_start(void) * Create the rpciod thread and wait for it to start. */ dprintk("RPC: creating workqueue rpciod\n"); - wq = alloc_workqueue("rpciod", WQ_RESCUER, 0); + wq = create_workqueue("rpciod"); rpciod_workqueue = wq; return rpciod_workqueue != NULL; } diff --git a/trunk/net/sunrpc/xdr.c b/trunk/net/sunrpc/xdr.c index cd9e841e7492..a1f82a87d34d 100644 --- a/trunk/net/sunrpc/xdr.c +++ b/trunk/net/sunrpc/xdr.c @@ -111,23 +111,6 @@ xdr_decode_string_inplace(__be32 *p, char **sp, } EXPORT_SYMBOL_GPL(xdr_decode_string_inplace); -/** - * xdr_terminate_string - '\0'-terminate a string residing in an xdr_buf - * @buf: XDR buffer where string resides - * @len: length of string, in bytes - * - */ -void -xdr_terminate_string(struct xdr_buf *buf, const u32 len) -{ - char *kaddr; - - kaddr = kmap_atomic(buf->pages[0], KM_USER0); - kaddr[buf->page_base + len] = '\0'; - kunmap_atomic(kaddr, KM_USER0); -} -EXPORT_SYMBOL(xdr_terminate_string); - void xdr_encode_pages(struct xdr_buf *xdr, struct page **pages, unsigned int base, unsigned int len) @@ -412,29 +395,24 @@ xdr_shrink_pagelen(struct xdr_buf *buf, size_t len) { struct kvec *tail; size_t copy; + char *p; unsigned int pglen = buf->page_len; - unsigned int tailbuf_len; tail = buf->tail; BUG_ON (len > pglen); - tailbuf_len = buf->buflen - buf->head->iov_len - buf->page_len; - /* Shift the tail first */ - if (tailbuf_len != 0) { - unsigned int free_space = tailbuf_len - tail->iov_len; - - if (len < free_space) - free_space = len; - tail->iov_len += free_space; - - copy = len; + if (tail->iov_len != 0) { + p = (char *)tail->iov_base + len; if (tail->iov_len > len) { - char *p = (char *)tail->iov_base + len; - memmove(p, tail->iov_base, tail->iov_len - len); + copy = tail->iov_len - len; + memmove(p, tail->iov_base, copy); } else - copy = tail->iov_len; + buf->buflen -= len; /* Copy from the inlined pages into the tail */ + copy = len; + if (copy > tail->iov_len) + copy = tail->iov_len; _copy_from_pages((char *)tail->iov_base, buf->pages, buf->page_base + pglen - len, copy); @@ -572,27 +550,6 @@ void xdr_init_decode(struct xdr_stream *xdr, struct xdr_buf *buf, __be32 *p) } EXPORT_SYMBOL_GPL(xdr_init_decode); -/** - * xdr_inline_peek - Allow read-ahead in the XDR data stream - * @xdr: pointer to xdr_stream struct - * @nbytes: number of bytes of data to decode - * - * Check if the input buffer is long enough to enable us to decode - * 'nbytes' more bytes of data starting at the current position. - * If so return the current pointer without updating the current - * pointer position. - */ -__be32 * xdr_inline_peek(struct xdr_stream *xdr, size_t nbytes) -{ - __be32 *p = xdr->p; - __be32 *q = p + XDR_QUADLEN(nbytes); - - if (unlikely(q > xdr->end || q < p)) - return NULL; - return p; -} -EXPORT_SYMBOL_GPL(xdr_inline_peek); - /** * xdr_inline_decode - Retrieve non-page XDR data to decode * @xdr: pointer to xdr_stream struct diff --git a/trunk/sound/soc/omap/omap-mcbsp.c b/trunk/sound/soc/omap/omap-mcbsp.c index d211c9fa5a91..99696187b55a 100644 --- a/trunk/sound/soc/omap/omap-mcbsp.c +++ b/trunk/sound/soc/omap/omap-mcbsp.c @@ -31,6 +31,7 @@ #include #include +#include #include #include #include "omap-mcbsp.h" @@ -597,6 +598,93 @@ static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, return 0; } +static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data, + int clk_id) +{ + int sel_bit; + u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1; + + if (cpu_class_is_omap1()) { + /* OMAP1's can use only external source clock */ + if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)) + return -EINVAL; + else + return 0; + } + + if (cpu_is_omap2420() && mcbsp_data->bus_id > 1) + return -EINVAL; + + if (cpu_is_omap343x()) + reg_devconf1 = OMAP343X_CONTROL_DEVCONF1; + + switch (mcbsp_data->bus_id) { + case 0: + reg = OMAP2_CONTROL_DEVCONF0; + sel_bit = 2; + break; + case 1: + reg = OMAP2_CONTROL_DEVCONF0; + sel_bit = 6; + break; + case 2: + reg = reg_devconf1; + sel_bit = 0; + break; + case 3: + reg = reg_devconf1; + sel_bit = 2; + break; + case 4: + reg = reg_devconf1; + sel_bit = 4; + break; + default: + return -EINVAL; + } + + if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK) + omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg); + else + omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg); + + return 0; +} + +static int omap_mcbsp_dai_set_rcvr_src(struct omap_mcbsp_data *mcbsp_data, + int clk_id) +{ + int sel_bit, set = 0; + u16 reg = OMAP2_CONTROL_DEVCONF0; + + if (cpu_class_is_omap1()) + return -EINVAL; /* TODO: Can this be implemented for OMAP1? */ + if (mcbsp_data->bus_id != 0) + return -EINVAL; + + switch (clk_id) { + case OMAP_MCBSP_CLKR_SRC_CLKX: + set = 1; + case OMAP_MCBSP_CLKR_SRC_CLKR: + sel_bit = 3; + break; + case OMAP_MCBSP_FSR_SRC_FSX: + set = 1; + case OMAP_MCBSP_FSR_SRC_FSR: + sel_bit = 4; + break; + default: + return -EINVAL; + } + + if (set) + omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg); + else + omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg); + + return 0; +} + static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, unsigned int freq, int dir) @@ -605,14 +693,6 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; int err = 0; - /* The McBSP signal muxing functions are only available on McBSP1 */ - if (clk_id == OMAP_MCBSP_CLKR_SRC_CLKR || - clk_id == OMAP_MCBSP_CLKR_SRC_CLKX || - clk_id == OMAP_MCBSP_FSR_SRC_FSR || - clk_id == OMAP_MCBSP_FSR_SRC_FSX) - if (cpu_class_is_omap1() || mcbsp_data->bus_id != 0) - return -EINVAL; - mcbsp_data->in_freq = freq; switch (clk_id) { @@ -620,20 +700,8 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, regs->srgr2 |= CLKSM; break; case OMAP_MCBSP_SYSCLK_CLKS_FCLK: - if (cpu_class_is_omap1()) { - err = -EINVAL; - break; - } - err = omap2_mcbsp_set_clks_src(mcbsp_data->bus_id, - MCBSP_CLKS_PRCM_SRC); - break; case OMAP_MCBSP_SYSCLK_CLKS_EXT: - if (cpu_class_is_omap1()) { - err = 0; - break; - } - err = omap2_mcbsp_set_clks_src(mcbsp_data->bus_id, - MCBSP_CLKS_PAD_SRC); + err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id); break; case OMAP_MCBSP_SYSCLK_CLKX_EXT: @@ -642,18 +710,11 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, regs->pcr0 |= SCLKME; break; - case OMAP_MCBSP_CLKR_SRC_CLKR: - omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKR); - break; case OMAP_MCBSP_CLKR_SRC_CLKX: - omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKX); - break; case OMAP_MCBSP_FSR_SRC_FSR: - omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSR); - break; case OMAP_MCBSP_FSR_SRC_FSX: - omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSX); + err = omap_mcbsp_dai_set_rcvr_src(mcbsp_data, clk_id); break; default: err = -ENODEV; diff --git a/trunk/sound/soc/omap/omap-mcpdm.c b/trunk/sound/soc/omap/omap-mcpdm.c index bed09c27e44c..f161c2f5ed36 100644 --- a/trunk/sound/soc/omap/omap-mcpdm.c +++ b/trunk/sound/soc/omap/omap-mcpdm.c @@ -32,6 +32,7 @@ #include #include +#include #include #include #include "mcpdm.h"