From 0c50f91004d87d6d9cc1b0d0672b8c916ceaa295 Mon Sep 17 00:00:00 2001 From: Clemens Ladisch Date: Thu, 10 Jun 2010 08:34:13 +0200 Subject: [PATCH] --- yaml --- r: 206811 b: refs/heads/master c: 27a2329f8235d6ce637463f5d83e98d760ef006e h: refs/heads/master i: 206809: 231607dee17d8aa38ab4c26cce8016c7db8f585c 206807: a64bbad21554a28ea750297da74c2a6755f0ced3 v: v3 --- [refs] | 2 +- trunk/drivers/firewire/core-transaction.c | 14 +++++++++++--- trunk/drivers/firewire/ohci.c | 14 +++++++++++++- 3 files changed, 25 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index 56ca82fb1f15..2610a26c29e5 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: a48777e03ad53777ed119a5f86dd22a6c5a378ad +refs/heads/master: 27a2329f8235d6ce637463f5d83e98d760ef006e diff --git a/trunk/drivers/firewire/core-transaction.c b/trunk/drivers/firewire/core-transaction.c index 2a390726fa76..8146133818dc 100644 --- a/trunk/drivers/firewire/core-transaction.c +++ b/trunk/drivers/firewire/core-transaction.c @@ -1115,6 +1115,17 @@ static void handle_registers(struct fw_card *card, struct fw_request *request, rcode = RCODE_TYPE_ERROR; break; + case CSR_BUSY_TIMEOUT: + if (tcode == TCODE_READ_QUADLET_REQUEST) + *data = cpu_to_be32(card->driver-> + read_csr_reg(card, CSR_BUSY_TIMEOUT)); + else if (tcode == TCODE_WRITE_QUADLET_REQUEST) + card->driver->write_csr_reg(card, CSR_BUSY_TIMEOUT, + be32_to_cpu(*data)); + else + rcode = RCODE_TYPE_ERROR; + break; + case CSR_BROADCAST_CHANNEL: if (tcode == TCODE_READ_QUADLET_REQUEST) *data = cpu_to_be32(card->broadcast_channel); @@ -1140,9 +1151,6 @@ static void handle_registers(struct fw_card *card, struct fw_request *request, BUG(); break; - case CSR_BUSY_TIMEOUT: - /* FIXME: Implement this. */ - default: rcode = RCODE_ADDRESS_ERROR; break; diff --git a/trunk/drivers/firewire/ohci.c b/trunk/drivers/firewire/ohci.c index 3d4badb7c79b..9c588fd01250 100644 --- a/trunk/drivers/firewire/ohci.c +++ b/trunk/drivers/firewire/ohci.c @@ -1731,7 +1731,8 @@ static int ohci_enable(struct fw_card *card, reg_write(ohci, OHCI1394_ATRetries, OHCI1394_MAX_AT_REQ_RETRIES | (OHCI1394_MAX_AT_RESP_RETRIES << 4) | - (OHCI1394_MAX_PHYS_RESP_RETRIES << 8)); + (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | + (200 << 16)); seconds = lower_32_bits(get_seconds()); reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25); @@ -2023,6 +2024,10 @@ static u32 ohci_read_csr_reg(struct fw_card *card, int csr_offset) spin_unlock_irqrestore(&ohci->lock, flags); return value; + case CSR_BUSY_TIMEOUT: + value = reg_read(ohci, OHCI1394_ATRetries); + return (value >> 4) & 0x0ffff00f; + default: WARN_ON(1); return 0; @@ -2053,6 +2058,13 @@ static void ohci_write_csr_reg(struct fw_card *card, int csr_offset, u32 value) spin_unlock_irqrestore(&ohci->lock, flags); break; + case CSR_BUSY_TIMEOUT: + value = (value & 0xf) | ((value & 0xf) << 4) | + ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); + reg_write(ohci, OHCI1394_ATRetries, value); + flush_writes(ohci); + break; + default: WARN_ON(1); break;