From 0c73908c9c24e3958abe15c60d5410f0ce75ae99 Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Mon, 17 Oct 2011 15:51:52 -0700 Subject: [PATCH] --- yaml --- r: 269828 b: refs/heads/master c: d15bf23bc025ded52054ac3a05d6433a54e43fd2 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/iommu/intel-iommu.c | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 66e3ef9a1216..96ebb32f44ed 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 130c2561dea1c7418e53c1db2282b91a38641abe +refs/heads/master: d15bf23bc025ded52054ac3a05d6433a54e43fd2 diff --git a/trunk/drivers/iommu/intel-iommu.c b/trunk/drivers/iommu/intel-iommu.c index c621c98c99da..ff266034ead8 100644 --- a/trunk/drivers/iommu/intel-iommu.c +++ b/trunk/drivers/iommu/intel-iommu.c @@ -3950,7 +3950,11 @@ static void __devinit quirk_calpella_no_shadow_gtt(struct pci_dev *dev) if (!(ggc & GGC_MEMORY_VT_ENABLED)) { printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n"); dmar_map_gfx = 0; - } + } else if (dmar_map_gfx) { + /* we have to ensure the gfx device is idle before we flush */ + printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n"); + intel_iommu_strict = 1; + } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);