From 0d5e3581db2f338343c5fec26a1a97df0d1787cc Mon Sep 17 00:00:00 2001
From: Michael Chan <mchan@broadcom.com>
Date: Wed, 22 Mar 2006 01:05:31 -0800
Subject: [PATCH] --- yaml --- r: 22665 b: refs/heads/master c:
 caf636c760b33c72ebf018ff03c1b0d79ea6656a h: refs/heads/master i:   22663:
 0be08472f06e853ad44a09f070e5ac261cac6e3f v: v3

---
 [refs]                  |  2 +-
 trunk/drivers/net/tg3.c | 12 +++++++++---
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/[refs] b/[refs]
index b7a38676d7bc..90644f920c97 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 9a6b9f2e763a1d1492e164f13c13b995a9b98d78
+refs/heads/master: caf636c760b33c72ebf018ff03c1b0d79ea6656a
diff --git a/trunk/drivers/net/tg3.c b/trunk/drivers/net/tg3.c
index e03d1ae50c3e..cb687fcaae1f 100644
--- a/trunk/drivers/net/tg3.c
+++ b/trunk/drivers/net/tg3.c
@@ -9436,12 +9436,18 @@ static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
 	return NULL;
 }
 
-/* Since this function may be called in D3-hot power state during
- * tg3_init_one(), only config cycles are allowed.
- */
 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
 {
 	u32 val;
+	u16 pmcsr;
+
+	/* On some early chips the SRAM cannot be accessed in D3hot state,
+	 * so need make sure we're in D0.
+	 */
+	pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
+	pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
+	pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
+	msleep(1);
 
 	/* Make sure register accesses (indirect or otherwise)
 	 * will function correctly.