From 0da3ea989117e56c637657758647fc9c6cf0c868 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Wed, 31 Oct 2012 19:23:16 +0000 Subject: [PATCH] --- yaml --- r: 345482 b: refs/heads/master c: 42d42e7e4220753bab3eb7b857721f203a4cd821 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_bios.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index e49bfeceb946..1bf900b07e27 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 607a6f7a6621f65706ff536b2615ee65b5c2f575 +refs/heads/master: 42d42e7e4220753bab3eb7b857721f203a4cd821 diff --git a/trunk/drivers/gpu/drm/i915/intel_bios.c b/trunk/drivers/gpu/drm/i915/intel_bios.c index 0ed6baff4b0c..87e9b92039df 100644 --- a/trunk/drivers/gpu/drm/i915/intel_bios.c +++ b/trunk/drivers/gpu/drm/i915/intel_bios.c @@ -762,7 +762,8 @@ void intel_setup_bios(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; /* Set the Panel Power On/Off timings if uninitialized. */ - if ((I915_READ(PP_ON_DELAYS) == 0) && (I915_READ(PP_OFF_DELAYS) == 0)) { + if (!HAS_PCH_SPLIT(dev) && + I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) { /* Set T2 to 40ms and T5 to 200ms */ I915_WRITE(PP_ON_DELAYS, 0x019007d0);