From 0db98914179ddb12dea2b571078ee6a62fc14ac7 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Wed, 6 Mar 2013 20:03:14 -0300 Subject: [PATCH] --- yaml --- r: 371195 b: refs/heads/master c: ca291363ccc7c0e9b337fe3b46f732247238537e h: refs/heads/master i: 371193: 5f4cec85a68b123b6335b2d784fc581d518ea4fa 371191: 89231576bc6be3af6da8482583292440b1cdeb1a v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_display.c | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index c0bf4c86466a..7feba81f4383 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 51889b35224cb05b5a9d187f3ebf872653ae06d2 +refs/heads/master: ca291363ccc7c0e9b337fe3b46f732247238537e diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index 1e706769de66..630a96770043 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -9349,7 +9349,8 @@ intel_display_capture_error_state(struct drm_device *dev) if (INTEL_INFO(dev)->gen <= 3) error->plane[i].size = I915_READ(DSPSIZE(i)); error->plane[i].pos = I915_READ(DSPPOS(i)); - error->plane[i].addr = I915_READ(DSPADDR(i)); + if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) + error->plane[i].addr = I915_READ(DSPADDR(i)); if (INTEL_INFO(dev)->gen >= 4) { error->plane[i].surface = I915_READ(DSPSURF(i)); error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); @@ -9394,7 +9395,8 @@ intel_display_print_error_state(struct seq_file *m, if (INTEL_INFO(dev)->gen <= 3) seq_printf(m, " SIZE: %08x\n", error->plane[i].size); seq_printf(m, " POS: %08x\n", error->plane[i].pos); - seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); + if (!IS_HASWELL(dev)) + seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); if (INTEL_INFO(dev)->gen >= 4) { seq_printf(m, " SURF: %08x\n", error->plane[i].surface); seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);