From 0e3ea7d2bdd600396bdd7f8bf547ce3e2412de6c Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Thu, 2 Feb 2012 11:23:14 +0800 Subject: [PATCH] --- yaml --- r: 287385 b: refs/heads/master c: 529febeee680dc22416fca033151a5e8bc620447 h: refs/heads/master i: 287383: d89a53f074d3f8e26dfd949ec877767f69f4b85f v: v3 --- [refs] | 2 +- trunk/drivers/usb/host/ehci-fsl.c | 11 +++++++++-- trunk/drivers/usb/host/ehci-fsl.h | 1 + 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 5a0441eb561d..49995ce5032f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: ed2833ac7ee86ee00f6dd3085a32752209fd8b6e +refs/heads/master: 529febeee680dc22416fca033151a5e8bc620447 diff --git a/trunk/drivers/usb/host/ehci-fsl.c b/trunk/drivers/usb/host/ehci-fsl.c index b556a72264d1..c26a82e83f6e 100644 --- a/trunk/drivers/usb/host/ehci-fsl.c +++ b/trunk/drivers/usb/host/ehci-fsl.c @@ -239,7 +239,7 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci, ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); } -static void ehci_fsl_usb_setup(struct ehci_hcd *ehci) +static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) { struct usb_hcd *hcd = ehci_to_hcd(ehci); struct fsl_usb2_platform_data *pdata; @@ -299,12 +299,19 @@ static void ehci_fsl_usb_setup(struct ehci_hcd *ehci) #endif out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001); } + + if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & CTRL_PHY_CLK_VALID)) { + printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n"); + return -ENODEV; + } + return 0; } /* called after powerup, by probe or system-pm "wakeup" */ static int ehci_fsl_reinit(struct ehci_hcd *ehci) { - ehci_fsl_usb_setup(ehci); + if (ehci_fsl_usb_setup(ehci)) + return -ENODEV; ehci_port_power(ehci, 0); return 0; diff --git a/trunk/drivers/usb/host/ehci-fsl.h b/trunk/drivers/usb/host/ehci-fsl.h index 491806221165..bdf43e2adc51 100644 --- a/trunk/drivers/usb/host/ehci-fsl.h +++ b/trunk/drivers/usb/host/ehci-fsl.h @@ -45,5 +45,6 @@ #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */ #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ +#define CTRL_PHY_CLK_VALID (1 << 17) #define SNOOP_SIZE_2GB 0x1e #endif /* _EHCI_FSL_H */