From 0e5fd9393c96229f7994d53d24facad75b60019e Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Tue, 23 Apr 2013 12:01:51 +0530 Subject: [PATCH] --- yaml --- r: 372507 b: refs/heads/master c: 37746c9a2dd28d52790dd84267b848c087a63b2e h: refs/heads/master i: 372505: 943cc78e9970b7f5aa0981a3b07716165ea0f0da 372503: 92ca66fd2e7d1940445f07d41eb501a9763a9149 v: v3 --- [refs] | 2 +- trunk/drivers/clk/samsung/clk-exynos5250.c | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/[refs] b/[refs] index 11b3876b1db2..4c09a4c5fd6d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: db60074b468c5935760bd1f33cd192fae3c28b2b +refs/heads/master: 37746c9a2dd28d52790dd84267b848c087a63b2e diff --git a/trunk/drivers/clk/samsung/clk-exynos5250.c b/trunk/drivers/clk/samsung/clk-exynos5250.c index 7290faa518d2..bb54606ff035 100644 --- a/trunk/drivers/clk/samsung/clk-exynos5250.c +++ b/trunk/drivers/clk/samsung/clk-exynos5250.c @@ -276,10 +276,10 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = { DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8), DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4), - DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 8, 8), - DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 24, 8), - DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 8, 8), - DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 24, 8), + DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), + DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), + DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), + DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4), DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4), DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4), @@ -421,13 +421,13 @@ struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { SRC_MASK_DISP1_0, 20, 0, 0), GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0), - GATE(sclk_mmc0, "sclk_mmc0", "div_mmc0", + GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0), - GATE(sclk_mmc1, "sclk_mmc1", "div_mmc1", + GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0), - GATE(sclk_mmc2, "sclk_mmc2", "div_mmc2", + GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0), - GATE(sclk_mmc3, "sclk_mmc3", "div_mmc3", + GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0), GATE(sclk_sata, "sclk_sata", "div_sata", SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),