From 0e930e41faede326443ee164aba60aa2918677f9 Mon Sep 17 00:00:00 2001
From: Stephane Eranian <eranian@hpl.hp.com>
Date: Thu, 7 Dec 2006 02:14:02 +0100
Subject: [PATCH] --- yaml --- r: 43013 b: refs/heads/master c:
 bb0d977ed42c79ed709c79dbab4ff2159941eb2a h: refs/heads/master i:   43011:
 033fe60c7f18d4a882c3ed780ce4192715f3bee6 v: v3

---
 [refs]                       |  2 +-
 trunk/include/asm-i386/msr.h | 13 +++++++++++++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 4496df3081de..a9b9422c78f2 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 86efef50cfff9905c4e4ec64f3d3d3b299226674
+refs/heads/master: bb0d977ed42c79ed709c79dbab4ff2159941eb2a
diff --git a/trunk/include/asm-i386/msr.h b/trunk/include/asm-i386/msr.h
index 62b76cd96957..1820d9d73af3 100644
--- a/trunk/include/asm-i386/msr.h
+++ b/trunk/include/asm-i386/msr.h
@@ -141,6 +141,10 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val)
 #define MSR_IA32_MC0_ADDR		0x402
 #define MSR_IA32_MC0_MISC		0x403
 
+#define MSR_IA32_PEBS_ENABLE		0x3f1
+#define MSR_IA32_DS_AREA		0x600
+#define MSR_IA32_PERF_CAPABILITIES	0x345
+
 /* Pentium IV performance counter MSRs */
 #define MSR_P4_BPU_PERFCTR0 		0x300
 #define MSR_P4_BPU_PERFCTR1 		0x301
@@ -284,4 +288,13 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val)
 #define MSR_TMTA_LRTI_READOUT		0x80868018
 #define MSR_TMTA_LRTI_VOLT_MHZ		0x8086801a
 
+/* Intel Core-based CPU performance counters */
+#define MSR_CORE_PERF_FIXED_CTR0	0x309
+#define MSR_CORE_PERF_FIXED_CTR1	0x30a
+#define MSR_CORE_PERF_FIXED_CTR2	0x30b
+#define MSR_CORE_PERF_FIXED_CTR_CTRL	0x38d
+#define MSR_CORE_PERF_GLOBAL_STATUS	0x38e
+#define MSR_CORE_PERF_GLOBAL_CTRL	0x38f
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL	0x390
+
 #endif /* __ASM_MSR_H */