From 0eb681fc84fad709b0f1fb56e9ade5dc3498a291 Mon Sep 17 00:00:00 2001 From: Matt Carlson Date: Mon, 12 Nov 2007 21:19:37 -0800 Subject: [PATCH] --- yaml --- r: 73611 b: refs/heads/master c: 5f5c51e3d473d8ddc0c32156c2b27e2fe92b9b57 h: refs/heads/master i: 73609: 99bd1fc1a62051c6415a119ebaf72d93b785708e 73607: 86f34b37cb861c3e537c15b21478a12159456daa v: v3 --- [refs] | 2 +- trunk/drivers/net/tg3.c | 8 +++++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 90c70e1e6a8e..611d97c886eb 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: aa6c91fe5913faa2cd2a62de993a3130799412b1 +refs/heads/master: 5f5c51e3d473d8ddc0c32156c2b27e2fe92b9b57 diff --git a/trunk/drivers/net/tg3.c b/trunk/drivers/net/tg3.c index ecd64a224e95..72db78b1ec3b 100644 --- a/trunk/drivers/net/tg3.c +++ b/trunk/drivers/net/tg3.c @@ -5098,12 +5098,15 @@ static void tg3_restore_pci_state(struct tg3 *tp) pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); - if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { + if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) + pcie_set_readrq(tp->pdev, 4096); + else { pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, tp->pci_cacheline_sz); pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, tp->pci_lat_timer); } + /* Make sure PCI-X relaxed ordering bit is clear. */ if (tp->pcix_cap) { u16 pcix_cmd; @@ -11215,6 +11218,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); if (pcie_cap != 0) { tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; + + pcie_set_readrq(tp->pdev, 4096); + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { u16 lnkctl;