From 0f07a26a792ea85c1419d90ba23123f8ad231607 Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Tue, 9 Nov 2010 15:31:08 +1000
Subject: [PATCH] --- yaml --- r: 231823 b: refs/heads/master c:
 0ef6c9b8f7bf62ea05be5b26ee14b18a116b0c2a h: refs/heads/master i:   231821:
 9edf1027c0c641fc35ceb4782ff9a2a6efa66a0e   231819:
 d2e69fb55b362931d13e84b751474c0c260f286f   231815:
 d316f0e7a7112f06477577e267ce0039f42a29b9   231807:
 7b237b1860a0ef95c60d98a9525de8e14a414fef v: v3

---
 [refs]                                 |  2 +-
 trunk/arch/m68k/include/asm/m52xxacr.h | 30 +++++++++++++-----------
 trunk/arch/m68knommu/Kconfig           | 32 ++++++++++++++++++++++++++
 3 files changed, 49 insertions(+), 15 deletions(-)

diff --git a/[refs] b/[refs]
index 3dffda5192fd..6b8c2116a3c4 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: d475e3e4739ce465df740b51decbbea3b1b51823
+refs/heads/master: 0ef6c9b8f7bf62ea05be5b26ee14b18a116b0c2a
diff --git a/trunk/arch/m68k/include/asm/m52xxacr.h b/trunk/arch/m68k/include/asm/m52xxacr.h
index 52230b5e1e4d..701f680bced9 100644
--- a/trunk/arch/m68k/include/asm/m52xxacr.h
+++ b/trunk/arch/m68k/include/asm/m52xxacr.h
@@ -53,23 +53,25 @@
 #define ACR_WPROTECT	0x00000004	/* Write protect region */
 
 /*
- * Set the cache controller settings we will use. This code is set to
- * only use the instruction cache, even on the controllers that support
- * split cache. (This setup is trying to preserve the existing behavior
- * for now, in the furture I hope to actually use the split cache mode).
+ * Set the cache controller settings we will use. On the cores that support
+ * a split cache configuration we allow all the combinations at Kconfig
+ * time. For those cores that only have an instruction cache we just set
+ * that as on.
  */
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
-    defined(CONFIG_M5249) || defined(CONFIG_M5272)
-#define CACHE_INIT	(CACR_CINV)
-#define CACHE_MODE	(CACR_CENB + CACR_DCM)
+#if defined(CONFIG_CACHE_I)
+#define CACHE_TYPE	CACR_DISD
+#elif defined(CONFIG_CACHE_D)
+#define CACHE_TYPE	CACR_DISI
 #else
-#ifdef CONFIG_COLDFIRE_SW_A7
-#define CACHE_INIT	(CACR_CINV + CACR_DISD)
-#define CACHE_MODE	(CACR_CENB + CACR_DISD + CACR_DCM)
-#else
-#define CACHE_INIT	(CACR_CINV + CACR_DISD + CACR_EUSP)
-#define CACHE_MODE	(CACR_CENB + CACR_DISD + CACR_DCM + CACR_EUSP)
+#define CACHE_TYPE
 #endif
+
+#if defined(CONFIG_HAVE_CACHE_SPLIT)
+#define CACHE_INIT	(CACR_CINV + CACHE_TYPE + CACR_EUSP)
+#define CACHE_MODE	(CACR_CENB + CACHE_TYPE + CACR_DCM + CACR_EUSP)
+#else
+#define CACHE_INIT	(CACR_CINV)
+#define CACHE_MODE	(CACR_CENB + CACR_DCM)
 #endif
 
 #define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV)
diff --git a/trunk/arch/m68knommu/Kconfig b/trunk/arch/m68knommu/Kconfig
index e6f482d18d05..61c29081b998 100644
--- a/trunk/arch/m68knommu/Kconfig
+++ b/trunk/arch/m68knommu/Kconfig
@@ -79,6 +79,9 @@ config COLDFIRE_SW_A7
 	bool
 	default n
 
+config HAVE_CACHE_SPLIT
+	bool
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
@@ -124,12 +127,14 @@ config M5206e
 config M520x
 	bool "MCF520x"
 	select GENERIC_CLOCKEVENTS
+	select HAVE_CACHE_SPLIT
 	help
 	   Freescale Coldfire 5207/5208 processor support.
 
 config M523x
 	bool "MCF523x"
 	select GENERIC_CLOCKEVENTS
+	select HAVE_CACHE_SPLIT
 	help
 	  Freescale Coldfire 5230/1/2/4/5 processor support
 
@@ -141,6 +146,7 @@ config M5249
 
 config M5271
 	bool "MCF5271"
+	select HAVE_CACHE_SPLIT
 	help
 	  Freescale (Motorola) ColdFire 5270/5271 processor support.
 
@@ -152,12 +158,14 @@ config M5272
 
 config M5275
 	bool "MCF5275"
+	select HAVE_CACHE_SPLIT
 	help
 	  Freescale (Motorola) ColdFire 5274/5275 processor support.
 
 config M528x
 	bool "MCF528x"
 	select GENERIC_CLOCKEVENTS
+	select HAVE_CACHE_SPLIT
 	help
 	  Motorola ColdFire 5280/5282 processor support.
 
@@ -250,6 +258,30 @@ config OLDMASK
 	  Build support for the older revision ColdFire 5307 silicon.
 	  Specifically this is the 1H55J mask revision.
 
+if HAVE_CACHE_SPLIT
+choice
+	prompt "Split Cache Configuration"
+	default CACHE_I
+
+config CACHE_I
+	bool "Instruction"
+	help
+	  Use all of the ColdFire CPU cache memory as an instruction cache.
+
+config CACHE_D
+	bool "Data"
+	help
+	  Use all of the ColdFire CPU cache memory as a data cache.
+
+config CACHE_BOTH
+	bool "Both"
+	help
+	  Split the ColdFire CPU cache, and use half as an instruction cache
+	  and half as a data cache.
+endchoice
+
+endif
+
 comment "Platform"
 
 config PILOT3