From 0f67e7e6d00f115d2fbf7de5cd5617fdeb1d27be Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Tue, 1 Nov 2011 20:03:29 +0100 Subject: [PATCH] --- yaml --- r: 284687 b: refs/heads/master c: fb469f084fdf1631e31d87270f5263c20a7f5cd6 h: refs/heads/master i: 284685: 625851455c1d3466d1e3ed21a6bf434c6a3e4061 284683: 9f091760655ed1082e290959a8ce805b7365909e 284679: 5b25328f62b0543f5881f2889a55913da5437923 284671: f5eec5e12b3479b7ebab9615d97c3c1300b54b6e v: v3 --- [refs] | 2 +- trunk/arch/mips/alchemy/devboards/bcsr.c | 11 ++--------- 2 files changed, 3 insertions(+), 10 deletions(-) diff --git a/[refs] b/[refs] index ceeb7ee15cfe..ea5cf69713a0 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 435037c630dcd984cf95c9cfff973f8626cea368 +refs/heads/master: fb469f084fdf1631e31d87270f5263c20a7f5cd6 diff --git a/trunk/arch/mips/alchemy/devboards/bcsr.c b/trunk/arch/mips/alchemy/devboards/bcsr.c index 463d2c4d9441..1e83ce2e1147 100644 --- a/trunk/arch/mips/alchemy/devboards/bcsr.c +++ b/trunk/arch/mips/alchemy/devboards/bcsr.c @@ -97,14 +97,9 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d) enable_irq(irq); } -/* NOTE: both the enable and mask bits must be cleared, otherwise the - * CPLD generates tons of spurious interrupts (at least on my DB1200). - * -- mlau - */ static void bcsr_irq_mask(struct irq_data *d) { unsigned short v = 1 << (d->irq - bcsr_csc_base); - __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR); __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); wmb(); } @@ -112,7 +107,6 @@ static void bcsr_irq_mask(struct irq_data *d) static void bcsr_irq_maskack(struct irq_data *d) { unsigned short v = 1 << (d->irq - bcsr_csc_base); - __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR); __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */ wmb(); @@ -121,7 +115,6 @@ static void bcsr_irq_maskack(struct irq_data *d) static void bcsr_irq_unmask(struct irq_data *d) { unsigned short v = 1 << (d->irq - bcsr_csc_base); - __raw_writew(v, bcsr_virt + BCSR_REG_INTSET); __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET); wmb(); } @@ -137,9 +130,9 @@ void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq) { unsigned int irq; - /* mask & disable & ack all */ - __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTCLR); + /* mask & enable & ack all */ __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR); + __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSET); __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT); wmb();