From 0fa69b87fee068880e96e4d0a087a0f93510d906 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Thu, 7 Oct 2010 16:01:15 -0700 Subject: [PATCH] --- yaml --- r: 218293 b: refs/heads/master c: 5b2adf897146edeac6a1e438fb67b5a53dbbdf34 h: refs/heads/master i: 218291: 1af5bebe3c3b66bfc74d6e07295e97ecc1981f87 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_reg.h | 1 + trunk/drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 0f7134581a9d..6a0dcf42e751 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 9f0e7ff4b366d27570cbe0ffa137ed1018009114 +refs/heads/master: 5b2adf897146edeac6a1e438fb67b5a53dbbdf34 diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h index a72335e940f1..5a22887a5381 100644 --- a/trunk/drivers/gpu/drm/i915/i915_reg.h +++ b/trunk/drivers/gpu/drm/i915/i915_reg.h @@ -2782,6 +2782,7 @@ #define FDI_RXA_CHICKEN 0xc200c #define FDI_RXB_CHICKEN 0xc2010 #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1) +#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, FDI_RXA_CHICKEN, FDI_RXB_CHICKEN) /* CPU: FDI_TX */ #define FDI_TXA_CTL 0x60100 diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index 349710a8014c..5812fc7c5a0f 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -1714,6 +1714,9 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc) POSTING_READ(reg); udelay(150); + /* Ironlake workaround, enable clock pointer after FDI enable*/ + I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE); + reg = FDI_RX_IIR(pipe); for (tries = 0; tries < 5; tries++) { temp = I915_READ(reg); @@ -2192,6 +2195,11 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) POSTING_READ(reg); udelay(100); + /* Ironlake workaround, disable clock pointer after downing FDI */ + I915_WRITE(FDI_RX_CHICKEN(pipe), + I915_READ(FDI_RX_CHICKEN(pipe) & + ~FDI_RX_PHASE_SYNC_POINTER_ENABLE)); + /* still set train pattern 1 */ reg = FDI_TX_CTL(pipe); temp = I915_READ(reg);