From 0fd70e7fc5db6c73c93475f50bc8adaf31195faf Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 14 Sep 2012 16:25:12 +1000 Subject: [PATCH] --- yaml --- r: 331425 b: refs/heads/master c: d72a5abb7edfccde54776b2600f735c4e10234a6 h: refs/heads/master i: 331423: fc1cbef536ef8e0fb4f774f8e71319335abc86f4 v: v3 --- [refs] | 2 +- trunk/arch/m68k/include/asm/m5272sim.h | 26 +++++++++++------------ trunk/arch/m68k/platform/coldfire/m5272.c | 5 +---- 3 files changed, 15 insertions(+), 18 deletions(-) diff --git a/[refs] b/[refs] index d4d9a7c9c2a6..7d65ceeaf11e 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 35142b915bd1307fef4316848a4c5dc5b38836f4 +refs/heads/master: d72a5abb7edfccde54776b2600f735c4e10234a6 diff --git a/trunk/arch/m68k/include/asm/m5272sim.h b/trunk/arch/m68k/include/asm/m5272sim.h index 3a5319e57062..52d1a33887d1 100644 --- a/trunk/arch/m68k/include/asm/m5272sim.h +++ b/trunk/arch/m68k/include/asm/m5272sim.h @@ -21,11 +21,11 @@ /* * Define the 5272 SIM register set addresses. */ -#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */ -#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/ -#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */ -#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */ -#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */ +#define MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */ +#define MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */ +#define MCFSIM_PMR (MCF_MBAR + 0x08) /* Power Management */ +#define MCFSIM_APMR (MCF_MBAR + 0x0e) /* Active Low Power */ +#define MCFSIM_DIR (MCF_MBAR + 0x10) /* Device Identity */ #define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */ #define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */ @@ -59,14 +59,14 @@ #define MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */ #define MCFSIM_CSOR7 (MCF_MBAR + 0x7c) /* CS7 Option */ -#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */ -#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */ -#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */ -#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */ -#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */ -#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ -#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ +#define MCFSIM_SDCR (MCF_MBAR + 0x180) /* SDRAM Config */ +#define MCFSIM_SDTR (MCF_MBAR + 0x184) /* SDRAM Timing */ +#define MCFSIM_DCAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address */ +#define MCFSIM_DCMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask */ +#define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */ +#define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */ +#define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */ +#define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */ #define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */ #define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */ diff --git a/trunk/arch/m68k/platform/coldfire/m5272.c b/trunk/arch/m68k/platform/coldfire/m5272.c index a95680b7ed6e..eae59f67bc1c 100644 --- a/trunk/arch/m68k/platform/coldfire/m5272.c +++ b/trunk/arch/m68k/platform/coldfire/m5272.c @@ -62,11 +62,8 @@ static void m5272_cpu_reset(void) void __init config_BSP(char *commandp, int size) { #if defined (CONFIG_MOD5272) - volatile unsigned char *pivrp; - /* Set base of device vectors to be 64 */ - pivrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_PIVR); - *pivrp = 0x40; + writeb(0x40, MCFSIM_PIVR); #endif #if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)