From 1028bf85dd0c8bd9392692849482e2e2b0a32b41 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 2 Jul 2012 11:30:34 +0200 Subject: [PATCH] --- yaml --- r: 311679 b: refs/heads/master c: c520c921eacdced7e2095ba6cbbb9921906c7b67 h: refs/heads/master i: 311677: dd7d2eb875342a7dfd3f67b49170b09de92a372e 311675: 27c4bbc6a43275ccddb0873aa4edbda8b8ff8772 311671: a4828a6b13e3af4d5dbd37fa48662d12ba633846 311663: 1d6c950c3247df8e4e644cbf9718136607d0d04d 311647: 5fd51f3816b6616e3a3aff8a9824f04482536ae5 311615: bb74b3c2efebcf640b4b0a362d932dbd36b9bbbf 311551: 606cd78d0af42df0c3e8c08c4ad766e5b34ba698 v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-imx/clk-imx35.c | 9 ++++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index efaddced15b1..132c3394b526 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 396c89b327269c5a90bdd6152b5339e4cd2b8e73 +refs/heads/master: c520c921eacdced7e2095ba6cbbb9921906c7b67 diff --git a/trunk/arch/arm/mach-imx/clk-imx35.c b/trunk/arch/arm/mach-imx/clk-imx35.c index 920a8cc42726..c6422fb10bae 100644 --- a/trunk/arch/arm/mach-imx/clk-imx35.c +++ b/trunk/arch/arm/mach-imx/clk-imx35.c @@ -201,7 +201,6 @@ int __init mx35_clocks_init() pr_err("i.MX35 clk %d: register failed with %ld\n", i, PTR_ERR(clk[i])); - clk_register_clkdev(clk[pata_gate], NULL, "pata_imx"); clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0"); clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1"); @@ -264,6 +263,14 @@ int __init mx35_clocks_init() clk_prepare_enable(clk[iim_gate]); clk_prepare_enable(clk[emi_gate]); + /* + * SCC is needed to boot via mmc after a watchdog reset. The clock code + * before conversion to common clk also enabled UART1 (which isn't + * handled here and not needed for mmc) and IIM (which is enabled + * unconditionally above). + */ + clk_prepare_enable(clk[scc_gate]); + imx_print_silicon_rev("i.MX35", mx35_revision()); #ifdef CONFIG_MXC_USE_EPIT