From 107be1f76ae1ba3e4ba371f45e891ac9005f4155 Mon Sep 17 00:00:00 2001
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Wed, 8 Aug 2012 14:15:29 -0300
Subject: [PATCH] --- yaml --- r: 329273 b: refs/heads/master c:
 dfcef252e024b4ca6fe5be9e1d656ac1929ce894 h: refs/heads/master i:   329271:
 3fb326fc84299021ff9fa146a3019da72fbbb6b7 v: v3

---
 [refs]                                 |  2 +-
 trunk/drivers/gpu/drm/i915/i915_reg.h  |  1 +
 trunk/drivers/gpu/drm/i915/intel_ddi.c | 26 ++++++++++++++++++++------
 3 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/[refs] b/[refs]
index c7caf55cd14d..cf4a523fc3c9 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: f63eb7c4528060e54688baafb7a499e9391eefe6
+refs/heads/master: dfcef252e024b4ca6fe5be9e1d656ac1929ce894
diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h
index 896b27966bc4..f3fafb865365 100644
--- a/trunk/drivers/gpu/drm/i915/i915_reg.h
+++ b/trunk/drivers/gpu/drm/i915/i915_reg.h
@@ -4308,6 +4308,7 @@
 #define  PIPE_DDI_MODE_SELECT_DP_SST	(2<<24)
 #define  PIPE_DDI_MODE_SELECT_DP_MST	(3<<24)
 #define  PIPE_DDI_MODE_SELECT_FDI		(4<<24)
+#define  PIPE_DDI_BPC_MASK			(7<<20)
 #define  PIPE_DDI_BPC_8					(0<<20)
 #define  PIPE_DDI_BPC_10				(1<<20)
 #define  PIPE_DDI_BPC_6					(2<<20)
diff --git a/trunk/drivers/gpu/drm/i915/intel_ddi.c b/trunk/drivers/gpu/drm/i915/intel_ddi.c
index 1fbd67cd5586..8b383593b0d3 100644
--- a/trunk/drivers/gpu/drm/i915/intel_ddi.c
+++ b/trunk/drivers/gpu/drm/i915/intel_ddi.c
@@ -725,14 +725,28 @@ void intel_ddi_mode_set(struct drm_encoder *encoder,
 	/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 	temp = I915_READ(DDI_FUNC_CTL(pipe));
 	temp &= ~PIPE_DDI_PORT_MASK;
-	temp &= ~PIPE_DDI_BPC_12;
+	temp &= ~PIPE_DDI_BPC_MASK;
 	temp &= ~PIPE_DDI_MODE_SELECT_MASK;
 	temp &= ~(PIPE_DDI_PVSYNC | PIPE_DDI_PHSYNC);
-	temp |= PIPE_DDI_SELECT_PORT(port) |
-			((intel_crtc->bpp > 24) ?
-				PIPE_DDI_BPC_12 :
-				PIPE_DDI_BPC_8) |
-			PIPE_DDI_FUNC_ENABLE;
+	temp |= PIPE_DDI_FUNC_ENABLE | PIPE_DDI_SELECT_PORT(port);
+
+	switch (intel_crtc->bpp) {
+	case 18:
+		temp |= PIPE_DDI_BPC_6;
+		break;
+	case 24:
+		temp |= PIPE_DDI_BPC_8;
+		break;
+	case 30:
+		temp |= PIPE_DDI_BPC_10;
+		break;
+	case 36:
+		temp |= PIPE_DDI_BPC_12;
+		break;
+	default:
+		WARN(1, "%d bpp unsupported by pipe DDI function\n",
+		     intel_crtc->bpp);
+	}
 
 	if (intel_hdmi->has_hdmi_sink)
 		temp |= PIPE_DDI_MODE_SELECT_HDMI;